ADSP-2183KSTZ-133 [ADI]
IC 24-BIT, 16.67 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128, Digital Signal Processor;型号: | ADSP-2183KSTZ-133 |
厂家: | ADI |
描述: | IC 24-BIT, 16.67 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128, Digital Signal Processor 时钟 外围集成电路 |
文件: | 总31页 (文件大小:247K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
a
DSP Microcomputer
ADSP-2183
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time from 26.32 MHz Crystal
@ 3.3 Volts
52 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
POWERDOWN
PROGRAMMABLE
CONTROL
I/O
FLAGS
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
BYTE DMA
CONTROLLER
DAG 1 DAG 2
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
Multifunction Instructions
PROGRAM MEMORY DATA
DATA MEMORY DATA
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 300 Cycle Recovery from
Power-Down Condition
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
SERIAL PORTS
SPORT 0 SPORT 1
INTERNAL
DMA
PORT
TIMER
Low Power Dissipation in Idle Mode
ALU MAC SHIFTER
DMA
BUS
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
ADSP-2100 BASE
ARCHITECTURE
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead LQFP, 144-Ball Mini-BGA
GENERAL DESCRIPTION
The ADSP-2183 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2183 combines the ADSP-2100 family base architec-
ture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.
The ADSP-2183 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equipment.
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball
Mini-BGA packages.
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays
In addition, the ADSP-2183 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2183 operates with a 19 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2183’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2183 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
ICE-Port is a trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
ADSP-2183
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
ARCHITECTURE OVERVIEW
The ADSP-2183 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2183 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Development System
The ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2183. The assembler has an algebraic syntax
that is easy to program and debug. The linker combines object
files into an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment.
Figure 1 is an overall block diagram of the ADSP-2183. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The EZ-KIT Lite is a hardware/software kit offering a com-
plete development environment for the ADSP-21xx family:
an ADSP-2189M evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-2189M evaluation board is a low-cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite include the
following features:
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
• 35.7 MHz ADSP-2189M
• Full 16-bit Stereo Audio I/O with AD73322 CODEC
• RS-232 Interface
The ADSP-21xx family DSPs contain a shadow register that is
useful for single cycle context switching of the processor.
• EZ-ICE Connector for Emulator Control
• DSP Demo Programs
• Evaluation Suite of VisualDSP
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2183 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
The ADSP-218x EZ-ICE® Emulator aids in the hardware debug-
ging of ADSP-218x systems. The ADSP-218x integrates on-chip
emulation support with a 14-pin ICE-Port interface. This inter-
face provides a simpler target board connection requiring fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-218x device need not be removed
from the target system when using the EZ-ICE, nor are any
adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
(See Designing An EZ-ICE-Compatible Target System section
of this data sheet for exact specifications of the EZ-ICE target
board connector.)
Additional Information
This data sheet provides a general overview of ADSP-2183
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.
Program memory can store both instructions and data, permit-
ting the ADSP-2183 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2183 can fetch an operand from program memory and
the next instruction in the same cycle.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
–2–
REV. C
ADSP-2183
In addition to the address and data bus for external memory
connection, the ADSP-2183 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
The ADSP-2183 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2183 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
Serial Ports
The ADSP-2183 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2183
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.
The ADSP-2183 can respond to thirteen possible interrupts,
eleven of which are accessible at any given time. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals, internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
21xx CORE
ADSP-2183 INTEGRATION
2
POWER
DOWN
CONTROL
LOGIC
PROGRAM
SRAM
DATA
SRAM
16k
؋
16 INSTRUCTION
REGISTER
8
16k
؋
24 PROGRAMMABLE
I/O
BYTE
DMA
CONTROLLER
DATA
ADDRESS
GENERATOR
#2
DATA
ADDRESS
GENERATOR
#1
3
PROGRAM
FLAGS
SEQUENCER
PMA BUS
DMA BUS
14
14
PMA BUS
14
MUX
DMA BUS
EXTERNAL
ADDRESS
BUS
PMD BUS
24
PMD BUS
EXTERNAL
DATA
BUS
BUS
MUX
EXCHANGE
DMD
BUS
DMD BUS
24
16
IN
P
U
T
R
E
G
S
INPUT REGS
SHIFTER
INPUT REGS
COMPANDING
CIRCUITRY
16
INTERNAL
DMA
PORT
ALU
MAC
TIMER
TRANSMIT REG
TRANSMIT REG
OUTPUT REGS
OUTPUT REGS
OUTPUT REGS
RECEIVE REG
RECEIVE REG
4
SERIAL
PORT 0
SERIAL
PORT 0
16
INTERRUPTS
R BUS
5
5
Figure 1. Block Diagram
–3–
REV. C
ADSP-2183
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
#
of
Pins
Pin
Name(s)
Input/
Output Function
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
CLKOUT
SPORT0
SPORT1
1
5
5
O
I/O
I/O
Processor Clock Output.
Serial Port I/O Pins
Serial Port 1 or Two External
IRQs, Flag In and Flag Out
IDMA Port Read/Write Inputs
IDMA Port Select
IDMA Port Address Latch
Enable
IDMA Port Address/Data Bus
IDMA Port Access Ready
Acknowledge
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
IRD, IWR
IS
2
1
1
I
I
I
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
IAL
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
IAD
IACK
16
1
I/O
O
PWD
1
1
I
O
Power-Down Control
Power-Down Control
Pin Descriptions
The ADSP-2183 is available in a 128-lead LQFP package, and
Mini-BGA.
PWDACK
FL0, FL1,
FL2
PF7:0
EE
EBR
3
8
1
1
1
1
1
1
1
1
1
11
6
O
I/O
*
*
*
*
*
*
*
Output Flags
Programmable I/O Pins
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
(Emulator Only*)
Ground Pins (LQFP)
Power Supply Pins (LQFP)
Ground Pins (Mini-BGA)
Power Supply Pins (Mini-BGA)
PIN FUNCTION DESCRIPTIONS
#
of
Pin
Input/
Output Function
Name(s)
Pins
EBG
Address
14
O
Address Output Pins for Program,
Data, Byte, & I/O Spaces
Data I/O Pins for Program and
Data Memory Spaces (8 MSBs
Are Also Used as Byte Space
Addresses)
Processor Reset Input
Edge- or Level-Sensitive
Interrupt Request
ERESET
EMS
Data
24
I/O
EINT
ECLK
ELIN
ELOUT
GND
VDD
GND
VDD
*
*
RESET
IRQ2
1
1
I
I
IRQL0,
IRQL1
22
11
2
1
I
I
Level-Sensitive Interrupt
Requests
Edge-Sensitive Interrupt
Request
*These ADSP-2183 pins must be connected only to the EZ-ICE connector in
the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
IRQE
BR
1
1
1
1
1
1
1
1
1
1
1
1
I
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Interrupts
BG
O
O
O
O
O
O
O
O
O
I
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2183 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2183 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power-down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
BGH
PMS
DMS
BMS
IOMS
CMS
RD
Program Memory Select Output
Data Memory Select Output
Byte Memory Select Output
I/O Space Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Memory Map Select Input
Boot Option Control Input
WR
MMAP
BMODE
CLKIN,
XTAL
I
2
I
Clock or Quartz Crystal Input
–4–
REV. C
ADSP-2183
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Power-Down
The ADSP-2183 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. Refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter for detailed
information about the power-down feature.
Source of Interrupt
Address (Hex)
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
002C
0004
IRQL1
IRQL0
0008
000C
0010
0014
0018
001C
0020
0024
• Quick recovery from power-down. The processor begins
executing instructions in as few as 300 CLKIN cycles.
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 300 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 300 CLKIN
cycle start-up.
0028 (Lowest Priority)
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
The ADSP-2183 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
• Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
• The RESET pin also can be used to terminate
power-down.
• Power-down acknowledge pin indicates when the
processor has entered power-down.
The IFC register is a write-only register used to force and clear
interrupts.
Idle
When the ADSP-2183 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2183 to
let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency,
a programmable fraction of the normal clock rate, is speci-
fied by a selectable divisor given in the IDLE instruction.
The format of the instruction is
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
IDLE (n);
The ADSP-2183 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. C
–5–
ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock, and thus its response time, to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2183 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2183 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
When the IDLE (n) instruction is used in systems with an exter-
nally generated serial clock (SCLK), the serial clock rate may be
faster than the processor’s reduced internal clock rate. Under
these conditions, interrupts must not be generated at a faster
rate than can be serviced, due to the additional time the processor
takes to come out of the idle state (a maximum of n processor
cycles).
Because the ADSP-2183 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2183, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2183 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
ADSP-2183
XTAL
CLKIN
DSP
CLKOUT
1/2x CLOCK
OR
CLKIN
XTAL
A
14
13-0
ADDR13-0
CRYSTAL
A0-A21
D
23-16
FL0-2
PF0-7
BYTE
D
15-8
24
MEMORY
DATA23-0
DATA
IRQ2
BMS
CS
IRQE
IRQL0
IRQL1
Figure 3. External Crystal Connections
A
D
10-0
ADDR
DATA
Reset
23-8
RD
WR
I/O
SPACE
SPORT1
The RESET signal initiates a master reset of the ADSP-2183.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
SCLK1
RFS1 OR IRQ0
(PERIPHERALS)
SERIAL
DEVICE
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
IOMS
CS
2048 LOCATIONS
A
13-0
SPORT0
SCLK0
RFS0
ADDR
DATA
OVERLAY
MEMORY
D
23-0
SERIAL
DEVICE
TFS0
TWO 8K
PMS
DMS
CMS
DT0
PM SEGMENTS
DR0
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
TWO 8K
IDMA PORT
DM SEGMENTS
BR
BG
BGH
IRD
IWR
IS
IAL
IACK
SYSTEM
INTERFACE
OR
PWD
CONTROLLER
16
PWDACK
IAD15-0
Figure 2. ADSP-2183 Basic System Configuration
Clock Signals
mum pulsewidth specification, tRSP
.
The ADSP-2183 can be clocked by either a crystal or a TTL-
compatible clock signal.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
–6–
REV. C
ADSP-2183
Table II.
PMOVLAY Memory A13
Memory Architecture
The ADSP-2183 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O.
A12:0
0
1
Internal
Not Applicable Not Applicable
Program Memory is a 24-bit-wide space for storing both
instruction opcodes and data. The ADSP-2183 has 16K words
of Program Memory RAM on chip and the capability of access-
ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.
External
Overlay 1
0
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
2
External
13 LSBs of Address
Between 0x2000
and 0x3FFF
Overlay 2
Data Memory is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. The
ADSP-2183 has 16K words on Data Memory RAM on chip,
consisting of 16,352 user-accessible locations and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus.
This organization provides for two external 8K overlay segments
using only the normal 14 address bits. This allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space because the processor core (i.e., the sequencer)
does not take the PMOVLAY register value into account. For
example, if a loop operation were occurring on one of the exter-
nal overlays, and the program changes to another external over-
lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.
Byte Memory provides access to an 8-bit-wide memory space
through the Byte DMA (BDMA) port. The Byte Memory inter-
face provides access to 4 MBytes of memory by utilizing eight
data lines as additional address lines. This gives the BDMA Port
an effective 22-bit address range. On power-up, the DSP can
automatically load bootstrap code from byte memory.
I/O Space allows access to 2048 locations of 16-bit-wide data.
It is intended to be used to communicate with parallel periph-
eral devices such as data converters and external registers or
latches.
For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
In this mode, booting is disabled and overlay memory is dis-
abled (PMOVLAY must be 0). Figure 5 shows the memory map
in this configuration.
Program Memory
The ADSP-2183 contains a 16K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2183 allows the use of 8K
external memory overlays.
PROGRAM MEMORY
ADDRESS
0x3FFF
INTERNAL 8K
(PMOVLAY = 0,
MMAP = 1)
0x2000
0x1FFF
The program memory space organization is controlled by the
MMAP pin and the PMOVLAY register. Normally, the ADSP-
2183 is configured with MMAP = 0 and program memory orga-
nized as shown in Figure 4.
8K EXTERNAL
0x0000
PROGRAM MEMORY
ADDRESS
0x3FFF
Figure 5. Program Memory (MMAP = 1)
Data Memory
The ADSP-2183 has 16,352 16-bit words of internal data
memory. In addition, the ADSP-2183 allows the use of 8K
external memory overlays. Figure 6 shows the organization of
the data memory.
8K INTERNAL
(PMOVLAY = 0,
MMAP = 0)
OR
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MMAP = 0)
0x2000
0x1FFF
DATA MEMORY
ADDRESS
8K INTERNAL
0x3FFF
32 MEMORY–
MAPPED REGISTERS
0x0000
0x3FEO
0x3FDF
Figure 4. Program Memory (MMAP = 0)
INTERNAL
8160 WORDS
There are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to
something other than 0, external accesses occur at addresses
0x2000 through 0x3FFF. The external address is generated as
shown in Table II.
0x2000
0x1FFF
8K INTERNAL
(DMOVLAY = 0)
OR
EXTERNAL 8K
(DMOVLAY = 1, 2)
0x0000
Figure 6. Data Memory
REV. C
–7–
ADSP-2183
There are 16,352 words of memory accessible internally when
the DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
Byte Memory
Table III.
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.
DMOVLAY Memory A13
A12:0
0
1
Internal
Not Applicable Not Applicable
External
Overlay 1
0
1
13 LSBs of Address
Between 0x0000
and 0x1FFF
The byte memory space on the ADSP-2183 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
2
External
13 LSBs of Address
Between 0x0000
and 0x1FFF
Overlay 2
Byte Memory DMA (BDMA)
This organization allows for two external 8K overlays using only
the normal 14 address bits.
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space,
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.
I/O Space
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.
The ADSP-2183 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper 3 bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space.
The I/O space also has four dedicated 3-bit wait state regis-
ters, IOWAIT0-3, which specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table IV.
Table V.
Internal
Memory Space
BTYPE
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
Full Word
Full Word
MSBs
Table IV.
8
LSBs
Address Range
Wait State Register
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Composite Memory Select (CMS)
The ADSP-2183 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
When set, each bit in the CMSSEL register causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory; use either DMS or PMS as the additional
address bit.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
MMAP, PMOVLAY or DMOVLAY.
–8–
REV. C
ADSP-2183
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
a destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
Table VI. Boot Summary Table
MMAP BMODE
Booting Method
0
0
BDMA feature is used in default mode
to load the first 32 program memory
words from the byte memory space.
Program execution is held off until all
32 words have been loaded.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
0
1
1
IDMA feature is used to load any inter-
nal memory as desired. Program execu-
tion is held off until internal program
memory location 0 is written to.
X
Bootstrap features disabled. Program
execution immediately starts from
location 0.
Internal Memory DMA Port (IDMA Port)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2183. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
BDMA Booting
When the BMODE and MMAP pins specify BDMA booting
(MMAP = 0, BMODE = 0), the ADSP-2183 initiates a BDMA
boot sequence when reset is released. The BDMA interface is
set up during reset to the following defaults when BDMA boot-
ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis-
ters are set to 0, the BTYPE register is set to 0 to specify
program memory 24 bit words, and the BWCOUNT register is
set to 32. This causes 32 words of on-chip program memory to
be loaded from byte memory. These 32 words are used to set up
the BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be held
off until all 32 words are loaded into on-chip program memory.
Execution then begins at address 0.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2183 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-
bit address and 1-bit destination type can be driven onto the bus
by an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface.
IDMA Booting
The ADSP-2183 can also boot programs through its Internal
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2183
boots from the IDMA port. IDMA feature can load as much on-
chip memory as desired. Program execution is held off until on-
chip program memory location 0 is written to.
Once the address is stored, data can either be read from or
written to the ADSP-2183’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2183 that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
The ADSP-2100 Family Development Software (Revision 5.02
and later) can generate IDMA compatible boot code.
Bus Request and Bus Grant
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
The ADSP-2183 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2183 is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Bootstrap Loading (Booting)
The ADSP-2183 has two mechanisms to allow automatic load-
ing of the on-chip program memory after reset. The method for
booting after reset is controlled by the MMAP and BMODE
pins as shown in Table VI.
• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• asserting the bus grant (BG) signal, and
• halting program execution.
REV. C
–9–
ADSP-2183
If Go Mode is enabled, the ADSP-2183 will not halt program
execution until it encounters an instruction that requires an
external memory access.
• The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2183’s interrupt vector and reset vector map.
If the ADSP-2183 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The ADSP-2183 has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
The BGH pin is asserted when the ADSP-2183 is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re-
lease the bus by deasserting bus request. Once the bus is re-
leased, the ADSP-2183 deasserts BG and BGH and executes
the external memory access.
The ICE-Port interface consists of the following ADSP-2183 pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
Flag I/O Pins
The ADSP-2183 has eight general purpose programmable in-
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2183’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
These ADSP-2183 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2183 and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:
In addition to the programmable flags, the ADSP-2183 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2.
FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.
BR
BG
RESET
GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2183 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
INSTRUCTION SET DESCRIPTION
The ADSP-2183 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
–10–
REV. C
ADSP-2183
Restriction: All memory strobe signals on the ADSP-2183
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected
when the EZ-ICE is being used. The pull-up resistors are nec-
essary because there are no internal pull-ups to guarantee their
state during prolonged three-state conditions resulting from
typical EZ-ICE debugging sessions. These resistors may be
removed at your option when the EZ-ICE is not being used.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
3
2
4
GND
BG
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced
by the EZ-ICE board:
EBG
BR
5
6
EBR
EINT
ELIN
ECLK
7
8
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
KEY (NO PIN)
9
10
12
14
ELOUT
EE
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
11
13
EMS
• EZ-ICE emulation ignores RESET and BR when single-
stepping.
ERESET
RESET
TOP VIEW
• EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).
Figure 7. Target Board Connector for EZ-ICE
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie, and Samtec.
Target Architecture File
The EZ-ICE software lets you load your program in its linked
(executable) form. The EZ-ICE PC program can not load
sections of your executable located in boot pages (by the
linker). With the exception of boot page 0 (loaded into PM
RAM), all sections of your executable mapped into boot pages
are not loaded.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines
listed below.
Write your target architecture file to indicate that only PM
RAM is available for program storage, when using the EZ-ICE
software’s loading feature. Data can be loaded to PM RAM or
DM RAM.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
REV. C
–11–
ADSP-2183–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
3.0
0
3.6
+70
3.0
–40
3.6
+85
V
°C
ELECTRICAL CHARACTERISTICS
K/B Grades
Typ
Parameter
Test Conditions
Min
Max
Unit
VIH
VIL
VOH
Hi-Level Input Voltage1, 2
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
@ VDD = max
@ VDD = min
@ VDD = min
2.0
V
V
0.4
I
OH = –0.5 mA
2.4
V
@ VDD = min
I
OH = –100 µA6
VDD – 0.3
V
VOL
IIH
Lo-Level Output Voltage1, 4, 5
Hi-Level Input Current3
@ VDD = min
IOL = 2 mA
@ VDD = max
0.4
10
10
10
8
V
V
IN = VDD max
@ VDD = max
IN = 0 V
µA
µA
µA
µA
IIL
Lo-Level Input Current3
V
IOZH
IOZL
IDD
Three-State Leakage Current7
Three-State Leakage Current7
Supply Current (Idle)9, 10
@ VDD = max
VIN = VDD max8
@ VDD = max
V
IN = 0 V8
@ VDD = 3.3
AMB = +25°C
CK = 19 ns11
T
t
10
9
8
mA
mA
mA
mA
tCK = 25 ns11
t
t
CK = 30 ns11
CK = 34.7 ns11
6
IDD
Supply Current (Dynamic)10, 12
@ VDD = 3.3
AMB = +25°C
CK = 19 ns11
T
t
44
35
30
26
mA
mA
mA
mA
tCK = 25 ns11
t
t
CK = 30 ns11
CK = 34.7 ns11
CI
Input Pin Capacitance3, 6, 13
@ VIN = 2.5 V
IN = 1.0 MHz
f
TAMB = +25°C
8
8
pF
pF
CO
Output Pin Capacitance6, 7, 13, 14
@ VIN = 2.5 V
f
IN = 1.0 MHz
TAMB = +25°C
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.
12Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
13Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
14Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.
15Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
16Guaranteed but not tested.
17Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7.
180 V on BR, CLKIN Active (to force three-state condition).
19Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10Current reflects device operating with no output loads.
11
V
I
= 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are
IN
12
DD
1type 2 and type 6, and 20% are idle instructions.
13Applies to LQFP package type and Mini-BGA.
14Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. C
–12–
ADSP-2183
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING PARAMETERS
GENERAL NOTES
MEMORY TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
The table below shows common memory device specifications
and the corresponding ADSP-2183 timing parameters, for your
convenience.
Memory
Device
ADSP-2183 Timing
Timing
Parameter
Specification
Parameter Definition
TIMING NOTES
Address Setup to
Write Start
Address Setup to
Write End
tASW
A0–A13, xMS Setup before
WR Low
A0–A13, xMS Setup before
WR Deasserted
A0–A13, xMS Hold after
WR Deasserted
Data Setup before WR
High
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
tAW
Address Hold Time tWRA
Data Setup Time
tDW
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Data Hold Time
OE to Data Valid
Address Access Time tAA
tDH
tRDD
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing pa-
rameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (34.7 ns) – 7 ns = 10.35 ns
REV. C
–13–
ADSP-2183
Parameter
Min
Max
Unit
Clock Signals and Reset
Timing Requirements:
tCKI
CLKIN Period
CLKIN Width Low
CLKIN Width High
38
15
15
100
ns
ns
ns
tCKIL
tCKIH
Switching Characteristics:
tCKL
CLKOUT Width Low
0.5tCK – 7
0.5tCK – 7
0
ns
ns
ns
tCKH
tCKOH
CLKOUT Width High
CLKIN High to CLKOUT High
20
Control Signals
Timing Requirement:
1
tRSP
RESET Width Low
5tCK
ns
NOTE
1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 8. Clock Signals
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
tIFS
tIFH
IRQx, FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High 1, 2, 3, 4
0.25tCK + 15
0.25tCK
ns
ns
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
0.5tCK – 7
ns
ns
0.5tCK + 6
NOTES
1If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 9. Interrupts and Flags
–14–
REV. C
ADSP-2183
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
tBS
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
0.25tCK + 2
0.25tCK + 17
ns
ns
Switching Characteristics:
tSD
CLKOUT High to xMS,
0.25tCK + 10
ns
RD, WR Disable
xMS, RD, WR
Disable to BG Low
BG High to xMS,
RD, WR Enable
tSDB
tSE
0
ns
ns
ns
ns
ns
0
tSEC
tSDBH
tSEH
xMS, RD, WR
Enable to CLKOUT High
xMS, RD, WR
0.25tCK – 4
Disable to BGH Low2
BGH High to xMS,
RD, WR Enable2
0
0
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
tSEC
WR
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 10. Bus Request–Bus Grant
REV. C
–15–
ADSP-2183
Parameter
Min
Max
Unit
Memory Read
Timing Requirements:
tRDD
tAA
RD Low to Data Valid
A0–A13, xMS to Data Valid
Data Hold from RD High
0.5tCK – 8 + w
0.75tCK – 10.5 + w
ns
ns
ns
tRDH
0
Switching Characteristics:
tRP
RD Pulsewidth
0.5tCK – 5 + w
0.25tCK – 2
0.25tCK – 4
0.25tCK – 3
0.5tCK – 5
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
CLKOUT High to RD Low
0.25tCK + 7
A0–A13, xMS Setup before RD Low
A0–A13, xMS Hold after RD Deasserted
RD High to RD or WR Low
w = wait states × tCK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 – A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tCRD
tRP
tRWR
D
tRDD
tRDH
tAA
WR
Figure 11. Memory Read
–16–
REV. C
ADSP-2183
Parameter
Min
Max
Unit
Memory Write
Switching Characteristics:
tDW
tDH
Data Setup before WR High
Data Hold after WR High
0.5tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 4
0.25tCK – 4
0.25tCK – 2
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWP
WR Pulsewidth
tWDE
tASW
tDDR
tCWR
tAW
tWRA
tWWR
WR Low to Data Enabled
A0–A13, xMS Setup before WR Low
Data Disable before WR or RD Low
CLKOUT High to WR Low
A0–A13, xMS, Setup before WR Deasserted
A0–A13, xMS Hold after WR Deasserted
WR High to RD or WR Low
0.25 tCK + 7
w = wait states × tCK
.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tWWR
tASW
tWP
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
RD
Figure 12. Memory Write
REV. C
–17–
ADSP-2183
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
38
4
7
ns
ns
ns
ns
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
15
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
SCLK High to DT Enable
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
0.25tCK
0
0.25tCK + 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
15
15
0
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
0
0
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
14
15
15
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
tCC
tSCK
SCLK
tSCP
tSCP
tSCS tSCH
DR
TFS
RFS
IN
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
ALTERNATE
FRAME MODE
tRDV
RFS
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 13. Serial Ports
–18–
REV. C
ADSP-2183
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
tIALP
tIASU
tIAH
Duration of Address Latch1, 2
10
5
2
0
3
ns
ns
ns
ns
ns
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
IACK Low before Start of Address Latch1
tIKA
tIALS
Start of Write or Read after Address Latch End2, 3
NOTES
1Start of Address Latch = IS Low and IAL High.
2End of Address Latch = IS High or IAL Low.
3Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
IAL
tIALP
IS
tIASU
tIAH
IAD15–0
tIALS
IRD OR
IWR
Figure 14. IDMA Address Latch
REV. C
–19–
ADSP-2183
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
tIWP
tIDSU
tIDH
IACK Low before Start of Write1
0
15
5
ns
ns
ns
ns
Duration of Write1, 2
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
2
Switching Characteristic:
tIKHW
Start of Write to IACK High
15
ns
NOTES
1Start of Write = IS Low and IWR Low.
2End of Write = IS High or IWR High.
3If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
4If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
tIKW
IACK
IS
tIKHW
tIWP
IWR
tIDH
tIDSU
DATA
IAD15–0
Figure 15. IDMA Write, Short Write Cycle
–20–
REV. C
ADSP-2183
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
tIKSU
tIKH
IACK Low before Start of Write1
0
ns
ns
ns
IAD15–0 Data Setup before IACK Low2, 3
IAD15–0 Data Hold after IACK Low2, 3
0.5tCK + 10
2
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW Start of Write to IACK High
1.5tCK
ns
ns
15
NOTES
1Start of Write = IS Low and IWR Low.
2If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
3If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
4This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User’s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 16. IDMA Write, Long Write Cycle
REV. C
–21–
ADSP-2183
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read1
0
15
ns
ns
Duration of Read
Switching Characteristics:
tIKHR
tIKDS
tIKDH
tIKDD
tIRDE
tIRDV
tIRDH1
tIRDH2
IACK High after Start of Read1
15
ns
ns
ns
ns
ns
ns
ns
ns
IAD15–0 Data Setup before IACK Low
0.5tCK – 7
0
IAD15–0 Data Hold after End of Read2
IAD15–0 Data Disabled after End of Read2
10
15
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
IAD15–0 Previous Data Hold after Start of Read (PM2)4
0
2tCK – 5
tCK – 5
NOTES
1Start of Read = IS Low and IRD Low.
2End of Read = IS High or IRD High.
3DM read or first half of PM read.
4Second half of PM read.
IACK
IS
tIKHR
tIKR
tIRP
IRD
tIKDS
tIKDH
tIRDE
PREVIOUS
DATA
READ
DATA
IAD15–0
tIRDV
tIKDD
tIRDH
Figure 17. IDMA Read, Long Read Cycle
–22–
REV. C
ADSP-2183
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR
tIRP
IACK Low before Start of Read1
0
15
ns
ns
Duration of Read
Switching Characteristics:
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read1
15
10
15
ns
ns
ns
ns
ns
IAD15–0 Data Hold after End of Read2
0
0
IAD15–0 Data Disabled after End of Read2
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
NOTES
1Start of Read = IS Low and IRD Low.
2End of Read = IS High or IRD High.
IACK
IS
tIKR
tIKHR
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tIKDD
tIRDV
Figure 18. IDMA Read, Short Read Cycle
REV. C
–23–
ADSP-2183
OUTPUT DRIVE CURRENTS
PINT = internal power dissipation from Power vs. Frequency
Figure 19 shows typical I-V characteristics for the output drivers
of the ADSP-2183. The curves represent the current drive
capability of the output drivers as a function of output voltage.
graph (Figure 20).
(C × VDD2 × f ) is calculated for each output:
100
75
# of
Pins × C
2
× VDD
× f
50
Address, DMS
Data Output, WR
RD
8
9
1
1
× 10 pF × 3.32
V
× 33.3 MHz
=
29.0 mW
× 10 pF × 3.32 V × 16.67 MHz = 16.3 mW
25
3.6V, –40°C
× 10 pF × 3.32
× 10 pF × 3.32 V × 33.3 MHz
V
× 16.67 MHz =
1.8 mW
3.6 mW
50.7 mW
0
3.3V, +25°C
CLKOUT
=
3.0V, +85°C
–25
–50
3.0V, +85°C
–75
Total power dissipation for this example is PINT + 50.7 mW.
3.3V, +25
°
C
–100
–125
3.6V, –40°C
1, 3, 4
2183 POWER, INTERNAL
220
205
–150
–175
–200
190
184mW
175
0
0.75
1.50
2.25
3.00
3.75
4.50
5.25
V
= 3.6V
SOURCE VOLTAGE – V
160
145
130
DD
150mW
120mW
Figure 19. Typical Drive Currents
V
V
= 3.3V
= 3.0V
DD
1000
100
10
110mW
90mW
115
100
DD
V
V
V
= 3.6V
= 3.3V
= 3.0V
DD
DD
DD
85 72mW
70
28
32
36
40
CK
44
48
52
1/t – MHz
1, 2, 3
POWER, IDLE
50
45
40
35
38mW
V
V
= 3.6V
= 3.3V
DD
30mW
24mW
30 27mW
DD
25
20mW
0
0
25
55
85
20
TEMPERATURE – °C
V
= 3.0V
DD
15
NOTES:
1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE.
15mW
10
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.
5
0
28
36
40
CK
44
48
32
52
1/t – MHz
Figure 20. Power-Down Supply Current (Typical)
3
POWER, IDLE n MODES
32
30
POWER DISSIPATION
30mW
IDLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
28
26
2
C × VDD × f
24
22
C = load capacitance, f = output switching frequency.
20
18
20mW
Example:
16
14
12
10
8
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as
follows:
13.8mW
13mW
IDLE (16)
IDLE (128)
11mW
10.6mW
Assumptions:
28
32
36
40
CK
44
48
52
1/t – MHz
•
•
External data memory is accessed every cycle with 50% of the
address pins switching.
VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.
External data memory writes occur every other cycle with
50% of the data pins switching.
DD
3
4
TYPICAL POWER DISSIPATION AT 3.3V V AND 25؇C EXCEPT WHERE SPECIFIED.
DD
I
MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
DD
•
•
Each address and data pin has a 10 pF total load at the pin.
The application operates at VDD = 3.3 V and tCK = 30.0 ns.
2
Total Power Dissipation = PINT + (C × VDD × f )
Figure 21. Power vs. Frequency
REV. C
–24–
ADSP-2183
CAPACITIVE LOADING
Figures 22 and 23 show the capacitive loading characteristics of
the ADSP-2183.
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
25
T = +85؇C
DD
INPUT
1.5V
1.5V
OR
V
= 3.0V
OUTPUT
20
15
10
5
Figure 24. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
0
0
20
40
60
80 100 120 140 160 180 200
– pF
C
L
Figure 22. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
REFERENCE
SIGNAL
tMEASURED
tDIS
18
16
tENA
V
V
OH
OH
(MEASURED)
(MEASURED)
14
12
10
8
V
V
(MEASURED) – 0.5V
2.0V
1.0V
OH
OL
OUTPUT
(MEASURED) +0.5V
V
V
OL
OL
tDECAY
(MEASURED)
(MEASURED)
6
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
4
2
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
NOMINAL
–2
–4
–6
Figure 25. Output Enable/Disable
I
OL
0
40
80
120
– pF
160
200
C
L
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TO
OUTPUT
PIN
+1.5V
50pF
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
I
OH
Figure 26. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)
,
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
T
AMB = TCASE – (PD × θCA
)
CASE = Case Temperature in °C
PD = Power Dissipation in W
θ
θ
θ
CA = Thermal Resistance (Case-to-Ambient)
JA = Thermal Resistance (Junction-to-Ambient)
JC = Thermal Resistance (Junction-to-Case)
CL • 0.5V
tDECAY
=
iL
from which
Package
JA
JC
CA
tDIS = tMEASURED – tDECAY
LQFP
Mini-BGA
50°C/W
70.7°C/W
2°C/W
7.4°C/W
48°C/W
63.3°C/W
REV. C
–25–
ADSP-2183
128-Lead LQFP Package Pinout
102
101
100
99
IAL
PF3
PF2
PF1
PF0
WR
1
2
GND
D23
D22
D21
D20
PIN 1
IDENTIFIER
3
4
5
98
6
97 D19
96
7
D18
RD
95
8
D17
IOMS
BMS
DMS
CMS
94
9
D16
93
10
11
D15
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
GND
GND 12
V
DD
13
14
15
V
GND
D14
D13
D12
D11
D10
D9
DD
PMS
A0
A1 16
A2 17
18
A3
A4 19
20
ADSP-2183
TOP VIEW
(Not to Scale)
A5
A6 21
D8
D7
22
23
24
25
A7
XTAL
CLKIN
GND
D6
D5
GND
D4
CLKOUT 26
D3
27
28
29
30
GND
D2
V
D1
DD
D0
A8
A9
V
DD
A10 31
32
BG
A11
EBG
BR
A12 33
A13 34
EBR
EINT
35
IRQE
67 ELIN
MMAP 36
66
65
37
38
ELOUT
ECLK
PWD
IRQ2
–26–
REV. C
ADSP-2183
LQFP Pin Configurations
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
IAL
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A12
A13
IRQE
MMAP
PWD
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
ECLK
ELOUT
ELIN
EINT
EBR
BR
EBG
BG
VDD
D0
D1
D2
D3
D4
97
98
99
D19
D20
D21
D22
D23
GND
IWR
PF3
PF2
PF1
PF0
WR
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
IRQ2
RD
BMODE
PWDACK
IACK
BGH
VDD
GND
IRQL0
IRQL1
FL0
FL1
FL2
DT0
TFS0
RFS0
DR0
SCLK0
DT1/F0
TFS1/IRQ1
RFS1/IRQ0
GND
DR1/FI
SCLK1
ERESET
RESET
EMS
IOMS
BMS
DMS
CMS
GND
VDD
PMS
A0
A1
A2
A3
A4
A5
A6
A7
XTAL
CLKIN
GND
CLKOUT
GND
VDD
A8
IRD
9
IAD15
IAD14
IAD13
IAD12
IAD11
IAD10
IAD9
IAD8
IAD7
IAD6
VDD
GND
IAD5
IAD4
IAD3
IAD2
IAD1
IAD0
PF7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
GND
VDD
GND
D15
D16
D17
D18
PF6
PF5
PF4
GND
IS
A9
A10
A11
EE
REV. C
–27–
ADSP-2183
144-Lead Mini-BGA Package Pinout
(Bottom View)
12
11
10
9
8
7
6
5
4
2
1
3
GND
D21
D17
GND
IWR
IAD14
IAD10
IAD6
GND
IAD2
PF6
GND
IS
IAL
A
D23
D20
IRD
IAD15
IAD13
IAD11
IAD8
VDD
VDD
GND
IAD0
IAD1
PF4
PF5
PF2
GND
WR
GND
A0
PF3
PF0
PF1
RD
B
C
D22
GND
D14
D10
D15
GND
D11
D18
VDD
D13
D19
GND
D12
D16
GND
IAD9
IAD7
D8
IAD5
CMS
IAD4
PF7
IAD3
PMS
A8
IOMS
BMS
A3
DMS
VDD
A1
GND
VDD
A2
D
E
IAD12
A4
F
D6
D5
D2
D9
GND
D1
D4
D0
D7
D3
DT0
DT1
A7
A6
GND
GND
GND
A10
A5
XTAL
CLKIN
CLKOUT
A9
G
H
GND
VDD
EBG
IRQL0
IRQL1
TFS0
VDD
VDD
FL2
GND
VDD
A12
J
VDD
BR
BG
RFS1
SCLK1
SCLK0
TFS1
VDD
EBR
ERESET
PWDACK
A11
K
L
EINT
ELOUT
EE
ELIN
RESET
GND
GND
DR0
FL0
FL1
GND
GND
IACK
BGH
IRQE
MMAP
A13
M
ECLK
EMS
DR1
RFS0
BMODE
IRQ2
PWD
–28–
REV. C
ADSP-2183
Mini-BGA Pin Configurations
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
IAL
IS
GND
PF6
IAD2
GND
IAD6
IAD10
IAD14
IWR
GND
GND
PF1
PF3
GND
PF5
IAD1
GND
VDD
IAD11
IAD15
IRD
D23
D21
RD
PF0
WR
PF2
PF4
IAD0
VDD
IAD8
IAD13
D22
D20
D17
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
E01
E02
E03
E04
E05
E06
E07
E08
E09
E10
E11
E12
F01
F02
F03
F04
F05
F06
F07
F08
F09
F10
F11
F12
GND
DMS
GND
IOMS
PF7
IAD5
IAD9
D16
D19
D18
D15
GND
VDD
VDD
A0
BMS
IAD3
CMS
IAD7
GND
GND
VDD
GND
D14
A2
G01
G02
G03
G04
G05
G06
G07
G08
G09
G10
G11
G12
H01
H02
H03
H04
H05
H06
H07
H08
H09
H10
H11
H12
J01
XTAL
A5
GND
A6
A8
A7
DT0
D7
D4
D9
K01
K02
K03
K04
K05
K06
K07
K08
K09
K10
K11
K12
L01
L02
L03
L04
L05
L06
L07
L08
L09
L10
L11
L12
M01
M02
M03
M04
M05
M06
M07
M08
M09
M10
M11
M12
A9
A12
A11
PWDACK
FL2
TFS0
TFS1
SCLK1
ERESET
EBR
BR
EBG
D5
D6
CLKIN
GND
GND
GND
VDD
IRQL0
DT1
D3
A13
MMAP
IRQE
IACK
GND
FL0
DR0
GND
RESET
ELIN
ELOUT
EINT
PWD
IRQ2
BMODE
BGH
GND
FL1
RFS0
GND
DR1
EMS
EE
D0
GND
D2
GND
CLKOUT
VDD
A10
VDD
VDD
IRQL1
SCLK0
RFS1
BG
A1
A4
A3
J02
J03
J04
J05
J06
J07
J08
J09
PMS
IAD4
D8
IAD12
D12
D13
D11
D10
J10
J11
J12
D1
VDD
VDD
ECLK
REV. C
–29–
ADSP-2183
OUTLINE DIMENSIONS
Dimensions given in mm and (inches).
128-Lead Metric Plastic Thin Quad Flatpack (LQFP)
(ST-128)
16.20 (0.638)
16.00 (0.630)
15.80 (0.622)
1.60 (0.063)
MAX
0.75 (0.030)
0.60 (0.024)
0.50 (0.020)
128
1
103
102
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.08 (0.003)
MAX LEAD
COPLANARITY
38
39
65
64
0.15 (0.006)
0.05 (0.002)
0.27 (0.011)
0.22 (0.009)
0.50 (0.020)
BSC
LEAD PITCH
0.17 (0.007)
LEAD WIDTH
1.45 (0.057)
1.40 (0.055)
1.35 (0.053)
14.10 (0.555)
14.00 (0.551)
13.90 (0.547)
NOTES:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08
(0.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
–30–
REV. C
ADSP-2183
OUTLINE DIMENSIONS
Dimensions given in mm and (inches).
144-Lead Mini-BGA Package Pinout
(CA-144)
0.404 (10.25)
0.394 (10.00) SQ
0.384 (9.75)
12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
0.346
(8.80)
BSC
0.404 (10.25)
0.394 (10.00) SQ
0.384 (9.75)
TOP VIEW
0.031
(0.80)
BSC
K
L
M
0.031 (0.80) BSC
0.346 (8.80) BSC
DETAIL A
0.067 (1.70) MAX
NOTE
0.010
(0.25)
NOM
DETAIL A
0.034 (0.85) MIN
THE ACTUAL POSITION OF THE BALL POPULATION
IS WITHIN 0.006 (0.150) OF ITS IDEAL POSITION
RELATIVE TO THE PACKAGE EDGES. THE ACTUAL
POSITION OF EACH BALL IS WITHIN 0.003 (0.08) OF
0.010 (0.25) MIN
0.022 (0.55)
0.020 (0.50)
0.018 (0.45)
0.005
(0.12)
MAX
SEATING
PLANE
ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION.
BALL DIAMETER
ORDERING GUIDE
Ambient
Temperature
Range
Instruction
Rate
(MHz)
Package
Description
Package
Option
Part Number
ADSP-2183KST-115
ADSP-2183BST-115
ADSP-2183KST-133
ADSP-2183BST-133
ADSP-2183KST-160
ADSP-2183BST-160
ADSP-2183KST-210
ADSP-2183KCA-210
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
28.8
28.8
33.3
33.3
40
40
52
128-Lead LQFP
128-Lead LQFP
128-Lead LQFP
128-Lead LQFP
128-Lead LQFP
128-Lead LQFP
128-Lead LQFP
144-Lead Mini-BGA
ST-128
ST-128
ST-128
ST-128
ST-128
ST-128
ST-128
CA-144
52
REV. C
–31–
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