ADSP-2184NBST-320_技术文档

a

DSP Microcomputer

ADSP-218xN Series

PERFORMANCE FEATURES

12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS

Sustained Performance

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP and 144-Ball Mini-BGA

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

SYSTEM INTERFACE FEATURES

Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to On-

Chip Memory (Mode Selectable)

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 200 CLKIN Cycle Recovery

from Power-Down Condition

4M-Byte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program and

Data Memory Transfers (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or through

Internal DMA Port

Low Power Dissipation in Idle Mode

INTEGRATION FEATURES

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

Up to 256K Bytes of On-Chip RAM, Configured as

Up to 48K Words Program Memory RAM

Up to 56K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Six External Interrupts

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

13 Programmable Flag Pins Provide Flexible System

Signaling

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

UART Emulation through Software SPORT

Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

FULL MEMORY MODE

MEMORY

PROGRAMMABLE

PROGRAM

EXTERNAL

ADDRESS

BUS

DATA

MEMORY

UP TO

DATA ADDRESS

GENERATORS

I/O

MEMORY

AND

FLAGS

PROGRAM

SEQUENCER

UP TO

DAG1 DAG2

48K ꢀ 24-BIT

56K ꢀ 16-BIT

.

e

r

EXTERNAL

DATA

BUS

e

h

m

PROGRAM MEMORY ADDRESS

a

r

g

a

i

d

BYTE DMA

CONTROLLER

k

DATA MEMORY ADDRESS

c

o

l

b

p

i

PROGRAM MEMORY DATA

DATA MEMORY DATA

h

c

OR

t

r

e

s

n

I

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

MAC SHIFTER

SERIAL PORTS

TIMER

INTERNAL

DMA

PORT

ALU

SPORT0

SPORT1

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

ICE-Port is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reli-

able. However, no responsibility is assumed by Analog Devices for its use,

nor for any infringements of patents or other rights of third parties that may One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

result from its use. No license is granted by implication or otherwise under Tel:781/329-4700

any patent or patent rights of Analog Devices. Fax:781/326-8703

http://www.analog.com

ADSP-218xN Series

GENERAL DESCRIPTION

This takes place while the processor continues to:

The ADSP-218xN series consists of six single chip micro-

computers optimized for digital signal processing applica-

tions. The high-level block diagram for the ADSP-218xN

series members appears on the previous page. All series

membersarepin-compatibleandaredifferentiatedsolelyby

the amount of on-chip SRAM. This feature, combined with

ADSP-21xx code compatibility, provides a great deal of

flexibility in the design decision. Specific family members

are shown in Table 1.

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the

internal DMA port

• Receive and/or transmit data through the byte DMA port

• Decrement timer

DEVELOPMENT SYSTEM

Analog Devices’ wide range of software and hardware

development tools supports the ADSP-218xN series. The

DSP tools include an integrated development environment,

an evaluation kit, and a serial port emulator.

Table 1. ADSP-218xN DSP Microcomputer Family

Program

VisualDSP++™isanintegrateddevelopmentenvironment,

allowing for fast and easy development, debug, and deploy-

ment.TheVisualDSP++projectmanagementenvironment

lets programmers develop and debug an application. This

environmentincludesaneasy-to-useassemblerthatisbased

on an algebraic syntax; an archiver (librarian/library build-

er); a linker; a PROM-splitter utility; a cycle-accurate,

instruction-level simulator; a C compiler; and a C run-time

library that

Memory

(K Words)

Data Memory

(K Words)

Device

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

4

16

8

32

48

32

4

16

8

32

56

48

includes DSP and mathematical functions.

ADSP-218xN series members combine the ADSP-2100

family base architecture (three computational units, data

address generators, and a program sequencer) with two

serial ports, a 16-bit internal DMA port, a byte DMA port,

a programmable timer, Flag I/O, extensive interrupt capa-

bilities, and on-chip program and data memory.

Debugging both C and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C and assembly code (interleaved source and

object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

ADSP-218xN series members integrate up to 256K bytes

of on-chip memory configured as up to 48K words (24-bit)

of program RAM, and up to 56K words (16-bit) of data

RAM. Power-down circuitry is also provided to meet the

low power needs of battery-operated portable equipment.

The ADSP-218xN is available in a 100-lead LQFP package

and 144-Ball Mini-BGA.

• Trace instruction execution

• Fill and dump memory

• Source level debugging

The VisualDSP++ IDE lets programmers define and

manage DSP software development. The dialog boxes and

property pages let programmers configure and manage all

of the ADSP-218xN development tools, including the

syntax highlighting in the VisualDSP++ editor. This capa-

bilitycontrolshowthedevelopmenttoolsprocessinputsand

generate outputs.

Fabricated in a high-speed, low-power, 0.18 µm CMOS

process, ADSP-218xN series members operate with a

12.5 ns instruction cycle time. Every instruction can

execute in a single processor cycle.

The ADSP-218xN’s flexible architecture and comprehen-

sive instruction set allow the processor to perform multiple

operationsinparallel. Inoneprocessorcycle, ADSP-218xN

series members can:

The ADSP-2189M EZ-KIT Lite™ provides developers

with a cost-effective method for initial evaluation of the

powerful ADSP-218xN DSP family architecture. The

ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP-

2189M DSP board supported by an evaluation suite of

VisualDSP++. With this EZ-KIT Lite, users can learn

about DSP hardware and software development and evalu-

ate potential applications of the ADSP-218xN series. The

ADSP-2189M EZ-KIT Lite provides an evaluation suite of

the VisualDSP++ development environment with the

C compiler, assembler, and linker. The size of the DSP

erxecutable that can be built using the EZ-KIT Lite tools is

limited to 8K words.

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc.

–2–

REV. 0

ADSP-218xN Series

The EZ-KIT Lite includes the following features:

• 75 MHz ADSP-2189M

units process 16-bit data directly and have provisions to

support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs single-

cycle multiply, multiply/add, and multiply/subtract opera-

tions with 40 bits of accumulation. The shifter performs

logical and arithmetic shifts, normalization, denormaliza-

tion, and derive exponent operations.

• Full 16-Bit Stereo Audio I/O with AD73322 Codec

• RS-232 Interface

• EZ-ICE Connector for Emulator Control

• DSP Demonstration Programs

• Evaluation Suite of VisualDSP++

The shifter can be used to efficiently implement numeric

format control, including multiword and block floating-

point representations.

TheADSP-218xEZ-ICE^®Emulator provides an easier and

more cost-effective method for engineers to develop and

optimize DSP systems, shortening product development

cycles for faster time-to-market. ADSP-218xN series

membersintegrateon-chipemulationsupportwitha14-pin

ICE-Port interface. This interface provides a simpler target

board connection that requires fewer mechanical clearance

considerations than other ADSP-2100 Family EZ-ICEs.

ADSP-218xN series members need not be removed from

thetargetsystem whenusing the EZ-ICE, nor areany adapt-

ers needed. Due to the small footprint of the EZ-ICE con-

nector, emulation can be supported in final board

designs.The EZ-ICE performs a full range of functions,

including:

The internal result (R) bus connects the computational

units so that the output of any unit may be the input of any

unit on the next cycle.

A powerful program sequencer and two dedicated data

address generators ensure efficient delivery of operands to

these computational units. The sequencer supports condi-

tional jumps, subroutine calls, and returns in a single cycle.

With internal loop counters and loop stacks, ADSP-218xN

series members execute looped code with zero overhead; no

explicit jump instructions are required to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access

data (indirect addressing), it is post-modified by the value

of one of four possible modify registers. A length value may

be associated with each pointer to implement automatic

modulo addressing for circular buffers.

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined

and altered

• PC upload and download functions

• Instruction-level emulation of program booting

and execution

Five internal buses provide efficient data transfer:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

• Complete assembly and disassembly of instructions

• C source-level debugging

Additional Information

This data sheet provides a general overview of ADSP-

218xN series functionality. For additional information on

the architecture and instruction set of the processor, refer

to the ADSP-218x DSP Hardware Reference and the ADSP-

218x DSP Instruction Set Reference.

The two address buses (PMA and DMA) share a single

external address bus, allowing memory to be expanded off-

chip, and the two data buses (PMD and DMD) share a

single external data bus. Byte memory space and I/O

memory space also share the external buses.

ARCHITECTURE OVERVIEW

The ADSP-218xN series instruction set provides flexible

data moves and multifunction (one or two data moves with

a computation) instructions. Every instruction can be exe-

cuted in a single processor cycle. The ADSP-218xN assem-

bly language uses an algebraic syntax for ease of coding and

readability. A comprehensive set of development tools sup-

ports program development.

Program memory can store both instructions and data, per-

mitting ADSP-218xN series members to fetch two oper-

ands in a single cycle, one from program memory and one

from data memory. ADSP-218xN series members can fetch

an operand from program memory and the next instruction

in the same cycle.

In lieu of the address and data bus for external memory

connection, ADSP-218xN series members may be config-

ured for 16-bit Internal DMA port (IDMA port) connec-

tion to external systems. The IDMA port is made up of 16

The functional block diagram is an overall block diagram of

the ADSP-218xN series. The processor contains three in-

dependent computational units: the ALU, the multiplier/

accumulator (MAC), and the shifter. The computational

EZ-ICE is a registered trademark of Analog Devices, Inc.

REV. 0

–3–

ADSP-218xN Series

data/address pins and five control pins. The IDMA port

provides transparent, direct access to the DSP’s on-chip

program and data RAM.

• SPORTs have independent framing for the receive and

transmit sections. Sections run in a frameless mode or

withframesynchronizationsignalsinternallyorexternally

generated. Frame sync signals are active high or inverted,

with either of two pulsewidths and timings.

An interface to low-cost byte-wide memory is provided by

the Byte DMA port (BDMA port). The BDMA port is

bidirectional and can directly address up to four megabytes

of external RAM or ROM for off-chip storage of program

overlays or data tables.

• SPORTs support serial data word lengths from 3 to

16 bits and provide optional A-law and µ-law compand-

ing, according to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate

unique interrupts on completing a data word transfer.

Thebytememory and I/O memoryspaceinterface supports

slow memories and I/O memory-mapped peripherals with

programmable wait state generation. External devices can

gain control of external buses with bus request/grant signals

(BR, BGH, and BG). One execution mode (Go Mode)

allows the ADSP-218xN to continue running from on-chip

memory. Normal execution mode requires the processor to

halt while buses are granted.

• SPORTscanreceiveandtransmitanentirecircularbuffer

of data with only one overhead cycle per data word. An

interrupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively

receive and transmit a 24 or 32 word, time-division mul-

tiplexed, serial bitstream.

ADSP-218xN series members can respond to eleven inter-

rupts. There can be up to six external interrupts (one edge-

sensitive, two level-sensitive, and three configurable) and

seven internal interrupts generated by the timer, the serial

ports (SPORT), the Byte DMA port, and the power-down

circuitry. There is also a master RESET signal. The two

serial ports provide a complete synchronous serial interface

with optional companding in hardware and a wide variety

of framed or frameless data transmit and receive modes of

operation.

• SPORT1 can be configured to have two external inter-

rupts (IRQ0 and IRQ1) and the FI and FO signals. The

internally generated serial clock may still be used in this

configuration.

PIN DESCRIPTIONS

ADSP-218xN series members are available in a 100-lead

LQFP package and a 144-Ball Mini-BGA package. In order

tomaintainmaximumfunctionalityandreducepackagesize

and pin count, some serial port, programmable flag, inter-

rupt and external bus pins have dual, multiplexed function-

ality. The external bus pins are configured during RESET

only, while serial port pins are software configurable during

program execution. Flag and interrupt functionality is

retained concurrently on multiplexed pins. In cases where

pin functionalityisreconfigurable, thedefaultstateisshown

in plain text in Table 2, while alternate functionality is

shown in italics.

Each port can generate an internal programmable serial

clock or accept an external serial clock.

ADSP-218xN series members provide up to 13 general-

purpose flag pins. The data input and output pins on

SPORT1 can be alternatively configured as an input flag

and an output flag. In addition, eight flags are programma-

ble as inputs or outputs, and three flags are always outputs.

A programmable interval timer generates periodic inter-

rupts. A 16-bit count register (TCOUNT) decrements

every n processor cycle, where n is a scaling value stored

in an 8-bit register (TSCALE). When the value of the count

register reaches zero, an interrupt is generated and the

count register is reloaded from a 16-bit period register

(TPERIOD).

Serial Ports

ADSP-218xN series members incorporate two complete

synchronous serial ports (SPORT0 and SPORT1) for serial

communications and multiprocessor communication.

Following is a brief list of the capabilities of the ADSP-

218xN SPORTs. For additional information on Serial

Ports, refer to the ADSP-218x DSP Hardware Reference.

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

–4–

REV. 0

ADSP-218xN Series

Table 2. Common-Mode Pins

Pin Name

# of Pins I/O

Function

RESET

BR

BG

BGH

DMS

PMS

IOMS

BMS

1

I

Processor Reset Input

Bus Request Input

Bus Grant Output

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

Byte Memory Select Output

O

CMS

1

O

Combined Memory Select Output

RD

WR

IRQ2

PF7

IRQL1

PF6

1

O

I

I/O

I

Memory Read Enable Output

Memory Write Enable Output

Edge- or Level-Sensitive Interrupt Request¹

Programmable I/O pin

1

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

I/O

IRQL0

PF5

I

I/O

IRQE

PF4

I

I/O

Mode D

PF3

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode C

PF2

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode B

PF1

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode A

PF0

I

I/O

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

CLKIN

XTAL

1

5

I

O

I/O

Clock Input

Quartz Crystal Output

Processor Clock Output

Serial Port I/O Pins

CLKOUT

SPORT0

SPORT1

IRQ1–0, FI, FO

PWD

PWDACK

FL0, FL1, FL2

V_DDINT

V_DDEXT

GND

V_DDINT

V_DDEXT

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts, FI, FO²

Power-Down Control Input

Power-Down Acknowledge Control Output

Output Flags

1

3

2

4

10

4

I

O

I

Internal V_DD(1.8 V) Power (LQFP)

External V_DD(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)

Ground (LQFP)

Internal V_DD(1.8 V) Power (Mini-BGA)

External V_DD(1.8 V, 2.5 V, or 3.3 V) Power (Mini-

BGA)

I

7

GND

EZ-Port

20

9

I

I/O

Ground (Mini-BGA)

For Emulation Use

1

2

Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will

vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable

flag.

SPORT configuration determined by the DSP System Control Register. Software configurable.

REV. 0

–5–

ADSP-218xN Series

Memory Interface Pins

signals at specific pins of the DSP during either of the two

operating modes (Full Memory or Host). A signal in one

table shares a pin with a signal from the other table, with the

active signal determined by the mode that is set. For the

sharedpinsandtheiralternatesignals(e.g.,A4/IAD3), refer

tothepackagepinouts inTable 27 onpage 40 andTable 28

on page 42.

ADSP-218xN series members can be used in one of two

modes:FullMemoryMode, whichallowsBDMAoperation

with full external overlay memory and I/O capability, or

Host Mode, which allows IDMA operation with limited

external addressing capabilities.

The operating mode is determined by the state of the Mode

C pin during RESET and cannot be changed while the

processor is running. Table 3 and Table 4 list the active

Table 3. Full Memory Mode Pins (Mode C = 0)

Pin Name

# of Pins

I/O

Function

A13–0

D23–0

14

24

O

I/O

Address Output Pins for Program, Data, Byte, and I/O Spaces

Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used

as Byte Memory Addresses.)

Table 4. Host Mode Pins (Mode C = 1)

Pin Name

# of Pins

I/O

Function

IAD15–0

A0

D23–8

IWR

IRD

16

1

16

1

I/O

O

I/O

I

IDMA Port Address/Data Bus

Address Pin for External I/O, Program, Data, or Byte Access¹

Data I/O Pins for Program, Data, Byte, and I/O Spaces

IDMA Write Enable

1

I

IDMA Read Enable

IAL

1

I

IDMA Address Latch Pin

IS

1

I

IDMA Select

IACK

1

O

IDMA Port Acknowledge Configurable in Mode D; Open Drain

1

In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

Terminating Unused Pins

Table 5 shows the recommendations for terminating

unused pins.

Table 5. Unused Pin Terminations

I/O

3-State

Reset

State

Pin Name¹

(Z)²

Hi-Z³Caused By

Unused Configuration

XTAL

CLKOUT

A13–1 or

IAD12–0

A0

D23–8

D7 or

IWR

D6 or

IRD

D5 or

IAL

O

Float

Float⁴

O (Z)

I/O (Z)

O (Z)

I/O (Z)

I

I/O (Z)

I

I/O (Z)

I

Hi-Z

I

Hi-Z

I

Hi-Z

I

BR, EBR

IS

BR, EBR

Float

High (Inactive)

Float

High (Inactive)

Float

Low (Inactive)

Float

BR, EBR

D4 or

IS

I/O (Z)

I

Hi-Z

I

BR, EBR

High (Inactive)

–6–

REV. 0

ADSP-218xN Series

Table 5. Unused Pin Terminations (Continued)

I/O

3-State

Reset

State

Pin Name¹

(Z)²

Hi-Z³Caused By

Unused Configuration

D3 or

IACK

I/O (Z)

Hi-Z

BR, EBR

Float

D2–0 or

IAD15–13

PMS

DMS

BMS

IOMS

CMS

RD

I/O (Z)

O (Z)

I

Hi-Z

O

BR, EBR

IS

Float

BR, EBR

WR

BR

Float

High (Inactive)

I

BG

BGH

IRQ2/PF7

O (Z)

O

I/O (Z)

O

I

EE

Float

Input = High (Inactive) or Program as

Output, Set to 1, Let Float⁵

IRQL1/PF6

IRQL0/PF5

IRQE/PF4

I/O (Z)

I

Input = High (Inactive) or Program as

Output, Set to 1, Let Float⁵

Input = High (Inactive) or Program as

Output, Set to 1, Let Float⁵

Input = High (Inactive) or Program as

Output, Set to 1, Let Float⁵

PWD

I

High

SCLK0

RFS0

DR0

I/O

I

Input = High or Low, Output = Float

High or Low

TFS0

DT0

I/O

O

I/O

I

I/O

O

I

O

I

O

I

High or Low

Float

Input = High or Low, Output = Float

High or Low

Float

SCLK1

RFS1/IRQ0

DR1/FI

TFS1/IRQ1

DT1/FO

EE

Float

EBR

I

Float

EBG

ERESET

EMS

O

I

O

I

O

I

O

I

Float

EINT

ECLK

ELIN

I

Float

ELOUT

O

Float

1

2

3

4

5

CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.

All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.

Hi-Z = High Impedance.

If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.

If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function

as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts,

and let pins float.

REV. 0

–7–

ADSP-218xN Series

Interrupts

The IFC register is a write-only register used to force and

clear interrupts. On-chip stacks preserve the processor

status and are automatically maintained during interrupt

handling. The stacks are 12 levels deep to allow interrupt,

loop, and subroutine nesting. The following instructions

allow global enable or disable servicing of the interrupts

(including power-down), regardless of the state of IMASK:

The interrupt controller allows the processor to respond to

the eleven possible interrupts and reset with minimum over-

head. ADSP-218xN series members provide four dedicated

external interrupt input pins: IRQ2, IRQL0, IRQL1, and

IRQE (shared with the PF7–4 pins). In addition, SPORT1

may be reconfigured for IRQ0, IRQ1, FI and FO, for a total

of six external interrupts. The ADSP-218xN also supports

internal interrupts from the timer, the byte DMA port, the

two serial ports, software, and the power-down control cir-

cuit. The interrupt levels are internally prioritized and indi-

vidually maskable (except power-down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to

be either level- or edge-sensitive. IRQL0 and IRQL1 are

level-sensitive and IRQE is edge-sensitive. The priorities

and vector addresses of all interrupts are shown in Table 6.

ENA INTS;

DIS INTS;

Disabling the interrupts does not affect serial port auto-

buffering or DMA. When the processor is reset, interrupt

servicing is enabled.

LOW-POWER OPERATION

ADSP-218xN series members have three low-power modes

that significantly reduce the power dissipation when the

deviceoperatesunder standbyconditions. Thesemodesare:

Table 6. Interrupt Priority and Interrupt Vector

Addresses

• Power-Down

• Idle

Interrupt Vector Address

(Hex)

• Slow Idle

Source Of Interrupt

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Reset (or Power-Up with

PUCR = 1)

0x0000 (Highest Priority)

Power-Down

(Nonmaskable)

IRQ2

IRQL1

IRQL0

SPORT0 Transmit

SPORT0 Receive

IRQE

BDMA Interrupt

SPORT1 Transmit or

IRQ1

0x002C

Power-Down

ADSP-218xNseriesmembershavealow-powerfeaturethat

lets the processor enter a very low-power dormant state

through hardware or software control. Following is a brief

list of power-down features. Refer to the ADSP-218x DSP

HardwareReference,“SystemInterface”chapter,fordetailed

information about the power-down feature.

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

0x0020

• Quick recovery from power-down. The processor begins

executing instructions in as few as 200 CLKIN cycles.

• Support for an externally generated TTL or CMOS

processor clock. The external clock can continue running

during power-down without affecting the lowest power

rating and 200 CLKIN cycle recovery.

SPORT1 Receive or IRQ0 0x0024

Timer

0x0028 (Lowest Priority)

• Support for crystal operation includes disabling the oscil-

lator to save power (the processor automatically waits

approximately 4096 CLKIN cycles for the crystal oscilla-

tor to start or stabilize), and letting the oscillator run to

allow 200 CLKIN cycle start-up.

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. In-

terrupts can be masked or unmasked with the IMASK reg-

ister. Individual interrupt requests are logically ANDed

with the bits in IMASK; the highest priority unmasked in-

terrupt is then selected. The power-down interrupt is non-

maskable.

• Power-down is initiated by either the power-down pin

(PWD) or the software power-down force bit. Interrupt

support allows an unlimited number of instructions to be

executed before optionally powering down. The power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

ADSP-218xN series members mask all interrupts for one

instruction cycle following the execution of an instruction

thatmodifiestheIMASKregister. Thisdoesnotaffectserial

port autobuffering or DMA transfers.

• Context clear/save control allows the processor to

continuewhereitleftofforstartwithacleancontextwhen

leaving the power-down state.

The interrupt control register, ICNTL, controls interrupt

nesting and defines the IRQ0, IRQ1, and IRQ2 external

interrupts to be either edge- or level-sensitive. The IRQE

pin is an external edge-sensitive interrupt and can be forced

and cleared. The IRQL0 and IRQL1 pins are external level

sensitive interrupts.

–8–

REV. 0

ADSP-218xN Series

• The RESET pin also can be used to terminate power-

down.

When the IDLE (n) instruction is used, it effectively slows

down the processor’s internal clock and thus its response

time to incoming interrupts. The one-cycle response time

of the standard idle state is increased by n, the clock divisor.

When an enabled interrupt is received, ADSP-218xN series

members remain in the idle state for up to a maximum of n

processor cycles (n = 16, 32, 64, or 128) before resuming

normal operation.

• Power-down acknowledge pin (PWDACK) indicates

when the processor has entered power-down.

Idle

When the ADSP-218xN is in the Idle Mode, the processor

waits indefinitely in a low-power state until an interrupt

occurs. When an unmasked interrupt occurs, it is serviced;

execution then continues with the instruction following the

IDLE instruction. In Idle mode IDMA, BDMA, and auto-

buffer cycle steals still occur.

When the IDLE (n) instruction is used in systems that have

an externally generated serial clock(SCLK), the serialclock

rate may be faster than the processor’s reduced internal

clock rate. Under these conditions, interrupts must not be

generated at a faster rate than can be serviced, due to the

additional time the processor takes to come out of the idle

state (a maximum of n processor cycles).

Slow Idle

The IDLE instruction is enhanced on ADSP-218xN series

members to let the processor’s internal clock signal be

slowed, further reducing power consumption. The reduced

clock frequency, a programmable fraction of the normal

clock rate, is specified by a selectable divisor given in the

IDLE instruction.

SYSTEM INTERFACE

Figure 1 shows typical basic system configurations with the

ADSP-218xN series, two serial devices, a byte-wide

EPROM, and optional external program and data overlay

memories (mode-selectable). Programmable wait state gen-

eration allows the processor to connect easily to slow periph-

eral devices. ADSP-218xN series members also provide

four external interrupts and two serial ports or six external

interrupts and one serial port. Host Memory Mode allows

access to the full external data bus, but limits addressing to

a single address bit (A0). Through the use of external hard-

ware, additional system peripherals can be added in this

mode to generate and latch address signals.

The format of the instruction is:

IDLE (N);

where N = 16, 32, 64, or 128. This instruction keeps the

processor fully functional, but operating at the slower clock

rate. While it is in this state, the processor’s other internal

clock signals, such as SCLK, CLKOUT, and timer clock,

are reduced by the same ratio. The default form of the in-

struction, when no clock divisor is given, is the standard

IDLE instruction.

FULL MEMORY MODE

ADSP-218xN

HOST MEMORY MODE

ADSP-218xN

1/2X CLOCK

OR

CRYSTAL

CLKIN

1/2X CLOCK

OR

CRYSTAL

A13–0

14

XTAL

ADDR13–0

1

A0

FL0–2

D23–16

D15–8

A0–A21

FL0–2

BYTE

MEMORY

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

16

24

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

DATA23–8

DATA23–0

DATA

CS

BMS

IRQL1/PF6

BMS

MODE D/PF3

MODE C/PF2

MODE A/PF0

A10–0

D23–8

WR

RD

WR

RD

MODE D/PF3

MODE C/PF2

MODE A/PF0

MODE B/PF1

ADDR

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

MODE B/PF1

DATA

IOMS

CS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

A13–0

D23–0

SERIAL

DEVICE

OVERLAY

MEMORY

ADDR

DATA

SERIAL

DEVICE

TWO 8K

PM SEGMENTS

DR1 OR FI

PMS

DMS

CMS

PMS

DMS

CMS

DR1 OR FI

SPORT0

SCLK0

RFS0

TFS0

DT0

DR0

TWO 8K

DM SEGMENTS

SPORT0

SCLK0

RFS0

TFS0

DT0

DR0

SERIAL

DEVICE

BR

BG

BGH

BR

BG

BGH

PWD

SERIAL

DEVICE

PWD

IDMA PORT

IRD/D6

PWDACK

SYSTEM

INTERFACE

OR

IWR/D7

IS/D4

IAL/D5

µCONTROLLER

IACK/D3

IAD15-0

16

Figure 1. Basic System Interface

REV. 0

–9–

ADSP-218xN Series

Clock Signals

RESET

ADSP-218xN series members can be clocked by either a

crystal or a TTL-compatible clock signal.

The RESET signal initiates a master reset of the ADSP-

218xN. The RESET signal must be asserted during the

power-up sequence to assure proper initialization. RESET

during initial power-up must be held long enough to allow

theinternalclocktostabilize.IfRESETisactivatedanytime

after power-up, the clock continues to run and does not

require stabilization time.

The CLKIN input cannot be halted, changed during oper-

ation, nor operated below the specified frequency during

normal operation. The only exceptionis while the processor

isinthepower-downstate. For additionalinformation, refer

to the ADSP-218x DSP Hardware Reference, for detailed

information on this power-down feature.

The power-up sequence is defined as the total time required

for the crystal oscillator circuit to stabilize after a valid V_DD

isappliedtotheprocessor, andfor theinternal phase-locked

loop (PLL) to lock onto the specific crystal frequency. A

minimum of 2000 CLKIN cycles ensures that the PLL has

locked, but does not include the crystal oscillator start-up

time. During this power-up sequence the RESET signal

should be held low. On any subsequent resets, the RESET

signal must meet the minimum pulse-width specification

(t_RSP).

If an external clock is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is

connected to the processor’s CLKIN input. When an exter-

nal clock is used, the XTAL pin must be left unconnected.

ADSP-218xN series members use an input clock with a

frequency equal to half the instruction rate; a 40 MHz input

clock yields a 12.5 ns processor cycle (which is equivalent

to 80 MHz). Normally, instructions are executed in a single

processor cycle. All device timing is relative to the internal

instruction clock rate, which is indicated by the CLKOUT

signal when enabled.

The RESET input contains some hysteresis; however, if an

RC circuit is used to generate the RESET signal, the use of

an external Schmitt trigger is recommended.

Because ADSP-218xN series members include an on-chip

oscillator circuit, an external crystal may be used. The

crystal should be connected across the CLKIN and XTAL

pins, with two capacitors connected as shown in Figure 2.

Capacitor values are dependent on crystal type and should

be specified by the crystal manufacturer. A parallel-

resonant, fundamental frequency, microprocessor-grade

crystal should be used.

The master reset sets all internal stack pointers to the empty

stackcondition,masksallinterrupts,andclearstheMSTAT

register. When RESET is released, if there is no pending

bus request and the chip is configured for booting, the boot-

loading sequence is performed. The first instruction is

fetched from on-chip program memory location 0x0000

once boot loading completes.

POWER SUPPLIES

ADSP-218xN series members have separate power supply

connections for the internal (V_DDINT) and external (V_DDEXT

power supplies. The internal supply must meet the 1.8 V

requirement. The external supply can be connected to a

A clock output (CLKOUT) signal is generated by the pro-

cessor at the processor’s cycle rate. This can be enabled and

disabled by the CLKODIS bit in the SPORT0 Autobuffer

Control Register.

)

1.8 V, 2.5 V, or 3.3 V supply. All external supply pins must

be connected to the same supply. All input and I/O pins can

tolerate input voltages up to 3.6 V, regardless of the external

supply voltage. This feature provides maximum flexibility

in mixing 1.8 V, 2.5 V, or 3.3 V components.

XTAL

CLKOUT

CLKIN

DSP

Figure 2. External Crystal Connections

–10–

REV. 0

ADSP-218xN Series

MODES OF OPERATION

The ADSP-218xN series modes of operation appear in

Table 7.

Table 7. Modes of Operation

Mode D

Mode C

Mode B

Mode A

Booting Method

X

0

BDMA feature is used to load the first 32 program memory words

from the byte memory space. Program execution is held off until all

32 words have been loaded. Chip is configured in Full Memory

Mode.¹

X

0

1

0

1

0

1

0

1

No automatic boot operations occur. Program execution starts at

external memory location 0. Chip is configured in Full Memory

Mode. BDMA can still be used, but the processor does not automat-

ically use or wait for these operations.

BDMA feature is used to load the first 32 program memory words

from the byte memory space. Program execution is held off until all

32 words have been loaded. Chip is configured in Host Mode. IACK

has active pull-down. (Requires additonal hardware.)

IDMA feature is used to load any internal memory as desired.

Program execution is held off until the host writes to internal

program memory location 0. Chip is configured in Host Mode.

IACK has active pull-down.¹

BDMA feature is used to load the first 32 program memory words

from the byte memory space. Program execution is held off until all

32 words have been loaded. Chip is configured in Host Mode; IACK

requires external pull-down. (Requires additonal hardware.)

IDMA feature is used to load any internal memory as desired.

Program execution is held off until the host writes to internal

program memory location 0. Chip is configured in Host Mode.

IACK requires external pull-down.¹

1

Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

Setting Memory Mode

Active Configuration

Memory Mode selection for the ADSP-218xN series is

made during chip reset through the use of the Mode C pin.

ThispinismultiplexedwiththeDSP’sPF2pin,socaremust

be taken in how the mode selection is made. The two meth-

ods for selecting the value of Mode C are active and passive.

Active Configuration involves the use of a three-statable

external driver connected to the Mode C pin. A driver’s

output enable should be connected to the DSP’s RESET

signal such that it only drives the PF2 pin when RESET is

active (low). When RESET is deasserted, the driver should

be three-state, thus allowing full use of the PF2 pin as either

an inputoroutput. Tominimizepower consumption during

power-down, configure the programmable flag as an output

when connected to a three-stated buffer. This ensures that

the pin will be held at a constant level, and will not oscillate

should the three-state driver’s level hover around the logic

switching point.

Passive Configuration

Passive Configuration involves the use of a pull-up or pull-

down resistor connected to the Mode C pin. To minimize

power consumption, or if the PF2 pin is to be used as

an output in the DSP application, a weak pull-up or pull-

down resistance, on the order of 10 kꢁ, can be used. This

value should be sufficient to pull the pin to the desired level

and still allow the pin to operate as a programmable flag

output without undue strain on the processor’s output

driver. For minimum power consumption during power-

down, reconfigure PF2 to be an input, as the pull-up or pull-

down resistance will hold the pin in a known state, and will

not switch.

IDMA ACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven

signal and cannot be “wire ORed.” Mode D = 1 and in host

mode: IACK is an open drain and requires an external

pull-down, but multiple IACK pins can be “wire ORed”

together.

REV. 0

–11–

ADSP-218xN Series

MEMORY ARCHITECTURE

RefertoFigure 3throughFigure 8,Table 8onpage 14,and

Table 9 on page 14 for PM and DM memory allocations in

the ADSP-218xN series.

The ADSP-218xN series provides a variety of memory and

peripheral interface options. The key functional groups are

Program Memory, Data Memory, Byte Memory, and I/O.

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

DATA MEMORY

MODEB = 0

0X3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0X3FE0

0X3FDF

RESERVED

4064 RESERVED

WORDS

PM OVERLAY 0

(RESERVED)

0X3000

0X2FFF

0X2000

0X1FFF

0X2000

0X1FFF

INTERNAL DM

0X2000

0X1FFF

RESERVED

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

0X1000

0X0FFF

DM OVERLAY 0

(RESERVED)

INTERNAL PM

0X0000

Figure 3. ADSP-2184 Memory Architecture

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

MODEB = 1

0X3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0X3FE0

0X3FDF

RESERVED

PM OVERLAY 0

(RESERVED)

INTERNAL DM

0X2000

0X1FFF

0X2000

0X1FFF

0X2000

0X1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0

(INTERNAL DM)

0X0000

Figure 4. ADSP-2185 Memory Architecture

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0X3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0X3FE0

0X3FDF

RESERVED

PM OVERLAY 0

(RESERVED)

INTERNAL DM

0X2000

0X1FFF

0X2000

0X1FFF

0X2000

0X1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0

(RESERVED)

0X0000

Figure 5. ADSP-2186 Memory Architecture

–12–

REV. 0

ADSP-218xN Series

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0X3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0X3FE0

0X3FDF

RESERVED

PM OVERLAY 0,4,5

(INTERNAL PM)

INTERNAL DM

0X2000

0X1FFF

0X2000

0X1FFF

0X2000

0X1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0,4,5

(INTERNAL DM)

0X0000

Figure 6. ADSP-2187 Memory Architecture

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

MODEB = 1

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY

0,4,5,6,7

INTERNAL DM

(INTERNAL PM)

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY

0,4,5,6,7,8

(INTERNAL DM)

0x0000

Figure 7. ADSP-2188 Memory Architecture

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

MODEB = 1

0X3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0X3FE0

0X3FDF

RESERVED

PM OVERLAY 0,4,5

(INTERNAL PM)

INTERNAL DM

0X2000

0X1FFF

0X2000

0X1FFF

0X2000

0X1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY

0,4,5,6,7

(INTERNAL DM)

0X0000

Figure 8. ADSP-2189 Memory Architecture

REV. 0

–13–

ADSP-218xN Series

Program Memory

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single exter-

nal address line (A0). External program execution is not

available in host mode due to a restricted data bus that is

only 16 bits wide.

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction opcodes and data. The

ADSP-218xN series has up to 48K words of Program

Memory RAM on chip, and the capability of accessing up

to two 8K external memory overlay spaces, using the exter-

nal data bus.

Table 8. PMOVLAY Bits

Processor

PMOVLAY

Memory

A13

A12–0

ADSP-2184N No Internal

Overlay Region

Not Applicable

ADSP-2185N

ADSP-2186N No Internal

Overlay Region

0

Internal Overlay

Not Applicable

ADSP-2187N 0, 4, 5

ADSP-2188N 0, 4, 5, 6, 7

ADSP-2189N 0, 4, 5

Internal Overlay

External Overlay 1

Not Applicable

0

Not Applicable

13 LSBs of Address Between 0x2000 and

0x3FFF

All Processors

1

All Processors

2

External Overlay 2

1

13 LSBs of Address Between 0x2000 and

0x3FFF

Data Memory

plete in one cycle. Accesses to external memory are timed

using the wait states specified by the DWAIT register and

the wait state mode bit.

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-

mapped control registers. The ADSP-218xN series has up

to 56K words of Data Memory RAM on-chip. Part of this

space is used by 32 memory-mapped registers. Support also

exists for up to two 8K external memory overlay spaces

through the external data bus. All internal accesses com-

Data Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single exter-

nal address line (A0).

Table 9. DMOVLAY Bits

Processor

DMOVLAY

Memory

A13

A12–0

ADSP-2184N No Internal Overlay

Region

Not Applicable

ADSP-2185N

ADSP-2186N No Internal Overlay

Region

0

Internal Overlay

Not Applicable

ADSP-2187N 0, 4, 5

ADSP-2188N 0, 4, 5, 6, 7, 8

ADSP-2189N 0, 4, 5, 6, 7

Internal Overlay

External Overlay 1

Not Applicable

0

Not Applicable

13 LSBs of Address

Between 0x0000

and 0x1FFF

All Processors

1

All Processors

2

External Overlay 2

1

13 LSBs of Address

Between 0x0000

and 0x1FFF

–14–

REV. 0

ADSP-218xN Series

Memory-Mapped Registers (New to the ADSP-218xM

and N series)

WAIT STATE CONTROL

15 14 13 12 11 10

9

8

7

6

5

4

3

2

¹r

0

1

e

t

ADSP-218xN series members have three memory-mapped

registers that differ from other ADSP-21xx Family DSPs.

The slight modifications to these registers (Wait State Con-

trol, Programmable Flag and Composite Select Control,

and System Control) provide the ADSP-218xN’s wait state

and BMS control features. Default bit values at reset are

shown; if no value is shown, the bit is undefined at reset.

Reserved bits are shown on a grey field. These bits should

always be written with zeros.

s

1

i

g

DM(0X3FFE)

1

¹e ¹

R

l

o

r

t

_IoOn_WAIT1

DWAIT

IOWAIT3

IOWAIT0

^IOWAIT2C

e

t

a

t

S

t

WAIT STATE MODE SELECT

i

a

0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES,

W

t

r

^{RANGING FROM 0 TO}e⁷⁾

s

n

I

1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,

RANGING FROM 0 TO 15)

Figure 9. Wait State Control Register

Composite Memory Select

I/O Space (Full Memory Mode)

ADSP-218xN series members have a programmable

memory select signal that is useful for generating memory

select signals for memories mapped to more than one space.

The CMS signal is generated to have the same timing as

each of the individual memory select signals (PMS, DMS,

BMS, IOMS) but can combine their functionality. Each bit

in the CMSSEL register, when set, causes the CMS signal

to be asserted when the selected memory select is asserted.

For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in

the CMSSEL register and use the CMS pinto drive the chip

select of the memory, and use either DMS or PMS as the

additional address bit.

ADSP-218xN series members support an additional exter-

nal memory space called I/O space. This space is designed

to support simple connections to peripherals (such as data

converters and external registers) or to bus interface ASIC

data registers. I/O space supports 2048 locations of 16-bit

wide data. The lower eleven bits of the external address bus

are used; the upper three bits are undefined.

Two instructions were added to the core ADSP-2100

Familyinstruction set to readfrom and writeto I/Omemory

space. The I/O space also has four dedicated three-bit wait

state registers, IOWAIT0–3 as shown in Figure 9, which in

combination with the wait state mode bit, specify up to 15

wait states to be automatically generated for each of four

regions. The wait states act on address ranges, as shown

in Table 10.

The CMS pin functions like the other memory select signals

with thesametiming andbusrequestlogic. A 1in the enable

bit causes the assertion of the CMS signal at the same time

as the selected memory select signal. All enable bits default

to 1 at reset, except the BMS bit.

Note:InFullMemoryMode, all2048locationsofI/Ospace

are directly addressable. In Host Memory Mode, only

address pin A0 is available; therefore, additional logic is

requiredexternallytoachievecompleteaddressabilityofthe

2048 I/O space locations.

See Figure 10 and Figure 11 for illustration of the program-

mable flag and composite control register and the system

control register.

Table 10. Wait States

Address Range Wait State Register

PROGRAMMABLE FLAG AND COMPOSITE

SELECT CONTROL

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0 and Wait State Mode

Select Bit

IOWAIT1 and Wait State Mode

Select Bit

IOWAIT2 and Wait State Mode

Select Bit

IOWAIT3 and Wait State Mode

Select Bit

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM(0X3FE6)

1

0

1

0

BM WAIT

CM SSEL

0 = DISABLE CMS

1 = ENABLE CMS

PFT YPE

0

1

=

INPUT

O UTPUT

(WHERE BIT: 11-IOM , 10-BM, 9-DM , 8-PM)

Figure 10. Programmable Flag and Composite Control

Register

REV. 0

–15–

ADSP-218xN Series

SYSTEM CONTROL

BDMA CONTROL

15 14 13 12 11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

0

1

0

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

1

0

1

DM (0x3FE3)

0

DM(0X3FFF)

0

1

0

BTYPE

BDIR

0 = LOAD FROM BM

BMPAGE

BDMA

OVERLAY

BITS

RESERVED

SET TO 0

RESERVED, ALWAYS

SET TO 0

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

0 = DISABLE

1 = ENABLE

(SEE TABLE 12)

1 = STORE TO BM

BCR

DISABLE BMS

0 = ENABLE BMS

1 = DISABLE BMS

0 = RUN DURING BDMA

1 = HALT DURING BDMA

SPORT1 ENABLE

0 = DISABLE

1 = ENABLE

Figure 12. BDMA Control Register

SPORT1 CONFIGURE

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SPORT1

TheBDMA circuit supportsfour differentdataformatsthat

are selected by the BTYPE register field. The appropriate

number of 8-bit accesses are done from the byte memory

space to build the word size selected. Table 11 shows the

data formats supported by the BDMA circuit.

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS

SHOULD ALWAYS BE WRITTEN WITH ZEROS.

Figure 11. System Control Register

Byte Memory Select

Table 11. Data Formats

Internal

The ADSP-218xN’s BMS disable feature combined with

the CMS pin allows use of multiple memories in the byte

memory space. For example, an EPROM could be attached

to the BMS select, and a flash memory could be connected

to CMS. Because at reset BMS is enabled, the EPROM

would be used for booting. After booting, software could

disable BMS and set the CMS signal to respond to BMS,

enabling the flash memory.

BTYPE Memory Space

Word Size Alignment

00

Program

24

Full Word

Memory

01

10

11

Data Memory

16

8

Full Word

MSBs

8

LSBs

Byte Memory

Unused bits in the 8-bit data memory formats are filled with

0s. The BIAD register field is used to specify the starting

address for the on-chip memory involved with the transfer.

The 14-bit BEAD register specifies the starting address for

the external byte memory space. The 8-bit BMPAGE reg-

ister specifies thestarting pagefor the external bytememory

space. The BDIR register field selects the direction of the

transfer. Finally, the 14-bit BWCOUNT register specifies

the number of DSP words to transfer and initiates the

BDMA circuit transfers.

The byte memory space is a bidirectional, 8-bit-wide,

external memory space used to store programs and data.

BytememoryisaccessedusingtheBDMAfeature. Thebyte

memory space consists of 256 pages, each of which is

16K ꢀ 8 bits.

The byte memory space on the ADSP-218xN series sup-

ports read and write operations as well as four different data

formats. Thebytememory usesdata bits15–8 for data. The

byte memory uses data bits 23–16 and address bits 13–0

to create a 22-bit address. This allows up to a 4 meg ꢀ 8

(32 megabit) ROM or RAM to be used without glue logic.

All byte memory accesses are timed by the BMWAIT reg-

ister and the wait state mode bit.

BDMA accesses can cross page boundaries during sequen-

tial addressing. A BDMA interrupt is generated on the com-

pletion of the number of transfers specified by the

BWCOUNT register.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller (Figure 12) allows

loading and storing of program instructions and data using

the byte memory space. The BDMA circuit is able to access

the byte memory space while the processor is operating

normally and steals only one DSP cycle per 8-, 16-, or 24-

bit word transferred.

The BWCOUNT register is updated after each transfer so

it can be used to check the status of the transfers. When

it reaches zero, the transfers have finished and a BDMA

interrupt is generated. The BMPAGE and BEAD registers

must not be accessed by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always

be on-chip program or data memory.

When the BWCOUNT register is written with a nonzero

value the BDMA circuit starts executing byte memory

accesses with wait states set by BMWAIT. These accesses

continue until the count reaches zero. When enough access-

es have occurred to create a destination word, it is trans-

ferred to or from on-chip memory. The transfer takes one

–16–

REV. 0

ADSP-218xN Series

Table 12. IDMA/BDMA Overlay Bits

DSP cycle. DSP accesses to external memory have priority

over BDMA byte memory accesses.

IDMA/BDMA

PMOVLAY

IDMA/BDMA

DMOVLAY

The BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occur-

ring. Setting the BCR bit to 0 allows the processor to con-

tinue operations. Setting the BCR bit to 1 causes the

processor to stop execution while the BDMA accesses are

occurring, to clear the context of the processor, and start

execution at address 0 when the BDMA accesses have

completed.

Processor

0

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

0, 4, 5

0, 4, 5, 6, 7

0, 4, 5

0, 4, 5, 6, 7, 8

ADSP-2189N 0, 4, 5

0, 4, 5, 6, 7

The BDMA overlay bits specify theOVLAY memory blocks

to be accessed for internal memory. Set these bits as indi-

cated in.

The IDMA port has a 16-bit multiplexed address and data

bus and supports 24-bit program memory. The IDMA port

is completely asynchronous and can be written while the

ADSP-218xN is operating at full speed.

Note: BDMA cannot access external overlay memory

regions 1 and 2.

TheDSPmemoryaddressislatchedandthenautomatically

incremented after each IDMA transaction. An external

devicecanthereforeaccessablockofsequentiallyaddressed

memory by specifying only the starting address of the block.

This increases throughput as the address does not have to

be sent for each memory access.

The BMWAIT field, which has four bits on ADSP-218xN

series members, allows selection up to 15 wait states for

BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

IDMA Port access occurs in two phases. The first is the

IDMA Address Latch cycle. When the acknowledge is as-

serted, a 14-bit address and 1-bit destination type can be

driven onto the bus by an external device. The address spec-

ifies an on-chip memory location, the destination type spec-

ifies whether it is a DM or PM access. The falling edge of

the IDMA address latch signal (IAL) or the missing edge of

the IDMA select signal (IS) latches this value into the

IDMAA register.

The IDMA Port provides an efficient means of communi-

cation between a host system and ADSP-218xN series

members. The port is used to access the on-chip program

memory and data memory of the DSP with only one DSP

cycle per word overhead. The IDMA port cannot, however,

be used to write to the DSP’s memory-mapped control reg-

isters. A typical IDMA transfer process is shown as follows:

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is

busy.

Once the address is stored, datacan be read from, or written

to, the ADSP-218xN’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD

and IWR respectively) signals the ADSP-218xN that a par-

ticular transaction is required. In either case, there is a one-

processor-cycle delay for synchronization. The memory

access consumes one additional processor cycle.

3. Host uses IS and IAL control lines to latch either the

DMA starting address (IDMAA) or the PM/DM

OVLAY selection into the DSP’s IDMA control regis-

ters. If Bit 15 = 1, the value of bits 7–0 represent the

IDMA overlay; bits 14 – 8 must be set to 0. If Bit 15 = 0,

the value of Bits 13–0 represent the starting address

of internal memory to be accessed and Bit 14 reflects

PM or DM for access. Set IDDMOVLAY and

IDPMOVLAY bits in the IDMA overlay register as

indicted in Table 12.

Once an access has occurred, the latched address is auto-

matically incremented, and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Asserting the IDMA port select (IS) and address latch

enable (IAL) directs the ADSP-218xN to write the address

onto the IAD14–0 bus into the IDMA Control Register

(Figure 13). If Bit 15 is set to 0, IDMA latches the address.

If Bit 15 is set to 1, IDMA latches into the OVLAY register.

This register, also shown in Figure 13, is memory-mapped

at address DM (0x3FE0). Note that the latched address

(IDMAA) cannot be read back by the host.

4. Host uses IS and IRD (or IWR) to read (or write) DSP

internal memory (PM or DM).

5. Host checks IACK line to see if the DSP has completed

the previous IDMA operation.

6. Host ends IDMA transfer.

When Bit 14 in 0x3FE7 is set to zero, short reads use the

timing shown in Figure 34 on page 37. When Bit 14 in

0x3FE7 is set to 1, timing in Figure 35 on page 38 applies

for short reads in short read only mode. Set IDDMOVLAY

REV. 0

–17–

ADSP-218xN Series

IDMA Port Booting

and IDPMOVLAY bits in the IDMA overlay register as

indicated in Table 12. Refer to the ADSP-218x DSP Hard-

ware Reference for additional details.

ADSP-218xN series members can also boot programs

through its Internal DMA port. If Mode C = 1, Mode B =

0,andModeA=1,theADSP-218xNbootsfromtheIDMA

port. IDMA feature can load as much on-chip memory as

desired. Program execution is held off until the host writes

to on-chip program memory location 0.

Note: In full memory mode all locations of 4M-byte

memory space are directly addressable. In host memory

mode, only address pin A0 is available, requiring additional

external logic to provide address information for the byte.

BUS REQUEST AND BUS GRANT

ADSP-218xN series members can relinquish control of the

data and address buses to an external device. When the

external device requires access to memory, it asserts the Bus

Request (BR) signal. If the ADSP-218xN is not performing

an external memory access, it responds to the active BR

input in the following processor cycle by:

IDMA OVERLAY

15 14 13 12 11 10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

DM (0x3FE7)

RESERVED SET TO 0

IDDMOVLAY

IDPMOVLAY

(SEE TABLE 12)

SHORT READ ONLY

0 = DISABLE

1 = ENABLE

• Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

• Asserting the bus grant (BG) signal, and

• Halting program execution.

0

U

DM (0x3FE0)

IDMAA ADDRESS

IDMAD DESTINATION MEMORY

TYPE

0 = PM

1 = DM

If Go Mode is enabled, the ADSP-218xN will not halt

program execution until it encounters an instruction that

requires an external memory access.

RESERVED SET TO 0

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE

BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.

IfanADSP-218xNseriesmemberisperforminganexternal

memory access when the external device asserts the BR

signal, it will not three-state the memory interfaces nor

assert the BGsignal untiltheprocessor cycle after the access

completes. The instruction does not need to be completed

when the bus is granted. If a single instruction requires two

external memory accesses, the bus will be granted between

the two accesses.

Figure 13. IDMA OVLAY/Control Registers

Bootstrap Loading (Booting)

ADSP-218xN series members have two mechanisms to

allow automatic loading of the internal program memory

after reset. The method for booting is controlled by the

Mode A, B, and C configuration bits.

When the BR signal is released, the processor releases the

BG signal, re-enables the output drivers, and continues

program execution from the point at which it stopped.

When the mode pins specify BDMA booting, the ADSP-

218xN initiates a BDMA boot sequence when reset is

released.

The bus request feature operates at all times, including

when the processor is booting and when RESET is active.

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR,

BMPAGE, BIAD, and BEAD registers are set to 0, the

BTYPE register is set to 0 to specify program memory 24-

bit words, and the BWCOUNT register is set to 32. This

causes 32 words of on-chip program memory to be loaded

from byte memory. These 32 words are used to set up the

BDMA to load in the remaining program code. The BCR

bit is also set to 1, which causes program execution to be

held off until all 32 words are loaded into on-chip program

memory. Execution then begins at address 0.

The BGH pin is asserted when an ADSP-218xN series

member requires the external bus for a memory or BDMA

access, but is stopped. The other device can release the bus

by deasserting bus request. Once the bus is released, the

ADSP-218xN deasserts BG and BGH and executes the

external memory access.

FLAG I/O PINS

ADSP-218xN series members have eight general-purpose

programmable input/output flag pins. They are controlled

by two memory-mapped registers. The PFTYPE register

determines the direction, 1 = output and 0 = input. The

PFDATA register is used to read and write the values on the

pins. Data being read from a pin configured as an input is

synchronized to the ADSP-218xN’s clock. Bits that are pro-

grammed as outputs will read the value being output. The

PF pins default to input during reset.

The ADSP-2100 Family development software (Revision

5.02 and later) fully supports the BDMA booting feature

and can generate byte memoryspace-compatible boot code.

The IDLE instruction can also be used to allow the proces-

sor to hold off execution while booting continues through

the BDMA interface. For BDMA accesses while in Host

Mode, the addresses to boot memory must be constructed

externally to the ADSP-218xN. The only memory address

bit provided by the processor is A0.

–18–

REV. 0

ADSP-218xN Series

In addition to the programmable flags, ADSP-218xN series

members have fivefixed-mode flags, FI, FO, FL0, FL1, and

FL2. FL0–FL2 are dedicated output flags. FI and FO are

available as an alternate configuration of SPORT1.

if the RESET pin is being used as a method of setting the

value of the mode pins, the effects of an emulator reset must

be taken into consideration.

One methodof ensuring that the values located on the mode

pins are those desired is to construct a circuit like the one

shown in Figure 14. This circuit forces the value located on

the Mode A pin to logic high, regardless of whether it is

latched via the RESET or ERESET pin.

Note: Pins PF0, PF1, PF2, and PF3 are also used for device

configuration during reset.

INSTRUCTION SET DESCRIPTION

The ADSP-218xN series assembly language instruction set

has an algebraic syntax that was designed for ease of coding

and readability. The assembly language, which takes full

advantage of the processor’s unique architecture, offers the

following benefits:

ERESET

RESET

ADSP-218xN

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

1kꢁ

MODE A/PF0

PROGRAMMABLE I/O

• Everyinstructionassemblesintoasingle, 24-bitwordthat

can execute in a single instruction cycle.

Figure 14. Mode A Pin/EZ-ICE Circuit

• The syntax is a superset ADSP-2100 Family assembly

language and is completely source and object code com-

patible with other family members. Programs may need

to be relocated to utilize on-chip memory and conform to

the ADSP-218xN’s interrupt vector and reset vector map.

The ICE-Port interface consists of the following ADSP-

218xN pins: EBR, EINT, EE, EBG, ECLK, ERESET,

ELIN, EMS, and ELOUT.

These ADSP-218xN pins must be connected only to the

EZ-ICE connector in the target system. These pins have no

function except during emulation, and do not require pull-

up or pull-down resistors. The traces for these signals

between the ADSP-218xN and the connector must be kept

as short as possible, no longer than 3 inches.

• Sixteen condition codes are available. For conditional

jump, call, return, or arithmetic instructions, the

condition can be checked and the operation executed in

the same instruction cycle.

• Multifunction instructions allow parallel execution of an

arithmetic instruction, with up to two fetches or one write

to processor memory space, during a single instruc-

tion cycle.

The following pins are also used by the EZ-ICE: BR, BG,

RESET, and GND.

The EZ-ICE uses the EE (emulator enable) signal to take

control of the ADSP-218xN in the target system. This

causes the processor to use its ERESET, EBR, and EBG

pins instead of the RESET, BR, and BG pins. The BG

output is three-stated. These signals do not need to be

jumper-isolated in the system.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

ADSP-218xN series members have on-chip emulation

support and an ICE-Port, a special set of pins that interface

to the EZ-ICE. These features allow in-circuit emulation

without replacing the target system processor by using only

a 14-pin connection from the target system to the EZ-ICE.

Target systems must have a 14-pin connector to accept the

EZ-ICE’s in-circuit probe, a 14-pin plug.

TheEZ-ICEconnectstothetargetsystemviaaribboncable

and a 14-pin female plug. The female plug is plugged onto

the 14-pin connector (a pin strip header) on the target

board.

Note: The EZ-ICE uses the same V_DDvoltage as the V_DD

voltage used for V_DDEXT. Because the input pins of the

ADSP-218xN series members are tolerant to input voltages

up to 3.6 V, regardless of the value of V_DDEXT, the voltage

setting for the EZ-ICE must not exceed 3.3 V.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is

shown in Figure 15. This connector must be added to the

target board design to use the EZ-ICE. Be sure to allow

enough room in the system to fit the EZ-ICE probe onto

the 14-pin connector.

Issuing the chip reset command during emulation causes

the DSP to perform a full chip reset, including a reset of its

memory mode. Therefore, it is vital that the mode pins are

set correctly PRIOR to issuing a chip reset command from

the emulator user interface. If a passive method of maintain-

ing mode information is being used (as discussed in Setting

Memory Mode on page 11), it does not matter that the

modeinformation islatched by anemulatorreset. However,

The 14-pin, 2-row pin strip header is keyed at the Pin 7

location—Pin 7mustberemoved fromtheheader.Thepins

must be 0.025 inch square and at least 0.20 inch in length.

REV. 0

–19–

ADSP-218xN Series

Target System Interface Signals

2

4

1

When the EZ-ICE board is installed, the performance on

some system signals changes. Design the system to be com-

patible with the following system interface signal changes

introduced by the EZ-ICE board:

GND

BG

3

EBG

BR

5

6

EBR

EINT

ELIN

ECLK

EMS

ERESET

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the

RESET signal.

8

7

ꢀ

KEY (NO PIN)

9

10

12

14

ELOUT

11

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the BR

signal.

EE

13

RESET

• EZ-ICE emulation ignores RESET and BR, when

single-stepping.

TOP VIEW

Figure 15. Target Board Connector for EZ-ICE

• EZ-ICE emulation ignores RESET and BR when in

Emulator Space (DSP halted).

Pin spacing should be 0.1ꢀ0.1 inches. The pin strip header

must have at least 0.15 inch clearance on all sides to accept

the EZ-ICE probe plug.

• EZ-ICEemulationignoresthestateoftargetBRincertain

modes. As a result, the target system may take control of

the DSP’s external memory bus only if bus grant (BG) is

asserted by the EZ-ICE board’s DSP.

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

Target Memory Interface

For the target system to be compatible with the EZ-ICE

emulator, it must comply with the memory interface guide-

lines listed below.

PM, DM, BM, IOM, and CM

Design the Program Memory (PM), Data Memory (DM),

Byte Memory (BM), I/O Memory (IOM), and Composite

Memory (CM) external interfaces to comply with worst-

case device timing requirements and switching characteris-

tics as specified in this data sheet. The performance of the

EZ-ICE may approach published worst-case specification

for somememory access timingrequirements and switching

characteristics.

Note: If the target does not meet the worst-case chip spec-

ification for memory access parameters, the circuitry may

not be able to be emulated at the desired CLKIN frequency.

Depending on the severity of the specification violation, the

system may be difficult to manufacture, as DSP compo-

nents statistically varyinswitchingcharacteristicand timing

requirements, within published limits.

Restriction: All memory strobe signals on the ADSP-

218xN (RD, WR, PMS, DMS, BMS, CMS, and IOMS)

used in the target system must have 10 kꢁ pull-up resistors

connected when the EZ-ICE is being used. The pull-up

resistors are necessary because there are no internal pull-

ups to guarantee their state during prolonged three-state

conditions resulting from typical EZ-ICE debugging ses-

sions. These resistors may be removed when the EZ-ICE is

not being used.

–20–

REV. 0

ADSP-218xN Series

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade (Commercial)

B Grade (Industrial)

Parameter¹

Unit

Max

Min

Max

Min

V_DDINT

V_DDEXT

V_INPUT

1.71

V_IL= – 0.3

0

1.89

3.6

V_IH= + 3.6

70

1.8

V_IL= – 0.3

–40

2.0

3.6

V_IH= + 3.6

+85

V

°C

2

T_AMB

1

2

Specifications subject to change without notice.

The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max V ), but voltage compliance (on outputs, V ) depends on the input V

,

IH

OH

DDEXT

because V

(max) approximately equals V

(max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1,

OH

DDEXT

TFS0, TFS1, A13–A1, PF7–PF0) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD).

ELECTRICAL CHARACTERISTICS

Parameter¹Description

Test Conditions

Min

Typ Max

Unit

V_IH

Hi-Level Input Voltage^{2, 3}

@ V_DDEXT= 1.71 to 2.0 V,

V_DDINT= max

1.25

V

@ V_DDEXT= 2.1 to 3.6 V,

V_DDINT= max

@ V_DDEXTϹ 2.0 V,

V_DDINT= min

V_IL

Lo-Level Input Voltage^{2, 3}

0.6

0.7

V

@ V_DDEXTм 2.0 V,

V

_DDINT= min

V_OH

Hi-Level Output Voltage^{2, 4, 5}@ V_DDEXT= 1.71 to 2.0 V,

I_OH= – 0.5 mA

1.35

V

@ V_DDEXT= 2.1 to 2.9 V, I_OH2.0

= – 0.5 mA

V

@ V_DDEXT= 3.0 to 3.6 V, I_OH2.4

= – 0.5 mA

V

@ V_DDEXT= 1.71 to 3.6 V,

V_DDEXT– 0.3

V

I_OH= – 100 µA⁶

V_OL

I_IH

Lo-Level Output Voltage^{2, 4, 5}@ V_DDEXT= 1.71 to 3.6 V,

I_OL= 2.0 mA

0.4

V

Hi-Level Input Current³

@ V_DDINT= max,

V_IN= 3.6 V

@ V_DDINT= max,

10

µA

mA

I_IL

Lo-Level Input Current³

10

V

_IN= 0 V

I_OZH

I_OZL

I_DD

Three-State Leakage

Current⁷

@ V_DDEXT= max,

10

V_IN= 3.6 V⁸

Three-State Leakage

@ V_DDEXT= max,

V_IN= 0 V⁸

@ V_DDINT= 1.8 V,

t_CK= 12.5 ns,

T_AMB= 25°C

@ V_DDINT= 1.8 V,

t_CK= 12.5 ns¹¹,

T_AMB= 25°C

10

Current⁷

Supply Current (Idle)⁹

6

I_DD

Supply Current (Dynamic)¹⁰

25

mA

REV. 0

–21–

ADSP-218xN Series

ELECTRICAL CHARACTERISTICS (CONTINUED)

Parameter¹Description

Test Conditions

Min

Typ Max

Unit

I_DD

Supply Current (Idle)⁹

@ V_DDINT= 1.9 V,

t_CK= 12.5 ns,

6.5

mA

T

_AMB= 25°C

I_DD

Supply Current (Dynamic)¹⁰

@ V_DDINT= 1.9 V,

t_CK= 12.5 ns¹¹,

T_AMB= 25°C

26

mA

@ V_DDINT= 1.8 V,

T_AMB= 25°C

in Lowest Power Mode

@ V_IN= 1.8 V,

f_IN= 1.0 MHz,

T_AMB= 25°C

I_DD

C_I

Supply Current (Power-

Down)¹²

100

µA

Input Pin Capacitance^{3, 6}

8

pF

C_O

Output Pin

@ V_IN= 1.8 V,

8

pF

Capacitance^{6, 7, 12, 13}

f

_IN= 1.0 MHz,

T_AMB= 25°C

1

2

3

4

5

6

7

8

9

Specifications subject to change without notice.

Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.

Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.

Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to V_DDEXTand GND, assuming no dc loads.

Guaranteed but not tested.

Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.

0 V on BR.

Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

I_DDmeasurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30%

are Type 2 and Type 6, and 20% are idle instructions.

V_IN= 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.

See ADSP-218x DSP Hardware Reference for details.

Output pin capacitance is the capacitive load for any three-stated output pin.

10

11

12

13

ABSOLUTE MAXIMUM RATINGS

Internal Supply Voltage (V_DDINT)¹. . . . . . . . –0.3 V to +2.2 V

External Supply Voltage (V_DDEXT) . . . . . . . . –0.3 V to +4.0 V

Input Voltage². . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

Output Voltage Swing³. . . . . . . . . . .–0.5 V to V_DDEXT+0.5 V

Operating Temperature Range . . . . . . . . . . .–40ºC to +85ºC

Storage Temperature Range . . . . . . . . . . . .–65ºC to +150ºC

Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . –280ºC

1

Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only. Functional operation of the device at these

or any other conditions greater than those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

2

Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0,

TFS1, A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1,

PWD).

Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR,

3

PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH).

–22–

REV. 0

ADSP-218xN Series

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-218xN features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

Power Dissipation

Assumptions:

To determine total power dissipation in a specific applica-

tion, the following equation should be applied for each

output: C ꢀ V_DD²ꢀ f

• External data memory is accessed every cycle with 50%

of the address pins switching.

• External data memory writes occur every other cycle with

50% of the data pins switching.

where:C=loadcapacitance, f= outputswitchingfrequency.

Example: In an application where external data memory

is used and no other outputs are active, power dissipation is

calculated as follows:

• Each address and data pin has a10 pFtotal load at the pin.

• Application operates at V_DDEXT= 3.3 V and t_CK= 30 ns.

Total Power Dissipation = P_INT+ (C ꢀV_DDEXT²ꢀ f)

P

_INT= internal power dissipation from Figure 20 on

page 26.

(C ꢀ V_DDEXT²ꢀ f) is calculated for each output, as in the

example in Table 13.

Table 13. Example Power Dissipation Calculation

Parameters

# of Pins

× C (pF)

× V_DDEXT²(V)

× f (MHz)

PD (mW)

Address

Data Output, WR

7

9

10

3.3²

20.0

15.25

19.59

RD

1

2

10

20.0

40.0

2.18

8.70

CLKOUT, DMS

45.72

Total power dissipation for this example is

P_INT+ 45.72 mW.

REV. 0

–23–

ADSP-218xN Series

Environmental Conditions

REFERENCE

SIGNAL

Table 14. Thermal Resistance

t_MEASURED

t_DIS

t_ENA

Mini-

BGA

(°C/W)

V

OH

LQFP

Symbol (°C/W)

(MEASURED)

Rating Description¹

V

(MEASURED) – 0.5V

(MEASURED) + 0.5V

OH

2.0V

1.0V

OUTPUT

V

Thermal Resistance

(Case-to-Ambient)

Thermal Resistance

(Junction-to-Ambient)

Thermal Resistance

(Junction-to-Case)

θ_CA

θ_JA

θ_JC

48

50

2

63.3

70.7

7.4

OL

V

OL

t_DECAY

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

1

Where the Ambient Temperature Rating (T_AMB) is:

Figure 18. Output Enable/Disable

Output Disable Time

T_AMB= T_CASE– (PD × θ_CA

)

T_CASE= Case Temperature in °C

PD = Power Dissipation in W

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. The

output disable time (t_DIS) is the difference of t_MEASUREDand

t_DECAY, as shown in Figure 18. The time is the interval from

when a reference signal reaches a high or low voltage level

to when the output voltages have changed by 0.5 V from the

measured output high or low voltage.

Test Conditions

INPUT

1.5V

2.0V

1.5V

0.8V

OUTPUT

The decay time, t_DECAY, is dependent on the capacitive load,

C_L, and the current load, i_L, on the output pin. It can be

approximated by the following equation:

Figure 16. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

C

_L× 0.5V

-------------------------

=

t_DECAY

i_L

I

OL

from which

t_DIS= t_MEASURED– t_DECAY

is calculated. If multiple pins (such as the data bus) are

disabled, the measurement value is that of the last pin to

stop driving.

TO

OUTPUT

1.5V

50pF

Output Enable Time

Output pins are considered to be enabled when they have

made a transition from a high-impedance state to when they

start driving. The output enable time (t_ENA) is the interval

from when a reference signal reaches a high or low voltage

level to when the output has reached a specified high or low

trip point, as shown in Figure 18. If multiple pins (such as

the data bus) are enabled, the measurement value is that of

the first pin to start driving.

I

OH

Figure 17. Equivalent Loading for AC Measurements

(Including All Fixtures)

–24–

REV. 0

ADSP-218xN Series

80

60

40

20

0

V

= 3.6V @ –40ꢂC

DDEXT

V

= 3.3V @ +25ꢂC

TIMING SPECIFICATIONS

DDEXT

OH

V

= 2.5V @ +85ꢂC

DDEXT

This section contains timing information for the DSP’s

external signals.

V

= 1.8V @ +85ꢂC

DDEXT

General Notes

V

= 3.6V @ –40ꢂC

–20

–40

–60

–80

DDEXT

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of

others. While addition or subtraction would yield meaning-

ful results for an individual device, the values given in this

data sheet reflect statistical variations and worst cases. Con-

sequently, parameters cannot be added up meaningfully to

derive longer times.

VV

==11.8.8/2/2.5.5VV@@++8855ꢂCꢂC

V

DDDDEEXXTT

OL

V

= 3.3V @ +25ꢂC

DDEXT

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE – V

Figure 19. Typical Output Driver Characteristics

for V_DDEXTat 3.6 V, 3.3 V, 2.5 V, and 1.8 V

Timing Notes

Switching characteristics specifyhow theprocessor changes

its signals. Designers have no control over this timing—

circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching

characteristics tell what the processor will do in a given

circumstance. Switching characteristics can also be used to

ensure that any timing requirement of a device connected

to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input

for a read operation. Timing requirements guarantee that

the processor operates correctly with other devices.

Frequency Dependency For Timing Specifications

t_CKis defined as 0.5 t_CKI. The ADSP-218xN uses an input

clock with a frequency equal to half the instruction rate. For

example, a 40 MHz input clock (which is equivalent to

25 ns) yields a 12.5 ns processor cycle (equivalent to

80 MHz). t_CKvalues within the range of 0.5 t_CKIperiod

should be substituted for all relevant timing parameters to

obtain the specification value.

Example: t_CKH= 0.5 t_CK– 2 ns = 0.5 (12.5 ns) – 2 ns= 4.25 ns

Output Drive Currents

Figure 19 shows typical I-V characteristics for the output

driversontheADSP-218xNseries.Thecurvesrepresentthe

current drive capability of the output drivers as a function

of output voltage.

Figure 21 shows the typical power-down supply current.

Capacitive Loading

Figure 22 and Figure 23 on page 26 show the capacitive

loading characteristics of the ADSP-218xN.

REV. 0

–25–

ADSP-218xN Series

1000

100

V

= 2.0V

= 1.9V

= 1.8V

= 1.7V

1, 2, 3

DD

POWER, INTERNAL

60

55

50

45

40

55mW

50mW

45mW

40mW

V

8

.

1

42mW

38mW

=

T

N

I

D

VD

35

30

34mW

30mW

10

0

25

20

55

60

65

70

1/t_CK– MHz

75

80

85

0

25

55

85

TEMPERATURE – °C

NOTES

1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER

1, 2, 4

POWER, IDLE

15.0

MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE

ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)

2. CURRENT REFLECTS DEVICE OPERATING WITH NO

INPUT LOADS.

14.0

13.0

13.5mW

12mW

12.0

11.0

Figure 21. Typical Power-Down Current

10.5mW

9.5m W

10.5mW

9mW

10.0

9.0

30

8.5mW

7.5mW

T = 85ꢂC

8.0

7.0

6.0

5.0

V

= 0V TO 2.0V

DD

25

20

15

55

60

65

70

1/t_CK– MHz

75

85

2

POWER, IDLE n MODES

12.0

10.0

8.0

12.0mW

10.5mW

10

5

9.5mW

8.5mW

V

CO R E = 1. 9V

CO R E = 1. 8V

D D

0

50

0

100

150

– pF

200

250

300

5.2mW

4.9mW

4.7mW

4.3mW

6.0

4.0

2.0

0.0

C

L

4.2mW

3.8mW

3.4mW

Figure 22. Typical Output Rise Time vs. Load Capacitance

(at Maximum Ambient Operating Temperature)

18

55

60

65

70

75

85

16

14

1/t_CK– MHz

NOTES

12

10

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT

LOADS.

2

3

8

TYPICAL POWER DISSIPATION AT 1.8V OR 1.9V V

25°C, EXCEPT WHERE SPECIFIED.

AND

DDINT

6

4

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS

DD

EXECUTING FROM INTERNAL MEMORY. 50% OF THE

2

INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13,

14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE

INSTRUCTIONS.

NOMINAL

4

–2

–4

–6

IDLE REFERS TO STATE OF OPERATION DURING EXECUTION

OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO

EITHER V

OR GND.

DD

0

50

100

150

200

250

C

– pF

L

Figure 20. Power vs. Frequency

Figure 23. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maximum Ambient Operating

Temperature)

–26–

REV. 0

ADSP-218xN Series

Clock Signals and Reset

Table 15. Clock Signals and Reset

Parameter

Min

Max

Unit

Timing Requirements:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

25

8

40

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5t_CK– 3

0

ns

8

Control Signals Timing Requirements:

1

t_RSP

t_MS

t_MH

RESET Width Low

Mode Setup before RESET High

Mode Hold after RESET High

5t_CK

7

5

ns

1

Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including

crystal oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

MODE A

D

t_MH

t_MS

RESET

t_RSP

Figure 24. Clock Signals and Reset

REV. 0

–27–

ADSP-218xN Series

Interrupts and Flags

Table 16. Interrupts and Flags

Parameter

Min

Max

Unit

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

0.25t_CK+ 10

0.25t_CK

ns

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5t_CK– 5

ns

0.5t_CK+ 4

1

2

If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be

recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference

for further information on interrupt servicing.)

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

3

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

Flag Outputs = PFx, FL0, FL1, FL2, FO.

4

5

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 25. Interrupts and Flags

–28–

REV. 0

ADSP-218xN Series

Bus Request–Bus Grant

Table 17. Bus Request–Bus Grant

Parameter

Min

Max

Unit

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

0.25t_CK+ 2

0.25t_CK+ 8

ns

BR Setup before CLKOUT Low¹

Switching Characteristics:

t_SD

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

CLKOUT High to xMS, RD, WR Disable²

0.25t_CK+ 8

ns

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low³

BGH High to xMS, RD, WR Enable³

0

0.25t_CK– 3

0

1

BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be

recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

xMS = PMS, DMS, CMS, IOMS, BMS.

2

3

BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

CMS, WR,

t_SD

t_SEC

IOMS

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 26. Bus Request–Bus Grant

REV. 0

–29–

ADSP-218xN Series

Memory Read

Table 18. Memory Read

Parameter

Min

Max

Unit

Timing Requirements:

t_RDD

t_AA

t_RDH

RD Low to Data Valid¹

0.5t_CK– 5 + w

0.75t_CK– 6 + w

ns

A13–0, xMS to Data Valid²

Data Hold from RD High

0

Switching Characteristics:

t_RP

RD pulsewidth

CLKOUT High to RD Low

A13–0, xMS Setup before RD Low

A13–0, xMS Hold after RD Deasserted

RD High to RD or WR Low

0.5t_CK– 3 + w

0.25t_CK– 2

0.25t_CK– 3

0.5t_CK– 3

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25t_CK+ 4

1

2

w = wait states x t_CK

xMS = PMS, DMS, CMS, IOMS, BMS.

.

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

t_ASR

t_CRD

t_RP

t_RWR

D0–D23

t_RDD

t_RDH

t_AA

WR

Figure 27. Memory Read

–30–

REV. 0

ADSP-218xN Series

Memory Write

Table 19. Memory Write

Parameter

Min

Max

Unit

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High¹

Data Hold after WR High

WR pulsewidth

WR Low to Data Enabled

0.5t_CK– 4 + w

0.25t_CK– 1

0.5t_CK– 3 + w

0

0.25t_CK– 3

0.25t_CK– 2

0.75t_CK– 5 + w

0.25t_CK– 1

0.5t_CK– 3

ns

A13–0, xMS Setup before WR Low²

Data Disable before WR or RD Low

CLKOUT High to WR Low

A13–0, xMS Setup before WR Deasserted

A13–0, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.25t_CK+ 4

t_WRA

t_WWR

1

w = wait states ꢀ t_CK

.

2

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

D0–D23

t_DW

t_WDE

RD

Figure 28. Memory Write

REV. 0

–31–

ADSP-218xN Series

Serial Ports

Table 20. Serial Ports

Parameter

Min

Max

Unit

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

30

4

7

ns

DR/TFS/RFS Setup before SCLK Low

DR/TFS/RFS Hold after SCLK Low

SCLKIN Width

12

Switching Characteristics:

t_CC

CLKOUT High to SCLKOUT

SCLK High to DT Enable

SCLK High to DT Valid

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

0.25t_CK

0

0.25t_CK+ 6

ns

t_SCDE

t_SCDV

t_RH

12

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

12

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCP

t_SCH

DR

TFS

I

N

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME

MODE

t_RDV

RFS

OUT

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME

MODE

t_RDV

RFS

IN

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

Figure 29. Serial Ports

–32–

REV. 0

ADSP-218xN Series

IDMA Address Latch

Table 21. IDMA Address Latch

Parameter

Min

Max

Unit

Timing Requirements:

t_IALP

t_IASU

t_IAH

t_IKA

t_IALS

t_IALD

Duration of Address Latch^{1, 2}

10

5

3

0

3

ns

IAD15–0 Address Setup before Address Latch End²

IAD15–0 Address Hold after Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read after Address Latch End^{2, 3}

Address Latch Start after Address Latch End^{1, 2}

2

1

2

3

Start of Address Latch = IS Low and IAL High.

End of Address Latch = IS High or IAL Low.

Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

t_IALD

IAL

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

IRD OR

IWR

Figure 30. IDMA Address Latch

REV. 0

–33–

ADSP-218xN Series

IDMA Write, Short Write Cycle

Table 22. IDMA Write, Short Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

10

3

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

10

ns

1

2

3

4

Start of Write = IS Low and IWR Low.

End of Write = IS High or IWR High.

If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 31. IDMA Write, Short Write Cycle

–34–

REV. 0

ADSP-218xN Series

IDMA Write, Long Write Cycle

Table 23. IDMA Write, Long Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

0.5t_CK+ 5

0

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5t_CK

ns

10

1

2

3

4

Start of Write = IS Low and IWR Low.

If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 32. IDMA Write, Long Write Cycle

REV. 0

–35–

ADSP-218xN Series

IDMA Read, Long Read Cycle

Table 24. IDMA Read, Long Read Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKR

t_IRK

IACK Low before Start of Read¹

End of read after IACK Low²

0

2

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

10

ns

IAD15–0 Data Setup before IACK Low

0.5t_CK– 3

0

IAD15 –0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

10

11

0

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³2t_CK– 5

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

t_CK– 5

1

2

3

4

Start of Read = IS Low and IRD Low.

End of Read = IS High or IRD High.

DM read or first half of PM read.

Second half of PM read.

IACK

t_iKHR

t_IKR

IS

IRD

t_IRK

t_IKDH

t_IKDS

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_{IRDH1 OR}t_IRDH2

t_iKDD

Figure 33. IDMA Read, Long Read Cycle

–36–

REV. 0

ADSP-218xN Series

IDMA Read, Short Read Cycle

Table 25. IDMA Read, Short Read Cycle

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements:

t_IKR

t_IRP1

t_IRP2

IACK Low before Start of Read³

0

10

ns

Duration of Read (DM/PM1)⁴

Duration of Read (PM2)⁵

2t_CK– 5

t_CK– 5

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read³

10

ns

IAD15–0 Data Hold after End of Read⁶

0

IAD15–0 Data Disabled after End of Read⁶

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

1

Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) bit 14 of the IDMA overlay

register, and is disabled by default upon reset.

Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.

Start of Read = IS Low and IRD Low.

DM Read or first half of PM Read.

Second half of PM Read.

2

3

4

5

6

End of Read = IS High or IRD High.

IACK

t_IKR

t_IKHR

IS

t_IRP

IRD

t_IKDH

t_IRDE

DATA

t_IKDD

t_iRDV

Figure 34. IDMA Read, Short Read Cycle

REV. 0

–37–

ADSP-218xN Series

IDMA Read, Short Read Cycle in Short Read Only Mode

Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode

Parameter¹

Min

Max

Unit

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read²

Duration of Read³

0

10

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read²

10

ns

IAD15–0 Previous Data Hold after End of Read³

IAD15–0 Previous Data Disabled after End of Read³

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

0

1

Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing

to the register or by an external host writing to the register. Disabled by default.

Start of Read = IS Low and IRD Low. Previous data remains until end of read.

End of Read = IS High or IRD High.

2

3

IACK

t_IKR

t_{IK HR}

IS

t_IRP

IRD

t_{IKD H}

t_IRDE

IAD15–0

t_IKDD

t_IRDV

LEGEND:

IMPLIES THAT IS AND IRD CAN BE

HELD INDEFINITELY BY HOST

Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode

–38–

REV. 0

ADSP-218xN Series

deassertion of RESET. The multiplexed pins DT1/FO,

TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode

selectable by setting Bit 10 (SPORT1 configure) of the

System Control Register. If Bit 10 = 1, these pins have serial

port functionality. If Bit 10 = 0, these pins are the external

interrupt and flag pins. This bit is set to 1 by default, upon

reset.

LQFP Package Pinout

TheLQFPpackagepinoutisshown in theillustrationbelow

and in Table 27. Pin names in bold text in the table replace

the plain-text-named functions when Mode C = 1. A + sign

separates two functions when either function can be active

for either major I/O mode. Signals enclosed in brackets [ ]

are state bits latched from the value of the pin at the

100-LEAD LQFP PIN CONFIGURATION

75 D15

74 D14

A4/IAD3

A5/IAD4

GND

1

2

3

4

5

6

7

8

9

PIN 1

IDENTIFIER

D13

73

72 D12

71 GND

70 D11

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

69

D10

68 D9

V

67

DDEXT

66 GND

65 D8

A12/IAD11 10

A13/IAD12 11

GND 12

64 D7/IWR

63 D6/IRD

ADSP-218xN

CLKIN 13

TOP VIEW

(Not to Scale)

XTAL

62

D5/IAL

14

15

61 D4/IS

V

DDEXT

60 GND

CLKOUT 16

GND 17

V

59

DDINT

V

58 D3/IACK

57 D2/IAD15

56 D1/IAD14

55 D0/IAD13

54 BG

18

DDINT

WR 19

RD 20

BMS 21

DMS 22

PMS 23

53 EBG

52 BR

IOMS 24

CMS 25

51 EBR

REV. 0

–39–

ADSP-218xN Series

Table 27. LQFP Package Pinout

Table 27. LQFP Package Pinout (Continued)

Pin #

Pin Name

Pin #

Pin Name

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

BR

EBG

BG

1

2

3

4

5

6

7

8

A4/IAD3

A5/IAD4

GND

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

V_DDINT

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

V_DDEXT

D9

D10

D11

GND

D12

D13

D14

D15

D16

D17

D18

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

V_DDEXT

CLKOUT

GND

V_DDINT

WR

RD

BMS

DMS

PMS

IOMS

CMS

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

V_DDEXT

DT1/FO

TFS1/IRQ1

RFS1/IRQ0

DR1/FI

GND

SCLK1

ERESET

RESET

EMS

EE

ECLK

ELOUT

ELIN

EINT

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3 [Mode D]

PF2 [Mode C]

V_DDEXT

PWD

GND

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

EBR

–40–

REV. 0

ADSP-218xN Series

at the deassertion of RESET. The multiplexed pins

DT1/FO,TFS1/IRQ1,RFS1/IRQ0,andDR1/FI,aremode

selectable by setting Bit 10 (SPORT1 configure) of the

System Control Register. If Bit 10 = 1, these pins have serial

port functionality. If Bit 10 = 0, these pins are the external

interrupt and flag pins. This bit is set to 1 by default upon

reset.

Mini-BGA Package Pinout

The Mini-BGA package pinout is shown in the illustration

below and in Table 28. Pin names in bold text in the table

replace the plain text named functions when Mode C = 1.

A + sign separates two functions when either function can

be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin

144-BALL MINI-BGA PACKAGE PINOUT (BOTTOM VIEW)

1

12

11

10

9

8

7

6

5

4

3

2

A

B

GND

D22

NC

GND

NC

A0

GND

A1/IAD0

A2/IAD1

V

D16

D17

D18

D20

D23

GND

NC

GND

A3/IAD2

A4/IAD3

DDEXT

V

C

D

E

F

D14

GND

D10

D9

NC

D15

D12

D19

D13

GND

D11

D21

NC

PWD

A7/IAD6

A9/IAD8

A5/IAD4

BGH

RD

NC

A6/IAD5

PWDACK

NC

DDEXT

PF2

PF1

[MODE B]

WR

[MODE C]

PF3

PF0

[MODE A]

V

GND

NC

GND

FL2

NC

FL0

A8/IAD7

A12/IAD11

DDEXT

[MODE D]

D8

D7/IWR

NC

FL1

NC

A11/IAD10

NC

A13/IAD12

G

H

D4/IS

NC

D5/IAL

D6/IRD

NC

A10/IAD9

GND

NC

XTAL

V

GND

D3/IACK

D2/IAD15

TFS0

DT0

GND

CLKIN

DDINT

V

J

D1/IAD14

BG

RFS1/IRQ0

D0/IAD13

SCLK0

RFS0

NC

CLKOUT

DDEXT

DDINT

DDEXT

DDINT

K

EBG

BR

EBR

ERESET

SCLK1

TFS1/IRQ1

DMS

BMS

NC

L

IRQL1 + PF6

EINT

ELOUT

EE

ELIN

RESET

GND

DR0

PMS

GND

IOMS

CMS

IRQE + PF4

M

ECLK

EMS

NC

DR1/FI

DT1/FO

NC

IRQ2 + PF7 IRQL0 + PF5

REV. 0

–41–

ADSP-218xN Series

Table 28. Mini-BGA Package Pinout

(Continued)

Ball #

Pin Name

Ball #

Pin Name

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

E01

A2/IAD1

A1/IAD0

GND

A0

NC

GND

NC

D22

GND

A4/IAD3

A3/IAD2

GND

NC

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

J01

A8/IAD7

FL0

PF0 [MODE A]

FL2

PF3 [MODE D]

GND

V_DDEXT

GND

D10

A13/IAD12

NC

A12/IAD11

A11/IAD10

FL1

NC

D7/IWR

D11

D8

NC

D9

XTAL

NC

GND

NC

GND

V_DDEXT

D23

D20

D18

D17

D16

PWDACK

A6/IAD5

RD

A5/IAD4

A7/IAD6

PWD

V_DDEXT

D21

D19

D15

NC

D14

NC

WR

NC

BGH

A9/IAD8

PF1 [MODE B]

PF2 [MODE C]

NC

D13

D12

A10/IAD9

NC

D6/IRD

D5/IAL

NC

D4/IS

CLKIN

GND

V_DDINT

DT0

TFS0

D2/IAD15

D3/IACK

GND

NC

GND

CLKOUT

V_DDINT

NC

GND

V_DDEXT

J02

J03

V_DDEXT

E02

V_DDEXT

J04

J05

V_DDEXT

–42–

REV. 0

ADSP-218xN Series

Table 28. Mini-BGA Package Pinout

(Continued)

Ball #

Pin Name

J06

J07

J08

J09

SCLK0

D0/IAD13

RFS1/IRQ0

BG

J10

J11

J12

D1/IAD14

V_DDINT

NC

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

NC

BMS

DMS

RFS0

TFS1/IRQ1

SCLK1

ERESET

EBR

BR

EBG

IRQE + PF4

NC

IRQL1 + PF6

IOMS

GND

PMS

DR0

GND

RESET

ELIN

ELOUT

EINT

IRQL0 + PF5

IRQL2 + PF7

NC

CMS

GND

DT1/FO

DR1/FI

GND

NC

EMS

EE

ECLK

REV. 0

–43–

ADSP-218xN Series

OUTLINE DIMENSIONS

Dimensions in outline dimension drawings are shown in millimeters.

144-BALL MINI-BGA

(CA-144)

A1 CORNER INDEX

10.10

TRIANGLE

10.00 SQ

9.90

12 11 10 9 8 7 6 5 4

3

2 1

A

B

C

D

E

F

G

H

J

8.80

BSC

SQ

0.80

BSC

BALL

PITCH

K

L

M

BOTTOM VIEW

TOP VIEW

DETAIL A

1.40

MAX

1.00

0.85

0.43

0.25

NOTES:

1.

DIMENSIONS IN MILLIMETERS .

SEATING

PLANE

2. ACTUAL POSITION OF THE BALL GRID IS

WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE

TO THE PACKAGE EDGES.

0.55

0.50

0.45

0.10

MAX

3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.08

OF ITS IDEAL POSITION, RELATIVE TO THE

BALL GRID.

BALL

DIAMETER

DETAIL A

CENTER DIMENSIONS ARE NOMINAL.

4.

100-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP)

(ST-100)

16.20

16.00 SQ

15.80

14.05

14.00 SQ

13.95

1.60 MAX

12.00 TYP BSC

0.75

0.60 TYP

0.50

100

1

76

75

12ꢂ

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.08

MAX LEAD

COPLANARITY

25

26

51

50

6ꢂ ± 4ꢂ

0ꢂ - 7ꢂ

0.50

BSC (LEAD PITCH)

0.27

0.15

0.05

0.22 TYP (LEAD WIDTH)

0.17

NOTES:

DIMENSIONS IN MILLIMETERS.

1.

2.

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

CENTER DIMENSIONS ARE NOMINAL.

3.

–44–

REV. 0

ADSP-218xN Series

ORDERING GUIDE

Table 29. Ordering Guide

Ambient

Temperature

Range

Part

Number

Instruction

Rate (MHz)

Package

Description

Package

Option

ADSP-2184NKST-320

ADSP-2184NBST-320

ADSP-2185NKST-320

ADSP-2185NBST-320

ADSP-2186NKST-320

ADSP-2186NBST-320

ADSP-2187NKST-320

ADSP-2187NBST-320

ADSP-2188NKST-320

ADSP-2188NBST-320

ADSP-2189NKST-320

ADSP-2189NBST-320

ADSP-2184NKCA-320

ADSP-2184NBCA-320

ADSP-2185NKCA-320

ADSP-2185NBCA-320

ADSP-2186NKCA-320

ADSP-2186NBCA-320

ADSP-2187NKCA-320

ADSP-2187NBCA-320

ADSP-2188NKCA-320

ADSP-2188NBCA-320

ADSP-2189NKCA-320

ADSP-2189NBCA-320

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to 85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

–40ºC to +85ºC

0ºC to 70ºC

80

100-Lead LQFP

144-Ball MBGA

ST-100

CA-144

80

–40ºC to +85ºC

REV. 0

–45–

–46–

–47–

–48–


型号：	ADSP-2184NBST-320
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总48页 (文件大小：1466K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2184NBST-320 [ADI]

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