ADSP-2185_技术文档

a

DSP Microcomputer

ADSP-2185

FUNCTIO NAL BLO CK D IAGRAM

FEATURES

PERFORMANCE

30 ns Instruction Cycle Tim e 33 MIPS Sustained

Perform ance

Single-Cycle Instruction Execution

Single-Cycle Context Sw itch

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

PROGRAMMABLE

DATA ADDRESS

GENERATORS

I/O

AND

FLAGS

EXTERNAL

ADDRESS

BUS

16k

؋

24

PROGRAM

MEMORY

16k

؋

16

DATA

MEMORY

PROGRAM

SEQUENCER

DAG 1 DAG 2

EXTERNAL

DATA

BUS

3-Bus Architecture Allow s Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Pow er-Dow n Mode Featuring Low CMOS Standby

Pow er Dissipation w ith 100 Cycle Recovery from

Pow er-Dow n Condition

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

ALU SHIFTER

SERIAL PORTS

SPORT 0 SPORT 1

TIMER

Low Pow er Dissipation in Idle Mode

INTERNAL

DMA

PORT

MAC

INTEGRATION

ADSP-2100 Fam ily Code Com patible, w ith Instruction

Set Extensions

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

80K Bytes of On-Chip RAM, Configured as

16K Words On-Chip Program Mem ory RAM and

16K Words On-Chip Data Mem ory RAM

Dual Purpose Program Mem ory for Both Instruction

and Data Storage

Six External Interrupts

13 Program m able Flag Pins Provide Flexible System

Signaling

UART Em ulation through Softw are SPORT Reconfiguration

ICE-Port™* Em ulator Interface Supports Debugging

in Final System s

Independent ALU, Multiplier/ Accum ulator and Barrel

Shifter Com putational Units

Tw o Independent Data Address Generators

Pow erful Program Sequencer Provides

Zero Overhead Looping Conditional Instruction

Execution

GENERAL NO TE

T his data sheet represents production grade specifications for

the ADSP-2185 (5 V).

Program m able 16-Bit Interval Tim er w ith Prescaler

100-Lead TQFP

GENERAL D ESCRIP TIO N

T he ADSP-2185 is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

On-Chip Mem ory (Mode Selectable)

T he ADSP-2185 combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

4 MByte Byte Mem ory Interface for Storage of Data

Tables & Program Overlays

8-Bit DMA to Byte Mem ory for Transparent Program

and Data Mem ory Transfers (Mode Selectable)

I/ O Mem ory Interface w ith 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Program m able Mem ory Strobe & Separate I/ O Mem ory

Space Perm its “Glueless” System Design

(Mode Selectable)

T he ADSP-2185 integrates 80K bytes of on-chip memory con-

figured as 16K words (24-bit) of program RAM and 16K words

(16-bit) of data RAM. Power-down circuitry is also provided to

meet the low power needs of battery operated portable equip-

ment. T he ADSP-2185 is available in 100-pin T QFP package.

Program m able Wait State Generation

Tw o Double-Buffered Serial Ports w ith Com panding

Hardw are and Autom atic Data Buffering

Autom atic Booting of On-Chip Program Mem ory from

Byte-Wide External Mem ory, e.g., EPROM, or

Through Internal DMA Port

In addition, the ADSP-2185 supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking, for increased flexibility.

*ICE -P or t is a tr adem ar k of Analog D evices, Inc.

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

ADSP-2185

T he EZ-ICE^®* performs a full range of functions, including:

Fabricated in a high speed, double metal, low power, 0.5 µm

CMOS process, the ADSP-2185 operates with a 30 ns instruc-

tion cycle time. Every instruction can execute in a single proces-

sor cycle.

• In-target operation

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

• Instruction-level emulation of program booting and execution

• Complete assembly and disassembly of instructions

• C source-level debugging

See Designing An EZ-ICE^®*-Compatible T arget System in the

ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as

well as the T arget Board Connector for EZ-ICE^®* Probe sec-

tion of this data sheet for the exact specifications of the EZ-ICE^®*

target board connector.

T he ADSP-2185’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle the ADSP-2185 can:

• generate the next program address

• fetch the next instruction

• perform one or two data moves

• update one or two data address pointers

• perform a computational operation

T his takes place while the processor continues to:

• receive and transmit data through the two serial ports

• receive and/or transmit data through the internal DMA port

• receive and/or transmit data through the byte DMA port

• decrement timer

Additional Infor m ation

T his data sheet provides a general overview of ADSP-2185

functionality. For additional information on the architecture and

instruction set of the processor, refer to the ADSP-2100 Family

User’s Manual. For more information about the development

tools, refer to the ADSP-2100 Family Development Tools Data

Sheet.

D evelopm ent System

T he ADSP-2100 Family Development Software, a complete set

of tools for software and hardware system development, sup-

ports the ADSP-2185. T he System Builder provides a high level

method for defining the architecture of systems under develop-

ment. T he Assembler has an algebraic syntax that is easy to

program and debug. T he Linker combines object files into an

executable file. The Simulator provides an interactive instruction-

level simulation with a reconfigurable user interface to display

different portions of the hardware environment. A PROM

Splitter generates PROM programmer compatible files. T he

C Compiler, based on the Free Software Foundation’s GNU

C Compiler, generates ADSP-2185 assembly source code. T he

source code debugger allows programs to be corrected in the

C environment. T he Runtime Library includes over 100 ANSI-

standard mathematical and DSP-specific functions.

ARCH ITECTURE O VERVIEW

T he ADSP-2185 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. T he ADSP-2185 assembly language uses an alge-

braic syntax for ease of coding and readability. A comprehensive

set of development tools supports program development.

POWER-DOWN

CONTROL

FULL MEMORY

MODE

MEMORY

PROGRAMMABLE

DATA ADDRESS

GENERATORS

I/O

AND

FLAGS

EXTERNAL

ADDRESS

BUS

16k

؋

24

PROGRAM

MEMORY

16k

؋

16

DATA

MEMORY

PROGRAM

SEQUENCER

DAG 1 DAG 2

T he EZ-KIT Lite is a hardware/software kit offering a complete

development environment for the entire ADSP-21xx family: an

ADSP-218x based evaluation board with PC monitor software

plus Assembler, Linker, Simulator and PROM Splitter software.

T he ADSP-21xx EZ-KIT Lite is a low cost, easy to use hard-

ware platform on which you can quickly get started with your

DSP software design. T he EZ-KIT Lite includes the following

features:

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

ALU SHIFTER

SERIAL PORTS

SPORT 0 SPORT 1

TIMER

INTERNAL

DMA

PORT

MAC

• 33 MHz ADSP-2181

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

• Full 16-bit Stereo Audio I/O with AD1847 SoundPort^®* Codec

• RS-232 Interface to PC with Windows^®3.1 Control Software

• Stand-Alone Operation with Socketed EPROM

• EZ-ICE^®*Connector for Emulator Control

• DSP Demo Programs

Figure 1. Block Diagram

Figure 1 is an overall block diagram of the ADSP-2185. T he

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. T he

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. T he ALU per-

forms a standard set of arithmetic and logic operations; division

primitives are also supported. T he MAC performs single-cycle

multiply, multiply/add and multiply/subtract operations with 40

bits of accumulation. T he shifter performs logical and arith-

metic shifts, normalization, denormalization and derive expo-

nent operations.

T he ADSP-218x EZ-ICE^®* Emulator aids in the hardware

debugging of an ADSP-2185 system. T he emulator consists of

hardware, host computer resident software, and the target board

connector. T he ADSP-2185 integrates on-chip emulation sup-

port with a 14-pin ICE-PORT ™* interface. T his interface pro-

vides a simpler target board connection that requires fewer

mechanical clearance considerations than other ADSP-2100

Family EZ-ICE^®*s. The ADSP-2185 device need not be removed

from the target system when using the EZ-ICE^®*, nor are any

adapters needed. Due to the small footprint of the EZ-ICE^®*

connector, emulation can be supported in final board designs.

T he shifter can be used to efficiently implement numeric

format control including multiword and block floating-point

representations.

*All trademarks are the property of their respective holders.

*EZ-ICE and SoundPORT are registered trademarks of Analog Devices, Inc.

REV. 0

–2–

ADSP-2185

wide variety of framed or frameless data transmit and receive

modes of operation.

T he internal result (R) bus connects the computational units so

the output of any unit may be the input of any unit on the next

cycle.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. T he sequencer supports conditional jumps, sub-

routine calls and returns in a single cycle. With internal loop

counters and loop stacks, the ADSP-2185 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain loops.

T he ADSP-2185 provides up to 13 general-purpose flag pins.

T he data input and output pins on SPORT 1 can be alternatively

configured as an input flag and an output flag. In addition,

eight flags are programmable as inputs or outputs, and three

flags are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (T COUNT ) decrements every n processor

cycle, where n is a scaling value stored in an 8-bit register

(T SCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (T PERIOD).

T wo data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from data memory and pro-

gram memory. Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four pos-

sible modify registers. A length value may be associated with

each pointer to implement automatic modulo addressing for

circular buffers.

Ser ial P or ts

T he ADSP-2185 incorporates two complete synchronous serial

ports (SPORT 0 and SPORT 1) for serial communications and

multiprocessor communication.

Efficient data transfer is achieved with the use of five internal

buses:

Here is a brief list of the capabilities of the ADSP-2185 SPORTs.

For additional information on Serial Ports, refer to the ADSP-

2100 Family User’s Manual.

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

• SPORT s are bidirectional and have a separate, double-buff-

ered transmit and receive section.

• SPORT s can use an external serial clock or generate their own

serial clock internally.

T he two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

• SPORT s have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulse widths and timings.

Program memory can store both instructions and data, permit-

ting the ADSP-2185 to fetch two operands in a single cycle, one

from program memory and one from data memory. T he ADSP-

2185 can fetch an operand from program memory and the next

instruction in the same cycle.

• SPORT s support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCIT T recommendation G.711.

When configured in host mode, the ADSP-2185 has a 16-bit

Internal DMA port (IDMA port) for connection to external

systems. T he IDMA port is made up of 16 data/address pins

and five control pins. T he IDMA port provides transparent,

direct access to the DSPs on-chip program and data RAM.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORT s can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). T he BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

• SPORT 0 has a multichannel interface to selectively receive

and transmit a 24 or 32 word, time-division multiplexed,

serial bitstream.

• SPORT 1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he

internally generated serial clock may still be used in this con-

figuration.

T he byte memory and I/O memory space interface supports

slow memories and I/O memory-mapped peripherals with

programmable wait state generation. External devices can

gain control of external buses with bus request/grant signals

(BR, BGH and BG). One execution mode (Go Mode) allows

the ADSP-2185 to continue running from on-chip memory.

Normal execution mode requires the processor to halt while

buses are granted.

P IN D ESCRIP TIO NS

T he ADSP-2185 will be available in a 100-lead T QFP package.

In order to maintain maximum functionality and reduce pack-

age size and pin count, some serial port, programmable flag,

interrupt and external bus pins have dual, multiplexed function-

ality. T he external bus pins are configured during RESET only,

while serial port pins are software configurable during program

execution. Flag and interrupt functionality is retained concur-

rently on multiplexed pins. In cases where pin functionality is

reconfigurable, the default state is shown in plain text; alternate

functionality is shown in italics.

T he ADSP-2185 can respond to eleven interrupts. T here can be

up to six external interrupts (one edge-sensitive, two level-sensitive

and three configurable) and seven internal interrupts generated

by the timer, the serial ports (SPORT s), the Byte DMA port

and the power-down circuitry. T here is also a master RESET

signal. T he two serial ports provide a complete synchronous

serial interface with optional companding in hardware and a

REV. 0

–3–

ADSP-2185

Com m on-Mode P ins

Mem or y Inter face P ins

T he ADSP-2185 processor can be used in one of two modes,

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode,

which allows IDMA operation with limited external addressing

capabilities. T he operating mode is determined by the state of

the Mode C pin during RESET and cannot be changed while

the processor is running.

#

of

Input/

O ut-

P in

Nam e(s)

P ins put

Function

RESET

BR

1

I

Processor Reset Input

I

Bus Request Input

BG

O

I

Bus Grant Output

Full Mem or y Mode Pins (Mode C = 0)

BGH

DMS

PMS

IOMS

BMS

CMS

RD

Bus Grant Hung Output

Data Memory Select Output

Program Memory Select Output

Memory Select Output

#

of

Input/

P in Nam e P ins

O utput Function

Byte Memory Select Output

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

A13:0

14

24

O

Address Output Pins for Pro-

gram, Data, Byte and I/O

Spaces

D23:0

I/O

Data I/O Pins for Program,

Data, Byte and I/O Spaces

(8 MSBs Are Also Used as

Byte Memory Addresses)

WR

IRQ2/

Edge- or Level-Sensitive

Interrupt Request¹

PF7

I/O

Programmable I/O Pin

IRQL0/

PF5

1

I

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Host Mode Pins (Mode C = 1)

I/O

#

IRQL1/

PF6

I

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

of

Input/

O utput Function

I/O

P in Nam e P ins

IRQE/

PF4

I

Edge-Sensitive Interrupt Requests¹

Programmable I/O Pin

I/O

IAD15:0

A0

16

1

I/O

O

IDMA Port Address/Data Bus

PF3

1

I/O

I

Programmable I/O Pin

Address Pin for External I/O,

Program, Data, or Byte Access

Mode C/

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

D23:8

16

I/O

Data I/O Pins for Program,

Data Byte and I/O Spaces

PF2

I/O

IWR

IRD

IAL

1

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

Mode B/

PF1

1

I

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

I

I/O

IS

I

IACK

O

IDMA Port Acknowledge

Mode A/

PF0

I

Mode Select Input—Checked

only During RESET

Programmable I/O Pin During

Normal Operation

In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS, and IOMS signals

I/O

Setting Mem or y Mode

CLKIN, XTAL 2

I

Clock or Quartz Crystal Input

Processor Clock Output

Serial Port I/O Pins

Memory Mode selection for the ADSP-2185 is made during

chip reset through the use of the Mode C pin. T his pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. T he two methods for selecting the

value of Mode C are active and passive.

CLKOUT

SPORT 0

1

5

O

I/O

SPORT 1/

IRQ1:0

FI, FO

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts,

Flag In, Flag Out²

Passive configuration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. T o minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order of

100 kΩ, can be used. T his value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as a

programmable flag output without undue strain on the processor’s

output driver. For minimum power consumption during

power-down, reconfigure PF2 to be an input as the pull-up or

pull-down will hold the pin in a known state and will not switch.

PWD

1

3

I

Power-Down Control Input

Power-Down Control Output

Output Flags

PWDACK

FL0, FL1, FL2

O

I

VDD and GND 16

Power and Ground

EZ-Port

9

I/O

For Emulation Use

NOT ES

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to

enable the corresponding interrupts, the DSP will vector to the appropriate

interrupt vector address when the pin is asserted, either by external devices or

set as a programmable flag.

Active configuration involves the use of a three-stateable exter-

nal driver connected to the Mode C pin. A driver’s output en-

able should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). After

²SPORT configuration determined by the DSP System Control Register. Soft-

ware configurable.

REV. 0

–4–

ADSP-2185

RESET is deasserted, the driver should three-state, thus allow-

ing full use of the PF2 pin as either an input or output.

T he IFC register is a write-only register used to force and clear

interrupts.

T o minimize power consumption during power-down, configure

the programmable flag as an output when connected to a three-

stated buffer. T his ensures that the pin will be held at a constant

level and not oscillate should the three-state driver’s level hover

around the logic switching point.

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling. The stacks are twelve

levels deep to allow interrupt, loop and subroutine nesting.

T he following instructions allow global enable or disable servic-

ing of the interrupts (including power-down), regardless of the

state of IMASK. Disabling the interrupts does not affect serial

port autobuffering or DMA.

Inter r upts

T he interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

T he ADSP-2185 provides four dedicated external interrupt

input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the

PF7:4 pins). In addition, SPORT 1 may be reconfigured for

IRQ0, IRQ1, FLAG_IN and FLAG_OUT , for a total of six

external interrupts. T he ADSP-2185 also supports internal

interrupts from the timer, the byte DMA port, the two serial

ports, software and the power-down control circuit. T he inter-

rupt levels are internally prioritized and individually maskable

(except power-down and reset). T he IRQ2, IRQ0 and IRQ1

input pins can be programmed to be either level- or edge-sensitive.

IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.

T he priorities and vector addresses of all interrupts are shown in

T able I.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LO W P O WER O P ERATIO N

T he ADSP-2185 has three low power modes that significantly

reduce the power dissipation when the device operates under

standby conditions. T hese modes are:

• Power-Down

• Idle

• Slow Idle

T he CLKOUT pin may also be disabled to reduce external

power dissipation.

Table I. Interrupt P riority & Interrupt Vector Addresses

P ower -D own

Source O f Interrupt

Interrupt Vector Address (Hex)

T he ADSP-2185 processor has a low power feature that lets the

processor enter a very low power dormant state through hard-

ware or software control. Here is a brief list of power-down

features. Refer to the ADSP-2100 Family User’s Manual, “System

Interface” chapter, for detailed information about the power-

down feature.

Reset (or Power-Up with

PUCR = 1)

0000 (Highest Priority)

Power-down (Nonmaskable) 002C

IRQ2

0004

0008

000C

0010

0014

0018

001C

IRQL1

•

Quick recovery from power-down. T he processor begins

executing instructions in as few as 100 CLKIN cycles.

IRQL0

SPORT 0 T ransmit

SPORT 0 Receive

IRQE

•

Support for an externally generated T T L or CMOS proces-

sor clock. T he external clock can continue running during

power-down without affecting the lowest power rating and

100 CLKIN cycle recovery.

BDMA Interrupt

•

Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits approxi-

mately 4096 CLKIN cycles for the crystal oscillator to start

or stabilize), and letting the oscillator run to allow 100 CLKIN

cycle start-up.

SPORT 1 T ransmit or IRQ1 0020

SPORT 1 Receive or IRQ0

0024

T imer

0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority

interrupts taking precedence, or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. T he power-down interrupt is nonmaskable.

•

Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit.

Interrupt support allows an unlimited number of instructions

to be executed before optionally powering down. T he power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

T he ADSP-2185 masks all interrupts for one instruction cycle

following the execution of an instruction that modifies the

IMASK register. T his does not affect serial port autobuffering

or DMA transfers.

•

Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

T he interrupt control register, ICNT L, controls interrupt nest-

ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. T he IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. T he

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

•

T he RESET pin also can be used to terminate power-down.

Power-down acknowledge pin indicates when the processor

has entered power-down.

REV. 0

–5–

ADSP-2185

HOST MEMORY MODE

ADSP-2185

Idle

When the ADSP-2185 is in the Idle Mode, the processor waits

indefinitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then

continues with the instruction following the IDLE instruction.

In Idle mode IDMA, BDMA and autobuffer cycle steals still

occur.

A

14

13-0

1/2x CLOCK

OR

CRYSTAL

CLKIN

ADDR13-0

XTAL

D

A0-A21

23-16

FL0-2

BYTE

D

24

15-8

PF3

MEMORY

DATA

DATA23-0

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

CS

BMS

A

10-0

Slow Idle

ADDR

DATA

D

MODE C/PF2

MODE B/PF1

MODE A/PF0

23-8

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

T he IDLE instruction is enhanced on the ADSP-2185 to let the

processor’s internal clock signal be slowed, further reducing

power consumption. T he reduced clock frequency, a program-

mable fraction of the normal clock rate, is specified by a select-

able divisor given in the IDLE instruction. T he format of the

instruction is

CS

IOMS

A

13-0

ADDR

DATA

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

OVERLAY

MEMORY

D

23-0

SERIAL

DEVICE

TWO 8K

PM SEGMENTS

PMS

DMS

CMS

TWO 8K

DM SEGMENTS

IDLE (n);

SPORT0

SCLK0

RFS0

TFS0

DT0

BR

BG

BGH

SERIAL

DEVICE

where n = 16, 32, 64 or 128. T his instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

such as SCLK, CLKOUT and timer clock, are reduced by the

same ratio. T he default form of the instruction, when no clock

divisor is given, is the standard IDLE instruction.

PWD

PWDACK

DR0

HOST MEMORY MODE

ADSP-2185

1/2x CLOCK

OR

CRYSTAL

CLKIN

1

A0

XTAL

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to in-

coming interrupts. T he one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the ADSP-2185 will remain in the idle

state for up to a maximum of n processor cycles (n = 16, 32, 64

or 128) before resuming normal operation.

FL0-2

PF3

16

DATA23-0

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

BMS

MODE C/PF2

MODE B/PF1

MODE A/PF0

IOMS

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

SERIAL

DEVICE

PMS

DMS

CMS

SPORT0

SCLK0

RFS0

TFS0

DT0

SERIAL

DEVICE

BR

BG

BGH

DR0

IDMA PORT

PWD

PWDACK

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

SYSTEM

INTERFACE

OR

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the

ADSP-2185, two serial devices, a byte-wide EPROM and optional

external program and data overlay memories (mode selectable).

Programmable wait state generation allows the processor to

easily connect to slow peripheral devices. T he ADSP-2185 also

provides four external interrupts and two serial ports or six

external interrupts and one serial port.

µCONTROLLER

16

IAD15-0

Figure 2. Basic System Configuration

Clock Signals

T he ADSP-2185 can be clocked by either a crystal or a T T L-

compatible clock signal.

Host Memory mode allows access to the full external data bus,

but limits addressing to a single address bit (A0). Additional

system peripherals can be added in this mode through the use of

external hardware to generate and latch address signals.

T he CLKIN input cannot be halted, changed during operation

or operated below the specified frequency during normal opera-

tion. T he only exception is while the processor is in the power-

down state. For additional information, refer to Chapter 9,

ADSP-2100 Family User’s Manual, for detailed information on

this power-down feature.

If an external clock is used, it should be a T T L-compatible

signal running at half the instruction rate. T he signal is con-

nected to the processor’s CLKIN input. When an external clock

is used, the XT AL input must be left unconnected.

REV. 0

–6–

ADSP-2185

T he ADSP-2185 uses an input clock with a frequency equal to

half the instruction rate; a 16.67 MHz input clock yields a 30 ns

processor cycle (which is equivalent to 33 MHz). Normally,

instructions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

MEMO RY ARCH ITECTURE

T he ADSP-2185 provides a variety of memory and peripheral

interface options. The key functional groups are Program Memory,

Data Memory, Byte Memory and I/O.

P r ogr am Mem or y is a 24-bit-wide space for storing both

instruction opcodes and data. T he ADSP-2185 has 16K words

of Program Memory RAM on chip, and the capability of access-

ing up to two 8K external memory overlay spaces using the

external data bus. Both an instruction opcode and a data value

can be read from on-chip program memory in a single cycle.

Because the ADSP-2185 includes an on-chip oscillator circuit,

an external crystal may be used. T he crystal should be con-

nected across the CLKIN and XT AL pins, with two capacitors

connected as shown in Figure 3. Capacitor values are dependent

on crystal type and should be specified by the crystal manufac-

turer. A parallel-resonant, fundamental frequency, microproces-

sor-grade crystal should be used.

D ata Mem or y is a 16-bit-wide space used for the storage of

data variables and for memory-mapped control registers. T he

ADSP-2185 has 16K words on Data Memory RAM on chip,

consisting of 16,352 user-accessible locations and 32 memory-

mapped registers. Support also exists for up to two 8K external

memory overlay spaces through the external data bus.

A clock output (CLKOUT ) signal is generated by the proces-

sor at the processor’s cycle rate. T his can be enabled and

disabled by the CLKODIS bit in the SPORT 0 Autobuffer

Control Register.

Byte Mem or y (Full Mem or y Mode) provides access to an

8-bit wide memory space through the Byte DMA (BDMA) port.

T he Byte Memory interface provides access to 4 MBytes of

memory by utilizing eight data lines as additional address lines.

T his gives the BDMA Port an effective 22-bit address range. On

power-up, the DSP can automatically load bootstrap code from

byte memory.

XTAL

CLKIN

CLKOUT

DSP

I/O Space (Full Mem or y Mode) allows access to 2048 loca-

tions of 16-bit-wide data. It is intended to be used to communi-

cate with parallel peripheral devices such as data converters and

external registers or latches.

Figure 3. External Crystal Connections

Reset

T he RESET signal initiates a master reset of the ADSP-2185.

T he RESET signal must be asserted during the power-up

sequence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

P r ogr am Mem or y

T he ADSP-2185 contains a 16K × 24 on-chip program RAM.

T he on-chip program memory is designed to allow up to two

accesses each cycle so that all operations can complete in a

single cycle. In addition, the ADSP-2185 allows the use of 8K

external memory overlays.

T he power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis

applied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 CLKIN cycles ensures that the PLL has locked, but does

not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

T he program memory space organization is controlled by the

Mode B pin and the PMOVLAY register. Normally, the ADSP-

2185 is configured with Mode B = 0 and program memory

organized as shown in Figure 4.

PROGRAM MEMORY

ADDRESS

0x3FFF

8K INTERNAL

(PMOVLAY = 0,

MODE B = 0)

OR

mum pulse width specification, t_RSP

.

EXTERNAL 8K

(PMOVLAY = 1 or 2,

MODE B = 0)

T he RESET input contains some hysteresis; however, if you use

an RC circuit to generate your RESET signal, the use of an

external Schmidt trigger is recommended.

0x2000

0x1FFF

T he master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MST AT

register. When RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading

sequence is performed. T he first instruction is fetched from

on-chip program memory location 0x0000 once boot loading

completes.

8K INTERNAL

0x0000

Figure 4. Program Mem ory (Mode B = 0)

T here are 16K words of memory accessible internally when the

PMOVLAY register is set to 0. When PMOVLAY is set to some-

thing other than 0, external accesses occur at addresses 0x2000

through 0x3FFF. T he external address is generated as shown in

T able II.

REV. 0

–7–

ADSP-2185

Table II.

T here are 16,352 words of memory accessible internally when

the DMOVLAY register is set to 0. When DMOVLAY is set to

something other than 0, external accesses occur at addresses

0x0000 through 0x1FFF. T he external address is generated as

shown in T able III.

P MO VLAY Mem ory A13

A12:0

0

1

Internal

Not Applicable Not Applicable

External

Overlay 1

0

1

13 LSBs of Address

Between 0x2000

and 0x3FFF

Table III.

D MO VLAY Mem ory A13

A12:0

2

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

0

1

Internal

Not Applicable Not Applicable

13 LSBs of Address

External

Overlay 1

0

Between 0x2000

and 0x3FFF

T his organization provides for two external 8K overlay segments

using only the normal 14 address bits. T his allows for simple

program overlays using one of the two external segments in

place of the on-chip memory. Care must be taken in using this

overlay space in that the processor core (i.e., the sequencer)

does not take into account the PMOVLAY register value. For

example, if a loop operation was occurring on one of the exter-

nal overlays and the program changes to another external over-

lay or internal memory, an incorrect loop operation could occur.

In addition, care must be taken in interrupt service routines as

the overlay registers are not automatically saved and restored on

the processor mode stack.

2

External

Overlay 2

13 LSBs of Address

Between 0x2000

and 0x3FFF

1

T his organization allows for two external 8K overlays using only

the normal 14 address bits. All internal accesses complete in one

cycle. Accesses to external memory are timed using the wait

states specified by the DWAIT register.

I/O Space (Full Mem or y Mode)

T he ADSP-2185 supports an additional external memory space

called I/O space. T his space is designed to support simple con-

nections to peripherals or to bus interface ASIC data registers.

I/O space supports 2048 locations. T he lower eleven bits of the

external address bus are used; the upper three bits are unde-

fined. T wo instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. T he I/O space also has four dedicated 3-bit wait state

registers, IOWAIT 0-3, which specify up to seven wait states to

be automatically generated for each of four regions. T he wait

states act on address ranges as shown in T able IV.

When Mode B = 1, booting is disabled and overlay memory is

disabled (PMOVLAY must be 0). Figure 5 shows the memory

map in this configuration.

PROGRAM MEMORY

ADDRESS

0x3FFF

INTERNAL 8K

(PMOVLAY = 0,

MODE B = 1)

0x2000

0x1FFF

8K EXTERNAL

Table IV.

0x0000

Address Range

Wait State Register

Figure 5. Program Mem ory (Mode B = 1)

D ata Mem or y

T he ADSP-2185 has 16,352 16-bit words of internal data

memory. In addition, the ADSP-2185 allows the use of 8K

external memory overlays. Figure 6 shows the organization of

the data memory.

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT 0

IOWAIT 1

IOWAIT 2

IOWAIT 3

Com posite Mem or y Select (CMS)

T he ADSP-2185 has a programmable memory select signal that

is useful for generating memory select signals for memories

mapped to more than one space. T he CMS signal is generated

to have the same timing as each of the individual memory select

signals (PMS, DMS, BMS, IOMS), but can combine their

functionality.

DATA MEMORY

ADDRESS

0x3FFF

32 MEMORY–

MAPPED REGISTERS

0x3FEO

0x3FDF

INTERNAL

8160 WORDS

When set, each bit in the CMSSEL register causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip select

of the memory and use either DMS or PMS as the additional

address bit.

0x2000

0x1FFF

8K INTERNAL

(DMOVLAY = 0)

OR

EXTERNAL 8K

(DMOVLAY = 1, 2)

0x0000

T he CMS pin functions as the other memory select signals, with

the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

Figure 6. Data Mem ory

REV. 0

–8–

ADSP-2185

selected memory select signal. All enable bits, except the BMS

bit, default to 1 at reset,

create a destination word, it is transferred to or from on-chip

memory. T he transfer takes one DSP cycle. DSP accesses to

external memory have priority over BDMA byte memory

accesses.

Byte Mem or y

T he byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. T he byte memory space

consists of 256 pages, each of which is 16K × 8.

T he BDMA Context Reset bit (BCR) controls whether the

processor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor and to start execution at address 0

when the BDMA accesses have completed.

T he byte memory space on the ADSP-2185 supports read and

write operations as well as four different data formats. T he byte

memory uses data bits 15:8 for data. T he byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

T his allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

Inter nal Mem or y D MA P or t (ID MA P or t; H ost Mem or y

Mode)

T he IDMA Port provides an efficient means of communication

between a host system and the ADSP-2185. T he port is used to

access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. T he IDMA

port cannot, however, be used to write to the DSP’s memory-

mapped control registers.

Byte Mem or y D MA (BD MA, Full Mem or y Mode)

T he Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

T he BDMA circuit is able to access the byte memory space

while the processor is operating normally and steals only one

DSP cycle per 8-, 16- or 24-bit word transferred.

T he IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. T he IDMA port is com-

pletely asynchronous and can be written to while the ADSP-

2185 is operating at full speed.

T he BDMA circuit supports four different data formats, which

are selected by the BT YPE register field. T he appropriate num-

ber of 8-bit accesses are done from the byte memory space to

build the word size selected. T able V shows the data formats

supported by the BDMA circuit.

T he DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device

can therefore access a block of sequentially addressed memory

by specifying only the starting address of the block. T his in-

creases throughput as the address does not have to be sent for

each memory access.

Table V.

Internal

BTYP E

Mem ory Space

Word Size

Alignm ent

IDMA Port access occurs in two phases. T he first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. T he address specifies an on-chip memory

location, the destination type specifies whether it is a DM or

PM access. T he falling edge of the address latch signal latches

this value into the IDMAA register.

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

8

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address for

the on-chip memory involved with the transfer. The 14-bit BEAD

register specifies the starting address for the external byte memory

space. The 8-bit BMPAGE register specifies the starting page for

the external byte memory space. T he BDIR register field selects

the direction of the transfer. Finally the 14-bit BWCOUNT

register specifies the number of DSP words to transfer and

initiates the BDMA circuit transfers.

Once the address is stored, data can then be either read from or

written to the ADSP-2185’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2185 that a particular

transaction is required. In either case, there is a one-processor-

cycle delay for synchronization. T he memory access consumes

one additional processor cycle.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

T he BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. T he BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

T hrough the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Bootstr ap Loading (Booting)

T he ADSP-2185 has two mechanisms to allow automatic load-

ing of the internal program memory after reset. T he method for

booting is controlled by the Mode A, B and C configuration bits

as shown in T able VI. T hese four states can be compressed into

two-state bits by allowing an IDMA boot with Mode C = 1.

However, three bits are used to ensure future compatibility with

parts containing internal program memory ROM.

T he source or destination of a BDMA transfer will always be

on-chip program or data memory, regardless of the values of

Mode B, PMOVLAY or DMOVLAY.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT . T hese accesses continue until the

count reaches zero. When enough accesses have occurred to

BD MA Booting

When the MODE pins specify BDMA booting, the ADSP-2185

initiates a BDMA boot sequence when RESET is released.

REV. 0

–9–

ADSP-2185

Table VI. Boot Sum m ary Table

ID MA P or t Booting

T he ADSP-2185 can also boot programs through its Internal

DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the

ADSP-2185 boots from the IDMA port. IDMA feature can load

as much on-chip memory as desired. Program execution is held

off until on-chip program memory location 0 is written to.

MO D E C MO D E B MO D E A Booting Method

0

BDMA feature is used to load

the first 32 program memory

words from the byte memory

space. Program execution is

held off until all 32 words

have been loaded. Chip is

configured in Full Memory

Mode.

T he ADSP-2100 Family development software (Revision 5.02

and later) can generate IDMA compatible boot code.

Bus Request & Bus Gr ant

T he ADSP-2185 can relinquish control of the data and address

buses to an external device. When the external device requires

access to memory, it asserts the bus request (BR) signal. If the

ADSP-2185 is not performing an external memory access, it

responds to the active BR input in the following processor cycle

by:

0

1

0

No Automatic boot opera-

tions occur. Program execu-

tion starts at external memory

location 0. Chip is config-

ured in Full Memory Mode.

BDMA can still be used but

the processor does not auto-

matically use or wait for these

operations.

• T hree-stating the data and address buses and the PMS, DMS,

BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal and

• Halting program execution.

If Go Mode is enabled, the ADSP-2185 will not halt program

execution until it encounters an instruction that requires an

external memory access.

1

0

BDMA feature is used to load

the first 32 program memory

words from the byte memory

space. Program execution is

held off until all 32 words

have been loaded. Chip is

configured in Host Mode.

Additional interface hardware

is required.

If the ADSP-2185 is performing an external memory access

when the external device asserts the BR signal, then it will not

three-state the memory interfaces or assert the BG signal until

the processor cycle after the access completes. T he instruction

does not need to be completed when the bus is granted. If a

single instruction requires two external memory accesses, the

bus will be granted between the two accesses.

1

0

1

IDMA feature is used to load

any internal memory as de-

sired. Program execution is

held off until internal pro-

gram memory location 0 is

written to. Chip is configured

in Host Mode.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point where it stopped.

T he bus request feature operates at all times, including when

the processor is booting and when RESET is active.

T he BGH pin is asserted when the ADSP-2185 is ready to

execute an instruction but is stopped because the external bus is

already granted to another device. T he other device can release

the bus by deasserting bus request. Once the bus is released, the

ADSP-2185 deasserts BG and BGH and executes the external

memory access.

The BDMA interface is set up during reset to the following de-

faults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0; the BT YPE register is

set to 0 to specify program memory 24 bit words; and the

BWCOUNT register is set to 32. T his causes 32 words of on-

chip program memory to be loaded from byte memory. T hese

32 words are used to set up the BDMA to load in the remaining

program code. T he BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at address 0.

Flag I/O P ins

The ADSP-2185 has eight general purpose programmable input/

output flag pins. T hey are controlled by two memory mapped

registers. T he PFT YPE register determines the direction,

1 = output and 0 = input. T he PFDAT A register is used to read

and write the values on the pins. Data being read from a pin

configured as an input is synchronized to the ADSP-2185’s

clock. Bits that are programmed as outputs will read the value

being output. T he PF pins default to input during reset.

T he ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space compatible boot code.

T he IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in H ost Mode, the ad-

dresses to boot memory must be constructed externally to the

ADSP-2185. T he only memory address bit provided by the

processor is A0.

In addition to the programmable flags, the ADSP-2185 has five

fixed-mode flags, FLAG_IN, FLAG_OUT , FL0, FL1 and

FL2. FL0-FL2 are dedicated output flags. FLAG_IN and

FLAG_OUT are available as an alternate configuration of

SPORT 1.

Note: Pins PF0, PF1 and PF2 are also used for device configu-

ration during reset.

REV. 0

–10–

ADSP-2185

BIASED RO UND ING

I/O Space Instr uctions

A mode is available on the ADSP-2185 to allow biased round-

ing in addition to the normal unbiased rounding. When the

BIASRND bit is set to 0, the normal unbiased rounding opera-

tions occur. When the BIASRND bit is set to 1, biased round-

ing occurs instead of the normal unbiased rounding. When

operating in biased rounding mode all rounding operations with

MR0 set to 0x8000 will round up, rather than only rounding up

odd MR1 values.

T he instructions used to access the ADSP-2185’s I/O memory

space are as follows:

Syntax: IO(addr) = dreg

dreg = IO(addr);

where addr is an address value between 0 and 2047 and dreg is

any of the 16 data registers.

Exam ples: IO(23) = AR0;

AR1 = IO(17);

For example:

D escr iption: T he I/O space read and write instructions move

data between the data registers and the I/O

memory space.

Table VII.

MR Value

Biased

Unbiased

Before RND

RND Result

D ESIGNING AN EZ-ICE ^®*-CO MP ATIBLE SYSTEM

T he ADSP-2185 has on-chip emulation support and an

ICE-Port™*, a special set of pins that interface to the EZ-ICE^®*.

T hese features allow in-circuit emulation without replacing the

target system processor by using only a 14-pin connection from

the target system to the EZ-ICE^®*. T arget systems must have a

14-pin connector to accept the EZ-ICE^®*’s in-circuit probe, a

14-pin plug. See the ADSP-2100 Family EZ-Tools data sheet for

complete information on ICE products.

00-0000-8000

00-0001-8000

00-0000-8001

00-0001-8001

00-0000-7FFF

00-0001-7FFF

00-0001-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

00-0000-8000

00-0002-8000

00-0001-8001

00-0002-8001

00-0000-7FFF

00-0001-7FFF

T his mode only has an effect when the MR0 register contains

0x8000; all other rounding operations work normally. T his

mode allows more efficient implementation of bit-specified

algorithms that use biased rounding, for example the GSM

speech compression routines. Unbiased rounding is preferred

for most algorithms.

T he ICE-Port™* interface consists of the following ADSP-2185

pins:

EBR

EBG

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

EE

Note: BIASRND bit is Bit 12 of the SPORT 0 Autobuffer Con-

trol register.

Instr uction Set D escr iption

T he ADSP-2185 assembly language instruction set has an alge-

braic syntax that was designed for ease of coding and readabil-

ity. T he assembly language, which takes full advantage of the

processor’s unique architecture, offers the following benefits:

These ADSP-2185 pins must be connected only to the EZ-ICE^®*

connector in the target system. T hese pins have no function

except during emulation, and do not require pull-up or pull-down

resistors. T he traces for these signals between the ADSP-2185

and the connector must be kept as short as possible, no longer

than three inches.

•

T he algebraic syntax eliminates the need to remember cryptic

assembler mnemonics. For example, a typical arithmetic add

instruction, such as AR = AX0 + AY0, resembles a simple

equation.

•

Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

T he following pins are also used by the EZ-ICE^®*:

BR

BG

RESET

GND

T he syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be relo-

cated to use on-chip memory and conform to the ADSP-

2185’s interrupt vector and reset vector map.

T he EZ-ICE^®* uses the EE (emulator enable) signal to take

control of the ADSP-2185 in the target system. T his causes the

processor to use its ERESET, EBR and EBG pins instead of the

RESET, BR and BG pins. T he BG output is three-stated.

T hese signals do not need to be jumper-isolated in your system.

T he EZ-ICE^®* connects to your target system via a ribbon cable

and a 14-pin female plug. T he female plug is plugged onto the

14-pin connector (a pin strip header) on the target board.

•

Sixteen condition codes are available. For conditional jump,

call, return or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

REV. 0

–11–

ADSP-2185

Tar get Boar d Connector for EZ-ICE ^®* P r obe

Note: If your target does not meet the worst case chip specifica-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. Depend-

ing on the severity of the specification violation, you may have

trouble manufacturing your system as DSP components statisti-

cally vary in switching characteristic and timing requirements

within published limits.

T he EZ-ICE^®* connector (a standard pin strip header) is shown

in Figure 7. You must add this connector to your target board

design if you intend to use the EZ-ICE^®*. Be sure to allow

enough room in your system to fit the EZ-ICE^®* probe onto the

14-pin connector.

Restriction: All memory strobe signals on the ADSP-2185 (RD,

WR, PMS, DMS, BMS, CMS and IOMS) used in your target

system must have 10 kΩ pull-up resistors connected when the

EZ-ICE^®* is being used. T he pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE^®* debugging sessions. T hese resistors may be removed

at your option when the EZ-ICE^®* is not being used.

1

3

5

2

4

BG

GND

EBG

BR

6

EBR

EINT

ELIN

ECLK

EMS

7

×

8

KEY (NO PIN)

9

10

12

14

Tar get System Inter face Signals

ELOUT

EE

When the EZ-ICE^®* board is installed, the performance on

some system signals change. Design your system to be compat-

ible with the following system interface signal changes intro-

duced by the EZ-ICE^®* board:

11

13

RESET

ERESET

• EZ-ICE^®* emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the RESET

signal.

TOP VIEW

Figure 7. Target Board Connector for EZ-ICE^®*

• EZ-ICE^®* emulation introduces an 8 ns propagation delay

T he 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. T he pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

ing should be 0.1 × 0.1 inches. T he pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE^®*

probe plug. Pin strip headers are available from vendors such as

3M, McKenzie and Samtec.

between your target circuitry and the DSP on the BR signal.

• EZ-ICE^®* emulation ignores RESET and BR when single-

stepping.

• EZ-ICE^®* emulation ignores RESET and BR when in Emu-

lator Space (DSP halted).

• EZ-ICE^®* emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (BG) is asserted

by the EZ-ICE^®* board’s DSP.

Tar get Mem or y Inter face

For your target system to be compatible with the EZ-ICE^®*

emulator, it must comply with the memory interface guidelines

listed below.

P M, D M, BM, IO M and CM

Design your Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM) and Composite Memory

(CM) external interfaces to comply with worst case device tim-

ing requirements and switching characteristics as specified in

this DSP’s data sheet. The performance of the EZ-ICE^®*may

approach published worst case specification for some memory

access timing requirements and switching characteristics.

REV. 0

–12–

ADSP-2185

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

P aram eter

Min

Max

Min

Max

Unit

V_DD

T _AMB

4.5

0

5.5

+70

4.5

–40

5.5

+85

V

°C

ELECTRICAL CHARACTERISTICS

K/B Grades

Typ

P aram eter

Test Conditions

Min

Max

Unit

V_IH

V_IL

V_OH

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ V_DD= max

@ V_DD= min

I_OH= –0.5 mA

@ V_DD= min

I_OH= –100 µA⁶

@ V_DD= min

I_OL= 2 mA

@ V_DD= max

V_IN= V_DDmax

@ V_DD= max

V_IN= 0 V

2.0

2.2

V

0.8

2.4

V

V_DD– 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

0.4

10

V

µA

I_IL

Lo-Level Input Current³

I_OZH

I_OZL

T hree-State Leakage Current⁷

@ V_DD= max

V_IN= V_DDmax⁸

@ V_DD= max

V_IN= 0 V⁸

µA

mA

I_DD

Supply Current (Idle)⁹

@ V_DD= 5.0

T_AMB= +25°C

t_CK= 30 ns¹¹

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= +25°C

@ V_IN= 2.5 V,

f_IN= 1.0 MHz,

T_AMB= +25°C

12.4

63

Supply Current (Dynamic)¹⁰

mA

pF

C_I

Input Pin Capacitance^{3, 6, 12}

8

C_O

Output Pin Capacitance^{6, 7, 12, 13}

pF

NOT ES

¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, T FS0, T FS1, A1–A13, PF0-PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT 0, DT 1, CLKOUT , FL2-0, BGH.

⁵Although specified for T T L outputs, all ADSP-2185 outputs are CMOS-compatible and will drive to V _DDand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷T hree-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT 0, DT 1, SCLK0, SCLK1, T FS0, T FS1, RFS0, RSF1, PF0–PF7.

⁸0 V on BR, CLKIN Inactive.

⁹Idle refers to ADSP-2185 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V _DDor GND.

¹⁰IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

and type 6, and 20% are idle instructions.

11

V

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

IN

¹²Applies to T QFP package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0

–13–

ADSP-2185

ABSO LUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating T emperature Range (Ambient) . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . +280°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T hese are stress ratings only; functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ESD SENSITIVITY

T he ADSP-2185 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily

accumulate on the human body and equipment and can discharge without detection. Permanent

damage may occur to devices subjected to high energy electrostatic discharges.

WARNING!

T he ADSP-2185 features proprietary ESD protection circuitry to dissipate high energy discharges

(H uman Body Model) per method 3015 of MIL-ST D-883. Proper ESD precautions are recom-

mended to avoid performance degradation or loss of functionality. Unused devices must be stored in

conductive foam or shunts, and the foam should be discharged to the destination before devices are

removed.

ESD SENSITIVE DEVICE

ADSP-2185 TIMING PARAMETERS

GENERAL NO TES

MEMO RY TIMING SP ECIFICATIO NS

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results for

an individual device, the values given in this data sheet reflect

statistical variations and worst cases. Consequently, you cannot

meaningfully add up parameters to derive longer times.

T he table below shows common memory device specifications

and the corresponding ADSP-2185 timing parameters, for your

convenience.

Mem ory

AD SP -2185 Tim ing

D evice

Tim ing

P aram eter

Specification

P aram eter D efinition

TIMING NO TES

Address Setup to

Write Start

t_ASW

t_AW

A0-A13, xMS Setup

before WR Low

Switching characteristics specify how the processor changes its

signals. You have no control over this timing—circuitry external

to the processor must be designed for compatibility with these

signal characteristics. Switching characteristics tell you what the

processor will do in a given circumstance. You can also use

switching characteristics to ensure that any timing requirement

of a device connected to the processor (such as memory) is

satisfied.

Address Setup to

Write End

A0-A13, xMS Setup

before WR Deasserted

Address Hold T ime t_WRA

A0-A13, xMS Hold before

WR Low

Data Setup T ime

t_DW

Data Setup before WR

High

Data Hold T ime

t_DH

Data Hold after WR High

RD Low to Data Valid

T iming requirements apply to signals that are controlled by

circuitry external to the processor, such as the data input for a

read operation. T iming requirements guarantee that the proces-

sor operates correctly with other devices.

OE to Data Valid

t_RDD

Address Access T ime t_AA

A0-A13, xMS to Data

Valid

xMS = PMS, DMS, BMS, CMS, IOMS.

FREQ UENCY D EP END ENCY FO R TIMING

SP ECIFICATIO NS

t_CKis defined as 0.5t_CKI. T he ADSP-2185 uses an input clock

with a frequency equal to half the instruction rate: a 16.67 MHz

input clock (which is equivalent to 60 ns) yields a 30 ns proces-

sor cycle (equivalent to 33 MHz). t_CKvalues within the range of

0.5t_CKIperiod should be substituted for all relevant timing para-

meters to obtain the specification value.

Example: t_CKH= 0.5t_CK– 7 ns = 0.5 (30 ns) – 7 ns = 8 ns

REV. 0

–14–

ADSP-2185

2185 POWER, INTERNAL^{1, 3, 4}

ENVIRO NMENTAL CO ND ITIO NS

Ambient T emperature Rating:

440

420

396mW

400

380

360

340

320

300

280

260

240

220

200

T_AMB= T _CASE– (PD x θ_CA

)

V

= 5.5V

= 5.0V

DD

T_CASE= Case T emperature in °C

PD = Power Dissipation in W

θ_CA= T hermal Resistance (Case-to-Ambient)

349mW

277mW

315mW

243mW

θ

_JA= T hermal Resistance (Junction-to-Ambient)

V

DD

θ_JC= T hermal Resistance (Junction-to-Case)

= 4.5V

31

DD

P ackage

␪

JC

␪

CA

JA

214mW

29

T QFP

50°C/W

2°C/W

48°C/W

28

30

32

33

34

1/t_CK– MHz

POWER, IDLE^{1, 2}

95

90

P O WER D ISSIP ATIO N

T o determine total power dissipation in a specific application,

the following equation should be applied for each output:

83mW

85

80

V

= 5.5V

= 5.0V

DD

2

C × V_DD× f

75

70

65

60

55

50

45

40

75mW

56mW

C = load capacitance, f = output switching frequency.

Exam ple:

62mW

DD

In an application where external data memory is used and no

other outputs are active, power dissipation is calculated as follows:

45mW

33

Assumptions:

V

= 4.5V

31

DD

40mW

29

• External data memory is accessed every cycle with 50% of the

address pins switching.

28

30

32

34

1/f – MHz

CK

POWER, IDLE n MODES³

• External data memory writes occur every other cycle with

50% of the data pins switching.

75

70

• Each address and data pin has a 10 pF total load at the pin.

65

60

62mW

IDLE

• T he application operates at V_DD= 5.0 V and t_CK= 30 ns.

56mW

2

55

50

45

n

Total Power Dissipation = P_INT+ (C × V_DD× f)

P_INT= internal power dissipation from Power vs. Frequency

graph (Figure 8).

38mW

36mW

40

35

30

25

2

IDLE (16)

IDLE (128)

36mW

34mW

(C × V_DD× f) is calculated for each output:

# of

P ins

؋

C

2

؋

V_{D D}

؋

f

28

29

30

31

32

33

34

1/f – MHz

× 10 pF × 5²V × 33.3 MHz = 66.6 mW

× 10 pF × 5²V × 16.67 MHz = 37.5 mW

× 10 pF × 5²V × 16.67 MHz = 4.2 mW

× 10 pF × 5²V × 33.3 MHz = 8.3 mW

116.6 mW

CK

Address, DMS

Data Output, WR 9

RD

CLKOUT

8

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

2

IDLE REFERS TO ADSP-2185 STATE OF OPERATION DURING EXECUTION OF IDLE

INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND.

1

DD

3

TYPICAL POWER DISSIPATION AT 5.0V V AND 25°C EXCEPT WHERE SPECIFIED.

DD

4

I

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL

MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),

30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.

DD

T otal power dissipation for this example is P_INT+ 116.6 mW.

Figure 8. Power vs. Frequency

REV. 0

–15–

ADSP-2185

CAP ACITIVE LO AD ING

Figures 9 and 10 show the capacitive loading characteristics of

the ADSP-2185.

is calculated. If multiple pins (such as the data bus) are dis-

abled, the measurement value is that of the last pin to stop

driving.

30

T = +85°C

INPUT

1.5V

V

= 4.5V

DD

25

2.0V

1.5V

0.3V

OUTPUT

20

15

Figure 11. Voltage Reference Levels for AC Measure-

m ents (Except Output Enable/Disable)

10

5

O utput Enable Tim e

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. T he output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram. If multiple pins (such as

the data bus) are enabled, the measurement value is that of the

first pin to start driving.

0

100

150

– pF

200

250

300

50

C

L

Figure 9. Typical Output Rise Tim e vs. Load Capacitance,

C_L(at Maxim um Am bient Operating Tem perature)

18

16

14

12

10

REFERENCE

SIGNAL

t_MEASURED

t_DIS

t_ENA

V

OH

(MEASURED)

8

6

V

(MEASURED) – 0.5V

(MEASURED) +0.5V

2.0V

1.0V

OH

OL

OUTPUT

4

V

OL

(MEASURED)

t_DECAY

(MEASURED)

2

NOMINAL

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

–2

–4

–6

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

0

100

150

200

250

50

C

– pF

L

Figure 12. Output Enable/Disable

Figure 10. Typical Output Valid Delay or Hold vs. Load

Capacitance, C_L(at Maxim um Am bient Operating

Tem perature)

I

OL

TEST CO ND ITIO NS

O utput D isable Tim e

TO

OUTPUT

+1.5V

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured

output high or low voltage to a high impedance state. T he out-

put disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY

50pF

,

as shown in the Output Enable/Disable diagram. T he time is the

interval from when a reference signal reaches a high or low

voltage level to when the output voltages have changed by 0.5 V

from the measured output high or low voltage. T he decay time,

I

OH

Figure 13. Equivalent Device Loading for AC Measure-

m ents (Including All Fixtures)

t

_DECAY, is dependent on the capacitive load, C_L, and the current

load, i_L, on the output pin. It can be approximated by the fol-

lowing equation:

C_L× 0.5V

t_DECAY

=

i_L

from which

t_DIS= t_MEASURED– t_DECAY

REV. 0

–16–

ADSP-2185

TIMING PARAMETERS

P aram eter

Min

Max

Unit

Clock Signals and Reset

Timing Requirements:

t_CKI

t_CKIL

t_CKIH

CLKIN Period

CLKIN Width Low

CLKIN Width High

60

20

150

ns

Switching Characteristics:

t_CKL

t_CKH

t_CKOH

CLKOUT Width Low

CLKOUT Width High

CLKIN High to CLKOUT High

0.5 t_CK– 7

0

ns

20

Contr ol Signals

Timing Requirements:

t_RSP

t_MS

t_MH

RESET Width Low¹

Mode Setup Before RESET High

Mode Setup After RESET High

5 t_CK

2

5

ns

NOT E

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKCH

t_CKH

CLKOUT

t_CKL

PF(2:0)

*

t_MH

t_MS

RESET

*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 14. Clock Signals

–17–

REV. 0

ADSP-2185

P aram eter

Min

Max

Unit

Inter r upts and Flag

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25 t_CK+ 15

0.25 t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5 t_CK– 7

ns

0.25 t_CK+ 5

NOT ES

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-2100 Family User’s Manual for further information on

interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag outputs = PFx, FL0, FL1, FL2, Flag_out⁴.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 15. Interrupts and Flags

REV. 0

–18–

ADSP-2185

P aram eter

Min

Max

Unit

Bus Request/Gr ant

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25 t_CK+ 2

0.25 t_CK+ 17

ns

Switching Characteristics:

t_SD

t_SDB

t_SE

t_SEC

t_SDBH

t_SEH

CLKOUT High to xMS, RD, WR Disable

0.25 t_CK+ 10

ns

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT Hig

xMS, RD, WR Disable to BGH Low²

BGH High to xMS, RD, WR Enable²

0

0.25 t_CK– 7

0

NOT ES

xMS = PMS, DMS, CMS, IOMS, BMS

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

t_SD

t_SEC

WR

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 16. Bus Request–Bus Grant

–19–

REV. 0

ADSP-2185

P aram eter

Min

Max

Unit

Mem or y Read

Timing Requirements:

t_RDD

t_AA

t_RDH

RD Low to Data Valid

A0-A13, xMS to Data Valid

Data Hold from RD High

0.5 t_CK– 9 + w

0.75 t_CK– 10.5 + w

ns

0

Switching Characteristics:

t_RP

RD Pulse Width

CLKOUT High to RD Low

A0–A13, xMS Setup before RD Low

A0–A13, xMS Hold after RD Deasserted

RD High to RD or WR Low

0.5 t_CK– 5 + w

0.25 t_CK– 5

0.25 t_CK– 6

0.25 t_CK– 3

0.5 t_CK– 5

ns

t_CRD

t_ASR

t_RDA

t_RWR

0.25 t_CK+ 7

w = wait states × t_CK

xMS = PMS, DMS, CMS, IOMS, BMS

CLKOUT

A0–A13

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

RD

D

t_ASR

t_CRD

t_RP

t_RWR

t_RDD

t_RDH

t_AA

WR

Figure 17. Mem ory Read

REV. 0

–20–

ADSP-2185

P aram eter

Min

Max

Unit

Mem or y Wr ite

Switching Characteristics:

t_DW

t_DH

t_WP

t_WDE

t_ASW

t_DDR

t_CWR

t_AW

Data Setup before WR High

Data Hold after WR High

WR Pulse Width

WR Low to Data Enabled

A0–A13, xMS Setup before WR Low

Data Disable before WR or RD Low

CLKOUT High to WR Low

A0–A13, xMS, Setup before WR Deasserted

A0–A13, xMS Hold after WR Deasserted

WR High to RD or WR Low

0.5 t_CK– 7+ w

0.25 t_CK– 2

0.5 t_CK– 5 + w

0

0.25 t_CK– 6

0.25 t_CK– 7

0.25 t_CK– 5

0.75 t_CK– 9 + w

0.25 t_CK– 3

0.5 t_CK– 5

ns

0.25 t_CK+ 7

t_WRA

t_WWR

w = wait states × t_CK

xMS = PMS, DMS, CMS, IOMS, BMS

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_ASW

t_WWR

t_WP

t_AW

t_DH

t_DDR

t_CWR

D

t_DW

t_WDE

RD

Figure 18. Mem ory Write

–21–

REV. 0

ADSP-2185

P aram eter

Min

Max

Unit

Ser ial P or ts

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

50

4

7

ns

DR/T FS/RFS Setup before SCLK Low

DR/T FS/RFS Hold after SCLK Low

SCLK_INWidth

20

Switching Characteristics:

t_CC

CLKOUT High to SCLK_OUT

SCLK High to DT Enable

SCLK High to DT Valid

T FS/RFS_OUTHold after SCLK High

T FS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

T FS (Alt) to DT Enable

T FS (Alt) to DT Valid

0.25 t_CK

0

0.25 t_CK+ 10

ns

t_SCDE

t_SCDV

t_RH

15

0

t_RD

t_SCDH

t_{T DE}

t_{T DV}

t_SCDD

t_RDV

0

14

15

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_SCK

SCLK

t_SCP

t_SCS

t_SCH

DR

TFS

IN

RFS

IN

t_RD

t_RH

RFS

TFS

OUT

t_SCDD

t_SCDV

t_SCDH

t_SCDE

DT

t_TDE

t_TDV

TFS

OUT

ALTERNATE

FRAME MODE

t_RDV

RFS

OUT

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

t_TDE

t_TDV

TFS

IN

ALTERNATE

FRAME MODE

t_RDV

RFS

IN

MULTICHANNEL MODE,

FRAME DELAY 0

(MFD = 0)

Figure 19. Serial Ports

REV. 0

–22–

ADSP-2185

P aram eter

Min

Max

Unit

ID MA Addr ess Latch

Timing Requirements:

t_IALP

t_IASU

t_IAH

t_IKA

t_IALS

Duration of Address Latch^{1, 3}

10

5

2

0

3

ns

IAD15–0 Address Setup before Address Latch End³

IAD15–0 Address Hold after Address Latch End³

IACK Low before Start of Address Latch¹

Start of Write or Read after Address Latch End^{2, 3}

NOT ES

¹Start of Address Latch = IS Low and IAL High.

²Start of Write or Read = IS Low and IWR Low or IRD Low.

³End of Address Latch = IS High or IAL Low.

IACK

t_IKA

IAL

t_IALP

IS

t_IASU

t_IAH

IAD 15–0

t_IALS

IRD

OR

IWR

Figure 20. IDMA Address Latch

–23–

REV. 0

ADSP-2185

P aram eter

Min

Max

Unit

ID MA Wr ite, Shor t Wr ite Cycle

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low before Start of Write¹

0

15

5

ns

Duration of Write^{1, 2}

IAD15–0 Data Setup before End of Write^{2, 3, 4}

IAD15–0 Data Hold after End of Write^{2, 3, 4}

2

Switching Characteristics:

t_IKHW

Start of Write to IACK High

15

ns

NOT ES

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

t_IKHW

IS

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD 15–0

Figure 21. IDMA Write, Short Write Cycle

REV. 0

–24–

ADSP-2185

P aram eter

Min

Max

Unit

ID MA Wr ite, Long Wr ite Cycle

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low before Start of Write¹

0

ns

IAD15–0 Data Setup before IACK Low^{2, 3, 4}

IAD15–0 Data Hold after IACK Low^{2, 3, 4}

0.5 t_CK+ 10

2

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5 t_CK

ns

15

NOT ES

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴T his is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD 15–0

Figure 22. IDMA Write, Long Write Cycle

–25–

REV. 0

ADSP-2185

P aram eter

Min

Max

Unit

ID MA Read, Long Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

0

15

ns

Duration of Read¹

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High after Start of Read¹

15

ns

IAD15–0 Data Setup before IACK Low

0.5 t_CK– 10

0

IAD15–0 Data Hold after End of Read²

IAD15–0 Data Disabled after End of Read²

10

15

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

IAD15–0 Previous Data Hold after Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold after Start of Read (PM2)⁴

0

2 t_CK– 5

t_CK– 5

NOT ES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRP

IRD

t_IKDS

t_IKDH

t_IRDE

READ

DATA

IAD 15–0

t_IRDV

t_IKDD

t_IRDH

Figure 23. IDMA Read, Long Read Cycle

REV. 0

–26–

ADSP-2185

P aram eter

Min

Max

Unit

ID MA Read, Shor t Read Cycle

Timing Requirements:

t_IKR

t_IRP

IACK Low before Start of Read¹

Duration of Read

0

15

ns

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High after Start of Read¹

15

10

15

ns

IAD15–0 Data Hold after End of Read²

0

IAD15–0 Data Disabled after End of Read²

IAD15–0 Previous Data Enabled after Start of Read

IAD15–0 Previous Data Valid after Start of Read

NOT ES

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

IACK

IS

t_IKR

t_IKHR

t_IRP

IRD

t_IKDH

t_IRDE

IAD 15–0

t_IKDD

t_IRDV

Figure 24. IDMA Read, Short Read Cycle

–27–

REV. 0

ADSP-2185

100-Lead TQFP P ackage P inout

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

A4/IAD3

A5/IAD4

GND

1

2

D15

D14

D13

PIN 1

IDENTIFIER

3

4

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

D12

5

GND

6

D11

D10

7

8

D9

9

VDD

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

D8

D7/IWR

D6/IRD

D5/IAL

ADSP-2185

CLKIN

TOP VIEW

(Not to Scale)

XTAL

D4/IS

VDD

CLKOUT

GND

VDD

GND

VDD

D3/IACK

D2/IAD15

WR

RD

56 D1/IAD14

55

54

53

52

51

D0/IAD13

BG

BMS

DMS

PMS

IOMS

CMS

EBG

BR

EBR

REV. 0

–28–

ADSP-2185

T he ADSP-2185 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in

brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET .

TQFP P in Configurations

TQFP

P in

TQFP

P in

TQFP

P in

TQFP

P in

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

Num ber

Nam e

1

2

3

4

5

6

7

8

A4/IAD 3

A5/IAD 4

GND

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT 0

T FS0

RFS0

DR0

SCLK0

VDD

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

EBR

BR

EBG

BG

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3

PF2 [Mode C]

VDD

PWD

GND

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD 0

A2/IAD 1

A3/IAD 2

A6/IAD 5

A7/IAD 6

A8/IAD 7

A9/IAD 8

A10/IAD 9

A11/IAD 10

A12/IAD 11

A13/IAD 12

GND

CLKIN

XT AL

VDD

CLKOUT

GND

VDD

WR

RD

BMS

DMS

PMS

IOMS

CMS

D0/IAD 13

D1/IAD 14

D2/IAD 15

D3/IACK

VDD

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

VDD

D9

D10

D11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DT 1

T FS1

RFS1

DR1

GND

SCLK1

ERESET

RESET

EMS

EE

GND

D12

D13

D14

D15

ECLK

ELOUT

ELIN

EINT

–29–

REV. 0

ADSP-2185

O RD ERING GUID E

Am bient

Tem perature

Range

Instruction

Rate

(MH z)

P ackage

D escription

P ackage

O ption*

P art Num ber

ADSP-2185KST -115

ADSP-2185BST -115

ADSP-2185KST -133

ADSP-2185BST -133

0°C to +70°C

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

28.8

33.3

100-Lead T QFP

ST -100

*ST = Plastic T hin Quad Flatpack (T QFP).

O UTLINE D IMENSIO NS

D imensions shown in inches and millimeters.

100-Lead Metric Thin P lastic Quad Flatpack (TQFP )

(ST-100)

0.640 (16.25)

0.630 (16.00)

0.620 (15.75)

TYP SQ

0.555 (14.05)

0.551 (14.00)

0.547 (13.90)

0.476 (12.10)

0.474 (12.05)

0.472 (12.00)

0.063 (1.60) MAX

0.024 (0.75)

0.022 (0.60) TYP

0.020 (0.50)

100

1

76

75

12°

TYP

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004

(0.102)

MAX LEAD

COPLANARITY

25

51

50

26

6° ± 4°

0° – 10°

0.020 (0.50)

BSC

0.007 (0.177)

0.010 (0.27)

0.005 (0.127) TYP

0.003 (0.077)

0.009 (0.22) TYP

0.006 (0.17)

LEAD PITCH

LEAD WIDTH

REV. 0

–30–

–31–

–32–


型号：	ADSP-2185
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总32页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2185 [ADI]

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