ADSP-2188NKSTZ-3202_技术文档

DSP Microcomputer

ADSP-218xN Series

a

PERFORMANCE FEATURES

SYSTEM INTERFACE FEATURES

12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus-

tained performance

Single-cycle instruction execution

Single-cycle context switch

Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation

All inputs tolerate up to 3.6 V regardless of mode

16-bit internal DMA port for high-speed access to on-chip

memory (mode selectable)

4M-byte memory interface for storage of data tables and pro-

gram overlays (mode selectable)

3-bus architecture allows dual operand fetches in every

instruction cycle

8-bit DMA to byte memory for transparent program and data

memory transfers (mode selectable)

Programmable memory strobe and separate I/O memory

space permits “glueless” system design

Multifunction instructions

Power-down mode featuring low CMOS standby power dissi-

pation with 200 CLKIN cycle recovery from power-down

condition

Programmable wait state generation

Low power dissipation in idle mode

Two double-buffered serial ports with companding hardware

and automatic data buffering

Automatic booting of on-chip program memory from byte-

wide external memory, for example, EPROM, or through

internal DMA Port

INTEGRATION FEATURES

ADSP-2100 family code compatible (easy to use algebraic

syntax), with instruction set extensions

Up to 256K byte of on-chip RAM, configured

Up to 48K words program memory RAM

Up to 56K words data memory RAM

Dual-purpose program memory for both instruction and

data storage

Independent ALU, multiplier/accumulator, and barrel shifter

computational units

Six external interrupts

13 programmable flag pins provide flexible system signaling

UART emulation through software SPORT reconfiguration

ICE-Port™ emulator interface supports debugging in final

systems

Two independent data address generators

Powerful program sequencer provides zero overhead loop-

ing conditional instruction execution

Programmable 16-bit interval timer with prescaler

100-lead LQFP and 144-ball BGA

POWER-DOWN

CONTROL

FULL MEMORY MODE

PROGRAMMABLE

MEMORY

PROGRAM

EXTERNAL

ADDRESS

BUS

DATA

MEMORY

UP TO

DATA ADDRESS

GENERATORS

I/O

MEMORY

UP TO

48K

؋

24-BIT

PROGRAM

SEQUENCER

AND

FLAGS

DAG1

DAG2

56K

؋

16-BIT

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

SERIAL PORTS

TIMER

INTERNAL

DMA

PORT

ALU

MAC

SHIFTER

SPORT0

SPORT1

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

Figure 1. Functional Block Diagram

ICE-Port is a trademark of Analog Devices, Inc.

Rev. A

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

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Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-218xN

TABLE OF CONTENTS

General Description ................................................. 3

Architecture Overview ........................................... 3

Modes Of Operation .............................................. 5

Interrupts ........................................................... 5

Low-power Operation ............................................ 6

System Interface ................................................... 7

Reset .................................................................. 8

Power Supplies ..................................................... 8

Memory Architecture ............................................ 9

Bus Request and Bus Grant ................................... 14

Flag I/O Pins ..................................................... 15

Instruction Set Description ................................... 15

Development System ........................................... 15

Additional Information ........................................ 17

Pin Descriptions .................................................... 18

Memory Interface Pins ......................................... 19

Terminating Unused Pins ..................................... 19

Specifications ........................................................ 22

Recommended Operating Conditions ...................... 22

Electrical Characteristics ....................................... 22

Absolute Maximum Ratings .................................. 23

ESD Sensitivity ................................................... 23

ESD Diode Protection .......................................... 24

Power Dissipation ............................................... 24

Environmental Conditions .................................... 25

Test Conditions .................................................. 25

Timing Specifications .......................................... 26

LQFP Package Pinout .......................................... 40

BGA Package Pinout ........................................... 42

Outline Dimensions ............................................... 45

Surface Mount Design .......................................... 46

Ordering Guide ..................................................... 47

REVISION HISTORY

8/06—Rev. 0 to Rev. A

Miscellaneous Format Updates.......................... Universal

Applied Corrections or Additional Information to:

Clock Signals ....................................................... 8

External Crystal Connections .................................. 8

ADSP-2185 Memory Architecture ............................ 9

Electrical Characteristics ....................................... 22

Absolute Maximum Ratings ................................... 23

ESD Diode Protection .......................................... 24

Memory Read ..................................................... 31

Memory Write .................................................... 32

Serial Ports ........................................................ 33

Outline Dimensions ............................................. 45

Ordering Guide .................................................. 47

Rev. A

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ADSP-218xN

GENERAL DESCRIPTION

The ADSP-218xN series consists of six single chip microcom-

puters optimized for digital signal processing applications. The

high-level block diagram for the ADSP-218xN series members

appears on the previous page. All series members are pin-com-

patible and are differentiated solely by the amount of on-chip

SRAM. This feature, combined with ADSP-21xx code compati-

bility, provides a great deal of flexibility in the design decision.

Specific family members are shown in Table 1.

• Receive and/or transmit data through the byte DMA port

• Decrement timer

ARCHITECTURE OVERVIEW

The ADSP-218xN series instruction set provides flexible data

moves and multifunction (one or two data moves with a com-

putation) instructions. Every instruction can be executed in a

single processor cycle. The ADSP-218xN assembly language

uses an algebraic syntax for ease of coding and readability. A

comprehensive set of development tools supports program

development.

Table 1. ADSP-218xN DSP Microcomputer Family

Program Memory Data Memory

Device

(K words)

The functional block diagram is an overall block diagram of the

ADSP-218xN series. The processor contains three independent

computational units: the ALU, the multiplier/accumulator

(MAC), and the shifter. The computational units process 16-bit

data directly and have provisions to support multiprecision

computations. The ALU performs a standard set of arithmetic

and logic operations; division primitives are also supported. The

MAC performs single-cycle multiply, multiply/add, and multi-

ply/subtract operations with 40 bits of accumulation. The shifter

performs logical and arithmetic shifts, normalization, denor-

malization, and derive exponent operations.

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

4

16

8

16

8

32

48

32

56

48

ADSP-218xN series members combine the ADSP-2100 family

base architecture (three computational units, data address gen-

erators, and a program sequencer) with two serial ports, a 16-bit

internal DMA port, a byte DMA port, a programmable timer,

Flag I/O, extensive interrupt capabilities, and on-chip program

and data memory.

The shifter can be used to efficiently implement numeric format

control, including multiword and block floating-point

representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

ADSP-218xN series members integrate up to 256K bytes of on-

chip memory configured as up to 48K words (24-bit) of pro-

gram RAM, and up to 56K words (16-bit) of data RAM. Power-

down circuitry is also provided to meet the low power needs of

battery-operated portable equipment. The ADSP-218xN is

available in a 100-lead LQFP package and 144-ball BGA.

A powerful program sequencer and two dedicated data address

generators ensure efficient delivery of operands to these compu-

tational units. The sequencer supports conditional jumps,

subroutine calls, and returns in a single cycle. With internal

loop counters and loop stacks, ADSP-218xN series members

execute looped code with zero overhead; no explicit jump

instructions are required to maintain loops.

Fabricated in a high-speed, low-power, 0.18 μm CMOS process,

ADSP-218xN series members operate with a 12.5 ns instruction

cycle time. Every instruction can execute in a single pro-

cessor cycle.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four address

pointers. Whenever the pointer is used to access data (indirect

addressing), it is post-modified by the value of one of four possi-

ble modify registers. A length value may be associated with each

pointer to implement automatic modulo addressing for

circular buffers.

The ADSP-218xN’s flexible architecture and comprehensive

instruction set allow the processor to perform multiple opera-

tions in parallel. In one processor cycle, ADSP-218xN series

members can:

• Generate the next program address

• Fetch the next instruction

• Perform one or two data moves

Five internal buses provide efficient data transfer:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

• Update one or two data address pointers

• Perform a computational operation

This takes place while the processor continues to:

• Receive and transmit data through the two serial ports

• Receive and/or transmit data through the internal

DMA port

Rev. A

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ADSP-218xN

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

Serial Ports

ADSP-218xN series members incorporate two complete syn-

chronous serial ports (SPORT0 and SPORT1) for serial

communications and multiprocessor communication.

Following is a brief list of the capabilities of the ADSP-218xN

SPORTs. For additional information on Serial Ports, refer to the

ADSP-218x DSP Hardware Reference.

Program memory can store both instructions and data, permit-

ting ADSP-218xN series members to fetch two operands in a

single cycle, one from program memory and one from data

memory. ADSP-218xN series members can fetch an operand

from program memory and the next instruction in the

same cycle.

• SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

In lieu of the address and data bus for external memory connec-

tion, ADSP-218xN series members may be configured for 16-bit

Internal DMA port (IDMA port) connection to external sys-

tems. The IDMA port is made up of 16 data/address pins and

five control pins. The IDMA port provides transparent, direct

access to the DSP’s on-chip program and data RAM.

• SPORTs have independent framing for the receive and

transmit sections. Sections run in a frameless mode or with

frame synchronization signals internally or externally gen-

erated. Frame sync signals are active high or inverted, with

either of two pulsewidths and timings.

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

• SPORTs support serial data word lengths from 3 bits to

16 bits and provide optional A-law and μ-law companding,

according to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

The byte memory and I/O memory space interface supports

slow memories and I/O memory-mapped peripherals with pro-

grammable wait state generation. External devices can gain

control of external buses with bus request/grant signals (BR,

BGH, and BG). One execution mode (Go Mode) allows the

ADSP-218xN to continue running from on-chip memory. Nor-

mal execution mode requires the processor to halt while buses

are granted.

• SPORTs can receive and transmit an entire circular buffer

of data with only one overhead cycle per data word. An

interrupt is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24 word or 32-word, time-division multi-

plexed, serial bitstream.

ADSP-218xN series members can respond to eleven interrupts.

There can be up to six external interrupts (one edge-sensitive,

two level-sensitive, and three configurable) and seven internal

interrupts generated by the timer, the serial ports (SPORT), the

BDMA port, and the power-down circuitry. There is also a mas-

ter RESET signal. The two serial ports provide a complete

synchronous serial interface with optional companding in hard-

ware and a wide variety of framed or frameless data transmit

and receive modes of operation.

• SPORT1 can be configured to have two external interrupts

(IRQ0 and IRQ1) and the FI and FO signals. The internally

generated serial clock may still be used in this

configuration.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

ADSP-218xN series members provide up to 13 general-purpose

flag pins. The data input and output pins on SPORT1 can be

alternatively configured as an input flag and an output flag. In

addition, eight flags are programmable as inputs or outputs, and

three flags are always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) decrements every n processor

cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Rev. A

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ADSP-218xN

MODES OF OPERATION

The ADSP-218xN series modes of operation appear in Table 2.

Table 2. Modes of Operation

Mode D

Mode C

Mode B

Mode A

Booting Method

X

0

BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is

configured in Full Memory Mode.¹

X

0

1

0

1

0

1

0

No automatic boot operations occur. Program execution starts at external memory

location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the

processor does not automatically use or wait for these operations.

BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is

configured in Host Mode. IACK has active pull-down. (Requires additonal hardware.)

IDMA feature is used to load any internal memory as desired. Program execution is held

off until the host writes to internal program memory location 0. Chip is configured in

Host Mode. IACK has active pull-down.¹

BDMA feature is used to load the first 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is

configured in Host Mode; IACK requires external pull-down. (Requires additonal

hardware.)

1

0

1

IDMA feature is used to load any internal memory as desired. Program execution is held

off until the host writes to internal program memory location 0. Chip is configured in

Host Mode. IACK requires external pull-down.¹

¹Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

the programmable flag as an output when connected to a three-

Setting Memory Mode

stated buffer. This ensures that the pin will be held at a constant

level, and will not oscillate should the three-state driver’s level

hover around the logic switching point.

Memory Mode selection for the ADSP-218xN series is made

during chip reset through the use of the Mode C pin. This pin is

multiplexed with the DSP’s PF2 pin, so care must be taken in

how the mode selection is made. The two methods for selecting

the value of Mode C are active and passive.

IDMA ACK Configuration

Mode D = 0 and in host mode: IACK is an active, driven signal

and cannot be “wire-OR’ed.” Mode D = 1 and in host mode:

IACK is an open drain and requires an external pull-down, but

multiple IACK pins can be “wire-OR’ed” together.

Passive Configuration

Passive Configuration involves the use of a pull-up or pull-

down resistor connected to the Mode C pin. To minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down resistance, on the

order of 10 kΩ, can be used. This value should be sufficient to

pull the pin to the desired level and still allow the pin to operate

as a programmable flag output without undue strain on the pro-

cessor’s output driver. For minimum power consumption

during power-down, reconfigure PF2 to be an input, as the pull-

up or pull-down resistance will hold the pin in a known state,

and will not switch.

INTERRUPTS

The interrupt controller allows the processor to respond to the

eleven possible interrupts and reset with minimum overhead.

ADSP-218xN series members provide four dedicated external

interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared

with the PF7–4 pins). In addition, SPORT1 may be reconfig-

ured for IRQ0, IRQ1, FI, and FO, for a total of six external

interrupts. The ADSP-218xN also supports internal interrupts

from the timer, the byte DMA port, the two serial ports, soft-

ware, and the power-down control circuit. The interrupt levels

are internally prioritized and individually maskable (except

power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins

can be programmed to be either level- or edge-sensitive. IRQL0

and IRQL1 are level-sensitive and IRQE is edge-sensitive. The

priorities and vector addresses of all interrupts are shown in

Table 3.

Active Configuration

Active Configuration involves the use of a three-statable exter-

nal driver connected to the Mode C pin. A driver’s output

enable should be connected to the DSP’s RESET signal such that

it only drives the PF2 pin when RESET is active (low). When

RESET is deasserted, the driver should be three-state, thus

allowing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, configure

Rev. A

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ADSP-218xN

Table 3. Interrupt Priority and Interrupt Vector Addresses

The CLKOUT pin may also be disabled to reduce external

power dissipation.

Interrupt Vector Address

Power-Down

Source Of Interrupt

(Hex)

Reset (or Power-Up with PUCR = 1) 0x0000 (Highest Priority)

ADSP-218xN series members have a low-power feature that lets

the processor enter a very low-power dormant state through

hardware or software control. Following is a brief list of power-

down features. Refer to the ADSP-218x DSP Hardware Refer-

ence, “System Interface” chapter, for detailed information about

the power-down feature.

Power-Down (Nonmaskable)

IRQ2

0x002C

0x0004

IRQL1

0x0008

IRQL0

0x000C

SPORT0 Transmit

SPORT0 Receive

IRQE

0x0010

• Quick recovery from power-down. The processor begins

executing instructions in as few as 200 CLKIN cycles.

0x0014

0x0018

• Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the lowest power rating and

200 CLKIN cycle recovery.

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

0x001C

0x0020

0x0024

0x0028 (Lowest Priority)

• Support for crystal operation includes disabling the oscilla-

tor to save power (the processor automatically waits

approximately 4096 CLKIN cycles for the crystal oscillator

to start or stabilize), and letting the oscillator run to allow

200 CLKIN cycle start-up.

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The power-down interrupt is nonmaskable.

• Power-down is initiated by either the power-down pin

(PWD) or the software power-down force bit. Interrupt

support allows an unlimited number of instructions to be

executed before optionally powering down. The power-

down interrupt also can be used as a nonmaskable, edge-

sensitive interrupt.

ADSP-218xN series members mask all interrupts for one

instruction cycle following the execution of an instruction that

modifies the IMASK register. This does not affect serial port

autobuffering or DMA transfers.

• Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving

the power-down state.

The interrupt control register, ICNTL, controls interrupt nest-

ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts to

be either edge- or level-sensitive. The IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level sensitive interrupts.

• The RESET pin also can be used to terminate power-down.

• Power-down acknowledge pin (PWDACK) indicates when

the processor has entered power-down.

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

are 12 levels deep to allow interrupt, loop, and subroutine nest-

ing. The following instructions allow global enable or disable

servicing of the interrupts (including power-down), regardless

of the state of IMASK:

Idle

When the ADSP-218xN is in the Idle Mode, the processor waits

indefinitely in a low-power state until an interrupt occurs.

When an unmasked interrupt occurs, it is serviced; execution

then continues with the instruction following the IDLE instruc-

tion. In Idle mode IDMA, BDMA, and autobuffer cycle steals

still occur.

ENA INTS;

DIS INTS;

Slow Idle

Disabling the interrupts does not affect serial port autobuffering

or DMA. When the processor is reset, interrupt servicing

is enabled.

The IDLE instruction is enhanced on ADSP-218xN series mem-

bers to let the processor’s internal clock signal be slowed, further

reducing power consumption. The reduced clock frequency, a

programmable fraction of the normal clock rate, is specified by a

selectable divisor given in the IDLE instruction.

LOW-POWER OPERATION

ADSP-218xN series members have three low-power modes that

significantly reduce the power dissipation when the device oper-

ates under standby conditions. These modes are:

The format of the instruction is:

IDLE (n);

• Power-Down

• Idle

where n = 16, 32, 64, or 128. This instruction keeps the proces-

sor fully functional, but operating at the slower clock rate. While

it is in this state, the processor’s other internal clock signals,

• Slow Idle

Rev. A

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ADSP-218xN

such as SCLK, CLKOUT, and timer clock, are reduced by the

same ratio. The default form of the instruction, when no clock

divisor is given, is the standard IDLE instruction.

faster rate than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to

incoming interrupts. The one-cycle response time of the stan-

dard idle state is increased by n, the clock divisor. When an

enabled interrupt is received, ADSP-218xN series members

remain in the idle state for up to a maximum of n processor

cycles (n = 16, 32, 64, or 128) before resuming nor-

mal operation.

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the

ADSP-218xN series, two serial devices, a byte-wide EPROM,

and optional external program and data overlay memories

(mode-selectable). Programmable wait state generation allows

the processor to connect easily to slow peripheral devices.

ADSP-218xN series members also provide four external inter-

rupts and two serial ports or six external interrupts and one

serial port. Host Memory Mode allows access to the full external

data bus, but limits addressing to a single address bit (A0).

Through the use of external hardware, additional system

peripherals can be added in this mode to generate and latch

address signals.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

FULL MEMORY MODE

ADSP-218xN

HOST MEMORY MODE

ADSP-218xN

1/2

؋

CLOCK

OR

CRYSTAL

CLKIN

XTAL

FL0–2

CLKIN

1/2

؋

CLOCK

OR

CRYSTAL

A13–0

14

XTAL

ADDR13–0

1

A0

D23–16

D15–8

A0–A21

FL0–2

BYTE

MEMORY

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

16

24

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

DATA23–8

DATA23–0

DATA

CS

BMS

WR

RD

BMS

MODE D/PF3

MODE C/PF2

MODE A/PF0

A10–0

D23–8

WR

RD

MODE D/PF3

MODE C/PF2

MODE A/PF0

MODE B/PF1

ADDR

I/O SPACE

(PERIPHERALS)

2048 LOCATIONS

MODE B/PF1

DATA

IOMS

SPORT1

CS

IOMS

SPORT1

SCLK1

A13–0

D23–0

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

SERIAL

DEVICE

OVERLAY

MEMORY

ADDR

DATA

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

SERIAL

DEVICE

TWO 8K

PM SEGMENTS

DR1 OR FI

PMS

DMS

CMS

PMS

DMS

CMS

SPORT0

SCLK0

RFS0

TWO 8K

DM SEGMENTS

SPORT0

SCLK0

RFS0

TFS0

DT0

SERIAL

DEVICE

BR

BG

BGH

BR

BG

BGH

PWD

TFS0

DT0

DR0

SERIAL

DEVICE

PWD

IDMA PORT

IRD/D6

DR0

PWDACK

SYSTEM

INTERFACE

OR

IWR/D7

IS/D4

IAL/D5

IACK/D3

µCONTROLLER

IAD15-0

16

Figure 2. Basic System Interface

Rev. A

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ADSP-218xN

2000 CLKIN cycles ensures that the PLL has locked, but does

not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

mum pulse-width specification (t_RSP).

Clock Signals

ADSP-218xN series members can be clocked by either a crystal

or a TTL-compatible clock signal.

The CLKIN input cannot be halted, changed during operation,

nor operated below the specified frequency during normal oper-

ation. The only exception is while the processor is in the power-

down state. For additional information, refer to the ADSP-218x

DSP Hardware Reference, for detailed information on this

power-down feature.

The RESET input contains some hysteresis; however, if an RC

circuit is used to generate the RESET signal, the use of an exter-

nal Schmitt trigger is recommended.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and clears the MSTAT

register. When RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading

sequence is performed. The first instruction is fetched from on-

chip program memory location 0x0000 once boot loading

completes.

If an external clock is used, it should be a TTL-compatible signal

running at half the instruction rate. The signal is connected to

the processor’s CLKIN input. When an external clock is used,

the XTAL pin must be left unconnected.

ADSP-218xN series members use an input clock with a fre-

quency equal to half the instruction rate; a 40 MHz input clock

yields a 12.5 ns processor cycle (which is equivalent to

80 MHz). Normally, instructions are executed in a single pro-

cessor cycle. All device timing is relative to the internal instruc-

tion clock rate, which is indicated by the CLKOUT signal

when enabled.

POWER SUPPLIES

ADSP-218xN series members have separate power supply con-

nections for the internal (V_DDINT) and external (V_DDEXT) power

supplies. The internal supply must meet the 1.8 V requirement.

The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V

supply. All external supply pins must be connected to the same

supply. All input and I/O pins can tolerate input voltages up to

3.6 V, regardless of the external supply voltage. This feature pro-

vides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V

components.

Because ADSP-218xN series members include an on-chip oscil-

lator circuit, an external crystal may be used. The crystal should

be connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 3. Capacitor values are

dependent on crystal type and should be specified by the crystal

manufacturer. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal should be used. To provide an

adequate feedback path around the internal amplifier circuit,

place a resistor in parallel with the circuit, as shown in Figure 3.

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This can be enabled and disabled by

the CLKODIS bit in the SPORT0 Autobuffer Control Register.

1M ⍀

X TA L

C LK O U T

C LK IN

D S P

Figure 3. External Crystal Connections

RESET

The RESET signal initiates a master reset of the ADSP-218xN.

The RESET signal must be asserted during the power-up

sequence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis

applied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

Rev. A

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ADSP-218xN

Figure 4 through Figure 9, Table 4 on Page 11, and Table 5 on

Page 11 for PM and DM memory allocations in the ADSP-

218xN series.

MEMORY ARCHITECTURE

The ADSP-218xN series provides a variety of memory and

peripheral interface options. The key functional groups are Pro-

gram Memory, Data Memory, Byte Memory, and I/O. Refer to

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

0x3FE0

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FDF

RESERVED

4064 RESERVED

PM OVERLAY 0

(RESERVED)

WORDS

0x3000

0x2FFF

0x2000

0x1FFF

0x2000

0x1FFF

INTERNAL DM

0x2000

0x1FFF

RESERVED

DM OVERLAY 1,2

EXTERNAL PM

(EXTERNAL DM)

0x1000

0x0FFF

DM OVERLAY 0

(RESERVED)

INTERNAL PM

0x0000

Figure 4. ADSP-2184 Memory Architecture

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY 0

(INTERNAL PM)

INTERNAL DM

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0

(INTERNAL DM)

0x0000

Figure 5. ADSP-2185 Memory Architecture

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY 0

(RESERVED)

INTERNAL DM

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0

(RESERVED)

0x0000

Figure 6. ADSP-2186 Memory Architecture

Rev. A

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ADSP-218xN

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY 0,4,5

(INTERNAL PM)

INTERNAL DM

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY 0,4,5

(INTERNAL DM)

0x0000

Figure 7. ADSP-2187 Memory Architecture

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY

0,4,5,6,7

INTERNAL DM

(INTERNAL PM)

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY

0,4,5,6,7,8

(INTERNAL DM)

0x0000

Figure 8. ADSP-2188 Memory Architecture

PROGRAM MEMORY

MODEB = 1

PROGRAM MEMORY

MODEB = 0

DATA MEMORY

0x3FFF

32 MEMORY-MAPPED

CONTROL REGISTERS

PM OVERLAY 1,2

(EXTERNAL PM)

0x3FE0

0x3FDF

RESERVED

PM OVERLAY 0,4,5

(INTERNAL PM)

INTERNAL DM

0x2000

0x1FFF

0x2000

0x1FFF

0x2000

0x1FFF

DM OVERLAY 1,2

(EXTERNAL DM)

EXTERNAL PM

INTERNAL PM

DM OVERLAY

0,4,5,6,7

(INTERNAL DM)

0x0000

Figure 9. ADSP-2189 Memory Architecture

DSPs of this series have up to 48K words of Program Memory

RAM on chip, and the capability of accessing up to two 8K

external memory overlay spaces, using the external data bus.

Program Memory

Program Memory (Full Memory Mode) is a 24-bit-wide space

for storing both instruction opcodes and data. The member

Rev. A

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ADSP-218xN

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is only 16 bits wide.

Table 4. PMOVLAY Bits

Processor

PMOVLAY

Memory

A13

A12–0

ADSP-2184N

No Internal Overlay Not Applicable

Region

Not Applicable

ADSP-2185N

ADSP-2186N

0

Internal Overlay

Not Applicable

No Internal Overlay Not Applicable

Region

ADSP-2187N

ADSP-2188N

ADSP-2189N

All Processors

0, 4, 5

Internal Overlay

External Overlay 1

External Overlay 2

Not Applicable

0, 4, 5, 6, 7

Not Applicable

0, 4, 5

Not Applicable

1

2

0

1

13 LSBs of Address Between 0x2000 and 0x3FFF

All internal accesses complete in one cycle. Accesses to external

memory are timed using the wait states specified by the DWAIT

register and the wait state mode bit.

Data Memory

Data Memory (Full Memory Mode) is a 16-bit-wide space used

for the storage of data variables and for memory-mapped con-

trol registers. The ADSP-218xN series has up to 56K words of

Data Memory RAM on-chip. Part of this space is used by 32

memory-mapped registers. Support also exists for up to two 8K

external memory overlay spaces through the external data bus.

Data Memory (Host Mode) allows access to all internal mem-

ory. External overlay access is limited by a single external

address line (A0).

Table 5. DMOVLAY Bits

Processor

DMOVLAY

Memory

A13

A12–0

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

All Processors

No Internal Overlay Region

Not Applicable

Internal Overlay

Not Applicable

Internal Overlay

External Overlay 1

Not Applicable

0

Not Applicable

0

No Internal Overlay Region

0, 4, 5

0, 4, 5, 6, 7, 8

0, 4, 5, 6, 7

1

13 LSBs of Address

Between 0x0000 and

0x1FFF

All Processors

2

External Overlay 2

1

13 LSBs of Address

Between 0x0000 and

0x1FFF

Memory-Mapped Registers (New to the ADSP-218xM and

N series)

I/O Space (Full Memory Mode)

ADSP-218xN series members support an additional external

memory space called I/O space. This space is designed to sup-

port simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data registers.

I/O space supports 2048 locations of 16-bit wide data. The lower

eleven bits of the external address bus are used; the upper three

bits are undefined.

ADSP-218xN series members have three memory-mapped reg-

isters that differ from other ADSP-21xx Family DSPs. The slight

modifications to these registers (Wait State Control, Program-

mable Flag and Composite Select Control, and System Control)

provide the ADSP-218xN’s wait state and BMS control features.

Default bit values at reset are shown; if no value is shown, the bit

is undefined at reset. Reserved bits are shown on a grey field.

These bits should always be written with zeros.

Two instructions were added to the core ADSP-2100 Family

instruction set to read from and write to I/O memory space. The

I/O space also has four dedicated three-bit wait state registers,

Rev. A

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August 2006

ADSP-218xN

IOWAIT0–3 as shown in Figure 10, which in combination with

the wait state mode bit, specify up to 15 wait states to be auto-

matically generated for each of four regions. The wait states act

on address ranges, as shown in Table 6.

PROGRAMMABLE FLAG AND COMPOSITE

SELECT CONTROL

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM(0x3FE6)

1

0

1

0

Note: In Full Memory Mode, all 2048 locations of I/O space are

directly addressable. In Host Memory Mode, only address pin

A0 is available; therefore, additional logic is required externally

to achieve complete addressability of the 2048 I/O

space locations.

BMWAIT

CMSSEL

0 = DISABLE CMS 0 = INPUT

1 = ENABLE CMS 1 = OUTPUT

PFTYPE

(WHERE BIT: 11-IOM, 10-BM, 9-DM, 8-PM)

Figure 11. Programmable Flag and Composite Control Register

Table 6. Wait States

SYSTEM CONTROL

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Address Range

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

Wait State Register

DM(0x3FFF)

0

1

0

1

IOWAIT0 and Wait State Mode Select Bit

IOWAIT1 and Wait State Mode Select Bit

IOWAIT2 and Wait State Mode Select Bit

IOWAIT3 and Wait State Mode Select Bit

RESERVED

SET TO 0

RESERVED,ALWAYS

SET TO 0

PWAIT

PROGRAM MEMORY

WAIT STATES

SPORT0 ENABLE

0 = DISABLE

1 = ENABLE

DISABLE BMS

0 = ENABLE BMS

1 = DISABLE BMS

SPORT1 ENABLE

0 = DISABLE

WAIT STATE CONTROL

1 = ENABLE

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

DM(0x3FFE)

SPORT1 CONFIGURE

0 = FI, FO, IRQ0, IRQ1, SCLK

1 = SPORT1

1

DWAIT

IOWAIT3

IOWAIT2 IOWAIT1

IOWAIT0

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS

SHOULD ALWAYS BE WRITTEN WITH ZEROS.

WAIT STATE MODE SELECT

0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES,

RANGING FROM 0 TO 7)

1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,

RANGING FROM 0 TO 15)

Figure 12. System Control Register

select, and a flash memory could be connected to CMS. Because

at reset BMS is enabled, the EPROM would be used for booting.

After booting, software could disable BMS and set the CMS sig-

nal to respond to BMS, enabling the flash memory.

Figure 10. Wait State Control Register

Composite Memory Select

ADSP-218xN series members have a programmable memory

select signal that is useful for generating memory select signals

for memories mapped to more than one space. The CMS signal

is generated to have the same timing as each of the individual

memory select signals (PMS, DMS, BMS, IOMS) but can com-

bine their functionality. Each bit in the CMSSEL register, when

set, causes the CMS signal to be asserted when the selected

memory select is asserted. For example, to use a 32K word

memory to act as both program and data memory, set the PMS

and DMS bits in the CMSSEL register and use the CMS pin to

drive the chip select of the memory, and use either DMS or PMS

as the additional address bit.

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide,

external memory space used to store programs and data. Byte

memory is accessed using the BDMA feature. The byte memory

space consists of 256 pages, each of which is 16K

؋

8 bits.

The byte memory space on the ADSP-218xN series supports

read and write operations as well as four different data formats.

The byte memory uses data bits 15–8 for data. The byte mem-

ory uses data bits 23–16 and address bits 13–0 to create a 22-bit

address. This allows up to a 4 megabit

؋

8 (32 megabit) ROM

or RAM to be used without glue logic. All byte memory accesses

are timed by the BMWAIT register and the wait state mode bit.

The CMS pin functions like the other memory select signals

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at

reset, except the BMS bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The byte memory DMA controller (Figure 13) allows loading

and storing of program instructions and data using the byte

memory space. The BDMA circuit is able to access the byte

memory space while the processor is operating normally and

steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.

See Figure 11 and Figure 12 for illustration of the programma-

ble flag and composite control register and the system

control register.

Byte Memory Select

The ADSP-218xN’s BMS disable feature combined with the

CMS pin allows use of multiple memories in the byte memory

space. For example, an EPROM could be attached to the BMS

Rev. A

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ADSP-218xN

The BDMA Context Reset bit (BCR) controls whether the pro-

cessor is held off while the BDMA accesses are occurring.

Setting the BCR bit to 0 allows the processor to continue opera-

tions. Setting the BCR bit to 1 causes the processor to stop

execution while the BDMA accesses are occurring, to clear the

context of the processor, and start execution at address 0 when

the BDMA accesses have completed.

BDMA CONTROL

14

0

12

0

15

0

13

0

11 10

9

0

8

0

7

0

6

0

5

0

4

0

3

1

2

0

1

0

DM (0x3FE3)

BTYPE

BDIR

0 = LOAD FROM BM

1 = STORE TO BM

BMPAGE

BDMA

OVERLAY

BITS

(SEE TABLE 12)

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

The BDMA overlay bits specify the OVLAY memory blocks to

be accessed for internal memory. Set these bits as indicated in

Figure 13.

Figure 13. BDMA Control Register

Note: BDMA cannot access external overlay memory regions 1

The BDMA circuit supports four different data formats that are

selected by the BTYPE register field. The appropriate number of

8-bit accesses are done from the byte memory space to build the

word size selected. Table 7 shows the data formats supported by

the BDMA circuit.

and 2.

The BMWAIT field, which has four bits on ADSP-218xN series

members, allows selection up to 15 wait states for BDMA

transfers.

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

Table 7. Data Formats

Internal Memory

Space

The IDMA Port provides an efficient means of communication

between a host system and ADSP-218xN series members. The

port is used to access the on-chip program memory and data

memory of the DSP with only one DSP cycle per word over-

head. The IDMA port cannot, however, be used to write to the

DSP’s memory-mapped control registers. A typical IDMA

transfer process is shown as follows:

BTYPE

00

Word Size

Alignment

Full Word

MSBs

Program Memory

Data Memory

24

16

8

01

10

11

8

LSBs

1. Host starts IDMA transfer.

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address for

the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally, the 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

2. Host checks IACK control line to see if the DSP is busy.

3. Host uses IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selec-

tion into the DSP’s IDMA control registers. If Bit 15 = 1,

the values of Bits 7–0 represent the IDMA overlay; Bits

14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13–0

represent the starting address of internal memory to be

accessed and Bit 14 reflects PM or DM for access. Set

IDDMOVLAY and IDPMOVLAY bits in the IDMA over-

lay register as indicted in Table 8.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

4. Host uses IS and IRD (or IWR) to read (or write) DSP

internal memory (PM or DM).

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

5. Host checks IACK line to see if the DSP has completed the

previous IDMA operation.

6. Host ends IDMA transfer.

The source or destination of a BDMA transfer will always be on-

chip program or data memory.

Table 8. IDMA/BDMA Overlay Bits

When the BWCOUNT register is written with a nonzero value

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to

external memory have priority over BDMA byte mem-

ory accesses.

IDMA/BDMA

PMOVLAY

IDMA/BDMA

DMOVLAY

Processor

ADSP-2184N

ADSP-2185N

ADSP-2186N

ADSP-2187N

ADSP-2188N

ADSP-2189N

0

0, 4, 5

0, 4, 5, 6, 7

0, 4, 5

0, 4, 5, 6, 7, 8

0, 4, 5, 6, 7

Rev. A

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ADSP-218xN

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is com-

pletely asynchronous and can be written while the ADSP-218xN

is operating at full speed.

IDMA OVERLAY

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

0

1

0

DM (0x3FE7)

RESERVED SET TO 0

IDDMOVLAY

IDPMOVLAY

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device

can therefore access a block of sequentially addressed memory

by specifying only the starting address of the block. This

increases throughput as the address does not have to be sent for

each memory access.

(SEE TABLE 12)

SHORT READ

ONLY

0 = DISABLE

1 = ENABLE

IDMA CONTROL (U = UNDEFINED AT RESET)

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

U

DM (0x3FE0)

IDMA port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a 14-bit

address and 1-bit destination type can be driven onto the bus by

an external device. The address specifies an on-chip memory

location, the destination type specifies whether it is a DM or PM

access. The falling edge of the IDMA address latch signal (IAL)

or the missing edge of the IDMA select signal (IS) latches this

value into the IDMAA register.

IDMAA ADDRESS

IDMAD DESTINATION MEMORY

TYPE

0 = PM

1 = DM

RESERVED SET TO 0

NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE

BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS.

Figure 14. IDMA OVLAY/Control Registers

The BDMA interface is set up during reset to the following

defaults when BDMA booting is specified: the BDIR, BMPAGE,

BIAD, and BEAD registers are set to 0, the BTYPE register is set

to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at address 0.

Once the address is stored, data can be read from, or written to,

the ADSP-218xN’s on-chip memory. Asserting the select line

(IS) and the appropriate read or write line (IRD and IWR

respectively) signals the ADSP-218xN that a particular transac-

tion is required. In either case, there is a one-processor-cycle

delay for synchronization. The memory access consumes one

additional processor cycle.

Once an access has occurred, the latched address is automati-

cally incremented, and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation.

Asserting the IDMA port select (IS) and address latch enable

(IAL) directs the ADSP-218xN to write the address onto the

IAD14–0 bus into the IDMA Control Register (Figure 14). If Bit

15 is set to 0, IDMA latches the address. If Bit 15 is set to 1,

IDMA latches into the OVLAY register. This register, also

shown in Figure 14, is memory-mapped at address DM

(0x3FE0). Note that the latched address (IDMAA) cannot be

read back by the host.

The ADSP-2100 Family development software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory space-compatible boot code.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the addres-

ses to boot memory must be constructed externally to the

ADSP-218xN. The only memory address bit provided by the

processor is A0.

IDMA Port Booting

When Bit 14 in 0x3FE7 is set to zero, short reads use the timing

shown in Figure 36 on Page 38. When Bit 14 in 0x3FE7 is set to

1, timing in Figure 37 on Page 39 applies for short reads in short

read only mode. Set IDDMOVLAY and IDPMOVLAY bits in

the IDMA overlay register as indicated in Table 8. Refer to the

ADSP-218x DSP Hardware Reference for additional details.

ADSP-218xN series members can also boot programs through

its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A

= 1, the ADSP-218xN boots from the IDMA port. IDMA feature

can load as much on-chip memory as desired. Program execu-

tion is held off until the host writes to on-chip program memory

location 0.

Note: In full memory mode all locations of 4M-byte memory

space are directly addressable. In host memory mode, only

address pin A0 is available, requiring additional external logic to

provide address information for the byte.

BUS REQUEST AND BUS GRANT

ADSP-218xN series members can relinquish control of the data

and address buses to an external device. When the external

device requires access to memory, it asserts the Bus Request

Bootstrap Loading (Booting)

ADSP-218xN series members have two mechanisms to allow

automatic loading of the internal program memory after reset.

The method for booting is controlled by the Mode A, B, and C

configuration bits.

When the mode pins specify BDMA booting, the ADSP-218xN

initiates a BDMA boot sequence when reset is released.

Rev. A

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ADSP-218xN

(BR) signal. If the ADSP-218xN is not performing an external

memory access, it responds to the active BR input in the follow-

ing processor cycle by:

INSTRUCTION SET DESCRIPTION

The ADSP-218xN series assembly language instruction set has

an algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full advantage

of the processor’s unique architecture, offers the follow-

ing benefits:

• Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

• Asserting the bus grant (BG) signal, and

• Halting program execution.

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical arith-

metic add instruction, such as AR = AX0 + AY0, resembles

a simple equation.

If Go Mode is enabled, the ADSP-218xN will not halt program

execution until it encounters an instruction that requires an

external memory access.

• Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

If an ADSP-218xN series member is performing an external

memory access when the external device asserts the BR signal, it

will not three-state the memory interfaces nor assert the BG sig-

nal until the processor cycle after the access completes. The

instruction does not need to be completed when the bus is

granted. If a single instruction requires two external memory

accesses, the bus will be granted between the two accesses.

• The syntax is a superset ADSP-2100 Family assembly lan-

guage and is completely source and object code compatible

with other family members. Programs may need to be

relocated to utilize on-chip memory and conform to the

ADSP-218xN’s interrupt vector and reset vector map.

• Sixteen condition codes are available. For conditional

jump, call, return, or arithmetic instructions, the condition

can be checked and the operation executed in the same

instruction cycle.

When the BR signal is released, the processor releases the BG

signal, re-enables the output drivers, and continues program

execution from the point at which it stopped.

The bus request feature operates at all times, including when the

processor is booting and when RESET is active.

• Multifunction instructions allow parallel execution of an

arithmetic instruction, with up to two fetches or one write

to processor memory space, during a single instruc-

tion cycle.

The BGH pin is asserted when an ADSP-218xN series member

requires the external bus for a memory or BDMA access, but is

stopped. The other device can release the bus by deasserting bus

request. Once the bus is released, the ADSP-218xN deasserts BG

and BGH and executes the external memory access.

DEVELOPMENT SYSTEM

Analog Devices’ wide range of software and hardware

development tools supports the ADSP-218xN series. The DSP

tools include an integrated development environment, an evalu-

ation kit, and a serial port emulator.

VisualDSP++^®^†is an integrated development environment,

allowing for fast and easy development, debug, and deployment.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy-to-use assembler that is based on an algebraic

syntax; an archiver (librarian/library builder); a linker; a

PROM-splitter utility; a cycle-accurate, instruction-level simu-

lator; a C compiler; and a C run-time library that includes DSP

and mathematical functions.

FLAG I/O PINS

ADSP-218xN series members have eight general-purpose pro-

grammable input/output flag pins. They are controlled by two

memory-mapped registers. The PFTYPE register determines

the direction, 1 = output and 0 = input. The PFDATA register is

used to read and write the values on the pins. Data being read

from a pin configured as an input is synchronized to the

ADSP-218xN’s clock. Bits that are programmed as outputs

will read the value being output. The PF pins default to input

during reset.

In addition to the programmable flags, ADSP-218xN series

members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.

FL0 to FL2 are dedicated output flags. FI and FO are available as

an alternate configuration of SPORT1.

Debugging both C and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C and assembly code (interleaved source and

object information)

Note: Pins PF0, PF1, PF2, and PF3 are also used for device con-

figuration during reset.

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

^†VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. A

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Page 15 of 48

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August 2006

ADSP-218xN

• Fill and dump memory

• Source level debugging

• Complete assembly and disassembly of instructions

• C source-level debugging

The VisualDSP++ IDE lets programmers define and manage

DSP software development. The dialog boxes and property

pages let programmers configure and manage all of the ADSP-

218xN development tools, including the syntax highlighting in

the VisualDSP++ editor. This capability controls how the devel-

opment tools process inputs and generate outputs.

The ADSP-2189M EZ-KIT Lite^®^†provides developers with a

cost-effective method for initial evaluation of the powerful

ADSP-218xN DSP family architecture. The ADSP-2189M EZ-

KIT Lite includes a stand-alone ADSP-2189M DSP board sup-

ported by an evaluation suite of VisualDSP++. With this EZ-

KIT Lite, users can learn about DSP hardware and software

development and evaluate potential applications of the ADSP-

218xN series. The ADSP-2189M EZ-KIT Lite provides an evalu-

ation suite of the VisualDSP++ development environment with

the C compiler, assembler, and linker. The size of the DSP exe-

cutable that can be built using the EZ-KIT Lite tools is limited to

8K words.

Designing an EZ-ICE-Compatible System

ADSP-218xN series members have on-chip emulation support

and an ICE-Port, a special set of pins that interface to the EZ-

ICE. These features allow in-circuit emulation without replac-

ing the target system processor by using only a 14-pin

connection from the target system to the EZ-ICE. Target sys-

tems must have a 14-pin connector to accept the EZ-ICE’s in-

circuit probe, a 14-pin plug.

Note: The EZ-ICE uses the same V_DDvoltage as the V_DDvoltage

used for V_DDEXT. Because the input pins of the ADSP-218xN

series members are tolerant to input voltages up to 3.6 V,

regardless of the value of V_DDEXT, the voltage setting for the EZ-

ICE must not exceed 3.3 V.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

PRIOR to issuing a chip reset command from the emulator user

interface. If a passive method of maintaining mode information

is being used (as discussed in Setting Memory Mode on Page 5),

it does not matter that the mode information is latched by an

emulator reset. However, if the RESET pin is being used as a

method of setting the value of the mode pins, the effects of an

emulator reset must be taken into consideration.

The EZ-KIT Lite includes the following features:

• 75 MHz ADSP-2189M

• Full 16-Bit Stereo Audio I/O with AD73322 Codec

• RS-232 Interface

• EZ-ICE Connector for Emulator Control

• DSP Demonstration Programs

One method of ensuring that the values located on the mode

pins are those desired is to construct a circuit like the one shown

in Figure 15. This circuit forces the value located on the Mode A

pin to logic high, regardless of whether it is latched via the

RESET or ERESET pin.

• Evaluation Suite of VisualDSP++

The ADSP-218x EZ-ICE^®^‡Emulator provides an easier and

more cost-effective method for engineers to develop and opti-

mize DSP systems, shortening product development cycles for

faster time-to-market. ADSP-218xN series members integrate

on-chip emulation support with a 14-pin ICE-Port interface.

This interface provides a simpler target board connection that

requires fewer mechanical clearance considerations than other

ADSP-2100 Family EZ-ICEs. ADSP-218xN series members

need not be removed from the target system when using the EZ-

ICE, nor are any adapters needed. Due to the small footprint of

the EZ-ICE connector, emulation can be supported in final

board designs.The EZ-ICE performs a full range of functions,

including:

ERESET

RESET

ADSP-218xN

1k⍀

MODE A/PF0

PROGRAMMABLE I/O

Figure 15. Mode A Pin/EZ-ICE Circuit

• In-target operation

The ICE-Port interface consists of the following ADSP-218xN

pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and

ELOUT.

• Up to 20 breakpoints

• Single-step or full-speed operation

• Registers and memory values can be examined and altered

• PC upload and download functions

These ADSP-218xN pins must be connected only to the EZ-ICE

connector in the target system. These pins have no function

except during emulation, and do not require pull-up or pull-

down resistors. The traces for these signals between the

ADSP-218xN and the connector must be kept as short as possi-

ble, no longer than 3 inches.

• Instruction-level emulation of program booting

and execution

The following pins are also used by the EZ-ICE: BR, BG, RESET,

and GND.

^†EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

^‡EZ-ICE is a registered trademark of Analog Devices, Inc.

Rev. A

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ADSP-218xN

The EZ-ICE uses the EE (emulator enable) signal to take control

of the ADSP-218xN in the target system. This causes the proces-

sor to use its ERESET, EBR, and EBG pins instead of the RESET,

BR, and BG pins. The BG output is three-stated. These signals

do not need to be jumper-isolated in the system.

difficult to manufacture, as DSP components statistically vary in

switching characteristic and timing requirements, within pub-

lished limits.

Restriction: All memory strobe signals on the ADSP-218xN

(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target

system must have 10 kΩ pull-up resistors connected when the

EZ-ICE is being used. The pull-up resistors are necessary

because there are no internal pull-ups to guarantee their state

during prolonged three-state conditions resulting from typical

EZ-ICE debugging sessions. These resistors may be removed

when the EZ-ICE is not being used.

The EZ-ICE connects to the target system via a ribbon cable and

a 14-pin female plug. The female plug is plugged onto the 14-

pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in

Figure 16. This connector must be added to the target board

design to use the EZ-ICE. Be sure to allow enough room in the

system to fit the EZ-ICE probe onto the 14-pin connector.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some

system signals changes. Design the system to be compatible with

the following system interface signal changes introduced by the

EZ-ICE board:

2

4

1

3

5

GND

EBG

EBR

BG

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the

RESET signal.

BR

6

EINT

ELIN

ECLK

EMS

ERESET

8

7

؋

• EZ-ICE emulation introduces an 8 ns propagation

delay between the target circuitry and the DSP on the BR

signal.

KEY (NO PIN)

9

10

12

14

ELOUT

11

13

• EZ-ICE emulation ignores RESET and BR, when

single-stepping.

EE

RESET

• EZ-ICE emulation ignores RESET and BR when in Emula-

tor Space (DSP halted).

TOP VIEW

Figure 16. Target Board Connector for EZ-ICE

• EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of

the DSP’s external memory bus only if bus grant (BG) is

asserted by the EZ-ICE board’s DSP.

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—Pin 7 must be removed from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spacing

should be 0.1

؋

0.1 inch. The pin strip header must have at least

0.15 inch clearance on all sides to accept the EZ-ICE probe plug.

ADDITIONAL INFORMATION

This data sheet provides a general overview of ADSP-218xN

series functionality. For additional information on the architec-

ture and instruction set of the processor, refer to the ADSP-218x

DSP Hardware Reference and the ADSP-218x DSP Instruction

Set Reference.

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

Target Memory Interface

For the target system to be compatible with the EZ-ICE emula-

tor, it must comply with the following memory interface

guidelines:

Design the Program Memory (PM), Data Memory (DM), Byte

Memory (BM), I/O Memory (IOM), and Composite Memory

(CM) external interfaces to comply with worst-case device

timing requirements and switching characteristics as specified

in this data sheet. The performance of the EZ-ICE may

approach published worst-case specification for some memory

access timing requirements and switching characteristics.

Note: If the target does not meet the worst-case chip specifica-

tion for memory access parameters, the circuitry may not be

able to be emulated at the desired CLKIN frequency. Depending

on the severity of the specification violation, the system may be

Rev. A

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ADSP-218xN

PIN DESCRIPTIONS

ADSP-218xN series members are available in a 100-lead LQFP

package and a 144-ball BGA package. In order to maintain max-

imum functionality and reduce package size and pin count,

some serial port, programmable flag, interrupt and external bus

pins have dual, multiplexed functionality. The external bus pins

are configured during RESET only, while serial port pins are

software configurable during program execution. Flag and

interrupt functionality is retained concurrently on multiplexed

pins. In cases where pin functionality is reconfigurable, the

default state is shown in plain text in Table 9, while alternate

functionality is shown in italics.

Table 9. Common-Mode Pins

Pin Name

RESET

BR

No. of Pins

I/O

I

Function

1

Processor Reset Input

I

Bus Request Input

BG

O

I

Bus Grant Output

BGH

Bus Grant Hung Output

DMS

Data Memory Select Output

PMS

Program Memory Select Output

Memory Select Output

IOMS

BMS

Byte Memory Select Output

CMS

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

Edge- or Level-Sensitive Interrupt Request¹

Programmable I/O Pin

RD

WR

IRQ2

PF7

I/O

I

IRQL1

PF6

1

Level-Sensitive Interrupt Requests¹

I/O

I

Programmable I/O Pin

IRQL0

PF5

Level-Sensitive Interrupt Requests¹

Programmable I/O Pin

Edge-Sensitive Interrupt Requests¹

I/O

I

IRQE

PF4

I/O

I

Programmable I/O Pin

Mode D

PF3

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Mode Select Input—Checked Only During RESET

Programmable I/O Pin During Normal Operation

Clock Input

I/O

I

Mode C

PF2

I/O

I

Mode B

PF1

I/O

I

Mode A

PF0

I/O

I

CLKIN

XTAL

1

5

O

I/O

Quartz Crystal Output

CLKOUT

SPORT0

SPORT1

IRQ1–0, FI, FO

PWD

Processor Clock Output

Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts, FI, FO²

1

I

Power-Down Control Input

PWDACK

FL0, FL1, FL2

V_DDINT

V_DDEXT

GND

1

O

I

Power-Down Acknowledge Control Output

Output Flags

3

2

Internal V_DD(1.8 V) Power (LQFP)

External V_DD(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)

Ground (LQFP)

4

I

10

I

Rev. A

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ADSP-218xN

Table 9. Common-Mode Pins (Continued)

Pin Name

V_DDINT

No. of Pins

I/O

Function

4

I

Internal V_DD(1.8 V) Power (BGA)

External V_DD(1.8 V, 2.5 V, or 3.3 V) Power (BGA)

Ground (BGA)

V_DDEXT

7

I

GND

20

I

EZ-Port

9

I/O

For Emulation Use

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector

address when the pin is asserted, either by external devices or set as a programmable flag.

²SPORT configuration determined by the DSP System Control Register. Software configurable.

The operating mode is determined by the state of the Mode C

pin during RESET and cannot be changed while the processor is

running. Table 10 and Table 11 list the active signals at specific

pins of the DSP during either of the two operating modes (Full

Memory or Host). A signal in one table shares a pin with a sig-

nal from the other table, with the active signal determined by

the mode that is set. For the shared pins and their alternate sig-

nals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on

Page 41 and Table 28 on Page 43.

MEMORY INTERFACE PINS

ADSP-218xN series members can be used in one of two modes:

Full Memory Mode, which allows BDMA operation with full

external overlay memory and I/O capability, or Host Mode,

which allows IDMA operation with limited external addressing

capabilities.

Table 10. Full Memory Mode Pins (Mode C = 0)

Pin Name

A13–0

No. of Pins

I/O

O

Function

14

24

Address Output Pins for Program, Data, Byte, and I/O Spaces

D23–0

I/O

Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory

Addresses.)

Table 11. Host Mode Pins (Mode C = 1)

Pin Name

IAD15–0

A0

No. of Pins

I/O

Function

16

1

I/O

IDMA Port Address/Data Bus

O

Address Pin for External I/O, Program, Data, or Byte Access¹

Data I/O Pins for Program, Data, Byte, and I/O Spaces

IDMA Write Enable

D23–8

IWR

16

1

I/O

I

IRD

1

I

IDMA Read Enable

IAL

1

I

IDMA Address Latch Pin

IS

1

I

IDMA Select

IACK

1

O

IDMA Port Acknowledge Configurable in Mode D; Open Drain

¹In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.

TERMINATING UNUSED PINS

Table 12 shows the recommendations for terminating unused

pins.

Table 12. Unused Pin Terminations

I/O

3-State

Reset

State

Pin Name¹

XTAL

(Z)²

Hi-Z³Caused By

Unused Configuration

O

Float

Float⁴

Float

CLKOUT

A13–1 or

IAD12–0

A0

O

O (Z)

I/O (Z)

O (Z)

Hi-Z

BR, EBR

IS

BR, EBR

Rev. A

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August 2006

ADSP-218xN

Table 12. Unused Pin Terminations (Continued)

I/O

3-State

Reset

State

Pin Name¹

D23–8

D7 or

IWR

(Z)²

Hi-Z³Caused By

BR, EBR

Unused Configuration

I/O (Z)

Hi-Z

I

Float

I/O (Z)

BR, EBR

Float

I

High (Inactive)

Float

D6 or

IRD

I/O (Z)

Hi-Z

I

BR, EBR

I

High (Inactive)

Float

D5 or

IAL

I/O (Z)

Hi-Z

I

Low (Inactive)

Float

D4 or

IS

I/O (Z)

I

Hi-Z

I

BR, EBR

High (Inactive)

Float

D3 or

IACK

D2–0 or

IAD15–13

PMS

I/O (Z)

Hi-Z

Float

I/O (Z)

O (Z)

I

Hi-Z

O

BR, EBR

IS

Float

BR, EBR

Float

DMS

BMS

O

Float

O

Float

IOMS

CMS

O

Float

O

Float

RD

O

Float

WR

O

Float

BR

I

High (Inactive)

Float

BG

O (Z)

O

EE

BGH

O

Float

IRQ2/PF7

I/O (Z)

I

Input = High (Inactive) or Program as Output, Set to

1, Let Float⁵

IRQL1/PF6

IRQL0/PF5

IRQE/PF4

I/O (Z)

I

Input = High (Inactive) or Program as Output, Set to

1, Let Float⁵

Input = High (Inactive) or Program as Output, Set to

1, Let Float⁵

Input = High (Inactive) or Program as Output, Set to

1, Let Float⁵

PWD

I

High

SCLK0

RFS0

I/O

I

Input = High or Low, Output = Float

I

High or Low

DR0

I

High or Low

TFS0

I/O

O

I

High or Low

DT0

O

I

Float

SCLK1

RFS1/IRQ0

DR1/FI

TFS1/IRQ1

DT1/FO

EE

I/O

I

Input = High or Low, Output = Float

I

High or Low

Float

I

I/O

O

I

O

I

Float

EBR

I

Float

EBG

O

Float

Rev. A

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August 2006

ADSP-218xN

Table 12. Unused Pin Terminations (Continued)

I/O

3-State

Reset

State

Pin Name¹

ERESET

EMS

(Z)²

Hi-Z³Caused By

Unused Configuration

I

Float

O

I

O

I

EINT

ECLK

I

ELIN

I

ELOUT

O

¹CLKIN, RESET, and PF3–0/Mode D–A are not included in this table because these pins must be used.

²All bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive.

³Hi-Z = High Impedance.

⁴If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register.

⁵If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts

and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float.

Rev. A

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ADSP-218xN

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade (Commercial)

B Grade (Industrial)

Parameter¹

Unit

Min

Max

1.89

Min

Max

V_DDINT

V_DDEXT

1.71

1.8

2.0

V

1.71

3.6

1.8

3.6

V

2

V_INPUT

V_IL= – 0.3

0

V_IH= + 3.6

70

V_IL= – 0.3

–40

V_IH= + 3.6

+85

V

T_AMB

°C

¹Specifications subject to change without notice.

²The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max V_IH), but voltage compliance (on outputs, V_OH) depends on the input V_DDEXT, because V_OH(max)

approximately equals V_DDEXT(max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–A1, PF7–PF0) and input-

only pins (CLKIN, RESET, BR, DR0, DR1, PWD).

ELECTRICAL CHARACTERISTICS

Parameter¹

Description

Hi-Level Input Voltage^{2, 3}

Test Conditions

Min

Typ

Max

Unit

V_IH

@ V_DDEXT= 1.71 V to 2.0 V,

V_DDINT= max

1.25

V

@ V_DDEXT= 2.1 V to 3.6 V,

V_DDINT= max

1.7

V

V_IL

Lo-Level Input Voltage^{2, 3}

@ V_DDEXT≤ 2.0 V,

V_DDINT= min

@ V_DDEXT≥ 2.0 V,

V_DDINT= min

0.6

0.7

V

V_OH

Hi-Level Output Voltage^{2, 4, 5}

@ V_DDEXT= 1.71 V to 2.0 V,

I_OH= – 0.5 mA

@ V_DDEXT= 2.1 V to 2.9 V,

I_OH= – 0.5 mA

@ V_DDEXT= 3.0 V to 3.6 V,

I_OH= – 0.5 mA

1.35

V

2.0

2.4

@ V_DDEXT= 1.71 V to 3.6 V,

V_DDEXT– 0.3

I_OH= – 100 μA⁶

V_OL

I_IH

Lo-Level Output Voltage^{2, 4, 5}

Hi-Level Input Current³

@ V_DDEXT= 1.71 V to 3.6 V,

I_OL= 2.0 mA

0.4

10

V

@ V_DDINT= max,

V_IN= 3.6 V

μA

mA

I_IL

Lo-Level Input Current³

@ V_DDINT= max,

V_IN= 0 V

I_OZH

I_OZL

I_DD

Three-State Leakage Current⁷

Supply Current (Idle)⁹

@ V_DDEXT= max,

V_IN= 3.6 V⁸

@ V_DDEXT= max,

V_IN= 0 V⁸

@ V_DDINT= 1.8 V,

6

t

_CK= 12.5 ns,

T_AMB= 25°C

I_DD

Supply Current (Dynamic)¹⁰

@ V_DDINT= 1.8 V,

t_CK= 12.5 ns¹¹,

T_AMB= 25°C

25

mA

Rev. A

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August 2006

ADSP-218xN

Parameter¹

Description

Supply Current (Idle)⁹

Test Conditions

Min

Typ

Max

Unit

I_DD

@ V_DDINT= 1.9 V,

t_CK= 12.5 ns,

T_AMB= 25°C

6.5

mA

I_DD

C_I

Supply Current (Dynamic)¹⁰

Supply Current (Power-Down)¹²

Input Pin Capacitance^{3, 6}

@ V_DDINT= 1.9 V,

t_CK= 12.5 ns¹¹,

T_AMB= 25°C

@ V_DDINT= 1.8 V,

T_AMB= 25°C

26

mA

μA

pF

100

in Lowest Power Mode

@ V_IN= 1.8 V,

f_IN= 1.0 MHz,

T_AMB= 25°C

@ V_IN= 1.8 V,

f_IN= 1.0 MHz,

T_AMB= 25°C

8

C_O

Output Pin Capacitance^{6, 7, 12, 13}

pF

¹Specifications subject to change without notice.

²Bidirectional pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–FL0, BGH.

⁵Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to V_DDEXTand GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0.

⁸0 V on BR.

⁹Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either V_DDor GND.

10

I

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type

DD

6, and 20% are idle instructions.

IN

11

V

= 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section.

¹²See ADSP-218x DSP Hardware Reference for details.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

1

Internal Supply Voltage (V_DDINT

)

–0.3 V to +2.2 V

–0.3 V to +4.0 V

–0.5 V to +4.0 V

–0.5 V to V_DDEXT+0.5 V

–40°C to +85°C

–65°C to +150°C

External Supply Voltage (V_DDEXT

Input Voltage²

Output Voltage Swing³

)

Operating Temperature Range

Storage Temperature Range

¹Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only. Functional operation of the device at these

or any other conditions greater than those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

²Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1,

A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD).

³Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,

A0, DT0, DT1, CLKOUT, FL2–0, BGH).

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-218xN features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

Rev. A

|

Page 23 of 48

|

August 2006

ADSP-218xN

ESD DIODE PROTECTION

POWER DISSIPATION

During the power-up sequence of the DSP, differences in the

ramp-up rates and activation time between the two supplies can

cause current to flow in the I/O ESD protection circuitry. To

prevent damage to the ESD diode protection circuitry, Analog

Devices recommends including a bootstrap Schottky diode.

To determine total power dissipation in a specific application,

the following equation should be applied for each output: C

؋

V_DD²

؋

f

where:

C = load capacitance.

f = output switching frequency.

The bootstrap Schottky diode is connected between the core

and I/O power supplies, as shown in Figure 17. It protects the

ADSP-218xN processor from partially powering the I/O supply.

Including a Schottky diode will shorten the delay between the

supply ramps and thus prevent damage to the ESD diode pro-

tection circuitry. With this technique, if the core rail rises ahead

of the I/O rail, the Schottky diode pulls the I/O rail along with

the core rail.

Example: In an application where external data memory is used

and no other outputs are active, power dissipation is calculated

as follows:

Assumptions:

• External data memory is accessed every cycle with 50% of

the address pins switching.

DC INPUT

SOURCE

• External data memory writes occur every other cycle with

50% of the data pins switching.

I/O VOLTAGE

REGULATOR

V_DDEXT

• Each address and data pin has a 10 pF total load at the pin.

• Application operates at V_DDEXT= 3.3 V and t_CK= 30 ns.

Total Power Dissipation = P_INT+ (C

؋

V_DDEXT²

؋

f)

ADSP-218xN

CORE

VOLTAGE

REGULATOR

V_DDINT

P

_INT= internal power dissipation from Figure 22 on Page 27.

Figure 17. Dual Voltage Schottky Diode

(C

؋

V_DDEXT²

؋

f) is calculated for each output, as in the exam-

ple in Table 13.

Table 13. Example Power Dissipation Calculation¹

Parameters

Address

No. of Pins

× C (pF)

10

× V_DDEXT²(V)

3.3²

× f (MHz)

20.0

PD (mW)

15.25

19.59

2.18

7

9

1

2

Data Output, WR

RD

10

20.0

10

20.0

CLKOUT, DMS

10

40.0

8.70

45.72

¹Total power dissipation for this example is P_INT+ 45.72 mW.

Rev. A

|

Page 24 of 48

|

August 2006

ADSP-218xN

ENVIRONMENTAL CONDITIONS

REFERENCE

SIGNAL

Table 14. Thermal Resistance

t_MEASURED

t_DIS

t_ENA

LQFP

(°C/W)

BGA

(°C/W)

V

OH

Rating Description¹

Symbol

(MEASURED)

V

(MEASURED) – 0.5V

(MEASURED) + 0.5V

OH

2.0V

1.0V

Thermal Resistance (Case- θ_CA

to-Ambient)

48

50

2

63.3

70.7

7.4

OUTPUT

V

OL

V

OL

t_DECAY

Thermal Resistance

(Junction-to-Ambient)

θ_JA

θ_JC

(MEASURED)

OUTPUT STARTS

DRIVING

OUTPUT STOPS

DRIVING

Thermal Resistance

(Junction-to-Case)

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

¹Where the Ambient Temperature Rating (T_AMB) is:

T_AMB= T_CASE– (PD × θ_CA

)

Figure 20. Output Enable/Disable

T_CASE= Case Temperature in °C

PD = Power Dissipation in W

Output Disable Time

TEST CONDITIONS

Output pins are considered to be disabled when they have

stopped driving and started a transition from the measured out-

put high or low voltage to a high impedance state. The output

disable time (t_DIS) is the difference of t_MEASUREDand t_DECAY, as

shown in Figure 20. The time is the interval from when a refer-

ence signal reaches a high or low voltage level to when the

output voltages have changed by 0.5 V from the measured out-

put high or low voltage.

INPUT

1.5V

2.0V

1.5V

0.8V

OUTPUT

The decay time, t_DECAY, is dependent on the capacitive load, C_L,

and the current load, i_L, on the output pin. It can be approxi-

mated by the following equation:

Figure 18. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

I_OL

C_L× 0.5V

-----------------------

t_DECAY

=

i_L

from which

TO

OUTPUT

1.5V

t_DIS= t_MEASURED– t_DECAY

50pF

is calculated. If multiple pins (such as the data bus) are disabled,

the measurement value is that of the last pin to stop driving.

I_OH

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to when they start

driving. The output enable time (t_ENA) is the interval from when

a reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in Figure 20. If multiple pins (such as the data bus) are enabled,

the measurement value is that of the first pin to start driving.

Figure 19. Equivalent Loading for AC Measurements (Including All Fixtures)

Rev. A

|

Page 25 of 48

|

August 2006

ADSP-218xN

TIMING SPECIFICATIONS

80

60

40

V

=

3.6V

@ –40؇C

DDEXT

This section contains timing information for the DSP’s

external signals.

V_DDEXT= 3.3V @ +25؇C

V_OH

V_DDEXT= 2.5V @ +85؇C

General Notes

20

0

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently,

parameters cannot be added up meaningfully to derive

longer times.

V_DDEXT= 1.8V @ +85؇C

V_DDEXT= 3.6V @ –40؇C

–20

–40

–60

–80

V

= 1.8/2.5V @ +85؇C

V _OL

V_D_D_D_D_E_E_X_X_T_T= 1.8/2.5V @ +85؇C

V_DDEXT= 3.3V @ +25؇C

Timing Notes

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE –

V

Switching characteristics specify how the processor changes its

signals. Designers have no control over this timing—circuitry

external to the processor must be designed for compatibility

with these signal characteristics. Switching characteristics tell

what the processor will do in a given circumstance. Switching

characteristics can also be used to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Figure 21. Typical Output Driver Characteristics

for V_DDEXTat 3.6 V, 3.3 V, 2.5 V, and 1.8 V

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Frequency Dependency For Timing Specifications

t_CKis defined as 0.5 t_CKI. The ADSP-218xN uses an input clock

with a frequency equal to half the instruction rate. For example,

a 40 MHz input clock (which is equivalent to 25 ns) yields a

12.5 ns processor cycle (equivalent to 80 MHz). t_CKvalues

within the range of 0.5 t_CKIperiod should be substituted for all

relevant timing parameters to obtain the specification value.

Example: t_CKH= 0.5 t_CK– 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25 ns

Output Drive Currents

Figure 21 shows typical I-V characteristics for the output driv-

ers on the ADSP-218xN series.The curves represent the current

drive capability of the output drivers as a function of

output voltage.

Figure 23 shows the typical power-down supply current.

Capacitive Loading

Figure 24 and Figure 25 show the capacitive loading characteris-

tics of the ADSP-218xN.

Rev. A

|

Page 26 of 48

|

August 2006

ADSP-218xN

1000

100

1, 2, 3

POWER, INTERNAL

V

= 2.0V

= 1.9V

= 1.8V

= 1.7V

DD

60

55

50

45

40

55m W

50 mW

45m W

40 mW

4 2mW

38m W

35

30

34 m W

30 m W

10

0

25

20

55

60

65

70

75

80

85

0

25

55

85

1/t_{C K}– MHz

TEMPERATURE – °C

NOTES

1 , 2, 4

POWER, IDLE

1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER

MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE

ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.)

2. CURRENT REFLECTS DEVICE OPERATING WITH NO

INPUT LOADS.

15.0

14.0

13.0

13.5m W

12 mW

12.0

11.0

10.0

10. 5m W

9.5m W

10.5m W

Figure 23. Typical Power-Down Current

9.0

8.0

7.0

6.0

5.0

9m W

8 .5 mW

7 .5 mW

30

T = 85؇C

V

= 0V TO 2.0V

DD

25

55

60

65

7 0

1/t_{C K}– MHz

75

80

8 5

20

15

2

POWER, IDLE n MODE S

12.0

10.0

8.0

12.0mW

10.5mW

10

5

9.5mW

8.5m W

V _{D D}C O RE = 1.9V

V _{D D}C OR E = 1.8V

5.2mW

6.0

4.0

2.0

0.0

0

4.9mW

4.7mW

4.3mW

50

0

100

150

– pF

200

250

300

4.2mW

3.8m W

3.4m W

C

L

Figure 24. Typical Output Rise Time vs. Load Capacitance (at Maximum

Ambient Operating Temperature)

55

60

65

70

75

80

8 5

18

1/t_{C K}– MHz

NOTES

16

14

VALID FOR ALL TEMPERATURE GRADES.

1

POWER REFLECTS DE VICE OPE RATING WITH NO OUTPUT

LOADS.

12

10

2

3

TYPICAL P OWER DISS IPATION AT 1.8V OR 1.9V V_{D D INT}AND

25°C, EX CEPT WHERE SPE CIFIED.

8

I_{D D}MEASUREMENT TAKE N WITH ALL INS TRUCTIONS

6

4

EXECUTING FRO M INT ERNAL MEMORY. 50% OF THE

INSTRUCTIO NS ARE MULT IFUNCTION (TYP ES 1, 4, 5, 12, 13,

14), 30% ARE TY PE 2 AND TYPE 6, AND 20% ARE IDLE

INSTRUCTIO NS.

2

4

IDLE RE FE RS TO S TATE OF OP ERATION DURING EX ECUTION

OF IDLE INSTRUCTION. DE ASSE RTED PINS ARE DRIVEN TO

EITHE R V_DDO R GND.

NOMINAL

–2

–4

–6

Figure 22. Power vs. Frequency

0

50

100

150

200

250

C_L– pF

Figure 25. Typical Output Valid Delay or Hold vs. Load Capacitance, C_L(at

Maximum Ambient Operating Temperature)

Rev. A

|

Page 27 of 48

|

August 2006

ADSP-218xN

Clock Signals and Reset

Table 15. Clock Signals and Reset

Parameter

Min

Max

Unit

Timing Requirements:

t_CKI

CLKIN Period

25

8

40

ns

t_CKIL

t_CKIH

CLKIN Width Low

CLKIN Width High

8

Switching Characteristics:

t_CKL

CLKOUT Width Low

0.5t_CK– 3

0

ns

t_CKH

t_CKOH

CLKOUT Width High

CLKIN High to CLKOUT High

8

Control Signals Timing Requirements:

1

t_RSP

t_MS

t_MH

RESET Width Low

5t_CK

ns

Mode Setup before RESET High

Mode Hold after RESET High

7

5

¹Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator

start-up time).

t_CKI

t_CKIH

CLKIN

t_CKIL

t_CKOH

t_CKH

CLKOUT

t_CKL

MODE A

D

t_MH

t_MS

RESET

t_RSP

Figure 26. Clock Signals and Reset

Rev. A

|

Page 28 of 48

|

August 2006

ADSP-218xN

Interrupts and Flags

Table 16. Interrupts and Flags

Parameter

Min

Max

Unit

Timing Requirements:

t_IFS

t_IFH

IRQx, FI, or PFx Setup before CLKOUT Low^{1, 2, 3, 4}

IRQx, FI, or PFx Hold after CLKOUT High^{1, 2, 3, 4}

0.25t_CK+ 10

0.25t_CK

ns

Switching Characteristics:

t_FOH

Flag Output Hold after CLKOUT Low⁵

t_FOD

Flag Output Delay from CLKOUT Low⁵

0.5t_CK– 5

ns

0.5t_CK+ 4

¹If IRQx and FI inputs meet t_IFSand t_IFHsetup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the

following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on

interrupt servicing.)

²Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

³IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

⁴PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

⁵Flag Outputs = PFx, FL0, FL1, FL2, FO.

t_FOD

CLKOUT

t_FOH

FLAG

OUTPUTS

t_IFH

IRQx

FI

PFx

t_IFS

Figure 27. Interrupts and Flags

Rev. A

|

Page 29 of 48

|

August 2006

ADSP-218xN

Bus Request–Bus Grant

Table 17. Bus Request–Bus Grant

Parameter

Min

Max

Unit

Timing Requirements:

t_BH

t_BS

BR Hold after CLKOUT High¹

BR Setup before CLKOUT Low¹

0.25t_CK+ 2

0.25t_CK+ 8

ns

Switching Characteristics:

t_SD

CLKOUT High to xMS, RD, WR Disable²

0.25t_CK+ 8

ns

t_SDB

t_SE

xMS, RD, WR Disable to BG Low

BG High to xMS, RD, WR Enable

xMS, RD, WR Enable to CLKOUT High

xMS, RD, WR Disable to BGH Low³

BGH High to xMS, RD, WR Enable³

0

t_SEC

t_SDBH

t_SEH

0.25t_CK– 3

0

¹BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on

the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

²xMS = PMS, DMS, CMS, IOMS, BMS.

³BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.

t_BH

CLKOUT

BR

t_BS

CLKOUT

PMS, DMS

BMS, RD

CMS, WR,

t_SD

t_SEC

IOMS

BG

t_SDB

t_SE

BGH

t_SDBH

t_SEH

Figure 28. Bus Request–Bus Grant

Rev. A

|

Page 30 of 48

|

August 2006

ADSP-218xN

Memory Read

Table 18. Memory Read

Parameter

Min

Max

Unit

Timing Requirements:

t_RDD

t_AA

RD Low to Data Valid¹

A13–0, xMS to Data Valid²

0.5t_CK– 5 + w

0.75t_CK– 6 + w

ns

t_RDH

Data Hold from RD High

0

Switching Characteristics:

t_RP

RD Pulse Width

0.5t_CK– 3 + w

0.25t_CK– 2

0.25t_CK– 3

0.5t_CK– 3

ns

t_CRD

CLKOUT High to RD Low

A13–0, xMS Setup before RD Low

A13–0, xMS Hold after RD Deasserted

RD High to RD or WR Low

.

0.25t_CK+ 4

t_ASR

t_RDA

t_RWR

¹w = wait states 3 t_CK

²xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

1

ADDRESS LINES

DMS, PMS,

BMS, IOMS,

CMS

t_RDA

t_RWR

t_RDH

RD

t_ASR

t_CRD

t_RP

2

DATA LINES

t_RDD

t_AA

WR

1

2

DATA LINES FOR ACCESSES ARE:

ADDRESS LINES FOR ACCESSES ARE:

BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)

I/O SPACE: A10–0

EXTERNAL PM AND DM: A13–0

BDMA: D15–8

I/O SPACE: D23–8

EXTERNAL DM: D23–8

EXTERNAL PM: D23–0

Figure 29. Memory Read

Rev. A

|

Page 31 of 48

|

August 2006

ADSP-218xN

Memory Write

Table 19. Memory Write

Parameter

Min

Max

Unit

Switching Characteristics:

t_DW

Data Setup before WR High¹

0.5t_CK– 4 + w

0.25t_CK– 1

0.5t_CK– 3 + w

0

ns

t_DH

Data Hold after WR High

WR Pulse Width

t_WP

t_WDE

WR Low to Data Enabled

A13–0, xMS Setup before WR Low²

Data Disable before WR or RD Low

CLKOUT High to WR Low

A13–0, xMS Setup before WR Deasserted

A13–0, xMS Hold after WR Deasserted

WR High to RD or WR Low

.

t_ASW

0.25t_CK– 3

0.25t_CK– 2

0.75t_CK– 5 + w

0.25t_CK– 1

0.5t_CK– 3

t_DDR

t_CWR

0.25t_CK+ 4

t_AW

t_WRA

t_WWR

¹w = wait states 3 t_CK

²xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

1

ADDRESS LINES

DMS, PMS,

BMS, CMS,

IOMS

t_WRA

WR

t_WWR

t_ASW

t_WP

t_AW

t_DH

t_DDR

t_CWR

2

DATA LINES

t_DW

t_WDE

RD

1

2

DATA LINES FOR ACCESSES ARE:

BDMA: D15–8

I/O SPACE: D23–8

EXTERNAL DM: D23–8

EXTERNAL PM: D23–0

ADDRESS LINES FOR ACCESSES ARE:

BDMA: A13–0 (14 LSBs), D23–16 (8 MSBs)

I/O SPACE: A10–0

EXTERNAL PM AND DM: A13–0

Figure 30. Memory Write

Rev. A

|

Page 32 of 48

|

August 2006

ADSP-218xN

Serial Ports

Table 20. Serial Ports

Parameter

Min

Max

Unit

Timing Requirements:

t_SCK

t_SCS

t_SCH

t_SCP

SCLK Period

30

4

ns

DR/TFS/RFS Setup Before SCLK Low

DR/TFS/RFS Hold After SCLK Low

SCLKIN Width

7

12

Switching Characteristics:

t_CC

CLKOUT High to SCLKOUT

0.25t_CK

0

0.25t_CK+ 6

ns

t_SCDE

t_SCDV

t_RH

SCLK High to DT Enable

SCLK High to DT Valid

7

TFS/RFS_OUTHold after SCLK High

TFS/RFS_OUTDelay from SCLK High

DT Hold after SCLK High

0

t_RD

t_SCDH

t_TDE

t_TDV

t_SCDD

t_RDV

0

TFS (Alt) to DT Enable

TFS (Alt) to DT Valid

7

SCLK High to DT Disable

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

t_CC

t_{S CK}

SCLK

t_{S CP}

t_SCS

t_SCH

t_SCP

DR

TFS_IN

RFS_IN

t_RD

t_RH

RFS_{O UT}

TFS_{O UT}

t_{S CDD}

t_SCDV

t_SCDH

t_{S CDE}

DT

t_TDE

t_TDV

TFS_{O UT}

ALTERNATE

FRAM E

M ODE

t_RDV

RFS_OUT

MULTICHANNE L

M ODE ,

FRAME DE LAY 0

t_TDE

( MFD

= 0)

t_TDV

TFS_IN

ALTE RNATE

FRAME

MO DE

t_RDV

RFS_IN

MULTICHANNE L

M ODE ,

FRAME DE LAY 0

( MFD

= 0)

Figure 31. Serial Ports

Rev. A

|

Page 33 of 48

|

August 2006

ADSP-218xN

IDMA Address Latch

Table 21. IDMA Address Latch

Parameter

Min

Max

Unit

Timing Requirements:

t_IALP

t_IASU

t_IAH

Duration of Address Latch^{1, 2}

10

5

ns

IAD15–0 Address Setup Before Address Latch End²

IAD15–0 Address Hold After Address Latch End²

IACK Low before Start of Address Latch^{2, 3}

Start of Write or Read After Address Latch End^{2, 3}

Address Latch Start After Address Latch End^{1, 2}

3

t_IKA

0

t_IALS

t_IALD

3

2

¹Start of Address Latch = IS Low and IAL High.

²End of Address Latch = IS High or IAL Low.

³Start of Write or Read = IS Low and IWR Low or IRD Low.

IACK

t_IKA

IAL

t_IALD

t_IALP

IS

IAD15–0

t_IASU

t_IAH

t_IALS

IRD OR IWR

Figure 32. IDMA Address Latch

Rev. A

|

Page 34 of 48

|

August 2006

ADSP-218xN

IDMA Write, Short Write Cycle

Table 22. IDMA Write, Short Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKW

t_IWP

t_IDSU

t_IDH

IACK Low Before Start of Write¹

Duration of Write^{1, 2}

IAD15–0 Data Setup Before End of Write^{2, 3, 4}

IAD15–0 Data Hold After End of Write^{2, 3, 4}

0

ns

10

3

2

Switching Characteristic:

t_IKHW

Start of Write to IACK High

10

ns

¹Start of Write = IS Low and IWR Low.

²End of Write = IS High or IWR High.

³If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

⁴If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

t_IKW

IACK

IS

t_IKHW

t_IWP

IWR

t_IDH

t_IDSU

DATA

IAD15–0

Figure 33. IDMA Write, Short Write Cycle

Rev. A

|

Page 35 of 48

|

August 2006

ADSP-218xN

IDMA Write, Long Write Cycle

Table 23. IDMA Write, Long Write Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKW

t_IKSU

t_IKH

IACK Low Before Start of Write¹

IAD15–0 Data Setup Before End of Write^{2, 3, 4}

IAD15–0 Data Hold After End of Write^{2, 3, 4}

0

ns

0.5t_CK+ 5

0

Switching Characteristics:

t_IKLW

Start of Write to IACK Low⁴

t_IKHWStart of Write to IACK High

1.5t_CK

ns

10

¹Start of Write = IS Low and IWR Low.

²If Write Pulse ends before IACK Low, use specifications t_IDSU, t_IDH

.

³If Write Pulse ends after IACK Low, use specifications t_IKSU, t_IKH

.

⁴This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.

t_IKW

IACK

t_IKHW

t_IKLW

IS

IWR

t_IKSU

t_IKH

DATA

IAD15–0

Figure 34. IDMA Write, Long Write Cycle

Rev. A

|

Page 36 of 48

|

August 2006

ADSP-218xN

IDMA Read, Long Read Cycle

Table 24. IDMA Read, Long Read Cycle

Parameter

Min

Max

Unit

Timing Requirements:

t_IKR

t_IRK

IACK Low Before Start of Read¹

End of read After IACK Low²

0

2

ns

Switching Characteristics:

t_IKHR

t_IKDS

t_IKDH

t_IKDD

t_IRDE

t_IRDV

t_IRDH1

t_IRDH2

IACK High After Start of Read¹

10

ns

IAD15–0 Data Setup Before IACK Low

IAD15 –0 Data Hold After End of Read²

IAD15–0 Data Disabled After End of Read²

0.5t_CK– 3

0

10

11

IAD15–0 Previous Data Enabled After Start of Read

IAD15–0 Previous Data Valid After Start of Read

IAD15–0 Previous Data Hold After Start of Read (DM/PM1)³

IAD15–0 Previous Data Hold After Start of Read (PM2)⁴

0

2t_CK– 5

t_CK– 5

¹Start of Read = IS Low and IRD Low.

²End of Read = IS High or IRD High.

³DM read or first half of PM read.

⁴Second half of PM read.

IACK

IS

t_IKHR

t_IKR

t_IRK

IRD

t_IKDH

t_IKDS

t_IRDE

READ

DATA

IAD15–0

t_IRDV

t_{IRDH1 OR}t_IRDH2

t_IKDD

Figure 35. IDMA Read, Long Read Cycle

Rev. A

|

Page 37 of 48

|

August 2006

ADSP-218xN

IDMA Read, Short Read Cycle

Table 25. IDMA Read, Short Read Cycle

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements:

t_IKR

IACK Low Before Start of Read³

Duration of Read (DM/PM1)⁴

Duration of Read (PM2)⁵

0

ns

t_IRP1

t_IRP2

Switching Characteristics:

10

2t_CK– 5

t_CK– 5

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High After Start of Read³

IAD15–0 Data Hold After End of Read⁶

IAD15–0 Data Disabled After End of Read⁶

IAD15–0 Previous Data Enabled After Start of Read

IAD15–0 Previous Data Valid After Start of Read

10

ns

0

¹Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is

disabled by default upon reset.

²Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.

³Start of Read = IS Low and IRD Low.

⁴DM Read or first half of PM Read.

⁵Second half of PM Read.

⁶End of Read = IS High or IRD High.

IACK

t_IKR

t_IKHR

IS

t_IRP

IRD

t_IKDH

t_IRDE

DATA

t_IKDD

t_IRDV

Figure 36. IDMA Read, Short Read Cycle

Rev. A

|

Page 38 of 48

|

August 2006

ADSP-218xN

IDMA Read, Short Read Cycle in Short Read Only Mode

Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode

Parameter¹

Min

Max

Unit

Timing Requirements:

t_IKR

t_IRP

IACK Low Before Start of Read²

Duration of Read³

0

ns

10

Switching Characteristics:

t_IKHR

t_IKDH

t_IKDD

t_IRDE

t_IRDV

IACK High After Start of Read²

10

ns

IAD15–0 Previous Data Hold After End of Read³

IAD15–0 Previous Data Disabled After End of Read³

IAD15–0 Previous Data Enabled After Start of Read

IAD15–0 Previous Data Valid After Start of Read

0

¹Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register

or by an external host writing to the register. Disabled by default.

²Start of Read = IS Low and IRD Low. Previous data remains until end of read.

³End of Read = IS High or IRD High.

IACK

t_IKR

t_IKHR

IS

t_IRP

IRD

t_IKDH

t_IRDE

IAD15–0

t_IKDD

t_{IR DV}

LEGEND :

IMPLIES THAT IS AND IRD CAN BE

HELD INDEFINITELY BY HOST

Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode

Rev. A

|

Page 39 of 48

|

August 2006

ADSP-218xN

value of the pin at the deassertion of RESET. The multiplexed

pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode

selectable by setting Bit 10 (SPORT1 configure) of the System

Control Register. If Bit 10 = 1, these pins have serial port func-

tionality. If Bit 10 = 0, these pins are the external interrupt and

flag pins. This bit is set to 1 by default, upon reset.

LQFP PACKAGE PINOUT

The LQFP package pinout is shown Figure 38 and in Table 27.

Pin names in bold text in the table replace the plain-text-named

functions when Mode C = 1. A + sign separates two functions

when either function can be active for either major I/O mode.

Signals enclosed in brackets [ ] are state bits latched from the

75 D15

74 D14

A4/IAD3

A5/IAD4

GND

1

2

3

4

5

6

7

8

9

PIN 1

IDENTIFIER

D13

73

72 D12

71 GND

70 D11

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

69

D10

68 D9

V_DDEXT

67

66 GND

65 D8

A12/IAD11 10

A13/IAD12 11

GND 12

64 D7/IWR

63 D6/IRD

ADSP-218xN

CLKIN 13

TOP VIEW

(Not to Scale)

XTAL

14

62

D5/IAL

V_DDEXT

61 D4/IS

15

60 GND

CLKOUT 16

GND 17

V_DDINT

59

V_DDINT

58 D3/IACK

57 D2/IAD15

56 D1/IAD14

55 D0/IAD13

54 BG

18

WR 19

RD 20

BMS 21

DMS 22

PMS 23

IOMS 24

CMS 25

53 EBG

52 BR

51 EBR

Figure 38. 100-Lead LQFP Pin Configuration

Rev. A

|

Page 40 of 48

|

August 2006

ADSP-218xN

Table 27. LQFP Package Pinout

Table 27. LQFP Package Pinout (Continued)

Pin No.

1

2

3

4

5

6

7

8

Pin Name

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Pin Name

EBR

BR

EBG

BG

D0/IAD13

D1/IAD14

D2/IAD15

D3/IACK

V_DDINT

GND

D4/IS

D5/IAL

D6/IRD

D7/IWR

D8

GND

V_DDEXT

D9

D10

D11

GND

D12

D13

D14

D15

D16

D17

D18

D19

GND

D20

D21

D22

D23

FL2

FL1

FL0

PF3 [Mode D]

PF2 [Mode C]

V_DDEXT

PWD

GND

A4/IAD3

A5/IAD4

GND

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

V_DDEXT

CLKOUT

GND

V_DDINT

WR

RD

BMS

DMS

PMS

IOMS

CMS

IRQE + PF4

IRQL0 + PF5

GND

IRQL1 + PF6

IRQ2 + PF7

DT0

TFS0

RFS0

DR0

SCLK0

V_DDEXT

DT1/FO

TFS1/IRQ1

RFS1/IRQ0

DR1/FI

GND

SCLK1

ERESET

RESET

EMS

EE

ECLK

ELOUT

ELIN

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

PF1 [Mode B]

PF0 [Mode A]

BGH

PWDACK

A0

A1/IAD0

A2/IAD1

A3/IAD2

EINT

Rev. A

|

Page 41 of 48

|

August 2006

ADSP-218xN

value of the pin at the deassertion of RESET. The multiplexed

pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode

selectable by setting Bit 10 (SPORT1 configure) of the System

Control Register. If Bit 10 = 1, these pins have serial port func-

tionality. If Bit 10 = 0, these pins are the external interrupt and

flag pins. This bit is set to 1 by default upon reset.

BGA PACKAGE PINOUT

The BGA package pinout is shown in Figure 39 and in Table 28.

Pin names in bold text in the table replace the plain text named

functions when Mode C = 1. A + sign separates two functions

when either function can be active for either major I/O mode.

Signals enclosed in brackets [ ] are state bits latched from the

1

12

11

10

9

8

7

6

5

4

3

2

A

B

GND

D22

NC

GND

NC

A0

GND

A1/IAD0

A2/IAD1

V_DDEXT

D16

D17

D18

D20

D23

GND

NC

GND

A3/IAD2

A4/IAD3

V_DDEXT

C

D

D14

GND

D10

D9

NC

D15

D12

D19

D13

GND

D11

D21

NC

PWD

A7/IAD6

A9/IAD8

A5/IAD4

BGH

RD

NC

A6/IAD5

WR

PWDACK

PF2

[MODE C]

PF1

[MODE B]

NC

PF3

[MODE D]

PF0

[MODE A]

V_DDEXT

E

F

GND

NC

GND

FL2

NC

FL0

A8/IAD7

D8

D7/IWR

NC

FL1

A11/IAD10 A12/IAD11

NC

A13/IAD12

G

H

D4/IS

NC

D5/IAL

D6/IRD

NC

A10/IAD9

GND

NC

XTAL

V_{DD IN T}

GND

D3/IACK

D2/IAD15

TFS0

DT0

GND

CLKIN

V_DDEXT

V_{DD IN T}

V_DDEXT

V_DDINT

J

D1/IAD14

BG

RFS1/IRQ0

D0/IAD13

SCLK0

RFS0

NC

CLKOUT

K

EBG

BR

EBR

ERESET

SCLK1

TFS1/IRQ1

DMS

BMS

NC

L

IRQL1 + PF6

EINT

ELOUT

EE

ELIN

RESET

GND

DR0

PMS

GND

IOMS

CMS

NC

IRQE + PF4

M

ECLK

EMS

NC

DR1/FI

DT1/FO

NC

IRQ2 + PF7 IRQL0 + PF5

Figure 39. 144-Ball BGA Package Pinout (Bottom View)

Rev. A

|

Page 42 of 48

|

August 2006

ADSP-218xN

Table 28. BGA Package Pinout

(Continued)

Ball No.

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

E01

Pin Name

A2/IAD1

A1/IAD0

GND

A0

NC

GND

NC

D22

GND

A4/IAD3

A3/IAD2

GND

NC

Ball No.

E02

E03

E04

E05

E06

E07

E08

E09

E10

E11

E12

F01

F02

F03

F04

F05

F06

F07

F08

F09

F10

F11

F12

G01

G02

G03

G04

G05

G06

G07

G08

G09

G10

G11

G12

H01

H02

H03

H04

H05

H06

H07

H08

H09

H10

H11

H12

J01

Pin Name

V_DDEXT

A8/IAD7

FL0

PF0 [MODE A]

FL2

PF3 [MODE D]

GND

V_DDEXT

GND

D10

A13/IAD12

NC

A12/IAD11

A11/IAD10

FL1

NC

D7/IWR

D11

D8

NC

D9

XTAL

NC

GND

V_DDEXT

D23

D20

D18

D17

D16

PWDACK

A6/IAD5

RD

A5/IAD4

A7/IAD6

PWD

V_DDEXT

D21

D19

D15

NC

D14

NC

WR

NC

BGH

A9/IAD8

PF1 [MODE B]

PF2 [MODE C]

NC

D13

D12

GND

A10/IAD9

NC

D6/IRD

D5/IAL

NC

D4/IS

CLKIN

GND

V_DDINT

DT0

TFS0

D2/IAD15

D3/IACK

GND

NC

GND

CLKOUT

V_DDINT

NC

GND

V_DDEXT

J02

Rev. A

|

Page 43 of 48

|

August 2006

ADSP-218xN

Table 28. BGA Package Pinout

(Continued)

Ball No.

J03

Pin Name

NC

J04

J05

J06

J07

J08

J09

V_DDEXT

SCLK0

D0/IAD13

RFS1/IRQ0

BG

J10

J11

J12

D1/IAD14

V_DDINT

NC

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

K12

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

L12

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

M12

NC

BMS

DMS

RFS0

TFS1/IRQ1

SCLK1

ERESET

EBR

BR

EBG

IRQE + PF4

NC

IRQL1 + PF6

IOMS

GND

PMS

DR0

GND

RESET

ELIN

ELOUT

EINT

IRQL0 + PF5

IRQL2 + PF7

NC

CMS

GND

DT1/FO

DR1/FI

GND

NC

EMS

EE

ECLK

Rev. A

|

Page 44 of 48

|

August 2006

ADSP-218xN

OUTLINE DIMENSIONS

A1 CORNER

INDEX AREA

10.10

10.00 SQ

9.90

9

7

11

5

4

3

1

2

12

10

8

6

A

B

C

D

E

F

BALL A1

INDICATOR

8.80

BSC

SQ

G

H

J

0.80

BSC

(BALL

PITCH)

K

L

M

BOTTOM VIEW

DETAIL A

TOP VIEW

DETAIL A

1.40

MAX

1.11

0.85

0.25

MIN

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARD MO-205-AC.

0.50

0.45

0.40

SEATING

PLANE

2. ACTUAL POSTION OF THE BALL GRID IS WITHIN

0.15 OF ITS IDEAL POSTION RELATIVE TO THE

PACKAGE EDGES.

0.12 MAX (BALL

COPLANARITY)

(BALL DIAMETER,

SEE NOTE 4)

3. CENTER DIMENSIONS ARE NOMINAL.

4. DIMENSION IN DRAWING IS FOR PB-FREE BALL.

PB-BEARING BALL DIMENSION IS 0.45/0.50/0.55.

Figure 40. 144-Ball BGA [CSP_BGA] (BC-144-6)

16.00 BSC SQ

14.00 BSC SQ

1.60 MAX

0.75

0.60

0.45

100

76

75

12°

TYP

1

SEATING

PLANE

12.00

REF

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

VIEW A

7°

3.5°

0°

25

26

51

50

0.15

0.05

SEATING

PLANE

0.08

MAX LEAD

COPLANARITY

0.27

0.50 BSC

0.22

0.17

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BED

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL

POSITION WHEN MEASURED IN THE LATERAL DIRECTION.

Figure 41. 100-Lead Low Profile Quad Flat Package [LQFP] (ST-100-1)

Rev. A

|

Page 45 of 48

|

August 2006

ADSP-218xN

SURFACE MOUNT DESIGN

Table 29 is provided as an aid to PCB design. For industry-stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface Mount Design and Land Pattern

Standard.

Table 29. BGA Data for Use with Surface Mount Design

Ball Attach

Type

Solder Mask

Opening

Package

Ball Pad Size

144-Ball BGA Solder Mask 0.40 mm

(BC-144-6) Defined diameter

0.50 mm

diameter

Rev. A

|

Page 46 of 48

|

August 2006

ADSP-218xN

ORDERING GUIDE

Temperature

Range¹

Instruction

Rate (MHz)

Package

Description

Package

Option

Model

ADSP-2184NBCA-320

ADSP-2184NBST-320

ADSP-2184NKCA-320

ADSP-2184NKST-320

ADSP-2184NKSTZ-320²

ADSP-2185NBCA-320

ADSP-2185NBST-320

ADSP-2185NBSTZ-320²

ADSP-2185NKCA-320

ADSP-2185NKST-320

ADSP-2185NKSTZ-320²

ADSP-2186NBCA-320

ADSP-2186NBST-320

ADSP-2186NBSTZ-320²

ADSP-2186NKCA-320

ADSP-2186NKST-320

ADSP-2186NKSTZ-320²

ADSP-2187NBCA-320

ADSP-2187NBST-320

ADSP-2187NBSTZ-320²

ADSP-2187NKCA-320

ADSP-2187NKST-320

ADSP-2187NKSTZ-320²

ADSP-2188NBCA-320

ADSP-2188NBST-320

ADSP-2188NBSTZ-320²

ADSP-2188NKCA-320

ADSP-2188NKCAZ-320²

ADSP-2188NKST-320

ADSP-2188NKSTZ-320²

ADSP-2189NBCA-320

ADSP-2189NBCAZ-320²

ADSP-2189NBST-320

ADSP-2189NBSTZ-320²

ADSP-2189NKCA-320

ADSP-2189NKCAZ-320²

ADSP-2189NKST-320

ADSP-2189NKSTZ-320²

–40°C to +85°C

0°C to 70°C

80

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

144-Ball CSP_BGA

100-Lead LQFP

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

BC-144-6

ST-100-1

0°C to 70°C

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

–40°C to +85°C

0°C to 70°C

¹Ranges shown represent ambient temperature.

²Z = Pb-free part.

Rev. A

|

Page 47 of 48

|

August 2006

ADSP-218xN

©

registered trademarks are the property of their respective owners.

C02666-0-8/06(A)

Rev. A

|

Page 48 of 48

|

August 2006


型号：	ADSP-2188NKSTZ-3202
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 电脑
文件：	总48页 (文件大小：1644K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2188NKSTZ-3202 [ADI]

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