ADSP-2191MKST-160X [ADI]
IC 16-BIT, 160 MHz, OTHER DSP, PQFP144, METRIC, PLASTIC, TQFP-144, Digital Signal Processor;型号: | ADSP-2191MKST-160X |
厂家: | ADI |
描述: | IC 16-BIT, 160 MHz, OTHER DSP, PQFP144, METRIC, PLASTIC, TQFP-144, Digital Signal Processor 微控制器和处理器 外围集成电路 数字信号处理器 电脑 时钟 |
文件: | 总52页 (文件大小:1735K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
a
DSP Microcomputer
ADSP-2191M
PERFORMANCE FEATURES
Multifunction Instructions
6.25 ns Instruction Cycle Time, for up to 160 MIPS
Sustained Performance
Pipelined Architecture Supports Efficient Code
Execution
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Architectural Enhancements for Compiled C and C++
Code Efficiency
Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-
putation and Memory Instructions
Instruction Cache Allows Dual Operand Fetches in Every
Instruction Cycle
Architectural Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, and Peripherals
Flexible Power Management with User-Selectable
Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
ADSP-219x
DSP CORE
JTAG
24 BIT
24 BIT
16 BIT
16 BIT
ADDRESS
DATA
DATA
DATA
DATA
6
ADDRESS
ADDRESS
TEST &
EMULATION
CACHE
64
؋
24-BIT ADDRESS
DAG1
4
؋
4 ؋
16 DAG2
4
؋
4 ؋
16 PROGRAM
SEQUENCER
EXTERNAL PORT
24
PM ADDRESS BUS
22
16
I/O ADDRESS
18
ADDR BUS
MUX
DM ADDRESS BUS
24
24
DMA ADDRESS
DMA
CONNECT
DMA DATA
24
24
16
PM DATA BUS
PX
DATA BUS
MUX
DM DATA BUS
16
I/O DATA
DATA
REGISTER
FILE
I/O PROCESSOR
HOST PORT
24
INPUT
REGISTERS
I/O REGISTERS
(MEMORY-MAPPED)
RESULT
REGISTERS
18
6
SERIAL PORTS
(3)
BARREL
SHIFTER
CONTROL
STATUS
BUFFERS
ALU
MULT
DMA
CONTROLLER
16
؋
16-BIT SPI PORTS
(2)
2
UART PORT
(1)
3
PROGRAMMABLE
FLAGS (16)
SYSTEM INTERRUPT CONTROLLER
TIMERS (3)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADSP-2191M
INTEGRATION FEATURES
TABLE OF CONTENTS
160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM
Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Unified Memory Space Allows Flexible Address Genera-
tion, Using Two Independent DAG Units
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Enhanced Interrupt Controller Enables Programming of
Interrupt Priorities and Nesting Modes
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Environmental Conditions . . . . . . . . . . . . . . . . . . . .42
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49
SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit
Host Interface
16-Bit External Memory Interface for up to 16M Words of
Addressable Memory Space
Three Full-Duplex Multichannel Serial Ports, with
Support for H.100 and up to 128 TDM Channels with
A-Law and -Law Companding Optimized for Telecom-
munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Inter-
rupt Support
Three Programmable Interval Timers with PWM
Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time
for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External
8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection
Programmable PLL Supports 1
؋
to 32؋
Input Frequency Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages
–2–
REV. 0
ADSP-2191M
GENERAL DESCRIPTION
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The ADSP-2191M DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The functional block diagram on page 1 shows the architecture
of the ADSP-219x core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from the
register file and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
The ADSP-2191M combines the ADSP-219x family base
architecture (three computational units, two data address gener-
ators, and a program sequencer) with three serial ports, two
SPI-compatible ports, one UART port, a DMA controller, three
programmable timers, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.
The ADSP-2191M architecture is code-compatible with DSPs
of the ADSP-218x family. Although the architectures are
compatible, the ADSP-2191M architecture has a number of
enhancements over the ADSP-218x architecture. The enhance-
ments to computational units, data address generators, and
program sequencer make the ADSP-2191M more flexible and
even easier to program.
Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
Indirect addressing options provide addressing flexibility—
premodifywithnoupdate, pre-andpost-modifybyanimmediate
8-bit, two’s-complement value and base address registers for
easier implementation of circular buffering.
The ADSP-2191M integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also
provided to reduce power consumption. The ADSP-2191M is
available in 144-lead LQFP and 144-ball mini-BGA packages.
mation, see the ADSP-219x DSP Instruction Set Reference
.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-2191M executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2191M operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except single-word instructions,
execute in one processor.
The ADSP-2191M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2191M can:
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to access
data (indirect addressing), it is pre- or post-modified by the value
of one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
These operations take place while the processor continues to:
• Receive and transmit data through two serial ports
• Receive and/or transmit data from a Host
• Receive or transmit data through the UART
• Receive or transmit data over two SPI ports
Efficient data transfer in the core is achieved with the use of
internal buses:
• Access external memory through the external memory
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• DMA Address Bus
interface
• Decrement the timers
DSP Core Architecture
The ADSP-2191M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-2191M assembly language
• DMA Data Bus
REV. 0
–3–
ADSP-2191M
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
ADSP-2191M
EXTERNAL
MEMORY
(O PTION AL)
CLOCK
OR
CRYSTAL
CLKOUT
CLKIN
XTAL
ADDR21–0
DATA15–8
DATA7–0
MS3–0
ADDR21–0
DATA15–8
DATA7–0
TIMER
OUT OR
CAPTURE
TMR2–0
Program memory can store both instructions and data, permit-
ting the ADSP-2191M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
DSP’s dual memory buses also let the ADSP-219x core fetch an
operand from data memory and the next instruction from
program memory in a single cycle.
CS
CLOCK
MULTIPLY
AND
MSEL6–0/PF6–0
DF/PF7
RD
OE
WR
WE
ACK
RANGE
BYPASS
ACK
BOOT
AND OP
MODE
BMODE1–0
OPMODE
BOOT
MEMORY
(O PTION AL)
DSP Peripherals Architecture
ADDR21–0
DATA15–8
DATA7–0
SPORT0
TCLK0
The functional block diagram on page 1 shows the DSP’s
on-chip peripherals, which include the external memory inter-
face, Host port, serial ports, SPI-compatible ports, UART port,
JTAG test and emulation port, timers, flags, and interrupt con-
troller. Theseon-chipperipheralscan connect tooff-chip devices
as shown in Figure 1.
TFS0
SERIAL
DEVICE
DT0
BMS
CS
RCLK0
OE
(OPTION AL)
RFS0
WE
ACK
DR0
SPORT1
TCLK1
BR
BG
The ADSP-2191M has a 16-bit Host port with DMA capability
that lets external Hosts access on-chip memory. This 24-pin
parallel port consists of a 16-pin multiplexed data/address bus
and provides a low-service overhead data move capability. Con-
figurable for 8 or 16 bits, this port provides a glueless interface
to a wide variety of 8- and 16-bit microcontrollers. Two
chip-selects provide Hosts access to the DSP’s entire memory
map. The DSP is bootable through this port.
EXTERNAL
I/O MEMORY
(O PTIO NAL)
TFS1
BGH
SERIAL
DEVICE
(O PTION AL)
ADDR17–0
DATA15–8
DATA7–0
DT1
RCLK1
RFS1
DR1
IOMS
CS
SPORT2
TCLK2/SCK0
TFS2/MOSI0 SPI0
DT2/MISO0
RCLK2/SCK1
RFS2/MOSI1 SPI1
OE
WE
ACK
The ADSP-2191M also has an external memory interface that is
shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1,SPORT2,SPI0,SPI1,andtheHostport.Theexternal
port consists of a 16-bit data bus, a 22-bit address bus, and
control signals. The data bus is configurable to provide an 8 or
16 bit interface to external memory. Support for word packing
lets the DSP access 16- or 24-bit words from external memory
regardless of the external data bus width. When configured for
an 8-bit interface, the unused eight lines provide eight program-
mable, bidirectional general-purpose Programmable Flag lines,
six of which can be mapped to software condition signals.
SERIAL
DEVICE
(OPTION AL)
HOST
PROCESSOR
(O PTIO NAL)
ADDR15–0/
DATA15–0
ADDR16
DR2/MISO1
HAD15–0
HA16
CS0
UART
RXD
HCMS
HCIOMS
HRD
UART
DEVICE
(OPTION AL)
CS1
RD
TXD
HWR
WR
RESET
JTAG
HACK
ACK
ALE
HALE
6
HACK_P
The memory DMA controller lets the ADSP-2191M move data
andinstructionsfrombetweenmemoryspaces:internal-to-exter-
nal, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.
Figure 1. System Diagram
tion. Each serial port can transmit or receive an internal or
external, programmable serial clock and frame syncs. Each serial
port supports 128-channel Time Division Multiplexing.
The ADSP-2191M can respond to up to seventeen interrupts at
any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. The programmer assigns a
peripheral to one of the 12 user-defined interrupts. The priority
of each peripheral for interrupt service is determined by these
assignments.
The ADSP-2191M provides up to sixteen general-purpose I/O
pins, which are programmable as either inputs or outputs. Eight
of these pins are dedicated-general purpose Programmable Flag
pins. The other eight of them are multifunctional pins, acting as
general-purpose I/O pins when the DSP connects to an 8-bit
external data bus and acting as the upper eight data pins when
the DSP connects to a 16-bit external data bus. These Program-
mable Flag pins can implement edge- or level-sensitive
interrupts, some of which can be used to base the execution of
conditional instructions.
There are three serial ports on the ADSP-2191M that provide a
completesynchronous,full-duplexserialinterface.Thisinterface
includes optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of opera-
–4–
REV. 0
ADSP-2191M
Three programmable interval timers generate periodic inter-
rupts. Each timer can be independently set to operate in one of
three modes:
internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.
• Pulse Waveform Generation mode
• Pulsewidth Count/Capture mode
• External Event Watchdog mode
As shown in Figure 2, the DSP’s two internal memory blocks
populate all of Page 0. The entire DSP memory map consists of
256 pages (Pages 0−255), and each page is 64K words long.
External memory space consists of four memory banks (banks
0–3)andsupportsawidevarietyofSRAMmemorydevices.Each
bank is selectable using the memory select pins (MS3–0) and has
configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page 255whiletheremaining254 pagesareaddressableoff-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their
own select pin (IOMS). Pages 0–7 of I/O memory space reside
on-chip and contain the configuration registers for the peripher-
als. Both the core and DMA-capable peripherals can access the
DSP’s entire memory map.
Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer’s configuration register enables or
disables the corresponding timer independently of the others.
Memory Architecture
The ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page 0 in the DSP’s memory map. In addition to the
64K WORD
MEMORY
PAGES
LOGICAL
ADDRESS
LOWER PAGE BOUNDARIES
ARE CONFIGURABLE FOR
BANKS OF EXTERNAL MEMORY.
BOUNDARIES SHOWN ARE
BANK SIZES AT RESET.
MEMORY SELECTS (MS)
FOR PORTIONS OF THE
MEMORY MAP APPEAR
WITH THE SELECTED
MEMORY.
0
؋
FF FFFF 0
؋
FF 0400 RESERVED
INTERNAL
MEMORY
PAGE 255
0
؋
FF 03FF 0
؋
FF 0000 BOOT ROM, 24-BIT
BANK3
(MS3)
PAGES 192–254
PAGES 128–191
PAGES 64–127
PAGES 1–63
0
؋
C0 0000 0
؋
80 0000 0
؋
40 0000 BANK2
(MS2)
BOOT MEMORY
I/O MEMORY
16- BIT
EXTERNAL
MEMORY
(16- BIT)
16-BIT
(BMS)
LOGICAL
ADDRESS
1K WORD
PAGES 8–255
BANK1
(MS1)
64K WORD
0
؋
FE FFFF 1K WORD
PAGES 0–7
LOGICAL
ADDRESS
PAGES 1–254
BANK0
(MS0)
0
؋
FF 3FF 0
؋
01 0000 0
؋
01 0000 0
؋
00 C000 0
؋
00 8000 EXTERNAL
(IOMS)
BLOCK3, 16-BIT
BLOCK2, 16-BIT
BLOCK1, 24-BIT
INTERNAL
MEMORY
0
؋
08 000 PAGE 0
0
؋
07 3FF 0
؋
00 000 0
؋
00 4000 0
؋
00 0000 INTERNAL
BLOCK0, 24-BIT
8-BIT 10-BIT
Figure 2. Memory Map
Internal (On-Chip) Memory
The ADSP-2191M’s unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly
REV. 0
–5–
ADSP-2191M
External Memory Space
different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.
External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0
• TheDAGsgenerate24-bitaddressesfordatafetchesfrom
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.
containing pages 1
containing pages 128
192 254. The MS3–0 memory bank pins select Banks 3–0,
−63, Bank1 containing pages 64
−127, Bank2
−191, and Bank3 that contains pages
−
respectively. The external memory interface is byte-addressable
and decodes the 8 MSBs of the DSP program address to select
oneofthefourbanks. BoththeADSP-219xcoreandDMA-capa-
ble peripherals can access the DSP’s external memory space.
• The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
theprogramsequencerbasesaddressesforrelativejumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
I/O Memory Space
The ADSP-2191M supports an additional external memory
called I/O memory space. This space is designed to support
simple connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports a total of 256K locations. The first 8K addresses
are reserved for on-chip peripherals. The upper 248K addresses
are available for external peripheral devices. The DSP’s instruc-
tion set provides instructions for accessing I/O space. These
instructions use an 18-bit address that is assembled from an
8-bit I/O page (IOPG) register and a 10-bit immediate value
suppliedintheinstruction. BoththeADSP-219xcoreandaHost
(through the Host Port Interface) can access I/O memory space.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
addressbits. Beforeacross pagejumpor call, theprogram
must set the program sequencer’s IJPG register to the
appropriate memory page.
Boot Memory Space
Boot memory space consists of one off-chip bank with 63 pages.
The BMS memory bank pin selects boot memory space. Both
the ADSP-219x core and DMA-capable peripherals can access
the DSP’s off-chip boot memory space. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
Depending on the boot configuration, the boot ROM code can
startbootingtheDSP from bootmemory. For more information,
see “Booting Modes” on page 11.
TheADSP-2191Mhas1Kwordofon-chipROMthatholdsboot
routines. If peripheral booting is selected, the DSP starts
executing instructions from the on-chip boot ROM, which starts
the boot process from the selected peripheral. For more informa-
tion, see “Booting Modes” on page 11. The on-chip boot ROM
is located on Page 255 in the DSP’s memory space map.
External (Off-Chip) Memory
Each of the ADSP-2191M’s off-chip memory spaces has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write waitcounts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
theexternalmemoryaccessstrobewidths.Formoreinformation,
see“ClockSignals”onpage 11. Theoff-chipmemoryspaces are:
Interrupts
The interrupt controller lets the DSP respond to 17 interrupts
withminimumoverhead.Thecontrollerimplementsaninterrupt
priority scheme as shown in Table 1. Applications can use the
unassigned slots for software and peripheral interrupts.
Table 2 shows the ID and priority at reset of each of the periph-
eral interrupts. To assign the peripheral interrupts a different
priority, applications write the new priority to their correspond-
ing control bits (determined by their ID) in the Interrupt Priority
Control register. The peripheral interrupt’s position in the
IMASK and IRPTL register and its vector address depend on its
priority level, as shown in Table 1. Because the IMASK and
IRPTL registers are limited to 16 bits, any peripheral interrupts
• External memory space (MS3–0 pins)
• I/O memory space (IOMS pin)
• Boot memory space (BMS pin)
All of these off-chip memory spaces are accessible through the
External Port, which can be configured for data widths of
8 or 16 bits.
–6–
REV. 0
ADSP-2191M
assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x00 01E0.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The general-purpose Programmable Flag (PFx) pins can be con-
figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitive operation.
Table 1. Interrupt Priorities/Addresses
IMASK/
IRPTL
Vector
Address
1
Interrupt
Emulator (NMI)—
Highest Priority
NA
NA
Table 3. Interrupt Control (ICNTL) Register Bits
Reset (NMI)
Power-Down (NMI)
Loop and PC Stack
0
1
2
3
4
5
6
7
0x00 0000
0x00 0020
0x00 0040
0x00 0060
0x00 0080
0x00 00A0
0x00 00C0
0x00 00E0
0x00 0100
0x00 0120
0x00 0140
0x00 0160
0x00 0180
0x00 01A0
0x00 01C0
0x00 01E0
Bit
Description
0–3
4
5
6
7
8–9
10
11
12–15
Reserved
Interrupt Nesting Enable
Global Interrupt Enable
Reserved
MAC-Biased Rounding Enable
Reserved
PC Stack Interrupt Enable
Loop Stack Interrupt Enable
Reserved
Emulation Kernel
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt—
Lowest Priority
8
9
10
11
12
13
14
15
TheIRPTLregisterisusedtoforceandclearinterrupts. On-chip
stacks preserve the processor status and are automatically main-
tainedduringinterrupthandling. Tosupportinterrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack-level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.
1These interrupt vectors start at address 0x10000 when the DSP is in
“no-boot,” run from external memory mode.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
Table 2. Peripheral Interrupts and Priority at Reset
Reset
ENA INT;
DIS INT;
Interrupt
ID
Priority
Slave DMA/Host Port Interface
SPORT0 Receive
SPORT0 Transmit
SPORT1 Receive
SPORT1 Transmit
SPORT2 Receive/SPI0
SPORT2 Transmit/SPI1
UART Receive
UART Transmit
Timer 0
Timer 1
Timer 2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA Controller
The ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M’s internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa-
ble peripherals include the Host port, SPORTs, SPI ports, and
UART.EachindividualDMA-capableperipheralhasadedicated
DMA channel. To describe each DMA sequence, the DMA con-
troller uses a set of parameters—called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
canbelinkedorchainedtogether, sothecompletionofoneDMA
sequence auto-initiates and starts the next sequence. DMA
sequences do not contend for bus access with the DSP core;
instead DMAs “steal” cycles to access memory.
8
9
8
9
10
11
12
13
14
10
11
11
11
11
Programmable Flag A (any PFx)
Programmable Flag B (any PFx)
Memory DMA port
Interrupt routines can either be nested with higher priority inter-
ruptstakingprecedenceorprocessedsequentially. Interruptscan
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
REV. 0
–7–
ADSP-2191M
All DMA transfers use the DMA bus shown in the functional
block diagram on page 1. Because all of the peripherals use the
same bus, arbitration for DMA bus access is needed. The arbi-
tration for DMA bus access appears in Table 4.
The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac-
tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.
Table 4. I/O Bus Arbitration Priority
Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini-
tialized at reset based on the values driven on HACK and
HACK_P pins (shown in Table 5); HPCR7 is always cleared (0)
at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configuration register.
DMA Bus Master
Arbitration Priority
SPORT0 Receive DMA
SPORT1 Receive DMA
SPORT2 Receive DMA
SPORT0 Transmit DMA
SPORT1 Transmit DMA
SPORT2 Transmit DMA
SPI0 Receive/Transmit DMA
SPI1 Receive/Transmit DMA
UART Receive DMA
UART Transmit DMA
Host Port DMA
0—Highest
1
2
3
4
5
6
7
Table 5. Host Port Acknowledge Mode Selection
Values Driven At
Reset
HPCR [7:6]
Initial Values
8
9
10
Acknowledge
Mode
HACK_P HACK
Bit 7
Bit 6
0
0
1
1
0
1
0
1
0
0
0
0
1
0
0
1
Ready Mode
ACK Mode
ACK Mode
Ready Mode
Memory DMA
11—Lowest
Host Port
The ADSP-2191M’s Host port functions as a slave on the
external bus of an external Host. The Host port interface lets a
Host read from or write to the DSP’s memory space, boot space,
or internal I/O space. Examples of Hosts include external micro-
controllers, microprocessors, or ASICs.
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
• ACK Mode—Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes the HACK.
TheHostportisamultiplexedaddressanddatabusthatprovides
both an 8-bit and a 16-bit data path and operates using an asyn-
chronous transmission protocol. Through this port, an off-chip
Host can directly access the DSP’s entire memory space map,
boot memory space, and internal I/O space. To access the DSP’s
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP’s core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP’s I/O mapped
peripherals.
• ReadyMode—Ready active on strobes, goes low to inser t
waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.
The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans-
ferred from the Host for every data transfer.
Host Port Chip Selects
There are two chip-select signals associated with the Host port:
Host Port Acknowledge (HACK) Modes
HCMS and HCIOMS. TheHost ChipMemorySelect (HCMS
)
The Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready Modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC Mode from the HALE and
HWR inputs.
lets the Host select the DSP and directly access the DSP’s inter-
nal/external memory space or boot memory space. The Host
ChipI/OMemorySelect(HCIOMS)letstheHostselecttheDSP
and directly access the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
combines the data from one, two, or three consecutive Host
accesses (up to one 24-bit value) into a single DMA bus access
to prefetch Host direct reads or to post direct writes. During
assembly of larger words, the Host port interface asserts ACK for
The Host port HACK signal polarity is selected (only at reset) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
configuration register as a read only bit.
–8–
REV. 0
ADSP-2191M
each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.
SCKx). Two SPI chip select input pins (SPISSx) let other SPI
devices select the DSP, and fourteen SPI chip select output pins
(SPIxSEL7–1) let the DSP select other SPI devices. The SPI
selectpinsarereconfiguredProgrammableFlagpins.Usingthese
pins, the SPI ports provide a full duplex, synchronous serial inter-
face, which supports both master and slave modes and
multimaster environments.
DSP Serial Ports (SPORTs)
The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:
EachSPIport’sbaudrateandclockphase/polaritiesareprogram-
mable (see equation below for SPI clock rate calculation), and
each has an integrated DMA controller, configurable to support
both transmit and receive data streams. The SPI’s DMA control-
ler can only service unidirectional accesses at any given time.
• Bidirectional operation—each SPORT has independent
transmit and receive pins.
• Double-buffered transmit and receive ports—each port
has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.
HCLK
2 × SPIBAUD
--------------------------------------
SPI Clock Rate =
• Clocking—each transmit and receive port can either use
an external serial clock (40 MHz) or generate its own, in
frequencies ranging from 19 Hz to 40 MHz.
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial data
lines. The serial clock line synchronizes the shifting and sampling
of data on the two serial data lines.
• Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.
UART Port
• Framing—each transmit and receive port can run with or
withoutframesyncsignalsforeachdataword. Framesync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.
TheUARTportprovidesasimplifiedUARTinterfacetoanother
peripheral or Host. It performs full duplex, asynchronous
transfers of serial data. Options for the UART include support
for 5–8 data bits; 1 or 2 stop bits; and none, even, or odd parity.
The UART port supports two modes of operation:
• Companding in hardware—each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.
• Programmed I/O
The DSP’s core sends or receives data by writing or
reading I/O-mapped THR or RBR registers, respectively.
The data is double-buffered on both transmit and receive.
• DMA (direct memory access)
• DMA operations with single-cycle overhead—each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
EithertheDSP’scoreoraHostprocessorcanlinkorchain
sequences of DMA transfers between a SPORT and
memory. ThechainedDMAcanbedynamicallyallocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.
The UART’s baud rate (see following equation for UART clock
rate calculation), serial data format, error code generation and
status, and interrupts are programmable:
• Interrupts—each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Supported bit rates range from 9.5 bits to 5M bits per
second (80 MHz peripheral clock).
• Multichannel capability—each SPORT supports the
H.100 standard.
• Supported data formats are 7- to 12-bit frames.
• Transmit and receive status can be configured to generate
maskable interrupts to the DSP’s core.
Serial Peripheral Interface (SPI) Ports
The DSP has two SPI-compatible ports that enable the DSP to
communicatewithmultipleSPI-compatibledevices.Theseports
are multiplexed with SPORT2, so either SPORT2 or the SPI
ports are active, depending on the state of the OPMODE pin
during hardware reset.
The timers can be used to provide a hardware-assisted autobaud
detection mechanism for the UART interface.
HCLK
16 × D
------------------
UART Clock Rate =
The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,
Where D is the programmable divisor = 1 to 65536.
REV. 0
–9–
ADSP-2191M
Programmable Flag (PFx) Pins
Idle Mode
The ADSP-2191M has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve either
as general-purpose I/O pins (if the DSP is connected to an 8-bit
external data bus) or serve as DATA15–8 lines (if the DSP is
connectedtoa16-bitexternaldatabus).TheProgrammableFlag
pins have special functions for clock multiplier selection and for
SPI port operation. For more information, see Serial Peripheral
Interface (SPI) Ports on page 9 and Clock Signals on page 11.
Tenmemory-mappedregisters controloperationoftheProgram-
mable Flag pins:
When the ADSP-2191M is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline,andwaitsforaninterrupt.Thecoreclockandperipheral
clock continue running.
To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core Mode
When theADSP-2191M is inPower-DownCoremode, theDSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.
• Flag Direction register
Specifies the direction of each individual PFx pin as input
or output.
To enter Power-Down Core mode, the DSP executes an IDLE
instruction after performing the following tasks:
• Flag Control and Status registers
Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.
• Enter a power-down interrupt service routine
• Check for pending interrupts and I/O service routines
• Clear (= 0) the PDWN bit in the PLLCTL register
• Clear (= 0) the STOPALL bit in the PLLCTL register
• Set (= 1) the STOPCK bit in the PLLCTL register
• Flag Interrupt Mask registers
Enable and disable each individual PFx pin to function
as an interrupt to the DSP’s core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts—latching in the IMASK and IRPTL
registers.
To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.
Power-Down Core/Peripherals Mode
When the ADSP-2191M is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.
• Flag Interrupt Polarity register
Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin.
ToenterPower-DownCore/Peripherals mode, theDSPexecutes
an IDLE instruction after performing the following tasks:
• Flag Sensitivity registers
Specify whether individual PFx pins are level- or
edge-sensitive and specify—if edge-sensitive—whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif-
icant for edge-sensitivity.
• Enter a power-down interrupt service routine
• Check for pending interrupts and I/O service routines
• Clear (= 0) the PDWN bit in the PLLCTL register
• Set (= 1) the STOPALL bit in the PLLCTL register
To exit Power-Down Core/Peripherals mode, the DSP responds
to a wake-up event and (after five to six cycles of latency) resumes
executing instructions with the instruction after the IDLE.
Low Power Operation
The ADSP-2191M has four low-power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-2191M uses configu-
ration of the PDWN, STOPCK, and STOPALL bits in the
PLLCTL register to select between the low-power modes as the
DSPexecutestheIDLE.Dependingonthemode,anIDLEshuts
off clocks to different parts of the DSP in the different modes.
The low power modes are:
Power-Down All Mode
When the ADSP-2191M is in Power-Down All mode, the DSP
coreclock, theperipheralclock, andthePLL areallstopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.
To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:
• Enter a power-down interrupt service routine
• Check for pending interrupts and I/O service routines
• Set (= 1) the PDWN bit in the PLLCTL register
• Idle
• Power-Down Core
• Power-Down Core/Peripherals
• Power-Down All
–10–
REV. 0
ADSP-2191M
To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after the
IDLE.
1M⍀
25MHz
XTAL
CLKIN
CLKOUT
Clock Signals
MSEL0 (PF0)
MSEL1 (PF1)
The ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a
VDD
ADSP-2191M
VDD
1 M
Ωshunt resistor connected as shown in Figure 3. Capacitor
MSEL2 (PF2)
MSEL3 (PF3)
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
quency, microprocessor-grade crystal should be used for this
configuration.
RUNTIME
PF PIN I/O
MSEL4 (PF4)
If a buffered, shaped clock is used, this external clock connects
to the DSP’s CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.
MSEL5 (PF5)
MSEL6 (PF6)
THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASS PINS
SELECT THE CORE CLOCK
RATIO.
The DSP provides a user-programmable 1
؋
to 32؋
multiplica- DF (PF7)
BYPASS
RESET
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL6–0,BYPASS,andDFpinsdecidethePLLmultiplication
factor at reset. At runtime, the multiplication factor can be con-
trolled in software. The combination of pullup and pull-down
resistors in Figure sets up a core clock ratio of 6:1, which
produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the ADSP-219x/2191 DSP
HERE, THE SELECTION (6:1)
AND 25MHz INPUT CLOCK
PRODUCE A 150MHz CORE
CLOCK.
RESET
SOURCE
Figure 3. External Crystal Connections
The RESET input contains some hysteresis. If using an RC
circuit to generate your RESET signal, the circuit should use an
external Schmidt trigger.
Hardware Reference
.
The peripheral clock is supplied to the CLKOUT pin.
All on-chip peripherals for the ADSP-2191M operate at the rate
set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is 160 MHz and the maximum periph-
eral clock is 80 MHz—the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.
Themasterresetsetsallinternalstackpointerstotheemptystack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When RESET is released, if
there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF 0000).
Reset
Power Supplies
The ADSP-2191M has separate power supply connections for
The RESET signal initiates a master reset of the ADSP-2191M.
The RESET signal must be asserted during the powerup
sequence to assure proper initialization. RESET during initial
powerup must be held long enough to allow the internal clock to
stabilize.
the internal (V
) and external (V
) power supplies.
DDINT
DDEXT
The internal supply must meet the 2.5 V requirement. The
external supply must be connected to a 3.3 V supply. All external
supply pins must be connected to the same supply.
The powerup sequence is defined as the total time required for
Powerup Sequence
Power up together the two supplies V
they cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.
thecrystaloscillatorcircuittostabilizeafteravalidV
isapplied
DD
and V
. If
DDINT
DDEXT
to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100 µs
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the
RESET signal should be held low. On any subsequent resets, the
RESET signal must meet the minimum pulsewidth specifica-
Booting Modes
The ADSP-2191M has five mechanisms (listed in Table 6) for
automatically loading internal program memory after reset. Two
No-boot modes are also supported.
tion, t
.
WRST
REV. 0
–11–
ADSP-2191M
Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
• Execute from memory external 8 bits (No Boot)—
Execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is config-
ured for the default clock multiplier (128) and read
waitstates (7).
Function
• Boot from UART—The Host downloads
boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
withintheUART’s clockingcapabilities. Afterahardware
reset, the DSP’s UART expects a 0xAA character (eight
bits data, one start bit, one stop bit, no parity bit) on the
RXD pin to determine the bit rate; and then replies with
anOKstring. OncethehostreceivesthisOKitdownloads
the boot stream without further handshake.The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.
0
0
0
Execute from external memory 16 bits
(No Boot)
Boot from EPROM
Boot from Host
0
0
0
1
0
1
1
0
1
0
1
0
Reserved
Execute from external memory 8 bits
(No Boot)
Boot from UART
Boot from SPI, up to 4K bits
Boot from SPI, >4K bits up to
512K bits
1
1
1
0
1
1
1
0
1
• Boot from SPI, up to 4K bits—The SPI0 port uses the
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EEPROM device, submits a read command
ataddress0x00,andbeginsclockingconsecutivedatainto
internal or external memory. Use only SPI-compatible
EEPROMs of ≤ 4K bit (12-bit address range). The SPI0
boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
rationisSPIBAUD0=60(decimal),CPHA=1,CPOL=1,
8-bit data, and MSB first.
The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configuration
Register implement these modes:
• Execute from memory external 16 bits—The memory
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x010000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).
• Boot from EPROM—The EPROM boot routine located
in boot ROM memory space fetches a boot-stream-for-
matted program located at physical address 0x00 0000 of
boot memory space, packing 8- or 16-bit external data
into 24-bit internal data. The External Port Interface is
configured for the default clock multiplier (32) and read
waitstates (7).
• Boot from SPI, from >4K bits to 512K bits—The SPI0
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EEPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EEPROMs of ≥ 4K bit (16-bit address
range). The SPI0 boot routine, located in internal ROM
memory space, executes a boot-stream-formatted
• Boot from Host—The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.
program, using the top 16 locations of Page 0 program
memoryandthetop272locationsofPage 0datamemory.
Asindicated in Table 6, theOPMODEpin hasadualrole, acting
as a boot mode select during reset and determining SPORT or
SPI operation at runtime. If the OPMODE pin at reset is the
opposite of what is needed in an application during runtime, the
application needs to set the OPMODE bit appropriately during
runtime prior to using the corresponding peripheral.
The internal boot ROM sets semaphore A (an IO register
within the Host port) and then polls until the semaphore
isreset. Oncedetected, theinternalbootROMwillremap
the interrupt vector table to Page 0 internal memory and
jump to address 0x00 0000 internal memory. From the
point of view of the host interface, an external host has
full control of the DSP's memory map. The Host has the
freedom to directly write internal memory, external
memory, and internal I/O memory space. The DSP core
execution is held off until the Host clears the semaphore
register. This strategy allows the maximum flexibility for
the Host to boot in the program and data code, by leaving
it up to the programmer.
Bus Request and Bus Grant
TheADSP-2191Mcanrelinquishcontrolofthedataandaddress
buses to an external device. When the external device requires
access to the bus, it asserts the bus request (BR) signal. The (BR
)
signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Because of
–12–
REV. 0
ADSP-2191M
Development Tools
synchronizer and arbitration delays, bus grants will be provided
with a minimum of three peripheral clock delays. ADSP-2191M
DSPs will respond to the bus grant by:
The ADSP-2191M is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++® development environment. The
same emulator hardware that supports other ADSP-219x DSPs,
also fully emulates the ADSP-2191M.
• Three-stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
• Asserting the bus grant (BG) signal.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. Two key points for these tools are:
The ADSP-2191M will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or periph-
eral memory spaces. If an instruction requires two external
memory read accesses, bus requests will not be granted between
the two accesses. If an instruction requires an external memory
read and an external memory write access, the bus may be
granted between the two accesses. The external memory
interface can be configured so that the core will have exclusive
use of the interface. DMA and Bus Requests will be granted.
When the external device releases BR, the DSP releases BG and
continues program execution from the point at which it stopped.
• Compiled ADSP-219x C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to ADSP-219x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.
• ADSP-218x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-218x applications to the ADSP-219x.
The bus request feature operates at all times, even while the DSP
is booting and RESET is active.
The ADSP-2191M asserts the BGH pin when it is ready to start
another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.
Debugging both C/C++ and assembly programs with the Visu-
alDSP++ debugger, programmers can:
• View mixed C/C++ and assembly code (interleaved
source and object information)
• Insert break points
Instruction Set Description
• Set conditional breakpoints on registers, memory, and
stacks
The ADSP-2191M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• Trace instruction execution
• Perform linear or statistical profiling of program
• ADSP-219xassemblylanguagesyntaxisasupersetofand
source-code-compatible (except for two data registers
and DAG base address registers) with ADSP-218x family
syntax. It may be necessary to restructure ADSP-218x
programs to accommodate the ADSP-2191M’s unified
memory space and to conform to its interrupt vector map.
execution
• Fill, dump, and graphically plot the contents of memory
• Source level debugging
• Create custom debugger windows
The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the syntax highlighting in the Visu-
alDSP++ editor. This capability permits:
• The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.
• Control how the development tools process inputs and
generate outputs.
• Every instruction, but two, assembles into a single, 24-bit
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16-
or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.
• Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-2191M processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonin-
trusivein-circuitemulationisassuredbytheuseoftheprocessor’s
JTAG interface—the emulator does not affect target system
loading or timing.
• Multifunction instructions allow parallel execution of an
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.
• Program flow instructions support a wider variety of con-
ditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.
REV. 0
–13–
ADSP-2191M
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
toolsincludeADSP-219xPCplug-incards. Thirdpartysoftware
tools include DSP libraries, real-time operating systems, and
block diagram design tools.
As can be seen in Figure 4, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TDO, TRST, and EMU used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and BTRST that are optionally used for
board-level (boundary scan) testing.
Whentheemulatorisnotconnectedtothisheader,placejumpers
across BTMS, BTCK, BTRST, andBTDI as shownin Figure 5.
This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.
Designing an Emulator-Compatible DSP Board
(Target)
The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.
1
3
5
2
4
6
EMU
GND
TMS
GND
KEY (NO PIN)
BTMS
7
9
8
BTCK
TCK
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.
10
12
BTRST
TRST
9
11
Target Board Header
BTDI
GND
TDI
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in Figure 4. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
13
14
TDO
TOP VIEW
square post header, set on 0.1"
؋
0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
Figure 5. JTAG Target Board Connector with No Local
Boundary Scan
Also, the clearance (length, width, and height)around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
JTAG Emulator Pod Connector
Figure 6 detailsthedimensionsoftheJTAG pod connector atthe
14-pin target end. Figure 7 displays the keep-out area for a target
board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
shouldcontainnocomponents(chips, resistors, capacitors,etc.).
The dimensions are referenced to the center of the 0.25" square
post pin.
1
3
5
2
4
6
EMU
GND
KEY (NO PIN)
GND
TMS
BTMS
7
9
8
BTCK
TCK
10
12
BTRST
TRST
9
0.64"
11
BTDI
GND
TDI
13
14
TDO
0.88"
TOP VIEW
0.24"
Figure 4. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in
Place)
Figure 6. JTAG Pod Connector Dimensions
–14–
REV. 0
ADSP-2191M
Additional Information
This data sheet provides a general overview of the ADSP-2191M
architecture and functionality. For detailed information on the
core architecture of the ADSP-219x family, refer to the
ADSP-219x/2191 DSP Hardware Reference. For details on the
0.10"
instruction set, refer to the ADSP-219x Instruction Set Reference
.
0.15"
PIN FUNCTION DESCRIPTIONS
Figure 7. JTAG Pod Connector Keep-Out Area
ADSP-2191M pin definitions are listed in Table 7. All
ADSP-2191M inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices JTAG Emulation Technical Reference on the Analog
Devices website (www.analog.com)—use site search on
“EE-68.” This document is updated regularly to keep pace with
improvements to emulator support.
Tie or pull unused inputs to V
or GND, except for
DDEXT
ADDR21–0, DATA15–0, PF7-0, and inputs that have internal
pull-up or pull-down resistors (TRST, BMODE0, BMODE1,
OPMODE, BYPASS, TCK, TMS, TDI, and RESET)—these
pins can be left floating. These pins have a logic-level hold circuit
that prevents input from floating internally.
The following symbols appear in the Type column of Table : G
= Ground, I = Input, O = Output, P = Power Supply, and T =
Three-State.
Table 7. Pin Function Descriptions
Pin
Type
Function
A21–0
D7–0
O/T
External Port Address Bus
I/O/T External Port Data Bus, least significant 8 bits
D15
I/O/T Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave
/PF15
/SPI1SEL7
D14
I/O
I
Select output 7 (if 8-bit external bus, when SPI1 enabled)
I/O/T Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave
/PF14
/SPI0SEL7
D13
I/O
I
Select output 7 (if 8-bit external bus, when SPI0 enabled)
I/O/T Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave
/PF12
/SPI1SEL6
D12
I/O
I
Select output 6 (if 8-bit external bus, when SPI1 enabled)
I/O/T Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave
/PF12
/SPI0SEL6
D11
I/O
I
Select output 6 (if 8-bit external bus, when SPI0 enabled)
I/O/T Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave
/PF11
/SPI1SEL5
D10
I/O
I
Select output 5 (if 8-bit external bus, when SPI1 enabled)
I/O/T Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave
/PF10
/SPI0SEL5
D9
I/O
I
Select output 5 (if 8-bit external bus, when SPI0 enabled)
I/O/T Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select
/PF9
/SPI1SEL4
D8
I/O
I
output 4 (if 8-bit external bus, when SPI1 enabled)
I/O/T Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select
/PF8
/SPI0SEL4
PF7
I/O
I
output 4 (if 8-bit external bus, when SPI0 enabled)
I/O/T Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency
/SPI1SEL3
/DF
I
I
(divisor select for PLL input during boot)
PF6
I/O/T Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6
/SPI0SEL3
/MSEL6
I
I
(during boot)
REV. 0
–15–
ADSP-2191M
Table 7. Pin Function Descriptions (continued)
Pin
Type
Function
PF5
I/O/T Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5
/SPI1SEL2
/MSEL5
PF4
I
I
(during boot)
I/O/T Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4
/SPI0SEL2
/MSEL4
I
I
(during boot)
PF3
I/O/T Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3
/SPI1SEL1
/MSEL3
I
I
(during boot)
PF2
I/O/T Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2
/SPI0SEL1
/MSEL2
I
I
(during boot)
PF1
I/O/T Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1
/SPISS1
/MSEL1
I
I
(during boot)
PF0
I/O/T Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0
/SPISS0
/MSEL0
I
I
(during boot)
RD
WR
ACK
BMS
IOMS
MS3–0
BR
O/T
O/T
I
O/T
O/T
O/T
I
External Port Read Strobe
External Port Write Strobe
External Port Access Ready Acknowledge
External Port Boot Space Select
External Port IO Space Select
External Port Memory Space Selects
External Port Bus Request
BG
O
External Port Bus Grant
BGH
O
External Port Bus Grant Hang
HAD15–0
HA16
I/O/T Host Port Multiplexed Address and Data Bus
I
Host Port MSB of Address Bus
HACK_P
HRD
I
I
Host Port ACK Polarity
Host Port Read Strobe
HWR
I
Host Port Write Strobe
HACK
HALE
HCMS
HCIOMS
CLKIN
XTAL
BMODE1–0
OPMODE
CLKOUT
BYPASS
RCLK1–0
O
I
I
I
I
O
I
I
O
I
Host Port Access Ready Acknowledge
Host Port Address Latch Strobe or Address Cycle Control
Host Port Internal Memory–Internal I/O Memory–Boot Memory Select
Host Port Internal I/O Memory Select
Clock Input/Oscillator input
Oscillator output
Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 kΩ internal pull-up resistors.
Operating Mode. The OPMODE pin has a 85 kΩ internal pull-up resistor.
Clock Output
Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 kΩ internal pull-up resistor.
I/O/T SPORT1–0 Receive Clock
RCLK2/SCK1 I/O/T SPORT2 Receive Clock/SPI1 Serial Clock
RFS1–0
I/O/T SPORT1–0 Receive Frame Sync
RFS2/MOSI1
TCLK1–0
I/O/T SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data
I/O/T SPORT1–0 Transmit Clock
TCLK2/SCK0 I/O/T SPORT2 Transmit Clock/SPI0 Serial Clock
TFS1–0
I/O/T SPORT1–0 Transmit Frame Sync
TFS2/MOSI0
DR1–0
DR2/MISO1
DT1–0
I/O/T SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data
I/T
I/O/T SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data
O/T SPORT1–0 Serial Data Transmit
SPORT1–0 Serial Data Receive
DT2/MISO0
TMR2–0
I/O/T SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data
I/O/T Timer output or capture
–16–
REV. 0
ADSP-2191M
Table 7. Pin Function Descriptions (continued)
Pin
Type
Function
RXD
TXD
RESET
I
O
I
UART Serial Receive Data
UART Serial Transmit Data
Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the
program memory location specified by the hardware reset vector address. The RESET input
must be asserted (low) at powerup. The RESET pin has an 85 kΩ internal pull-up resistor.
Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85 kΩ
internal pull-up resistor.
Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85 kΩ
internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a
85 kΩ internal pull-up resistor.
TCK
TMS
TDI
I
I
I
TDO
TRST
O
I
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
powerup or held low for proper operation of the ADSP-2191M. The TRST pin has a 65 kΩ
internal pull-down resistor.
EMU
O
Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board
connector only.
VDDINT
VDDEXT
GND
P
P
G
Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor. (four pins)
I/O Power Supply. Nominally 3.3 V dc. (nine pins)
Power Supply Return. (twelve pins)
NC
Do Not Connect. Reserved pins that must be left open and unconnected.
REV. 0
–17–
ADSP-2191M
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade (Commercial) B Grade (Industrial)
1
Parameter
Test Conditions
Min
Max
Min
Max
Unit
VDDINT
Internal (Core) Supply
Voltage
2.37
2.63
2.37
2.63
V
VDDEXT
VIH
External (I/O) Supply
Voltage
High Level Input Voltage @ VDDINT = max, 2.0
VDDEXT = max
2.97
3.6
2.97
3.6
V
V
DDEXT+0.3 2.0
VDDEXT+0.3 V
VIL
Low Level Input Voltage @ VDDINT = min, –0.3
VDDEXT = min
0.8
70
–0.3
–40
0.8
V
TAMB
Ambient Operating
Temperature
0
+85
ºC
1Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
K and B Grades
1
Parameter
Test Conditions
Min
Typ
Max
Unit
VOH
VOL
IIH
High Level Output Voltage2
Low Level Output Voltage2
High Level Input Current3, 4
Low Level Input Current3, 5
High Level Input Current5
Low Level Input Current4
Three-State Leakage Current6
Three-State Leakage Current6
Input Capacitance7, 8
@ VDDEXT = min,
IOH = –0.5 mA
@ VDDEXT = min,
IOL = 2.0 mA
@ VDDEXT = max,
VIN = VDD max
@ VDDEXT = max,
VIN = 0 V
@ VDDEXT = max,
VIN = VDD max
@ VDDEXT = max,
VIN = 0 V
@ VDDEXT = max,
VIN = VDD max
@ VDDEXT = max,
VIN = 0 V
2.4
V
0.4
10
10
100
70
10
10
8
V
µA
µA
µA
µA
µA
µA
pF
IIL
IIHP
IILP
IOZH
IOZL
CIN
30
20
fIN = 1 MHz,
T
CASE = 25°C,
VIN = 2.5 V
1Specifications subject to change without notice.
2Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,
BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,
RFS2/MOSI1, BMS, TDO, TXD, EMU, DR2/MISO1.
3Applies to input pins: ACK, BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P.
4Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.
5Applies to input pin with internal pull-down: TRST.
6Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx,
HAD15–0, TMR2–0.
7Applies to all signal pins.
8Guaranteed, but not tested.
–18–
REV. 0
ADSP-2191M
ABSOLUTE MAXIMUM RATINGS
VDDINT Internal (Core) Supply Voltage1,2. . –0.3 V to 3.0 V
VDDEXT External (I/O) Supply Voltage . . . . –0.3 V to 4.6 V
VIL–VIH Input Voltage . . . . . . . . –0.5 V to VDDEXT+0.5 V
VOL–VOH Output Voltage Swing. –0.5 V to VDDEXT+0.5 V
T
STOREStorage Temperature Range . . . . . .–65ºC to 150ºC
T
LEADLead Temperature of ST-144 (5 seconds) . . . . 185ºC
1Specifications subject to change without notice.
2Stressesgreaterthanthoselistedabovemaycausepermanentdamagetothedevice.
These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
Power Dissipation
Using the operation-versus-current information in Table 8, designers can estimate the ADSP-2191M’s internal power supply
(V
) input current for a specific application, according to the formula for I
calculation beneath Table 8. For calculation
DDINT
DDINT
of external supply current and total supply current, see Power Dissipation on page 41.
Table 8. Operation Types Versus Input Current
K-Grade
(mA) CCLK = 160 MHz
B-Grade
1
I
I
(mA) CCLK = 140 MHz
DDINT
DDINT
Core
Peripheral
Core
Peripheral
1
2
1
2
1
2
1
2
Activity
Typ
Max
Typ
Max
Typ
Max
Typ
Max
Power Down3
100µA
1
1
184
215
600µA
2
2
210
240
0
5
60
60
60
50µA
8
70
70
70
100µA
1
1
165
195
500µA
2
2
185
210
0
4
55
55
55
50µA
7
62
62
62
Idle 14
Idle 25
Typical6
Peak7
1Test conditions: V
2Test conditions: V
= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T
= 25ºC.
= 25ºC.
DDINT
DDINT
AMB
AMB
3PLL, Core, peripheral clocks, and CLKIN are disabled.
4PLL is enabled and Core and peripheral clocks are disabled.
5Core CLK is disabled and peripheral clock is enabled.
6All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using
a linear address sequence. 50% of the instructions are type 3 instructions.
7All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear
address sequence.
IDDINT = (%Typical × IDDINT-TYPICAL) + (%Idle × IDDINT-IDLE) + (%Power Down × IDDINT-PWRDWN
)
REV. 0
–19–
ADSP-2191M
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.
Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.
Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation.Timing requirements guarantee that the processor operates correctly with other devices.
Clock In and Clock Out Cycle Timing
Table 9 and Figure 8 describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-
eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.
Table 9. Clock In and Clock Out Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
tCKOD
tCKO
CLKOUT Delay from CLKIN
0
12.5
5.8
ns
ns
CLKOUT Period1
Timing Requirements
tCK
CLKIN Period2, 3
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulsewidth Low
10
4.5
4.5
200
ns
ns
ns
ns
µs
ns
tCKL
tCKH
tWRST
tMSS
tMSH
200tCLKOUT
MSELx/BYPASS Stable Before RESET Deasserted Setup 40
MSELx/BYPASS Stable After RESET Deasserted Hold
MSELx/BYPASS Stable After RESET Asserted
Flag Output Disable Time After RESET Asserted
1000
tMSD
tPFD
200
10
ns
ns
1CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
2In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), tCK=t
.
CCLK
3In bypass mode, tCK=tCCLK
.
–20–
REV. 0
ADSP-2191M
tCK
CLKIN
tCKL
tCKH
tW RST
RESET
tMSD
tPFD
tM SS
tMSH
MSEL6–0
BYPASS
DF
tCK OD
tC KO
CLKOUT
Figure 8. Clock In and Clock Out Cycle Timing
REV. 0
–21–
ADSP-2191M
Programmable Flags Cycle Timing
Table 10 and Figure 9 describe Programmable Flag operations.
Table 10. Programmable Flags Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDFO
tHFO
Flag Output Delay with Respect to CLKOUT
Flag Output Hold After CLKOUT High
7
6
ns
ns
Timing Requirement
tHFI Flag Input Hold is asynchronous
3
ns
CLKOUT
tDFO
tHFO
PF
(OUTPUT)
FLAG OUTPUT
tHFI
PF
(INPUT)
FLAG INPUT
Figure 9. Programmable Flags Cycle Timing
Timer PWM_OUT Cycle Timing
Table 11 and Figure 10 describe timer expired operations. The input signal is asynchronous in “width capture mode” and has an
absolute maximum input frequency of 40 MHz.
Table 11. Timer PWM_OUT Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristic
tHTO
Timer Pulsewidth Output1
12.5
(232–1) cycles
ns
1The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232 –1) cycles.
HCLK
tHT O
PWM_OUT
Figure 10. Timer PWM_OUT Cycle Timing
–22–
REV. 0
ADSP-2191M
External Port Write Cycle Timing
Table 12 and Figure 11 describe external port write operations.
The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP
requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the
ADSP-219x/2191 DSP Hardware Reference
.
Table 12. External Port Write Cycle Timing
1, 2
Parameter
Min
Max
Unit
Switching Characteristics
tCSWS
tAWS
tWSCS
tWSA
tWW
tCDA
tCDD
tDSW
tDHW
tDHW
tWWR
Chip Select Asserted to WR Asserted Delay
0.5tHCLK–4
0.5tHCLK–3
0.5tHCLK–4
0.5tHCLK–3
tHCLK–2+W3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to WR Setup and Delay
WR Deasserted to Chip Select Deasserted
WR Deasserted to Address Invalid
WR Strobe Pulsewidth
WR to Data Enable Access Delay
0
WR to Data Disable Access Delay
0.5tHCLK–3
tHCLK+1+W3
3.4
tHCLK+3.4
tHCLK
0.5tHCLK+4
Data Valid to WR Deasserted Setup
WR Deasserted to Data Invalid Hold Time; E_WHC4
WR Deasserted to Data Invalid Hold Time; E_WHC4
WR Deasserted to WR, RD Asserted
tHCLK+7+W3
Timing Requirements
tAKW
ACK Strobe Pulsewidth
12.5
0
ns
ns
tDWSAK
ACK Delay from WR Low
1tHCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
3W = (number of waitstates specified in wait register)
؋
tHCLK. 4Write hold cycle–memory select control registers (MS
؋
CTL). t C S W
t W S C S
S
M S3–0
IOM S
BM S
A 2 1 – 0
t W W
t A W
t W S A
S
W R
t W W
t D W S A K
R
t A K W
A C K
t C D D
t D H W
t C D A
t D S W
D 1 5 – 0
RD
Figure 11. External Port Write Cycle Timing
REV. 0
–23–
ADSP-2191M
External Port Read Cycle Timing
Table 13 and Figure 12 describe external port read operations. For additional information on the ACK signal, see the discussion
on page 23.
Table 13. External Port Read Cycle Timing
1, 2
Parameter
Min
Max
Unit
Switching Characteristics
tCSRS
tARS
tRSCS
tRW
tRSA
tRWR
Chip Select Asserted to RD Asserted Delay
0.5tHCLK–3
0.5tHCLK–3
0.5tHCLK–2
tHCLK–2+W3
0.5tHCLK–2
tHCLK
ns
ns
ns
ns
ns
Address Valid to RD Setup and Delay
RD Deasserted to Chip Select Deasserted Setup
RD Strobe Pulsewidth
RD Deasserted to Address Invalid Setup
RD Deasserted to WR, RD Asserted
Timing Requirements
tAKW
tRDA
tADA
tSDA
tSD
ACK Strobe Pulsewidth
tHCLK
ns
ns
ns
ns
ns
ns
RD Asserted to Data Access Setup
Address Valid to Data Access Setup
Chip Select Asserted to Data Access Setup
Data Valid to RD Deasserted Setup
RD Deasserted to Data Invalid Hold
tHCLK–4+W3
tHCLK+W3
tHCLK+W3
7
0
tHRD
tDRSAK
ACK Delay from RD Low
0
ns
1tHCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
3W = (number of waitstates specified in wait register)
؋
tHCLK .
tR S C S
tC S R S
MS3–0
IOMS
BMS
A 2 1 – 0
tR W
tR S A
tA R S
RD
tD R S A K
tR W R
tA K W
A C K
tC D A
tH R D
tS D
D 1 5 – 0
tR D A
tA D A
tS D A
WR
Figure 12. External Port Read Cycle Timing
–24–
REV. 0
ADSP-2191M
External Port Bus Request and Grant Cycle Timing
Table 14 and Figure 13 describe external port bus request and bus grant operations.
Table 14. External Port Bus Request and Grant Cycle Timing
1, 2
Parameter
Min
Max
Unit
Switching Characteristics
tSD
tSE
tDBG
tEBG
tDBH
tEBH
CLKOUT High to xMS, Address, and RD/WR Disable
CLKOUT Low to xMS, Address, and RD/WR Enable
CLKOUT High to BG Asserted Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH Asserted Setup
CLKOUT High to BGH Deasserted Hold Time
0.5tHCLK+1
ns
ns
ns
ns
ns
ns
0
0
0
0
0
4
4
4
4
4
Timing Requirements
tBS
tBH
BR Asserted to CLKOUT High Setup
CLKOUT High to BR Deasserted Hold Time
4.6
0
ns
ns
1tHCLK is the peripheral clock period.
2These are timing parameters that are based on worst-case operating conditions.
CLKOUT
tBS
tBH
BR
tSD
tSE
MS3–0
IOMS
BMS
tSD
tSE
A21–0
tSE
tSD
WR
RD
tDBG
tEBG
BG
tDBH
tEB H
BGH
Figure 13. External Port Bus Request and Grant Cycle Timing
REV. 0
–25–
ADSP-2191M
Host Port ALE Mode Write Cycle Timing
Table 15 and Figure 14 describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 15. Host Port ALE Mode Write Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
1
1
tWHKS1
HWR Asserted to HACK Asserted (Setup, ACK Mode) First
10
5tHCLK+tNH
ns
Byte
tWHKS2
tWHKH
HWR Asserted to HACK Asserted (Setup, ACK Mode)2
HWR Deasserted to HACK Deasserted (Hold, ACK Mode)
10
10
ns
ns
tWHS
tWHH
HWR Asserted to HACK Asserted (Setup, Ready Mode)
HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
10
ns
ns
0
5tHCLK+tNH
Timing Requirements
tCSAL
tALPW
tALCSW
tWCSW
tALW
HCMS or HCIOMS Asserted to HALE Asserted
HALE Asserted Pulsewidth
0
4
1
0
1
0
ns
ns
ns
ns
ns
ns
HALE Deasserted to HCMS or HCIOMS Deasserted
HWR Deasserted to HCMS or HCIOMS Deasserted
HALE Deasserted to HWR Asserted
HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)
HACK Asserted to HWR Deasserted (Hold, ACK Mode)
Address Valid to HALE Deasserted (Setup)
HALE Deasserted to Address Invalid (Hold)
Data Valid to HWR Deasserted (Setup)
tWCS
tHKWD
tAALS
tALAH
tDWS
1.5
2
4
4
1
ns
ns
ns
ns
ns
tWDH
HWR Deasserted to Data Invalid (Hold)
1tNH are peripheral bus latencies (n
؋
tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory at the same time.
2Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
–26–
REV. 0
ADSP-2191M
H CMS
HIOMS
tALCSW
tALPW
tWCSW
tCSAL
HALE
tWCS
tALW
HWR
tHKWD
tWHKS
tWHKH
HACK
(ACK
MODE)
HA CK EACH BYTE
H AC K FIRST B YTE
tWHH
tWHS
HACK
(READY
M ODE)
tALAH
tDWS
tAALS
tWDH
HAD15–0
HA16
ADDR ESS
VALID
DA TA
VALID
DATA
VALID
ADDRESS
VALID
START
NEXT WORD
STA RT
FIRST W OR D
FIRST
BYTE
LAST
BYTE
Figure 14. Host Port ALE Mode Write Cycle Timing
REV. 0
–27–
ADSP-2191M
Host Port ACC Mode Write Cycle Timing
Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 16. Host Port ACC Mode Write Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
1
1
tWHKS1
tWHKS2
tWHKH
tWHS
HWR Asserted to HACK Asserted (ACK Mode) First Byte
10
5tHCLK+tNH
12
10
10
ns
ns
ns
ns
ns
HWR Asserted to HACK Asserted (Setup, ACK Mode)2
HWR Deasserted to HACK Deasserted (Hold, ACK Mode)
HWR Asserted to HACK Asserted (Setup, Ready Mode)
HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
tWHH
0
5tHCLK+tNH
tWSHKS
HWR Asserted to HACK Asserted (Setup) During Address
Latch
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
10
10
ns
ns
tWHHKH
Timing Requirements
tWAL
tCSAL
tALCS
HWR Asserted to HALE Deasserted (Delay)
1.5
0
1
ns
ns
ns
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
tWCSW
tALW
tCSW
tWCS
HWR Deasserted to HCMS or HCIOMS Deasserted
HALE Asserted to HWR Asserted
HCMS or HCIOMS Asserted to HWR Asserted
HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)
HALE Deasserted to HWR Asserted
HACK Asserted to HWR Deasserted (Hold, ACK Mode)
Address Valid to HWR Asserted (Setup)
HWR Deasserted to Address Invalid (Hold)
Data Valid to HWR Deasserted (Setup)
0
0.5
0
ns
ns
ns
ns
0
tALEW
tHKWD
tADW
tWAD
tDWS
1
1.5
3
3
2
ns
ns
ns
ns
ns
ns
tWDH
HWR Deasserted to Data Invalid (Hold)
2
tHKWAL
HACK Asserted to HWR Deasserted (Hold) During Address
2
ns
Latch2
1tNH are peripheral bus latencies (n
؋
tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory at the same time.
2 Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent
on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
–28–
REV. 0
ADSP-2191M
HCMS
HIOMS
tALCS
tWAL
tWCSW
tCS A L
H ALE
tCS W
tALE W
tWCS
tALW
HWR
tH KW D
tW HK S
tHKW A L
tW S HK S
tWHKH
HACK
( ACK
H AC K EAC H B YTE
MOD E)
tWHH
tWHHKH
tWHS
HACK
(REA DY
M OD E)
HACK FIR ST B YTE
tWAD
tADW
tDWS
tWDH
H A D15 –0
H A 16
ADDRESS
VA LID
DA TA
VALID
D ATA
VALID
AD DRESS
VA LID
S TAR T
NEX T WORD
START
FIRST WORD
FIRST
B YTE
LA ST
BYTE
Figure 15. Host Port ACC Mode Write Cycle Timing
REV. 0
–29–
ADSP-2191M
Host Port ALE Mode Read Cycle Timing
Table 17 and Figure 16 describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 17. Host Port ALE Mode Read Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
1
1
tRHKS1
tRHKS2
tRHKH
tRHS
HRD Asserted to HACK Asserted (ACK Mode) First Byte
12tHCLK
15tHCLK+tNH
12
10
10
ns
ns
ns
ns
ns
HRD Asserted to HACK Asserted (Setup, ACK Mode)2
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD Asserted to HACK Asserted (Setup, Ready Mode)
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
tRHH
12tHCLK
1
15tHCLK+tNH
tRDH
tRDD
HRD Deasserted to Data Invalid (Hold)
ns
ns
HRD Deasserted to Data Disable
10
Timing Requirements
tCSAL HCMS or HCIOMS Asserted to HALE Asserted (Delay)
tALCS
0
1
ns
ns
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
tRCSW
tALR
tRCS
HRD Deasserted to HCMS or HCIOMS Deasserted
HALE Deasserted to HRD Asserted
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
HALE Asserted Pulsewidth
HACK Asserted to HRD Deasserted (Hold, ACK Mode)
Address Valid to HALE Deasserted (Setup)
HALE Deasserted to Address Invalid (Hold)
0
5
0
ns
ns
ns
tALPW
tHKRD
tAALS
tALAH
4
1.5
2
ns
ns
ns
ns
4
1tNH are peripheral bus latencies (n
؋
tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
–30–
REV. 0
ADSP-2191M
HCMS
HIOMS
tALCS
tRCS W
tCS A L
H ALE
tALPW
tRCS
tAL R
HRD
tHKRD
tRHKS
tRHKH
HACK
( ACK
HA CK FOR EACH BYTE
MOD E)
tRHH
tRHS
HACK
(READY
MODE)
HA CK FIRST BYTE
tAL A H
tAALS
tRDH
tRDD
HA D15–0
H A16
AD DR ESS
VALID
D ATA
VA LID
D ATA
VALID
ADDR ESS
VALID
ST A RT
FIRST
WORD
FIRST
B YTE
LA ST
B YTE
STA RT
NEXT
WORD
Figure 16. Host Port ALE Mode Read Cycle Timing
REV. 0
–31–
ADSP-2191M
Host Port ACC Mode Read Cycle Timing
Table 18 and Figure 17 describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK,
Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.
Table 18. Host Port ACC Mode Read Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
1
1
tRHKS1
tRHKS2
tRHKH
tRHS
HRD Asserted to HACK Asserted (ACK Mode) First Byte
12tHCLK
15tHCLK+tNH
10
10
10
ns
ns
ns
ns
ns
HRD Asserted to HACK Asserted (Setup, ACK Mode)2
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
HRD Asserted to HACK Asserted (Setup, Ready Mode)
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
tRHH
12tHCLK
1
15tHCLK+tNH
tRDH
HRD Deasserted to Data Invalid (Hold)
ns
ns
tWSHKS
HWR Asserted to HACK Asserted (Setup) During Address
Latch
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
10
10
10
tWHHKH
tRDD
ns
ns
HRD Deasserted to Data Disable
Timing Requirements
tCSAL HCMS or HCIOMS Asserted to HALE Asserted (Delay)
tALCS
0
1
ns
ns
HALE Deasserted to Optional HCMS or HCIOMS
Deasserted
tRCSW
tALW
tALER
tCSR
HRD Deasserted to HCMS or HCIOMS Deasserted
HALE Asserted to HWR Asserted
HALE Deasserted to HWR Asserted
0
0.5
1
0
0
ns
ns
ns
ns
ns
HCMS or HCIOMS Asserted to HRD Asserted
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
HWR Deasserted to HALE Deasserted (Delay)
HACK Asserted to HRD Deasserted (Hold, ACK Mode)
Address Valid to HWR Deasserted (Setup)
HWR Deasserted to Address Invalid (Hold)
HACK Asserted to HWR Deasserted (Hold) During Address
Latch2
tRCS
tWAL
tHKRD
tADW
tWAD
tHKWAL
2.5
1.5
2
1
2
ns
ns
ns
ns
ns
1tNH are peripheral bus latencies (n
؋
tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at the same time.
2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
–32–
REV. 0
ADSP-2191M
HCMS
HIOMS
tALCS
tRCS W
tCSAL
HALE
tWAL
tRCS
tALW
HWR
HRD
tCS R
tALE R
tHKWAL
tRHKS
tHKRD
tRHKH
tWSHKS
HACK
(ACK
HA CK EAC H BYTE
MODE)
tWHHKH
tRHH
tRHS
H ACK
(READY
MODE)
HA CK FIRST BYTE
tADW
tWAD
tRDH
tRDD
HAD15–0
HA16
ADDRESS
VALID
D ATA
VALID
DATA
VALID
A DDRESS
VA LID
S TAR T
NEX T WORD
START
FIRST WORD
FIRST
B YTE
LA ST
BYTE
Figure 17. Host Port ACC Mode Read Cycle Timing
REV. 0
–33–
ADSP-2191M
Serial Ports
Table 19 and Figure 18 describe SPORT transmit and receive operations, while Figure 19 and Figure 20 describe SPORT Frame
Sync operations.
1, 2
Table 19. Serial Ports
Parameter
Min
Max
Unit
External Clock
Timing Requirements
tSFSE
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TFS/RFS Setup Before TCLK/RCLK3
4
4
1.5
4
0.5tHCLK–1
2tHCLK
ns
ns
ns
ns
ns
ns
TFS/RFS Hold After TCLK/RCLK3
Receive Data Setup Before RCLK3
Receive Data Hold After RCLK3
TCLK/RCLK Width
TCLK/RCLK Period
Internal Clock
Timing Requirements
tSFSI
TFS Setup Before TCLK4; RFS Setup Before RCLK3
4
3
2
5
ns
ns
ns
ns
tHFSI
tSDRI
tHDRI
TFS/RFS Hold After TCLK/RCLK3
Receive Data Setup Before RCLK3
Receive Data Hold After RCLK3
External or Internal Clock
Switching Characteristics
tDFSE
TFS/RFS Delay After TCLK/RCLK (Internally
14
ns
ns
Generated FS)4
tHOFSE
TFS/RFS Hold After TCLK/RCLK (Internally
3
Generated FS)4
External Clock
Switching Characteristics
tDDTE
tHDTE
Internal Clock
Transmit Data Delay After TCLK4
Transmit Data Hold After TCLK4
13.4
13.4
ns
ns
4
4
Switching Characteristics
tDDTI
tHDTI
Transmit Data Delay After TCLK4
ns
ns
ns
Transmit Data Hold After TCLK4
TCLK/RCLK Width
tSCLKIW
0.5tHCLK–3.5 0.5tHCLK+2.5
Enable and Three-State5
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable from External TCLK4
0
0
12.1
13
13
ns
ns
ns
ns
Data Disable from External TCLK4
Data Enable from Internal TCLK4
Data Disable from External TCLK4
12
External Late Frame Sync
Switching Characteristics
tDDTLFSE
tDTENLFSE
DataDelayfromLateExternalTFSwithMCE=1, MFD=06, 7
10.5
ns
ns
Data Enable from Late FS or MCE=1, MFD=06, 7
3.5
1To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay
and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.
2Word selected timing for I2S mode is the same as TFS/RFS timing (normal framing only).
3Referenced to sample edge.
4Referenced to drive edge.
5Only applies to SPORT0/1.
6MCE=1, TFS enable, and TFS valid follow tDDTENFS and tDDTLFSE
.
7If external RFSD/TFS setup to RCLK/TCLK>0.5tLSCK, tDDTLSCK and tDTENLSCK apply; otherwise tDDTLFSE and tDTENLFS apply.
–34–
REV. 0
ADSP-2191M
DATA RECEIVE-INTERNAL CLOCK
DATA RECEIVE-EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
t
t
SCLKW
SCLKIW
RCLK
RCLK
t
t
DFSE
HOFSE
DFSE
t
t
HOFSE
t
t
t
t
HFSE
SFSI
HFSI
SFSE
RFS
DR
RFS
DR
t
t
t
SDRE
HDRE
t
SDRI
HDRI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT-INTERNAL CLOCK
DATA TRANSMIT-EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
t
t
SCLKW
SCLKIW
TCLK
TFS
DT
TCLK
TFS
DT
t
t
DFSE
DFSE
t
HOFSE
t
t
HOFSE
t
t
t
SFSI
t
SFSE
HFSI
HFSE
t
t
DDTI
DDTE
t
HDTI
HDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK (EXT)
TFS ("LATE," EXT.)
TCLK / RCLK
t
t
DDTEN
DDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TFS ("LATE," INT.)
TCLK / RCLK
t
DDTIN
t
DDTTI
DT
Figure 18. Serial Ports
REV. 0
–35–
ADSP-2191M
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
tHOSFSE/ I
tSFSE/ I
RFS
tDDTE/ I
tHDTE/I
tDTENLFSE
DT
1ST BIT
2ND BIT
tDDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
tHOSFSE/ I
tSFSE/ I
TFS
tDDTE/ I
tHDTE/ I
tDTENLFSE
1ST BIT
2ND BIT
DT
tDDTLFSE
Figure 19. Serial Ports—External Late Frame Sync (Frame Sync Setup > 0.5t
)
SCLK
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
DRIVE
SAMPLE
RCLK
RFS
t
HOFSE/ I
t
SFSE/ I
t
t
DDTE/ I
DTENLFSE
t
HDTE/ I
1ST BIT
2ND BIT
DT
t
DDTLFSE
LATE EXTERNAL TFS
DRIVE
DRIVE
SAMPLE
TCLK
t
HOFSE/ I
t
SFSE/ I
TFS
DT
t
t
DDTE/ I
DTENLFSE
t
HDTE/ I
1ST BIT
2ND BIT
t
DDTLFSE
Figure 20. Serial Ports—External Late Frame Sync (Frame Sync Setup < 0.5t
)
HCLK
–36–
REV. 0
ADSP-2191M
Serial Peripheral Interface (SPI) Port—Master Timing
Table 20 and Figure 21 describe SPI port master operations.
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Min
Max
Unit
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tDDSPID
tHDSPID
SPIxSEL Low to First SCLK edge (x=0 or 1)
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCLK Edge to SPIxSEL High (x=0 or 1)
Sequential Transfer Delay
2tHCLK–3
2tHCLK–3
2tHCLK–3
4tHCLK–1
2tHCLK–3
2tHCLK–2
0
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Edge to Data Output Valid (Data Out Delay)
SCLK Edge to Data Output Invalid (Data Out Hold)
6
5
0
Timing Requirements
tSSPID Data Input Valid to SCLK Edge (Data Input Setup)
tHSPID
8
1
ns
ns
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
tS P IC H M
SPIxSEL
(OUTPUT)
(x = 0 or 1)
tH D S M
tS P ITD M
tS P IC L K
tS D S C IM
tS P IC L M
SC LK
(CPOL = 0)
(OUTPUT)
tS P IC L M
tS P IC H M
SCLK
(CPOL = 1)
(OUTPUT)
tD D S P ID
tH D S P ID
MOSI
(OUTPUT)
MSB
LSB
tS S PID
tS S P ID
tH S P ID
tH S PID
CPHA = 1
MISO
(INPUT)
MSB
VALID
LSB
VALID
tD D S P ID
tH D S P ID
MOSI
(OU TPUT)
MSB
LSB
CPHA = 0
tS S P ID
tH S P ID
MSB
LSB
MISO
VALID
VALID
(IN PUT)
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
REV. 0
–37–
ADSP-2191M
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 21 and Figure 22 describe SPI port slave operations.
Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDSOE
SPISS Assertion to Data Out Active
0
0
0
0
8
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPISS Deassertion to Data High Impedance
SCLK Edge to Data Out Valid (Data Out Delay)
SCLK Edge to Data Out Invalid (Data Out Hold)
10
10
10
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
tSSPID
tHSPID
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SPICLK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SPICLK Edge
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
2tHCLK
2tHCLK
4tHCLK
2tHCLK
2tHCLK+4
2tHCLK
1.6
ns
ns
ns
ns
ns
ns
ns
ns
2.4
SPISS
(INPUT)
tSPICHS
tSPICLS
tSPICLK
tHDS
tSPITDS
SCLK
(CPOL = 0)
(INPUT)
tSPICLS
tSDSCI
tSPICHS
SCLK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID tHDSPID
tDDSPID
tDSDHI
MISO
(OUTPUT)
MSB
LSB
CPHA = 1
tSSPID
tSSPID
tHSPID
tHSPID
MOSI
(INPUT)
MSB
VALID
LSB
VALID
tDDSPID
tDSOE
tDSDHI
MISO
(OUTPUT)
LSB
MSB
CPHA = 0
tSSPID
tHSPID
MSB
VALID
LSB
VALID
MOSI
(INPUT)
Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing
–38–
REV. 0
ADSP-2191M
Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing
Figure 23 describes UART port receive and transmit operations. The maximum baud rate is HCLK/16. As shown in Figure 23 there
is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at
the data transmission rates for the UART.
HCLK
(SAMPLE
CLOCK)
DATA(5–8)
RXD
STOP
RECEIVE
INTERNAL
UART RECEIVE
INTERRUPT
UART RECEIVE BIT SET BY DATA STOP;
CLEARED BY FIFO READ
START
DATA(5–8)
STOP (1–2)
TXD
AS DATA
WRITTEN TO
BUFFER
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 23. UART Port—Receive and Transmit Timing
REV. 0
–39–
ADSP-2191M
JTAG Test And Emulation Port Timing
Table 22 and Figure 24 describe JTAG port operations.
Table 22. JTAG Port Timing
Parameter
Min
Max
Unit
Switching Characteristics
tDTDO
tDSYS
TDO Delay from TCK Low
8
22
ns
ns
System Outputs Delay After TCK Low1
0
Timing Requirements
tTCK
TCK Period
20
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low2
System Inputs Hold After TCK Low2
TRST Pulsewidth3
4
4
4
5
4tTCK
1System Outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,
TFS0, TFS1, RFS0, RFS1, BMS.
2System Inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,
CLKIN, RESET.
350 MHz max.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 24. JTAG Port Timing
–40–
REV. 0
ADSP-2191M
Output Drive Currents
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Figure 25 shows typical I-V characteristics for the output drivers
of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
• Number of output pins that switch during each cycle (O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
60
V
= 3.65V @ – 40°C
DDEXT
• Their voltage swing (VDD
)
V
= 3.3V @ + 25°C
DDEXT
40
20
and is calculated by the formula below.
VOH
OUTPUT CURRENT
PEXT = O × C × VDD2 × f
0
–20
V
= 3.0V @ + 85°C
= 3.0V @ + 85°C
DDEXT
V
DDEXT
The load capacitance includes the processor’s package capaci-
VOL
–40
tance (C ). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
IN
V
= 3.3V @ + 25°C
= 3.65V @ – 40°C
DDEXT
DDEXT
–60
V
low at a maximum rate of 1/(2t ). The write strobe can switch
CK
everycycleatafrequencyof1/t .Selectpinsswitchat1/(2t ),
–80
CK
CK
INPUT CURRENT
but selects can switch on each cycle. For example, estimate P
with the following assumptions:
EXT
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SOURCE (
) VOLTAGE – V
VDDEXT
• A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
Figure 25. Typical Drive Currents
• One 64K
؋
16 RAM chip is used with a load of 10 pF Power Dissipation
• Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
• External data memory writes occur every other cycle, a
rate of 1/(4tHCLK), with 50% of the pins switching
• The bus cycle time is 80 MHz (tHCLK = 12.5 nsec)
The P
equation is calculated for each class of pins that can
EXT
drive as shown in Table 23.
Table 23. P
Pin Type
Calculation Example
EXT
2
# of Pins
% Switching
؋
C ؋
f ؋
V = P
EXT
DD
Address
MSx
WR
Data
CLKOUT
15
1
1
16
1
50
0
—
50
—
10 pF
10 pF
10 pF
10 pF
10 pF
؋
20 MHz ؋
20 MHz ؋
40 MHz ؋
20 MHz ؋
80 MHz ؋
10.9 V ؋
10.9 V ؋
10.9 V ؋
10.9 V ؋
10.9 V = .01635 W
= 0 W
= .00436 W
= .01744 W
= .00872 W
P
EXT=.04687 W
Test Conditions
The DSP is tested for output enable, disable, and hold time.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Output Disable Time
Outputpinsareconsideredtobedisabledwhentheystopdriving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
PTOTAL= PEXT + PINT
Where:
to decay by – V is dependent on the capacitive load, C and the
L
• PEXT is from Table 23
load current, I . This decay time can be approximated by the
L
equation below.
• PINT is IDDINT
؋
2.5 V, using the calculation IDDINT listed in Power Dissipation on page 41.
Note that the conditions causing a worst-case P
are different
CL∆V
EXT
---------------
=
tDECAY
from those causing a worst-case P
. Maximum P
cannot
INT
INT
IL
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
REV. 0
–41–
ADSP-2191M
Example System Hold Time Calculation
The output disable time t
is the difference between
DIS
To determine the data output hold time in a particular system,
t
t
and t
as shown in Figure 26. The time
MEASURED
MEASURED
DECAY
firstcalculatet
usingtheequationatOutputDisableTime
is the interval from when the reference signal
DECAY
on page 41. Choose –V to be the difference between the
ADSP-2191M’s output voltage and the input threshold for the
switchestowhentheoutputvoltagedecays–Vfromthemeasured
output high or output low voltage. The t iscalculatedwith
DECAY
device requiring the hold time. A typical –V will be 0.4 V. C is
test loads C and I , and with –V equal to 0.5 V.
L
L
L
thetotalbuscapacitance(perdataline), andI isthetotalleakage
L
or three-state current (per data line). The hold time will be
t
plus the minimum disable time (i.e., t
for the
DECAY
DATRWH
REFERENCE
SIGNAL
write cycle).
Capacitive Loading
tMEASURED
tENA
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 30). The delay and hold specifica-
tions givenshould be deratedby afactor of1.5 ns/50 pF for loads
other than the nominal value of 50 pF. Figure 28 and Figure 29
show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
outputdisabledelays;seeOutputDisableTimeonpage 41.)The
graphs in these figures may not be linear outside the ranges
shown.
tDIS
VOH (MEASURED)
V
OH (MEASURED) – ⌬V
2.0V
1.0V
VOL (MEASURED) + ⌬V
VOL (MEASURED)
tDECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 26. Output Enable/Disable
40
I
OL
30
RISE TIME
TO
OUTPUT
PIN
20
10
0
+1.5V
50pF
I
OH
0
50
100
150
200
250
Figure 27. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
LOAD CAPACITANCE – pF
Figure 29. Typical Output Rise Time (10%-90%,
= Minimum at Maximum Ambient
V
DDEXT
Operating Temperature) vs. Load Capacitance
INPUT
OR
OUTPUT
1.5V
1.5V
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Figure 28. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Thermal Characteristics
The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array(mini-BGA) package. TheADSP-2191M isspecified
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
for an ambient temperature (T
formula below.
) as calculated using the
AMB
driving. The output enable time t
is the interval from when
ENA
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 26). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
ToensurethattheT
datasheetspecificationisnotexceeded,
AMB
a heatsink and/or an air flow source may be used. A heatsink
should be attached to the ground plane (as close as possible to
the thermal pathways) with a thermal adhesive.
TAMB = TCASE – PD × θCA
–42–
REV. 0
ADSP-2191M
Where:
30
20
10
• TAMB = Ambient temperature (measured near top
surface of package)
• PD = Power dissipation in W (this value depends upon
the specific application; a method for calculating PD is
shown under Power Dissipation).
• θCA = Value from Table 24.
• For the LQFP package: θJC = 0.96°C/W
For the mini-BGA package: θJC = 8.4°C/W
0
Table 24. θCA Values
Airflow
(Linear Ft./Min.)
Airflow
0
0
100
0.5
200
1
400
2
600
3
–10
0
50
100
150
200
250
LOAD CAPACITANCE – pF
(Meters/Second)
LQFP:
θCA (°C/W)
Mini-BGA:
θCA (°C/W)
Figure 30. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
44.3 41.4 38.5 35.3 32.1
26 24 22 20.9 19.8
REV. 0
–43–
ADSP-2191M
144-Lead LQFP Pinout
Table 25 lists the LQFP pinout by signal name. Table 26 lists
the LQFP pinout by pin.
Table 25. 144-Lead LQFP Pins (Alphabetically by Signal)
Pin
No. Signal
Pin
No. Signal
Pin
No. Signal
Pin
No. Signal
Pin
No.
Signal
A0
A1
A2
A3
A4
A5
A6
A7
84
85
86
87
88
89
91
92
93
95
96
97
98
99
BYPASS
72
GND
33
54
55
77
80
94
HCMS
HCIOMS
HRD
HWR
IOMS
MS0
27
28
31
32
TCLK1
TCLK2
TDI
65
47
75
74
59
66
48
43
44
45
76
79
53
13
25
40
CLKIN
CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
132 GND
130 GND
123 GND
124 GND
125 GND
126 GND
128 GND
135 GND
136 HA16
137 HACK
138 HACK_P
139 HAD0
140 HAD1
141 HAD2
142 HAD3
144 HAD4
TDO
114 TFS0
115 TFS1
116 TFS2
117 TMR0
119 TMR1
83
34
35
36
37
38
39
41
42
61
68
50
105 MS1
129 MS2
134 MS3
23
26
24
3
4
6
7
8
A8
A9
OPMODE
PF0
PF1
PF2
PF3
PF4
PF5
PF6
TMR2
TMS
TRST
TXD
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
ACK
BG
101 D11
102 D12
103 D13
104 D14
106 D15
107 DR0
108 DR1
109 DR2
120 DT0
111 DT1
110 DT2
63
90
1
2
HAD5
HAD6
HAD7
HAD8
HAD9
HAD10
HAD11
HAD12
HAD13
HAD14
HAD15
HALE
9
PF7
10
11
12
14
15
17
18
20
21
22
30
RCLK0
RCLK1
RCLK2
RD
RESET
RFS0
RFS1
RFS2
RXD
TCK
TCLK0
100
118
131
143
19
58
82
127
121
133
60
67
49
56
64
46
81
5
122 VDDEXT
73
62
69
51
52
78
57
VDDINT
VDDINT
VDDINT
VDDINT
WR
BGH
BMODE0
BMODE1
BMS
BR
70
71
EMU
GND
113 GND
112 GND
16
29
XTAL
–44–
REV. 0
ADSP-2191M
Table 26. 144-Lead LQFP Pins (Numerically by Pin Number)
Pin
Pin
Pin
Pin
Pin
No. Signal
No. Signal
No. Signal
No. Signal
No. Signal
1
2
3
4
5
6
7
8
D14
D15
HAD0
HAD1
GND
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
HALE
HRD
HWR
GND
PF0
PF1
PF2
PF3
PF4
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
TFS0
DR0
RCLK0
RFS0
VDDEXT
DT1
TCLK1
TFS1
DR1
RCLK1
RFS1
BMODE0
BMODE1
BYPASS
RESET
TDO
TDI
TMS
GND
TCK
TRST
GND
EMU
VDDINT
OPMODE
A0
88
89
90
91
92
93
94
95
96
97
98
99
A4
A5
VDDEXT
A6
A7
A8
GND
A9
A10
A11
A12
A13
117 MS2
118 VDDEXT
119 MS3
120 ACK
121 WR
122 RD
123 D0
124 D1
125 D2
126 D3
127 VDDINT
128 D4
129 GND
130 CLKOUT
131 VDDEXT
132 CLKIN
133 XTAL
134 GND
135 D5
136 D6
137 D7
138 D8
139 D9
140 D10
141 D11
142 D12
143 VDDEXT
144 D13
HAD2
HAD3
HAD4
HAD5
HAD6
HAD7
HAD8
VDDEXT
HAD9
HAD10
GND
HAD11
HAD12
VDDINT
HAD13
HAD14
HAD15
HA16
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PF5
VDDEXT
PF6
PF7
100 VDDEXT
101 A14
102 A15
103 A16
104 A17
105 GND
106 A18
107 A19
108 A20
109 A21
110 BGH
111 BG
TMR0
TMR1
TMR2
DT2
TCLK2
TFS2
DR2
RCLK2
RFS2
RXD
TXD
GND
GND
DT0
HACK_P
VDDEXT
HACK
HCMS
HCIOMS
GND
112 BR
113 BMS
114 IOMS
115 MS0
116 MS1
A1
A2
A3
TCLK0
VDDINT
REV. 0
–45–
ADSP-2191M
144-Lead Mini-BGA Pinout
Table 27 lists the mini-BGA pinout by signal name. Table 28
lists the mini-BGA pinout by ball number.
Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal)
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Signal
Signal
Signal
Signal
Signal
A0
A1
A2
A3
A4
A5
A6
A7
J11
H9
BYPASS
CLKIN
M11 GND
F7
F8
F9
G4
G5
G6
H5
L6
M1
HALE
HCIOMS
HCMS
HRD
HWR
IOMS
MS0
J1
J3
H1
J2
K2
E8
D9
A9
C9
D8
TCLK0
TCLK1
TCLK2
TDI
TDO
TFS0
TFS1
TFS2
TMR0
TMR1
J6
A5
C6
D7
A7
C7
A6
B7
A4
C5
B5
D5
A3
C4
B4
C3
A2
B1
B2
L7
K9
L5
H6
L8
H4
J10
A1
GND
GND
GND
GND
GND
GND
GND
GND
M9
K5
K12
L11
M8
J8
M5
K4
L4
H10 CLKOUT
G12 D0
H11 D1
G10 D2
F12 D3
G11 D4
F10 D5
F11 D6
E12 D7
E11 D8
E10 D9
MS1
MS2
A8
A9
GND
M12 MS3
OPMODE
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
ACK
BG
HACK
HACK_P
HAD0
HAD1
HAD2
HAD3
HAD4
HAD5
HAD6
HAD7
HAD8
HAD9
HAD10
HAD11
HAD12
HAD13
HAD14
H3
G1
C1
B3
C2
D1
D4
D3
D2
E1
E4
E2
F1
E3
F2
G2
F3
G3
H2
H12 TMR2
J4
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
RCLK0
RCLK1
RCLK2
RD
RESET
RFS0
RFS1
RFS2
RXD
TCK
K1
L1
M2
L2
M3
L3
K3
M4
K7
J9
TMS
TRST
TXD
K10
J12
M7
E5
E6
F5
E9
D10
D11 D11
D10 D12
D12 D13
C11 D14
C12 D15
B12 DR0
B11 DR1
A11 DR2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
F6
G7
G8
H7
H8
D6
F4
G9
J7
C8
B6
J5
B8
A8
DT0
C10 DT1
B10 DT2
L10 EMU
L9
A10 GND
B9 GND
L12 VDDINT
K8 VDDINT
M10 VDDINT
M6
K6
BGH
BMODE0
BMODE1
BMS
BR
GND
WR
XTAL
A12 HAD15
E7 HA16
K11
–46–
REV. 0
ADSP-2191M
Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number)
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Ball
No.
Signal
Signal
Signal
Signal
Signal
A1
A2
A3
A4
A5
A6
A7
A8
A9
GND
D13
D9
D5
CLKIN
D3
D1
ACK
MS1
C6
C7
C8
C9
C10 BG
C11 A17
C12 A18
D1
D2
D3
D4
D5
D6
D7
D8
D9
CLKOUT
D2
WR
E11 A11
E12 A10
H4
H5
H6
H7
H8
H9
DT2
GND
DT0
VDDEXT
VDDEXT
A1
K9
DR1
K10 TMS
K11 TCK
K12 TDI
F1
F2
F3
F4
F5
F6
F7
F8
F9
HAD10
MS2
HAD12
HAD14
VDDINT
VDDEXT
VDDEXT
GND
L1
L2
L3
L4
L5
L6
L7
L8
L9
PF1
PF3
PF5
TMR1
DR2
GND
DR0
DT1
H10 A2
H11 A4
H12 OPMODE
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
HAD3
HAD6
HAD5
HAD4
D8
VDDINT
D0
A10 BMS
A11 A21
A12 GND
GND
GND
HALE
HRD
F10 A8
F11 A9
F12 A6
HCIOMS
TMR2
RCLK2
TCLK0
VDDINT
TFS1
RCLK1
EMU
A0
B1
B2
B3
B4
B5
B6
B7
B8
B9
D14
D15
HAD1
D11
D7
XTAL
D4
RD
BMODE1
L10 BMODE0
L11 TDO
L12 RESET
MS3
MS0
G1
G2
G3
G4
G5
G6
G7
G8
G9
HACK_P
HAD13
HAD15
GND
GND
GND
VDDEXT
VDDEXT
VDDINT
D10 A15
D11 A14
D12 A16
M1
M2
M3
M4
M5
M6
M7
M8
M9
GND
PF2
PF4
E1
E2
E3
E4
E5
E6
E7
E8
E9
HAD7
PF7
BR
HAD9
HAD11
HAD8
VDDEXT
VDDEXT
GND
TRST
PF0
HWR
TFS2
RFS2
TXD
TFS0
TCLK1
B10 BGH
B11 A20
B12 A19
C1
C2
C3
C4
C5
G10 A5
G11 A7
G12 A3
PF6
HAD0
HAD2
D12
D10
D6
TMR0
TCLK2
RXD
RCLK0
RFS0
M10 RFS1
M11 BYPASS
M12 GND
IOMS
A13
H1
H2
H3
HCMS
HA16
HACK
E10 A12
REV. 0
–47–
ADSP-2191M
OUTLINE DIMENSIONS
144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)
22.00 BSC SQ
20.00 BSC SQ
0.75
0.60
0.45
109
144
1
108
0.27
0.22
0.17
TYP
SEATING
PLANE
0.08 MAX LEAD
COPLANARITY
1.45
1.40
1.35
0.15
0.05
73
3 6
72
37
1.60 MAX
0.50 BSC
LEAD PITCH
DETAIL A
DETAIL A
TOP VIEW (PINS DOWN)
NOTES:
1.
2.
DIMENSIONS IN MILLIMETERS.
ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.
3.
CENTER DIMENSIONS ARE NOMINAL.
144-BALL MINI-BGA (CA-144A)
A1 CORNER INDEX
TRIANGLE
10.10
10.00 SQ
9.90
12 11 10 9 8
7 6 5 4 3 2 1
A
B
C
D
E
F
8.80
BSC
SQ
G
H
J
K
L
0.80
BSC
BALL
PITCH
M
BOTTOM VIEW
TOP VIEW
1.70
MAX
DETAIL A
0.85
MIN
0.25
MIN
NOTES:
SEATING
PLANE
0.55
0.50
0.45
1.
2.
DIMENSIONS IN MILLIMETERS.
ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE TO
THE PACKAGE EDGES.
BALL
DIAMETER
0.10 MAX BALL
COPLANARITY
DETAIL A
3.
4.
ACTUAL POSITION OF EACH BALL IS WITHIN 0.08
OF ITS IDEAL POSITION, RELATIVE TO THE BALL
GRID.
CENTER DIMENSIONS ARE NOMINAL.
–48–
REV. 0
ADSP-2191M
ORDERING GUIDE
Instruction
Ambient Temperature Range Rate (MHz)
Package
Description
1, 2
Part Number
Operating Voltage
ADSP-2191MKST-160
ADSP-2191MBST-140
ADSP-2191MKCA-160
ADSP-2191MBCA-140
0ºC to 70ºC
–40ºC to +85ºC
0ºC to 70ºC
160
140
160
140
144-Lead LQFP
144-Lead LQFP
144-Ball Mini-BGA 2.5 Int./3.3 Ext. V
144-Ball Mini-BGA 2.5 Int./3.3 Ext. V
2.5 Int./3.3 Ext. V
2.5 Int./3.3 Ext. V
–40ºC to +85ºC
1ST = Plastic Thin Quad Flatpack (LQFP).
2CA = Mini Ball Grid Array
REV. 0
–49–
ADSP-2191M
–50–
REV. 0
ADSP-2191M
REV. 0
–51–
PRINTED IN U.S.A.
C02936-0-4/02(0)
相关型号:
ADSP-2195M
ADSP-2195M: 16-bit Fixed-Point DSP for Telecommunications Applications Preliminary Data Sheet (Rev. PrA. 9/01)
ETC
ADSP-2196M
ADSP-2196M: 16-bit Fixed-Point DSP. 160 MIPS Performance with Enhanced System I/O Prelim Data Sheet (Rev. PrA. 9/01)
ETC
©2020 ICPDF网 联系我们和版权申明