ADSP-219212MKST160_技术文档

a

DSP Microcomputer

ADSP-2192M

ADSP-2192M DUAL CORE DSP FEATURES

320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package

with PCI, USB, Sub-ISA, and CardBus Interfaces

3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface

with Bus Mastering over Four DMA Channels with

Scatter-Gather Support

Integrated USB 1.1 Compliant Interface

Sub-ISA Interface

AC’97 Revision 2.1 Compliant Interface for External

Audio, Modem, and Handset Codecs with DMA

Capability

80K Words of On-Chip RAM on P0, Configured as

64K Words On-Chip 16-Bit RAM for Data Memory and

16K Words On-Chip 24-Bit RAM for Program Memory

48K Words of On-Chip RAM on P1, Configured as

32K Words On-Chip 16-Bit RAM for Data Memory and

16K Words On-Chip 24-Bit RAM for Program Memory

4K Words of Additional On-Chip RAM Shared by Both

Cores, Configured as 4K Words On-Chip 16-Bit RAM

Flexible Power Management with Selectable Power-

Down and Idle Modes

Programmable PLL Supports Frequency Multiplication,

Enabling Full Speed Operation from Low Speed

Input Clocks

Dual ADSP-219x Core Processors (P0 and P1) on Each

ADSP-2192M DSP Chip

132K Words of Memory Includes 4K ꢀ 16-Bit Shared

Data Memory

2.5 V Internal Operation Supports 3.3 V/5.0 V

Compliant I/O

FUNCTIONAL BLOCK DIAGRAM

P0

P1

SHARED

MEMORY

16Kꢀ24 PM

64Kꢀ16 DM

BOOT ROM

ADDR DATA

16Kꢀ24 PM

4Kꢀ16 DM

32Kꢀ16 DM

BOOT ROM

ADDR DATA

ADSP-219x

DSP CORE

ADSP-219x

DSP CORE

(SEE FIGURE 1

ON PAGE 3)

(SEE FIGURE 1

ON PAGE 3)

CORE

INTERFACE

CORE

INTERFACE

PROCESSOR P0

PROCESSOR P1

ADDR DATA

P1 DMA

ADDR DATA

P0 DMA

CONTROLLER

SHARED DSP

I/O MAPPED

REGISTERS

FIFOS

HOST PORT

GP I/O PINS

(AND

SERIAL PORT

JTAG

EMULATION

PORT

PCI 2.2

OR

USB 1.1

OPTIONAL

SERIAL

EEPROM)

AC'97

COMPLIANT

REV. 0

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use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

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registered trademarks are the property of their respective companies.

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Tel:781/329-4700

Fax:781/326-8703

www.analog.com

ADSP-2192M

ADSP-2192M DUAL CORE DSP FEATURES (continued)

Eight Dedicated General-Purpose I/O Pins with Integrated

Interrupt Support

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3

DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 3

DSP Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Internal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Register Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CardBus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Using the PCI Interface . . . . . . . . . . . . . . . . . . . . . . . 7

Using the USB Interface . . . . . . . . . . . . . . . . . . . . . 13

General USB Device Definitions . . . . . . . . . . . . . . . 17

Sub-ISA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PCI Interface to DSP Memory . . . . . . . . . . . . . . . . 22

USB Interface to DSP Memory . . . . . . . . . . . . . . . . 22

AC’97 Codec Interface to DSP Memory . . . . . . . . . 22

Data FIFO Architecture . . . . . . . . . . . . . . . . . . . . . 22

System Reset Description . . . . . . . . . . . . . . . . . . . . 23

Power Management Description . . . . . . . . . . . . . . . 24

Power Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 V Regulator Options . . . . . . . . . . . . . . . . . . . . . 24

Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 25

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Instruction Set Description . . . . . . . . . . . . . . . . . . . 26

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 26

Additional Information . . . . . . . . . . . . . . . . . . . . . . 28

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 28

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 31

ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 31

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 31

Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 34

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Environmental Conditions . . . . . . . . . . . . . . . . . . . 35

144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . 36

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 38

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 38

Each DSP Core Has a Programmable 32-Bit Interval Timer

Five DMA Channels Available on Each Core

Boot Methods Include Booting Through PCI Port, USB

Port, or Serial EEPROM

JTAG Test Access Port Supports On-Chip Emulation and

System Debugging

144-Lead LQFP Package

DSP CORE FEATURES

6.25 ns Instruction Cycle Time (Internal), for up to

160 MIPS Sustained Performance

ADSP-218x Family Code Compatible with the Same Easy

to Use Algebraic Syntax

Single-Cycle Instruction Execution

Dual Purpose Program Memory for Both Instruction and

Data Storage

Fully Transparent Instruction Cache Allows Dual Operand

Fetches in Every Instruction Cycle

Unified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-Bit

Accumulators

Single-Cycle Context Switch between Two Sets of

Computational and DAG Registers

Parallel Execution of Computation and Memory

Instructions

Pipelined Architecture Supports Efficient Code Execution

at Speeds up to 160 MIPS

Register File Computations with All Nonconditional,

Nonparallel Computational Instructions

Powerful Program Sequencer Provides Zero-Overhead

Looping and Conditional Instruction Execution

Architectural Enhancements for Compiled C/C++ Code

Efficiency

Architecture Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for

Added Registers, Ports, and Peripherals

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ADSP-2192M

GENERAL DESCRIPTION

The ADSP-2192M’s flexible architecture and comprehensive

instruction set support multiple operations in parallel. For

example, in one processor cycle, each DSP core within the

ADSP-2192M can:

TheADSP-2192Misasingle-chipmicrocomputeroptimizedfor

digital signal processing (DSP) and other high speed numeric

processing applications, and is ideally suited for PC peripherals.

The ADSP-2192M combines the ADSP-219x family base archi-

tecture (three computational units, two data address generators

and a program sequencer) into a chip with two core processors

(see the Functional Block Diagram on Page 1 and Figure 1).

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

• Update one or two data address pointers

• Perform a computational operation

DSP CORE

These operations take place while the processor continues to:

CACHE

64 ꢀ 24-BIT

• Receive and/or transmit data through the Host port (PCI

or USB interfaces)

DAG1

4 ꢀ 4 ꢀ 16

DAG2

4 ꢀ 4 ꢀ 16

PROGRAM

SEQUENCER

• Receive or transmit data through the AC’97

• Decrement the two timers

PM ADDRESS BUS

24

DSP Core Architecture

DM ADDRESS BUS

The ADSP-219xarchitectureis code compatiblewiththeADSP-

218x DSP family. Though the architectures are compatible, the

ADSP-219x architecture has many enhancements over the

ADSP-218x architecture. The enhancements to computational

units, data address generators, and program sequencer make the

ADSP-219x more flexible and more compiler friendly.

PM DATA BUS

24

16

BUS

CONNECT

(PX)

DM DATA BUS

CORE

INTERFACE

DATA

REGISTER

FILE

Indirect addressing options provide addressing flexibility: base

address registers for easier implementation of circular buffering,

pre-modify with no update, post-modify with update, pre- and

post-modify by an immediate 8-bit, twos-complement value.

INPUT

REGISTERS

RESULT

REGISTERS

BARREL

SHIFTER

ALU

MULT

The ADSP-219x instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Every single-word instruction can be executed in a

single processor cycle. The ADSP-219x assembly language uses

an algebraic syntax for ease of coding and readability. A compre-

hensive set of development tools supports program development.

16 ꢀ 16-BIT

TheFunctionalBlockDiagramon Page 1showsthearchitecture

of the ADSP-219x dual core DSP, while the block diagram of

Figure 1 illustrates the ADSP-219x DSP core. Each core

contains three independent computational units: the multi-

plier/accumulator (MAC), the ALU, and the shifter. The

computational units process 16-bit data from the register file and

have provisions to support multiprecision computations. The

ALU performs a standard set of arithmetic and logic operations;

division primitives are also supported. The MAC performs

single-cycle multiply, multiply/add, and multiply/subtract oper-

ations. The MAC has two 40-bit accumulators that help with

overflow. The shifter performs logical and arithmetic shifts, nor-

malization, denormalization, and derive exponent operations.

The shifter can be used to efficiently implement numeric format

control, including multiword and block floating-point

representations.

Figure 1. ADSP-219x DSP Core

The ADSP-2192M includes a PCI-compatible port, a USB-

compatible port, an AC’97-compatible port, a DMA controller,

a programmable timer, general-purpose Programmable Flag

pins, extensive interrupt capabilities, and on-chip program and

data memory spaces.

The ADSP-2192M integrates 132K words of on-chip memory

configured as 32K words (24-bit) of program RAM, and 100K

words (16-bit) of data RAM. power-down circuitry is also

provided to reduce power consumption. The ADSP-2192M is

available in a 144-lead LQFP package.

Fabricated in a high speed, low power, CMOS process, the

ADSP-2192M operates with a 6.25 ns instruction cycle time

(320 MIPS) using both cores. All instructions can execute in a

single DSP cycle.

Register-usage rules influence placement of input and results

within the computational units. For most operations, the com-

putational units’ data registers act as a data register file,

permitting any input or result register to provide input to any unit

for a computation. For feedback operations, the computational

units let the output (result) of any unit be input to any unit on

REV. 0

–3–

ADSP-2192M

the next cycle. For conditional or multifunction instructions,

there are restrictions on which data registers may provide inputs

or receive results from each computational unit. For more infor-

The programmable interval timer generates periodic interrupts.

A 16-bit count register (TCOUNT) is decremented every

n cycles where n-1 is a scaling value stored in a 16-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

mation, see the ADSP-219x DSP Instruction Set Reference

.

A powerful program sequencer controls the flow of instruction

execution. The sequencer supports conditional jumps, subrou-

tine calls, and low interrupt overhead. With internal loop

counters and loop stacks, the ADSP-219x core executes looped

code with zero overhead; no explicit jump instructions are

required to maintain loops.

Memory Architecture

The ADSP-2192M provides 132K words of on-chip SRAM

memory. This memory is divided into Program and Data

Memory blocks in each DSP’s memory map. In addition to the

internal memory space, the two cores can address two additional

and separate off-core memory spaces: I/O space and shared

memory space, as shown in Figure 2.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches. Each DAG maintains and

updates four 16-bit address pointers. Whenever the pointer is

used to access data (indirect addressing), it is pre- or post-

modified by the value of one of four possible modify registers. A

lengthvalueandbaseaddressmaybeassociatedwitheachpointer

to implement automatic modulo addressing for circular buffers.

Page registers in the DAGs allow linear or circular addressing

within 64K word boundaries of each of the memory pages, but

these buffers may not cross page boundaries. Secondary registers

duplicate all the primary registers in the DAGs; switching

between primary and secondary registers provides a fast context

switch.

TheADSP-2192M’stwocorescanaccess80Kand48Klocations

that are accessible through two 24-bit address buses, the PMA

andDMAbuses.TheDSPhasthreefunctionsthatsupportaccess

to the full memory map.

• TheDAGsgenerate24-bitaddressesfordatafetchesfrom

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page.

Efficient data transfer in the core is achieved with the use of

internal buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

theprogramsequencerbasesaddressesforrelativejumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two-word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

Program memory can store both instructions and data, permit-

ting the ADSP-219x to fetch two operands in a single cycle, one

from program memory and one from data memory. The DSP’s

dualmemorybusesalsolettheADSP-219xcorefetchanoperand

from data memory and the next instruction from program

memory in a single cycle.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

address bits. Beforeacrosspagejumporcall, theprogram

must set the program sequencer’s IJPG register to the

appropriate memory page.

DSP Peripherals

The Functional Block Diagram on Page 1 shows the DSP’s

on-chip peripherals, which include the Host port (PCI or USB),

AC’97 port, JTAG test and emulation port, flags, and interrupt

controller.

EachADSP-219xDSPcorehasanon-chipROMthatholdsboot

routines (See Booting Modes on Page 23.).

The ADSP-2192M can respond to up to thirteen interrupts at

any given time. A list of these interrupts appears in Table 2.

Interrupts

The AC’97 Codec port on the ADSP-2192M provides a

completesynchronous,full-duplexserialinterface.Thisinterface

supports the AC’97 standard.

The interrupt controller lets the DSP respond to 13 interrupts

withminimumoverhead.Thecontrollerimplementsaninterrupt

priority scheme as shown in Table 2. Applications can use the

unassigned slots for software and peripheral interrupts. The

DSP’s Interrupt Control (ICNTL) register (shown in Table 3)

provides controls for global interrupt enable, stack interrupt con-

figuration, and interrupt nesting.

TheADSP-2192Mprovidesuptoeightgeneral-purposeI/Opins

that are programmable as either inputs or outputs. These pins

are dedicated general-purpose Programmable Flag pins.

–4–

REV. 0

ADSP-2192M

DSP P0

DSP P1

ME MORY MAP

MEMORY MAP

ADDRESS

0x02 0FFF

0x02 0000

0x01 FFFF

0x02 0FF F

0x02 0000

0x01 FFFF

SHARED RAM

(1 6 ꢀ 4K)

SHARED RAM

(1 6 ꢀ 4K)

SAME

PAGE 2

PAGE 1

PAGE 2

PAGE 1

RESERVED

0x01 5000

0x01 4FFF

0x01 4000

0x01 5000

0x01 4FF F

0x01 4000

PROGRAM ROM

24 ꢀ 4K

0x01 3FFF

0x01 3FF F

PROGRAM RAM

(24 ꢀ 16K)

(2 4 ꢀ 16K)

0x01 0000

0x00 FFFF

0x01 0000

0x00 FFFF

DATA RAM

BLO CK3

(16 ꢀ 16K)

SHARED

DSP I/O

MAPPED

REGISTERS

0x00 C000

0x00 BFFF

RESERVED

DATA RAM

BLO CK2

(16 ꢀ 16K)

ADDRESS

0xFF FF

0x00 8000

0x00 7FFF

0x00 8000

0x00 7FF F

PAGE 0

DATA RAM

BLO CK1

DATA RAM

BLO CK1

(16 ꢀ 16K)

(1 6 ꢀ 16K)

0x00 4000

0x00 3FFF

0x00 4000

0x00 3FF F

PAGES 0 255

(16 ꢀ 256)

DATA RAM

BLO CK0

DATA RAM

BLO CK0

(16 ꢀ 16K)

(1 6 ꢀ 16K)

0x00 0000

0x00 00

0x00 0000

Figure 2. ADSP-2192M Internal/External Memory, Boot Memory, and I/O Memory Maps

Table 2. Vector Table

Table 2showstheinterruptvectorandDSP-to-DSPsemaphores

at reset of each of the peripheral interrupts. The peripheral inter-

rupt’s position in the IMASK and IRPTL register and its vector

address depend on its priority level, as shown in Table 2.

Vector

Address

Bit

Priority

Interrupt

Offset¹

Table 1. DSP-to-DSP Semaphores Register Table

Flag

0

1

2

Reset (non-maskable) 0x00

Power-Down (non-

maskable)

0x04

Bit

Direction Function

2

3

Kernel interrupt

(single step)

Stack Status

Mailbox

Timer

GPIO

0x08

0

1

2

3

Output

DSP–DSP Semaphore 0

DSP–DSP Semaphore 1

DSP–DSP Interrupt

Reserved

3

4

5

6

7

8

9

10

11

12

13

14

15

4

5

6

7

8

9

10

11

12

13

14

15

16

0x0C

0x10

0x14

0x18

0x1C

0x20

0x24

0x28

0x2C

0x30

0x34

0x38

0x3C

4

Reserved

5

Reserved

PCI Bus Master

DSP–DSP

6

Reserved

7

8

9

10

11

12

Output

Input

Register Bus Lock

DSP–DSP Semaphore 0

DSP–DSP Semaphore 1

DSP–DSP Interrupt

Reserved

FIFO0 Transmit

FIFO0 Receive

FIFO1 Transmit

FIFO1 Receive

Reserved

AC’97 Register–PDC Bus Access

Status

Reserved

AC’97 Frame

13

Input

PDC Interface Busy Status (write

from DSP pending)

Reserved

¹The interrupt vector address values are represented as offsets from

address 0x01 0000. This address corresponds to the start of Program

Memory in DSP P0 and P1.

14

15

Input

Register Bus Lock Status

REV. 0

–5–

ADSP-2192M

External Interfaces

Interrupt routines can either be nested with higher priority inter-

ruptstakingprecedenceorprocessed sequentially. Interruptscan

be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the highest priority unmasked interrupt is then selected. The

emulation, power-down, and reset interrupts are nonmaskable

with the IMASK register, but software can use the DIS INT

instruction to mask the power-down interrupt.

Several different interfaces are supported on the ADSP-2192M.

These include both internal and external interfaces. The three

separate PCI configuration spaces are programmable to set up

the device in various Plug-and-Play configurations.

The ADSP-2192M provides the following types of external inter-

faces: PCI, USB, Sub-ISA, CardBus, AC’97, and serial

EEPROM. The following sections discuss those interfaces.

Table 3. Interrupt Control (ICNTL) Register Bits

PCI 2.2 Host Interface

The ADSP-2192M includes a 33 MHz, 32-bit bus master PCI

interface that is compliant with revision 2.2 of the PCI specifica-

tion. This interface supports the high data rates.

Bit

Description

0–3

4

5

6

7

8–9

10

11

12

13–15

Reserved

Interrupt nesting enable

Global interrupt enable

Reserved

MAC biased rounding enable

Reserved

PC stack interrupt enable

Loop stack interrupt enable

Low power idle enable

Reserved

USB 1.1 Host Interface

The ADSP-2192M USB interface enables the host system to

configure and attach a single device with multiple interfaces and

various endpoint configurations. The advantages of this design

include:

• Programmable descriptors and class-specific command

interpreter.

• An on-chip 8052-compatible MCU allows the user to soft

download different configurations and support standard

or class-specific commands.

TheIRPTLregisterisusedtoforceandclearinterrupts. On-chip

stacks preserve the processor status and are automatically main-

tainedduringinterrupthandling. Tosupportinterrupt,loop, and

subroutine nesting, the PC stack is 33 levels deep, the loop stack

is eight levels deep, and the status stack is 16 levels deep. To

prevent stack overflow, the PC stack can generate a stack level

interrupt if the PC stack falls below three locations full or rises

above 28 locations full.

• Total of eight user-defined endpoints provided.

Endpoints can be configured as either BULK, ISO, or

INT, and the endpoints can be grouped and assigned to

any interface.

Sub-ISA Interface

In systems that combine the ADSP-2192M chip with other

devices on a single PCI interface, the ADSP-2192M Sub-ISA

mode is used to provide a simpler interface that bypasses the

ADSP-2192M’s PCI interface. In this mode the Combo Master

assumes all responsibility for interfacing the function to the PCI

bus, including provision of Configuration Space registers for the

ADSP-2192M system as a separate PnP function. In Sub-ISA

Mode the PCI Pins are reconfigured for ISA operation.

The following instructions globally enable or disable interrupt

servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and

computational registers exist. Switching between the primary

and secondary registers lets programs quickly service interrupts,

while preserving the DSP’s state.

CardBus Interface

The CardBus standard provides higher levels of performance

than the 16-bit PC Card standard. For example, 32-bit CardBus

cards are able to take advantage of internal bus speeds that can

be as much as four to six times faster than 16-bit PC Cards. This

designprovidesforacompact,ruggedcardthatcanbecompletely

inserted within its host computer without any external cabling.

DMA Controller

The ADSP-2192M has a DMA controller that supports

automated data transfers with minimal overhead for the DSP

core. Cycle stealing DMA transfers can occur between the

ADSP-2192M’s internal memory and any of its DMA-capable

peripherals. DMA transfers can also be accomplished between

any of the DMA-capable peripherals. DMA-capable peripherals

includethePCIandAC’97ports. EachindividualDMA-capable

peripheral has a dedicated DMA channel. DMA sequences do

not contend for bus access with the DSP core; instead, DMAs

“steal” cycles to access memory. All DMA transfers use the

Program Memory (PMA/PMD) buses shown in the Functional

Block Diagram on Page 1.

Because CardBus performance attains the same high level as the

host platform’s internal (PCI) system bus, it is an excellent way

to add high speed communications to the notebook form factor.

In addition, CardBus PC Cards operate at a power-saving

3.3 volts, extending battery life in most configurations.

This new 32-bit CardBus technology provides up to 132M bytes

per second of bandwidth. This performance makes CardBus an

ideal vehicle to meet the demands of high throughput communi-

cations such as ADSL.

–6–

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ADSP-2192M

DSP Core Register Space

CardBus PC Cards generate less heat and consume less power.

This is attained by:

Each DSP has an internal register that is accessible with no

latency. These registers are accessible only from within the DSP,

using the REG( ) instruction.

• Low voltage operation at 3.3 V

• Software control of clock speed

Peripheral Device Control Register Space

• Advanced power management mechanism

This Register Space is accessible by both DSPs, the PCI, Sub-

ISA, and USB Buses. Note that certain sections of this space are

exclusive to either the PCI, USB, or Sub-ISA Buses. These

registers control the operation of the peripherals of the ADSP-

2192M. The DSP accesses these registers using the I/O space

instruction.

AC’97 2.1 External Codec Interface

The industry standard AC’97 serial interface (AC-Link) incor-

porates a 7-pin digital serial interface that links compliant codecs

to the ADSP-2192M. The ACLink implements a bidirectional,

fixed rate, serial PCM digital stream. It handles multiple input

and output audio streams as well as control and status register

accesses using a time division multiplex scheme.

USB Register Space

These registers control the operation and configuration of the

USB Interface. Most of these registers are only accessible via the

USB Bus, although a subset is accessible to the DSP.

Serial EEPROM Interface

The Serial EEPROM for the ADSP-2192M can overwrite the

following information which is returned during the USB GET

DEVICE DESCRIPTOR command. During the Serial

EEPROM initialization procedure, the DSP is responsible for

writingtheUSBDescriptorVendor ID, USBDescriptorProduct

ID, USB Descriptor Release Number, and USB Descriptor

Device Attributes registers to change the default settings.

CardBus Interface

The ADSP-2192M’s PC CardBus interface meets the state and

timing specifications defined for PCMCIA’s PC CardBus

Standard April 1998 Release 6.1. It supports up to three card

functions. Multiple function PC cards require a separate set of

Configuration registers per function. A primary Card Informa-

tion Structure common to all functions is required. Separate

secondary Card Information Structures, one per function, are

also required. Data for each CIS is loaded by the DSP during

bootstrap loading.

All descriptors can be changed when downloading the RAM-

based MCU renumeration code, except for the Manufacturer

andProduct, whicharesupportedintheCONFIGDEVICEand

cannot be overwritten or changed by the Serial EEPROM.

• Vendor ID (0x0456)

The host PC can read the CIS data at any time. If needed, the

WAIT control can be activated to extend the read operation to

meet bus write access to the CIS data.

• Product ID (0x2192)

• Device Release Number (0x0100)

• Device Attributes (0x80FA): SP (1 = self-powered,

0 = bus-powered, default = 0); RW (1 = have remote

wake-up capability, 0 = no remote wake-up capability,

default = 0); C[7:0] (power consumption from bus

expressed in 2 mA units; default = 0xFA 500 mA)

Using the PCI Interface

The ADSP-2192M includes a 33 MHz, 32-bit PCI interface to

provide control and data paths between the part and the host

CPU. The PCI interface is compliant with the PCI Local Bus

Specification Revision 2.2. The interface supports bus mastering

as well as bus target interfaces. The PCI Bus Power Management

Interface Specification Revision 1.1 is supported and additional

features as needed by PCI designs are included.

• Manufacturer (ADI)

• Product (ADI Device)

Internal Interfaces

Target/Slave Interface

The ADSP-2192M provides three types of internal interfaces:

registers, codec, and DSP memory buses. The following sections

discuss those interfaces.

The ADSP-2192M PCI interface contains three separate func-

tions, each with its own configuration space. Each function

containsfourbaseaddressregistersusedtoaccessADSP-2192M

control registers and DSP memory. Base Address Register

(BAR) 1 is used to point to the control registers. The addresses

specified in these tables are offsets from BAR1 in each of the

functions. PCI memory-type accesses are used to read and write

the registers.

Register Interface

The register interface allows the PCI interface, USB interface,

and both DSPs to communicate with the I/O Registers. These

registers map into DSP, PCI, and USB I/O spaces.

Register Spaces

DSP memory accesses use BAR2 or BAR3 of each function.

BAR2 is used to access 24-bit DSP memory; BAR3 accesses

16-bit DSP memory. Maps of the BAR2 and BAR3 registers

appear in Table 8 on Page 11 and Table 9 on Page 12.

Several different register spaces are defined on the ADSP-

2192M, as described in the following sections.

PCI Configuration Space

These registers control the configuration of the PCI Interface.

Most of these registers are only accessible via the PCI Bus

although a subset is accessible to the DSP for configuration

during the boot.

The lower half of the allocated space pointed to by each DSP

memory BAR is the DSP memory for DSP core P0. The upper

half is the memory space associated with DSP core P1. PCI

transactions to and from DSP memory use the DMA function

within the DSP core. Thus each word transferred to or from PCI

REV. 0

–7–

ADSP-2192M

space uses a single DSP clock cycle to perform the internal DSP

data transfer. Byte-wide accesses to DSP memory are not

supported.

To initiate a scatter-gather transfer between memory and the

ADSP-2192M, the following steps are involved:

1. Software driver prepares a SGD table in system memory.

Each descriptor is eight bytes long and consists of an

address pointer to the starting address and the transfer

count of the memory buffer to be transferred. In any

given SGD table, two consecutive SGDs are offset by

eight bytes and are aligned on a 4-byte boundary. Each

SGD contains:

I/O type accesses are supported via BAR4. Both the control

registers accessible via BAR1 and the DSP memory accessible

via BAR2 and BAR3 can be accessed with I/O accesses. Indirect

access is used to read and write both the control registers and the

DSP memory. For the control register accesses, an address reg-

ister points to the word to be accessed while a separate register is

used to transfer the data. Read/write control is part of the address

register. Only 16-bit accesses are possible via the I/O space.

a. Memory Address (Buffer Start) – 4 bytes

b.Byte Count (Buffer Size) – 3 bytes

c. End of Linked List (EOL) – 1 bit (MSBit)

d.Flag – 1 bit (MSBit – 1)

A separate set of registers is used to perform the same function

for DSP memory access. Control for these accesses includes a

24-bit/16-bit select as well as direction control. The data register

for DSP memory accesses is a full 24 bits wide. 16-bit accesses

will be loaded into the lower 16 bits of the register. Table 10 on

Page 14 lists the registers directly accessible from BAR4.

2. Initialize DMA control registers with transfer-specific

information such as number of total bytes to transfer,

direction of transfer, etc.

3. Software driver initializes the hardware pointer to the

SGD table.

Bus Master Interface

As a bus master, the PCI interface can transfer DMA data

between system memory and the DSP. The control registers for

these transfers are available both to the host and to the DSPs.

Four channels of bus mastering DMA are supported on the

ADSP-2192M.

4. Engage scatter-gather DMA by writing the start value to

the PCI channel Control/Status register.

5. The ADSP-2192M will then pull in samples as pointed

to by the descriptors as needed by the DMA engine.

When the EOL is reached, a status bit will be set and the

DMA will end if the data buffer is not to be looped. If

looping is to occur, DMA transfers will continue from

the beginning of the table until the channel is turned off.

Two channels are associated with the receive data and two are

associated with the transmit data. The internal DSPs will

typically control initiation of bus master transactions. DMA host

bus master transfers can specify either standard circular buffers

in system memory or perform scatter-gather DMA to host

memory.

6. Bits in the PCI Control/Status register control whether

an interrupt occurs when the EOL is reached or when

the FLAG bit is set.

Each bus master DMA channel includes four registers to specify

a standard circular buffer in system memory. The Base Address

points to the start of the circular buffer. The Current Address is

a pointer to the current position within that buffer. The Base

Count specifies the size of the buffer in bytes, while the Current

Count keeps track of how many bytes need to be transferred

beforetheend ofthebufferisreached. Whentheendofthebuffer

is reached, the channel can be programmed to loop back to the

beginning and continue the transfers. When this looping occurs,

a Status bit will be set in the DMA Control Register.

Scatter-gather DMA uses four registers. In scatter-gather mode

the functions of the registers are mapped as shown in Table 4.

Table 4. Register Mapping in Scatter-Gather Mode

Standard Circular

Buffer Mode

Scatter-Gather Mode

Function

Base Address

Current Address

SGD Table Pointer

SGD Current Pointer

Address

The PCI DMA controller can be programmed to perform

scatter-gatherDMA,whentransferringsamplestoandfromDSP

memory. This mode allows the data to be split up in memory,

and yet be transferable to and from the ADSP-2192M without

processor intervention. In scatter-gather mode, the DMA con-

troller can read the memory address and word count from an

array of buffer descriptors called the Scatter-Gather Descriptor

(SGD) table. This allows the DMA engine to sustain DMA

transfers until all buffers in the SGD table are transferred.

Base Count

Current Count

SGD Pointer

Current SGD Count

In either mode of operation, interrupts can be generated based

upon the totalnumber of bytestransferred. Each channelhas two

24-bit registers to count the bytes transferred and generate inter-

rupts as appropriate. The Interrupt Base Count register specifies

the number of bytes to transfer prior to generating an interrupt.

The Interrupt Count register specifies the current number left

prior to generating the interrupt. When the Interrupt Count

–8–

REV. 0

ADSP-2192M

Table 6. PCI Control Register

register reaches zero, a PCI interrupt can be generated. Also, the

Interrupt Count register will be reloaded from the Interrupt Base

Count and continue counting down for the next interrupt.

Bit

Name

Comments

1–0

PCI Functions

Configured

00 = One PCI function

enabled, 01 = Two functions,

10 = Three functions

When0, disablesPCIaccesses

to the ADSP-2192M (termi-

nated with Retry). Must be set

to 1 by DSP ROM code after

initializing configuration

space. Once 1, cannot be

written to 0.

Table 5. PCI Interrupt Register

Bit Name

Comments

2

Configuration

Ready

0

1

Reserved

Reserve

Rx0DMAChannel Receive Channel 0 Bus

Interrupt

Rx1DMAChannel Receive Channel 1 Bus

Interrupt Master Transactions

Tx0DMAChannel Transmit Channel 0 Bus

Interrupt Master Transactions

Tx1DMAChannel Transmit Channel 1 Bus

Interrupt Master Transactions

Incoming Mailbox PCI to DSP Mailbox 0

0 PCI Interrupt Transfer

Incoming Mailbox PCI to DSP Mailbox 1

1 PCI Interrupt Transfer

Outgoing Mailbox DSP to PCI Mailbox 0

0 PCI Interrupt Transfer

Outgoing Mailbox DSP to PCI Mailbox 1

Master Transactions

2

3

4

5

6

7

8

9

15–3 Reserved

Similarities Between the Three PCI Functions

Each function contains a complete set of registers in the pre-

defined header region as defined in the PCI Local Bus

Specification Revision 2.2. In addition, each function contains

the optional registers to support PCI Bus Power Management.

Generally, registers that are unimplemented or read-only in one

function are similarly defined in the other functions. Each

function contains four base address registers that are used to

access ADSP-2192M control registers and DSP memory.

1 PCI Interrupt

Reserved

Transfer

Base address register (BAR) 1 is used to access the ADSP-

2192M control registers. Accesses to the control registers via

BAR1 uses PCI memory accesses. BAR1 requests a memory

allocation of 1024 bytes. Access to DSP memory occurs via

BAR2 and BAR3. BAR2 is used to access 24-bit DSP memory

(for DSP program downloading) while BAR3 is used to access

16-bit DSP memory. BAR4 provides I/O space access to both the

control registers and the DSP memory.

10 Reserved

11 I/O Wake-up

12 AC’97 Wake-up

I/O Pin Initiated

AC’97 Interface Initiated

13 PCI Master Abort PCI Interface Master Abort

Interrupt

14 PCI Target Abort

Interrupt

Detected

PCI Interface Target Abort

Detected

15 Reserved

Table 7 shows the configuration space headers for the three

spaces. While these are the default uses for each of the configu-

rations, they can be redefined to support any possible function

by writing to the class code register of that function during boot.

Additionally, during boot time, the DSP can disable one or more

of the functions. If only two functions are enabled, they will be

functions 0 and 1. If only one function is enabled, it will be

function 0.

PCI Interrupts

There are a variety of potential sources of interrupts to the PCI

host besides the bus master DMA interrupts. A single interrupt

pin, INTA is used to signal these interrupts back to the host. The

PCI Interrupt Register consolidates all of the possible interrupt

sources;thebitsofthisregisterareshowninTable 5. Theregister

bits are set by the various sources, and can be cleared by writing

a 1 to the bit(s) to be cleared.

Interactions Between the Three PCI Configurations

Because the configurations must access and control a single set

of resources, potential conflicts can occur between the control

specified by the configuration.

PCI Control Register.

This register must be initialized by the DSP ROM code prior to

PCI enumeration. (It has no effect in ISA or USB mode.) Once

the Configuration Ready bit has been set to 1, the PCI Control

Register becomes read-only, and further access by the DSP to

configuration space is disallowed. The bits of this register are

shown in Table 6.

Target accesses to registers and DSP memory can go through any

function. As long as the Memory Space access enable bit is set in

that function, then PCI memory accesseswhoseaddressesmatch

the locations programmed into a function, BARs 1–3 will be able

to read or write any visible register or memory location within the

ADSP-2192M. Similarly, if I/O space access enable is set, then

PCI I/O accesses can be performed via BAR4.

PCI Configuration Space

The ADSP-2192M PCI Interface provides three separate con-

figuration spaces, one for each possible function. This document

describes the registers in each function, their reset condition, and

how the three functions interact to access and control the ADSP-

2192M hardware.

Within the Power Management section of the configuration

blocks, there are a few interactions. The part will stay in the

highest power state between the three configurations.

REV. 0

–9–

ADSP-2192M

Table 7. PCI Configuration Space 0, 1, and 2

Address

Name

Reset

Comments

0x01–0x00

0x03–0x02

Vendor ID

0x11D4

0x2192

0x219A

0x219E

0x0

Writable from the DSP during initialization

Bus Master, Memory Space Capable, I/O Space

Capable

Config 0 Device ID

Config 1 Device ID

Config 2 Device ID

Command Register

0x05–0x04

0x07–0x06

Status Register

0x0

Bits enabled: Capabilities List, Fast B2B,

Medium Decode

0x08

0x0B–0x09

0x0C

0x0D

0x0E

Revision ID

Class Code

Cache Line Size

Latency Timer

Header Type

BIST

0x0

0x48000

0x0

0x80

0x0

Writable from the DSP during initialization

Read Only

Multifunction bit set

Unimplemented

0x0F

0x13–0x10

Base Address 1

0x08

Register Access for all ADSP-2192M Registers,

Prefetchable Memory

0x17–0x14

0x1B–0x18

0x1F–0x1C

0x23–0x20

0x27–0x24

0x2B–0x28

Base Address2

Base Address3

Base Address4

Base Address5

0x08

0x01

0x0

24-bit DSP Memory Access

16-bit DSP Memory Access

I/O access for control registers and DSP memory

Unimplemented

CIS RAM Pointer - Function 0 (Read Only)

CIS RAM Pointer - Function 1 (Read Only)

CIS RAM Pointer - Function 2 (Read Only)

Writable from the DSP during initialization

Unimplemented

Base Address6

0x0

Config 0 CardBus CIS Pointer

Config 1 CardBus CIS Pointer

Config 2 CardBus CIS Pointer

Subsystem Vendor ID

Config 0 Subsystem Device ID

Config 1 Subsystem Device ID

Config 2 Subsystem Device ID

Expansion ROM Base Address

Capabilities Pointer

0x1FF03

0x1FE03

0x1FD03

0x11D4

0x2192

0x219A

0x219E

0x0

0x2D–0x2C

0x2F–0x2E

0x33–0x30

0x34

0x40

Read Only

0x3C

Interrupt Line

0x0

0x3D

Interrupt Pin

0x1

Uses INTA Pin

0x3E

Min_Gnt

0x1

Read Only

0x3F

Max_Lat

0x4

Read Only

0x40

0x41

Capability ID

Next_Cap_Ptr

0x1

0x0

Power Management Capability Identifier

Read Only

0x43–0x42

0x45–0x44

0x46

Power Management Capabilities

Power Management Control/Status

Power Management Bridge

Power Management Data

0x6C22

0x0

Writable from the DSP during initialization

Bits 15 and 8 initialized only on Power-up

Unimplemented

0x47

0x0

Unimplemented

PCI Memory Map

Mode is typically used for Program Memory Access. Byte3 is

alwaysunused.Bytes[2:0]areusedfor24-bitMemoryLocations.

As shown in Figure 3, Bytes[2:1] are used for 16-bit Memory

Locations.

The ADSP-2192M On-Chip Memory is mapped to the PCI

Address Space. Because some ADSP-2192M Memory Blocks

are 24 bits wide (Program Memory) while others are 16 bits

(Data Memory), two different footprints are available in PCI

Address Space. These footprints are available to each PCI

function by accessing different PCI Base Address Registers

(BAR). BAR2 supports 24-bit “Unpacked” Memory Access.

BAR3 supports 16-bit “Packed” Memory Access.

In 16-bit (BAR3) Mode (Figure 4), each 32-bit (four Consecu-

tive PCI Byte Address Locations) PCI Data Word corresponds

to two ADSP-2192M Memory Locations. Bytes[3:2] contain

one 16-bit Data Word, Bytes[1:0] contain a second 16-bit Data

Word. BAR3 Mode is typically used for Data Memory Access.

Only the 16 MSBs of a Data Word are accessed in 24-bit Blocks;

the 8 LSBs are ignored.

In 24-bit (BAR2) Mode, each 32 bits (four Consecutive PCI

Byte Address Locations, which make up one PCI Data word)

correspond to a single ADSP-2192M Memory Location. BAR2

–10–

REV. 0

ADSP-2192M

PCI DWORD

BYTE3

BYTE2

BYTE1

BYTE0

BYTE3 IS

ALWAYS

UNUSED

PCI BYTE ADDRESS

DSP WORD ADDRESS

0x0000

0x0 0000

BYTE0 IS UNUSED

BY 16-BIT MEMORY

LOCATIONS

16K ꢀ 24-BIT BLOCK

16K ꢀ 16-BIT BLOCK

0x0 FFFC

0x1 0000

0x3FFF

0x4000

ALLOWED BYTE

ENABLES:

CBE = 1100

CBE = 0011

UNUSED

0x1 FFFC

0x7FFF

Figure 3. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 24-Bit Access (BAR2) Mode

PCI DWORD

BYTE3

BYTE2

BYTE1

BYTE0

PCI BYTE ADDRESS

DSP WORD ADDRESS

0x0000

DATA WORD N + 1

DATA WORD N

0x0 0000

DATA WORD N

UNUSED

ALL BYTES ARE USED.

DATA WORD N + 1

0x0 7FFE

0x0 8000

16K ꢀ 24-BIT BLOCK

0x3FFF

0x4000

ALLOWED BYTE

ENABLES:

CBE = 1100

CBE = 0011

CBE = 0000

16K ꢀ 16-BIT BLOCK

0x7FFF

0x0 FFFE

Figure 4. PCI Addressing for 24-Bit and 16-Bit Memory Blocks in 16-Bit Access (BAR3) Mode

24-Bit PCI DSP Memory Map (BAR2)

The complete PCI address footprint for the ADSP-2192M DSP

Memory Spaces in 24-bit (BAR2) Mode is shown in Table 8.

Table 8. 24-Bit PCI DSP Memory Map (BAR2 Mode)¹

Block

Byte3

Byte2

Byte1

Byte0

Offset

DSP P0 Data RAM

Block 0

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0000 0000

0x0000 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0000 FFFC

DSP P0 Data RAM

Block 1

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0001 0000

0x0001 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0001 FFFC

DSP P0 Data RAM

Block 2

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0002 0000

0x0002 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0002 FFFC

DSP P0 Data RAM

Block 3

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0003 0000

0x0003 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0003 FFFC

DSP P0 Program RAM UNUSED

D[23:16]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0004 0000

0x0004 0004

. . .

Block

UNUSED

. . .

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x0004 FFFC

REV. 0

–11–

ADSP-2192M

Table 8. 24-Bit PCI DSP Memory Map (BAR2 Mode)¹(continued)

Block

Byte3

Byte2

Byte1

Byte0

Offset

DSP P0 Program ROM UNUSED

D[23:16]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0005 0000

0x0005 0004

. . .

Block

UNUSED

. . .

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x0005 3FFC

Reserved Space

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

0x0005 4000

. . .

RESERVED

0x0007 FFFC

DSP P1 Data RAM

Block 0

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0008 0000

0x0008 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0008 FFFC

DSP P1 Data RAM

Block 1

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x0009 0000

0x0009 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x0009 FFFC

UNUSED

0x000A 0000

Reserved Space

UNUSED

. . .

D[15:8]

. . .

D[7:0]

. . .

UNUSED

. . .

0x000A 0004

. . .

UNUSED

D[15:8]

D[7:0]

UNUSED

0x000B FFFC

DSP P1 Program RAM UNUSED

D[23:16]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x000C 0000

0x000C 0004

. . .

Block

UNUSED

. . .

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000C FFFC

DSP P1 Program ROM UNUSED

D[23:16]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x000D 0000

0x000D 0004

. . .

Block

UNUSED

. . .

UNUSED

D[23:16]

D[15:8]

D[7:0]

0x000D 3FFC

Reserved Space

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

0x000D 4000

. . .

RESERVED

0x000F FFFC

¹The “. . .” entries in this table indicate the continuation of the pattern shown in the first rows of each section.

16-Bit PCI DSP Memory Map (BAR3)

The complete PCI address footprint for the ADSP-2192M DSP

Memory Spaces in 16-bit (BAR3) Mode is shown in Table 9.

Table 9. 16-Bit PCI DSP Memory Map (BAR3 Mode)¹

Block

Byte3

Byte2

Byte1

Byte0

Offset

DSP P0 Data RAM

Block 0

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0000 0000

0x0000 0004

. . .

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 7FFC

DSP P0 Data RAM

Block 1

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0000 8000

0x0000 8004

. . .

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0000 FFFC

DSP P0 Data RAM

Block 2

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0001 0000

0x0001 0004

. . .

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001 7FFC

–12–

REV. 0

ADSP-2192M

Table 9. 16-Bit PCI DSP Memory Map (BAR3 Mode)¹(continued)

Block

Byte3

Byte2

Byte1

Byte0

Offset

DSP P0 Data RAM

Block 3

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0001 8000

0x0001 8004

. . .

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0001 FFFC

DSP P0 Program RAM D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002 0000

0x0002 0004

Block

D[23:16]

. . .

D[23:16]

. . .

D[15:8]

. . .

D[23:16]

. . .

D[15:8]

. . .

0x0002 7FFC

DSP P0 Program ROM D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0002 8000

0x0002 8004

Block

D[23:16]

. . .

D[23:16]

. . .

D[15:8]

. . .

D[23:16]

. . .

D[15:8]

. . .

0x0002 9FFC

Reserved Space

RESERVED

0x0002 A000

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

0x0003 FFFC

DSP P1 Data RAM

Block 0

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004 0000

0x0004 0004

. . .

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0004 7FFC

DSP P1 Data RAM

Block 1

D[15:8]

D[7:0]

D[15:8]

D[7:0]

0x0004 8000

0x0004 8004

. . .

D[15:8]

. . .

D[7:0]

. . .

D[15:8]

. . .

D[7:0]

. . .

0x0004 FFFC

Reserved Space

RESERVED

0x0005 0000

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

0x0005 FFFC

DSP P1 Program RAM D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006 0000

0x0006 0004

Block

D[23:16]

. . .

D[23:16]

. . .

D[15:8]

. . .

D[23:16]

. . .

D[15:8]

. . .

0x0006 7FFC

DSP P1 Program ROM D[23:16]

D[15:8]

D[23:16]

D[15:8]

0x0006 8000

0x0006 8004

Block

D[23:16]

. . .

D[23:16]

. . .

D[15:8]

. . .

D[23:16]

. . .

D[15:8]

. . .

0x0006 9FFC

Reserved Space

RESERVED

0x0006 A000

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

RESERVED

. . .

0x0007 FFFC

¹The “. . .” entries in this table indicate the continuation of the pattern shown in the first rows of each section.

16-Bit PCI DSP I/O Memory Map (BAR4)

PCI Base Address Register (BAR4) allows indirect access to the

ADSP-2192M Control Registers and DSP Memory. The DSP

Memory Indirect Access Registers accessible from BAR4 are

shown in Table 10.

Using the USB Interface

The ADSP-2192M USB design enables the ADSP-2192M to be

configured and attached to a single device with multiple inter-

faces and various endpoint configurations, as follows:

1. Programmable descriptors and a class-specific com-

mand interpreter are accessible through the USB 8052

registers. An 8052 compatible MCU is supported

on-board, to enable soft downloading of different config-

urations, and support of standard or class-specific

commands.

DSP P0 Memory Indirect Address Space occupies PCI BAR4

Space 0x000000 through 0x01FFFF

DSP P1 Memory Indirect Address Space occupies PCI BAR4

Space 0x020000 through 0x03FFFF

All Indirect DSP Memory Accesses are 24-bit or 16-bit Word

Accesses.

2. A total of eight user-defined endpoints are provided.

Endpoints can be configured as BULK, ISO, or INT,

and can be grouped.

REV. 0

–13–

ADSP-2192M

Table 10. 16-Bit PCI DSP I/O Space Indirect Access

Registers Map (BAR4 Mode)

Table 11. USB DSP Register Definitions (continued)

Page Address Name Comment

Offset

Name

Reset

Comments

0x0C 0x46–0x47 DSP Memory Buffer RD EP8

0x03–0x00 Control 0x0000

Address and direction

control for register

accesses

Data for register

accesses

Offset

Register

0x0C 0x48–0x49 DSP Memory Buffer WR EP8

Address

0x07–0x04 Control 0x0000

Register

Offset

0x0C 0x50–0x53 DSP Memory Buffer Base EP9

Addr

Data

0x0C 0x54–0x55 DSP Memory Buffer Size EP9

0x0B–0x08 DSP

Memory

Address

0x0F–0x0C DSP

0x000000 Address and Direction

control for Indirect

DSP memory accesses

0x000000 Data for DSP memory

accesses

0x0C 0x56–0x57 DSP Memory Buffer RD EP9

Offset

0x0C 0x58–0x59 DSP Memory Buffer WR EP9

Offset

Memory

Data

0x0C 0x60–0x63 DSP Memory Buffer Base EP10

Addr

0x0C 0x64–0x65 DSP Memory Buffer Size EP10

0x0C 0x66–0x67 DSP Memory Buffer RD EP10

USB DSP Register Definitions

Foreachendpoint,fourregistersaredefinedtoprovideamemory

buffer in the DSP. These registers are defined for each endpoint

Offset

0x0C 0x68–0x69 DSP Memory Buffer WR EP10

shared by all defined interfaces, for a total of 4

ꢀ 8 = 32 registers.

Offset

These registers are read/write by the DSP only. They are

described in Table 11.

0x0C 0x70–0x73 DSP Memory Buffer Base EP11

Addr

0x0C 0x74–0x75 DSP Memory Buffer Size EP11

0x0C 0x76–0x77 DSP Memory Buffer RD EP11

Table 11. USB DSP Register Definitions

Offset

Page Address

Name

Comment

0x0C 0x78–0x79 DSP Memory Buffer WR EP11

0x0C 0x0–0x3

DSP Memory Buffer Base EP4

Addr

DSP Memory Buffer Size EP4

DSP Memory Buffer RD EP4

Offset

0x0C 0x80–0x81 USB Descriptor Vendor

0x0C 0x4–0x5

0x0C 0x6–0x7

ID

0x0C 0x84–0x85 USB Descriptor Product

ID

0x0C 0x8–0x9

DSP Memory Buffer WR EP4

Offset

0x0C 0x86–0x87 USB Descriptor Release

Number

0x0C 0x88–0x89 USB Descriptor Device

Attributes

0x0C 0x10–0x13 DSP Memory Buffer Base EP5

Addr

0x0C 0x14–0x15 DSP Memory Buffer Size EP5

0x0C 0x16–0x17 DSP Memory Buffer RD EP5

USB DSP Memory Buffer Base Addr Register

Points to the base address for the DSP memory buffer assigned

to this endpoint.

Offset

0x0C 0x18–0x19 DSP Memory Buffer WR EP5

Offset

BA[17:0] = Memory Buffer Base Address

0x0C 0x20–0x23 DSP Memory Buffer Base EP6

Addr

USB DSP Memory Buffer Size Register

Indicates the size of the DSP memory buffer assigned to this

endpoint.

0x0C 0x24–0x25 DSP Memory Buffer Size EP6

0x0C 0x26–0x27 DSP Memory Buffer RD EP6

Offset

SZ[15:0] = Memory Buffer Size

0x0C 0x28–0x29 DSP Memory Buffer WR EP6

Offset

USB DSP Memory Buffer RD Pointer Offset Register

The offset from the base address for the read pointer of the

memory buffer assigned to this endpoint.

0x0C 0x30–0x33 DSP Memory Buffer Base EP7

Addr

0x0C 0x34–0x35 DSP Memory Buffer Size EP7

0x0C 0x36–0x37 DSP Memory Buffer RD EP7

Offset

0x0C 0x38–0x39 DSP Memory Buffer WR EP7

Offset

RD[15:0] = Memory Buffer RD Offset

USB DSP Memory Buffer WR Pointer Offset Register

The offset from the base address for the write pointer of the

memory buffer assigned to this endpoint.

0x0C 0x40–0x43 DSP Memory Buffer Base EP8

Addr

WR[15:0] = Memory Buffer WR Offset

0x0C 0x44–0x45 DSP Memory Buffer Size EP8

–14–

REV. 0

ADSP-2192M

USB Descriptor Vendor ID

USB Descriptor Device Attributes

The Vendor ID returned in the GET DEVICE DESCRIPTOR

command is contained in this register. The DSP can change the

Vendor ID by writing to this register during the Serial EEPROM

initialization. The default Vendor ID is 0x0456, which corre-

sponds to Analog Devices, Inc.

The device-specific attributes returned in the GET DEVICE

DESCRIPTOR command are contained in this register. The

DSP can change the attributes by writing to this register during

the Serial EEPROM initialization. The default attributes are

0x80FA, which correspond to bus-powered, no remote wake-up,

and max power = 500 mA.

V[15:0] = Vendor ID (default = 0x0456)

• SP: 1 = self-powered, 0 = bus-powered (default = 0)

USB Descriptor Product ID

• RW: 1 = have remote wake-up capability, 0 = no remote

wake-up capability (default = 0)

The Product ID returned in the GET DEVICE DESCRIPTOR

command is contained in this register. The DSP can change the

Product IDby writing to this register duringtheSerialEEPROM

initialization. The default Product ID is 0x2192.

• C[7:0] = power consumption from bus, expressed in

2 mA units (default = xFA 500 mA)

P[15:0] = Product ID (default = 0x2192)

USB DSP MCU Register Definitions

MCU registers, described in Table 12, are defined in four

memory spaces that are grouped by the following address ranges:

USB Descriptor Release Number

The Release Number returned in the GET DEVICE DESCRIP-

TORcommandiscontainedinthisregister.TheDSPcanchange

the Release Number by writing to this register during the Serial

EEPROM initialization. The default Release Number is 0x0100,

which corresponds to Version 01.00.

• 0x0XXX—This address range defines general-purpose

USB status and control registers

• 0x1XXX—This address range defines registers that are

specific to endpoint setup and control

R[15:0] = Release Number (default = 0x0100)

• 0x2XXX—This address range defines the registers used

for REGIO accesses to the DSP register space

• 0x3XXX—ThisaddressrangedefinestheMCUprogram

memory write address space

Table 12. USB MCU Register Definitions

Address

Name

Comments

0x0000–0x0007

0x0008–0x000F

0x0010–0x0011

0x0012–0x0013

0x0014–0x0015

0x0016–0x0017

0x0030–0x0031

0x0032–0x0033

USB SETUP Token Cmd

USB SETUP Token Data

USB SETUP Counter

USB Control

USB Address/Endpoint

USB Frame Number

Eight Bytes Total

16-bit Counter

Miscellaneous control including re-attach

Address of device/active endpoint

Current frame number

Defined by Analog Devices

USB Serial EEPROM Mailbox 1

USB Serial EEPROM Mailbox 2

0x0034–0x0035

0x1000–0x1001

0x1002–0x1003

0x1004–0x1005

0x1006–0x1007

0x1008–0x1009

0x100A–0x100B

0x100C–0x100D

0x100E–0x100F

0x1010–0x1011

0x1012–0x1013

0x1014–0x1015

0x1016–0x1017

0x1018–0x1019

0x101A–0x101B

0x101C–0x101D

0x101E–0x101F

0x1020–0x1021

0x1040–0x1043

USB Serial EEPROM Mailbox 3

USB EP4 Description

USB EP4 NAK

USB EP5 Description

USB EP5 NAK

USB EP6 Description

USB EP6 NAK

USB EP7 Description

USB EP7 NAK

USB EP8 Description

USB EP8 NAK

USB EP8 Description

USB EP9 NAK

USB EP10 Description

USB EP10 NAK

USB EP11 Description

USB EP11 NAK

Defined by Analog Devices

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

Configures endpoint

Counter

USB EP STALL

USB EP1 Code Download Base Address

Policy

Starting address for code download on endpoint 1

REV. 0

–15–

ADSP-2192M

Table 12. USB MCU Register Definitions (continued)

Address

Name

Comments

0x1044–0x1047

0x1048–0x104B

0x1060–0x1063

USB EP2 Code Download Base Address

USB EP3 Code Download Base Address

USB EP1 Code Current Write Pointer Offset Current write pointer offset for code download on

Starting address for code download on endpoint 2

Starting address for code download on endpoint 3

endpoint 1

0x1064–0x1067

0x1068–0x106B

USB EP2 Code Current Write Pointer Offset Current write pointer offset for code download on

endpoint 2

USB EP3 Code Current Write Pointer Offset Current write pointer offset for code download on

endpoint 3

USB Register I/O Address

USB Register I/O Data

0x2000–0x2001

0x2002–0x2003

0x3000–0x3FFF

USB MCU Program Memory

USB Endpoint Description Register

USB Endpoint 2 Code Download Base Address Register

Thisregistercontainsan18-bit addresswhichcorresponds tothe

starting location for DSP code download on endpoint 2. This

register is read/write by the MCU only.

The endpoint description register provides the USB core with

information about the endpoint type, direction, and max packet

size. This register is read/write by the MCU only. This register is

defined for endpoints 4–11.

USB Endpoint 3 Code Download Base Address Register

Thisregistercontainsan18-bit addresswhichcorresponds tothe

starting location for DSP code download on endpoint 3. This

register is read/write by the MCU only.

• PS[9:0] MAX Packet Size for endpoint

• LT[1:0] Last transaction indicator bits: 00 = Clear,

01 = ACK, 10 = NAK, or 11 = ERR

• TY[1:0] Endpoint type bits: 00 = DISABLED, 01 = ISO,

10 = Bulk, or 11 = Interrupt

USB Endpoint 1 Code Current Write Pointer Offset

Register

• DR Endpoint direction bit: 1 = IN or 0 = OUT

Thisregistercontainsan18-bit addresswhichcorresponds tothe

currentwritepointeroffsetfromthebaseaddressregisterforDSP

code download on endpoint 1. The sum of this register and the

EP1 Code Download Base Address Register represents the last

DSP PM location written.

• TB Toggle bit for endpoint. Reflects the current state of

the DATA toggle bit.

USB Endpoint NAK Counter Register

This register records the number of sequential NAKs that have

occurred on a given endpoint. This register is defined for

endpoints 4–11. This register is read/write by the MCU only.

This register is read by the MCU only and is cleared to 3FFFF

(–1) when the Endpoint 1 Code Download Base Address

Register is updated.

• N[3:0] NAK counter. Number of sequential NAKs that

have occurred on a given endpoint. When N[3:0] is equal

to the base NAK counter NK[3:0], a zero-length packet

or packet less that maxpacketsize will be issued.

USB Endpoint 2 Code Current Write Pointer Offset

Register

This register contains an 18-bit address that corresponds to the

currentwritepointeroffsetfromthebaseaddressregisterforDSP

code download on endpoint 2. The sum of this register and the

EP2 Code Download Base Address Register represents the last

DSP PM location written.

• ST 1 = Endpoint is stalled

USB Endpoint Stall Policy Register

This register contains NAK count and endpoint FIFO error

policy bit. The STALL status bits for endpoints 1–3 are included

as well. This register is read/write by the MCU only.

This register is read by the MCU only and is cleared to 3FFFF

(–1) when the Endpoint 2 Code Download Base Address

Register is updated.

• ST[3:1] 1 = Endpoint is stalled. ST[1] maps to endpoint

1, ST[2] maps to endpoint 2, etc.

USB Endpoint 3 Code Current Write Pointer Offset

Register

• NK[3:0] Base NAK counter. Determines how many

sequential NAKs are issued before sending zero length

packet on any given endpoint.

Thisregistercontainsan18-bit addresswhichcorresponds tothe

currentwritepointeroffsetfromthebaseaddressregisterforDSP

code download on endpoint 3. The sum of this register and the

EP3 Code Download Base Address Register represents the last

DSP PM location written.

• FE FIFO error policy. 1 = When endpoint FIFO is over-

run/underrun, STALL endpoint

USB Endpoint 1 Code Download Base Address Register

Thisregistercontainsan 18-bit addresswhichcorrespondstothe

starting location for DSP code download on endpoint 1. This

register is read/write by the MCU only.

This register is read by the MCU only and is cleared to 3FFFF

(–1) when the Endpoint 3 Code Download Base Address

Register is updated.

–16–

REV. 0

ADSP-2192M

USB SETUP Token Command Register

USB Control Register

This register is defined as eight bytes long and contains the data

sent on the USB from the most recent SETUP transaction. This

register is read by the MCU only.

This register controls various USB functions. This register is

read/write by the MCU only.

• MO 1 = MCU has completed boot sequence and is ready

to respond to USB commands

USB SETUP Token Data Register

• DI 1 = Disconnect CONFIG device and enumerate again

using the downloaded MCU configuration

IfthemostrecentSETUPtransactioninvolvesadataOUTstage,

this register is defined as eight bytes long and contains the data

sent on the USB during the data stage. This is also where the

MCU will write data to be sent in response to a SETUP transac-

tion involving a data IN stage. This register is read/write by the

MCU only.

• BB 1 = After reset boot from MCU RAM; 0 = after reset

boot from MCU ROM

• INT = Active interrupt for the 8052 MCU

• ISE = Current interrupt is for a SETUP token

• IIN = Current interrupt is for an IN token

• IOU = Current interrupt is for an OUT token

USB SETUP Counter Register

This register provides information as the total size of the setup

transaction data stage. This register is read/write by the MCU

only.

• ER = Error in the current SETUP transaction. Generate

STALL condition on EP0.

• C[3:0] Total amount of data (bytes) to be sent/received

during the data stage of the SETUP transaction

USB Address/Endpoint Register

This register contains the USB address and active endpoint. This

register is read/write by the MCU only.

USB Register I/O Address Register

This register contains the address of the ADSP-2192M register

that is to be read/written. This register is read/write by the MCU

only.

• A[6:0] USB address assigned to device

• EP[3:0] USB last active endpoint

• A[15] Start ADSP-2192M read/write cycle

• A[14] 1 = WRITE, 0 = READ

USB Frame Number Register

This register contains the last USB frame number. This register

is read by the MCU only.

• A[13:0] ADSP-2192M address to read/write

• FN[10:0] USB frame number

USB Register I/O Data Register

This register contains the data of the ADSP-2192M register

which has been read or is to be written. This register is read/write

by the MCU only.

General USB Device Definitions

ThefollowingtablesdefinetheUSBdevicedescriptors:Table 13

describes the USB device descriptor; offset fields 8–13 are user-

definable via Serial EEPROM. Table 14 describes the USB

configuration descriptor; offset fields 7–8 are user-definable via

SerialEEPROM. Table 15, Table 16, and Table 17 describe the

USB string descriptor indexes.

• D[15:0] During READ this register contains the data

readfromtheADSP-2192M;duringWRITEthisregister

is the data to be written to the ADSP-2192M.

Table 13. CONFIG DEVICE Device Descriptor

Offset

Field

Description

Value

0

1

2–3

4

5

bLength

bDescriptorType

bcdUSB

Length = 18 bytes

Type = DEVICE

USB Spec 1.1

0x12

0x01

0x0110

bDeviceClass

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize

idVendor (L)

idProduct (L)

bcdDevice (L)

iManufacturer

iProduct

Device class vendor specific

Device sub-class vendor specific

Device protocol vendor specific

Max packet size for EP0 = eight bytes

Vendor ID (L) = 0456 ADI

Product ID (L) = ADSP-2192M

Device release number = 1.00

Manufacturer index string

0xFF

0x08

0x0456

0x2192

0x0100

0x01

6

7

8–9

10–11

12–13

14

15

16

17

Product index string

Serial number index string

Number of configurations = 1

0x02

0x00

0x01

iSerialNumber

bNumConfigurations

REV. 0

–17–

ADSP-2192M

Table 14. CONFIG DEVICE Configuration Descriptor

Offset

Field

Description

Value

0

1

2

3

4

5

6

7

8

bLength

Descriptor Length = nine bytes

Descriptor Type = Configuration

Total Length (L)

Total Length (H)

Number of Interfaces

0x09

0x02

0x12

0x00

0x01

0x00

0x80

0xFA

bDescriptorType

wTotalLength (L)

wTotalLength (H)

bNumInterfaces

bConfigurationValue

iConfiguration

bmAttributes

Configuration Value

Index of string descriptor (None)

Bus powered, no wake-up

Max power = 500 mA

MaxPower

Table 15. CONFIG DEVICE String Descriptor Index 0

Offset

Field

Description

Value

0

1

2

bLength

bDescriptorType

wLANGID[0]

Descriptor Length = 4 bytes

Descriptor Type = String

LangID = 0409 (US English)

0x04

0x03

0x0409

Table 16. CONFIG DEVICE Descriptor Index 1 (Manufacturer)

Offset

Field

Description

Value

0

1

2–19

bLength

bDescriptorType

bString

Descriptor Length = 20 bytes

Descriptor Type = String

ADI

0x14

0x03

Table 17. CONFIG DEVICE String Descriptor Index 2 (Product)

Offset

Field

Description

Value

0

1

2–31

bLength

bDescriptorType

bString

Descriptor Length = 34 bytes

Descriptor Type = String

Analog Devices USB Device

0x22

0x03

Configuration 0, 1, and 2 Device Definition

• FIXED ENDPOINTS

Note: The GENERIC endpoints are shared between all

interfaces.

• CONTROL ENDPOINT 0

• Type: Control

Endpoint 0 Definition

In addition to the normally defined USB standard device

requests, the following vendor specific device requests are

supported with the use of EP0. These requests are issued from

the host driver via normal SETUP transactions on the USB.

• Dir: Bidirectional

• Maxpacketsize: 8

• BULK OUT ENDPOINT 1, 2, 3 = Used for code

download to DSP

USB MCU Code Download

USB MCUCODE is a three-stage control transfer with an OUT

data stage. Stage 1 is the SETUP stage, stage 2 is the data stage

involving the OUT packet, and stage 3 is the status stage. The

lengthofthedatastageisdeterminedbythedriverandisspecified

by the total length of the MCU code to be downloaded. See

Table 18 for details about the USB MCUCODE (code

download) fields.

• Type: Bulk

• Dir: OUT

• Maxpacketsize: 64

• PROGRAMMABLE ENDPOINTS: 4 5 6 7 8 9 10 11

• Programmable in:

• Type: via USB Endpoint Description Register

• Direction: via USB Endpoint Description Register

• Maxpacket size: via USB Endpoint Description Register

USB REGIO (Write)

Address 15–15 = 1 indicates a write to the MCU register space;

Address 15–15 = 0 indicates a write to the DSP register space.

When accessing DSP register space, the MCU must write the

data to be written into the USB Register I/O Data register and

• Memory Allocation: via DSP Memory Buffer Base Addr,

DSP Memory Buffer Size, DSP Memory Buffer RD

Pointer Offset, DSP Memory Buffer Write Pointer Offset

Registers

–18–

REV. 0

ADSP-2192M

Table 18. USB MCUCODE (Code Download)

Table 20. USB REGIO (Register Read)

Offset Field

Size Value

Description

Offset Field Size Value Description

0

bmRequest

1

0x40

VendorRequest,

OUT

0

bmRequest

1

0xC0 Vendor Request,

IN

1

bRequest

1

0xA1

USB

1

2

3

4

5

6

bRequest

1

0xA0 USB REGIO

XXX Address 7–0

XXX Address 15–8

0x00

0x02 Length =

02 bytes

MCUCODE

Address 7–0

Address 15–8

wValue (L)

wValue (H)

wIndex (L)

wIndex (H)

wLength (L)

2

3

4

5

6

wValue (L)

wValue (H)

wIndex (L)

wIndex (H)

wLength (L)

1

XXX

0x00

0xXX¹Length = XX

bytes

7

wLength (H)

1

0x00

7

wLength (H)

1

0xYY²Length = YY

bytes

DSP Code Download

Because EP0 has a max packet size of only eight, downloading

DSP code on EP0 can be inefficient when operating on a UHCI

controller that allows only a fixed quantity of control transactions

per frame. Therefore, to gain better throughput for code down-

load, downloading of DSP code involves synchronizing a control

SETUP command on EP0 with BULK OUT commands on

endpoints 1, 2, or 3. EachendpointhasanassociatedDSPdown-

load address that is set by using USB REGIO (write) command.

¹XX is user-specified.

²YY is user-specified.

write the address to be written to the USB Register I/O Address

register. Bit 15 of the USB Register I/O Address register starts

the transaction and Bit 14 is set to one to indicate a WRITE.

USBREGIO(registerwrite)isathree-stagecontroltransferwith

an OUT data stage. Stage 1 is the SETUP stage, stage 2 is the

data stage involving the OUT packet, and stage 3 is the status

stage. See Table 19 for details about the USB REGIO (register

write) fields.

Because three possible interfaces are supported, each interface

has its own DSP download address and uses its own BULK pipe

to download code. The driver for each interface must set the

download address before beginning to use the BULK pipe to

downloadDSPcode. The downloadaddress will auto-increment

as each byte of data is sent on the BULK pipe to the DSP.

Table 19. USB REGIO (Register Write)

Offset Field

Size Value Description

DSP instructions are three bytes long, and USB BULK pipes

have even-number packet sizes. The instructions to be down-

loaded must be formatted into four-byte groups with the least

significant byte always zero. The USB interface strips off the least

significant byte and properly formats the DSP instruction before

writing it into the program memory. For example, to write the

three-byte opcode 0x400000 to DSP program memory, the

driver sends 0x40000000 down the BULK pipe.

0

bmRequest

1

0x40 Vendor Request,

OUT

0xA0 USB REGIO

XXX Address 7–0

XXX Address 15–8

0x00

0x02 Length =

02 bytes

1

2

3

4

5

6

bRequest

1

wValue (L)

wValue (H)

wIndex (L)

wIndex (H)

wLength (L)

The following example illustrates the proper order of commands

and synchronizing that the driver must follow.

7

wLength (H)

1

0x00

1. Device enumerates with two interfaces. Each interface

has the capability to download DSP code and can initiate

at any time.

USB REGIO (Read)

Address 15–15 = 1 indicates a read to the MCU register space;

Address 15–15 = 0 indicates a read to the DSP register space.

When accessing DSP register space, the MCU must write the

address to be read to the USB Register I/O Address register.

2. The driver for interface 1 begins code download by

sending the USB REGIO (write) command with the

starting download address. The driver must wait for this

command to finish before starting code download.

Bit 15 of the USB Register I/O Address register starts the trans-

action, and Bit 14 is set to zero to indicate a READ. The data

read will be placed into the USB Register I/O Data register.

3. The driver for interface 2 begins code download by

sending the USB REGIO (write) command with the

starting download address. The driver must wait for this

command to finish before starting code download.

USB REGIO (register read) is a three-stage control transfer with

an IN data stage. Stage 1 is the SETUP stage, stage 2 is the data

stage involving the IN packet, and stage 3 is the status stage. See

Table 20 for details about the USB REGIO (register read) fields.

4. Each driver now streams the code to be downloaded to

the DSP: driver 1 onto BULK EP1 for interface 1, and

driver 2 onto BULK EP2 for interface 2. The code is

written to the DSP in 3-byte instructions starting at the

REV. 0

–19–

ADSP-2192M

location specified by the USB REGIO (write) com-

mand. The driver must wait for each command to finish

before sending a new code download address.

7. ADSL driver downloads code to DSP for ADSL service.

DSP also initializes the USB Endpoint Description Reg-

ister, DSP Memory Buffer Base Addr Register, DSP

Memory Buffer Size Register, DSP Memory Buffer RD

Pointer Offset, and DSP Memory Buffer WR Pointer

Offset registers for each endpoint. Endpoints can only be

used when these registers have been written. ADSL ser-

vice is now available.

5. If there is more code to be downloaded at a different

starting address, the driver begins the entire sequence

again, using steps 1–4.

General Comments:

• DSP code download is only available after the ADSP-

2192M has re-enumerated using the MCU soft firmware.

The DSP code download command will not be available

in the MCU boot ROM for the default CONFIG device.

8. FAX driver downloads code to DSP for FAX service.

DSP also initializes the USB Endpoint Description Reg-

ister, DSP Memory Buffer Base Addr Register, DSP

Memory Buffer Size Register, DSP Memory Buffer RD

Pointer Offset, and DSP Memory Buffer WR Pointer

Offset registers for each endpoint. Endpoints can only be

used when the above registers have been written. FAX

service is now available.

• After setting the download addresses using the USB

REGIO (write) command, code download can be

initiated for any length using normal BULK traffic.

Example Initialization Process

After attachment to the USB bus, the ADSP-2192M identifies

itself as a CONFIG device with one endpoint, which refers to its

one control, EP0. This will cause a generic user-defined

CONFIG driver to load.

USB Data Pipe Operations

All data transactions involving the generic endpoints (4–11)

streamdataintoandoutoftheDSPmemoryviaadedicatedUSB

hardware block. This hardware block manages all USB transac-

tions for these endpoints and serves as a conduit for the data

moving to and from the DSP memory FIFOs. There is no MCU

involvement in the management of these data pipes.

TheCONFIGdriverdownloadsappropriateMCUcodetosetup

the MCU, which includes the specific device descriptors, inter-

faces, and endpoints.

The external Serial EEPROM is read by the DSP and transferred

to the MCU. The CONFIG driver through the control EP0 pipe

generates a register read to determine the configuration value.

Based on this configuration code, the host downloads the proper

USB configurations to the MCU.

Table 21. Typical Configuration for ADSL Modem

End

Max

Point

Type

Packet

Comment

1

4

5

6

BULK OUT 64

BULK IN 64

BULK OUT 64

INT IN 16

DSP CODE

ADSL RCV

ADSL XMT

STATUS

Finally, the driver writes the USB Control Register, causing the

device to disconnect and then reconnect so the new downloaded

configuration is enumerated by the system. Upon enumeration,

each interface loads the appropriate device driver.

Table 22. Typical Configuration for FAX Modem

An example of this procedure is configuring the ADSP-2192M

to be an ADSL modem and a FAX modem.

End

Max

Point

Type

Packet

Comment

1. ADSP-2192M device is attached to USB bus. System

enumerates the CONFIG device in the ADSP-2192M

first. A user-defined driver is loaded.

2

7

8

9

BULK OUT 64

BULK IN 64

BULK OUT 64

INT IN 16

DSP CODE

FAX RCV

FAX XMT

STATUS

2. The user-defined driver reads the device descriptor,

which identifies the card as an ADSL/FAX modem.

3. The user-defined driver downloads USB configuration

and MCU code to the MCU for interface 1, which is the

ADSL modem.

The USB data FIFOs for these generic endpoints exist in DSP

memory space. The following memory buffer registers exist for

each endpoint:

4. Configuration specifies which endpoints are used (and

their definitions). A typical configuration for ADSL

appears in Table 21.

• Base Address (18 bits)

• Size (16 bits) – Offset from the Base Address

• Read Offset (16 bits) – Offset from the Base Address

• Write Offset (16 bits) – Offset from the Base Address

5. The user-defined driver downloads USB configuration

for interface 2, which is the FAX modem. Configuration

specifies which endpoints are used and their definitions.

A typical configuration for FAX appears in Table 22.

As part of initialization, the DSP code sets up these FIFOs before

USB data transactions for these endpoints can begin. When

setting up these USB FIFOs, Base+Size/Read Offset/Write

Offset cannot be greater than 18 bits. DSP memory addresses

cannot exceed 18 bits (0x000000–0x03FFFF).

6. The user-defined driver now writes the USB Config

Register, which causes the device to disconnect and

reconnect. The system enumerates all interfaces and

loads the appropriate drivers.

–20–

REV. 0

ADSP-2192M

IN Transactions (Device to Host)

The DSP memory interface on the ADSP-2192M only allows

reads/writes of 16-bit words. It cannot handle byte transactions.

Therefore, a 64-byte maxpacketsize means 32 DSP words. A

single byte cannot be transferred to/from the DSP. Endpoint 0

does not have this limitation. Because these FIFOs exist in DSP

memory, the DSP shares some pointer management tasks with

the USB core. For OUT transactions, the write pointer is con-

trolled by the USB core, while the read pointer is governed by

the DSP. The opposite is true for IN transactions.

When an IN transaction arrives for a particular endpoint, the

USB core once again computes how much read data is available

in the FIFO. It also determines if the amount of read data is

greater than or equal to the maxpacketsize. If both conditions are

met, the USB core will transfer the data. Upon receiving ACK

from the host, the USB core updates the Memory Buffer Read

Offset register.

If the amount of read data is less than the maxpacketsize (a short

packet), theUSBcoredetermines whethertosend the data based

upon a NAK count limit. This is a 4-bit field in the Endpoint

Stall Policy register that can be programmed with a value indi-

cating how many NAKs should be sent prior to transmitting a

short packet. This allows flexibility in determining how IRPs are

retired via short packets.

Both the write and read pointers for each memory buffer would

begin at zero. All USB buffers operate in a circular fashion. Once

a pointer reaches the end of the buffer, it will need to be set back

to zero.

OUT Transactions (Host to Device)

When an OUT transaction arrives for a particular endpoint, the

USB core calculates the difference between the write and read

pointerstodeterminetheamountofroomavailableintheFIFOs.

If all of the OUT data arrives and the write pointer never catches

up to the read pointer, that data is Backed and the USB core

updates the Memory Buffer Write Offset register.

Because the DSP controls the write pointer, it must determine if

there is sufficient room in the FIFO for placing new data. Once

it has completed writes to the FIFO, it needs to update the

Memory Buffer Write Offset register.

Sub-ISA Interface

In systems that combine the ADSP-2192M chip with other

devices on a single PCI interface, the ADSP-2192M Sub-ISA

mode is used to provide a simpler interface (to a PCI function

ASIC), which bypasses the ADSP-2192M’s PCI interface.

If at any time during the transaction the two pointers collide, the

USB block responds with a NAK indicating that the host must

resend the same data packet; in that case, the write pointer

remains unchanged.

In this mode, the Combo Master assumes all responsibility for

interfacing the function to the PCI bus, including provision of

Configuration Space registers for the ADSP-2192M system as a

separate PnP function. In Sub-ISA Mode the PCI Pins are recon-

figured for ISA operation as shown in Table 23.

If for some reason the host sends more data than the maxpack-

etsize, the USB core accepts it, as long as there is sufficient room

in the FIFO.

Because the DSP controls the read pointer, it must perform a

similar calculation to determine if there is sufficient data in the

FIFO to begin processing. Once The DSP has consumed some

amount of data, it will need to update the Memory Buffer Read

Offset register.

Table 23. Sub-ISA (PCI) Pin Descriptions

Pin Name

PCI Direction¹ISA Alias

ISA Direction

ISA Description

AD[15:0]

AD[18:16] In/Out

AD[31:22] In/Out

In/Out

ISAD[15:0]

ISAA[3:1]

Unused

RST

In/Out

In

Data

Register Address

Tie to GND in Sub-ISA Mode

Reset

RST

In

CBE0

CBE1

CBE2

INTA

AD21

AD20

AD19

PME

CLK

In/Out

Out (o/d)

In/Out

Out (o/d)

In

IOW

IOR

AEN

IRQ

PDW1

PDW0

PME_EN

PMERQ

Unused

IOCHRDY

In

Out

In

Write Strobe

Read Strobe

Chip Select (Access Enable)

(CMOS) Interrupt (Active High)

PCI D-state MSB (inverted) Power-Down

PCI D-state LSB (inverted) Power-Down

PME Enable

Power Management Event

Tie to GND in Sub-ISA Mode

I/O Ready

In

Out (o/d)

In

Out

CLKRUN In/Out

CLKRUN Out

Acknowledge

¹o/d = Open Drain

REV. 0

–21–

ADSP-2192M

In Sub-ISA mode, the ADSP-2192M’s PCI protocol is replaced

withanISA-like,asynchronousprotocolcontrolledbythestrobes

IOR, IOW, and AEN. Access is possible only to the PCI Base

Address 4 (BAR4) Registers (the InDirect Access Registers).

The Sub-ISA Address Map is shown in Table 24.

Assertion of PDW1 low signals a power-down interrupt to the

DSP. Deassertion of PDW1 high causes a wake-up of the DSP.

The PME_EN output from the Combo Master should reflect the

current PCI function PME_EN bit and should be connected to

the ADSP-2192M AD20 pin. The PMI_EN bit should be set to

enable interrupt and wake-up of the DSP upon any change of the

PME_EN state. If PME_EN is turned off, the DSPs can wake

upifnecessaryandthenpowerthemselvesandtheADSP-2192M

completely down (clocks stopped).

An active low RST input (to be derived from PCI RST and

possible other sources) and an active-high IRQ interrupt output

are available. Power Management is handled by the ADSP-

2192M inputs PDW1–0/PME_EN and the ADSP-2192M

output PMERQ. PDW1–0 should be the inversion of the PCI

power state in the function’s PMCSR register. PDW1 is con-

nected to AD21, and PDW0 is connected to AD20.

Table 24. Sub-ISA Indirect Access Registers

ISAA[3:1]

Name

Reset

Comments

0x0

0x1

Control Register Address

Reserved

0x0000

Address and direction control for register accesses

0x2

0x3

Control Register Data

Reserved

0x0000

Data for register accesses

0x5–0x4

DSP Memory Address

0x000000

Address and direction control for DSP memory

accesses

Data for DSP memory accesses.

0x7–0x6

DSP Memory Data

PCI Interface to DSP Memory

Data FIFO Architecture

The PCI interface can directly access the DSP memory space

using DMA transfers. The transactions can be either slave trans-

fers, in which the host initiates the transaction, or master

transfers, in which the ADSP-2192M initiates the PCI transac-

tion. Theregisters thatcontrolPCI DMA transfers are accessible

from both the DSP (on the Peripheral Device Control Bus) and

the PCI Bus.

Each DSP core within the ADSP-2192M contains four FIFOs

which provide a data communication path to the rest of the chip.

Two of the FIFOs are input FIFOs, receiving data into the DSP.

The other two FIFOs are transmit FIFOs, sending data from the

DSPtothecodec, AC’97 interface, ortheother DSP. EachFIFO

is eight words deep and sixteen bits wide. Interrupts to the DSP

can be generated when some words have been received in the

input FIFOs, or when some words are empty in the

Transmit FIFOs.

The PCI/Sub-ISA Bus uses the Peripheral Device Control

Register Space which is distributed throughout the ADSP-

2192M and connected through the Peripheral Device Control

Bus. The PCI bus can access these registers directly.

The interface to the FIFOs on the DSP is simply a register

interface to the Peripheral Interface bus. TX0, RX0, TX1, and

RX1 are the primary FIFO registers in the DSP’s universal

register map. The FIFOs can be used to generate interrupts to

the DSP, based upon FIFO transactions, or they can initiate

DMA requests.

USB Interface to DSP Memory

The USB interface can directly access the DSP memory space

using DMA transfers to memory locations specified by the USB

endpoints. The registers that control USB endpoint DMA

transfers are accessible from both the DSP (on the Peripheral

Device Control Bus) and the USB Bus.

When communicating with the AC’97 interface, the Connection

Enable bitsin thecontrolregisteraresetto10. Bit 3 selectsstereo

or mono transfers to and from the AC’97 interface. Bits 7–4

select the AC’97 slot associated with this FIFO.

The Peripheral Device Control Register Space is distributed

throughout the ADSP-2192M and connected through the

Peripheral Device Control Bus. The USB Bus can access these

registers directly.

When stereo is selected, the slot identified and the next slot are

both associated with the FIFO. Typically, stereo is selected for

left and rightdata, andbothleftand right must be associatedwith

thesameexternalAC’97codecandhavetheirsamplerateslocked

together. In thiscase, leftandrightdatawillalternatein theFIFO

with the left data coming first.

AC’97 Codec Interface to DSP Memory

Transfers from AC’97 data to DSP memory are accomplished

usingDMAtransferthroughtheDSPFIFOs. Each DSP hasfour

FIFOs available for data transfers to/from the AC’97 Codec

Interface. The registers that control FIFO DMA transfers are

only accessible from within the DSP and are defined as part of

the core register space.

IftheFIFOisenabledfortheAC’97interface, andavalidrequest

for data comes along that the FIFO cannot fulfill, the transmitter

underflow bit is set, indicating that an invalid value was sent over

the selected slot. Similarly, on the receive side, if the FIFO is full

and another valid word is received, the Overflow bit is sent to

indicate the loss of data.

–22–

REV. 0

ADSP-2192M

FIFO Control Registers

• RFF(Bit 13):ReceiveFIFOFull–ReadOnly.(0 = FIFO

The Transmit FIFO Control Register has the following bit field

definitions:

Not Full or 1 = FIFO Full)

• RFE (Bit 14): Receive FIFO Empty – Read Only.

(0 = FIFO Not Empty or 1 = FIFO Empty)

• CE (Bits 1–0): Connection Enable (00 = Disable,

01 = Reserved, 10 = Connect to AC’97, and

11 = Reserved)

• RO (Bit 15): Receive Overflow – Sticky, Write 1 Clear.

(0 = FIFO Overflow has not occurred or 1 = FIFO

Overflow has occurred)

• DPSel (Bit 2): Reserved (0)

• SMSel (Bit 3): Stereo/Mono Select - AC’97 Mode Only

(0 = Mono Stream or 1 = Stereo Stream)

Table 26. AC’97 Slot Select Values

Slot

Mono

Stereo

• SLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode Only

• FIP (Bits 10–8): FIFO interrupt position. An interrupt is

generated when FIP[2:0] words remain in the FIFO. The

interrupt is level-sensitive.

0000–0010

0011

0100

Reserved

Slot 3

Slot 4

Reserved

Slots 3/4

Slots 4/5

0101

0110

0111

1000

1001

1010

1011

1100

Slot 5

Slot 6

Slot 7

Slot 8

Slots 5/6

Slots 6/7

Slots 7/8

Slots 8/9

Slots 9/10

Slots 10/11

Slots 11/12

Not Allowed

Reserved

• DME (Bit 11): DMA Enable. (0 = DMA Disabled or

1 = DMA Enabled)

• TFF (Bit 13): Transmit FIFO Full - Read Only.

(0 = FIFO Not Full or 1 = FIFO Full)

Slot 9

• TFE (Bit 4): Transmit FIFO Empty - Read Only.

(0 = FIFO Not Empty or 1 = FIFO Empty)

Slot 10

Slot 11

Slot 12

Reserved

• TU(Bit 15):TransmitUnderflow–Sticky, Write1Clear.

(0 = FIFO Underflow has not occurred or 1 = FIFO

Underflow has occurred)

1101–1111

System Reset Description

There are several sources of reset to the ADSP-2192M.

Table 25. AC’97 Slot Select Values

Slot

Mono

Stereo

• Power-On Reset

0000–0010

0011

0100

Reserved

Slot 3

Slot 4

Reserved

Slots 3/4

Slots 4/5

• PCI Reset

• USB Reset

• Soft Reset (RST in CMSR Register)

0101

Slot 5

Slots 5/6

0110

0111

Slot 6

Slot 7

Slots 6/7

Slots 7/8

Power-On Reset

The DSP has an internal power-on reset circuit that resets the

DSP when power is applied. The DSP also has a Power-On Reset

PORST signal that can initiate this master reset. Note that

PORST is not needed when using PCI or USB (and is shown as

a no connect in Figure 7); these interfaces reset the DSP under

their control as needed.

1000

1001

1010

1011

1100

1101–1111

Slot 8

Slot 9

Slot 10

Slot 11

Slot 12

Reserved

Slots 8/9

Slots 9/10

Slots 10/11

Slots 11/12

Not Allowed

Reserved

DSP Software Reset

The DSP can generate a software reset using the RSTD bit in

DSP Interrupt/Power-down Registers). Generally, reset condi-

tions are handled by forcing the DSPs to execute ROM- or

RAM-based Reset Handler code. The Reset Handler that is

executed can be dictated by the Reset Source as defined by the

CRST[1:0] bits in the Chip Mode/Status Register (CMSR). The

exact Reset Functionality is therefore defined by the ROM and

RAM Reset Handler Code and as such is programmable.

The Receive FIFO Control Register has the following bit field

definitions:

• CE (Bits 1–0): Connection Enable. (00 = Disable,

01 = Reserved, 10 = Connect to AC’97, 11 = Reserved)

• DPSel (Bit 2): Reserved (0)

• SMSel (Bit 3): Stereo/Mono Select - AC’97 Mode Only.

(0 = Mono Stream or 1 = Stereo Stream)

• SLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode Only.

Booting Modes

The ADSP-2192M has two mechanisms for automatically

loading internal program memory after reset. The CRST pins,

sampled during power-on reset, implement these modes:

• FIP (Bit 10–8): FIFO interrupt position. An interrupt is

generated when FIP[2:0] + 1 words have been received

in the FIFO. The interrupt is level-sensitive.

• Boot from PCI Host

• Boot from USB Host

• DME (Bit 11): DMA Enable. (0 = DMA Disabled or

1 = DMA Enabled)

REV. 0

–23–

ADSP-2192M

Optionally, extra boot information can come from an SPI or

Microwire serial EPROM during PCI or USB booting. The boot

process flow appears in Figure 5.

DSP EMERGES FROM RESET AND PROGRAM FLOW JUMPS TO BOOT ROM

LOADER KERNEL READS CRST PINS AND DETERMINES MODE OF BOOTING.

ALSO PERFORMS HOUSEKEEPING OPERATIONS, SETTING UP INTERRUPTS, ETC.

CALL SUBROUTINE TO AUTO-DETECT SERIAL EEPROM

LOADER KERNEL READS BUS MODE PINS TO SET UP BUS CONFIGURATION

SERIAL

EEPROM

EXISTS?

NO

YES

DETERMINE 8- OR 16-BIT SPI OR MICROWIRE

LOAD SERIAL EEPROM CONFIGURATION AND DATA PACKETS.

LOAD PCI/USB CONFIGURATION REGISTERS ACCORDINGLY

NO

TRANSFER CONTROL TO PCI

OR USB, TO FACILITATE

REST OF BOOT

DOES ANY SERIAL

EEPROM NEED TO

BE EXECUTED?

YES

AFTER BOOTING IS COMPLETE,

USER HAS OPTION TO RETURN

TO SERIAL EEPROM OR JUMP TO

USER CODE AND BEGIN EXECUTION

EXECUTE PACKETS

FINISH

Figure 5. Boot Process Flow

Power Management Description

2.5 V Regulator Options

The ADSP-2192M supports several states with distinct power

management and functionality capabilities. These states encom-

pass both hardware and software states.

In 5 V and 3.3 V PCI applications the ADSP-2192M 2.5 V

IVDD supply will be generated by an on-chip regulator. The

internal 2.5 V supply (IVDD) can be generated by the on-chip

regulator combined with an external power transistor as shown

in Figure 6. To support the PCI specification’s power-down

modes, the two transistors control the primary and auxiliary

supply. If the reference voltage on RVDD (typically the same as

PCIVDD) drops out, the VCTRLAUX will switch on the device

connected to PCIVAUX and VCTRLVDD will switch off the

primary supply. USB applications may require an external high

efficiency switching regulator to generate the 2.5 V supply for the

ADSP-2192M.

The driver and DSP code take responsibility for detailed power

management of the modem, so minimum power levels are

achieved regardless of OS or BIOS. In response to events, the

driver and DSPs manage power by changing platform states as

necessary.

Power Regulators

The ADSP-2192M is intended to operate in a variety of different

systems. These include PCI, CardBus, USB, and embedded

(Sub-ISA) applications. The PCI and USB specifications define

power consumption limits that constrain the design of the DSP.

–24–

REV. 0

ADSP-2192M

Figure 7. Capacitor values are dependent on crystal type and

should be specified by the crystal manufacturer. A parallel-

resonant, fundamental frequency, microprocessor-grade

24.576 MHz crystal should be used for this configuration.

TANTALUM

OR

ELECTROLYTIC

CERAMIC

DSP

INTERNAL

CIRCUIT

PCIVDD

3.0V – 5.5V

2.5V @ 500mA

IVDD

24.576MHz

10µF

0.1µF

ZETEX

FZT951

XTALI

XTALO

VCTRLVDD

EXTERNAL

COMPONENTS

ADSP-2192M

3V OR 5V

CLOCK

CLKSEL

BUS1

–

PCIVAUX

3.0V – 3.6V

BUS SELECT

+

BUS0

VREF

ZE TEX

FZT951

PORST

POWR ON

RESET

V CTR LAUX

CLKRUN

CLK

PCI CLOCK RUN

PCI CLOCK

Figure 6. 2.5 V Regulator Options

Low Power Operation

RST

PCI RESET

In addition to supporting the PCI and USB standards’ power-

down modes, additional power-down modes for the DSP cores

and peripheral buses are supported by the ADSP-2192M. The

power-down modes are controlled by the DSP1 and DSP2 Inter-

rupt/Power-down registers.

AC'97 BIT

CLOCK

BITCLK

Figure 7. External Crystal Connections

Clock Signals

The ADSP-2192M can be clocked by a crystal oscillator. If a

crystal oscillator is used, the crystal should be connected across

the XTALI/O pins, with two capacitors connected as shown in

12.0MHz

USB PORT

USB

1/8.192 PLL AND

CLOCK

DOMAIN

CLOCK RECOVERY

33MHz

PCI CLK

X4

PLL

PCI

CLOCK

DOMAIN

49.152MHz

(SUB-ISA MODE)

24.576MHz

1/2

XTALI

147.456MHz

X6

DSP

CLOCK DOMAIN

PLL

49.152MHz

(PROGRAMMABLE)

1/2

PERIPHERAL DEVICE

CONTROL BUS

CLOCK DOMAIN

12.288 MHz

1/2

AC’97

CLOCK DOMAIN

BITCLK

Figure 8. Clock Domains

REV. 0

–25–

ADSP-2192M

Instruction Set Description

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

The ADSP-2192M assembly language instruction set has an

algebraic syntax that was designed for ease of coding and read-

ability. The assembly language, which takes full advantage of the

processor’s unique architecture, offers the following benefits:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• ADSP-219xassemblylanguagesyntaxisasupersetofand

source code compatible (except for two data registers and

DAG base address registers) with ADSP-218x family

syntax. Existing 218x programs may need to be restruc-

tured, however, to accommodate the ADSP-2192M’s

unified memory space and to conform to its interrupt

vector map.

• Set conditional breakpoints on registers, memory, and

stacks

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the ADSP-219x

development tools, including the syntax highlighting in the

VisualDSP++ editor. This capability permits:

• Every instruction, except two, assembles into a single,

24-bit word that can execute in a single instruction cycle.

The exceptions are two dual-word instructions, one of

which writes 16- or 24-bit immediate data to memory,

and the other of which jumps/calls to other pages

in memory.

• Control how the development tools process inputs and

generate outputs.

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test

access port of the ADSP-2192M processor to monitor and

control the target board processor during emulation. The

emulator provides full-speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Nonin-

trusivein-circuitemulationisassuredbytheuseoftheprocessor’s

JTAG interface—the emulator does not affect target system

loading or timing.

• Supportsawidervarietyofconditionalandunconditional

jumps and calls, and a larger set of conditions on which

to base execution of conditional instructions.

Development Tools

The ADSP-2192M is supported with a complete set of software

and hardware development tools, including Analog Devices

emulators and VisualDSP++^®development environment. The

same emulator hardware that supports other ADSP-219x DSPs,

also fully emulates the ADSP-2192M.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the ADSP-219x processor family. Hardware

toolsincludeADSP-219xPCplug-incards. Thirdpartysoftware

tools include DSP libraries, real-time operating systems, and

block diagram design tools.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler that is based on an algebraic

syntax; an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. Two key points for these tools are:

Designing an Emulator-Compatible DSP Board

(Target)

The White Mountain DSP (Product Line of Analog Devices,

Inc.) family of emulators are tools that every DSP developer

needs to test and debug hardware and software systems. Analog

Devices has supplied an IEEE 1149.1 JTAG Test Access Port

(TAP) on each JTAG DSP. The emulator uses the TAP to access

the internal features of the DSP, allowing the developer to load

code, set breakpoints, observe variables, observe memory, and

examine registers. The DSP must be halted to send data and

commands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

• Compiled ADSP-219x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-219x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

• ADSP-218x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-218x applications to the ADSP-219x.

To use these emulators, the target’s design must include the

interface between an Analog Devices JTAG DSP and the

emulation header on a custom DSP target board.

VisualDSP++ is a registered trademark of Analog Devices, Inc.

–26–

REV. 0

ADSP-2192M

Target Board Header

The emulator interface to an Analog Devices JTAG DSP is a

14-pin header, as shown in Figure 9. The customer must supply

this header on the target board in order to communicate with the

emulator. The interface consists of a standard dual row 0.025"

1

3

5

2

EMU

GND

TMS

GND

4

6

KEY (NO PIN)

BTMS

square post header, set on 0.1"

ꢀ 0.1" spacing, with a minimum

post length of 0.235". Pin 3 is the key position used to prevent

the pod from being inserted backwards. This pin must be clipped

on the target board.

7

9

8

BTCK

TCK

10

12

BTRST

TRST

1

3

5

2

4

6

11

EMU

GND

BTDI

GND

TDI

13

14

KEY (NO PIN)

GND

TMS

TDO

TOP VIEW

BTMS

7

9

8

Figure 10. JTAG Target Board Connector

with No Local Boundary Scan

BTCK

TCK

10

12

BTRST

TRST

11

BTDI

GND

TDI

13

14

TDO

TOP VIEW

0.64"

Figure 9. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in Place)

Also, the clearance (length, width, and height)around the header

must be considered. Leave a clearance of at least 0.15" and 0.10"

around the length and width of the header, and reserve a height

clearance to attach and detach the pod connector.

0.88"

0.24"

As can be seen in Figure 9, there are two sets of signals on the

header. There are the standard JTAG signals TMS, TCK, TDI,

TDO, TRST, and EMU used for emulation purposes (via an

emulator). There are also secondary JTAG signals BTMS,

BTCK, BTDI, and BTRST that are optionally used for board-

level (boundary scan) testing.

Figure 11. JTAG Pod Connector Dimensions

0.10"

Whentheemulatorisnotconnectedtothisheader,placejumpers

across BTMS, BTCK, BTRST, and BTDI as shown in

Figure 10. This holds the JTAG signals in the correct state to

allow the DSP to run free. Remove all the jumpers when con-

necting the emulator to the JTAG header.

0.15"

Figure 12. JTAG Pod Connector Keep-Out Area

JTAG Emulator Pod Connector

Design-for-Emulation Circuit Information

Figure 11 details the dimensions of the JTAG pod connector at

the 14-pin target end. Figure 12 displays the keep-out area for a

target board header. The keep-out area allows the pod connector

to properly seat onto the target board header. This board area

should contain no components (such as chips, resistors, capaci-

tors). The dimensions are referenced to the center of the 0.25"

square post pin.

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal buff-

ering, signal termination, and emulator pod logic, see the EE-68:

Analog Devices JTAG Emulation Technical Reference on the Analog

Devices website (www.analog.com)—use site search on

“EE-68.” This document is updated regularly to keep pace with

improvements to emulator support.

REV. 0

–27–

ADSP-2192M

Additional Information

Table 27. Pin Configurations:

PCI/USB Bus Interface (continued)

This data sheet provides a general overview of the ADSP-2192M

architecture and functionality. For detailed information on the

ADSP-219x Family core architecture and instruction set, refer

Pin Name

LQFP

I/O

Description

to the ADSP-219x/2191 DSP Hardware Reference

.

CBE2

16

I/O

PCI Cmd/Byte

Enable

PCI Cmd/Byte

Enable

PCI Clock

Clock Run

PCI Target Select

PCI Frame Select

Grant

PCI Initiator Select

PCI/ISA Interrupt

PCI Initiator Ready

PCI Bus Parity

PCI Ground

PIN DESCRIPTIONS

CBE3

4

I/O

ADSP-2192M pin definitions are listed in a series of tables

following this section. Inputs identified as synchronous (S) must

meet timing requirements with respect to CLKIN (or with

respect to TCK for TMS, TDI). Inputs identified as asynchro-

nous (A) can be asserted asynchronously to CLKIN (or to TCK

for TRST).

CLK

130

26

24

17

131

5

128

22

31

1, 10,

21, 30,

39, 52,

133

9, 18,

29, 38,

51,

132,

144

27

I

O

I/O

I

O

I/O

I

CLKRUN

DEVSEL

FRAME

GNT

IDSEL

INTAB

IRDY

The following symbols appear in the Type columns of these

tables: G = Ground, I = Input, O = Output, P = Power Supply,

and T = Three-State.

PAR

PCIGND

Table 27. Pin Configurations:

PCI/USB Bus Interface

Pin Name

LQFP

I/O

Description

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

57

56

55

54

53

48

47

46

44

43

42

37

36

35

34

33

15

14

13

12

11

8

7

6

3

2

143

142

141

138

137

136

I/O

Addr/Data Bus

PCIVDD

I

PCI VDD supply

PERR

PME

I/O

O

PCI Parity Error/

USB– (Inverting

Input)

PCI Power

Management Event

Request

AD8

AD9

135

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AD27

AD28

AD29

AD30

AD31

REQ

RST

SERR

134

129

28

O

I

O

PCI Reset

PCI System Error/

USB+ (Noninverting

Input)

PCI Target Stop

PCI Target Ready

STOP

TRDY

25

23

I/O

Table 28. Pin Configurations: Analog Pins

Pin Name

LQFP

I/O

Description

AGND

AQGND

CTRLAUX 61

CTRLVDD 63

IVDD

NC

RVAUX

RVDD

67

68

I

O

I

Analog Gnd.

Ref. Analog Gnd.

X Supply

Control VDD

Digital VDD

No Connect

X Supply

62

66

69

70

60

64

I

Analog VDD Supply

CBE0

45

I/O

PCI Cmd/Byte

Enable

CBE1

32

I/O

PCI Cmd/Byte

Enable

–28–

REV. 0

ADSP-2192M

Table 29. Pin Configurations: Emulator Pins

Table 33. Pin Configurations: IO Pins

Pin Name

LQFP

I/O

Description

Pin Name

LQFP

I/O

Description

EMU

TCK

74

78

O

I

Emulator Event Pin

Emulator Clock

Input

Emulator Data Input

Emulator Data

Output

Emulator Mode

Select

Emulator Logic Reset

AIOGND

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

76, 91

82

83

84

86

87

88

89

90

IO Ground

IO Pin, Bit 0

IO Pin, Bit 1

IO Pin, Bit 2

IO Pin, Bit 3

IO Pin, Bit 4

IO Pin, Bit 5

IO Pin, Bit 6

IO Pin, Bit 7

IO VDD

I/O

TDI

TDO

80

81

I

O

TMS

75

79

I

TRST

IOVDD

77, 85

Table 30. Pin Configurations: Crystal/Configuration

Pins

Table 34. Pin Configurations: Power Supply Pins

Pin Name

LQFP

I/O

Description

Pin Name

LQFP

I/O

Description

BUS0

124

I

PCI/Sub-ISA/

CardBus Select Pins

PCI/ Sub-ISA/

CardBus Select Pins

Clock Select

IGND

No Connect

Power-On Reset

Crystal Input Pin

(24.576 MHz)

Crystal Output Pin

ACVAUX

AIOGND

AVDD

CTRLAUX 61

CTRLVDD 63

92

91

65

AC’97 VAUX Input

IO Ground

Analog VDD Supply

AUX Control

Control VDD

Digital Ground

BUS1

123

I

CLKSEL

IGND

NC

PORST

XTALI

116

122

127

121

118

I/O

I

O

I

IGND

20, 41,

50, 59,

104,

120,

122,

126,

139

I

XTALO

119

I/O

Table 31. Pin Configurations: AC’97 Interface Pins

IVDD

19, 40,

49, 58,

62,

Digital VDD

Pin Name

LQFP

I/O

Description

ACRST

ACVAUX

ACVDD

BITCLK

SDI0

102

92

93

96

99

O

I

AC’97 Reset

103,

117,

125,

140

60

64

AC’97 VAUX Input

AC’97 VDD Input

AC’97 Bit Clock

AC’97 Serial Data

Input, Bit 0

RVAUX

RVDD

AUX Supply

Analog VDD Supply

SDI1

SDI2

SDO

98

I

AC’97 Serial Data

Input, Bit 1

AC’97 Serial Data

Input, Bit 2

AC’97 Serial Data

Output

AC’97 Sync

97

I

100

101

O

SYNC

Table 32. Pin Configurations: Serial EEPROM Pins

Pin Name

LQFP

I/O

Description

SCK

72

I

Serial EEPROM

Clock

SDA

SEN

71

73

I

Serial EEPROM Data

Serial EEPROM

Enable

REV. 0

–29–

ADSP-2192M

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade Parameter

Test Conditions

Min

Max

Unit

1

V_DDINT

V_DDEXT

Internal Supply Voltage

External Supply Voltage Option 3.3 V

(All Supplies)

External Supply Voltage Option 5.0 V

(V_DDEXTSupplies only)

2.38

3.0

2.62

3.6

V

2

3

V_DDEXT

4.75

5.25

V

V_IH1

V_IH2

V_IL1

V_IL2

T_AMB

High Level Input Voltage⁴

High Level Input Voltage⁵

Low Level Input Voltage²

Low Level Input Voltage⁶

Ambient Operating Temperature

@ V_DDEXT= Max 2.0

V_DDEXT

0.8

0.4

70

V

@ V_DDEXT= Max 0.65 ꢀ V_DDEXT

@ V_DDEXT= Min –0.3

@ V_DDINT= Min –0.3

0

°C

Specifications subject to change without notice.

¹V_DDINT= IVDD.

²V_DDEXT= IOVDD, PCIVDD, ACVDD, RVDD, RVAUX, ACVAUX.

³V_DDEXT= IOVDD, PCIVDD, ACVDD, RVDD only.

⁴Applies to PCI input and bidirectional pins.

⁵Applies to I/O bus bidirectional pins.

⁶Applies to input pins XTALI, BUS0, BUS1.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min Typ

Max Unit

V_OH

V_OL

I_IH

High Level Output Voltage¹

Low Level Output Voltage¹

High Level Input Current^{2, 3}

Low Level Input Current²

Low Level Input Current³

@ V_DDEXT= min, I_OH= –0.5 mA 2.4

@ V_DDEXT= max, I_OL= 2.0 mA

@ V_DDEXT= max, V_IN= V_DDmax

@ V_DDEXT= max, V_IN= 0 V

V

0.4

10

250

10

µA

mA

I_IL

I_ILP

I_OZH

I_OZL

I_DD

@ V_DDEXT= max, V_IN= 0 V

Three-State Leakage Current^{4, 5}@ V_DDEXT= max, V_IN= V_DDmax

Three-State Leakage Current⁴

Supply Current Dynamic

(Internal)⁶

@ V_DDEXT= max, V_IN= 0 V

@ 160 MHz V_DDINT= 2.5 V

340

45

I_DD-IDLE

C_IN

Supply Current (Idle)

V_DDINT= 2.5 V

f_IN=1 MHz, T_AMB= 25°C,

V_DDINT= 2.5 V

mA

pF

Input Capacitance^{7, 8}

20

I_DD–Power-Down Supply Current (Power-Down)

T_AMB= 25°C, V_DDINT= 2.5 V

0.8

mA

Specifications subject to change without notice.

¹Applies to output and bidirectional pins.

²Applies to input.

³Applies to input pins with internal pull-ups: EMS, EDI, ERSTB, SDA, SEN, SCR, BUS0, BUS1.

⁴Applies to three-statable pins.

⁵Applies to three-statable pins with internal pull-ups.

⁶DSP typical operating condition for supply current specification. DSP MACs, ALUs, and shifts 50%; data read/write/moves 30%, idle 20%.

⁷Applies to all signal pins.

⁸Guaranteed, but not tested.

–30–

REV. 0

ADSP-2192M

ABSOLUTE MAXIMUM RATINGS

Power Supply, Internal (V_DDINT)¹. . . . . . . . –0.3 V to +6.0 V

Power Supply, External (V_DDEXT) . . . . . . . –0.3 V to +6.0 V

Input Voltage (Signal Pins) . . . . . . –0.3 V to V_DDEXT+ 0.3 V

T

_STOREStorage Temperature Range . . . . . .–65ºC to +150ºC

T_LEADLead Temperature (5 seconds) max . . . . . . . . . 185ºC

¹Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these

or any other conditions greater than those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-2192M features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

TIMING SPECIFICATIONS

This section contains timing information for the DSP’s

Programmable Flags Cycle Timing

Table 35andFigure 13describeProgrammableFlagoperations.

The signals indicated are asynchronous and are not tied to any

clock.

external signals.

Table 35. Programmable Flags Cycle Timing

Parameter

Min

Max

Unit

t_GPTW

GPIO Timing Pulsewidth

XTALI High Pulsewidth

XTALI Low Pulsewidth

I/O Pins

40

10

15

0

ns

t_XTALIHI

t_XTALILO

t_ENABLE

t_DISABLE

I/O Pins

10

CLK

t_ENABLE

t_DISABLE

FLAG I/O PINS

Figure 13. Programmable Flags Cycle Timing

REV. 0

–31–

ADSP-2192M

Sub-ISA Interface Read/Write Cycle Timing

Table 36, Figure 14, and Figure 15 describe Sub-ISA Interface

Read and Write operations.

Table 36. Sub-ISA Interface Read/Write Cycle Timing

Parameter

Min

Max

Unit

t_ISTW

t_ICYC

t_AESU

t_AEHD

t_ADSU

t_ADHD

t_DHD1

t_DHD2

t_RDDV

t_WDSU

t_RDY1

t_RDY2

IOR/IOW Strobe Width

IOR/IOW Cycle Time

100

240

10

0

10

0

ns

AEN Setup to IOR/IOW Falling

AEN Hold from IOR/IOW Rising

Address Setup to IOR/IOW Falling

Address Hold from IOR/IOW Rising

Data Hold from IOR Rising

20

40

Data Hold from IOW Rising

15

IOR Falling to Valid Read Data

Write Data Setup to IOW Rising

IOR/IOW Rising from IOCHRDY Rising

IOCHRDY Falling from IOR/IOW Rising

10

0

20

AEN

t_AEHD

t_RDY2

t_AESU

t_RDY1

IOCHRDY

t_ICYC

IOR

t_ISTW

t_RDDV

t_DHD1

ISAD15–0

ISAA3–1

t_ADHD

t_ADSU

Figure 14. Sub-ISA Interface Read Cycle Timing

–32–

REV. 0

ADSP-2192M

AEN

IOCHRDY

IOW

t_AEHD

t_RDY2

t_AESU

t_RDY1

t_ICYC

t_STW

t_DHD2

t_WDSU

ISAD15–0

ISAA3–1

t_ADHD

t_ADSU

Figure 15. Sub-ISA Interface Write Cycle Timing

REV. 0

–33–

ADSP-2192M

Output Drive Currents

Power Dissipation

Figure 16 shows typical I-V characteristics for the output drivers

of the ADSP-2192M. The curves represent the current drive

capability of the output drivers as a function of output voltage.

Total power dissipation has two components, one due to internal

circuitry and one due to the switching of external output drivers.

Internal power dissipation is dependent on the instruction

execution sequence and the data operands involved.

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

80

V_DDEXT= 5.0V @ 25°C

60

• Number of output pins that switch during each cycle (O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

V_DDEXT= 3.3V @ 25°C

40

20

OUTPUT CURRENT

V_OH

• Their voltage swing (V_DD

)

0

and is calculated by the formula below.

–20

–40

V_OL

V_DDEXT= 3.3V @ 25°C

P_EXT= O × C × V_DD²× f

–60

–80

V_DDEXT= 5.0V @ 25°C

The load capacitance includes the processor’s package capaci-

tance (C_IN). The switching frequency includes driving the load

high and then back low. Address and data pins can drive high and

low at a maximum rate of 33 MHz.

INPUT CURRENT

–100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

SOURCE (V_DDEXT) VOLTAGE – V

The P_EXTequation is calculated for each class of pins that can

drive as shown in Table 37.

Figure 16. Typical Drive Currents

Table 37. P_EXTCalculation Example

Pin Type No. of Pins % Switching

Address/Data 32

2

ꢀ C

ꢀ f

ꢀ V_DD

= P_EXT

100

0

ꢀ10 pF

ꢀ33 MHz

ꢀ10.9 V

= 0.115 W

= 0.0 W

DEVSEL

1

CBE

100

ꢀ10 pF

ꢀ33 MHz

ꢀ10.9 V

= 0.003 W

CLK

= 0.003 W

P_EXT=0.04687 W

Output Disable Time

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation with the

following formula.

Outputpinsareconsideredtobedisabledwhentheystopdriving,

go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ∆V is dependent on the capacitive load, C_Land the

load current, I_L. This decay time can be approximated by the

equation below.

P_TOTAL= P_EXT+ P_INT

Where:

• P_EXTis from Table 37

C_L∆V

• P_INTis I_DDINTꢀ 2.5 V, using the calculation I_DDINTlisted

in Electrical Characteristics on Page 30.

---------------

=

t_DECAY

I_L

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching simultaneously.

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 17. The time t_MEASUREDis the

interval from when the reference signal switches to when the

output voltage decays

outputlowvoltage. Thet_DECAYis calculated with test loads C_Land

I_L, and with V equal to 0.5 V.

∆V from the measured output high or

∆

Test Conditions

The ADSP-2192M is tested for compliance with all support

industry standard interfaces (PCI, USB, and AC’97). Also, the

DSP is tested for output enable, disable, and pulsewidth. See

Table 35 for the values of these parameters.

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start

driving. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

–34–

REV. 0

ADSP-2192M

INPUT

OR

OUTPUT

REFERENCE

SIGNAL

1.5V

t_MEASURED

t_ENA

Figure 19. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

t_DIS

V_{OH (MEASURED)}

V

_{OH (MEASURED)}– ꢁV 2.0V

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 17). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

V_{OL (MEASURED)}+ ꢁV 1.0V

V_{OL (MEASURED)}

t_DECAY

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation at Output Disable Time

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

on Page 34. Choose

2192M’s output voltage and the input threshold for the device

requiring the hold time. A typical V will be 0.4 V. C_Lis the total

∆V to be the difference between the ADSP-

Figure 17. Output Enable/Disable

∆

bus capacitance (perdata line), and I_Lis the total leakageor three-

state current (per data line). The hold time will be t_DECAYplus the

minimum disable time (i.e., t_DATRWHfor the write cycle).

I

OL

Capacitive Loading

TO

OUTPUT

Output delays and holds are based on standard capacitive loads:

50 pF on all pins. The delay and hold specifications given should

be derated for loads other than the nominal value of 50 pF.

1.5V

50pF

Environmental Conditions

I

OH

The thermal characteristics in which the DSP is operating

influence performance (see Table 38).

Figure 18. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Table 38. Thermal Characteristics

Rating Description

Symbol LQFP

θ_JA33.79°C/W

Thermal Resistance

(Junction-to-Ambient)

Still Air

REV. 0

–35–

ADSP-2192M

144-Lead LQFP Pinout

Table 39 lists the LQFP pinout by signal name. Table 40 lists

the LQFP pinout by pin number.

Table 39. 144-Lead LQFP Pins (Alphabetically by Signal)

No. Signal

No.

Signal

ACRST

ACVAUX

ACVDD

AD0

AD1

AD2

AD3

AD4

AD5

AD6

102 AD26

143 IDSEL

142 IGND

141 IGND

138 IGND

137 IGND

136 IGND

5

IVDD

NC

125 PCIVDD

140 PCIVDD

51

92

93

57

56

55

54

53

48

47

46

44

43

42

37

36

35

34

33

15

14

13

12

11

8

AD27

AD28

AD29

AD30

20

41

50

59

104 NC

120 NC

122 NC

126 NC

139 NC

128 NC

82

83

84

86

87

88

89

90

76

77

85

22

19

40

49

58

132

144

27

135

121

134

129

60

64

72

71

99

98

97

100

73

28

25

101

78

80

81

62

PCIVDD

115 PERR

114 PME

108 PORST

105 REQ

109 RST

107 RVAUX

106 RVDD

110 SCK

127 SDA

NC

AD31

AGND

AIOGND

AQGND

AVDD

ACVAUX

ACVDD

BITCLK

BUS0

BUS1

CBE0

CBE1

CBE2

67

91

68

65

IGND

AD7

AD8

AD9

113 INTAB

112 IO0

NC

PAR

PCIGND

PCIVDD

96

IO1

70

66

94

69

95

31

1

10

21

30

39

52

SDI0

SDI1

SDI2

SDO

SEN

SERR

STOP

SYNC

TCK

TDI

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

124 IO2

123 IO3

45

32

16

4

IO4

IO5

IO6

IO7

CBE3

CLK

130 IOGND

26 IOVDD

116 IOVDD

CLKRUN

CLKSEL

CTRLAUX

CTRLVDD

DEVSEL

EMU

61

63

24

74

17

IRDY

IVDD

TDO

TMS

75

23

79

118

119

133 TRDY

7

9

TRST

6

3

FRAME

GND

18

29

38

XTALI

XTALO

111 IVDD

131 IVDD

103 PCIVDD

117 PCIVDD

2

GNT

–36–

REV. 0

ADSP-2192M

Table 40. 144-Lead LQFP Pins (Numerically by Pin Number)

No. Signal

1

2

3

4

5

6

7

8

PCIGND

AD25

AD24

CBE3

IDSEL

AD23

AD22

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

PCIGND

PAR

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

IGND

RVAUX

CTRLAUX

IVDD

CTRLVDD

RVDD

AVDD

NC

AGND

AQGND

NC

SDA

88

89

90

91

92

93

94

95

96

97

98

99

IO5

IO6

IO7

AIOGND

ACVAUX

ACVDD

NC

BITCLK

SDI2

117 IVDD

118 XTALI

119 XTALO

120 IGND

121 PORST

122 IGND

123 BUS1

124 BUS0

125 IVDD

126 IGND

127 NC

128 INTAB

129 RST

130 CLK

131 GNT

132 PCIVDD

133 PCIGND

134 REQ

CBE1

AD15

AD14

AD13

AD12

AD11

PCIVDD

PCIGND

IVDD

IGND

AD10

AD9

AD8

CBE0

AD7

AD6

AD5

IVDD

IGND

PCIVDD

PCIGND

AD4

AD3

AD2

AD1

AD0

AD21

9

PCIVDD

PCIGND

AD20

AD19

AD18

AD17

AD16

CBE2

FRAME

PCIVDD

IVDD

IGND

PCIGND

IRDY

TRDY

DEVSEL

STOP

CLKRUN

PERR

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

SDI1

SDI0

100 SDO

101 SYNC

102 ACRST

103 IVDD

104 IGND

105 NC

106 NC

107 NC

108 NC

109 NC

SCK

SEN

EMU

TMS

IOGND

IOVDD

TCK

TRST

TDI

TDO

IO0

IO1

IO2

IOVDD

IO3

135 PME

136 AD31

137 AD30

138 AD29

139 IGND

140 IVDD

141 AD28

142 AD27

143 AD26

144 PCIVDD

110 NC

111 GND

112 ACVDD

113 ACVAUX

114 NC

115 NC

116 CLKSEL

SERR

PCIVDD

IVDD

IO4

REV. 0

–37–

ADSP-2192M

OUTLINE DIMENSIONS

144-Lead Plastic Quad Flatpack [LQFP]

(ST-144)

22.00 BSC SQ

20.00 BSC SQ

109

144

1

108

PIN 1 INDICATOR

0.50

BSC

TYP

(LEAD

PITCH)

0.27

0.22

0.17

TYP

SEATING

PLANE

0.08 MAX (LEAD

COPLANARITY)

0.15

0.05

1.45

1.40

1.35

0.75

0.60 TYP

0.45

73

3 6

72

37

1.60 MAX

DETAIL A

TOP VIEW (PINS DOWN)

NOTES:

1.

2.

DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB.

ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3.

CENTER DIMENSIONS ARE NOMINAL.

ORDERING GUIDE

Ambient

Temperature Instruction

Range Rate

On-Chip

SRAM

Package

Description

Part Number¹

Operating Voltage

ADSP-219212MKST160 0ºC to 70ºC 160 MHz

2.4 Mbit

144-Lead LQFP 2.5 Int./3.3 or 5 Ext. V

¹ST = Plastic Quad Flatpack (LQFP).

–38–

REV. 0

–39–

–40–


型号：	ADSP-219212MKST160
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 微控制器和处理器外围集成电路数字信号处理器电脑时钟
文件：	总40页 (文件大小：1284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-219212MKST160 [ADI]

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