ADSP-2196MBST-140X_技术文档

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a

DSP Microcomputer

ADSP-2196

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit

Accumulators

Preliminary Technical Data

ADSP-219x DSP CORE FEATURES

6.25 ns Instruction Cycle Time (Internal), for up to

160 MIPS Sustained Performance

ADSP-218x Family Code Compatible with the Same

Easy -to-Use Algebraic Syntax

Single-Cycle Context Switch between Two Sets of

Computational and DAG Registers

Single-Cycle Instruction Execution

Up to 16M words of Addressable Memory Space with

24 Bits of Addressing Width

Dual Purpose Program Memory for Both Instruction and

Data Storage

Fully Transparent Instruction Cache Allows Dual

Operand Fetches in Every Instruction Cycle

Unified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units

Parallel Execution of Computation and Memory

Instructions

Pipelined Architecture Supports Efficient Code

Execution at Speeds up to 160 MIPS

Register File Computations with All Nonconditional,

Nonparallel Computational Instructions

Powerful Program Sequencer Provides Zero-Overhead

Looping and Conditional Instruction Execution

Architectural Enhancements for Compiled C

Code Efficiency

FUNCTIONAL BLOCK DIAGRAM

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REV. PrA

This information applies to a product under development. Its characteristics One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

and specifications are subject to change without notice. Analog Devices

assumes no obligation regarding future manufacturing unless otherwise

agreed to in writing.

Tel:781/329-4700

Fax:781/326-8703

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ADSP-2196

September 2001

ADSP-2196 DSP FEATURES

External Memory Interface Features Include:

16K Words of On-Chip RAM, Configured as 8K Words

On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM

16K Words of On-Chip 24-bit ROM

Architecture Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for

Added Registers, Ports, and Peripherals

Flexible Power Management with Selectable

Power-Down and Idle Modes

Programmable PLL Supports 1ꢀ to 32ꢀ Frequency

Multiplication, Enabling Full-Speed Operation from

Low-Speed Input Clocks

2.5 V Internal Operation Supports 3.3 V Compliant I/O

Three Full-Duplex Multichannel Serial Ports, Each

Supporting H.100 Standard with A-Law and ꢁ-Law

Companding in Hardware

Two SPI-Compatible Ports with DMA Capability

One UART Port with DMA Capability

Direct Access from the DSP to External Memory for

Data and Instructions.

Support for DMA Block Transfers to/from

External Memory.

Separate Peripheral Memory Space with Parallel

Support for 224K External 16-Bit Registers.

Four General-Purpose Memory Select Signals that

Provide Access to Separate Banks of External

Memory. Bank Boundaries and Size Are User-

Programmable.

Programmable Waitstate Logic with ACK Signal and

Separate Read and Write Wait Counts. Wait Mode

Completion Supports All Combinations of ACK

and/or Wait Count.

I/O Clock Rate Can Be Set to the Peripheral Clock Rate

Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow

Memory Devices.

16 General-Purpose I/O Pins (Eight Dedicated/Eight

Programmable from the External Memory Interface)

with Integrated Interrupt Support

Three Programmable 32-Bit Interval Timers with

Pulsewidth Counter, PWM Generation, and Externally

Clocked Timer Capabilities

Address Translation and Data Word Packing is Provided

to Support an 8- or 16-Bit External Data Bus.

Programmable Read and Write Strobe Polarity.

Separate Configuration Registers for the Four

General-Purpose, Peripheral, and Boot

Memory Spaces.

Up to 11 DMA Channels can be Active at any Given Time

Host Port With DMA Capability for Efficient, Glueless Host

Interface (16-Bit Transfers)

Bus Request and Grant Signals Support the Use of the

External Bus by an External Device.

Boot Methods Include Booting Through External Memory

Interface, SPI Ports, UART Port, or Host Interface

IEEE JTAG Standard 1149.1 Test Access Port Supports

On-Chip Emulation and System Debugging

144-Lead LQFP Package (20 ꢀ 20 ꢀ 1.4 mm) and 144-Lead

Mini-BGA Package (10 ꢀ 10 ꢀ 1.25 mm)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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TABLE OF CONTENTS

September 2001

ADSP-2196

ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . . . 1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . 1

ADSP-2196 DSP Features . . . . . . . . . . . . . . . . . . . . . 2

General Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4

DSP Core Architecture . . . . . . . . . . . . . . . . . . . . 4

DSP Peripherals Architecture . . . . . . . . . . . . . . . 5

Memory Architecture . . . . . . . . . . . . . . . . . . . . . 6

Internal (On-Chip) Memory . . . . . . . . . . . . . . . . 6

Internal On-Chip ROM . . . . . . . . . . . . . . . . . . . . 6

On-Chip Memory Security . . . . . . . . . . . . . . . . . 7

External (Off-Chip) Memory . . . . . . . . . . . . . . . . 7

External Memory Space . . . . . . . . . . . . . . . . . . . . 7

I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . 7

Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . 7

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . 10

Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Host Port Acknowledge (HACK) Modes . . . . . . 10

Host Port Chip Selects . . . . . . . . . . . . . . . . . . . 11

DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . 11

Serial Peripheral Interface (SPI) Ports . . . . . . . . 12

UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Programmable Flag (PFx) Pins . . . . . . . . . . . . . 13

Low Power Operation . . . . . . . . . . . . . . . . . . . . 13

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down Core Mode . . . . . . . . . . . . . . . . . . 13

Power-Down Core/Peripherals Mode . . . . . . . . . 13

Power-Down All Mode . . . . . . . . . . . . . . . . . . . 14

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . 15

Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . 15

Bus Request and Bus Grant . . . . . . . . . . . . . . . . 16

Instruction Set Description . . . . . . . . . . . . . . . . 16

Development Tools . . . . . . . . . . . . . . . . . . . . . . 16

Designing an Emulator-Compatible DSP Board

(Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Target Board Header . . . . . . . . . . . . . . . . . . . . . 17

JTAG Emulator Pod Connector . . . . . . . . . . . . 18

Design-for-Emulation Circuit Information . . . . . 18

Additional Information . . . . . . . . . . . . . . . . . . . 18

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Recommended Operating Conditions . . . . . . . . . . 22

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 22

ABSOLUTE MAXIMUM RATINGS . . . . . . . 24

ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . 24

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . 24

Clock In and Clock Out Cycle Timing . . . . . . . 25

Programmable Flags Cycle Timing . . . . . . . . . . 26

Timer PWM_OUT Cycle Timing . . . . . . . . . . . 27

External Port Write Cycle Timing . . . . . . . . . . . 28

External Port Read Cycle Timing . . . . . . . . . . . 30

External Port Bus Request and Grant Cycle

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Host Port ALE Mode Write Cycle Timing . . . . 34

Host Port ACC Mode Write Cycle Timing . . . . 36

Host Port ALE Mode Read Cycle Timing . . . . . 38

Host Port ACC Mode Read Cycle Timing . . . . 40

Serial Port (SPORT) Clocks and Data Timing . 42

Serial Port (SPORT) Frame Synch Timing . . . . 44

Serial Peripheral Interface (SPI) Port—Master

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Serial Peripheral Interface (SPI) Port—Slave

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Universal Asynchronous Receiver-Transmitter

(UART) Port—Receive and Transmit

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

JTAG Test And Emulation Port Timing . . . . . . 51

Output Drive Currents . . . . . . . . . . . . . . . . . . . 52

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 52

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . 54

Output Disable Time . . . . . . . . . . . . . . . . . . . . 54

Output Enable Time . . . . . . . . . . . . . . . . . . . . . 54

Example System Hold Time Calculation . . . . . . 55

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . 55

Environmental Conditions . . . . . . . . . . . . . . . . 55

Thermal Characteristics . . . . . . . . . . . . . . . . . . 55

ADSP-2196 144-Lead LQFP Pinout . . . . . . . . . 58

ADSP-2196 144-Lead Mini-BGA Pinout . . . . . 62

144-Lead Metric Thin Plastic Quad Flatpack

(LQFP) (ST-144) . . . . . . . . . . . . . . . . . . . 67

144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . 67

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

General Note

• Receive or transmit data over two SPI ports

This data sheet provides preliminary information for the

ADSP-2196 Digital Signal Processor.

• Access external memory through the external memory

interface

• Decrement the timers

GENERAL DESCRIPTION

The ADSP-2196 DSP is a single-chip microcomputer

optimizedfordigitalsignalprocessing(DSP)andotherhigh

speed numeric processing applications.

DSP Core Architecture

The ADSP-2196 instruction set provides flexible data

moves and multifunction (one or two data moves with a

computation) instructions. Every single-word instruction

canbeexecutedinasingleprocessorcycle.TheADSP-2196

assembly language uses an algebraic syntax for ease of

codingandreadability.Acomprehensivesetofdevelopment

tools supports program development.

The ADSP-2196 combines the ADSP-219x family base

architecture (three computational units, two data address

generators, and a program sequencer) with three serial

ports, two SPI-compatible ports, one UART port, a DMA

controller, three programmable timers, general-purpose

Programmable Flag pins, extensive interrupt capabilities,

and on-chip program and data memory spaces.

The functional blockdiagramon page 1shows the architec-

ture of the ADSP-219x core. It contains three independent

computational units: the ALU, the multiplier/accumulator

(MAC), and the shifter. The computational units process

16-bit data from the register file and have provisions to

support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division

primitives are also supported. The MAC performs sin-

gle-cycle multiply, multiply/add, and multiply/subtract

operations. The MAC has two 40-bit accumulators, which

help with overflow. The shifter performs logical and arith-

metic shifts, normalization, denormalization, and derive

exponent operations. The shifter can be used to efficiently

implement numeric format control, including multiword

and block floating-point representations.

The ADSP-2196 architecture is code-compatible with

ADSP-218x family DSPs. Although the architectures are

compatible, the ADSP-2196 architecture has a number of

enhancements over the ADSP-218x architecture. The

enhancements to computational units, data address gener-

ators, and program sequencer make the ADSP-2196 more

flexible and even easier to program than the

ADSP-218x DSPs.

Indirect addressing options provide addressing flexibility—

premodify with no update, pre- and post-modify by an

immediate 8-bit, two’s-complement value and base address

registers for easier implementation of circular buffering.

The ADSP-2196 integrates 32K words of on-chip memory

configured as 8K words (24-bit) of program RAM, 8K

words (16-bit) of data RAM, and 16K words (24-bit) of

program ROM. Power-down circuitry is also provided to

meet the low power needs of battery-operated portable

equipment. The ADSP-2196 is available in 144-leadLQFP

and mini-BGA packages.

Register-usage rules influence placement of input and

resultswithinthecomputationalunits.Formostoperations,

the computational units’ data registers act as a data register

file, permitting any input or result register to provide input

to any unit for a computation. For feedback operations, the

computational units let the output (result) of any unit be

input to any unit on the next cycle. For conditional or mul-

tifunction instructions, there are restrictions on which data

registers may provide inputs or receive results from each

computational unit. For more information, see the

ADSP-219x DSP Instruction Set Reference.

Fabricatedina high-speed, low-power, CMOSprocess, the

ADSP-2196 operates with a 6.25 ns instruction cycle time

(160 MIPS). All instructions, except two multiword

instructions, can execute in a single DSP cycle.

The ADSP-2196’s flexible architecture and comprehensive

instruction set support multiple operations in parallel. For

example, in one processor cycle, the ADSP-2196 can:

A powerful program sequencer controls the flow of instruc-

tion execution. The sequencer supports conditional jumps,

subroutine calls, and low interrupt overhead. With internal

loop counters and loop stacks, the ADSP-2196 executes

looped code with zero overhead; no explicit jump instruc-

tions are required to maintain loops.

• Generate an address for the next instruction fetch

• Fetch the next instruction

• Perform one or two data moves

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

16-bit address pointers. Whenever the pointer is used to

access data (indirect addressing), it is pre- or post-modified

bythevalueofoneoffourpossiblemodifyregisters.Alength

value and base address may be associated with each pointer

to implement automatic modulo addressing for circular

buffers.PageregistersintheDAGsallowcircularaddressing

• Update one or two data address pointers

• Perform a computational operation

These operations take place while the processor

continues to:

• Receive and transmit data through two serial ports

• Receive and/or transmit data from a Host

• Receive or transmit data through the UART

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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September 2001

ADSP-2196

within 64K word boundaries of each of the 256 memory

pages, but these buffers may not cross page boundaries.

Secondaryregistersduplicatealltheprimaryregistersinthe

DAGs; switching between primary and secondary registers

provides a fast context switch.

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Efficient data transfer in the core is achieved with the use of

internal buses:

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• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• DMA Address Bus

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The two address buses (PMA and DMA) share a single

external address bus, allowing memory to be expanded

off-chip, and the two data buses (PMD and DMD) share a

single external data bus. Boot memory space and I/O

memory space also share the external buses.

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Program memory can store both instructions and data, per-

mitting the ADSP-2196 to fetch two operands in a single

cycle, one from program memory and one from data

memory. The DSP’s dual memory buses also let the

ADSP-219x core fetch an operand from data memory and

thenext instructionfromprogrammemory ina singlecycle.

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DSP Peripherals Architecture

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The functional block diagram on page 1 shows the DSP’s

on-chip peripherals, which include the external memory

interface, Host port, serial ports, SPI-compatible ports,

UART port, JTAG test and emulation port, timers, flags,

and interrupt controller. These on-chip peripherals can

connect to off-chip devices as shown in Figure 1.

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The ADSP-2196 has a 16-bit Host port with DMA capa-

bility that lets external Hosts access on-chip memory. This

24-pin parallel port consists of a 16-pin multiplexed

data/address bus and provides a low-service overhead data

move capability. Configurable for 8- or 16-bits, this port

providesagluelessinterfacetoawidevarietyof8-and16-bit

microcontrollers. Two chip-selects provide Hosts access to

the DSP’s entire memory map. The DSP is bootable

through this port.

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Figure 1. ADSP-2196 System Diagram

eight lines provide eight programmable, bidirectional gen-

eral-purpose Programmable Flag lines, six of which can be

mapped to software condition signals.

TheADSP-2196alsohasanexternal memoryinterfacethat

issharedbytheDSP’s core, the DMAcontroller, andDMA

capable peripherals, which include the UART, SPORT0,

SPORT1, SPORT2, SPI0, SPI1, and the Host port. The

external port consists of a 16-bit data bus, a 22-bit address

bus, and control signals. The data bus is configurable to

providean8or16 bitinterfacetoexternalmemory.Support

for word packing lets the DSP access 16- or 24-bit words

from external memory regardless of the external data bus

width. When configured for an 8-bit interface, the unused

The memory DMA controller lets the ADSP-2196 move

data and instructions from between memory spaces: inter-

nal-to-external, internal-to-internal, and external-to-

external. On-chipperipheralscanalsousethiscontrollerfor

DMA transfers.

The ADSP-2196 can respond to up to seventeen interrupts

atanygiventime:threeinternal(stack, emulatorkernel, and

power-down),twoexternal(emulatorandreset),andtwelve

user-defined (peripherals) interrupts. Programmers assign

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

a peripheral to one of the 12 user-defined interrupts. These

assignments determine the priority of each peripheral for

interrupt service.

the remaining 254 pages are addressable off-chip. I/O

memory pages differ from external memory pages in that

I/Opages are 1Kword long, andthe external I/Opages have

their own select pin (IOMS). Pages 0–31 of I/O memory

space reside on-chip and contain the configuration registers

for the peripherals. Both the ADSP-2196 and DMA-capa-

ble peripherals can access the DSP’s entire memory map.

There are three serial ports on the ADSP-2196 that provide

a complete synchronous, full-duplex serial interface. This

interface includes optional companding in hardware and a

widevarietyofframedorframelessdatatransmitandreceive

modes of operation. Each serial port can transmit or receive

an internal or external, programmable serial clock and

frame syncs. Each serial port supports 128-channel Time

Division Multiplexing.

Internal (On-Chip) Memory

TheADSP-2196’sunifiedprogramanddata memoryspace

consists of 16M locations that are accessible through two

24-bit address buses, the PMA and DMA buses. The DSP

uses slightly different mechanisms to generate a 24-bit

address for each bus. The DSP has three functions that

support access to the full memory map.

The ADSP-2196 provides up to sixteen general-purpose

I/O pins, which are programmable as either inputs or

outputs. Eight of these pins are dedicated general purpose

Programmable Flag pins. The other eight of them are mul-

tifunctional pins, acting as general purpose I/O pins when

the DSP connects to an 8-bit external data bus and acting

as the upper eight data pins when the DSP connects to a

16-bitexternaldatabus.TheseProgrammableFlagpinscan

implementedge-orlevel-sensitiveinterrupts,someofwhich

can be used to base the execution of conditional

instructions.

• TheDAGsgenerate24-bitaddressesfordatafetchesfrom

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page.

Three programmable interval timers generate periodic

interrupts. Each timer can be independently set to operate

in one of three modes:

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

theprogramsequencerbasesaddressesforrelativejumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two-word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

• Pulse Waveform Generation mode

• Pulsewidth Count/Capture mode

• External Event Watchdog mode

Each timer has one bi-directional pin and four registers that

implement its mode of operation: A 7-bit configuration

register, a32-bit count register, a32-bit periodregister, and

a32-bitpulsewidthregister. Asinglestatusregistersupports

all three timers. A bit in the mode status register globally

enables or disables all three timers, and a bit in each timer’s

configurationregisterenablesordisablesthecorresponding

timer independently of the others.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

ProgramSequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

addressbits. Beforeacrosspagejumporcall, theprogram

must set the program sequencer’s IJPG register to the

appropriate memory page.

The ADSP-2196 has 1K word of on-chip ROM that holds

boot routines. If peripheral booting is selected, the DSP

starts executing instructions from the on-chip boot ROM,

which starts the boot process from the selected peripheral.

For more information, see Booting Modes on page 15. The

on-chip boot ROM is located on Page 255 in the DSP’s

memory space map.

Memory Architecture

The ADSP-2196 DSP provides 16K words of on-chip

SRAMmemory. Thismemory isdividedintotwo8Kblocks

located on memory Page 0 in the DSP’s memory map. The

DSP also provides 16Kwords of on-chip ROM. In addition

to the internal and external memory space, the ADSP-2196

can address two additional and separate off-chip memory

spaces: I/O space and boot space.

Internal On-Chip ROM

As shown in Figure 2, the DSP’s two internal memory

blocks populate all of Page 0. The entire DSP memory map

consists of 256 pages (Pages 0−255), and each page is 64K

words long. External memory space consists of four

memory banks (banks 0–3) and supports a wide variety of

SRAM memory devices. Each bank is selectable using the

memory select pins (MS3–0) and has configurable page

boundaries, waitstates, and waitstate modes. The 1K word

of on-chip boot-ROM populates the top of Page 255 while

The ADSP-2196 DSP features a 16K-word × 24-bit

on-chip maskable ROM mapped into program memory

space (Figure 3).

Customers canarrangetohavetheROMprogrammedwith

application-specific code.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Figure 2. ADSP-2196 Memory Map

On-Chip Memory Security

memory have Bank0 containing pages 1−63, Bank1 con-

taining pages 64−127, Bank2 containing pages 128−191,

and Bank3 containing Pages 192−254. The MS3–0

memory bank pins select Banks 3–0, respectively. The

external memory interface decodes the 8 MSBs of the DSP

program address to select one of the four banks. Both the

ADSP-219x core and DMA-capable peripherals can access

the DSP’s external memory space.

The ADSP-2196 has a maskable option to protect the

contents of on-chip memories from being accessed. When

the ROM protection is set, the on-chip ROM space cannot

be accessed by a hardware emulator.

External (Off-Chip) Memory

Each of the ADSP-2196’s off-chip memory spaces has a

separate control register, so applications can configure

unique access parameters for each space. The access param-

eters include read and write wait counts, waitstate

completion mode, I/O clock divide ratio, write hold time

extension, strobe polarity, and data bus width. The core

clock and peripheral clock ratios influence the external

memory access strobe widths. For more information, see

Clock Signals on page 14. The off-chip memory spaces are:

I/O Memory Space

The ADSP-2196 supports an additional external memory

called I/O memory space. This space is designed to support

simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data regis-

ters. I/O space supports a total of 256K locations. The first

8K addresses are reserved for on-chip peripherals. The

upper 248K addresses are available for external peripheral

devices. TheDSP’s instruction set providesinstructions for

accessing I/O space. These instructions use an 18-bit

address that is assembled from an 8-bit I/O page (IOPG)

register and a 10-bit immediate value supplied in the

instruction. Both the ADSP-219x core and a Host (through

the Host Port Interface) can access I/O memory space.

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through

the External Port, which can be configured for 8-bit or

16-bit data widths.

Boot Memory Space

External Memory Space

Boot memory space consists of one off-chip bank with 254

pages. The BMS memory bank pin selects boot memory

space. Both the ADSP-219x core and DMA-capable

External memory space consists of four memory banks.

These banks can contain a configurable number of 64K

word pages. At reset, the page boundaries for external

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Figure 3. ADSP-2196 Memory Map, with On-Chip ROM

Table 1. Interrupt Priorities/Addresses (Continued)

peripherals can access the DSP’s off-chip boot memory

space. After reset, the DSP always starts executing instruc-

tions from the on-chip boot ROM. Depending on the boot

configuration, the boot ROM code can start booting the

DSPfrombootmemory.Formoreinformation,seeBooting

Modes on page 15.

IMASK/

IRPTL

Vector

Address

1

Interrupt

Emulation Kernel

3

0x00 0060

0x00 0080

0x00 00A0

0x00 00C0

0x00 00E0

0x00 0100

0x00 0120

0x00 0140

0x00 0160

0x00 0180

User Assigned Interrupt

4

Interrupts

The interrupt controller lets the DSP respond to 17 inter-

rupts with minimum overhead. The controller implements

an interrupt priority scheme as shown in Table 1. Applica-

tions can use the unassigned slots for software and

peripheral interrupts.

5

6

7

8

Table 1. Interrupt Priorities/Addresses

9

IMASK/

IRPTL

Vector

Address

1

Interrupt

10

11

12

Emulator (NMI)—

Highest Priority

NA

Reset (NMI)

0

1

2

0x00 0000

0x00 0020

0x00 0040

Power-Down (NMI)

Loop and PC Stack

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Table 2. Peripheral Interrupts and Priority at Reset

Reset

Table 1. Interrupt Priorities/Addresses (Continued)

IMASK/

IRPTL

Vector

1

Interrupt

Address

Interrupt

ID

Priority

User Assigned Interrupt

13

14

15

0x00 01A0

0x00 01C0

0x00 01E0

Programmable Flag 0 (any PFx)

Programmable Flag 1 (any PFx)

Memory DMA port

12

13

14

11

User Assigned Interrupt—

Lowest Priority

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially.

Interrupts can be masked or unmasked with the IMASK

register. Individual interrupt requests are logically ANDed

with the bits in IMASK; the highest priority unmasked

interrupt isthenselected. Theemulation, power-down, and

reset interrupts are nonmaskable with the IMASK register,

but software can use the DIS INT instruction to mask the

power-down interrupt.

¹These interrupt vectors start at address 0x10000 when the DSP is in

“no-boot”, run-form-external memory mode.

Table 2 shows the ID and priority at reset of each of the

peripheral interrupts. To assign the peripheral interrupts a

differentpriority, applicationswritethenewprioritytotheir

corresponding control bits (determined by their ID) in the

Interrupt Priority Control register. The peripheral inter-

rupt’s position in the IMASK and IRPTL register and its

vector address depend on its priority level, as shown in

Table 1. Because the IMASK and IRPTL registers are

limited to 16 bits, any peripheral interrupts assigned a

priority level of 11 are aliased to the lowest priority bit

position (15) in these registers and share vector address

0x00 01E0.

The Interrupt Control (ICNTL) register controls interrupt

nesting and enables or disables interrupts globally. The gen-

eral-purpose Programmable Flag (PFx) pins can be

configured as outputs, can implement software interrupts,

and (as inputs) can implement hardware interrupts. Pro-

grammable Flag pin interrupts can be configured for

level-sensitive, single edge-sensitive, or dual edge-

sensitive operation.

Table 2. Peripheral Interrupts and Priority at Reset

Table 3. Interrupt Control (ICNTL) Register Bits

Reset

Interrupt

ID

Priority

Bit

Description

Slave DMA/Host Port Interface

SPORT0 Receive

SPORT0 Transmit

SPORT1 Receive

SPORT1 Transmit

SPORT2 Receive/SPI0

SPORT2 Transmit/SPI1

UART Receive

0

0–3

4

Reserved

1

Interrupt Nesting Enable

Global Interrupt Enable

Reserved

2

5

3

6

4

7

MAC-Biased Rounding Enable

Reserved

5

8–9

10

11

12–15

6

PC Stack Interrupt Enable

Loop Stack Interrupt Enable

Reserved

7

UART Transmit

Timer A

8

9

Timer B

10

11

10

11

The IRPTL register is used to force and clear interrupts.

On-chip stacks preserve the processor status and are auto-

maticallymaintainedduringinterrupthandling.Tosupport

interrupt, loop, and subroutine nesting, the PC stack is

33 levels deep, the loop stack is eight levels deep, and the

status stack is 16 levels deep. To prevent stack overflow, the

Timer C

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Table 4. I/O Bus Arbitration Priority (Continued)

PCstack can generate a stack-level interrupt if the PCstack

falls below three locations full or rises above 28

locations full.

DMA Bus Master

Arbitration Priority

The following instructions globally enable or disable

interrupt servicing, regardless of the state of IMASK.

UART Receive DMA

UART Transmit DMA

Host Port DMA

8

9

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

10

Memory DMA

11—Lowest

For quick servicing of interrupts, a secondary set of DAG

and computational registers exist. Switching between the

primary and secondary registers lets programs quickly

service interrupts, while preserving the DSP’s state.

Host Port

The ADSP-2196’s Host port functions as a slave on the

external bus of an external Host. The Host port interface

lets a Host read from or write to the DSP’s memory space,

bootspace, orinternalI/Ospace. ExamplesofHostsinclude

external microcontrollers, microprocessors, or ASICs.

DMA Controller

The ADSP-2196 has a DMA controller that supports

automated data transfers with minimal overhead for the

DSPcore. CyclestealingDMAtransferscanoccur between

the ADSP-2196’s internal memory and any of its

The Host port is a multiplexed address and data bus that

provides both an 8-bit and a 16-bit data path and operates

usinganasynchronoustransmissionprotocol. Throughthis

port, an off-chip Host can directly access the DSP’s entire

memory space map, boot memory space, and internal I/O

space. To access the DSP’s internal memory space, a Host

steals one cycle per access from the DSP. A Host access to

the DSP’s external memory uses the external port interface

and does not stall (or steal cycles from) the DSP’s core.

Because a Host can access internal I/O memory space, a

Host can control any of the DSP’s I/O mapped peripherals.

DMA-capable peripherals. Additionally, DMA transfers

can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interface. DMA-capable peripherals include the

Host port, SPORTs, SPI ports, andUART. Each individual

DMA-capableperipheralhasadedicatedDMAchannel. To

describe each DMA sequence, the DMA controller uses a

set of parameters—called a DMA descriptor. When succes-

sive DMA sequences are needed, these DMA descriptors

can be linked or chained together, so the completion of one

DMA sequence auto-initiates and starts the next sequence.

DMAsequencesdonotcontendforbusaccesswiththeDSP

core, instead DMAs “steal” cycles to access memory.

The Host port is most efficient when using the DSP as a

slave and uses DMA to automate the incrementing of

addresses for these accesses. In this case, an address does

not have to be transferred from the Host for every

data transfer.

All DMA transfers use the DMA bus shown in the func-

tional block diagram on page 1. Because all of the

peripherals use the same bus, arbitration for DMA bus

access is needed. The arbitration for DMA bus access

appears in Table 4.

Host Port Acknowledge (HACK) Modes

The Host port supports a number of modes (or protocols)

for generatinga HACKoutput for the host. The host selects

ACKor ReadyModes using the HACK_PandHACKpins.

The Host port also supports twomodes for address control:

Address Latch Enable (ALE) and Address Cycle Control

(ACC) modes. The DSP auto-detects ALE versus ACC

Mode from the HALE and HWR inputs.

Table 4. I/O Bus Arbitration Priority

DMA Bus Master

Arbitration Priority

SPORT0 Receive DMA

SPORT1 Receive DMA

SPORT2 Receive DMA

SPORT0 Transmit DMA

SPORT1 Transmit DMA

SPORT2 Transmit DMA

SPI0 Receive/Transmit DMA

SPI1 Receive/Transmit DMA

0—Highest

The host port HACK signal polarity is selected (only at

reset) as active high or active low, depending on the value

driven on the HACK_P pin.The HACK polarity is stored

into the host port configuration register as a read only bit.

1

2

3

4

5

6

7

The DSP uses HACK to indicate to the Host when to

complete an access. For a read transaction, a Host can

proceed and complete an access when valid data is present

inthe read buffer andthe host port isnot busy doing a write.

For a write transactions, a Host can complete an access

whenthewritebufferis not full andthehost port isnot busy

doing a write.

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Two mode bits in the Host Port configuration register

HPCR [7:6] define the functionality of the HACK line.

HPCR6 is initialized at reset based on the values driven on

HACK and HACK_P pins (shown in Table 5); HPCR7 is

always cleared (0) at reset. HPCR [7:6] can be modified

after reset by a write access to the host port

a single DMA bus access to prefetch Host direct reads or to

postdirectwrites.Duringassemblyoflargerwords,theHost

port interface asserts ACK for each byte access that does

not start a read or complete a write. Otherwise, the Host

port interface asserts ACK when it has completed the

memory access successfully.

configuration register.

DSP Serial Ports (SPORTs)

The ADSP-2196 incorporates three complete synchronous

serial ports (SPORT0, SPORT1, and SPORT2) for serial

and multiprocessor communications. The SPORTs

support the following features:

Table 5. Host Port Acknowledge Mode Selection

Values Driven At

Reset

HPCR [7:6]

Initial Values

Acknowledge

Mode

• Bidirectional operation—each SPORT has independent

transmit and receive pins.

HACK_P HACK

Bit 7

Bit 6

• Buffered (8-deep) transmit and receive ports—each port

has a data register for transferring data words to and from

otherDSPcomponentsandshiftregistersforshiftingdata

in and out of the data registers.

0

1

0

1

0

1

0

1

0

1

Ready Mode

ACK Mode

Ready Mode

• Clocking—each transmit and receive port can either use

an external serial clock (≤75 MHz) or generate its own,

in frequencies ranging from 1144 Hz to 75 MHz.

ThefunctionalmodesselectedbyHPCR[7:6]areasfollows

(assuming active high signal):

• Word length—each SPORT supports serial data words

from 3 to 16 bits in length transferred in Big Endian

(MSB) or Little Endian (LSB) format.

• ACK Mode—Acknowledge is active on strobes; HACK

goes high from the leading edge of the strobe to indicate

whenthe access cancomplete. After the Hostsamples the

HACK active, it can complete the access by removing the

strobe.The host port then removes the HACK.

• Framing—each transmit and receive port can run with or

withoutframesyncsignalsforeachdataword.Framesync

signals can be generated internally or externally, active

high or low, and with either of two pulsewidths and early

or late frame sync.

• ReadyMode—Ready active on strobes, goes low to inser t

wait state during the access.If the host port can not

complete the access, it de-asserts the HACK/READY

line. In this case, the Host has to extend the access by

keeping the strobe asserted. When the Host samples the

HACK asserted, it can then proceed and complete the

access by de-asserting the strobe.

• Companding in hardware—each SPORT can perform

A-laworµ-lawcompandingaccordingtoITUrecommen-

dation G.711. Companding can be selected on the

transmit and/or receive channel of the SPORT without

additional latencies.

• DMA operations with single-cycle overhead—each

SPORT can automatically receive and transmit multiple

buffers of memory data, one data word each DSP cycle.

EithertheDSP’scoreoraHostprocessorcanlinkorchain

sequences of DMA transfers between a SPORT and

memory. ThechainedDMAcanbedynamicallyallocated

and updated through the DMA descriptors (DMA

transfer parameters) that set up the chain.

While in Address Cycle Control (ACC) mode and the ACK

or Ready acknowledge modes, the HACKis returned active

for any address cycle.

Host Port Chip Selects

There are two chip-select signals associated with the Host

Port: HCMS and HCIOMS. The Host Chip Memory

Select (HCMS) lets the Host select the DSP and directly

access the DSP’s internal/external memory space or boot

memory space. The Host Chip I/O Memory Select

(HCIOMS) lets the Host select theDSPand directly access

the DSP’s internal I/O memory space.

• Interrupts—each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability—each SPORT supports the

H.100 standard.

Before starting a direct access, the Host configures Host

portinterfaceregisters, specifyingthewidthof external data

bus (8- or 16-bit) and the target address page (in the IJPG

register). The DSP generates the needed memory select

signals during the access, based on the target address. The

Host port interface combines the data from one, two, or

threeconsecutiveHostaccesses(uptoone24-bitvalue)into

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ADSP-2196

September 2001

Serial Peripheral Interface (SPI) Ports

In slave mode, the DSP’s core performs the following

sequencetoset uptheSPIport toreceive datafroma master

transmitter:

TheDSPhastwoSPI-compatibleportsthatenabletheDSP

to communicate with multiple SPI-compatible devices.

These ports are multiplexed with SPORT2, so either

SPORT2 or the SPI ports are active, depending on the state

of the OPMODE pin during hardware reset.

1. Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size

and transfer format) SPI transmitter.

The SPI interface uses three pins for transferring data: two

data pins (Master Output-Slave Input, MOSIx, and Master

Input-Slave Output, MISOx) and a clock pin (Serial Clock,

SCKx). Two SPI chip select input pins (SPISSx) let other

SPI devices select the DSP, and fourteen SPI chip select

output pins (SPIxSEL7–1) let the DSP select other SPI

devices.TheSPIselectpinsarereconfiguredProgrammable

Flag pins. Using these pins, the SPI ports provide a full

duplex, synchronous serial interface, which supports both

master and slave modes and multimaster environments.

2. Defines and generates a receive DMA descriptor in

Page 0 of memory space to interrupt at the end of the

data transfer (optional in DMA mode only).

3. Enables the SPI DMA engine for a receive access

(optional in DMA mode only).

4. Starts receiving the data on the appropriate SPI SCKx

edges after receiving an SPI chip select on an SPISSx

input pin (reconfigured Programmable Flag pin)

from a master

In DMA mode only, reception continues until the SPI

DMAwordcounttransitionsfrom1to 0. TheDSP’score

could continue, by queuing up the next DMA descriptor.

Each SPI port’s baud rate and clock phase/polarities are

programmable (see Figure 4), and each has an integrated

DMAcontroller, configurabletosupport bothtransmit and

receive data streams. The SPI’s DMA controller can only

service unidirectional accesses at any given time.

Aslavemodetransmit operationissimilar, excepttheDSP’s

core specifies the data buffer in memory space from which

to transmit data, generates and relinquishes control of the

transmit DMA descriptor, and begins filling the SPI port’s

data buffer. If the SPI controller isn’t ready on time to

transmit, it can transmit a “zero” word.

HCLK

--------------------------------------

SPI Clock Rate =

2 × SPIBAUD

Figure 4. SPI Clock Rate Calculation

UART Port

The UART port provides a simplified UART interface to

another peripheral or Host. It performs full duplex, asyn-

chronous transfers of serial data. Options for the UART

include support for 5–8 data bits; 1 or 2 stop bits; and none,

even, or odd parity. The UART port supports two modes

of operation:

Duringtransfers, theSPIportssimultaneouslytransmitand

receive by serially shifting data in and out on their two serial

datalines. Theserial clocklinesynchronizestheshiftingand

sampling of data on the two serial data lines.

In master mode, the DSP’s core performs the following

sequence to set up and initiate SPI transfers:

• PIO (programmed I/O)

1. Enables and configures the SPI port’s operation (data

size, and transfer format).

The DSP’s core sends or receives data by writing or

reading I/O-mapped UATX or UARX registers, respec-

tively. The data is double-buffered on both transmit and

receive.

2. Selects the target SPI slave with an SPIxSELy output

pin (reconfigured Programmable Flag pin).

3. Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

• DMA (direct memory access)

The DMA controller transfers both transmit and receive

data. This reduces the number and frequency of inter-

rupts required to transfer data to and from memory. The

UART has two dedicated DMA channels. These DMA

channels have lower priority than most DMA channels

because of their relatively low service rates.

4. Enables the SPI DMA engine and specifies transfer

direction (optional in DMA mode only).

5. In non-DMA mode only, reads or writes the SPI port

receive or transmit data buffer.

The SCKx line generates the programmed clock pulses

for simultaneously shifting data out on MOSIx and

shifting data in on MISOx. In DMA mode only, transfers

continue until the SPI DMA word count transitions

from 1 to 0.

The UART’s baud rate (see Figure 5), serial data format,

error code generation and status, and interrupts are

programmable:

• Supported bit rates range from 95 bits to 6.25M bits per

second (100 MHz peripheral clock).

• Supported data formats are 7- or 12-bit frames.

• Transmit and receive status canbe configured to generate

maskable interrupts to the DSP’s core.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

Low Power Operation

HCLK

16 × D

The ADSP-2196 has four low-power options that signifi-

cantly reduce the power dissipation when the device

operates under standby conditions. To enter any of these

modes, the DSP executes an IDLE instruction. The

ADSP-2196 uses configuration of the PDWN, STOPCK,

and STOPALL bits in the PLLCTL register to select

between the low-power modes as the DSP executes the

IDLE. Depending on the mode, an IDLE shuts off clocks

to different parts of the DSP in the different modes. The

low power modes are:

------------------

UART Clock Rate =

1

Figure 5. UART Clock Rate Calculation

¹Where D = 1 to 65536

The timers can be used to provide a hardware-assisted

autobaud detection mechanism for the UART interface.

Programmable Flag (PFx) Pins

TheADSP-2196has16 bidirectional, general-purposeI/O,

Programmable Flag (PF15–0) pins. The PF7–0 pins are

dedicated to general-purpose I/O. The PF15–8 pins serve

either as general-purpose I/O pins (if the DSP is connected

to an 8-bit external data bus) or serve as DATA15–8 lines

(if the DSP is connected to a 16-bit external data bus). The

Programmable Flag pins have special functions for clock

multiplier selection and for SPI port operation. For more

information, see Serial Peripheral Interface (SPI) Ports on

page 12 and Clock Signals on page 14. Ten mem-

ory-mapped registers control operation of the

• Idle

• Power-Down Core

• Power-Down Core/Peripherals

• Power-Down All

Idle Mode

When the ADSP-2196 is in Idle mode, the DSP core stops

executing instructions, retains the contents of the instruc-

tion pipeline, and waits for an interrupt. The core clock and

peripheral clock continue running.

Programmable Flag pins:

To enter Idle mode, the DSP can execute the IDLEinstruc-

tionanywhereincode. Toexit Idlemode, theDSPresponds

to an interrupt and (after two cycles of latency) resumes

executing instructions with the instruction after the IDLE.

• Flag Direction register

Specifies the direction of each individual PFx pin as input

or output.

• Flag Control and Status registers

Power-down Core Mode

When the ADSP-2196 is in Power-Down Core mode, the

DSP core clock is off, but the DSP retains the contents of

thepipelineandkeepsthePLLrunning. Theperipheral bus

keeps running, letting the peripherals receive data.

Specify the value to drive on each individual PFx output

pin. As input, software can predicate instruction

execution on the value of individual PFx input pins

captured in this register. One register sets bits, and one

register clears bits.

To enter Power-Down Core mode, the DSP executes an

IDLE instruction after performing the following tasks:

• Flag Interrupt Mask registers

Enable and disable each individual PFx pin to function

as an interrupt to the DSP’s core. One register sets bits to

enable interrupt function, and one register clears bits to

disable interrupt function. Input PFx pins function as

hardware interrupts, and output PFx pins function as

software interrupts—latching in the IMASK and IRPTL

registers.

• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

• Clear (= 0) the PDWN bit in the PLLCTL register

• Clear (= 0) the STOPALL bit in the PLLCTL register

• Set (= 1) the STOPCK bit in the PLLCTL register

To exit Power-Down Core mode, the DSP responds to an

interruptand(aftertwocyclesoflatency)resumesexecuting

instructions with the instruction after the IDLE.

• Flag Interrupt Polarity register

Specifies the polarity (active high or low) for interrupt

sensitivity on each individual PFx pin.

Power-Down Core/Peripherals Mode

• Flag Sensitivity registers

When the ADSP-2196 is in Power-Down Core/Peripherals

mode, the DSP core clock and peripheral bus clock are off,

but the DSP keeps the PLL running. The DSP does not

retain the contents of the instruction pipeline.The periph-

eral bus is stopped, so the peripherals cannot receive data.

Specify whether individual PFx pins are level- or

edge-sensitive and specify—if edge-sensitive—whether

just the rising edge or both the rising and falling edges of

the signal are significant. One register selects the type of

sensitivity, and one register selects which edges are signif-

icant for edge-sensitivity.

To enter Power-Down Core/Peripherals mode, the DSP

executes an IDLE instruction after performing the

following tasks:

• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

September 2001

• Clear (= 0) the PDWN bit in the PLLCTL register

• Set (= 1) the STOPALL bit in the PLLCTL register

All on-chip peripherals for the ADSP-2196 operate at the

rate set by the peripheral clock. The peripheral clock is

either equal to the core clock rate or one-half the DSP core

clock rate. This selection is controlled by the IOSEL bit in

the PLLCTL register. The maximum core clock

To exit Power-Down Core/Peripherals mode, the DSP

responds to an interrupt and (after five to six cycles of

latency)resumesexecutinginstructionswiththeinstruction

after the IDLE.

is 160 MHz, and the maximum peripheral clock

is 100 MHz—the combination of the input clock and

core/peripheral clock ratios may not exceed these limits.

Power-Down All Mode

When the ADSP-2196 is in Power-Down All mode, the

DSP core clock, the peripheral clock, and the PLL are all

stopped. The DSP does not retain the contents of the

instruction pipeline. The peripheral bus is stopped, so the

peripherals cannot receive data.

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ToenterPower-DownAllmode,theDSPexecutesanIDLE

instruction after performing the following tasks:

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• Enter a power-down interrupt service routine

• Check for pending interrupts and I/O service routines

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To exit Power-Down Core/Peripherals mode, the DSP

responds toan interrupt and (after 500 cycles to re-stabilize

the PLL) resumes executing instructions with the instruc-

tion after the IDLE.

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Clock Signals

The ADSP-2196 can be clocked by a crystal oscillator or a

buffered, shaped clock derived from an external clock oscil-

lator. If a crystal oscillator is used, the crystal should be

connected across the CLKIN and XTAL pins, with two

capacitors connected as shown in Figure 6. Capacitor

valuesaredependent oncrystaltypeandshouldbespecified

by the crystal manufacturer. A parallel-resonant, funda-

mental frequency, microprocessor-grade crystal should be

used for this configuration.

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If a buffered, shaped clock is used, this external clock

connects to the DSP’s CLKIN pin. CLKIN input cannot

be halted, changed, or operated below the specified

frequency during normal operation. This clock signal

shouldbeaTTL-compatiblesignal. Whenanexternalclock

is used, the XTAL input must be left unconnected.

Figure 6. External Crystal Connections

Reset

The RESET signal initiates a master reset of the

ADSP-2196. The RESET signal must be asserted during

the power-up sequence to assure proper initialization.

RESET during initial power-up must be held long enough

toallowtheinternalclocktostabilize. IfRESETis activated

any time after power up, the clock does not continue to run

and requires stabilization time when recovering from reset.

The DSP provides a user-programmable 1ꢀ to 32ꢀ multi-

plication of the input clock, including some fractional

values, to support 128 external tointernal (DSP core) clock

ratios. The MSEL6–0, BYPASS, and DF pins decide the

PLL multiplication factor at reset. At runtime, the multipli-

cationfactorcanbecontrolledinsoftware. Tosupportinput

clocks greater that 100 MHz, the PLL uses an additional

input: the Divide Frequency (DF) pin. If the input clock is

greater than 100 MHz, DF must be high. If the input clock

is less than 100 MHz, DF must be low. The combination of

pullup and pull-down resistors in Figure 6 set up a core

clock ratio of 6:1, which produces a 150 MHz core clock

fromthe 25 MHz input. For other clock multiplier settings,

see the ADSP-219x/2191 DSP Hardware Reference.

Thepower-up sequenceis definedasthe total timerequired

for the crystal oscillator circuit to stabilize after a valid V_DD

isappliedtotheprocessor, andfortheinternalphase-locked

loop (PLL) to lock onto the specific crystal frequency. A

minimum of 100 µs ensures that the PLL has locked, but

does not include the crystal oscillator start-up time. During

The peripheral clock is supplied to the CLKOUT pin.

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ADSP-2196

this power-up sequence the RESET signal should be held

low.Onanysubsequentresets,theRESETsignalmustmeet

The OPMODE, BMODE1, and BMODE0 pins, sampled

during hardware reset, and three bits in the Reset Configu-

ration Register implement these modes:

the minimum pulsewidth specification, t_RSP

.

The RESET input contains some hysteresis. If using an RC

circuit to generate your RESET signal, the circuit should

use an external Schmidt trigger.

• Boot from memory external 16 bits—The memory boot

routine located in boot ROM memory space executes a

boot-stream-formatted program located at address

0x10000 of boot memory space, packing 16-bit external

datainto24-bitinternaldata.TheExternalPortInterface

is configured for the default clock multiplier (128) and

read waitstates (7).

Themasterreset setsall internal stackpointerstothe empty

stack condition, masks all interrupts, and resets all registers

to their default values (where applicable). When RESET is

released, if there is no pending bus request and the chip is

configured for booting, the boot-loading sequence is per-

formed. Program control jumps to the location of the

on-chip boot ROM (0xFF0000).

• Boot from EPROM—The EPROM boot routine located

in boot ROM memory space executes a boot-stream-for-

matted program located at address 0x10000 of boot

memory space, packing 8- or 16-bit external data into

24-bit internal data. The External Port Interface is con-

figured for the default clock multiplier (32) and read

waitstates (7).

Power Supplies

TheADSP-2196 hasseparatepowersupplyconnectionsfor

the internal (V_DDINT) and external (V_DDEXT) power supplies.

The internal supply must meet the 2.5 V requirement. The

external supply must be connected to a 3.3 V supply. All

external supply pins must be connected to the same supply.

• Boot from Host—The (8- or 16-bit) Host downloads a

boot-stream-formatted program to internal or external

memory. The Host’s boot routine is located in internal

ROM memory space and uses the top 16 locations of

Page 0 program memory and the top 272 locations of

Page 0 data memory.

As indicated in Table 6, the OPMODE pin has a dual role,

acting as a boot mode select during reset and determining

SPORT or SPI operation at runtime. If the OPMODE pin

at reset is the opposite of what is needed in an application

during runtime, the application needs to set the OPMODE

bit appropriately during runtime prior to using the corre-

sponding peripheral.

The internal boot ROMsets semaphore A (anIOregister

within the host port) and then polls until the semaphore

isreset.Oncedetected,theinternalbootROMwillremap

the interrupt vector table to Page 0 internal memory and

jump to address 0x0000 internal. From the point of view

of the host interface, an external host has full control of

the DSP's memory map. The Host has the freedom to

directly write internal memory, external memory, and

internal I/O memory space. The DSP core execution is

heldoff until theHost clearsthesemaphoreregister. This

strategy allows the maximum flexibility for the Host to

boot in the program and data code, by leaving it up to

the programmer.

Booting Modes

The ADSP-2196 has seven mechanisms (listed in Table 6)

for automatically loading internal program memory

after reset.

Table 6. Select Boot Mode (OPMODE, BMODE1, and

BMODE0)

• Execute from memory external 8 bits (No Boot)—

execution starts from Page 1 of external memory space,

packing either 8- or 16-bit external data into 24-bit

internal data. The External Port Interface is configured

for the default clock multiplier (128) and read waitstates

(7).

Function

0

Execute from external memory 16 bits

(No Boot)

0

1

0

1

0

1

0

1

0

Boot from EPROM

Boot from Host

Reserved

• Boot from UART—The Host downloads

boot-stream-formatted program using an autobaud

handshake sequence. The Host agent selects a baud rate

withintheUART’sclockingcapabilities.Afterahardware

reset, the DSP’s UART transmits 0xFF values (eight bits

data, one start bit, one stop bit, no parity bit) until

detecting the start of the first memory block. The UART

boot routine is located in internal ROM memory space

and uses the top 16 locations of Page 0 program memory

and the top 272 locations of Page 0 data memory.

Execute from external memory 8 bits

(No Boot)

1

0

1

0

1

Boot from UART

Boot from SPI, up to 4K bits

Boot from SPI, >4K bits up to

512K bits

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• Boot from SPI, up to 4K bits—The SPI0 port uses the

SPI0SEL1 (reconfigured PF2) output pin to select a

single serial EPROM device, submits a read command at

address 0x00, and begins clocking consecutive data into

internal or external memory. Use only SPI-compatible

EPROMs of ≤ 4K bit (12-bit address range). The SPI0

boot routine located in internal ROM memory space

executesa boot-stream-formattedprogram, usingthetop

16 locations of Page 0 program memory and the top 272

locations of Page 0 data memory. The SPI boot configu-

rationisSPIBAUD0=60(decimal), CPHA=1, CPOL=1,

8-bit data, and MSB first.

The ADSP-2196 asserts the BGH pin when it is ready to

start another external port access, but is held off because

the bus was previously granted. This mechanism can be

extended to define more complex arbitration protocols for

implementing more elaborate multimaster systems.

Instruction Set Description

The ADSP-2196 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full

advantage of the processor’s unique architecture, offers the

following benefits:

• ADSP-219xassemblylanguagesyntaxisasupersetofand

source-code-compatible (except for two data registers

and DAG base address registers) with ADSP-218x family

syntax. It may be necessary to restructure ADSP-218x

programs to accommodate the ADSP-2196’s unified

memory space and to conform to its interrupt vector map.

• Boot from SPI, from >4K bits to 512K bits—The SPI0

port uses the SPI0SEL1 (re-configured PF2) output pin

to select a single serial EPROM device, submits a read

command at address 0x00, and begins clocking consecu-

tive data into internal or external memory. Use only

SPI-compatible EPROMs of ≥ 4K bit (16-bit address

range). The SPI0 boot routine located in internal ROM

memory space executes a boot-stream-formatted

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

program, using the top 16 locations of Page 0 program

memoryandthetop272locationsofPage 0datamemory.

• Every instruction, but two, assembles intoa single, 24-bit

word that can execute in a single instruction cycle. The

exceptionsaretwodualwordinstructions.Onewrites16-

or 24-bit immediate data to memory, and the other is an

absolutejump/call withthe24-bit address specifiedinthe

instruction.

Bus Request and Bus Grant

The ADSP-2196 can relinquish control of the data and

address buses to an external device. When the external

device requires access to the bus, it asserts the bus request

(BR) signal. The (BR) signal is arbitrated with core and

peripheral requests. External Bus requests have the lowest

priority. If no other internal request is pending, the external

bus request will be granted. Due to synchronizer and arbi-

tration delays, bus grants will be provided with a minimum

of three peripheral clock delays. The ADSP-2196 will

respond to the bus grant by:

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of

conditions on which to base execution of conditional

instructions.

• Three-statingthedataandaddressbuses andtheMS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

Development Tools

The ADSP-2196 will halt program execution if the bus is

granted to an external device and an instruction fetch or

data read/write request is made to external general-purpose

or peripheral memory spaces. If an instruction requires two

external memory read accesses, the bus will not be granted

between the two accesses. If an instruction requires an

externalmemoryreadandanexternalmemorywriteaccess,

the bus may be granted between the two accesses. The

external memory interface can be configured so that the

core will have exclusive use of the interface. DMA and Bus

Requests will be granted. When the external device releases

BR, the DSPreleases BGand continues program execution

from the point at which it stopped.

The ADSP-2196 is supported with a complete set of

softwareandhardwaredevelopmenttools,includingAnalog

Devices’ emulators and VisualDSP++® development envi-

ronment. The same emulator hardware that supports other

ADSP-219x DSPs, also fully emulates the ADSP-2196.

The VisualDSP++ project management environment lets

programmers develop and debug an application. This envi-

ronment includes an easy-to-use assembler that is based on

an algebraic syntax; an archiver (librarian/library builder),

a linker, a loader, a cycle-accurate instruction-level simula-

The bus request feature operates at all times, even while the

DSP is booting and RESET is active.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Designing an Emulator-Compatible DSP Board

(Target)

tor, a C/C++ compiler, and a C/C++ run-time library that

includes DSP and mathematical functions. Two key points

for these tools are:

The White Mountain DSP (Product Line of Analog

Devices, Inc.) family of emulators are tools that every DSP

developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG DSP. The

emulator uses the TAP to access the internal features of the

DSP, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers.

The DSP must be halted to send data and commands, but

once an operation has been completed by the emulator, the

DSP system is set running at full speed with no impact on

system timing.

• Compiled ADSP-219x C/C++ code efficiency—the

compiler has been developed for efficient translation of

C/C++ code to ADSP-219x assembly. The DSP has

architectural features that improve the efficiency of

compiled C/C++ code.

• ADSP-218x family code compatibility—The assembler

has legacy features to ease the conversion of existing

ADSP-218x applications to the ADSP-219x.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

To use these emulators, the target’s design must include the

interface between an Analog Devices’ JTAG DSP and the

emulation header on a custom DSP target board.

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert break points

• Set conditional breakpoints on registers, memory, and

stacks

Target Board Header

The emulator interface to an Analog Devices’ JTAG DSP

isa14-pinheader, asshowninFigure 7.Thecustomermust

supply this header on the target board in order to commu-

nicate with the emulator. The interface consists of a

standard dual row 0.025" square post header, set on

0.1" ꢀ 0.1" spacing, with a minimumpost length of 0.235".

Pin 3 is the key position used to prevent the pod from being

inserted backwards. This pin must be clipped on the target

board.

• Trace instruction execution

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

• Source level debugging

• Create custom debugger windows

The VisualDSP++ IDE lets programmers define and

manage DSP software development. Its dialog boxes and

property pages let programmers configure and manage all

of the ADSP-219x development tools, including the syntax

highlighting in the VisualDSP++ editor. This capability

permits:

Also, the clearance (length, width, and height) around the

header must be considered. Leave a clearance of at least

0.15" and 0.10" around the length and width of the header,

and reserve a height clearance to attach and detach the pod

connector.

• Control how the development tools process inputs and

generate outputs.

ꢅ

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(08

• Maintain a one-to-one correspondence with the tool’s

command line switches.

*1'

ꢂ

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706

AnalogDevices’DSPemulatorsusetheIEEE1149.1JTAG

testaccessportof theADSP-2196processortomonitorand

control the target board processor during emulation. The

emulatorprovidesfull-speedemulation,allowinginspection

and modification of memory, registers, and processor

stacks. Nonintrusive in-circuit emulation is assured by the

use of the processor’s JTAG interface—the emulator does

not affect target system loading or timing.

%706

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In addition tothe software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the ADSP-219x processor family.

Hardware tools include ADSP-219x PC plug-in cards.

Third Party software tools include DSP libraries, real-time

operating systems, and block diagram design tools.

ꢅꢂ

ꢅꢉ

7'2

723ꢀ9,(:

Figure 7. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in

Place)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

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For current information contact Analog Devices at 800/262-5643

ADSP-2196

September 2001

As can be seen in Figure 7, there are two sets of signals on

the header. There are the standard JTAG signals TMS,

TCK, TDI, TDO, TRST, and EMU used for emulation

purposes (via an emulator). There are also secondary JTAG

signals BTMS, BTCK, BTDI, and BTRSTthat are option-

ally used for board-level (boundary scan) testing.

ꢌꢐꢅꢌꢒ

ꢌꢐꢅꢍꢒ

When the emulator is not connected to this header, place

jumpers across BTMS, BTCK, BTRST, and BTDI as

shown in Figure 8. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the

jumpers whenconnectingthe emulator tothe JTAGheader.

Figure 10. JTAG Pod Connector Keep-Out Area

Design-for-Emulation Circuit Information

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal

buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.ana-

log.com)—use site search on “EE-68”. This document is

updated regularly to keep pace with improvements to

emulator support.

ꢅ

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706

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Additional Information

ꢎ

ꢋ

ꢆ

This data sheet provides a general overview of the

ADSP-2196 architecture and functionality. For detailed

information on the ADSP-219x family core architecture

and instruction set, refer to the ADSP-219x/2191 DSP

Hardware Reference.

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PIN DESCRIPTIONS

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ADSP-2196 pin definitions are listed in Table 7. All

ADSP-2196 inputs are asynchronous and can be asserted

asynchronously to CLKIN (or to TCK for TRST).

723ꢀ9,(:

Unused inputs should be tied or pulled to V_DDEXTor GND,

except for ADDR21–0, DATA15–0, PF7-0, and inputs that

have internal pull-up or pull-down resistors (TRST,

BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS,

TDI, and RESET)—these pins can be left floating. These

pins have a logic-level hold circuit that prevents input from

floating internally.

Figure 8. JTAG Target Board Connector with No Local

Boundary Scan

JTAG Emulator Pod Connector

Figure 9 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 10 displays the keep-out

area for a target board header. The keep-out area allows the

podconnectortoproperlyseatontothetarget boardheader.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25" square post pin.

The following symbols appear in the Type column of

Table 7: G = Ground, I = Input, O = Output, P = Power

Supply, and T = Three-State.

ꢌꢐꢈꢉꢒ

ꢌꢐꢄꢉꢒ

ꢌꢐꢆꢆꢒ

Figure 9. JTAG Pod Connector Dimensions

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

18

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ADSP-2196

Table 7. Pin Descriptions

Type

Function

A21–0

D7–0

O/T

External Port Address Bus

I/O/T External Port Data Bus, least significant 8 bits

I/O/T Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave

D15

/PF15

/SPI1SEL7

I/O

I

Select output 7 (if 8-bit external bus, when SPI1 enabled)

D14

/PF14

/SPI0SEL7

I/O/T Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave

I/O

I

Select output 7 (if 8-bit external bus, when SPI0 enabled)

D13

/PF12

I/O/T Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave

I/O

Select output 6 (if 8-bit external bus, when SPI1 enabled)

/SPI1SEL6

I

D12

/PF12

/SPI0SEL6

I/O/T Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave

I/O

I

Select output 6 (if 8-bit external bus, when SPI0 enabled)

D11

/PF11

/SPI1SEL5

I/O/T Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave

I/O

I

Select output 5 (if 8-bit external bus, when SPI1 enabled)

D10

/PF10

/SPI0SEL5

I/O/T Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave

I/O

I

Select output 5 (if 8-bit external bus, when SPI0 enabled)

D9

/PF9

/SPI1SEL4

I/O/T Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select

I/O

I

output 4 (if 8-bit external bus, when SPI1 enabled)

D8

/PF8

/SPI0SEL4

I/O/T Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select

I/O

I

output 4 (if 8-bit external bus, when SPI0 enabled)

PF7

/SPI1SEL3

I/O/T Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency

I

(divisor select for PLL input during boot)

/DF

I

PF6

/SPI0SEL3

/MSEL6

I/O/T Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6

I

(during boot)

PF5

/SPI1SEL2

/MSEL5

I/O/T Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5

I

(during boot)

PF4

/SPI0SEL2

/MSEL4

I/O/T Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4

I

(during boot)

PF3

/SPI1SEL1

/MSEL3

I/O/T Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3

I

(during boot)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Table 7. Pin Descriptions (Continued)

Type

Function

PF2

/SPI0SEL1

/MSEL2

I/O/T Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2

I

(during boot)

PF1

/SPISS1

/MSEL1

I/O/T Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1

I

(during boot)

PF0

/SPISS0

/MSEL0

I/O/T Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0

I

(during boot)

RD

O/T

I

External Port Read Strobe

WR

External Port Write Strobe

ACK

External Port Access Ready Acknowledge

External Port Boot Space Select

External Port IO Space Select

External Port Memory Space Selects

External Port Bus Request

BMS

O/T

I

IOMS

MS3–0

BR

BG

O

External Port Bus Grant

BGH

O

External Port Bus Grant Hang

HAD15–0

HA16

I/O/T Host Port Multiplexed Address and Data Bus

I

Host Port MSB of Address Bus

HACK_P

HRD

I

Host Port ACK Polarity

I

Host Port Read Strobe

HWR

I

Host Port Write Strobe

HACK

HALE

HCMS

HCIOMS

CLKIN

XTAL

O

I

Host Port Access Ready Acknowledge

Host Port Address Latch Strobe or Address Cycle Control

Host Port Internal Memory–Internal I/O Memory–Boot Memory Select

Host Port Internal I/O Memory Select

Clock Input/Oscillator input

I

O

I

Oscillator output

BMODE1–0

OPMODE

CLKOUT

BYPASS

Boot Mode 1–0. The BMODE1 and BMODE0 pins have 85 kΩ internal pull-up resistors.

Operating Mode. The OPMODE pin has a 85 kΩ internal pull-up resistor.

Clock Output

I

O

I

Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 kΩ internal pull-up

resistor.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

Table 7. Pin Descriptions (Continued)

Type

Function

RCLK1–0

I/O/T SPORT1–0 Receive Clock

RCLK2/SCK1 I/O/T SPORT2 Receive Clock/SPI1 Serial Clock

RFS1–0

I/O/T SPORT1–0 Receive Frame Sync

RFS2/MOSI1

TCLK1–0

I/O/T SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data

I/O/T SPORT1–0 Transmit Clock

TCLK2/SCK0 I/O/T SPORT2 Transmit Clock/SPI0 Serial Clock

TFS1–0

I/O/T SPORT1–0 Transmit Frame Sync

TFS2/MOSI0

DR1–0

I/O/T SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data

I/T

I/O/T SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data

O/T SPORT1–0 Serial Data Transmit

SPORT1–0 Serial Data Receive

DR2/MISO1

DT1–0

DT2/MISO0

TMR2–0

RXD

I/O/T SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data

I/O/T Timer output or capture

I

UART Serial Receive Data

UART Serial Transmit Data

TXD

O

I

RESET

ProcessorReset. Resetsthe ADSP-2196toa knownstateandbeginsexecutionat theprogram

memory location specified by the hardware reset vector address. The RESET input must be

asserted (low) at power-up. The RESET pin has a 85 kΩ internal pull-up resistor.

TCK

TMS

TDI

I

Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has a 85 kΩ

internal pull-up resistor.

Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has a 85 kΩ

internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has

a 85 kΩ internal pull-up resistor.

TDO

O

I

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after

power-up or held low for proper operation of the ADSP-2196. The TRST pin has a 65 kΩ

internal pull-down resistor.

EMU

O

Emulation Status (JTAG). Must be connected to the ADSP-2196 emulator target board

connector only.

V_DDINT

V_DDEXT

GND

NC

P

Core Power Supply. Nominally 2.5 V dc and supplies the DSP’s core processor. (four pins).

I/O Power Supply; Nominally 3.3 V dc. (nine pins).

P

G

Power Supply Return. (twelve pins).

Do Not Connect. Reserved pins that must be left open and unconnected.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

1

Parameter Description

Min

Max

Unit

V_DDINT

V_DDEXT

V_IH1

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

2.37

TBD

2.0

2.63

3.6

V

2

High Level Input Voltage , @ V_DDINT= max

V_DDEXT

0.6

V

3

V_IH2

High Level Input Voltage , @ V_DDINT= max

2.2

V

2

V_IL

Low Level Input Voltage , @ V_DDINT= min

–0.3

0

V

T_AMB

Ambient Operating Temperature

70

ºC

¹Specifications subject to change without notice.

²Applies to input and bidirectional pins: DATA15–0, HAD15–0, HA16, HALE, HACK, HACK_P, BYPASS, HRD, HWR, ACK, PF7–0, HCMS,

HCIOMS, BR, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1, RFS2/MOSI1, OPMODE, BMODE1–0, TMS, TDI, TCK, DT2/MISO0, DR0, DR1,

DR2/MISO1, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1.

³Applies to input pins: CLKIN, RESET, TRST.

ELECTRICAL CHARACTERISTICS

1

Parameter

Description

Test Conditions

Min

Typical Max

Unit

2

V_OH

High Level Output Voltage

@ V_DDEXT= min,

2.4

V

I_OH= –0.5 mA

2

V_OL

I_IH

Low Level Output Voltage

@ V_DDEXT= min,

0.4

V

I_OL= 2.0 mA

3, 4

High Level Input Current

@ V_DDEXT= max,

V_IN= V_DDmax

TBD

10

µA

mA

2

I_IL

Low Level Input Current

High Level Input Current

@ V_DDEXT= max,

V_IN= 0 V

5

I_INP

@ V_DDEXT= max,

V_IN= V_DDmax

3

I_ILP

Low Level Input Current

@ V_DDEXT= max,

V_IN= 0 V

6

5

I_OZH

I_OZL

I_DD-IDLE1

Three-State Leakage Current

Supply Current (Core) Idle1

@ V_DDEXT= max,

V_IN= V_DDmax

@ V_DDEXT= max,

V_IN= 0 V

10

PLL Enabled, CCLK

7

= 160 MHz

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

ELECTRICAL CHARACTERISTICS ^(CONTINUED)

1

Parameter

Description

Test Conditions

Min

Typical Max

Unit

I_DD-IDLE2

Supply Current (Core) Idle2

PLL Enabled, HCLK

= 80 MHz, CCLK

Disabled

1

mA

7

I_DD-TYPICAL

Supply Current (Core) Typical

Supply Current (Core) Peak

Supply Current (Peripheral)

HCLK = 80 MHz,

CCLK = 160

MHz

184

215

5

mA

7,8

I_DD-PEAK

HCLK = 80 MHz,

CCLK = 160

7,8

MHz

I

DD-PERIPHERAL1

PLL Enabled, Core,

7

HCLK Disabled

7

I

DD-PERIPHERAL2

Supply Current (Peripheral)

Supply Current

HCLK = 80 MHz

60

mA

µA

I

DD-POWERDOWN

PLL, Core, HCLK,

100

7

CLKIN Disabled

9, 10

C_IN

Input Capacitance

f_IN= 1 MHz,

TBD

pF

T_CASE= 25°C,

V_IN= 2.5 V

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,

BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,

RFS2/MOSI1, BMS, TDO, TXD, EMU.

³Applies toinput pins: ACK, BR, HCMS, HCIOMS, OPMODE, BMODE1–0, HA16, HALE, HRD, HWR, CLKIN, RESET, TCK, TDI, TMS, TRST,

DR0, DR1, BYPASS, RXD.

⁴Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI, RESET.

⁵Applies to input pin with internal pull-down: TRST

⁶Applies to three-statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU.

⁷Test Conditions: @ V_DDINT= 2.5V, T_AMB= 25ºC

⁸Refer to Table 23 on page 52 for definitions of operation types.

⁹Applies to all signal pins.

¹⁰Guaranteed, but not tested.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ABSOLUTE MAXIMUM RATINGS

1,2

V_DDINTInternal (Core) Supply Voltage .......–0.3 to 3.0 V

V_DDEXTExternal (I/O) Supply Voltage ............–0.3 to 4.6 V

V_IL–V_IHInput Voltage ......................–0.5 to V_DDEXT+0.5 V

V_OL–V_OHOutput Voltage Swing........–0.5 to V_DDEXT+0.5 V

C_LLoad Capacitance............................................ 200 pF

t_CCLKCore Clock Period........................................6.25 ns

f

_CCLKCore Clock Frequency.............................. 160 MHz

t_HCLKPeripheral Clock Period...................................10 ns

_HCLKPeripheral Clock Frequency...................... 100 MHz

T_STOREStorage Temperature Range .............. –65 to 150ºC

_LEADLead Temperature (5 seconds)...................... 185ºC

f

T

¹Specifications subject to change without notice.

²Stressesgreaterthanthoselistedabovemaycausepermanentdamagetothedevice.

These are stress ratings only, and functional operation of the device at these or any

other conditions greater than those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

ESD SENSITIVITY

CAUTION:

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-2196 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high-energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

TIMING SPECIFICATIONS

This section contains timing information for the DSP’s external signals.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Clock In and Clock Out Cycle Timing

Table 8 and Figure 11 describe clock and reset operations. Per V

Internal (Core) Supply Voltage, –0.3 to 3.0 V on

DDINT

page 24, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.

Table 8. Clock In and Clock Out Cycle Timing

Parameter

Description

Min

Max

Unit

Switching Characteristic

t_CKODCLKOUT delay from CLKIN

t_CKO

Timing Requirements

0

5.8

ns

1

CLKOUT period

10

2,3

t_CK

CLKIN period

6.25

200

ns

µs

ns

t_CKL

CLKIN low pulse

2.2

t_CKH

t_WRST

t_MSLS

t_MSLH

CLKIN high pulse

2.2

RESET asserted pulsewidth low

200t_CLKOUT

160

MSELx/BYPASS stable before RESET asserted setup

MSELx/BYPASS stable after RESET de-asserted hold

1000

¹Figure 11 shows a ꢀ2 ratio betweenCLKOUT =2ꢀCLKIN (or t_HCLK= 2ꢀt_CCLK), but the ratio has many programmable options. For more information

see the System Design chapter of the ADSP-219x/2191 DSP Hardware Reference.

²In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t_CK=t_CCLK

.

³In bypass mode, t_CK=t_CCLK

.

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W_: 5 6 7

5 ( 6 ( 7

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W_0 6 6

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& / . 2 8 7

Figure 11. Clock In and Clock Out Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Programmable Flags Cycle Timing

Table 9 and Figure 12 describe programmable flag operations.

Table 9. Programmable Flags Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristic

t_DFO

t_HFO

Timing Requirement

t_HFIFlag input hold is asynchronous

Flag output delay with respect to HCLK

3

ns

Flag output hold after HCLK high

TBD

3

TBD

ns

+ & / .

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W_+ ) 2

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3 )

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FL A G IN P U T

Figure 12. Programmable Flags Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

26

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September 2001

ADSP-2196

Timer PWM_OUT Cycle Timing

Table 10 and Figure 13 describe timer expired operations. The input signal is asynchronous in “width capture mode” and

has an absolute maximum input frequency of 50 MHz.

Table 10. Timer PWM_OUT Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristic

1

32

t_HTO

Timer pulsewidth output

6.25

(2 –1) cycles

ns

¹The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

+ & / .

ꢀW _+ 7 2

3 : 0 B 2 8 7

Figure 13. Timer PWM_OUT Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

External Port Write Cycle Timing

Table 11 and Figure 14 describe external port write operations.

The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates

and ACK. To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP

to wait, and the DSP requires two EMI clock cycles after ACK goes high to finish the access. For more information, see

the External Port chapter in the ADSP-219x/2191 DSP Hardware Reference

Table 11. External Port Write Cycle Timing

1, 2, 3

Parameter Description

Min

Max

Unit

Switching Characteristics

4

t_CWA

t_CSWS

t_AWS

t_AKS

EMI clock low to WR asserted delay

2.8

6.5

7.0

ns

Chip select asserted to WR de-asserted delay

Address valid to WR setup and delay

ACK asserted to EMI clock high delay

WR de-asserted to chip select de-asserted

WR de-asserted to address invalid

4.3

4.9

6.0

t_WSCS

t_WSA

t_CWD

t_WW

4.8

7.0

6.6

2.7

4.5

EMI clock low to WR de-asserted delay

WR strobe pulsewidth

2.5

t_HCLK–0.5

1.5

t_CDA

t_CDD

t_DSW

t_DHW

WR to data enable access delay

4.1

WR to data disable access delay

3.3

7.4

Data valid to WR de-asserted setup

WR de-asserted to data invalid hold time; wt_hold=0

WR de-asserted to data invalid hold time; wt_hold=1

t_HCLK–1.4

3.4

t_HCLK+4.8

7.4

t_HCLK+3.4

t_HCLK+7.4

Timing Requirement

t_AKW

ACK strobe pulsewidth

10.0

ns

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst-case operating conditions.

³The pad loads for these timing parameters are 20 pF.

⁴EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds

to HCLK (at similar clock ratios).

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

28

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September 2001

ADSP-2196

( 0 ,

& / 2 & .

W _& : $

W_& 6 : 6

W_$ . 6

W_& : '

W _: 6 & 6

0 6 ꢂ ± ꢌ

,2 0 6

% 0 6

$ ꢄ ꢅ ±

ꢌ

W_: :

W_$ : 6

W_: 6 $

: 5

W _$ . :

$ & .

W_& ' '

W _' + :

W_& ' $

W_' 6 :

' ꢅ ꢍ ±

ꢌ

Figure 14. External Port Write Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

External Port Read Cycle Timing

Table 12 and Figure 15 describe external port read operations. For additional information on the ACK signal, see the

discussion on on page 28.

Table 12. External Port Read Cycle Timing

1, 2, 3

Parameter Description

Min

Max

Unit

Switching Characteristics

4

t_CRA

t_CSRS

t_ARS

t_AKS

t_CRD

t_RSCS

t_RW

EMI clock low to RD asserted delay

2.8

6.5

7.0

ns

Chip select asserted to RD asserted delay

Address valid to RD setup and delay

ACK asserted to EMI clock high delay

EMI clock low to RD de-asserted delay

RD de-asserted to chip select de-asserted setup

RD strobe pulsewidth

4.3

4.9

6.0

2.5

2.7

7.0

4.8

t_HCLK–0.5

4.5

t_RSA

RD de-asserted to address invalid setup

6.6

Timing Requirements

t_AKW

t_CDA

t_RDA

t_ADA

t_SDA

t_SD

ACK strobe pulsewidth

10.0

0.0

ns

RD to data enable access delay

RD asserted to data access setup

Address valid to data access setup

Chip select asserted to data access setup

Data valid to RD de-asserted setup

RD de-asserted to data invalid hold

t_HCLK–5.5

t_HCLK–0.2

t_HCLK–0.6

1.8

0.0

t_HRD

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst-case operating conditions.

³The pad loads for these timing parameters are 20 pF.

⁴EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds

to HCLK (at similar clock ratios).

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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September 2001

ADSP-2196

( 0 ,

& / 2 & .

W _& 5 $

W_& 6 5 6

W_$ . 6

W _& 5 '

W _5 6 & 6

0 6 ꢂ ±

ꢌ

,2 0 6

% 0 6

$ ꢄ ꢅ ± ꢌ

W _5 :

W_5 6 $

W _$ 5 6

5 '

W _$ . :

$ & .

W_& ' $

W _+ 5 '

W_6 '

' ꢅ ꢍ ± ꢌ

W_5 ' $

W_$ ' $

W_6 ' $

Figure 15. External Port Read Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

External Port Bus Request and Grant Cycle Timing

Table 13 and Figure 16 describe external port bus request and bus grant operations.

Table 13. External Port Bus Request and Grant Cycle Timing

1, 2, 3

Parameter Description

Min

Max

Unit

Switching Characteristics

t_SD

CLKOUT high to xMS, address, and RD/WR disable

4.3

4.0

2.2

2.4

ns

t_SE

CLKOUT low to xMS, address, and RD/WR enable

CLKOUT high to BG asserted setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT high to BG de-asserted hold time

CLKOUT high to BGH asserted setup

CLKOUT high to BGH de-asserted hold time

Timing Requirements

t_BS

BR asserted to CLKOUT high setup

CLKOUT high to BR de-asserted hold time

4.6

0.0

ns

t_BH

¹t_HCLKis the peripheral clock period.

²These are preliminary timing parameters that are based on worst-case operating conditions.

³The pad loads for these timing parameters are 20 pF.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

32

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September 2001

ADSP-2196

& / . 2 8 7

W _% 6

W_% +

% 5

W_6 '

W_6 (

0 6 ꢂ ± ꢌ

,2 0 6

% 0 6

W_6 '

W_6 (

$ ꢄ ꢅ ± ꢌ

W_6 '

W_6 (

: 5

5 '

W _' % *

W_( % *

% *

W _' % +

W _( % +

% * +

Figure 16. External Port Bus Request and Grant Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Host Port ALE Mode Write Cycle Timing

Table 14 and Figure 17 describe host port write operations in Address Latch Enable (ALE) mode. For more information

on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.

Table 14. Host Port ALE Mode Write Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

1

t_WHKS

t_WHKH

t_WHS

HWR asserted to HACK asserted (setup, ACK Mode)

0.6

0.6+t_NH

ns

HWR de-asserted to HACK de-asserted (hold, ACK Mode)

HWR asserted to HACK asserted (setup, Ready Mode)

HWR asserted to HACK de-asserted (hold, Ready Mode)

2

0.6

1

t_WHH

2+t_NH

Timing Requirements

t_CSAL

t_ALPW

t_ALCSW

t_WCSW

t_ALW

HCMS or HCIOMS asserted to HALE asserted

0

4

1

ns

HALE asserted pulsewidth

HALE de-asserted to HCMS or HCIOMS de-asserted

HWR de-asserted to HCMS or HCIOMS de-asserted

HALE de-asserted to HWR asserted

t_WCS

HWR de-asserted (after last byte) to HCMS or

HCIOMS de-asserted (ready for next write)

t_HKWD

t_AALS

t_ALAH

t_DWS

HACK asserted to HWR de-asserted (hold, ACK Mode)

Address valid to HALE de-asserted (setup)

HALE de-asserted to address invalid (hold)

Data valid to HWR de-asserted (setup)

1.5

4

ns

1.5

4

t_WDH

HWR de-asserted to data invalid (hold)

1

¹t_NHare peripheral bus latencies (nꢀt_HCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

34

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September 2001

ADSP-2196

+ & 0 6

+ , 2 0 6

W _& 6 $ /

W _$ / 3 :

W_{$ / & 6 :}

W_: & 6 :

+ $ / (

W_: & 6

W _$ / :

+ : 5

W _+ . : '

W_: + . +

W_: + . 6

+ $ & .

ꢁ $ & .

+ $ & . ꢀ ( $ & + ꢀ % < 7 (

0 2 ' ( ꢃ

W_: + +

W _: + 6

+ $ & .

ꢁ5 ( $ ' <

0 2 ' ( ꢃ

+ $ & . ꢀ ) ,5 6 7 ꢀ % < 7 (

W_' : 6

W_$ $ / 6

W _$ / $ +

W_: ' +

+ $ ' ꢅ ꢍ ±

ꢌ

$ ' ' 5 ( 6 6

' $ 7 $

$ ' ' 5 ( 6 6

9 $ / ,'

+ $ ꢅ ꢈ

6 7 $ 5 7

) , 5 6 7

% < 7 (

/ $ 6 7

% < 7 (

1 ( ; 7 ꢀ : 2 5 '

) , 5 6 7 ꢀ : 2 5 '

Figure 17. Host Port ALE Mode Write Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Host Port ACC Mode Write Cycle Timing

Table 15 and Figure 18 describe host port write operations in Address Cycle Control (ACC) mode. For more information

on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.

Table 15. Host Port ACC Mode Write Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

1

t_WHKS

t_WHKH

t_WHS

HWR asserted to HACK asserted (setup, ACK Mode)

0.6

0.6+t_NH

ns

HWR de-asserted to HACK de-asserted (hold, ACK Mode)

HWR asserted to HACK asserted (setup, Ready Mode)

HWR asserted to HACK de-asserted (hold, Ready Mode)

2

0.6

1

t_WHH

2+t_NH

Timing Requirements

t_WAL

t_CSAL

t_ALCS

HWR asserted to HALE de-asserted (delay)

1.5

0

ns

HCMS or HCIOMS asserted to HALE asserted (delay)

HALE de-asserted to optional HCMS or HCIOMS

de-asserted

1

t_WCSW

t_ALW

t_CSW

t_WCS

HWR de-asserted to HCMS or HCIOMS de-asserted

HALE asserted to HWR asserted

1

ns

0.5

1

HCMS or HCIOMS asserted to HWR asserted

2

HWR de-asserted (after last byte) to HCMS or

HCIOMS de-asserted (ready for next write)

1

t_ALEW

t_HKWD

t_ADW

t_WAD

t_DWS

HALE de-asserted to HWR asserted

1

ns

HACK asserted to HWR de-asserted (hold, ACK Mode)

Address valid to HWR asserted (setup)

HWR de-asserted to address invalid (hold)

Data valid to HWR de-asserted (setup)

HWR de-asserted to data invalid (hold)

1.5

4

1

4

t_WDH

1

¹t_NHare peripheral bus latencies (nꢀt_HCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

36

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September 2001

ADSP-2196

+ & 0 6

+ , 2 0 6

W_$ / & 6

W_: & 6 :

W_: $ /

W_& 6 $ /

+ $ / (

W_& 6 :

W_: & 6

W_$ / :

W _$ / ( :

+ : 5

W _+ . : '

W _: + +

W _' : 6

W_: + . +

W _: + . 6

+ $ & .

ꢁ $ & .

+ $ & . ꢀ ( $ & + ꢀ % < 7 (

0 2 ' ( ꢃ

W_: + 6

+ $ & .

ꢁ5 ( $ ' <

0 2 ' ( ꢃ

+ $ & . ꢀ) ,5 6 7 ꢀ% < 7 (

W_$ ' :

W _: $ '

W _: ' +

+ $ ' ꢅ ꢍ ± ꢌ

+ $ ꢅ ꢈ

$ ' ' 5 ( 6 6

9 $ / ,'

$ ' ' 5 ( 6 6

9 $ / ,'

' $ 7 $

9 $ / ,'

6 7 $ 5 7

) , 5 6 7

% < 7 (

/ $ 6 7

% < 7 (

1 ( ; 7 ꢀ : 2 5 '

) , 5 6 7 ꢀ : 2 5 '

Figure 18. Host Port ACC Mode Write Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Host Port ALE Mode Read Cycle Timing

Table 16 and Figure 19 describe host port read operations in Address Latch Enable (ALE) mode. For more information

on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.

Table 16. Host Port ALE Mode Read Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

1

t_RHKS

t_RHKH

t_RHS

HRD asserted to HACK asserted (setup, ACK Mode)

2

2+t_NH

ns

HRD de-asserted to HACK de-asserted (hold, ACK Mode)

HRD asserted to HACK asserted (setup, Ready Mode)

HRD asserted to HACK de-asserted (hold, Ready Mode)

2

1

t_RHH

2+t_NH

Timing Requirements

t_CSALHCMS or HCIOMS asserted to HALE asserted (delay)

t_ALCS

0

1

ns

HALE de-asserted to optional HCMS or HCIOMS

de-asserted

t_RCSW

t_ALR

HRD de-asserted to HCMS or HCIOMS de-asserted

HALE de-asserted to HRD asserted

1

ns

t_RCS

HRD de-asserted (after last byte) to HCMS or

HCIOMS de-asserted (ready for next read)

t_ALPW

t_HKRD

t_AALS

t_ALAH

t_RDH

HALE asserted pulsewidth

4

ns

HACK asserted to HRD de-asserted (hold, ACK Mode)

Address valid to HALE de-asserted (setup)

HALE de-asserted to address invalid (hold)

HRD de-asserted to data invalid (hold)

1.5

4

1

¹t_NHare peripheral bus latencies (nꢀt_HCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

38

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September 2001

ADSP-2196

+ & 0 6

+ , 2 0 6

W _& 6 $ /

W_$ / 3 :

W_$ / & 6

W _5 & 6 :

+ $ / (

W_5 & 6

W _$ / 5

+ 5 '

W _+ . 5 '

W_5 + . +

W_5 + . 6

+ $ & .

ꢁ $ & .

+ $ & . ꢀ) 2 5 ꢀ( $ & + ꢀ % < 7 (

0 2 ' ( ꢃ

W_5 + +

W_5 + 6

+ $ & .

ꢁ5 ( $ ' <

+ $ & . ꢀ ) ,5 6 7ꢀ % < 7 (

0 2 ' ( ꢃ

W_$ $ / 6

W_$ / $ +

W_5 ' +

+ $ ' ꢅ ꢍ ±

ꢌ

$ ' ' 5 ( 6 6

9 $ / ,'

' $ 7 $

9 $ / ,'

$ ' ' 5 ( 6 6

9 $ / , '

9 $ / ,'

+ $ ꢅ ꢈ

6 7 $ 5 7

) , 5 6 7

: 2 5 '

) , 5 6 7

% < 7 (

/ $ 6 7

% < 7 (

1 ( ; 7 ꢀ : 2 5 '

Figure 19. Host Port ALE Mode Read Cycle TIming

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Host Port ACC Mode Read Cycle Timing

Table 17 and Figure 20 describe host port read operations in Address Cycle Control (ACC) mode. For more information

on ACK, Ready, ALE, and ACC mode selection, see the Host port modes description on page 10.

Table 17. Host Port ACC Mode Read Cycle Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

1

t_RHKS

t_RHKH

t_RHS

HRD asserted to HACK asserted (setup, ACK Mode)

1

1+t_NH

ns

HRD de-asserted to HACK de-asserted (hold, ACK Mode)

HRD asserted to HACK asserted (setup, Ready Mode)

HRD asserted to HACK de-asserted (hold, Ready Mode)

2

1

t_RHH

2+t_NH

Timing Requirements

t_CSALHCMS or HCIOMS asserted to HALE asserted (delay)

t_ALCS

0

1

ns

HALE de-asserted to optional HCMS or HCIOMS

de-asserted

t_RCSW

t_ALW

t_ALER

t_CSR

HRD de-asserted to HCMS or HCIOMS de-asserted

HALE asserted to HWR asserted

1

ns

0.5

1

HALE de-asserted to HWR asserted

HCMS or HCIOMS asserted to HRD asserted

1

2

t_RCS

HRD de-asserted (after last byte) to HCMS or

HCIOMS de-asserted (ready for next read)

1

t_WAL

t_HKRD

t_ADW

t_WAD

t_RDH

HWR de-asserted to HALE de-asserted (delay)

HACK asserted to HRD de-asserted (hold, ACK Mode)

Address valid to HWR de-asserted (setup)

HWR de-asserted to address invalid (hold)

HRD de-asserted to data invalid (hold)

1.5

4

ns

1

¹t_NHare peripheral bus latencies (nꢀt_HCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

40

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September 2001

ADSP-2196

+ & 0 6

+ , 2 0 6

W _$ / & 6

W _5 & 6 :

W_& 6 $ /

W_: $ /

+ $ / (

W_$ / :

W _5 & 6

+ : 5

W _& 6 5

W_$ / ( 5

+ 5 '

W_+ . 5 '

W_5 + . +

W_5 + . 6

+ $ & .

ꢁ $ & .

+ $ & . ꢀ ( $ & + ꢀ % < 7 (

0 2 ' ( ꢃ

W_5 + +

W_5 + 6

+ $ & .

ꢁ5 ( $ ' <

+ $ & . ꢀ ) ,5 6 7 ꢀ % < 7 (

0 2 ' ( ꢃ

W_: $ '

W _5 ' +

W_$ ' :

$ ' ' 5 ( 6 6

9 $ / ,'

' $ 7 $

9 $ / ,'

$ ' ' 5 ( 6

6

+ $ ' ꢅ ꢍ ±

ꢌ

9 $ / ,'

+ $ ꢅ ꢈ

9 $ / , '

6 7 $ 5 7

) , 5 6 7

% < 7 (

/ $ 6 7

% < 7 (

1 ( ; 7 ꢀ : 2 5 '

) , 5 6 7 ꢀ : 2 5 '

Figure 20. Host Port ACC Mode Read Cycle TIming

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Serial Port (SPORT) Clocks and Data Timing

Table 18 and Figure 21 describe SPORT transmit and receive operations.

1

Table 18. Serial Port (SPORT) Clocks and Data Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

2

t_HOFSE

t_DFSE

RFS Hold after RCLK (Internally Generated RFS)

RFS Delay after RCLK (Internally Generated RFS)

0

12.4

12.1

12.0

6.8

ns

2

t_DDTEN

t_DDTTE

t_DDTIN

t_DDTTI

Transmit Data Delay after TCLK

2

Data Disable from External TCLK

2

Data Enable from Internal TCLK

2

Data Disable from Internal TCLK

6.3

Timing Requirements

t_SCLKIWTCLK/RCLK Width

t_SFSITFS/RFS Setup before TCLK/RCLK

20

ns

3

–0.6

–0.3

–2.3

1.9

3, 4

t_HFSI

TFS/RFS Hold after TCLK/RCLK

3

t_SDRI

Receive Data Setup before RCLK

3

t_HDRI

t_SCLKW

t_SFSE

Receive Data Hold after RCLK

TCLK/RCLK Width

20

3

TFS/RFS Setup before TCLK/RCLK

–0.6

–2.2

1.8

3, 4

t_HFSE

t_SDRE

t_HDRE

TFS/RFS Hold after TCLK/RCLK

3

Receive Data Setup before RCLK

3

Receive Data Hold after RCLK

¹To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed:

1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

²Referenced to drive edge.

³Referenced to sample edge.

⁴RFS hold after RCLK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCLK for late external TFS is 0 ns minimum from

drive edge.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

' $ 7 $ ꢀ7 5 $ 1 6 ) ( 5 ² ꢀ, 1 7 ( 5 1 $ / ꢀ& / 2 & .

' $ 7 $ ꢀ7 5 $ 1 6 ) ( 5 ² ꢀ( ; 7 ( 5 1 $ / ꢀ & / 2 & .

' 5 , 9 (

( ' * (

6 $ 0 3 /(

( ' * (

' 5 , 9 (

( ' * (

6 $ 0 3 / (

( ' * (

W_{6 & / . , :}

W _{6 & / . :}

5 ꢇ 7 & / .

W_' ) 6 (

W_+ ) 6 (

W_{+ 2 ) 6 (}

W_6 ) 6 ,

W_+ ) 6 ,

W_{+ 2 ) 6 (}

W_6 ) 6 (

) 6

W_+ ' 5 (

W _+ ' 5 ,

W _6 ' 5 ,

W_6 ' 5 (

' 5

1 2 7 ( ꢑꢀ( , 7 + ( 5 ꢀ 7 + ( ꢀ 5 , 6 , 1 * ꢀ ( ' * ( ꢀ2 5 ꢀ) $ / / ,1 * ꢀ( ' * ( ꢀ 2 ) ꢀ 5 & / . ꢀ ꢁ( ; 7 ( 5 1 $ / ꢃ

2 5 ꢀ 5 & / . ꢀ ꢁ,1 7 ( 5 1 $ / ꢃꢀ & $ 1 ꢀ % ( ꢀ 8 6 ( ' ꢀ $ 6 ꢀ 7+ ( ꢀ$ & 7, 9 ( ꢀ 6 $ 0 3 /, 1 * ꢀ ( ' * ( ꢐ

' 5 ,9 ( ꢀ( ' * (

' 5 ,9 ( ꢀ ( ' * (

7 & / .

7 & / . ꢀ ꢁ( ; 7 ꢃ

W_{' ' 7 ( 1}

W _{' ' 7 7 (}

' 7

' 5 ,9 ( ꢀ( ' * (

' 5 ,9 ( ꢀ ( ' * (

7 & / . ꢀ ꢁ, 1 7 ꢃ

7 & / .

W _{' ' 7 , 1}

W _{' ' 7 7 ,}

' 7

Figure 21. Serial Port (SPORT) Clocks and Data

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September 2001

Serial Port (SPORT) Frame Synch Timing

Table 19 and Figure 22 describe SPORT frame synch operations.

To determine whether communication is possible between two devices at clock speed n, the following specifications must

be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3)

R/TCLK width.

Table 19. Serial Port (SPORT) Frame Synch Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

1

t_HOFSE

RFS Hold after RCLK (Internally Generated RFS)

12.4

12.2

4.7

ns

1

t_HOFSI

TFS Hold after TCLK (Internally Generated TFS)

2

t_DDTENFS

t_DDTLFSE

Data Enable from late FS or MCE = 1, MFD = 0

Data Delay from Late External TFS or External RFS with

4.7

3

MCE = 1, MFD = 0

1

t_HDTE

t_HDTI

t_DDTE

t_DDTI

Transmit Data Hold after TCLK (external clk)

12.4

12.2

11.1

ns

1

Transmit Data Hold after TCLK (internal clk)

0

1

Transmit Data Delay after TCLK (external clk)

1

Transmit Data Delay after TCLK (internal clk)

Timing Requirements

t_SFSETFS/RFS Setup before TCLK/RCLK (external clk)

t_SFSI

3

–0.6

TBD

ns

3

TFS/RFS Setup before TCLK/RCLK (internal clk)

¹Referenced to drive edge.

²MCE = 1, TFS enable and TFS valid follow t_DDTLFSEand t_DDTENFS

³Referenced to sample edge.

.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

(; 7( 5 1$ / ꢀ5 ( &( ,9( ꢀ)6 ꢀ: ,7+ ꢀ0 & ( ꢀꢓꢀꢅ ꢏꢀ0 )' ꢀꢓꢀꢌ

' 5 , 9 (ꢀ

6 $ 0 3 / (

' 5 , 9 (

5 ꢇ 7 & /.

W_{+ 2 ) 6 ( ꢇ ,}

_ꢀW_{6 ) 6 ( ꢇ ,}

ꢁ6 ( ( ꢀ 1 2 7 ( ꢃ

) 6

W _{' ' 7 ( ꢇ ,}

_ꢀW_{+ ' 7 ( ꢇ ,}

_ꢀW_{' ' 7 / ) 6 (}

W _{' ' 7 ( 1 ) 6}

' 5

) , 5 6 7 ꢀ % , 7

6 ( & 2 1 ' ꢀ% , 7

/$ 7 (ꢀ( ;7 ( 5 1 $ /ꢀ7 5 $ 1 60 ,7ꢀ) 6ꢀ

' 5 , 9 (ꢀ

6 $ 0 3 / (

' 5 , 9 (

5 ꢇ 7 & /.

_ꢀW_{6 ) 6 ( ꢇ ,}

W_{+ 2 ) 6 ( ꢇ}

ꢁ6 ( ( ꢀ 1 2 7 ( ꢃ

,

) 6

W_{' ' 7 ( ꢇ ,}

_ꢀW _{' ' 7 / ) 6 (}

_ꢀW_{+ ' 7 ( ꢇ ,}

W _{' ' 7 ( 1 ) 6}

' 7

) , 5 6 7 ꢀ % , 7

6 ( & 2 1 ' ꢀ% , 7

Figure 22. Serial Port (SPORT) Frame Synch

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

September 2001

Serial Peripheral Interface (SPI) Port—Master Timing

Table 20 and Figure 23 describe SPI port master operations.

Table 20. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

SPIxSEL low to first SCLK edge (x=0 or 1)

Serial clock high period

2t_HCLK

4t_HCLK

2t_HCLK

0

ns

Serial clock low period

Serial clock period

Last SCLK edge to SPIxSEL high (x=0 or 1)

Sequential transfer delay

t_SPITDM

t_DDSPID

t_HDSPID

SCLK edge to data out valid (data out delay)

SCLK edge to data out invalid (data out hold)

6

5

0

Timing Requirements

t_SSPIDData input valid to SCLK edge (data input setup)

t_HSPIDSCLK sampling edge to data input invalid

1.6

ns

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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6 3 , [ 6 ( /

ꢁ2 8 7 3 8 7 ꢃ

ꢁ[ ꢀꢓ ꢀꢌ ꢀR U ꢀꢅ ꢃ

W _+ ' 6 0

W _{6 3 , 7 ' 0}

W_{6 3 , & + 0}

W _{6 3 , & / 0}

W _{6 3 , & / .}

W _{6 ' 6 & , 0}

6 & / .

ꢁ& 3 2 / ꢀ ꢓꢀ ꢌ ꢃ

ꢁ2 8 7 3 8 7 ꢃ

W_{6 3 , & / 0}

W _{6 3 , & + 0}

6 & / .

ꢁ& 3 2 / ꢀ ꢓꢀ ꢅ ꢃ

ꢁ2 8 7 3 8 7 ꢃ

W_{' ' 6 3 , '}

W_{+ ' 6 3 , '}

0 2 6 ,

0 6 %

/ 6 %

ꢁ2 8 7 3 8 7 ꢃ

&3+$ꢓꢅ

W _{6 6 3 , '}

W _{+ 6 3 , '}

W_{6 6 3 , '}

W_{+ 6 3 , '}

0 ,6 2

0 6 %

9 $ / ,'

/ 6 %

ꢁ, 1 3 8 7 ꢃ

9 $ / , '

W _{' ' 6 3 , '}

W _{+ ' 6 3 , '}

0 2 6 ,

ꢁ2 8 7 3 8 7 ꢃ

0 6 %

/ 6 %

&3+$ꢓꢌ

W _{6 6 3 , '}

W _{+ 6 3 , '}

0 6 %

/ 6 %

0 , 6 2

9 $ / ,'

9 $ / , '

ꢁ, 1 3 8 7 ꢃ

Figure 23. Serial Peripheral Interface (SPI) Port—Master

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

September 2001

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 21 and Figure 24 describe SPI port slave operations.

Table 21. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter Description

Min

Max

Unit

Switching Characteristics

t_DSOE

SPISS assertion to data out active

0

6

5

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS deassertion to data high impedance

SCLK edge to data out valid (data out delay)

SCLK edge to data out invalid (data out hold)

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

Serial clock high period

2t_HCLK

4t_HCLK

2t_HCLK

1.6

ns

Serial clock low period

Serial clock period

Last SPICLK edge to SPISS not asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPISS assertion to first SPICLK edge

Data input valid to SCLK edge (data input setup)

SCLK sampling edge to data input invalid

1.6

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

6 3 , 6 6

ꢁ, 1 3 8 7

ꢃ

W _{6 3 , & + 6}

W_{6 3 , & / 6}

W_{6 3 , & / .}

W _+ ' 6

W_{6 3 , 7 ' 6}

6 & / .

ꢁ& 3 2 / ꢀ ꢓꢀ ꢌ ꢃ

ꢁ, 1 3 8 7 ꢃ

W _{6 3 , & / 6}

W_{6 ' 6 & ,}

W_{6 3 , & + 6}

6 & / .

ꢁ& 3 2 / ꢀ ꢓꢀ ꢅ ꢃ

ꢁ, 1 3 8 7 ꢃ

W_{' ' 6 3 , '}

W_' 6 2 (

W _{+ ' 6 3 , '}

W_{' ' 6 3 , '}

W_{' 6 ' + ,}

0 ,6 2

0 6 %

/ 6 %

ꢁ2 8 7 3 8 7 ꢃ

W _{+ 6 3 , '}

& 3 + $ ꢓ ꢅ

W_{6 6 3 , '}

W _{+ 6 3 , '}

W _{6 6 3 , '}

0 2 6 ,

0 6 %

/6 %

ꢁ, 1 3 8 7 ꢃ

9 $ / ,'

W_' 6 2 (

W_{' ' 6 3 , '}

W_{' 6 ' + ,}

0 ,6 2

/ 6 %

0 6 %

ꢁ2 8 7 3 8 7 ꢃ

& 3 + $ ꢓ ꢌ

W _{6 6 3 , '}

W_{+ 6 3 , '}

0 6 %

/ 6 %

0 2 6 ,

9 $ / ,'

9 $ / , '

ꢁ, 1 3 8 7 ꢃ

Figure 24. Serial Peripheral Interface (SPI) Port—Slave

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September 2001

internal UART interrupts and the external data operations.

These latencies are negligible at the data transmission rates

for the UART.

Universal Asynchronous Receiver-Transmitter (UART)

Port—Receive and Transmit Timing

Figure 25 describes UART port receive and transmit oper-

ations. The maximum baud rate is HCLK/16. As shown in

Figure 25 there is some latency between the generation

+ & / .

ꢁ6 $ 0 3 / (

& / 2 & . ꢃ

5 ; '

' $ 7 $ ꢁꢍ ± ꢆ ꢃ

6 7 2 3

5 ( & ( , 9 (

,1 7 ( 5 1 $ /

8 $ 5 7 ꢀ 5 ( & ( , 9 ( ꢀ ꢀ% , 7 ꢀ 6 ( 7 ꢀ% < ꢀ' $ 7 $ ꢀ6 7 2 3 ꢔ

& / ( $ 5 ( ' ꢀ % < ꢀ ) , ) 2 ꢀ 5 ( $ 'ꢀ

8 $ 5 7 ꢀ 5 ( & ( , 9 (

,1 7 ( 5 5 8 3 7

6 7 $ 5 7

7 ; '

' $ 7 $ ꢁꢍ ± ꢆ ꢃ

6 7 2 3 ꢀ ꢁ ꢅ ± ꢄ ꢃ

$ 6 ꢀ ' $ 7$

: 5 ,7 ( 1 ꢀ 7 2

% 8 ) ) ( 5

7 5 $ 1 6 0 , 7

, 1 7 ( 5 1 $ /

8 $ 5 7 ꢀ 7 5 $ 1 6 0 , 7

,1 7 ( 5 5 8 3 7

8 $ 5 7 ꢀ 7 5 $ 1 6 0 , 7 ꢀ % ,7 ꢀ 6 ( 7 ꢀ% < ꢀ3 5 2 * 5 $ 0 ꢔ

& / ( $ 5 ( ' ꢀ % < ꢀ : 5 , 7 ( ꢀ 7 2 ꢀ 7 5 $ 1 6 0 ,7

Figure 25. UART Port—Receive and Transmit Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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JTAG Test And Emulation Port Timing

September 2001

ADSP-2196

Table 22 and Figure 26 describe JTAG port operations.

Table 22. JTAG Port Timing

Parameter Description

Switching Characteristics

Min

Max

Unit

t_DTDO

t_DSYS

Timing Parameters

TDO Delay from TCK Low

4

5

ns

1

System Outputs Delay After TCK Low

0

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

t_SSYS

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

4

5

2

System Inputs Setup Before TCK Low

2

t_HSYS

t_TRSTW

System Inputs Hold After TCK Low

3

TRST Pulsewidth

4

¹SystemOutputs =DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF7–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,

TFS0, TFS1, RFS0, RFS1, BMS.

²SystemInputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF7–0, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,

CLKIN, RESET.

³50 MHz max.

W _7 & .

7 & .

W_6 7 $ 3

W _+ 7 $ 3

7 0 6

7 ' ,

W_' 7 ' 2

7 ' 2

W_6 6 < 6

W _+ 6 < 6

6 < 6 7 ( 0

,1 3 8 7 6

W_{' 6 < 6ꢀ}

6 < 6 7 ( 0

2 8 7 3 8 7 6

Figure 26. JTAG Port Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

September 2001

Output Drive Currents

ꢅꢄꢌ

Figure 27 shows typical I-V characteristics for the output

driversoftheADSP-2196. Thecurvesrepresentthecurrent

drive capability of the output drivers as a function of output

voltage.

ꢅꢌꢌ

ꢆꢌ

ꢈꢌ

ꢉꢌ

ꢄꢌ

Power Dissipation

ꢌ

7%'

Total power dissipation has two components, one due to

internal circuitry and one due to the switching of external

output drivers. Internal power dissipation is dependent on

the instruction execution sequence and the data operands

involved. Using the current-versus-operation information

in Table 23, designers can estimate the ADSP-2196’s

internal power supply (V_DDINT) input current for a specific

application, according to the formula in Figure 28.

±ꢄꢌ

±ꢉꢌ

±ꢈꢌ

±ꢆꢌ

±ꢅꢌꢌ

±ꢅꢄꢌ

ꢌ

ꢌꢐꢍ

ꢅ

ꢅꢐꢍ

ꢄꢐꢌ

ꢄꢐꢍ

ꢂꢐꢌ

ꢂꢐꢍ

6285&(ꢀꢁ9

ꢃꢀ92/7$*(ꢀ±ꢀ9

''( ;7

Figure 27. ADSP-2196 Typical Drive Currents

Table 23. ADSP-2196 Operation Types Versus Input Current

1

I_DD(mA)

CCLK = 80 MHz

CCLK = 160 MHz

Activity

Core

Peripheral

Core

Peripheral

2

Power down

0

3

Idle 1

0

3

0

5

4

Idle 2

0

30

0

60

5

Typical

95

184

6

Peak

112

215

¹Test conditions: V_DD= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; T_AMB= 25 ºC.

²PLL, Core, peripheral clocks, and CLKIN are disabled.

³PLL is enabled and Core and peripheral clocks are disabled.

⁴Core CLK is disabled and peripheral clock is enabled. This is a power- down interrupt mode. The timer can be used to generate an interrupt to enable the

Core clock.

⁵All instructions execute from internal memory. 100% of the instructions are MAC with dual operand addressing, with changing data fetched using a linear

address sequence, and 50% of the instructions move data from PM to a data register.

⁶All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using

a linear address sequence.

I_DDINT= (%Peak × I_DD-PEAK) + %Typical × I_DD-TYPICAL) + (%Idle × I_DD-IDLE) + (%Powerdown × I_DD-PWRDWN

)

Figure 28. I

Calculation

DDINT

Theexternalcomponentoftotalpowerdissipationiscaused

by the switching of output pins. Its magnitude depends on:

• Their load capacitance (C)

• Their voltage swing (V_DD)

• The number of output pins that switch during each cycle

(O)

and is calculated by the formula in Figure 29.

• The maximum frequency at which they can switch (f)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

P_EXT= O × C × V_DD²× f

Calculation

Figure 29. P

EXT

The load capacitance should include the processor’s

package capacitance (C_IN). The switching frequency

includes driving the load high and then back low. Address

and data pins can drive high and low at a maximum rate of

1/(2t_CK). The write strobe can switch every cycle at a

frequency of 1/t_CK. Select pins switch at 1/(2t_CK), but selects

can switch on each cycle. For example, estimate P_EXTwith

the following assumptions:

• A system with one bank of external data memory—asyn-

chronous RAM (16-bit)

• One64Kꢀ16RAMchipis used, eachwithaloadof10pF

• Maximum peripheral speed HCLK = 100 MHz

• External data memory writes occur every other cycle, a

rate of 1/(4t_HCLK), with 50% of the pins switching

• The bus cycle time is 100 MHz (t_HCLK= 20 nsec)

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ADSP-2196

The P_EXTequation is calculated for each class of pins that

can drive as shown in Table 24.

Table 24. P_EXTCalculation

2

Pin Type

# of Pins

% Switching

ꢀ C

ꢀ f

ꢀ V_DD

= P_EXT

Address

MSx

15

1

50

0

TBD pF

ꢀ25.0 MHz

ꢀ25 MHz

ꢀ10.9 V

ꢀ 10.9 V

ꢀ10.9 V

=TBD W

P_EXT=TBD W

WR

1

—

50

—

Data

16

1

ꢀ25.0 MHz

ꢀ100 MHz

CLKOUT

A typical power consumption can now be calculated for

these conditions by adding a typical internal power dissipa-

tion with the formula in Figure 30.

The output disable time t_DISis the difference between

t

_MEASUREDand t_DECAYas shown in Figure 32. The time

_MEASUREDis the interval from when the reference signal

switches to when the output voltage decays –V from the

measured output high or output low voltage. The t_DECAYis

calculated with test loads C_Land I_L, and with –V equal to

0.5 V.

P_TOTAL= P_EXT+ P_INT

Figure 30. P

(Typical) Calculation

TOTAL

5()(5(1&(

6,*1$/

Where:

• P_EXTis from Table 24

W_0($685( '

W_(1$

W_',6

ꢀ

• P_INTis I_DDINTꢀ 2.5V, using the calculation I_DDINTlisted in

Power Dissipation on page 52

9

2+ꢀꢁ0($6 85('ꢃ

9

ꢀ±ꢀ'9

ꢄꢐꢌ9

ꢅꢐꢌ9

2+ꢀꢁ0( $685('ꢃ

Note that the conditions causing a worst-case P_EXTare

different from those causing a worst-case P_INT. Maximum

ꢀꢕꢀ'9

2/ꢀꢁ0( $685('ꢃ

9

ꢀ

2/ꢀꢁ0($685('ꢃ

W_'(&$<

P_INTcannot occur while 100% of the output pins are

switching from all ones to all zeros. Note also that it is not

common for an application to have 100% or even 50% of

the outputs switching simultaneously.

287387ꢀ67236

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287387ꢀ67$576

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72ꢀ%(ꢀ$3352;,0$7(/<ꢀꢅꢐꢍ9

Test Conditions

The DSP is tested for output enable, disable, and hold time.

Figure 32. Output Enable/Disable

Output Disable Time

Output Enable Time

Output pins are considered to be disabled when they stop

driving, go into a high impedance state, and start to decay

from their output high or low voltage. The time for the

voltage on the bus to decay by – V is dependent on the

capacitive load, C_Landthe loadcurrent, I_L. This decay time

can be approximated by the equation in Figure 31.

Output pins are considered to be enabled when they have

made a transition from a high impedance state to when they

start driving. The output enable time t_ENAis the interval

from when a reference signal reaches a high or low voltage

level to when the output has reached a specified high or low

trip point, as shown in the Output Enable/Disable diagram

(Figure 32). If multiple pins (such as the data bus) are

enabled, the measurement value is that of the first pin to

start driving.

C_L∆V

---------------

=

t_DECAY

I_L

Figure 31. Decay Time Calculation

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ADSP-2196

0.4 V. C_Lis the total bus

capacitance (per data line),

ꢅꢐꢍ9

rise time varies with capaci-

tance. These figures also

and I_Lis the total leakage or show graphically how output

three-state current (per data delays and holds vary with

line). The hold time will be load capacitance. (Note that

,

2/

,1387

25

ꢅꢐꢍ9

287387

Figur3eV4o.ltagReeferencLeevelfsoArC

t

_DECAYplus the minimum

disable time (i.e., t_DATRWHfor not apply to output disable

this graph or derating does

72

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ꢕꢅꢐꢍ9

287387

3,1

ꢍꢌS)

the write cycle).

delays; see Output Disable

Time on page 54.) The

graphs in these figures may

not be linear outside the

ranges shown.

Example System Hold

Time Calculation

Todeterminethedataoutput

Capacitive Loading

Output delays and holds are

based on standard capacitive

loads: 50 pF on all pins (see

Figure 37). The delay and

hold specifications given

should be derated by a factor

of 1.5 ns/50 pF for loads

other than the nominal value

of 50 pF. Figure 35 and

hold time in a particular

,

s²y⁺stem, first calculate t_DECAY

using the equation given in

Figure 31. Choose –V to be

the difference between the

ADSP-2196’soutput voltage

and the input threshold for

the device requiring the hold

time. A typical –V will be

Figure 33. Equivalent

Device Loading

for AC

Measurements

(Includes All

Fixtures)

Figure 36 show how output

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7%'

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ꢌ

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Figure 35. Typical Output Rise Time (10%–90%,

=Max) vs. Load Capacitance

V

DDEXT

Environmental Conditions

The thermal characteristics

inwhichtheDSPisoperating

influence performance.

beused.Aheatsinkshouldbe • θ_CA= Value fromTable 25.

attached to the ground plane

• θ_JB= TBD°C/W

(as close as possible to the

There are some important

thermal pathways) with a

things to note about these

thermal adhesive.

Thermal Characteristics

The ADSP-2196 comes in a

144-lead LQFP or 144-lead

Ball Grid Array (mini-BGA)

package. The ADSP-2196 is

specified for an ambient tem-

perature(T_AMB)ascalculated

using the formula in

T_AMBcalculations and the

values in Table 25:

Where:

• T_AMB= Ambient tempera-

ture (measured near top

surface of package)

• This represents thermal

resistance at total power of

TBD W.

• PD = Power dissipation in

W (this value depends

upon the specific applica-

tion; a method for

calculating PD is shown

under Power Dissipation).

• For the LQFPpackage:θ_JC

= 0.96°C/W

For the mini-BGA

Figure 38.Toensurethatthe

package: θ_JC= 8.4°C/W

T_AMBdata sheet specification

is not exceeded, a heatsink

and/oranairflowsourcemay

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

ꢂꢐꢍ

ꢂꢐꢌ

ꢄꢐꢍ

ꢄꢐꢌ

7%'

ꢅꢐꢍ

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ꢌꢐꢍ

ꢌ

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ꢈꢌ

ꢆꢌ

ꢅꢌꢌ

ꢅꢄꢌ

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ꢅꢈꢌ

ꢅꢆꢌ

ꢄꢌꢌ

/2$'ꢀ&$3$&,7$1&( ±S)

Figure 36. Typical Output Rise Time (10%-90%,

V

=Min) vs. Load Capacitance

DDEXT

ꢍ

ꢉ

ꢂ

ꢄ

ꢅ

7%'

120,1$/

±

ꢄꢍ

ꢍꢌ

ꢎꢍ

ꢅꢌꢌ

ꢅꢄꢍ

ꢅꢍꢌ

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/2$'ꢀ&$3 $&,7$1&(±S)

Figure 37. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature)

T_AMB= T_CASE– PD × θ_CA

Figure 38. T

Calculation

CASE

1

Table 25. θ_CAValues

Airflow

(Linear Ft./Min.)

0

100

0.5

200 400 600

Airflow

1

2

3

(Meters/Second)

LQFP:

θ_CA(°C/W)

44.3 41.4 38.5 35.3 32.1

26 24 22 20.9 19.8

Mini-BGA:

θ_CA(°C/W)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

¹These are preliminary estimates.

September 2001

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Table 26. 144-Lead LQFP

Pins (Alphabetically By

Signal) (Continued)

Table 26. 144-Lead LQFP

Pins (Alphabetically By

Signal) (Continued)

Table 26. 144-Lead LQFP

Pins (Alphabetically By

Signal) (Continued)

ADSP-2196 144-Lead LQFP

Pinout

Table 26 lists the LQFP

pinout by signal name.

SIGNAL

PIN #

SIGNAL

PIN #

SIGNAL

PIN #

Table 26. 144-Lead LQFP

Pins (Alphabetically By

Signal)

BMODE1

BMS

BR

71

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAD8

HAD9

HAD10

HAD11

HAD12

HAD13

HAD14

HAD15

HA16

3

PF0

34

35

36

37

38

39

41

42

61

68

50

73

62

69

51

122

52

78

57

65

47

75

74

59

66

48

43

44

45

76

113

112

72

4

PF1

6

PF2

SIGNAL

PIN #

BYPASS

CLKOUT

D0

7

PF3

A0

84

130

123

124

125

126

128

135

136

137

138

139

140

141

142

144

1

8

PF4

A1

85

9

PF5

A2

86

D1

10

11

12

14

15

17

18

20

21

22

23

30

27

28

31

32

114

115

116

117

119

83

132

133

PF6

A3

87

D2

PF7

A4

88

D3

RCLK0

RCLK1

RCLK2

RESET

RFS0

RFS1

RFS2

RD

A5

89

D4

A6

91

D5

A7

92

D6

A8

93

D7

A9

95

D8

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

ACK

BG

96

D9

97

D10

98

D11

RXD

TCK

TCLK0

TCLK1

TCLK2

TDI

99

D12

HALE

HCMS

HCIOMS

HRD

101

102

103

104

106

107

108

109

120

111

110

70

D13

D14

D15

2

DR0

DR1

DR2

DT0

DT1

DT2

EMU

HACK

HACK_P

60

HWR

67

IOMS

MS0

TDO

TFS0

TFS1

TFS2

TMR0

TMR1

TMR2

TMS

49

56

MS1

64

MS2

46

MS3

81

OPMODE

CLKIN

XTAL

BGH

BMODE0

26

24

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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September 2001

Table 26. 144-Lead LQFP

Pins (Alphabetically By

Signal) (Continued)

Table 27. 144-Lead LQFP

Pins (Numerically By Pin

Number (Continued)

Table 27. 144-Lead LQFP

Pins (Numerically By Pin

Number (Continued)

Table 27 lists the LQFP

pinout by pin number.

Table 27. 144-Lead LQFP

Pins (Numerically By Pin

Number

SIGNAL

PIN #

SIGNAL

PIN #

SIGNAL

PIN #

TRST

TXD

79

GND

HALE

HRD

HWR

GND

PF0

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

TFS0

DR0

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

SIGNAL

PIN #

53

D14

1

V_DDEXT

V_DDINT

GND

WR

13

RCLK0

RFS0

V_DDEXT

DT1

D15

2

25

HAD0

HAD1

GND

3

40

4

63

5

90

PF1

TCLK1

TFS1

DR1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAD8

V_DDEXT

HAD9

HAD10

GND

6

100

118

131

143

19

PF2

7

PF3

8

PF4

RCLK1

RFS1

BMODE0

BMODE1

BYPASS

RESET

TDO

TDI

9

PF5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V_DDEXT

PF6

58

82

PF7

127

5

TMR0

TMR1

TMR2

DT2

16

29

TMS

HAD11

HAD12

V_DDINT

HAD13

HAD14

HAD15

HA16

33

TCLK2

TFS2

DR2

GND

TCK

54

55

TRST

GND

EMU

V_DDINT

OPMODE

A0

77

RCLK2

RFS2

RXD

TXD

GND

DT0

80

94

105

129

134

121

HACK_P

V_DDEXT

HACK

HCMS

HCIOMS

A1

A2

TCLK0

V_DDINT

A3

A4

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

September 2001

Table 27. 144-Lead LQFP

Pins (Numerically By Pin

Number (Continued)

SIGNAL

PIN #

A5

89

V_DDEXT

A6

90

91

A7

92

A8

93

GND

A9

94

95

A10

A11

A12

A13

V_DDEXT

A14

A15

A16

A17

GND

A18

A19

A20

A21

BGH

BG

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

BR

BMS

IOMS

MS0

MS1

MS2

V_DDEXT

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Table 27. 144-Lead LQFP

Pins (Numerically By Pin

Number (Continued)

SIGNAL

PIN #

MS3

ACK

WR

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

RD

D0

D1

D2

D3

V_DDINT

D4

GND

CLKOUT

V_DDEXT

CLKIN

XTAL

GND

D5

D6

D7

D8

D9

D10

D11

D12

V_DDEXT

D13

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

Table 28. 144-Lead Mini-BGA Pins (Alphabetically By

Signal)

ADSP-2196 144-Lead Mini-BGA Pinout

Table 28 lists the mini-BGA pinout by signal name.

(Continued)

Table 28. 144-Lead Mini-BGA Pins (Alphabetically By

Signal)

SIGNAL

BALL #

BMS

A10

B9

BR

SIGNAL

BALL #

BYPASS

CLKIN

M11

A5

A0

J11

A1

H9

CLKOUT C6

A2

H10

G12

H11

G10

F12

G11

F10

F11

E12

E11

E10

E9

D0

D7

A7

C7

A6

B7

A4

C5

B5

D5

A3

C4

B4

C3

A2

B1

B2

L7

K9

L5

J6

A3

D1

A4

D2

A5

D3

A6

D4

A7

D5

A8

D6

A9

D7

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

ACK

BG

BGH

D8

D9

D10

D11

D12

D13

D14

D15

DR0

DR1

DR2

TCLK0

DT1

DT2

EMU

HACK

HACK_P

D11

D10

D12

C11

C12

B12

B11

A11

A8

L8

H4

J10

H3

G1

C10

B10

BMODE0 L10

BMODE1 L9

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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ADSP-2196

Table 28. 144-Lead Mini-BGA Pins (Alphabetically By

Signal)

(Continued)

SIGNAL

BALL #

SIGNAL

BALL #

HAD0

HAD1

HAD2

HAD3

HAD4

HAD5

HAD6

HAD7

HAD8

HAD9

HAD10

HAD11

HAD12

HAD14

HAD15

HAD13

HA16

C1

B3

C2

D1

D4

D3

D2

E1

E4

E2

F1

E3

F2

F3

G3

G2

H2

J1

PF2

M2

L2

PF3

PF4

M3

L3

PF5

PF6

K3

M4

K7

J9

PF7

RCLK0

RCLK1

RCLK2

RD

J5

B8

RESET

RFS0

RFS1

RFS2

RXD

TCK

DT0

L12

K8

M10

M6

K6

K11

H6

M9

K5

K12

L11

M8

J8

HALE

HCIOMS

HCMS

HRD

TCLK1

TCLK2

TDI

J3

H1

J2

TDO

TFS0

TFS1

TFS2

TMR0

TMR1

TMR2

TMS

TRST

TXD

HWR

K2

E8

D9

A9

C9

D8

IOMS

MS0

M5

K4

L4

MS1

MS2

MS3

J4

OPMODE H12

K10

J12

M7

PF0

PF1

K1

L1

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Table 28. 144-Lead Mini-BGA Pins (Alphabetically By

Signal)

Table 29 lists the mini-BGA pinout by ball number.

Table 29. 144-Lead Mini-BGA Pins (Numerically By

Ball Number)

(Continued)

SIGNAL

BALL #

SIGNAL

BALL #

V_DDINT

V_DDEXT

GND

WR

D6

F4

GND

D13

D9

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

B1

G9

J7

D5

E5

E6

F5

CLKIN

D3

D1

F6

ACK

MS1

BMS

A21

G7

G8

H7

H8

A1

A12

E7

F7

GND

D14

D15

HAD1

D11

D7

B2

B3

B4

F8

B5

F9

XTAL

D4

B6

G4

G5

G6

H5

L6

M1

M12

C8

B6

B7

RD

B8

BR

B9

BGH

A20

B10

B11

B12

C1

C2

C3

C4

C5

A19

HAD0

HAD2

D12

D10

D6

XTAL

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Table 29. 144-Lead Mini-BGA Pins (Numerically By

Ball Number) (Continued)

Table 29. 144-Lead Mini-BGA Pins (Numerically By

Ball Number) (Continued)

SIGNAL

BALL #

SIGNAL

BALL #

CLKOUT

D2

C6

C7

A10

E12

F1

HAD10

HAD12

HAD14

V_DDINT

V_DDEXT

GND

A8

WR

C8

F2

MS2

C9

F3

BG

C10

C11

C12

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

E1

F4

A17

F5

A18

F6

HAD3

HAD6

HAD5

HAD4

D8

F7

F8

F9

F10

F11

F12

G1

G2

G3

G4

G5

G6

G7

G8

G9

G10

G11

G12

H1

H2

H3

H4

H5

A9

V_DDINT

D0

A6

HACK_P

HAD13

HAD15

GND

V_DDEXT

V_DDINT

A5

MS3

MS0

A15

A14

A16

HAD7

HAD9

HAD11

HAD8

V_DDEXT

GND

IOMS

A13

E2

E3

E4

E5

A7

E6

A3

E7

HCMS

HA16

HACK

DT2

E8

E9

A12

E10

E11

A11

GND

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-2196

Table 29. 144-Lead Mini-BGA Pins (Numerically By

Ball Number) (Continued)

Table 29. 144-Lead Mini-BGA Pins (Numerically By

Ball Number) (Continued)

SIGNAL

BALL #

SIGNAL

BALL #

DT0

H6

H7

H8

H9

H10

H11

H12

J1

TDI

K12

L1

V_DDEXT

A1

PF1

PF3

L2

PF5

L3

A2

TMR1

DR2

L4

A4

L5

OPMODE

HALE

HRD

GND

DR0

L6

L7

J2

DT1

L8

HCIOMS

TMR2

RCLK2

TCLK0

V_DDINT

TFS1

RCLK1

EMU

A0

J3

BMODE1

BMODE0

TDO

RESET

GND

PF2

L9

J4

L10

L11

L12

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

J5

J6

J7

J8

J9

PF4

J10

J11

J12

K1

K2

K3

K4

K5

K6

K7

K8

K9

K10

K11

PF7

TFS2

RFS2

TXD

TFS0

TCLK1

RFS1

BYPASS

GND

TRST

PF0

HWR

PF6

TMR0

TCLK2

RXD

RCLK0

RFS0

DR1

TMS

TCK

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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OUTLINE DIMENSIONS

September 2001

ADSP-2196

.

144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)

ꢀꢀꢄꢄꢐꢌꢌꢀ%6&ꢀ64ꢀꢀ

ꢅꢐꢈꢌꢀ0$;

ꢀꢀꢄꢌꢐꢌꢌꢀ%6&ꢀ64ꢀꢀ

ꢌꢐꢎꢍ

ꢌꢐꢈꢌ

ꢌꢐꢉꢍ

ꢅꢌꢋ

ꢅꢉꢉ

ꢅ

ꢅꢌꢆ

6($7,1*

3/$1(

ꢌꢐꢄꢎ

ꢌꢐꢄꢄ

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723ꢀ9,(:

ꢁ3,16ꢀ'2:1ꢃ

7<3

ꢎꢂ

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This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

67

35(/,0,1$5<ꢀ7(&+1,&$/ꢀ'$7$

For current information contact Analog Devices at 800/262-5643

ORDERING GUIDE

September 2001

ADSP-2196

1, 2

Part Number

Ambient Temperature Range Instruction Rate On-Chip SRAM Operating Voltage

ADSP-2196MKST-160X 0ºC to 70ºC

ADSP-2196MBST-140X -40ºC to 85ºC

ADSP-2196MKCA-160X 0ºC to 70ºC

ADSP-2196MBCA-140X -40ºC to 85ºC

160 MHz

140 MHz

160 MHz

140 MHz

1.3M bit

2.5 Int./3.3 Ext. V

¹ST = Plastic Thin Quad Flatpack (LQFP).

²CA = Chip array package

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

68


型号：	ADSP-2196MBST-140X
厂家：	ADI
描述：	DSP Microcomputer 微电脑DSP 微控制器和处理器外围集成电路数字信号处理器电脑时钟
文件：	总68页 (文件大小：885K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-2196MBST-140X [ADI]

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