ADSP-21990BCA_技术文档

Mixed-Signal DSP Controller

ADSP-21990

a

FEATURES

ADSP-2199x, 16-bit, fixed-point DSP core with up to 160

MIPS sustained performance

Dual 16-bit auxiliary PWM outputs

16 general-purpose flag I/O pins

8K words of on-chip RAM, configured as 4K words on-chip,

24-bit program RAM and 4K words on-chip, 16-bit

data RAM

3 programmable 32-bit interval timers

SPI communications port with master or slave operation

Synchronous serial communications port (SPORT) capable of

software UART emulation

External memory interface

Dedicated memory DMA controller for data/instruction

transfer between internal/external memory

Programmable PLL and flexible clock generation circuitry

enables full speed operation from low speed input clocks

IEEE JTAG Standard 1149.1 test access port supports on-chip

emulation and system debugging

8-channel, 14-bit analog-to-digital converter system, with up

to 20 MSPS sampling rate (at 160 MHz core clock rate)

3-phase, 16-bit, center-based PWM generation unit with 12.5

ns resolution at 160 MHz core clock (CCLK) rate

Dedicated 32-bit encoder interface unit with companion

encoder event timer

Integrated watchdog timer

Dedicated peripheral interrupt controller with software

priority control

Multiple boot modes

Precision 1.0 V voltage reference

Integrated power-on-reset (POR) generator

Flexible power management with selectable power-down

and idle modes

2.5 V internal operation with 3.3 V I/O

Operating temperature range of –40ЊC to +85ЊC

196-ball CSP_BGA and 176-lead LQFP package

CLOCK

GENERATOR/PLL

4k

؋

16

DM RAM

4k

؋

24

PM ROM

4k

؋

24

PM RAM

JTAG

TEST AND

ADSP-219x

EMULATION

DSP CORE

ADDRESS

EXTERNAL

MEMORY

INTERFACE

(EMI)

DATA

I/O

BUS

PM ADDRESS/DATA

DM ADDRESS/DATA

CONTROL

I/O REGISTERS

MEMORY DMA

CONTROLLER

SPI

SPORT

PWM

GENERATION

UNIT

ENCODER

INTERFACE

UNIT

(AND EET)

TIMER 0

ADC

CONTROL

PIPELINE

FLASH ADC

INTERRUPT

CONTROLLER

(ICNTL)

AUXILIARY

PWM

UNIT

WATCHDOG

TIMER

TIMER 1

TIMER 2

FLAG

I/O

POR

VREF

Figure 1. Functional Block Diagram

Rev. A

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ADSP-21990

TABLE OF CONTENTS

General Description ................................................. 3

DSP Core Architecture ........................................... 3

Memory Architecture ............................................ 5

Bus Request and Bus Grant ..................................... 6

DMA Controller ................................................... 6

DSP Peripherals Architecture .................................. 7

Serial Peripheral Interface (SPI) Port ......................... 7

DSP Serial Port (SPORT) ........................................ 8

Analog-to-Digital Conversion System ........................ 8

Voltage Reference ................................................. 9

PWM Generation Unit ........................................... 9

Auxiliary PWM Generation Unit .............................. 9

Encoder Interface Unit ........................................... 9

Flag I/O (FIO) Peripheral Unit ............................... 10

Watchdog Timer ................................................ 10

General-Purpose Timers ....................................... 10

Interrupts ......................................................... 10

Peripheral Interrupt Controller .............................. 11

Low Power Operation .......................................... 12

Clock Signals ...................................................... 12

Reset and Power-On Reset (POR) ........................... 13

Power Supplies ................................................... 13

Booting Modes ................................................... 13

Instruction Set Description .................................... 14

Development Tools .............................................. 14

Designing an Emulator-Compatible DSP Board .......... 15

Additional Information ........................................ 15

Pin Function Descriptions ........................................ 16

Specifications ........................................................ 19

Absolute Maximum Ratings ................................... 24

ESD Caution ...................................................... 24

Timing Specifications ........................................... 24

Power Dissipation ............................................... 40

Test Conditions .................................................. 40

Pin Configurations ................................................. 42

Outline Dimensions ................................................ 48

Ordering Guide ..................................................... 49

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Added RoHS part number to Ordering Guide .............. 49

Rev. A

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ADSP-21990

GENERAL DESCRIPTION

The ADSP-21990 is a mixed-signal DSP controller based on the

ADSP-2199x DSP core, suitable for a variety of high perfor-

mance industrial motor control and signal processing

applications that require the combination of a high performance

DSP and the mixed-signal integration of embedded control

peripherals such as analog-to-digital conversion. Target appli-

cations include: industrial motor drives, uninterruptible power

supplies, optical networking control, data acquisition systems,

test and measurement systems, and portable instrumentation.

• Decrement the timers.

• Operate the embedded control peripherals (ADC, PWM,

EIU, etc.).

DSP CORE ARCHITECTURE

• 6.25 ns instruction cycle time (internal), for up to

160 MIPS sustained performance (6.67 ns instruction cycle

time for 150 MIPS sustained performance).

• ADSP-218x family code compatible with the same easy to

use algebraic syntax.

The ADSP-21990 integrates the fixed-point ADSP-2199x fam-

ily-based architecture with a serial port, an SPI-compatible port,

a DMA controller, three programmable timers, general-purpose

programmable flag pins, extensive interrupt capabilities, on-

chip program and data memory spaces, and a complete set of

embedded control peripherals that permits fast motor control

and signal processing in a highly integrated environment.

• Single cycle instruction execution.

• Up to 1M words of addressable memory space with 24 bits

of addressing width.

• Dual-purpose program memory for both instruction and

data storage.

The ADSP-21990 architecture is code compatible with previous

ADSP-217xx based ADMCxxx products. Although the architec-

tures are compatible, the ADSP-21990, with ADSP-2199x

architecture, has a number of enhancements over earlier archi-

tectures. The enhancements to computational units, data

address generators, and program sequencer make the

ADSP-21990 more flexible and easier to program than the pre-

vious ADSP-21xx embedded DSPs.

• Fully transparent instruction cache allows dual operand

fetches in every instruction cycle.

• Unified memory space permits flexible address generation,

using two independent DAG units.

• Independent ALU, multiplier/accumulator, and barrel

shifter computational units with dual 40-bit accumulators.

• Single cycle context switch between two sets of computa-

tional and DAG registers.

Indirect addressing options provide addressing flexibility—pre-

modify with no update, pre- and post-modify by an immediate

8-bit, twos complement value and base address registers for eas-

ier implementation of circular buffering.

• Parallel execution of computation and memory

instructions.

• Pipelined architecture supports efficient code execution at

speeds up to 160 MIPS.

The ADSP-21990 integrates 8K words of on-chip memory con-

figured as 4K words (24-bit) of program RAM, and 4K words

(16-bit) of data RAM.

• Register file computations with all nonconditional, non-

parallel computational instructions.

Fabricated in a high speed, low power, CMOS process, the

ADSP-21990 operates with a 6.25 ns instruction cycle time for a

160 MHz CCLK and with a 6.67 ns instruction cycle time for a

150 MHz CCLK.

• Powerful program sequencer provides zero overhead loop-

ing and conditional instruction execution.

• Architectural enhancements for compiled C code

efficiency.

The flexible architecture and comprehensive instruction set of

the ADSP-21990 support multiple operations in parallel. For

example, in one processor cycle, the ADSP-21990 can:

• Architecture enhancements beyond ADSP-218xx family

are supported with instruction set extensions for added

registers, ports, and peripherals.

• Generate an address for the next instruction fetch.

• Fetch the next instruction.

The clock generator module of the ADSP-21990 includes clock

control logic that allows the user to select and change the main

clock frequency. The module generates two output clocks: the

DSP core clock, CCLK; and the peripheral clock, HCLK. CCLK

can sustain clock values of up to 160 MHz, while HCLK can be

equal to CCLK or CCLK/2 for values up to a maximum 80 MHz

peripheral clock at the 160 MHz CCLK rate.

• Perform one or two data moves.

• Update one or two data address pointers.

• Perform a computational operation.

These operations take place while the processor continues to:

• Receive and transmit data through the serial port.

• Receive or transmit data over the SPI port.

The ADSP-21990 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every single word instruction can be executed in a

single processor cycle. The ADSP-21990 assembly language uses

an algebraic syntax for ease of coding and readability. A com-

prehensive set of development tools supports program

development.

• Access external memory through the external memory

interface.

Rev. A

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ADSP-21990

INTERNAL MEMORY

FOUR INDEPENDENT BLOCKS

DATA

ADDRESS

24 BIT

16 BIT

ADSP-219x DSP CORE

JTAG

TEST AND

EMULATION

6

ADDRESS

CACHE

64

؋

24-BIT

16 BIT

DAG2

4

؋

4

؋

16

DAG1

4

؋

4

؋

16

PROGRAM

SEQUENCER

EXTERNAL PORT

PM ADDRESS BUS

24

I/O ADDRESS

ADDR BUS

MUX

18

20

DM ADDRESS BUS

PX

24

DMA CONNECT

DMA ADDRESS

24

DATA BUS

MUX

DMA DATA

PM DATA BUS

DM DATA BUS

I/O DATA

24

16

DATA

REGISTER

FILE

I/O PROCESSOR

INPUT

REGISTERS

RESULT

I/O REGISTERS

(MEMORY-MAPPED)

EMBEDDED

CONTROL

PERIPHERALS

AND

COMMUNICATIONS

PORTS

REGISTERS

16

؋

16-BIT

BARREL

SHIFTER

MULT

ALU

CONTROL

STATUS

BUFFERS

DMA CONTROLLER

3

SYSTEM INTERRUPT

CONTROLLER

TIMERS

(3)

PROGRAMMABLE

FLAGS (16)

Figure 2. Block Diagram

The block diagram (Figure 2) shows the architecture of the

embedded ADSP-21xx core. It contains three independent com-

putational units: the ALU, the multiplier/accumulator (MAC),

and the shifter. The computational units process 16-bit data

from the register file and have provisions to support multipreci-

sion computations. The ALU performs a standard set of

arithmetic and logic operations; division primitives are also sup-

ported. The MAC performs single cycle multiply, multiply/add,

and multiply/subtract operations. The MAC has two 40-bit

accumulators, which help with overflow. The shifter performs

logical and arithmetic shifts, normalization, denormalization,

and derive exponent operations. The shifter can be used to effi-

ciently implement numeric format control, including

counters and loop stacks, the ADSP-21990 executes looped code

with zero overhead; no explicit jump instructions are required

to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four 16-bit

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is pre- or post-modified by the value of

one of four possible modify registers. A length value and base

address may be associated with each pointer to implement auto-

matic modulo addressing for circular buffers. Page registers in

the DAGs allow circular addressing within 64K word bound-

aries of each of the 256 memory pages, but these buffers may not

cross page boundaries. Secondary registers duplicate all the pri-

mary registers in the DAGs; switching between primary and

secondary registers provides a fast context switch.

multiword and block floating-point representations.

Register usage rules influence placement of input and results

within the computational units. For most operations, the com-

putational unit data registers act as a data register file,

permitting any input or result register to provide input to any

unit for a computation. For feedback operations, the computa-

tional units let the output (result) of any unit be input to any

unit on the next cycle. For conditional or multifunction instruc-

tions, there are restrictions on which data registers may provide

inputs or receive results from each computational unit. For

more information, see the ADSP-2199x DSP Instruction Set

Reference.

Efficient data transfer in the core is achieved with the use of

internal buses:

• Program memory address (PMA) bus

• Program memory data (PMD) bus

• Data memory address (DMA) bus

• Data memory data (DMD) bus

• Direct memory access address bus

• Direct memory access data bus

A powerful program sequencer controls the flow of instruction

execution. The sequencer supports conditional jumps, subrou-

tine calls, and low interrupt overhead. With internal loop

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ADSP-21990

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Boot memory space and I/O memory space also share the

external buses.

0x00 0000

BLOCK 0: 4K

؋

24-BIT RAM

0x00 0FFF

0x00 1000

RESERVED (28K)

PAGE 0 (64K) ON-CHIP

0x00 7FFF

0x00 8000

(0 WAIT STATE)

BLOCK 1: 4K

؋

16-BIT RAM

0x00 8FFF

0x00 9000

Program memory can store both instructions and data, permit-

ting the ADSP-21990 to fetch two operands in a single cycle, one

from program memory and one from data memory. The dual

memory buses also let the embedded ADSP-21xx core fetch an

operand from data memory and the next instruction from pro-

gram memory in a single cycle.

RESERVED (28K)

0x00 FFFF

0x01 0000

PAGES 1 TO 63

BANK 0 (OFF-CHIP)

EXTERNAL MEMORY

(4M – 64K)

MS0

0x40 0000

0x80 0000

EXTERNAL MEMORY

PAGES 64 TO 127

BANK 1 (OFF-CHIP)

MS1

MS2

MS3

MEMORY ARCHITECTURE

PAGES 128 TO 191

BANK 2 (OFF-CHIP)

The ADSP-21990 provides 8K words of on-chip SRAM mem-

ory. This memory is divided into two blocks: a 4K × 24-bit

(block 0) and a 4K × 16-bit (block 1). In addition, the

ADSP-21990 provides a 4K × 24-bit block of program memory

boot ROM (that is reserved by ADI for boot load routines). The

memory map of the ADSP-21990 is illustrated in Figure 2.

0xC0 0000

0xFF 0000

PAGES 192 TO 254

BANK 0 (OFF-CHIP)

EXTERNAL MEMORY

(4M – 64K)

BLOCK 2: 4K

؋

24-BIT

PAGE 255

(ON-CHIP)

PM ROM

0xFF 0FFF

0xFF 1000

UNUSED ON-CHIP

MEMORY (60K)

As shown in Figure 2, the two internal memory RAM blocks

reside in memory Page 0. The entire DSP memory map consists

of 256 pages (Pages 0 to 255), and each page is 64K words long.

External memory space consists of four memory banks

0xFF FFFF

Figure 3. Core Memory Map at Reset

(Banks3–0) and supports a wide variety of memory devices.

Each bank is selectable using unique memory select lines

(MS3–0) and has configurable page boundaries, wait states, and

wait state modes. The 4K words of on-chip boot ROM populates

the top of Page 255, while the remaining 254 pages are address-

able off-chip. I/O memory pages differ from external memory in

that they are 1K word long, and the external I/O pages have

their own select pin (IOMS). Pages 31–0 of I/O memory space

reside on-chip and contain the configuration registers for the

peripherals. Both the ADSP-2199x core and DMA capable

peripherals can access the entire memory map of the DSP.

must set DMPG1 accordingly, when accessing data vari-

ables in external memory. A “C” program macro is

provided for setting this register.

• The program sequencer generates the addresses for

instruction fetches. For relative addressing instructions, the

program sequencer bases addresses for relative jumps, calls,

and loops on the 24-bit program counter (PC). In direct

addressing instructions (two word instructions), the

instruction provides an immediate 24-bit address value.

The PC allows linear addressing of the full 24-bit

address range.

NOTE: The physical external memory addresses are limited by

20 address lines, and are determined by the external data width

and packing of the external memory space. The strobe signals

(MS3-0) can be programmed to allow the user to change start-

ing page addresses at run time.

• For indirect jumps and calls that use a 16-bit DAG address

register for part of the branch address, the program

sequencer relies on an 8-bit indirect jump page (IJPG) reg-

ister to supply the most significant eight address bits.

Before a cross page jump or call, the program must set the

program sequencer IJPG register to the appropriate mem-

ory page.

Internal (On-Chip) Memory

The ADSP-21990 unified program and data memory space con-

sists of 16M locations that are accessible through two 24-bit

address buses, the PMA and DMA buses. The DSP uses slightly

different mechanisms to generate a 24-bit address for each bus.

The DSP has three functions that support access to the full

memory map.

The ADSP-21990 has 4K words of on-chip ROM that holds

boot routines. The DSP starts executing instructions from the

on-chip boot ROM, which starts the boot process. For more

information, see Booting Modes on Page 13. The on-chip boot

ROM is located on Page 255 in the DSP memory space map,

starting at address 0xFF0000.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG index

(address) registers are 16 bits wide and hold the lower

16 bits of the address, each of the DAGs has its own 8-bit

page register (DMPGx) to hold the most significant eight

address bits. Before a DAG generates an address, the pro-

gram must set the DAG DMPGx register to the appropriate

memory page. The DMPG1 register is also used as a page

register when accessing external memory. The program

External (Off-Chip) Memory

Each of the ADSP-21990 off-chip memory spaces has a separate

control register, so applications can configure unique access

parameters for each space. The access parameters include read

and write wait counts, wait state completion mode, I/O clock

divide ratio, write hold time extension, strobe polarity, and data

bus width. The core clock and peripheral clock ratios influence

Rev. A

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ADSP-21990

the external memory access strobe widths. For more informa-

tion, see Clock Signals on Page 12. The off-chip memory

spaces are:

access the DSP off-chip boot memory space. After reset, the

DSP always starts executing instructions from the on-chip

boot ROM.

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

0x01 0000

OFF-CHIP

All of the above off-chip memory spaces are accessible through

the external port, which can be configured for 8-bit or 16-bit

data widths.

BOOT MEMORY

PAGES 1 TO 254

16-BITS

64K WORDS/PAGE

External Memory Space

0xFE 0000

External memory space consists of four memory banks. These

banks can contain a configurable number of 64 K word pages.

At reset, the page boundaries for external memory have Bank0

containing Pages 1 to 63, Bank1 containing Pages 64 to 127,

Bank2 containing Pages 128 to 191, and Bank3 containing Pages

192 to 254. The MS3-0 memory bank pins select Banks 3-0,

respectively. Both the ADSP-2199x core and DMA capable

peripherals can access the DSP external memory space.

Figure 5. Boot Memory Map

BUS REQUEST AND BUS GRANT

The ADSP-21990 can relinquish control of the data and address

buses to an external device. When the external device requires

access to the bus, it asserts the bus request (BR) signal. The (BR)

signal is arbitrated with core and peripheral requests. External

bus requests have the lowest priority. If no other internal

request is pending, the external bus request will be granted. Due

to synchronizer and arbitration delays, bus grants will be pro-

vided with a minimum of three peripheral clock delays. The

ADSP-21990 will respond to the bus grant by:

All accesses to external memory are managed by the external

memory interface unit (EMI).

I/O Memory Space

The ADSP-21990 supports an additional external memory

called I/O memory space. The I/O space consists of 256 pages,

each containing 1024 addresses. This space is designed to sup-

port simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data registers.

The first 32K addresses (I/O Pages 0 to 31) are reserved for

on-chip peripherals. The upper 224K addresses (I/O Pages 32 to

255) are available for external peripheral devices. External I/O

pages have their own select pin (IOMS). The DSP instruction set

provides instructions for accessing I/O space.

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

The ADSP-21990 will halt program execution if the bus is

granted to an external device and an instruction fetch or data

read/write request is made to external general-purpose or

peripheral memory spaces. If an instruction requires two exter-

nal memory read accesses, the bus will not be granted between

the two accesses. If an instruction requires an external memory

read and an external memory write access, the bus may be

granted between the two accesses. The external memory inter-

face can be configured so that the core will have exclusive use of

the interface. DMA and bus requests will be granted. When the

external device releases BR, the DSP releases BG and continues

program execution from the point at which it stopped.

0x00::0x000

ON-CHIP

PAGES 0 TO 31

PERIPHERALS

16-BITS

1024 WORDS/PAGE

2 PERIPHERALS/PAGE

0x1F::0x3FF

0x20::0x000

The bus request feature operates at all times, even while the DSP

is booting and RESET is active.

OFF-CHIP

PERIPHERALS

16-BITS

PAGES 32 TO 255

The ADSP-21990 asserts the BGH pin when it is ready to start

another external port access, but is held off because the bus was

previously granted. This mechanism can be extended to define

more complex arbitration protocols for implementing more

elaborate multimaster systems.

1024 WORDS/PAGE

0xFF::0x3FF

DMA CONTROLLER

Figure 4. I/O Memory Map

The ADSP-21990 has a DMA controller that supports auto-

mated data transfers with minimal overhead for the DSP core.

Cycle stealing DMA transfers can occur between the

ADSP-21990 internal memory and any of its DMA capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA capable peripherals and external

Boot Memory Space

Boot memory space consists of one off-chip bank with 254

pages. The BMS memory bank pin selects boot memory space.

Both the ADSP-2199x core and DMA capable peripherals can

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ADSP-21990

devices connected to the external memory interface. DMA

capable peripherals include the SPORT and SPI ports, and ADC

control module. Each individual DMA capable peripheral has a

dedicated DMA channel. To describe each DMA sequence, the

DMA controller uses a set of parameters—called a DMA

descriptor. When successive DMA sequences are needed, these

DMA descriptors can be linked or chained together, so the com-

pletion of one DMA sequence autoinitiates and starts the next

sequence. DMA sequences do not contend for bus access with

the DSP core, instead DMAs “steal” cycles to access memory.

The embedded ADSP-21xx core can respond to up to 17 inter-

rupts at any given time: three internal (stack, emulator kernel,

and power down), two external (emulator and reset), and 12

user-defined (peripherals) interrupts. Programmers assign each

of the 32 peripheral interrupt requests to one of the 12 user

defined interrupts. These assignments determine the priority of

each peripheral for interrupt service.

The following sections provide a functional overview of the

ADSP-21990 peripherals.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

All DMA transfers use the DMA bus shown in Figure 2 on

Page 4. Because all of the peripherals use the same bus, arbitra-

tion for DMA bus access is needed. The arbitration for DMA

bus access appears in Table 1.

The serial peripheral interface (SPI) port provides functionality

for a generic configurable serial port interface based on the SPI

standard, which enables the DSP to communicate with multiple

SPI-compatible devices. Key features of the SPI port are:

Table 1. I/O Bus Arbitration Priority

• Interface to host microcontroller or serial EEPROM.

DMA Bus Master

Arbitration Priority

• Master or slave operation (3-wire interface MISO, MOSI,

SCK).

SPORT Receive DMA

SPORT Transmit DMA

ADC Control DMA

SPI Receive/Transmit DMA

Memory DMA

0—Highest

1

• Data rates to HCLK،4 (16-bit baud rate selector).

• 8- or 16-bit transfer.

2

3

• Programmable clock phase and polarity.

• Broadcast Mode-1 master, multiple slaves.

• DMA capability and dedicated interrupts.

• PF0 can be used as slave select input line.

• PF1–PF7 can be used as external slave select output.

4—Lowest

DSP PERIPHERALS ARCHITECTURE

The ADSP-21990 contains a number of special purpose, embed-

ded control peripherals, which can be seen in the functional

block diagram on Page 1. The ADSP-21990 contains a high per-

formance, 8-channel, 14-bit ADC system with dual-channel

simultaneous sampling ability across four pairs of inputs. An

internal precision voltage reference is also available as part of

the ADC system. In addition, a 3-phase, 16-bit, center-based

PWM generation unit can be used to produce high accuracy

PWM signals with minimal processor overhead.

SPI is a 3-wire interface consisting of two data pins (MOSI and

MISO), one clock pin (SCK), and a single slave select input

(SPISS) that is multiplexed with the PF0 flag I/O line and seven

slave select outputs (SPISEL1 to SPISEL7) that are multiplexed

with the PF1 to PF7 flag I/O lines. The SPISS input is used to

select the ADSP-21990 as a slave to an external master. The

SPISEL1 to SPISEL7 outputs can be used by the ADSP-21990

(acting as a master) to select/enable up to seven external slaves

in a multidevice SPI configuration. In a multimaster or a multi-

device configuration, all MOSI pins are tied together, all MISO

pins are tied together, and all SCK pins are tied together.

The ADSP-21990 also contains a flexible incremental encoder

interface unit for position sensor feedback; two adjustable fre-

quency auxiliary PWM outputs, 16 lines of digital I/O; a

16-bit watchdog timer; three general-purpose timers, and an

interrupt controller that manages all peripheral interrupts.

Finally, the ADSP-21990 contains an integrated power-on-reset

(POR) circuit that can be used to generate the required reset sig-

nal for the device on power-on.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on the serial data

line. The serial clock line synchronizes the shifting and sam-

pling of data on the serial data line.

The ADSP-21990 has an external memory interface that is

shared by the DSP core, the DMA controller, and DMA capable

peripherals, which include the ADC, SPORT, and SPI commu-

nication ports. The external port consists of a 16-bit data bus, a

20-bit address bus, and control signals. The data bus is config-

urable to provide an 8- or 16-bit interface to external memory.

Support for word packing lets the DSP access 16- or 24-bit

words from external memory regardless of the external data

bus width.

In master mode, the DSP core performs the following sequence

to set up and initiate SPI transfers:

• Enables and configures the SPI port operation (data size

and transfer format).

• Selects the target SPI slave with the SPISELx output pin

(reconfigured programmable flag pin).

• Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

The memory DMA controller lets the ADSP-21990 move data

and instructions from between memory spaces: internal-to-

external, internal-to-internal, and external-to-external. On-chip

peripherals can also use this controller for DMA transfers.

• Enables the SPI DMA engine and specifies transfer direc-

tion (optional in DMA mode only).

• In nonDMA mode only, reads or writes the SPI port

receive or transmit data buffer.

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ADSP-21990

The SCK line generates the programmed clock pulses for simul-

taneously shifting data out on MOSI and shifting data in on

MISO. In DMA mode only, transfers continue until the SPI

DMA word count transitions from 1 to 0.

• Direct memory access with single cycle overhead: using the

built-in DMA master, the SPORT can automatically receive

and/or transmit multiple memory buffers of data with an

overhead of only one DSP cycle per data-word. The on-

chip DSP via a linked list of memory space resident DMA

descriptor blocks can configure transfers between the

SPORT and memory space. This chained list can be

dynamically allocated and updated.

In slave mode, the DSP core performs the following sequence to

set up the SPI port to receive data from a master transmitter:

• Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size and

transfer format) SPI transmitter.

• Interrupts: Each SPORT section (receive and transmit)

generates an interrupt upon completing a data-word trans-

fer, or after transferring an entire buffer or buffers if DMA

is used.

• Defines and generates a receive DMA descriptor in Page 0

of memory space to interrupt at the end of the data transfer

(optional in DMA mode only).

• Multichannel capability: The SPORT can receive and trans-

mit data selectively from channels of a serial bit stream that

is time division multiplexed into up to 128 channels. This is

especially useful for T1 interfaces or as a network commu-

nication scheme for multiple processors. The SPORTs also

support T1 and E1 carrier systems.

• Enables the SPI DMA engine for a receive access (optional

in DMA mode only).

• Starts receiving the data on the appropriate SCK edges after

receiving an SPI chip select on the SPISS input pin (recon-

figured programmable flag pin) from a master.

• Each SPORT channel (Tx and Rx) supports a DMA buffer

of up to eight, 16-bit transfers.

In DMA mode only, reception continues until the SPI DMA

word count transitions from 1 to 0. The DSP core could con-

tinue, by queuing up the next DMA descriptor.

• The SPORT operates at a frequency of up to one-half the

clock frequency of the HCLK.

Slave mode transmit operation is similar, except that the DSP

core specifies the data buffer in memory space from which to

transmit data, generates and relinquishes control of the transmit

DMA descriptor, and begins filling the SPI port data buffer. If

the SPI controller is not ready on time to transmit, it can trans-

mit a “zero” word.

• The SPORT is capable of UART software emulation.

ANALOG-TO-DIGITAL CONVERSION SYSTEM

The ADSP-21990 contains a fast, high accuracy, multiple input

analog-to-digital conversion system with simultaneous sam-

pling capabilities. This analog-to-digital conversion system

permits the fast, accurate conversion of analog signals needed in

high performance embedded systems. Key features of the ADC

system are:

DSP SERIAL PORT (SPORT)

The ADSP-21990 incorporates a complete synchronous serial

port (SPORT) for serial and multiprocessor communications.

The SPORT supports the following features:

• 14-bit pipeline (6-stage pipeline) flash analog-to-digital

converter.

• Bidirectional: The SPORT has independent transmit and

receive sections.

• 8 dedicated analog inputs.

• Double buffered: The SPORT section (both receive and

transmit) has a data register for transferring data words to

and from other parts of the processor and a register for

shifting data in or out. The double buffering provides addi-

tional time to service the SPORT.

• Dual-channel simultaneous sampling capability.

• Programmable ADC clock rate to maximum of HCLK،4.

• First channel ADC data valid approximately 375 ns after

CONVST (at 20 MSPS).

• Clocking: The SPORT can use an external serial clock or

generate its own in a wide range of frequencies down

to 0 Hz.

• All 8 inputs converted in approximately 725 ns (at

20 MSPS).

• 2.0 V peak-to-peak input voltage range.

• Multiple convert start sources.

• Word length: Each SPORT section supports serial data

word lengths from three to 16 bits that can be transferred

either MSB first or LSB first.

• Internal or external voltage reference.

• Out of range detection.

• Framing: Each SPORT section (receive and transmit) can

operate with or without frame synchronization signals for

each data-word; with internally generated or externally

generated frame signals; with active high or active low

frame signals; with either of two pulse widths and frame

signal timing.

• DMA capable transfers from ADC to memory.

The ADC system is based on a pipeline flash converter core, and

contains dual input sample-and-hold amplifiers so that simulta-

neous sampling of two input signals is supported. The ADC

system provides an analog input voltage range of 2.0 V p-p and

provides 14-bit performance with a clock rate of up to

• Companding in hardware: Each SPORT section can per-

form A law and μ law companding according to CCITT

recommendation G.711.

HCLK ، 4. The ADC system can be programmed to operate at

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a clock rate that is programmable from HCLK ، 4 to

HCLK ، 30, to a maximum of 20 MHz (at 160 MHz

CCLK rate).

The six PWM output signals consist of three high side drive pins

(AH, BH, and CH) and three low side drive signals pins (AL, BL,

and CL). The polarity of the generated PWM signals may be set

via hardware by the PWMPOL input pin, so that either active

HI or active LO PWM patterns can be produced.

The ADC input structure supports eight independent analog

inputs; four of which are multiplexed into one sample-and-hold

amplifier (A_SHA) and four of which are multiplexed into the

other sample-and-hold amplifier (B_SHA).

The switching frequency of the generated PWM patterns is pro-

grammable using the 16-bit PWMTM register. The PWM

generator is capable of operating in two distinct modes, single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period,

so that the resultant PWM patterns are symmetrical about the

midpoint of the PWM period. In the double update mode, a sec-

ond updating of the PWM registers is implemented at the

midpoint of the PWM period. In this mode, it is possible to pro-

duce asymmetrical PWM patterns. that produce lower

At the 20 MHz sampling rate, the first data value is valid

approximately 375 ns after the convert start command. All eight

channels are converted in approximately 725 ns.

The core of the ADSP-21990 provides 14-bit data such that the

stored data values in the ADC data registers are 14 bits wide.

VOLTAGE REFERENCE

The ADSP-21990 contains an on-board band gap reference that

can be used to provide a precise 1.0 V output for use by the

analog-to-digital system and externally on the VREF pin for

biasing and level shifting functions. Additionally, the ADSP-

21990 may be configured to operate with an external reference

applied to the VREF pin, if required.

harmonic distortion in 3-phase PWM inverters.

AUXILIARY PWM GENERATION UNIT

Key features of the auxiliary PWM generation unit are:

• 16-bit, programmable frequency, programmable duty cycle

PWM outputs.

PWM GENERATION UNIT

• Independent or offset operating modes.

Key features of the 3-phase PWM generation unit are:

• 16-bit, center-based PWM generation unit.

• Double buffered control of duty cycle and period registers.

• Separate auxiliary PWM synchronization signal and associ-

ated interrupt (can be used to trigger ADC convert start).

• Programmable PWM pulse width, with resolutions to

12.5 ns (at 80 MHz HCLK rate).

• Separate auxiliary PWM shutdown signal (AUXTRIP).

• Single/double update modes.

The ADSP-21990 integrates a 2-channel, 16-bit, auxiliary PWM

output unit that can be programmed with variable frequency,

variable duty cycle values and may operate in two different

modes, independent mode or offset mode. In independent

mode, the two auxiliary PWM generators are completely inde-

pendent and separate switching frequencies and duty cycles may

be programmed for each auxiliary PWM output. In offset mode

the switching frequency of the two signals on the AUX0 and

AUX1 pins is identical. Bit 4 of the AUXCTRL register places

the auxiliary PWM channel pair in independent or offset mode.

• Programmable dead time and switching frequency.

• Twos complement implementation permits smooth transi-

tion into full ON and full OFF states.

• Possibility to synchronize the PWM generation to an exter-

nal synchronization.

• Special provisions for BDCM operation (crossover and

output enable functions).

• Wide variety of special switched reluctance (SR) operating

modes.

The auxiliary PWM generation unit provides two chip output

pins, AUX0 and AUX1 (on which the switching signals appear)

and one chip input pin, AUXTRIP, which can be used to shut

down the switching signals—for example, in a fault condition.

• Output polarity and clock gating control.

• Dedicated asynchronous PWM shutdown signal.

• Multiple shutdown sources, independently for each unit.

ENCODER INTERFACE UNIT

The ADSP-21990 integrates a flexible and programmable,

3-phase PWM waveform generator that can be programmed to

generate the required switching patterns to drive a 3-phase volt-

age source inverter for ac induction (ACIM) or permanent

magnet synchronous (PMSM) motor control. In addition, the

PWM block contains special functions that considerably sim-

plify the generation of the required PWM switching patterns for

control of the electronically commutated motor (ECM) or

brushless dc motor (BDCM). Tying a dedicated pin, PWMSR,

to GND, enables a special mode, for switched reluctance

motors (SRM).

The ADSP-21990 incorporates a powerful encoder interface

block to incremental shaft encoders that are often used for posi-

tion feedback in high performance motion control systems.

• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).

• Programmable filtering of all encoder input signals.

• 32-bit encoder counter.

• Variety of hardware and software reset modes.

• Two registration inputs to latch EIU count value with cor-

responding registration interrupt.

• Status of A/B signals latched with reading of EIU

count value.

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• Alternative frequency and direction mode.

• Single north marker mode.

FLAG I/O (FIO) PERIPHERAL UNIT

The FIO module is a generic parallel I/O interface that supports

16 bidirectional multifunction flags or general-purpose digital

I/O signals (PF15–0).

• Count error monitor function with dedicated error

interrupt.

All 16 FLAG bits can be individually configured as an input or

output based on the content of the direction (DIR) register, and

can also be used as an interrupt source for one of two FIO inter-

rupts. When configured as input, the input signal can be

programmed to set the FLAG on either a level (level sensitive

input/interrupt) or an edge (edge sensitive input/interrupt).

• Dedicated 16-bit loop timer with dedicated interrupt.

• Companion encoder event (1⁄T) timer unit.

The encoder interface unit (EIU) includes a 32-bit quadrature

up-/downcounter, programmable input noise filtering of the

encoder input signals and the zero markers, and has four dedi-

cated chip pins. The quadrature encoder signals are applied at

the EIA and EIB pins. Alternatively, a frequency and direction

set of inputs may be applied to the EIA and EIB pins. In addi-

tion, two north marker/strobe inputs are provided on pins EIZ

and EIS. These inputs may be used to latch the contents of the

encoder quadrature counter into dedicated registers,

EIZLATCH and EISLATCH, on the occurrence of external

events at the EIZ and EIS pins. These events may be pro-

grammed to be either rising edge only (latch event) or rising

edge if the encoder is moving in the forward direction and fall-

ing edge if the encoder is moving in the reverse direction

(software latched north marker functionality).

The FIO module can also be used to generate an asynchronous

unregistered wake-up signal FIO_WAKEUP for DSP core wake

up after power-down.

The FIO lines, PF7–1 can also be configured as external slave

select outputs for the SPI communications port, while PF0 can

be configured to act as a slave select input.

The FIO lines can be configured to act as a PWM shutdown

source for the 3-phase PWM generation unit of the

ADSP-21990.

WATCHDOG TIMER

The encoder interface unit incorporates programmable noise

filtering on the four encoder inputs to prevent spurious noise

pulses from adversely affecting the operation of the quadrature

counter. The encoder interface unit operates at a clock fre-

quency equal to the HCLK rate. The encoder interface unit

operates correctly with encoder signals at frequencies of up to

13.25 MHz at the 80 MHz HCLK rate, corresponding to a maxi-

mum quadrature frequency of 53 MHz (assuming an ideal

quadrature relationship between the input EIA and EIB signals).

The ADSP-21990 integrates a watchdog timer that can be used

as a protection mechanism against unintentional software

events. It can be used to cause a complete DSP and peripheral

reset in such an event. The watchdog timer consists of a 16-bit

timer that is clocked at the external clock rate (CLKIN or crystal

input frequency).

In order to prevent an unwanted timeout or reset, it is necessary

to periodically write to the watchdog timer register. During

abnormal system operation, the watchdog count will eventually

decrement to 0 and a watchdog timeout will occur. In the sys-

tem, the watchdog timeout will cause a full reset of the DSP core

and peripherals.

The EIU may be programmed to use the north marker on EIZ to

reset the quadrature encoder in hardware, if required.

Alternatively, the north marker can be ignored, and the encoder

quadrature counter is reset according to the contents of a maxi-

mum count register, EIUMAXCNT. There is also a “single

north marker” mode available in which the encoder quadrature

counter is reset only on the first north marker pulse.

GENERAL-PURPOSE TIMERS

The ADSP-21990 contains a general-purpose timer unit that

contains three identical 32-bit timers. The three programmable

interval timers (Timer0, Timer1, and Timer2) generate periodic

interrupts. Each timer can be independently set to operate in

one of three modes:

The encoder interface unit can also be made to implement some

error checking functions. If an encoder count error is detected

(due to a disconnected encoder line, for example), a status bit in

the EIUSTAT register is set, and an EIU count error interrupt is

generated.

• Pulse waveform generation (PWM_OUT) mode.

• Pulse width count/capture (WDTH_CAP) mode.

• External event watchdog (EXT_CLK) mode.

The encoder interface unit of the ADSP-21990 contains a 16-bit

loop timer that consists of a timer register, period register, and

scale register so that it can be programmed to time out and

reload at appropriate intervals. When this loop timer times out,

an EIU loop timer timeout interrupt is generated. This interrupt

could be used to control the timing of speed and position con-

trol loops in high performance drives.

Each timer has one bidirectional chip pin, TMR2-0. For each

timer, the associated pin is configured as an output pin in

PWM_OUT mode and as an input pin in WDTH_CAP and

EXT_CLK modes.

INTERRUPTS

The encoder interface unit also includes a high performance

encoder event timer (EET) block that permits the accurate tim-

ing of successive events of the encoder inputs. The EET can be

programmed to time the duration between up to 255 encoder

pulses and can be used to enhance velocity estimation, particu-

larly at low speeds of rotation.

The interrupt controller lets the DSP respond to 17 interrupts

with minimum overhead. The DSP core implements an inter-

rupt priority scheme as shown in Table 2. Applications can use

the unassigned slots for software and peripheral interrupts. The

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peripheral interrupt controller is used to assign the various

peripheral interrupts to the 12 user assignable interrupts of the

DSP core.

The interrupt control (ICNTL) register controls interrupt nest-

ing and enables or disables interrupts globally.

The IRPTL register is used to force and clear interrupts. On-

chip stacks preserve the processor status and are automatically

maintained during interrupt handling. To support interrupt,

loop, and subroutine nesting, the PC stack is 33 levels deep, the

loop stack is eight levels deep, and the status stack is 16 levels

deep. To prevent stack overflow, the PC stack can generate a

stack level interrupt if the PC stack falls below three locations

full or rises above 28 locations full.

Table 2. Interrupt Priorities/Addresses

IMASK/

IRPTL

Interrupt

Vector Address

Emulator (NMI)

NA

—Highest Priority

Reset (NMI)

0

1

2

3

4

0x00 0000

0x00 0020

0x00 0040

0x00 0060

0x00 0080

The following instructions globally enable or disable interrupt

servicing, regardless of the state of IMASK:

Power Down (NMI)

Loop and PC Stack

Emulation Kernel

• Ena Int.

• Dis Int.

User Assigned Interrupt

(USR0)

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and

computational registers exist. Switching between the primary

and secondary registers lets programs quickly service interrupts,

while preserving the state of the DSP.

User Assigned Interrupt

(USR1)

5

0x00 00A0

0x00 00C0

0x00 00E0

0x00 0100

0x00 0120

0x00 0140

0x00 0160

0x00 0180

0x00 01A0

0x00 01C0

0x00 01E0

User Assigned Interrupt

(USR2)

6

User Assigned Interrupt

(USR3)

7

PERIPHERAL INTERRUPT CONTROLLER

The peripheral interrupt controller is a dedicated peripheral

unit of the ADSP-21990 (accessed via I/O mapped registers).

The peripheral interrupt controller manages the connection of

up to 32 peripheral interrupt requests to the DSP core.

User Assigned Interrupt

(USR4)

8

User Assigned Interrupt

(USR5)

9

For each peripheral interrupt source, there is a unique 4-bit

code that allows the user to assign the particular peripheral

interrupt to any one of the 12 user assignable interrupts of the

embedded ADSP-2199x core. Therefore, the peripheral inter-

rupt controller of the ADSP-21990 contains eight, 16-bit

interrupt priority registers (Interrupt Priority Register 0 (IPR0)

to Interrupt Priority Register 7 (IPR7)).

User Assigned Interrupt

(USR6)

10

11

12

13

14

15

User Assigned Interrupt

(USR7)

User Assigned Interrupt

(USR8)

User Assigned Interrupt

(USR9)

Each interrupt priority register contains four 4-bit codes; one

specifically assigned to each peripheral interrupt. The user may

write a value between 0x0 and 0xB to each 4-bit location in

order to effectively connect the particular interrupt source to

the corresponding user assignable interrupt of the

ADSP-2199x core.

User Assigned Interrupt

(USR10)

User Assigned Interrupt

(USR11)

—Lowest Priority

Writing a value of 0x0 connects the peripheral interrupt to the

USR0 user assignable interrupt of the ADSP-2199x core while

writing a value of 0xB connects the peripheral interrupt to the

USR11 user assignable interrupt. The core interrupt USR0 is the

highest priority user interrupt, while USR11 is the lowest prior-

ity. Writing a value between 0xC and 0xF effectively disables the

peripheral interrupt by not connecting it to any ADSP-2199x

core interrupt input. The user may assign more than one

peripheral interrupt to any given ADSP-2199x core interrupt. In

that case, the burden is on the user software in the interrupt vec-

tor table to determine the exact interrupt source through

reading status bits.

There is no assigned priority for the peripheral interrupts after

reset. To assign the peripheral interrupts a different priority,

applications write the new priority to their corresponding con-

trol bits (determined by their ID) in the interrupt priority

control register.

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The emulation, power down, and reset interrupts are

nonmaskable with the IMASK register, but software can use the

DIS INT instruction to mask the power-down interrupt.

This scheme permits the user to assign the number of specific

interrupts that are unique to their application to the interrupt

scheme of the ADSP-2199x core. The user can then use the

existing interrupt priority control scheme to dynamically con-

trol the priorities of the 12 core interrupts.

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LOW POWER OPERATION

CLOCK SIGNALS

The ADSP-21990 has four low power options that significantly

reduce the power dissipation when the device operates under

standby conditions. To enter any of these modes, the DSP exe-

cutes an IDLE instruction. The ADSP-21990 uses the

configuration of the PD, STCK, and STALL bits in the PLLCTL

register to select between the low power modes as the DSP exe-

cutes the IDLE instruction. Depending on the mode, an IDLE

shuts off clocks to different parts of the DSP in the different

modes. The low power modes are:

The ADSP-21990 can be clocked by a crystal oscillator or a buff-

ered, shaped clock derived from an external clock oscillator. If a

crystal oscillator is used, the crystal should be connected across

the CLKIN and XTAL pins, with two capacitors connected as

shown in Figure 6. Capacitor values are dependent on crystal

type and should be specified by the crystal manufacturer. A par-

allel resonant, fundamental frequency, microprocessor grade

crystal should be used for this configuration.

If a buffered, shaped clock is used, this external clock connects

to the DSP CLKIN pin. CLKIN input cannot be halted, changed,

or operated below the specified frequency during normal opera-

tion. This clock signal should be a TTL-compatible signal.

When an external clock is used, the XTAL input must be left

unconnected.

• Idle

• Power-down core

• Power-down core/peripherals

• Power-down all

The DSP provides a user-programmable 1

؋

to 32

؋

multiplica-

tion of the input clock, including some fractional values, to

support 128 external to internal (DSP core) clock ratios. The

BYPASS pin, and MSEL6–0 and DF bits, in the PLL configura-

tion register, decide the PLL multiplication factor at reset. At

run time, the multiplication factor can be controlled in software.

To support input clocks greater that 100 MHz, the PLL uses an

additional bit (DF). If the input clock is greater than 100 MHz,

DF must be set. If the input clock is less than 100 MHz, DF must

be cleared. For clock multiplier settings, see the ADSP-2199x

Mixed Signal DSP Controller Hardware Reference.

Idle Mode

When the ADSP-21990 is in idle mode, the DSP core stops exe-

cuting instructions, retains the contents of the instruction

pipeline, and waits for an interrupt. The core clock and periph-

eral clock continue running.

To enter idle mode, the DSP can execute the IDLE instruction

anywhere in code. To exit Idle mode, the DSP responds to an

interrupt and (after two cycles of latency) resumes executing

instructions.

Power-Down Core Mode

The peripheral clock is supplied to the CLKOUT pin.

When the ADSP-21990 is in power-down core mode, the DSP

core clock is off, but the DSP retains the contents of the pipeline

and keeps the PLL running. The peripheral bus keeps running,

letting the peripherals receive data.

All on-chip peripherals for the ADSP-21990 operate at the rate

set by the peripheral clock. The peripheral clock (HCLK) is

either equal to the core clock rate or one half the DSP core clock

rate (CCLK). This selection is controlled by the IOSEL bit in the

PLLCTL register. The maximum core clock is 160 MHz for the

ADSP-21990BST and 150 MHz for the ADSP-21990BBC. The

maximum peripheral clock is 80 MHz for the ADSP-21990BST

and 75 MHz for the ADSP-21990BBC—the combination of the

input clock and core/peripheral clock ratios may not exceed

these limits.

To exit power-down core mode, the DSP responds to an inter-

rupt and (after two cycles of latency) resumes executing

instructions.

Power-Down Core/Peripherals Mode

When the ADSP-21990 is in power-down core/peripherals

mode, the DSP core clock and peripheral bus clock are off, but

the DSP keeps the PLL running. The DSP does not retain the

contents of the instruction pipeline.The peripheral bus is

stopped, so the peripherals cannot receive data.

To exit power-down core/peripherals mode, the DSP responds

to an interrupt and (after five to six cycles of latency) resumes

executing instructions.

XTAL

CLKIN

ADSP-2199x

Power-Down All Mode

When the ADSP-21990 is in power-down all mode, the DSP

core clock, the peripheral clock, and the PLL are all stopped.

The DSP does not retain the contents of the instruction pipe-

line. The peripheral bus is stopped, so the peripherals cannot

receive data.

Figure 6. External Crystal Connections

To exit power-down core/peripherals mode, the DSP responds

to an interrupt and (after 500 cycles to restabilize the PLL)

resumes executing instructions.

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RESET AND POWER-ON RESET (POR)

POWER SUPPLIES

The RESET pin initiates a complete hardware reset of the

ADSP-21990 when pulled low. The RESET signal must be

asserted when the device is powered up to assure proper initial-

ization. The ADSP-21990 contains an integrated power-on reset

(POR) circuit that provides an output reset signal, POR, from

the ADSP-21990 on power-up and if the power supply voltage

falls below the threshold level. The ADSP-21990 may be reset

from an external source using the RESET signal, or alterna-

tively, the internal power-on reset circuit may be used by

connecting the POR pin to the RESET pin. During power-up

the RESET line must be activated for long enough to allow the

DSP core’s internal clock to stabilize. The power-up sequence is

defined as the total time required for the crystal oscillator to sta-

bilize after a valid VDD is applied to the processor and for the

internal phase-locked loop (PLL) to lock onto the specific crys-

tal frequency. A minimum of 512 cycles will ensure that the PLL

has locked (this does not include the crystal oscillator

start-up time).

The ADSP-21990 has separate power supply connections for the

internal (V_DDINT) and external (V_DDEXT) power supplies. The

internal supply must meet the 2.5 V requirement. The external

supply must be connected to a 3.3 V supply. All external supply

pins must be connected to the same supply. The ideal power-on

sequence for the DSP is to provide power-up of all supplies

simultaneously. If there is going to be some delay in power-up

between the supplies, provide V_DDfirst, then V_{DD_IO}

.

BOOTING MODES

The ADSP-21990 supports a number of different boot modes

that are controlled by the three dedicated hardware boot mode

control pins (BMODE2, BMODE1, and BMODE0). The use of

three boot mode control pins means that up to eight different

boot modes are possible. Of these only five modes are valid on

the ADSP-21990. The ADSP-21990 exposes the boot mecha-

nism to software control by providing a nonmaskable boot

interrupt that vectors to the start of the on-chip ROM memory

block (at address 0xFF0000). A boot interrupt is automatically

initiated following either a hardware initiated reset, via the

RESET pin, or a software initiated reset, via writing to the Soft-

ware Reset register. Following either a hardware or a software

reset, execution always starts from the boot ROM at address

0xFF0000, irrespective of the settings of the BMODE2,

The RESET input contains some hysteresis. If an RC circuit is

used to generate the RESET signal, the circuit should use an

external Schmitt trigger.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and resets all registers to

their default values (where applicable). When RESET is

released, if there is no pending bus request, program control

jumps to the location of the on-chip boot ROM (0xFF0000) and

the booting sequence is performed.

BMODE1, and BMODE0 pins. The dedicated BMODE2,

BMODE1, and BMODE0 pins are sampled at hardware reset.

The particular boot mode for the ADSP-21990 associated with

the settings of the BMODE2, BMODE1, BMODE0 pins is

defined in Table 3.

Table 3. Summary of Boot Modes

Boot Mode

BMODE2

BMODE1

BMODE0

Function

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Illegal-Reserved

Boot from External 8-Bit Memory over EMI

Execute from External 8-Bit Memory

Execute from External 16-Bit Memory

Boot from SPI ≤ 4K Bits

Boot from SPI > 4K Bits

Illegal-Reserved

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ADSP-21990

cal profiling enables the programmer to nonintrusively poll the

processor as it is running the program. This feature, unique to

VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

INSTRUCTION SET DESCRIPTION

The ADSP-21990 assembly language instruction set has an alge-

braic syntax that was designed for ease of coding and

readability. The assembly language, which takes full advantage

of the unique architecture of the processor, offers the following

benefits:

• ADSP-21xx assembly language syntax is a superset of and

source code compatible (except for two data registers and

DAG base address registers) with ADSP-21xx family syn-

tax. It may be necessary to restructure ADSP-21xx

programs to accommodate the ADSP-21990 unified mem-

ory space and to conform to its interrupt vector map.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information).

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical arith-

metic add instruction, such as AR = AX0 + AY0, resembles

a simple equation.

• Insert breakpoints.

• Set conditional breakpoints on registers, memory,

and stacks.

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The

exceptions are two dual word instructions. One writes

16-bit or 24-bit immediate data to memory, and the other

is an absolute jump/call with the 24-bit address specified in

the instruction.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Create custom debugger windows.

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the ADSP-21xx

development tools, including the color syntax highlighting in

the VisualDSP++ editor. This capability permits

programmers to:

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of

conditions on which to base execution of conditional

instructions.

• Control how the development tools process inputs and

generate outputs.

DEVELOPMENT TOOLS

• Maintain a one-to-one correspondence with the command

line switches of the tool.

The ADSP-21990 is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The emulator hardware that supports

other ADSP-21xx DSPs also fully emulates the ADSP-21990.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The DSP has archi-

tectural features that improve the efficiency of compiled

C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have significant influence on the

design development schedule, increasing productivity. Statisti-

Rev. A

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Page 14 of 50

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August 2007

ADSP-21990

VCSE is a Analog Devices technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

applications. The user can download components from the

Web, drop them into the application and publish component

archives from within VisualDSP++. VCSE supports component

implementation in C/C++ or assembly language.

communications ports and embedded control peripherals, refer

to the ADSP-2199x Mixed Signal DSP Controller Hardware

Reference.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with the drag

of the mouse, and examine runtime stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the graphi-

cal and textual environments.

DSP emulators from Analog Devices use the IEEE 1149.1 JTAG

test access port of the ADSP-21990 processor to monitor and

control the target board processor during emulation. The emu-

lator provides full speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Non-

intrusive in-circuit emulation is assured by the use of the

processor JTAG interface—target system loading and timing are

not affected by the emulator.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the ADSP-21xx processor family.

Hardware tools include ADSP-21xx DSP PC plug-in cards.

Third-party software tools include DSP libraries, real-time

operating systems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG DSP. The emulator uses the

TAP to access the internal features of the DSP, allowing the

developer to load code, set breakpoints, observe variables,

observe memory, and examine registers. The DSP must be

halted to send data and commands, but once an operation has

been completed by the emulator, the DSP system is set running

at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21990

architecture and functionality. For detailed information on the

ADSP-21990 embedded DSP core architecture, instruction set,

Rev. A

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Page 15 of 50

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August 2007

ADSP-21990

PIN FUNCTION DESCRIPTIONS

ADSP-21990 pin definitions are listed in Table 4. All

ADSP-21990 inputs are asynchronous and can be asserted asyn-

chronously to CLKIN (or to TCK for TRST).

floating internally. PWMTRIP has an internal pull-down, but

should not be left floating to avoid unnecessary PWM

shutdowns.

Unused inputs should be tied or pulled to V_DDEXTor GND,

except for ADDR21–0, DATA15–0, PF7-0, and inputs that have

internal pull-up or pull-down resistors (TRST, BMODE0,

BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL,

PWMSR, and RESET)—these pins can be left floating. These

pins have a logic level hold circuit that prevents input from

The following symbols appear in the Type column of Table 4:

G = ground, I = input, O = output, P = power supply,

B = bidirectional, T = three-state, D = digital, A = analog,

CKG = clock generation pin, PU = internal pull-up, and

PD = internal pull-down.

Table 4. Pin Descriptions

Name

A19-0

D15-0

RD

Type

D, OT

D, BT

D, OT

D, I

Function

External Port Address Bus

External Port Data Bus

External Port Read Strobe

External Port Write Strobe

External Port Access Ready Acknowledge

External Port Bus Request

External Port Bus Grant

External Port Bus Grant Hang

External Port Memory Select Strobe 0

External Port Memory Select Strobe 1

External Port Memory Select Strobe 2

External Port Memory Select Strobe 3

External Port I/O Space Select Strobe

External Port Boot Memory Select Strobe

Clock Input/Oscillator Input/Crystal Connection 0

Oscillator Output/ Crystal Connection 1

Clock Output (HCLK)

WR

ACK

BR

D, I, PU

D, O

BG

BGH

D, O

MS0

D, OT

D, I, CKG

D, O, CKG

D, O

MS1

MS2

MS3

IOMS

BMS

CLKIN

XTAL

CLKOUT

BYPASS

RESET

POR

D, I, PU

D, O

PLL Bypass Mode Select

Processor Reset Input

Power on Reset Output

Boot Mode Select Input 2

Boot Mode Select Input 1

Boot Mode Select Input 0

JTAG Test Clock

BMODE2

BMODE1

BMODE0

TCK

D, I, PU

D, I, PD

D, I, PU

D, I

TMS

D, I, PU

D, OT

D, I, PU

D, OT, PU

A, I

JTAG Test Mode Select

TDI

JTAG Test Data Input

TDO

JTAG Test Data Output

TRST

EMU

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

JTAG Test Reset Input

Emulation Status

ADC Input 0

A, I

ADC Input 1

A, I

ADC Input 2

A, I

ADC Input 3

A, I

ADC Input 4

A, I

ADC Input 5

A, I

ADC Input 6

Rev. A

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Page 16 of 50

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August 2007

ADSP-21990

Table 4. Pin Descriptions (Continued)

Name

VIN7

Type

Function

A, I

ADC Input 7

ASHAN

BSHAN

CAPT

A, I

Inverting SHA_A Input

Inverting SHA_B Input

Noise Reduction Pin

A, I

A, O

CAPB

A, O

VREF

A, I, O

A, I

Voltage Reference Pin (Mode Selected by State of SENSE)

Voltage Reference Select Pin

Common-Mode Level Pin

SENSE

CML

A, O

CONVST

PF15

D, I

ADC Convert Start Input

D, BT, PD

D, BT

General-Purpose IO15

PF14

General-Purpose IO14

PF13

General-Purpose IO13

PF12

General-Purpose IO12

PF11

General-Purpose IO11

PF10

General-Purpose IO10

PF9

General-Purpose IO9

PF8

General-Purpose IO8

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS

SCK

General-Purpose IO7/SPI Slave Select Output 7

General-Purpose IO6/SPI Slave Select Output 6

General-Purpose IO5/SPI Slave Select Output 5

General-Purpose IO4/SPI Slave Select Output 4

General-Purpose IO3/SPI Slave Select Output 3

General-Purpose IO2/SPI Slave Select Output 2

General-Purpose IO1/SPI Slave Select Output 1

General-Purpose IO0/SPI Slave Select Input 0

SPI Clock

MISO

D, BT

SPI Master In Slave Out Data

SPI Master Out Slave In Data

SPORT Data Transmit

MOSI

D, BT

DT

D, OT

D, I

DR

SPORT Data Receive

RFS

D, BT

SPORT Receive Frame Sync

SPORT Transmit Frame Sync

SPORT Transmit Clock

TFS

D, BT

TCLK

D, BT

RCLK

D, BT

SPORT Receive Clock

EIA

D, I

Encoder A Channel Input

EIB

D, I

Encoder B Channel Input

EIZ

D, I

Encoder Z Channel Input

EIS

D, I

Encoder S Channel Input

AUX0

AUX1

AUXTRIP

TMR2

TMR1

TMR0

AH

D, O

Auxiliary PWM Channel 0 Output

Auxiliary PWM Channel 1 Output

Auxiliary PWM Shutdown Pin

Timer 0 Input/Output Pin

D, O

D, I, PD

D, BT

Timer 1 Input/Output Pin

D, BT

Timer 2 Input/Output Pin

D, O

PWM Channel A HI PWM

AL

D, O

PWM Channel A LO PWM

Rev. A

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Page 17 of 50

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August 2007

ADSP-21990

Table 4. Pin Descriptions (Continued)

Name

Type

D, O

Function

BH

PWM Channel B HI PWM

PWM Channel B LO PWM

PWM Channel C HI PWM

PWM Channel C LO PWM

PWM Synchronization

PWM Polarity

BL

D, O

CH

D, O

CL

D, O

PWMSYNC

PWMPOL

PWMTRIP

PWMSR

D, BT

D, I, PU

D, I, PD

D, I, PU

A, P

PWM Trip

PWM SR Mode Select

Analog Supply Voltage

Analog Ground

AVDD (2 pins)

AVSS (2 pins)

VDDINT (6 pins)

VDDEXT (10 pins)

GND (16 pins)

A, G

D, P

Digital Internal Supply

Digital External Supply

Digital Ground

D, P

D, G

Rev. A

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Page 18 of 50

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August 2007

ADSP-21990

SPECIFICATIONS

Specifications subject to change without notice.

RECOMMENDED OPERATING CONDITIONS—ADSP-21990BBC

Parameter

V_DDINT

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

150

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

V_DDEXT

V

AVDD

V

CCLK

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

MHz

ЊC

HCLK^{1, 2}

CLKIN³

0

75

Input Clock Frequency

0

150

4

T_JUNC

Silicon Junction Temperature

Ambient Operating Temperature

140ºC

+85ºC

T_AMB

–40ºC

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK ، 2, up to a maximum of a 75 MHz HCLK for the ADSP-21990BBC.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

RECOMMENDED OPERATING CONDITIONS—ADSP-21990BST

Parameter

V_DDINT

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

160

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

V_DDEXT

V

AVDD

V

CCLK

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

MHz

ЊC

HCLK^{1, 2}

CLKIN³

0

80

Input Clock Frequency

0

160

4

T_JUNC

Silicon Junction Temperature

Ambient Operating Temperature

140ºC

+85ºC

T_AMB

–40ºC

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK/2, up to a maximum of an 80 MHz HCLK for the ADSP-21990BST.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21990 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Rev. A

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Page 19 of 50

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August 2007

ADSP-21990

ELECTRICAL CHARACTERISTICS—ADSP-21990BBC

Parameter

Conditions

Test Conditions

Min

2.0

Typ

Max

V_DDEXT

0.8

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

V

2.2

V_OH

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

I_OL= 2.0 mA

0.4

10

V

@ V_DDINT= Maximum,

V_IN= 3.6 V

μA

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

150

10

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

10

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

10

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

150

10

I_OZH

I_OZL

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

10

C_I

Input Pin Capacitance

f_IN= 1 MHz

10

pF

C_O

Output Pin Capacitance

10

pF

I_DD-PEAK

I_DD-TYP

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

300

250

230

130

15

350

290

285

190

75

mA

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

10

60

55

65

I_AVDD-ADCOFF

20

35

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, HCLK = 75 MHz

for the ADSP-21990BBC. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDIINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINTmaximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum.

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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Page 20 of 50

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August 2007

ADSP-21990

ELECTRICAL CHARACTERISTICS—ADSP-21990BST

Parameter

Conditions

Test Conditions

Min

2.0

Typ

Max

V_DDEXT

0.8

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

V

2.2

V_OH

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

I_OL= 2.0 mA

0.4

10

V

@ V_DDINT= Maximum,

V_IN= 3.6 V

μA

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

150

10

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

10

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

10

I_IL

@ V_DDINT= Maximum,

V_IN= 0 V

150

10

I_OZH

I_OZL

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

10

C_I

Input Pin Capacitance

f_IN= 1 MHz

10

pF

C_O

Output Pin Capacitance

10

pF

I_DD-PEAK

I_DD-TYP

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

325

275

250

140

25

375

320

300

175

55

mA

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

15

45

55

65

I_AVDD-ADCOFF

20

35

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 160 MHz, HCLK = 80 MHz

for the ADSP-21990BST. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINT= maximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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Page 21 of 50

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August 2007

ADSP-21990

PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21990BBC

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTER

AC Specifications

SNR

Signal-to-Noise Ratio¹

68

64

71

dB

SNRD

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

68

dB

THD

–72

–78

–74

0.05

–66

0.2

dB

CTLK

dB

CMRR

dB

PSRR

%FSR

Accuracy

INL

Integral Nonlinearity¹

±1.0

±0.5

12

±2.0

±1.25

LSB

DNL

Differential Nonlinearity¹

LSB

No Missing Codes

Zero Error¹

Gain Error¹

Bits

1.25

0.5

2.5

1.5

%FSR

Input Voltage

V_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

C_IN

pF

Conversion Time

FCLK

ADC Clock Rate

18.75

773

MHz

ns

t_CONV

Total Conversion Time All 8 Channels

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON-RESET

V_RST

0.94

0.98

40

1.02

V

mV

μA

mV

kΩ

100

0.5

8

2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

V_HYST

50

mV

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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Page 22 of 50

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August 2007

ADSP-21990

PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21990BST

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTER

SNR

Signal-to-Noise Ratio¹

68

72

dB

SNRD

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

71

dB

THD

–80

–78

–74

0.05

–68

–66

0.2

dB

CTLK

dB

CMRR

dB

PSRR

%FSR

Accuracy

INL

Integral Nonlinearity¹

±0.6

±0.5

12

±2.0

±1.25

LSB

DNL

Differential Nonlinearity¹

LSB

No Missing Codes

Zero Error¹

Gain Error¹

Bits

1.25

0.5

2.5

1.5

%FSR

Input Voltage

V_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

C_IN

pF

Conversion Time

FCLK

ADC Clock Rate

20

MHz

ns

t_CONV

Total Conversion Time All 8 Channels

725

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON-RESET

V_RST

0.94

0.98

40

1.02

V

mV

μA

mV

kΩ

100

+0.5

8

–2

+2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

V_HYST

50

mV

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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ADSP-21990

ABSOLUTE MAXIMUM RATINGS

Table 5. Absolute Maximum Ratings

Parameter

Rating

1

Internal (Core) Supply Voltage (V_DDINT

)

–0.3 V to +3.0 V

–0.3 V to +4.6 V

–0.5 V to +5.5 V

200 pF

1

External (I/O) Supply Voltage (V_DDEXT

Input Voltage (V_IL– V_IH)^{1, 2}

)

1, 2

Output Voltage Swing (V_OL– V_OH

Load Capacitance (C_L)¹

)

1

Core Clock Period (t_CCLK

)

6.25 ns

1

Core Clock Frequency (f_CCLK

Peripheral Clock Period (t_HCLK

Peripheral Clock Frequency (f_HCLK

Storage Temperature Range (T_STORE

Lead Temperature (5 Seconds) (T_LEAD

)

160 MHz

1

)

12.5 ns

1

)

80 MHz

1

)

–65ЊC to +150ЊC

1

)

185ЊC

¹Stresses greater than those listed above may cause permanent damage to the device. These are

stress ratings only; functional operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

²Except CLKIN and analog pins.

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary circuitry, damage may occur

on devices subjected to high energy ESD. Therefore,

proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

TIMING SPECIFICATIONS

This section contains timing information for the DSP external

signals. Use the exact information given. Do not attempt to

derive parameters from the addition or subtraction of other

information. While addition or subtraction would yield mean-

ingful results for an individual device, the values given in this

data sheet reflect statistical variations and worst cases. Conse-

quently, parameters cannot be added meaningfully to derive

longer times.

Switching characteristics specify how the processor changes its

signals. No control is possible over this timing; circuitry exter-

nal to the processor must be designed for compatibility with

these signal characteristics. Switching characteristics indicate

what the processor will do in a given circumstance. Switching

characteristics can also be used to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation.Timing requirements guarantee that the processor

operates correctly with other devices.

Rev. A

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ADSP-21990

core clock rate. If the peripheral clock rate is equal to the core

clock rate, the maximum peripheral clock rate is 80 MHz for the

ADSP-21990BST and 75 MHz for the ADSP-21990BBC. The

peripheral clock is supplied to the CLKOUT pins.

Clock In and Clock Out Cycle Timing

Table 6 and Figure 7 describe clock and reset operations. Com-

binations of CLKIN and clock multipliers must not select

core/peripheral clocks in excess of 160 MHz/80 MHz for the

ADSP-21990BST and 150 MHz/75 MHz for the

When changing from bypass mode to PLL mode, allow 512

HCLK cycles for the PLL to stabilize.

ADSP-21990BBC, when the peripheral clock rate is one-half the

Table 6. Clock In and Clock Out Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period^{1, 2}

10

200

ns

μs

ns

t_CKL

t_CKH

t_WRST

t_MSS

t_MSH

t_MSD

t_PFD

CLKIN Low Pulse

4.5

CLKIN High Pulse

4.5

RESET Asserted Pulse Width Low

MSELx/BYPASS Stable Before RESET Deasserted Setup

MSELx/BYPASS Stable After RESET Deasserted Hold

MSELx/BYPASS Stable After RESET Asserted

Flag Output Disable Time After RESET Asserted

200t_CLKOUT

40

1000

200

10

Switching Characteristics

t_CKODCLKOUT Delay from CLKIN

t_CKO

CLKOUT Period³

0

5.8

ns

12.5

¹In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t_CK= t_CCLK

.

²In bypass mode, t_CK= t_CCLK

.

³CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

t_CK

CLKIN

t_CKL

t_CKH

t_WRST

RESET

t_MSD

t_PFD

t_MSS

t_MSH

MSEL6–0

BYPASS

DF

t_CKOD

t_CKO

CLKOUT

Figure 7. Clock In and Clock Out Cycle Timing

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ADSP-21990

Programmable Flags Cycle Timing

Table 7 and Figure 8 describe programmable flag operations.

Table 7. Programmable Flags Cycle Timing

Parameter

Min

Max

Unit

Timing Requirement

t_HFI

Flag Input Hold Is Asynchronous

3

ns

Switching Characteristics

t_DFOFlag Output Delay with Respect to CLKOUT

t_HFOFlag Output Hold After CLKOUT High

7

6

ns

CLKOUT

t_DFO

t_HFO

PF

(OUTPUT)

FLAG OUTPUT

t_HFI

PF

(INPUT)

FLAG INPUT

Figure 8. Programmable Flags Cycle Timing

Rev. A

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ADSP-21990

Timer PWM_OUT Cycle Timing

Table 8 and Figure 9 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and has

an absolute maximum input frequency of 40 MHz.

Table 8. Timer PWM_OUT Cycle Timing

Parameter

Min

Max

(2³²–1) cycles

Unit

Switching Characteristic

t_HTO

Timer Pulse Width Output¹

12.5

ns

¹The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

HCLK

t_HTO

PWM_OUT

Figure 9. Timer PWM_OUT Cycle Timing

Rev. A

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ADSP-21990

at the rising edge of EMI clock. ACK low causes the DSP to wait,

and the DSP requires two EMI clock cycles after ACK goes high

to finish the access. For more information, see the External Port

chapter in the ADSP-2199x Mixed Signal DSP Controller Hard-

ware Reference.

External Port Write Cycle Timing

Table 9 and Figure 10 describe external port write operations.

The external port lets systems extend read/write accesses in

three ways: wait states, ACK input, and combined wait states

and ACK. To add waits with ACK, the DSP must see ACK low

Table 9. External Port Write Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements^{1, 2}

t_AKW

ACK Strobe Pulse Width

ACK Delay from XMS Low

12.5

ns

t_DWSAK

0.5t_EMICLK– 1

Switching Characteristics

t_CSWS

t_AWS

t_WSCS

t_WSA

t_WW

Chip Select Asserted to WR Asserted Delay

0.5t_EMICLK– 4

0.5t_EMICLK– 3

0.5t_EMICLK– 4

0.5t_EMICLK– 3

t_EMICLK–2 + W³

ns

Address Valid to WR Setup and Delay

WR Deasserted to Chip Select Deasserted

WR Deasserted to Address Invalid

WR Strobe Pulse Width

t_CDA

t_CDD

t_DSW

t_DHW

t_WWR

WR to Data Enable Access Delay

0

WR to Data Disable Access Delay

0.5t_EMICLK– 3

t_EMICLK+ 1 + W³

3.4

0.5t_EMICLK+ 4

t_EMICLK+ 7 + W³

Data Valid to WR Deasserted Setup

WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 5}

WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 6}

WR Deasserted to WR, RD Asserted

t_EMICLK+ 3.4

t_HCLK

¹t_EMICLKis the external memory interface clock period. t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

³W = (number of wait states specified in wait register) ϫ t_BMCLK

⁴Write hold cycle–memory select control registers (MS ϫ CTL).

⁵Write wait state count (E_WHC) = 0

⁶Write wait state count (E_WHC) = 1

Rev. A

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ADSP-21990

t_CSWS

t_WSCS

MS3–0

IOMS

BMS

A21–0

t_WW

t_WSA

t_AWS

WR

t_WWR

t_AKW

ACK

t_CDD

t_DHW

t_CDA

t_DSW

t_DWSAK

D15–0

RD

Figure 10. External Port Write Cycle Timing

Rev. A

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ADSP-21990

External Port Read Cycle Timing

Table 10 and Figure 11 describe external port read operations.

For additional information on the ACK signal, see the discus-

sion on Page 28.

Table 10. External Port Read Cycle Timing

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements

t_AKW

t_RDA

t_ADA

t_SDA

t_SD

ACK Strobe Pulse Width

t_HCLK

ns

RD Asserted to Data Access Setup

Address Valid to Data Access Setup

Chip Select Asserted to Data Access Setup

Data Valid to RD Deasserted Setup

RD Deasserted to Data Invalid Hold

ACK Delay from XMS Low

t_EMICLK– 5 + W³

t_EMICLK+ W³

5

0

t_HRD

t_DRSAK

0.5t_EMICLK– 1

Switching Characteristics

t_CSRS

t_ARS

t_RSCS

t_RW

Chip Select Asserted to RD Asserted Delay

0.5t_EMICLK– 3

0.5t_EMICLK– 2

t_EMICLK–2 + W³

0.5t_HCLK– 2

t_HCLK

ns

Address Valid to RD Setup and Delay

RD Deasserted to Chip Select Deasserted Setup

RD Strobe Pulse Width

t_RSA

RD Deasserted to Address Invalid Setup

t_RWR

RD Deasserted to WR, RD Asserted

¹t_EMICLKis the external memory interface clock period. t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

³W = (number of wait states specified in wait register)

؋

t_EMICLK

.

Rev. A

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ADSP-21990

t_RSCS

t_CSRS

MS3–0

IOMS

BMS

A21–0

t_RW

t_RSA

t_ARS

RD

t_DRSAK

t_RWR

t_AKW

ACK

t_CDA

t_{H RD}

t_SD

D15–0

t_RDA

t_ADA

t_SDA

WR

Figure 11. External Port Read Cycle Timing

Rev. A

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ADSP-21990

External Port Bus Request/Grant Cycle Timing

Table 11 and Figure 12 describe external port bus request and

bus grant operations.

Table 11. External Port Bus Request and Grant Cycle Timing

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements

t_BS

BR Asserted to CLKOUT High Setup

4.6

0

ns

t_BH

CLKOUT High to BR Deasserted Hold Time

Switching Characteristics

t_SD

CLKOUT High to xMS, Address, and RD/WR Disable

0.5t_HCLK+ 1

ns

t_SE

CLKOUT Low to xMS, Address, and RD/WR Enable

CLKOUT High to BG Asserted Setup

0

4

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH Asserted Setup

CLKOUT High to BGH Deasserted Hold Time

¹t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

CLKOUT

t_BS

t_BH

BR

t_SD

t_SE

MS3–0

IOMS

BMS

t_SD

t_SE

A21–0

t_SE

t_SD

WR

RD

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 12. External Port Bus Request and Grant Cycle Timing

Rev. A

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ADSP-21990

Serial Port Timing

Table 12 and Figure 13 describe SPORT transmit and receive

operations, while Figure 14 and Figure 15 describe SPORT

Frame Sync operations.

Table 12. Serial Port^{1, 2}

Parameter

Min

Max

Unit

External Clock Timing Requirements

t_SFSE

TFS/RFS Setup Before TCLK/RCLK³

TFS/RFS Hold After TCLK/RCLK³

Receive Data Setup Before RCLK³

Receive Data Hold After RCLK³

TCLK/RCLK Width

4

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

4

1.5

4

0.5t_HCLK– 1

2t_HCLK

TCLK/RCLK Period

Internal Clock Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFS Setup Before TCLK⁴; RFS Setup Before RCLK³

4

3

2

5

ns

TFS/RFS Hold After TCLK/RCLK³

Receive Data Setup Before RCLK³

Receive Data Hold After RCLK³

External or Internal Clock Switching Characteristics

t_DFSE

TFS/RFS Delay After TCLK/RCLK (Internally

Generated FS)⁴

14

ns

t_HOFSE

TFS/RFS Hold After TCLK/RCLK (Internally

Generated FS)⁴

3

4

External Clock Switching Characteristics

t_DDTE

Transmit Data Delay After TCLK⁴

t_HDTE

Transmit Data Hold After TCLK⁴

13.4

ns

Internal Clock Switching Characteristics

t_DDTI

Transmit Data Delay After TCLK⁴

Transmit Data Hold After TCLK⁴

ns

t_HDTI

4

t_SCLKIW

TCLK/RCLK Width

0.5t_HCLK– 3.5

0.5t_HCLK+ 2.5

ns

Enable and Three-State Switching Characteristics⁵

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable from External TCLK⁴

Data Disable from External TCLK⁴

Data Enable from Internal TCLK⁴

Data Disable from External TCLK⁴

0

12.1

13

ns

13

12

External Late Frame Sync Switching Characteristics

t_DDTLFSE

Data Delay from Late External TFS with MCE=1, MFD=0^{6, 7}

Data Enable from Late FS or MCE=1, MFD=0^{6, 7}

10.5

ns

t_DTENLFSE

3.5

¹To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.

²Word selected timing for I²S mode is the same as TFS/RFS timing (normal framing only).

³Referenced to sample edge.

⁴Referenced to drive edge.

Rev. A

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ADSP-21990

⁵Only applies to SPORT.

⁶MCE=1, TFS enable, and TFS valid follow t_DDTENFSand t_DDTLFSE

.

⁷If external RFSD/TFS setup to RCLK/TCLK > 0.5t_LSCK, t_DDTLSCKand t_DTENLSCKapply; otherwise, t_DDTLFSEand t_DTENLFSapply.

DATA RECEIVE-INTERNAL CLOCK

DATA RECEIVE-EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

t_SCLKW

SAMPLE

EDGE

t_SCLKIW

RCLK

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

RFS

DR

RFS

DR

t_SDRE

t_HDRE

t_SDRI

t_HDRI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT-INTERNAL CLOCK

DATA TRANSMIT-EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

t_SCLKW

SAMPLE

EDGE

t_SCLKIW

TCLK

TFS

DT

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_SFSI

t_HFSI

t_HFSE

t_SFSE

TFS

DT

t_DDTI

t_DDTE

t_HDTI

t_HDTE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TCLK (EXT)

TFS (“LATE,” EXT)

TCLK/RCLK

t_DDTEN

t_DDTTE

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK (INT)

TFS (“LATE,” INT)

TCLK/RCLK

t_DDTIN

t_DDTTI

DT

Figure 13. Serial Port

Rev. A

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ADSP-21990

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

RCLK

t_{HOSFSE/ I}

t_SFSE/I

RFS

DT

t_{DDTE/ I}

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_{HOSFSE/ I}

t_SFSE/I

TFS

t_DDTE/I

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

DT

t_DDTLFSE

Figure 14. Serial Port—External Late Frame Sync (Frame Sync Setup > 0.5t_SCLK

)

Rev. A

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ADSP-21990

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

RCLK

t_SFSE/I

t_{HOFSE/ I}

RFS

t_DDTE/I

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

DT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_HOFSE/I

t_{SFSE/ I}

TFS

t_{DDTE/ I}

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

DT

t_DDTLFSE

Figure 15. Serial Port—External Late Frame Sync (Frame Sync Setup < 0.5t_HCLK

)

Rev. A

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ADSP-21990

Serial Peripheral Interface Port—Master Timing

Table 13 and Figure 16 describe SPI port master operations.

Table 13. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPID

t_HSPID

Data Input Valid to SCLK Edge (Data Input Setup)

8

1

ns

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

SPISEL Low to First SCLK Edge

2t_HCLK– 3

4t_HCLK– 1

2t_HCLK– 3

2t_HCLK– 2

0

ns

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCLK Edge to SPISEL High

Sequential Transfer Delay

t_SPITDM

t_DDSPID

t_HDSPID

SCLK Edge to Data Output Valid (Data Out Delay)

SCLK Edge to Data Output Invalid (Data Out Hold)

6

5

0

t_SPICHM

SPISEL

(OUTPUT)

t_HDSM

t_SPITDM

t_SPICLK

t_SDSCIM

t_SPICLM

SCLK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCLK

(CPOL = 1)

(OUTPUT)

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

t_SSPID

t_HSPID

CPHA = 1

LSB

MISO

MSB

VALID

(INPUT)

VALID

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

CPHA = 0

MSB

LSB

MISO

VALID

(INPUT)

Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. A

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ADSP-21990

Serial Peripheral Interface Port—Slave Timing

Table 14 and Figure 17 describe SPI port slave operations.

Table 14. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

Serial Clock High Period

2t_HCLK

4t_HCLK

2t_HCLK

2t_HCLK+ 4

2t_HCLK

1.6

ns

Serial Clock Low Period

Serial Clock Period

Last SPICLK Edge to SPISS Not Asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPISS Assertion to First SPICLK Edge

Data Input Valid to SCLK Edge (Data Input Setup)

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

2.4

Switching Characteristics

t_DSOE

SPISS Assertion to Data Out Active

0

8

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS Deassertion to Data High Impedance

SCLK Edge to Data Out Valid (Data Out Delay)

SCLK Edge to Data Out Invalid (Data Out Hold)

10

SPISS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCLK

(CPOL = 0)

(INPUT)

t_SPICLS

t_SDSCI

t_SPICHS

SCLK

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPIDt_HDSPID

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

t_SSPID

MSB

CPHA = 1

MOSI

(INPUT)

LSB

VALID

t_DDSPID

t_DSOE

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

CPHA = 0

t_SSPID

t_HSPID

MSB

VALID

LSB

VALID

MOSI

(INPUT)

Figure 17. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. A

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ADSP-21990

JTAG Test And Emulation Port Timing

Table 15 and Figure 18 describe JTAG port operations.

Table 15. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulse Width²

4

5

4t_TCK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

8

ns

0

22

¹System inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKIN, RESET.

²50 MHz maximum.

³System outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF15–0, DT, TCLK0, TCLK, RCLK, TFS, RFS, BMS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 18. JTAG Port Timing

Rev. A

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ADSP-21990

• Maximum peripheral speed CCLK = 80 MHz, HCLK =

80 MHz

POWER DISSIPATION

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

• External data memory writes occur every other cycle, a rate

of 1/(4t_HCLK), with 50% of the pins switching

• The bus cycle time is 80 MHz (t_HCLK= 12.5 ns)

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

The P_EXTequation is calculated for each class of pins that can

drive as shown in Table 16.

•

Number of output pins that switch during each cycle (O)

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation with

the following formula.

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

• Their voltage swing (V_DD

)

P

= P

+ P

TOTAL

INT

EXT

and is calculated by the formula below.

Where:

• P_EXTis from Table 16.

2

P

= O × C × V

× f

EXT

DD

• P_INTis I_DDINTϫ 2.5 V, using the calculation I_DDINTlisted in

Power Dissipation.

The load capacitance includes the processor package capaci-

tance (C_IN). The switching frequency includes driving the load

high and then back low. Address and data pins can drive high

and low at a maximum rate of 1/(2t_CK). The write strobe can

switch every cycle at a frequency of 1/t_CK. Select pins switch at

1/(2t_CK), but selects can switch on each cycle. For example, esti-

mate P_EXTwith the following assumptions:

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

• A system with one bank of external data memory—asyn-

chronous RAM (16-bit)

• One 64K

؋

16 RAM chip is used with a load of 10 pF

Table 16. P_EXTCalculation Example

2

Pin Type

Address

MSx

Number of Pins

% Switching

؋

C

؋

f

؋

V_DD

10.9 V

= P_EXT

15

1

50

0

10 pF

20 MHz

40 MHz

20 MHz

80 MHz

= 0.01635 W

= 0.0 W

WR

1

= 0.00436 W

= 0.01744 W

= 0.00872 W

= 0.04687 W

Data

16

1

50

CLKOUT

Rev. A

|

Page 40 of 50

|

August 2007

ADSP-21990

TEST CONDITIONS

INPUT

OR

OUTPUT

The DSP is tested for output enable, disable, and hold time.

1.5V

Output Disable Time

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ΔV is dependent on the capacitive load, C_L, and the

load current, I_L. This decay time can be approximated by the fol-

lowing equation.

Figure 21. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driv-

ing. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 19). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

C ΔV

L

--------------

t

=

DECAY

I

L

The output disable time t_DISis the difference between t_MEASURED

and t_DECAYas shown in Figure 19. The time t_MEASUREDis the inter-

val from when the reference signal switches to when the output

voltage decays ΔV from the measured output high or output low

voltage. The t_DECAYis calculated with test loads C_Land I_L, and

with ΔV equal to 0.5 V.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation at Output Disable Time

on Page 41. Choose ΔV to be the difference between the

ADSP-21990 output voltage and the input threshold for the

device requiring the hold time. A typical ΔV will be 0.4 V. C_Lis

the total bus capacitance (per data line), and I_Lis the total leak-

age or three-state current (per data line). The hold time will be

t_DECAYplus the minimum disable time (i.e., t_DATRWHfor the

write cycle).

REFERENCE

SIGNAL

t_MEASURED

t_ENA

t_DIS

V_{OH (MEASURED)}

V

_{OH (MEASURED)}– ⌬V 2.0V

V_{OL (MEASURED)}+ ⌬V 1.0V

V_{OL (MEASURED)}

t_DECAY

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

Figure 19. Output Enable/Disable

I

OL

TO

OUTPUT

1.5V

50pF

I

OH

Figure 20. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

Rev. A

|

Page 41 of 50

|

August 2007

ADSP-21990

PIN CONFIGURATIONS

Table 17 identifies the signal for each CSP_BGA ball number.

Table 4 on Page 16 describes each pin name.

Table 17. 196-Ball CSP_BGA Ball Number by Signal

Pin Name

A0

Ball No.

N1

Pin Name

CONVST

D0

Ball No.

G13

P10

N9

P9

Pin Name

Ball No.

E6

Pin Name

PF15

Ball No.

D14

H13

M11

N13

N14

M12

B2

nc

A1

N2

nc

E7

POR

A2

M1

M2

L1

D1

nc

E8

PWMPOL

PWMSYNC

PWMSR

PWMTRIP

RCLK

A3

D2

nc

E9

A4

D3

N8

P8

nc

E10

F5

A5

L2

D4

nc

A6

K1

D5

N7

P7

nc

F6

A7

K2

D6

nc

F7

RD

C2

A8

J1

D7

N6

P6

nc

F8

RESET

RFS

H14

A4

A9

J2

D8

nc

F9

A10

H1

D9

N5

P5

nc

F10

G5

SCK

B1

A11

H2

D10

D11

D12

D13

D14

D15

DR

nc

SENSE

TCK

B8

A12

G1

N4

P4

nc

G6

J13

B3

A13

G2

nc

G7

TCLK

A14

F1

N3

P3

nc

G8

TDI

J14

K14

B4

A15

F2

nc

G9

TDO

A16

E1

P2

nc

G10

H5

TFS

A17

E2

A2

nc

TMR0

H12

G12

F13

J12

K13

D11

E5

A18

D1

D2

D4

N11

M10

B6

DT

A3

nc

H6

TMR1

A19

EIA

E12

E13

E14

F12

K12

E4

nc

H7

TMR2

ACK

EIB

nc

H8

TMS

AH

EIS

nc

H9

TRST

AL

EIZ

nc

H10

J5

VDDEXT

VDDINT

VIN0

ASHAN

AUXTRIP

AUX1

AUX0

AVDD

AVSS

BG

EMU

GND

IOMS

MISO

MOSI

nc

D10

D12

D13

D5

D6

D7

D8

F3

nc

J6

H11

J4

E11

F4

nc

J7

nc

J8

L4

G11

H4

J11

K4

nc

J9

L6

nc

J10

M8

N12

P1

L9

nc

L10

M5

M7

G4

nc

K5

nc

BGH

BL

G3

K6

nc

P13

P14

A10

B10

C10

D9

P11

P12

M14

L13

L12

J3

K7

nc

L5

BH

K8

PF0/SPISS

PF1/SPISEL1

PF2/SPISEL2

PF3/SPISEL3

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8

L7

BMODE0

BMODE1

BMODE2

BMS

BR

K9

L8

K10

L11

M4

M6

D3

C3

K11

F11

A7

A11

B11

A12

A13

B12

C1

VIN1

A8

BSHAN

BYPASS

CAPB

A6

VIN2

B7

M13

B9

VIN3

A9

C4

VIN4

A5

Rev. A

|

Page 42 of 50

|

August 2007

ADSP-21990

Table 17. 196-Ball CSP_BGA Ball Number by Signal

Pin Name

CAPT

CH

Ball No.

C7

Pin Name

MS0

MS1

MS2

MS3

nc

Ball No.

K3

Pin Name

PF9

Ball No.

B13

Pin Name

VIN5

Ball No.

C6

N10

M9

L3

PF10

C11

VIN6

B5

CL

M3

PF11

C12

VIN7

C5

CLKIN

CLKOUT

CML

L14

H3

PF12

C13

VREF

WR

C8

G14

C9

A1

PF13

B14

E3

nc

A14

PF14

C14

XTAL

F14

Rev. A

|

Page 43 of 50

|

August 2007

ADSP-21990

Table 18 identifies the CSP_BGA ball number for each

signal name.

Table 18. 196-Ball CSP_BGA Signal by Ball Number

Ball No.

A1

Pin Name

nc

Ball No.

D8

D9

D10

D11

D12

D13

D14

E1

Pin Name

AVSS

PF3/SPISEL3

AUXTRIP

VDDEXT

AUX1

AUX0

PF15

A16

A17

WR

Ball No.

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

J1

Pin Name

A10

A11

MS3

GND

nc

Ball No.

L8

Pin Name

VDDINT

VDDEXT

GND

BMODE2

BMODE1

CLKIN

A2

DR

L9

A3

DT

L10

L11

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

N1

A4

RFS

A5

VIN4

A6

BSHAN

VIN0

nc

A7

nc

A8

VIN1

nc

A9

VIN3

E2

nc

A3

A10

A11

A12

A13

A14

B1

PF0/SPISS

PF4/SPISEL4

PF6/SPISEL6

PF7/SPISEL7

nc

E3

nc

MS2

E4

GND

VDDEXT

nc

VDDEXT

TMR0

POR

RESET

A8

GND

VDDEXT

GND

VDDEXT

nc

E5

E6

E7

nc

SCK

E8

nc

B2

RCLK

E9

nc

J2

A9

CL

B3

TCLK

E10

E11

E12

E13

E14

F1

nc

J3

BMS

VDDEXT

nc

AL

B4

TFS

GND

EIA

J4

PWMPOL

PWMTRIP

BYPASS

BMODE0

A0

B5

VIN6

J5

B6

ASHAN

VIN2

EIB

J6

nc

B7

EIS

J7

nc

B8

SENSE

CAPB

PF1/SPISEL1

PF5/SPISEL5

PF8

A14

A15

BG

J8

nc

B9

F2

J9

nc

N2

A1

B10

B11

B12

B13

B14

C1

F3

J10

J11

J12

J13

J14

K1

nc

N3

D13

F4

GND

nc

GND

TMS

TCK

TDI

N4

D11

F5

N5

D9

PF9

F6

nc

N6

D7

PF13

F7

nc

N7

D5

BR

F8

nc

A6

N8

D3

C2

RD

F9

nc

K2

A7

N9

D1

C3

MISO

MOSI

VIN7

F10

F11

F12

F13

F14

G1

nc

K3

MS0

GND

VDDINT

EMU

TRST

TDO

A4

N10

N11

N12

N13

N14

P1

CH

C4

VDDINT

EIZ

K4

AH

C5

K5

nc

C6

VIN5

TMR2

XTAL

A12

A13

BGH

VDDINT

nc

K6

PWMSYNC

PWMSR

nc

C7

CAPT

VREF

K7

C8

K8

C9

CML

G2

K9

P2

D15

C10

C11

C12

C13

C14

D1

PF2/SPISEL2

PF10

G3

K10

K11

K12

K13

K14

L1

P3

D14

G4

P4

D12

PF11

G5

P5

D10

PF12

G6

nc

P6

D8

PF14

G7

nc

P7

D6

A18

G8

nc

P8

D4

D2

A19

G9

nc

L2

A5

P9

D2

Rev. A

|

Page 44 of 50

|

August 2007

ADSP-21990

Table 18. 196-Ball CSP_BGA Signal by Ball Number

Ball No.

D3

Pin Name

IOMS

Ball No.

G10

Pin Name

nc

Ball No.

L3

Pin Name

MS1

Ball No.

P10

Pin Name

D0

BL

BH

nc

D4

ACK

G11

GND

L4

VDDEXT

VDDINT

VDDEXT

VDDINT

P11

D5

AVDD

AVSS

G12

TMR1

L5

P12

D6

G13

CONVST

CLKOUT

L6

P13

D7

G14

L7

P14

Rev. A

|

Page 45 of 50

|

August 2007

ADSP-21990

Table 19 identifies the signal for each LQFP lead.

Table 19. 176-Lead LQFP Signal by Lead Number

Lead No.

1

Signal

nc

Lead No.

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

Signal

VDDEXT

A4

Lead No.

89

Signal

nc

Lead No.

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

Signal

VDDEXT

PF11

2

nc

90

nc

3

VDDEXT

RCLK

SCK

MISO

MOSI

RD

A3

91

VDDEXT

BYPASS

BMODE0

BMODE1

BMODE2

nc

PF10

4

A2

92

PF9

5

A1

93

PF8

6

A0

94

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

GND

7

D15

D14

D13

D12

D11

GND

VDDEXT

GND

VDDINT

D10

D9

95

8

96

9

WR

97

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

ACK

BR

98

VDDINT

EMU

99

VDDEXT

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS

GND

BG

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

TRST

TDO

BGH

IOMS

BMS

MS3

GND

VDDEXT

MS2

MS1

MS0

GND

VDDINT

A19

A18

A17

A16

A15

A14

A13

GND

VDDEXT

A12

A11

A10

A9

TDI

TMS

TCK

POR

VDDINT

AVSS

D8

RESET

CLKIN

XTAL

CLKOUT

CONVST

TMR0

GND

D7

AVDD

nc

D6

D5

VREF

GND

VDDINT

D4

CML

CAPT

CAPB

D3

VDDEXT

TMR1

TMR2

EIS

SENSE

VIN3

D2

D1

VIN2

D0

VIN1

nc

GND

VIN0

GND

VDDEXT

CL

VDDINT

EIZ

ASHAN

BSHAN

VIN4

EIB

CH

EIA

VIN5

BL

AUXTRIP

AUX1

AUX0

PF15

PF14

PF13

PF12

GND

VIN6

BH

VIN7

AL

AVSS

A8

AH

AVDD

DT

A7

nc

A6

nc

DR

A5

PWMSYNC

PWMPOL

PWMSR

PWMTRIP

GND

RFS

GND

nc

TFS

nc

TCLK

nc

GND

nc

Rev. A

|

Page 46 of 50

|

August 2007

ADSP-21990

Table 20 identifies the LQFP lead for each signal name.

Table 20. 176-Lead LQFP Lead Number by Signal

Signal

A0

Lead No.

50

Signal

CAPB

CAPT

CH

Lead No.

156

155

77

Signal

EIS

Lead No.

116

119

99

Signal

PWMTRIP

RCLK

Lead No.

87

A1

49

EIZ

4

A10

35

EMU

RD

8

A11

34

CL

76

IOMS

MISO

MOSI

MS0

14

RESET

RFS

106

172

5

A12

33

CLKIN

CLKOUT

CML

CONVST

D0

107

109

154

110

72

6

A13

30

7

SCK

A14

29

21

SENSE

TCK

157

104

174

102

101

173

111

114

115

103

100

3

A15

28

MS1

20

A16

27

MS2

19

TCLK

A17

26

D1

71

MS3

16

TDI

A18

25

D10

D11

D12

D13

D14

D15

D2

60

nc

1

TDO

A19

24

55

nc

2

TFS

A2

48

54

nc

42

TMR0

TMR1

TMR2

TMS

A3

47

53

nc

43

A4

46

52

nc

44

A5

40

51

nc

83

A6

39

70

nc

89

TRST

A7

38

D3

69

nc

90

VDDEXT

VDDINT

VIN0

A8

37

D4

68

nc

96

18

A9

36

D5

65

nc

130

131

132

152

176

147

146

135

134

128

127

126

125

145

144

141

140

139

138

137

136

105

85

32

ACK

AH

10

D6

64

nc

45

81

D7

63

nc

57

AL

80

D8

62

nc

75

ASHAN

AUX0

AUX1

AUXTRIP

AVDD

AVSS

BG

162

124

123

122

151

169

150

168

12

D9

61

nc

91

GND

DR

17

PF0/SPISS

PF1/SPISEL1

PF10

113

133

143

23

22

31

41

PF11

56

PF12

59

58

PF13

67

66

PF14

98

74

PF15

118

149

161

160

159

158

164

165

166

167

153

9

BGH

BH

13

88

PF2/SPISEL2

PF3/SPISEL3

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8

79

97

BL

78

112

117

129

142

148

175

171

170

121

120

VIN1

BMODE0

BMODE1

BMODE2

BMS

BR

93

VIN2

94

VIN3

95

VIN4

15

VIN5

11

PF9

VIN6

BSHAN

BYPASS

nc

163

92

POR

VIN7

DT

PWMPOL

PWMSR

PWMSYNC

VREF

73

EIA

86

WR

nc

82

EIB

84

XTAL

108

Rev. A

|

Page 47 of 50

|

August 2007

ADSP-21990

OUTLINE DIMENSIONS

15.00

BSC

DETAIL B

SQ

13 12 11 10 9

8

6 5

7 4

14

3 2 1

A

B

C

D

E

F

G

H

J

13.00

BSC

1.00 BSC

K

L

M

N

P

1.85

1.70

1.55

1.00 BSC

TOP VIEW

DETAIL A

13.00 BSC

BOTTOM VIEW

0.75

0.70

0.65

1.10

1.00

0.90

0.55

NOM

1.10

1.00

0.90

0.57

0.52

0.47

0.70

0.60

0.50

0.20

MAX BALL

COPLANARITY

SEATING PLANE

BALL

DIAMETER

DETAIL A

DETAIL B

DIMENSIONS SHOWN IN MILLIMETERS

NOTES:

1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO

THE PACKAGE EDGES.

2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE TO THE

BALL GRID.

3. DIMENSIONS COMPLY WITH JEDEC STANDARD MO-192 VARIATION AAE-1 WITH THE EXCEPTION

OF MAXIMUM HEIGHT.

4. CENTER DIMENSIONS ARE NOMINAL.

Figure 22. 196-Ball CSP_BGA (BC-196-2)

Rev. A

|

Page 48 of 50

|

August 2007

ADSP-21990

26.20

26.00 SQ

25.80

0.75

0.60

0.45

1.60

MAX

133

132

176

1

PIN 1

24.20

24.00 SQ

23.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.15

0.05

89

44

45

SEATING

PLANE

0.08 MAX

88

COPLANARITY

VIEW A

0.27

0.22

0.17

0.50

BSC

VIEW A

ROTATED 90° CCW

LEAD PITCH

DIMENSIONS SHOWN IN MILLIMETERS

176-LEAD LOW PROFILE QUAD FLAT PACKAGE [LQFP] ST-176

NOTES:

1. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION,

WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE NOMINAL.

3. DIMENSIONS COMPLY WITH JEDEC STANDARD MS-026-BGA

Figure 23. 176-Lead LQFP (ST-176)

ORDERING GUIDE

Model

Temperature Range¹Instruction Rate Operating Voltage Package Description

Package Option

BC-196-2

ST-176

ADSP-21990BBC

ADSP-21990BST

ADSP-21990BSTZ²

–40ЊC to +85ЊC

150 MHz

160 MHz

2.5 Int. V/3.3 Ext. V 196-Ball CSP_BGA

2.5 Int. V/3.3 Ext. V 176-Lead LQFP

ST-176

¹Referenced temperature is ambient temperature.

²Z = RoHS Compliant Part.

Rev. A

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Page 49 of 50

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August 2007

ADSP-21990

registered trademarks are the property of their respective owners.

D02893-0-8/07(A)

Rev. A

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Page 50 of 50

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August 2007


型号：	ADSP-21990BCA
厂家：	ADI
描述：	IC 0-BIT, 160 MHz, OTHER DSP, PBGA196, MINI, BGA-196, Digital Signal Processor 时钟外围集成电路
文件：	总50页 (文件大小：1241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21990BCA [ADI]

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