ADSP-21992BSTZ_技术文档

Mixed-Signal DSP Controller with CAN

ADSP-21992

Dual 16-bit auxiliary PWM outputs

FEATURES

16 general-purpose flag I/O pins

ADSP-2199x, 16-bit, fixed-point DSP core with up to 160

MIPS sustained performance

48K words of on-chip RAM, as 32K words on-chip 24-bit pro-

gram RAM, and 16K words on-chip, 16-bit data RAM

External memory interface

Dedicated memory DMA controller for data/instruction

transfer between internal/external memory

Programmable PLL and flexible clock generation circuitry

enables full-speed operation from low speed

input clocks

3 programmable 32-bit interval timers

SPI communications port with master or slave operation

Synchronous serial communications port (SPORT) capable of

software UART emulation

Controller area network (CAN) module, fully compliant with

V2.0B standard

Integrated watchdog timer

Dedicated peripheral interrupt controller with software

priority control

Multiple boot modes

IEEE JTAG Standard 1149.1 test access port supports on-chip

emulation and system debugging

Precision 1.0 V voltage reference

Integrated power-on-reset (POR) generator

Flexible power management with selectable power-down

and idle modes

2.5 V internal operation with 3.3 V I/O

Operating temperature ranges of –40ЊC to +85ЊC and –40ЊC

to +125ЊC

8-channel, 14-bit analog-to-digital converter system, with up

to 20 MSPS sampling rate (at 160 MHz core clock rate)

3-phase 16-bit center based PWM generation unit with 12.5

ns resolution at 160 MHz core clock (CCLK) rate

Dedicated 32-bit encoder interface unit with companion

encoder event timer

CLOCK

GENERATOR/PLL

16K ϫ 16

DM RAM

4K ϫ 24

PM ROM

32K ϫ 24

PM RAM

JTAG

TEST AND

EMULATION

ADSP-219x

DSP CORE

ADDRESS

EXTERNAL

MEMORY

INTERFACE

(EMI)

DATA

I/O

BUS

PM ADDRESS/DATA

DM ADDRESS/DATA

CONTROL

I/O REGISTERS

CONTROLLER AREA

NETWORK (CAN)

MEMORY DMA

CONTROLLER

SPI

SPORT

PWM

GENERATION

ENCODER

INTERFACE

UNIT

(AND EET)

TIMER 0

ADC

CONTROL

PIPELINE

FLASH ADC

INTERRUPT

CONTROLLER

AUXILIARY

PWM

UNIT

WATCHDOG

TIMER

TIMER 1

TIMER 2

FLAG

I/O

UNIT

(ICNTL)

POR

VREF

Figure 1. Functional Block Diagram

Rev. A

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ADSP-21992

TABLE OF CONTENTS

General Description ................................................. 3

DSP Core Architecture ........................................... 3

Memory Architecture ............................................ 5

Bus Request and Bus Grant ..................................... 6

DMA Controller ................................................... 7

DSP Peripherals Architecture .................................. 7

Serial Peripheral Interface (SPI) Port ......................... 7

DSP Serial Port (SPORT) ........................................ 8

Controller Area Network (CAN) Module ................... 9

Analog-to-Digital Conversion System ........................ 9

Voltage Reference ................................................. 9

PWM Generation Unit ......................................... 10

Auxiliary PWM Generation Unit ............................ 10

Encoder Interface Unit ......................................... 10

Flag I/O (FIO) Peripheral Unit ............................... 11

Watchdog Timer ................................................ 11

General-Purpose Timers ....................................... 11

Interrupts ......................................................... 11

Peripheral Interrupt Controller .............................. 12

Low Power Operation .......................................... 12

Clock Signals ..................................................... 13

Reset and Power-On Reset (POR) ........................... 13

Power Supplies ................................................... 14

Booting Modes ................................................... 14

Instruction Set Description .................................... 14

Development Tools .............................................. 15

Designing an Emulator-Compatible DSP Board .......... 16

Additional Information ........................................ 16

Pin Function Descriptions ........................................ 17

Specifications ........................................................ 20

Operating Conditions ........................................... 20

Electrical Characteristics ....................................... 23

Absolute Maximum Ratings ................................... 30

ESD Caution ...................................................... 30

Timing Specifications ........................................... 30

Power Dissipation ............................................... 50

Test Conditions ..................................................... 51

Output Disable Time ............................................ 51

Output Enable Time ............................................ 51

Example System Hold Time Calculation ................... 51

Pin Configurations ................................................. 52

Outline Dimensions ................................................ 57

Ordering Guide ..................................................... 59

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Added RoHS part number to Ordering Guide ............... 59

Rev. A

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ADSP-21992

GENERAL DESCRIPTION

The ADSP-21992 is a mixed-signal DSP controller based on the

ADSP-2199x DSP core, suitable for a variety of high perfor-

mance industrial motor control and signal processing

applications that require the combination of a high performance

DSP and the mixed-signal integration of embedded control

peripherals, such as analog-to-digital conversion with commu-

nications interfaces such as CAN. Target applications include

industrial motor drives, uninterruptible power supplies, optical

networking control, data acquisition systems, test and measure-

ment Systems, and portable instrumentation.

• Decrement the timers.

• Operate the embedded control peripherals (ADC, PWM,

EIU, etc.).

DSP CORE ARCHITECTURE

• 6.25 ns instruction cycle time (internal), for up to

160 MIPS sustained performance (6.67 ns instruction cycle

time for 150 MIPS sustained performance and 10.0 ns

instruction cycle time for 100 MIPS sustained

performance).

The ADSP-21992 integrates the fixed-point ADSP-2199x fam-

ily-based architecture with a serial port, an SPI-compatible port,

a DMA controller, three programmable timers, general-purpose

programmable flag pins, extensive interrupt capabilities, on-

chip program and data memory spaces, and a complete set of

embedded control peripherals that permits fast motor control

and signal processing in a highly integrated environment.

• ADSP-218x family code compatible with the same easy to

use algebraic syntax.

• Single cycle instruction execution.

• Up to 1M words of addressable memory space with 24 bits

of addressing width.

• Dual-purpose program memory for both instruction and

data storage.

The ADSP-21992 architecture is code compatible with previous

ADSP-217x-based ADMCxxx products. Although the architec-

tures are compatible, the ADSP-21992, with ADSP-2199x

architecture, has a number of enhancements over earlier archi-

tectures. The enhancements to computational units, data

address generators, and program sequencer make the

ADSP-21992 more flexible and easier to program than the pre-

vious ADSP-21xx embedded DSPs.

• Fully transparent instruction cache allows dual operand

fetches in every instruction cycle.

• Unified memory space permits flexible address generation,

using two independent DAG units.

• Independent ALU, multiplier/accumulator, and barrel

shifter computational units with dual 40-bit accumulators.

Indirect addressing options provide addressing flexibility—pre-

modify with no update, pre- and post-modify by an immediate

8-bit, twos complement value and base address registers for eas-

ier implementation of circular buffering.

• Single cycle context switch between two sets of computa-

tional and DAG registers.

• Parallel execution of computation and memory

instructions.

The ADSP-21992 integrates 48K words of on-chip memory

configured as 32K words (24-bit) of program RAM, and 16K

words (16-bit) of data RAM.

• Pipelined architecture supports efficient code execution at

speeds up to 160 MIPS.

• Register file computations with all nonconditional, non-

parallel computational instructions.

Fabricated in a high speed, low power, CMOS process, the

ADSP-21992 operates with a 6.25 ns instruction cycle time for a

160 MHz CCLK, with a 6.67 ns instruction cycle time for a

150 MHz CCLK, and with a 10.0 ns instruction cycle time for a

100 MHz CCLK. All instructions, except two multiword

instructions, execute in a single DSP cycle.

• Powerful program sequencer provides zero overhead loop-

ing and conditional instruction execution.

• Architectural enhancements for compiled C code

efficiency.

The flexible architecture and comprehensive instruction set of

the ADSP-21992 support multiple operations in parallel. For

example, in one processor cycle, the ADSP-21992 can:

• Architecture enhancements beyond ADSP-218x family are

supported with instruction set extensions for added regis-

ters, ports, and peripherals.

• Generate an address for the next instruction fetch.

• Fetch the next instruction.

The clock generator module of the ADSP-21992 includes clock

control logic that allows the user to select and change the main

clock frequency. The module generates two output clocks: the

DSP core clock, CCLK; and the peripheral clock, HCLK. CCLK

can sustain clock values of up to 160 MHz, while HCLK can be

equal to CCLK or CCLK/2 for values up to a maximum 80 MHz

peripheral clock at the 160 MHz CCLK rate.

• Perform one or two data moves.

• Update one or two data address pointers.

• Perform a computational operation.

These operations take place while the processor continues to:

• Receive and transmit data through the serial port.

• Receive or transmit data over the SPI port.

The ADSP-21992 instruction set provides flexible data moves

and multifunction (one or two data moves with a computation)

instructions. Every single word instruction can be executed in a

single processor cycle. The ADSP-21992 assembly language uses

• Access external memory through the external memory

interface.

Rev. A

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ADSP-21992

INTERNAL MEMORY

FOUR INDEPENDENT BLOCKS

24 BIT

DATA

ADDRESS

ADDRESS24 BIT

16 BIT

ADSP-219x DSP CORE

JTAG

TEST AND

EMULATION

6

CACHE

64 ꢀ 24-BIT

ADDRESS

ADDRESS16 BIT

DAG1

4 ꢀ 4 ꢀ 16

DAG2

4 ꢀ 4 ꢀ 16

PROGRAM

SEQUENCER

EXTERNAL PORT

PM ADDRESS BUS

24

I/O ADDRESS

ADDR BUS

MUX

18

20

DM ADDRESS BUS

PX

24

DMA CONNECT

DMA ADDRESS

24

DATA BUS

MUX

DMA DATA

PM DATA BUS

DM DATA BUS

I/O DATA

24

16

DATA

REGISTER

FILE

I/O PROCESSOR

INPUT

REGISTERS

RESULT

REGISTERS

16 ꢀ 16-BIT

I/O REGISTERS

(MEMORY-MAPPED)

EMBEDDED

CONTROL

PERIPHERALS

BARREL

SHIFTER

MULT

ALU

CONTROL

STATUS

BUFFERS

AND

COMMUNICATIONS

PORTS

DMA CONTROLLER

3

SYSTEM INTERRUPT

CONTROLLER

TIMERS

(3)

PROGRAMMABLE

FLAGS (16)

Figure 2. Block Diagram

an algebraic syntax for ease of coding and readability. A com-

prehensive set of development tools supports program

development.

A powerful program sequencer controls the flow of instruction

execution. The sequencer supports conditional jumps, subrou-

tine calls, and low interrupt overhead. With internal loop

counters and loop stacks, the ADSP-21992 executes looped code

with zero overhead; no explicit jump instructions are required

to maintain loops.

The block diagram (Figure 2) shows the architecture of the

embedded SHARC core. It contains three independent compu-

tational units: the ALU, the multiplier/accumulator (MAC), and

the shifter. The computational units process 16-bit data from

the register file and have provisions to support multiprecision

computations. The ALU performs a standard set of arithmetic

and logic operations; division primitives are also supported. The

MAC performs single cycle multiply, multiply/add, and multi-

ply/subtract operations. The MAC has two 40-bit accumulators,

which help with overflow. The shifter performs logical and

arithmetic shifts, normalization, denormalization, and derive

exponent operations. The shifter can be used to efficiently

implement numeric format control, including multiword and

block floating-point representations.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four 16-bit

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is pre- or post-modified by the value of

one of four possible modify registers. A length value and base

address may be associated with each pointer to implement auto-

matic modulo addressing for circular buffers. Page registers in

the DAGs allow circular addressing within 64K word bound-

aries of each of the 256 memory pages, but these buffers may not

cross page boundaries. Secondary registers duplicate all the pri-

mary registers in the DAGs; switching between primary and

secondary registers provides a fast context switch.

Register usage rules influence placement of input and results

within the computational units. For most operations, the data

registers of the computational units act as a data register file,

permitting any input or result register to provide input to any

unit for a computation. For feedback operations, the computa-

tional units let the output (result) of any unit be input to any

unit on the next cycle. For conditional or multifunction instruc-

tions, there are restrictions on which data registers may provide

inputs or receive results from each computational unit. For

more information, see the ADSP-2199x DSP Instruction Set

Reference.

Efficient data transfer in the core is achieved with the use of

internal buses:

• Program memory address (PMA) bus

• Program memory data (PMD) bus

• Data memory address (DMA) bus

• Data memory data (DMD) bus

• Direct memory access address bus

• Direct memory access data bus

Rev. A

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ADSP-21992

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Boot memory space and I/O memory space also share the

external buses.

0x00 0000

BLOCK 0: 16K ꢀ 24-BIT PM RAM

0x00 3FFF

0x00 4000

Program memory can store both instructions and data, permit-

ting the ADSP-21992 to fetch two operands in a single cycle, one

from program memory and one from data memory. The DSP

dual memory buses also let the embedded SHARC core fetch an

operand from data memory and the next instruction from pro-

gram memory in a single cycle.

BLOCK 1: 16K ꢀ 24-BIT PM RAM

BLOCK 2: 16K ꢀ 16-BIT DM RAM

0x00 7FFF

0x00 8000

PAGE 0 (64K) ON-CHIP

(0 WAIT STATE)

0x00 BFFF

0x00 C000

RESERVED (16K)

0x00 FFFF

0x01 0000

PAGES 1 TO 63 BANK 0

(OFF-CHIP) MS0

EXTERNAL MEMORY

(4M–64K)

0x40 0000

0x80 0000

0xC0 0000

MEMORY ARCHITECTURE

PAGES 64 TO 127 BANK 1

EXTERNAL MEMORY (4M)

MS1

(OFF-CHIP)

The ADSP-21992 provides 48K words of on-chip SRAM mem-

ory. This memory is divided into three blocks: two 16K × 24-bit

blocks (Blocks 0 and 1) and one 16K × 16-bit block (Block 2). In

addition, the ADSP-21992 provides a 4K × 24-bit block of pro-

gram memory boot ROM (that is reserved by ADI for boot load

routines). The memory map of the ADSP-21992 is illustrated in

Figure 2.

PAGES 128 TO 191 BANK 2

(OFF-CHIP)

MS2

PAGES 192 TO 254 BANK 3

EXTERNAL MEMORY

(4M–64K)

(OFF-CHIP)

MS3

0xFF 0000

BLOCK 3: 4K ꢀ 24-BIT

PM ROM

PAGE 255

(INCLUDES ON-CHIP BOOT ROM)

0xFF 0FFF

0xFF 1000

As shown in Figure 2, the three internal memory RAM blocks

reside in memory page 0. The entire DSP memory map consists

of 256 pages (Pages 0 to 255), and each page is 64K words long.

External memory space consists of four memory banks

UNUSED ON-CHIP

MEMORY (60K)

0xFF FFFF

Figure 3. Core Memory Map at Reset

(Banks3–0) and supports a wide variety of memory devices.

Each bank is selectable using unique memory select lines

(MS3–0) and has configurable page boundaries, wait states, and

wait state modes. The 4K words of on-chip boot ROM populates

the top of Page 255, while the remaining 254 pages are address-

able off-chip. I/O memory pages differ from external memory in

that they are 1K word long, and the external I/O pages have

their own select pin (IOMS). Pages 31–0 of I/O memory space

reside on-chip and contain the configuration registers for the

peripherals. Both the ADSP-2199x core and DMA capable

peripherals can access the entire memory map of the DSP.

Internal (On-Chip) Memory

The unified program and data memory space of the

ADSP-21992 consists of 16M locations that are accessible

through two 24-bit address buses, the PMA, and DMA buses.

The DSP uses slightly different mechanisms to generate a 24-bit

address for each bus. The DSP has three functions that support

access to the full memory map.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG index

(address) registers are 16 bits wide and hold the lower

16 bits of the address, each of the DAGs has its own 8-bit

page register (DMPGx) to hold the most significant eight

address bits. Before a DAG generates an address, the pro-

gram must set the DAG DMPGx register to the appropriate

memory page. The DMPG1 register is also used as a page

register when accessing external memory. The program

must set DMPG1 accordingly, when accessing data vari-

ables in external memory. A “C” program macro is

provided for setting this register.

NOTE: The physical external memory addresses are limited by

20 address lines, and are determined by the external data width

and packing of the external memory space. The Strobe signals

(MS3-0) can be programmed to allow the user to change start-

ing page addresses at runtime.

• The program sequencer generates the addresses for

instruction fetches. For relative addressing instructions, the

program sequencer bases addresses for relative jumps, calls,

and loops on the 24-bit program counter (PC). In direct

addressing instructions (two word instructions), the

instruction provides an immediate 24-bit address value.

The PC allows linear addressing of the full 24-bit

address range.

• For indirect jumps and calls that use a 16-bit DAG address

register for part of the branch address, the program

sequencer relies on an 8-bit indirect jump page (IJPG)

Rev. A

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ADSP-21992

register to supply the most significant eight address bits.

Before a cross page jump or call, the program must set the

program sequencer IJPG register to the appropriate mem-

ory page.

255) are available for external peripheral devices. External I/O

pages have their own select pin (IOMS). The DSP instruction set

provides instructions for accessing I/O space.

The ADSP-21992 has 4K words of on-chip ROM that holds

boot routines. The DSP starts executing instructions from the

on-chip boot ROM, which starts the boot process. For more

information, see Booting Modes on Page 14. The on-chip boot

ROM is located on Page 255 in the DSP memory space map,

starting at address 0xFF0000.

0x00::0x000

ON-CHIP

PAGES 0 TO 31

PERIPHERALS

16-BITS

1024 WORDS/PAGE

2 PERIPHERALS/PAGE

0x1F::0x3FF

0x20::0x000

External (Off-Chip) Memory

Each of the off-chip memory spaces of the ADSP-21992 has a

separate control register, so applications can configure unique

access parameters for each space. The access parameters include

read and write wait counts, wait state completion mode, I/O

clock divide ratio, write hold time extension, strobe polarity,

and data bus width. The core clock and peripheral clock ratios

influence the external memory access strobe widths. For more

information, see Clock Signals on Page 13. The off-chip mem-

ory spaces are:

OFF-CHIP

PERIPHERALS

16-BITS

PAGES 32 TO 255

1024 WORDS/PAGE

0xFF::0x3FF

Figure 4. I/O Memory Map

Boot Memory Space

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

Boot memory space consists of one off-chip bank with 254

pages. The BMS memory bank pin selects boot memory space.

Both the ADSP-2199x core and DMA capable peripherals can

access the DSP off-chip boot memory space. After reset, the

DSP always starts executing instructions from the on-chip

boot ROM.

All of these off-chip memory spaces are accessible through the

external port, which can be configured for 8-bit or 16-bit

data widths.

External Memory Space

0x01 0000

External memory space consists of four memory banks. These

banks can contain a configurable number of 64K word pages. At

reset, the page boundaries for external memory have Bank0

containing pages 1 to 63, Bank1 containing pages 64 to 127,

Bank2 containing pages 128 to 191, and Bank3 containing pages

192 to 254. The MS3-0 memory bank pins select Banks 3-0,

respectively. Both the ADSP-2199x core and DMA capable

peripherals can access the DSP external memory space.

OFF-CHIP

BOOT MEMORY

PAGES 1 TO 254

16-BITS

64K WORDS/PAGE

0xFE 0000

All accesses to external memory are managed by the external

memory interface unit (EMI).

Figure 5. Boot Memory Map

BUS REQUEST AND BUS GRANT

I/O Memory Space

The ADSP-21992 can relinquish control of the data and address

buses to an external device. When the external device requires

access to the bus, it asserts the bus request (BR) signal. The (BR)

signal is arbitrated with core and peripheral requests. External

bus requests have the lowest priority. If no other internal

request is pending, the external bus request will be granted. Due

to synchronizer and arbitration delays, bus grants will be pro-

vided with a minimum of three peripheral clock delays. The

ADSP-21992 will respond to the bus grant by:

The ADSP-21992 supports an additional external memory

called I/O memory space. The I/O space consists of 256 pages,

each containing 1024 addresses. This space is designed to sup-

port simple connections to peripherals (such as data converters

and external registers) or to bus interface ASIC data registers.

The first 32K addresses (I/O pages 0 to 31) are reserved for on-

chip peripherals. The upper 224K addresses (I/O pages 32 to

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

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ADSP-21992

The ADSP-21992 will halt program execution if the bus is

granted to an external device and an instruction fetch or data

read/write request is made to external general-purpose or

peripheral memory spaces. If an instruction requires two exter-

nal memory read accesses, the bus will not be granted between

the two accesses. If an instruction requires an external memory

read and an external memory write access, the bus may be

granted between the two accesses. The external memory inter-

face can be configured so that the core will have exclusive use of

the interface. DMA and bus requests will be granted. When the

external device releases BR, the DSP releases BG and continues

program execution from the point at which it stopped.

DSP PERIPHERALS ARCHITECTURE

The ADSP-21992 contains a number of special purpose, embed-

ded control peripherals, which can be seen in the functional

block diagram on Page 1. The ADSP-21992 contains a high per-

formance, 8-channel, 14-bit ADC system with dual-channel

simultaneous sampling ability across four pairs of inputs. An

internal precision voltage reference is also available as part of

the ADC system. In addition, a 3-phase, 16-bit, center-based

PWM generation unit can be used to produce high accuracy

PWM signals with minimal processor overhead. The

ADSP-21992 also contains a flexible incremental encoder inter-

face unit for position sensor feedback; two adjustable frequency

auxiliary PWM outputs, 16 lines of digital I/O; a 16-bit watch-

dog timer; three general-purpose timers, and an interrupt

controller that manages all peripheral interrupts. Finally, the

ADSP-21992 contains an integrated power-on-reset (POR) cir-

cuit that can be used to generate the required reset signal for

device power-on.

The bus request feature operates at all times, even while the DSP

is booting and RESET is active.

The ADSP-21992 asserts the BGH pin when it is ready to start

another external port access, but is held off because the bus was

previously granted. This mechanism can be extended to define

more complex arbitration protocols for implementing more

elaborate multimaster systems.

The ADSP-21992 has an external memory interface that is

shared by the DSP core, the DMA controller, and DMA capable

peripherals, which include the ADC, SPORT, and SPI commu-

nication ports. The external port consists of a 16-bit data bus, a

20-bit address bus, and control signals. The data bus is config-

urable to provide an 8- or 16-bit interface to external memory.

Support for word packing lets the DSP access 16- or 24-bit

words from external memory regardless of the external data

bus width.

DMA CONTROLLER

The ADSP-21992 has a DMA controller that supports auto-

mated data transfers with minimal overhead for the DSP core.

Cycle stealing DMA transfers can occur between the

ADSP-21992 internal memory and any of its DMA capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA capable peripherals and external

devices connected to the external memory interface. DMA

capable peripherals include the SPORT and SPI ports, and ADC

control module. Each individual DMA capable peripheral has a

dedicated DMA channel. To describe each DMA sequence, the

DMA controller uses a set of parameters—called a DMA

descriptor. When successive DMA sequences are needed, these

DMA descriptors can be linked or chained together, so the com-

pletion of one DMA sequence autoinitiates and starts the next

sequence. DMA sequences do not contend for bus access with

the DSP core, instead DMAs “steal” cycles to access memory.

The memory DMA controller lets the ADSP-21992 move data

and instructions from between memory spaces: internal-to-

external, internal-to-internal, and external-to-external. On-chip

peripherals can also use this controller for DMA transfers.

The embedded SHARC core can respond to up to 17 interrupts

at any given time: three internal (stack, emulator kernel, and

power-down), two external (emulator and reset), and 12 user-

defined (peripherals) interrupts. Programmers assign each of

the 32 peripheral interrupt requests to one of the 12 user-

defined interrupts. These assignments determine the priority of

each peripheral for interrupt service.

All DMA transfers use the DMA bus shown in Figure 2 on

Page 4. Because all of the peripherals use the same bus, arbitra-

tion for DMA bus access is needed. The arbitration for DMA

bus access appears in Table 1.

The following sections provide a functional overview of the

ADSP-21992 peripherals.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

Table 1. I/O Bus Arbitration Priority

The serial peripheral interface (SPI) port provides functionality

for a generic configurable serial port interface based on the SPI

standard, which enables the DSP to communicate with multiple

SPI-compatible devices. Key features of the SPI port are:

DMA Bus Master

Arbitration Priority

SPORT Receive DMA

SPORT Transmit DMA

ADC Control DMA

SPI Receive/Transmit DMA

Memory DMA

0—Highest

• Interface to host microcontroller or serial EEPROM.

1

• Master or slave operation (3-wire interface MISO, MOSI,

SCK).

2

• Data rates to HCLK ꢁ 4 (16-bit baud rate selector).

• 8- or 16-bit transfer.

3

4—Lowest

• Programmable clock phase and polarity.

• Broadcast Mode–1 master, multiple slaves.

• DMA capability and dedicated interrupts.

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ADSP-21992

• PF0 can be used as slave select input line.

The slave mode transmit operation is similar, except the DSP

core specifies the data buffer in memory space, generates and

relinquishes control of the transmit DMA descriptor, and

begins filling the SPI port data buffer. If the SPI controller is not

ready on time to transmit, it can transmit a “zero” word.

• PF1–PF7 can be used as external slave select output.

SPI is a 3-wire interface consisting of 2 data pins (MOSI and

MISO), one clock pin (SCK), and a single slave select input

(SPISS) that is multiplexed with the PF0 Flag I/O line and seven

slave select outputs (SPISEL1 to SPISEL7) that are multiplexed

with the PF1 to PF7 flag I/O lines. The SPISS input is used to

select the ADSP-21992 as a slave to an external master. The

SPISEL1 to SPISEL7 outputs can be used by the ADSP-21992

(acting as a master) to select/enable up to seven external slaves

in a multidevice SPI configuration. In a multimaster or a multi-

device configuration, all MOSI pins are tied together, all MISO

pins are tied together, and all SCK pins are tied together.

DSP SERIAL PORT (SPORT)

The ADSP-21992 incorporates a complete synchronous serial

port (SPORT) for serial and multiprocessor communications.

The SPORT supports the following features:

• Bidirectional: The SPORT has independent transmit and

receive sections.

• Double buffered: The SPORT section (both receive and

transmit) has a data register for transferring data words to

and from other parts of the processor and a register for

shifting data in or out. The double buffering provides addi-

tional time to service the SPORT.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on the serial data

line. The serial clock line synchronizes the shifting and sam-

pling of data on the serial data line.

• Clocking: The SPORT can use an external serial clock or

generate its own in a wide range of frequencies down to

0 Hz.

In master mode, the DSP core performs the following sequence

to set up and initiate SPI transfers:

• Enables and configures the SPI port operation (data size

and transfer format).

• Word length: Each SPORT section supports serial data

word lengths from three to 16 bits that can be transferred

either MSB first or LSB first.

• Selects the target SPI slave with the SPISELx output pin

(reconfigured programmable flag pin).

• Framing: Each SPORT section (receive and transmit) can

operate with or without frame synchronization signals for

each data-word; with internally generated or externally

generated frame signals; with active high or active low

frame signals; with either of two pulse widths and frame

signal timing.

• Defines one or more DMA descriptors in Page 0 of I/O

memory space (optional in DMA mode only).

• Enables the SPI DMA engine and specifies transfer direc-

tion (optional in DMA mode only).

• In nonDMA mode only, reads or writes the SPI port

receive or transmit data buffer.

• Companding in hardware: Each SPORT section can per-

form A law and μ law companding according to CCITT

recommendation G.711.

The SCK line generates the programmed clock pulses for simul-

taneously shifting data out on MOSI and shifting data in on

MISO. In DMA mode only, transfers continue until the SPI

DMA word count transitions from 1 to 0.

• Direct memory access with single cycle overhead: Using the

built-in DMA master, the SPORT can automatically receive

and/or transmit multiple memory buffers of data with an

overhead of only one DSP cycle per data-word. The on-

chip DSP, via a linked list of memory space resident DMA

descriptor blocks, can configure transfers between the

SPORT and memory space. This chained list can be

dynamically allocated and updated.

In slave mode, the DSP core performs the following sequence to

set up the SPI port to receive data from a master transmitter:

• Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size and

transfer format) SPI transmitter.

• Defines and generates a receive DMA descriptor in Page 0

of memory space to interrupt at the end of the data transfer

(optional in DMA mode only).

• Interrupts: Each SPORT section (receive and transmit)

generates an interrupt upon completing a data-word trans-

fer, or after transferring an entire buffer or buffers if DMA

is used.

• Enables the SPI DMA engine for a receive access (optional

in DMA mode only).

• Multichannel capability: The SPORT can receive and trans-

mit data selectively from channels of a serial bit stream that

is time division multiplexed into up to 128 channels. This is

especially useful for T1 interfaces or as a network commu-

nication scheme for multiple processors. The SPORTs also

support T1 and E1 carrier systems.

• Starts receiving the data on the appropriate SCK edges after

receiving an SPI chip select on the SPISS input pin (recon-

figured programmable flag pin) from a master.

In DMA mode only, reception continues until the SPI DMA

word count transitions from 1 to 0. The DSP core could con-

tinue, by queuing up the next DMA descriptor.

• DMA Buffer: Each SPORT channel (Tx and Rx) supports a

DMA buffer of up to eight 16-bit transfers.

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• SPORT operates at a frequency of up to one-half the clock

frequency of the HCLK.

ADSP-21992 CAN module represents only the controller part of

the interface. The network I/O of this module is a single trans-

mit line and a single receive line, which communicate to a line

transceiver.

• SPORT: Capable of UART software emulation.

CONTROLLER AREA NETWORK (CAN) MODULE

ANALOG-TO-DIGITAL CONVERSION SYSTEM

The ADSP-21992 contains a controller area network (CAN)

module. Key features of the CAN module are:

The ADSP-21992 contains a fast, high accuracy, multiple input

analog-to-digital conversion system with simultaneous sam-

pling capabilities. This analog-to-digital conversion system

permits the fast, accurate conversion of analog signals needed in

high performance embedded systems. Key features of the ADC

system are:

• Conforms to the CAN V2.0B standard.

• Supports both standard (11-bit) and extended (29-bit)

identifiers.

Supports data rates of up to 1 Mbps (and higher).

• 16 configurable mailboxes (all receive or transmit).

• Dedicated acceptance mask for each mailbox.

• 14-bit pipeline (6-stage pipeline) flash analog-to-digital

converter.

• 8 dedicated analog inputs.

• Data filtering (first 2 bytes) which can be used for accep-

tance filtering.

• Dual-channel simultaneous sampling capability.

• Programmable ADC clock rate to maximum of HCLK ꢁ 4.

• Error status and warning registers.

• Transmit priority by identifier.

• Universal counter module.

• First channel ADC data valid approximately 375 ns after

CONVST (at 20 MSPS).

• All 8 inputs converted in approximately 725 ns (at

20 MSPS).

• Readable receive and transmit counters.

The CAN module is a low baud rate serial interface intended for

use in applications where baud rates are typically under 1 Mbps.

The CAN protocol incorporates a data CRC check, message

error tracking and fault node confinement as means to improve

network reliability to the level required for control applications.

• 2.0 V peak-to-peak input voltage range.

• Multiple convert start sources.

• Internal or external voltage reference.

• Out of range detection.

The CAN module architecture is based around a 16-entry mail-

box RAM. The mailbox is accessed sequentially by the CAN

serial interface or the host CPU. Each mailbox consists of eight

16-bit data words. The data is divided into fields, which includes

a message identifier, a time stamp, a byte count, up to 8 bytes of

data, and several control bits. Each node monitors the messages

being passed on the network. If the identifier in the transmitted

message matches an identifier in one of its mailboxes, then the

module knows that the message was meant for it, passes the data

into its appropriate mailbox, and signals the host of its arrival

with an interrupt.

• DMA capable transfers from ADC to memory.

The ADC system is based on a pipeline flash converter core, and

contains dual input sample-and-hold amplifiers so that simulta-

neous sampling of two input signals is supported. The ADC

system provides an analog input voltage range of 2.0 V p-p and

provides 14-bit performance with a clock rate of up to

HCLK ꢁ 4. The ADC system can be programmed to operate at

a clock rate from HCLK⁄4 to HCLK⁄30, to a maximum clock rate

of 20 MHz (at 160 MHz CCLK rate).

The ADC input structure supports eight independent analog

inputs; four of which are multiplexed into one sample-and-hold

amplifier (A_SHA) and four of which are multiplexed into the

other sample-and-hold amplifier (B_SHA).

The CAN network itself is a single, differential pair line. All

nodes continuously monitor this line. There is no clock wire.

Messages are passed in one of four standard message types or

frames. Synchronization is achieved by an elaborate sync

scheme performed in each CAN receiver. Message arbitration is

accomplished one bit at a time. A dominant polarity is estab-

lished for the network. All nodes are allowed to start

At the 20 MHz sampling rate, the first data value is valid

approximately 375 ns after the convert start command. All eight

channels are converted in approximately 725 ns.

The core of the ADSP-21992 provides 14-bit data such that the

stored data values in the ADC data registers are 14 bits wide.

transmitting at the same time following a frame sync pulse.

As each node transmits a bit, it checks to see if the bus is the

same state that it transmitted. If it is, it continues to transmit. If

not, then another node has transmitted a dominant bit so the

first node knows it has lost the arbitration and it stops transmit-

ting. The arbitration continues, bit by bit until only one node is

left transmitting.

VOLTAGE REFERENCE

The ADSP-21992 contains an on-board band gap reference that

can be used to provide a precise 1.0 V output for use by the

analog-to-digital system and externally on the VREF pin for

biasing and level shifting functions. Additionally, the ADSP-

21992 may be configured to operate with an external reference

applied to the VREF pin, if required.

The electrical characteristics of each network connection are

very stringent so the CAN interface is typically divided into two

parts: a controller and a transceiver. This allows a single con-

troller to support different drivers and CAN networks. The

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• Separate auxiliary PWM synchronization signal and associ-

ated interrupt (can be used to trigger ADC convert start).

PWM GENERATION UNIT

Key features of the 3-phase PWM generation unit are:

• 16-bit, center-based PWM generation unit.

• Separate auxiliary PWM shutdown signal (AUXTRIP).

The ADSP-21992 integrates a 2-channel, 16-bit, auxiliary PWM

output unit that can be programmed with variable frequency,

variable duty cycle values and may operate in two different

modes, independent mode or offset mode. In independent

mode, the two auxiliary PWM generators are completely inde-

pendent and separate switching frequencies and duty cycles may

be programmed for each auxiliary PWM output. In offset mode

the switching frequency of the two signals on the AUX0 and

AUX1 pins is identical. Bit 4 of the AUXCTRL register places

the auxiliary PWM channel pair in independent or offset mode.

• Programmable PWM pulse width, with resolutions to

12.5 ns (at 80 MHz HCLK Rate).

• Single/double update modes

• Programmable dead time and switching frequency.

• Twos complement implementation which permits smooth

transition into full ON and full OFF states.

• Possibility to synchronize the PWM generation to an exter-

nal synchronization.

• Special provisions for BDCM operation (crossover and

output enable functions).

The auxiliary PWM generation unit provides two chip output

pins, AUX0 and AUX1 (on which the switching signals appear),

and one chip input pin, AUXTRIP, which can be used to shut

down the switching signals—for example, in a fault condition.

• Wide variety of special switched reluctance (SR)

operating modes.

• Output polarity and clock gating control.

ENCODER INTERFACE UNIT

• Dedicated asynchronous PWM shutdown signal.

• Multiple shutdown sources, independently for each unit.

The ADSP-21992 incorporates a powerful encoder interface

block to incremental shaft encoders that are often used for posi-

tion feedback in high performance motion control systems.

The ADSP-21992 integrates a flexible and programmable, 3-

phase PWM waveform generator that can be programmed to

generate the required switching patterns to drive a 3-phase volt-

age source inverter for ac induction (ACIM) or permanent

magnet synchronous (PMSM) motor control. In addition, the

PWM block contains special functions that considerably sim-

plify the generation of the required PWM switching patterns for

control of the electronically commutated motor (ECM) or

brushless dc motor (BDCM). Tying a dedicated pin, PWMSR,

to GND, enables a special mode, for switched reluctance

motors (SRM).

• Quadrature rates to 53 MHz (at 80 MHz HCLK rate).

• Programmable filtering of all encoder input signals.

• 32-bit encoder counter.

• Variety of hardware and software reset modes.

• Two registration inputs to latch EIU count value with cor-

responding registration interrupt.

• Status of A/B signals latched with reading of EIU

count value.

• Alternative frequency and direction mode.

• Single north marker mode.

The six PWM output signals consist of three high side drive pins

(AH, BH, and CH) and three low side drive signals pins (AL, BL,

and CL). The polarity of the generated PWM signals may be set

via hardware by the PWMPOL input pin, so that either active

HI or active LO PWM patterns can be produced.

• Count error monitor function with dedicated error

interrupt.

• Dedicated 16-bit loop timer with dedicated interrupt.

The switching frequency of the generated PWM patterns is pro-

grammable using the 16-bit PWMTM register. The PWM

generator is capable of operating in two distinct modes, single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period,

so that the resultant PWM patterns are symmetrical about the

midpoint of the PWM period. In the double update mode, a sec-

ond updating of the PWM registers is implemented at the

midpoint of the PWM period. In this mode, it is possible to pro-

duce asymmetrical PWM patterns that produce lower harmonic

distortion in 3-phase PWM inverters.

• Companion encoder event (1⁄T) timer unit.

The encoder interface unit (EIU) includes a 32-bit quadrature

up-/downconverter, programmable input noise filtering of the

encoder input signals and the zero markers, and has four dedi-

cated chip pins. The quadrature encoder signals are applied at

the EIA and EIB pins. Alternatively, a frequency and direction

set of inputs may be applied to the EIA and EIB pins. In addi-

tion, two north marker/strobe inputs are provided on pins EIZ

and EIS. These inputs may be used to latch the contents of the

encoder quadrature counter into dedicated registers,

EIZLATCH and EISLATCH, on the occurrence of external

events at the EIZ and EIS pins. These events may be pro-

grammed to be either rising edge only (latch event) or rising

edge if the encoder is moving in the forward direction and fall-

ing edge if the encoder is moving in the reverse direction

(software latched north marker functionality).

AUXILIARY PWM GENERATION UNIT

Key features of the auxiliary PWM generation unit are:

• 16-bit, programmable frequency, programmable duty cycle

PWM outputs.

• Independent or offset operating modes.

• Double buffered control of duty cycle and period registers.

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The encoder interface unit incorporates programmable noise

filtering on the four encoder inputs to prevent spurious noise

pulses from adversely affecting the operation of the quadrature

counter. The encoder interface unit operates at a clock fre-

quency equal to the HCLK rate. The encoder interface unit

operates correctly with encoder signals at frequencies of up to

13.25 MHz, at the 80 MHz HCLK rate, corresponding to a max-

imum quadrature frequency of 53 MHz (assuming an ideal

quadrature relationship between the input EIA and EIB signals).

WATCHDOG TIMER

The ADSP-21992 integrates a watchdog timer that can be used

as a protection mechanism against unintentional software

events. It can be used to cause a complete DSP and peripheral

reset in such an event. The watchdog timer consists of a 16-bit

timer that is clocked at the external clock rate (CLKIN or crystal

input frequency).

In order to prevent an unwanted timeout or reset, it is necessary

to periodically write to the watchdog timer register. During

abnormal system operation, the watchdog count will eventually

decrement to 0 and a watchdog timeout will occur. In the sys-

tem, the watchdog timeout will cause a full reset of the DSP core

and peripherals.

The EIU may be programmed to use the north marker on EIZ to

reset the quadrature encoder in hardware, if required.

Alternatively, the north marker can be ignored, and the encoder

quadrature counter is reset according to the contents of a maxi-

mum count register, EIUMAXCNT. There is also a “single

north marker” mode available in which the encoder quadrature

counter is reset only on the first north marker pulse.

GENERAL-PURPOSE TIMERS

The ADSP-21992 contains a general-purpose timer unit that

contains three identical 32-bit timers. The three programmable

interval timers (Timer0, Timer1, and Timer2) generate periodic

interrupts. Each timer can be independently set to operate in

one of three modes:

The encoder interface unit can also be made to implement some

error checking functions. If an encoder count error is detected

(due to a disconnected encoder line, for example), a status bit in

the EIUSTAT register is set, and an EIU count error interrupt is

generated.

• Pulse waveform generation (PWM_OUT) mode.

• Pulse width count/capture (WDTH_CAP) mode.

• External event watchdog (EXT_CLK) mode.

The encoder interface unit of the ADSP-21992 contains a 16-bit

loop timer that consists of a timer register, period register, and

scale register so that it can be programmed to time out and

reload at appropriate intervals. When this loop timer times out,

an EIU loop timer timeout interrupt is generated. This interrupt

could be used to control the timing of speed and position con-

trol loops in high performance drives.

Each Timer has one bidirectional chip pin, TMR2-TMR0. For

each timer, the associated pin is configured as an output pin in

PWM_OUT mode and as an input pin in WDTH_CAP and

EXT_CLK modes.

The encoder interface unit also includes a high performance

encoder event timer (EET) block that permits the accurate tim-

ing of successive events of the encoder inputs. The EET can be

programmed to time the duration between up to 255 encoder

pulses and can be used to enhance velocity estimation, particu-

larly at low speeds of rotation.

INTERRUPTS

The interrupt controller lets the DSP respond to 17 interrupts

with minimum overhead. The DSP core implements an inter-

rupt priority scheme as shown in Table 2. Applications can use

the unassigned slots for software and peripheral interrupts. The

peripheral interrupt controller is used to assign the various

peripheral interrupts to the 12 user assignable interrupts of the

DSP core.

FLAG I/O (FIO) PERIPHERAL UNIT

The FIO module is a generic parallel I/O interface that supports

16 bidirectional multifunction flags or general-purpose digital

I/O signals (PF15–PF0).

Table 2. Interrupt Priorities/Addresses

All 16 FLAG bits can be individually configured as an input or

output based on the content of the direction (DIR) register, and

can also be used as an interrupt source for one of two FIO inter-

rupts. When configured as input, the input signal can be

programmed to set the FLAG on either a level (level sensitive

input/interrupt) or an edge (edge sensitive input/interrupt).

IMASK/

IRPTL

Interrupt

Vector Address

Emulator (NMI)

—Highest Priority

NA

Reset (NMI)

0

1

2

3

4

0x00 0000

0x00 0020

0x00 0040

0x00 0060

0x00 0080

The FIO module can also be used to generate an asynchronous

unregistered wake-up signal FIO_WAKEUP for DSP core wake

up after power-down.

Power-Down (NMI)

Loop and PC Stack

Emulation Kernel

The FIO lines, PF7–PF1 can also be configured as external slave

select outputs for the SPI communications port, while PF0 can

be configured to act as a slave select input.

The FIO lines can be configured to act as a PWM shutdown

source for the 3-phase PWM generation unit of the

ADSP-21992.

User Assigned Interrupt

(USR0)

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Table 2. Interrupt Priorities/Addresses (Continued)

loop stack is eight levels deep, and the status stack is 16 levels

deep. To prevent stack overflow, the PC stack can generate a

stack level interrupt if the PC stack falls below three locations

full or rises above 28 locations full.

IMASK/

IRPTL

Interrupt

Vector Address

The following instructions globally enable or disable interrupt

servicing, regardless of the state of IMASK.

User Assigned Interrupt

(USR1)

5

0x00 00A0

• Ena Int

User Assigned Interrupt

(USR2)

6

0x00 00C0

0x00 00E0

0x00 0100

0x00 0120

0x00 0140

0x00 0160

0x00 0180

0x00 01A0

0x00 01C0

0x00 01E0

• Dis Int

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and

computational registers exist. Switching between the primary

and secondary registers lets programs quickly service interrupts,

while preserving the state of the DSP.

User Assigned Interrupt

(USR3)

7

User Assigned Interrupt

(USR4)

8

PERIPHERAL INTERRUPT CONTROLLER

User Assigned Interrupt

(USR5)

9

The peripheral interrupt controller is a dedicated peripheral

unit of the ADSP-21992 (accessed via I/O mapped registers).

The peripheral interrupt controller manages the connection of

up to 32 peripheral interrupt requests to the DSP core.

User Assigned Interrupt

(USR6)

10

11

12

13

14

15

For each peripheral interrupt source, there is a unique 4-bit

code that allows the user to assign the particular peripheral

interrupt to any one of the 12 user assignable interrupts of the

embedded ADSP-2199x core. Therefore, the peripheral inter-

rupt controller of the ADSP-21992 contains eight 16-bit

interrupt priority registers (Interrupt Priority Register 0 (IPR0)

to Interrupt Priority Register 7 (IPR7)).

User Assigned Interrupt

(USR7)

User Assigned Interrupt

(USR8)

User Assigned Interrupt

(USR9)

Each interrupt priority register contains four 4-bit codes; one

specifically assigned to each peripheral interrupt. The user may

write a value between 0x0 and 0xB to each 4-bit location in

order to effectively connect the particular interrupt source to

the corresponding user assignable interrupt of the

ADSP-2199x core.

User Assigned Interrupt

(USR10)

User Assigned Interrupt

(USR11)

—Lowest Priority

Writing a value of 0x0 connects the peripheral interrupt to the

USR0 user assignable interrupt of the ADSP-2199x core while

writing a value of 0xB connects the peripheral interrupt to the

USR11 user assignable interrupt. The core interrupt USR0 is the

highest priority user interrupt, while USR11 is the lowest prior-

ity. Writing a value between 0xC and 0xF effectively disables the

peripheral interrupt by not connecting it to any ADSP-2199x

core interrupt input. The user may assign more than one

peripheral interrupt to any given ADSP-2199x core interrupt. In

that case, the burden is on the user software in the interrupt vec-

tor table to determine the exact interrupt source through

reading status bits.

There is no assigned priority for the peripheral interrupts after

reset. To assign the peripheral interrupts a different priority,

applications write the new priority to their corresponding con-

trol bits (determined by their ID) in the interrupt priority

control register.

Interrupt routines can either be nested with higher priority

interrupts taking precedence or processed sequentially. Inter-

rupts can be masked or unmasked with the IMASK register.

Individual interrupt requests are logically ANDed with the bits

in IMASK; the highest priority unmasked interrupt is then

selected. The emulation, power-down, and reset interrupts are

nonmaskable with the IMASK register, but software can use the

DIS INT instruction to mask the power-down interrupt.

This scheme permits the user to assign the number of specific

interrupts that are unique to their application to the interrupt

scheme of the ADSP-2199x core. The user can then use the

existing interrupt priority control scheme to dynamically con-

trol the priorities of the 12 core interrupts.

The interrupt control (ICNTL) register controls interrupt nest-

ing and enables or disables interrupts globally.

LOW POWER OPERATION

The IRPTL register is used to force and clear interrupts. On-

chip stacks preserve the processor status and are automatically

maintained during interrupt handling. To support interrupt,

loop, and subroutine nesting, the PC stack is 33 levels deep, the

The ADSP-21992 has four low power options that significantly

reduce the power dissipation when the device operates under

standby conditions. To enter any of these modes, the DSP exe-

cutes an IDLE instruction. The ADSP-21992 uses the

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configuration of the PD, STCK, and STALL bits in the PLLCTL

register to select between the low power modes as the DSP exe-

cutes the IDLE instruction. Depending on the mode, an IDLE

shuts off clocks to different parts of the DSP in the different

modes. The low power modes are:

type and should be specified by the crystal manufacturer. A par-

allel resonant, fundamental frequency, microprocessor grade

crystal should be used for this configuration.

If a buffered, shaped clock is used, this external clock connects

to the DSP CLKIN pin. CLKIN input cannot be halted, changed,

or operated below the specified frequency during normal opera-

tion. This clock signal should be a TTL-compatible signal.

When an external clock is used, the XTAL input must be left

unconnected.

• Idle

• Power-down core

• Power-down core/peripherals

• Power-down all

The DSP provides a user-programmable 1ϫ to 32ϫ multiplica-

tion of the input clock, including some fractional values, to

support 128 external to internal (DSP core) clock ratios. The

BYPASS pin, and MSEL6–0 and DF bits, in the PLL configura-

tion register, decide the PLL multiplication factor at reset. At

runtime, the multiplication factor can be controlled in software.

To support input clocks greater that 100 MHz, the PLL uses an

additional bit (DF). If the input clock is greater than 100 MHz,

DF must be set. If the input clock is less than 100 MHz, DF must

be cleared. For clock multiplier settings, see the ADSP-2199x

DSP Hardware Reference Manual.

Idle Mode

When the ADSP-21992 is in idle mode, the DSP core stops exe-

cuting instructions, retains the contents of the instruction

pipeline, and waits for an interrupt. The core clock and periph-

eral clock continue running.

To enter idle mode, the DSP can execute the IDLE instruction

anywhere in code. To exit idle mode, the DSP responds to an

interrupt and (after two cycles of latency) resumes executing

instructions.

The peripheral clock is supplied to the CLKOUT pin.

Power-Down Core Mode

All on-chip peripherals for the ADSP-21992 operate at the rate

set by the peripheral clock. The peripheral clock (HCLK) is

either equal to the core clock rate or one half the DSP core clock

rate (CCLK). This selection is controlled by the IOSEL bit in the

PLLCTL register. The maximum core clock is 160 MHz for the

ADSP-21992BST, 150 MHz for both the ADSP-21992BBC and

ADSP-21992YBC, and 100 MHz for the ADSP-21992YST. The

maximum peripheral clock is 80 MHz for the ADSP-21992BST,

75 MHz for both the ADSP-21992BBC and ADSP-21992YBC,

and 50 MHz for the ADSP-21992YST—the combination of the

input clock and core/peripheral clock ratios may not exceed

these limits.

When the ADSP-21992 is in power-down core mode, the DSP

core clock is off, but the DSP retains the contents of the pipeline

and keeps the PLL running. The peripheral bus keeps running,

letting the peripherals receive data.

To exit power-down core mode, the DSP responds to an inter-

rupt and (after two cycles of latency) resumes executing

instructions.

Power-Down Core/Peripherals Mode

When the ADSP-21992 is in power-down core/peripherals

mode, the DSP core clock and peripheral bus clock are off, but

the DSP keeps the PLL running. The DSP does not retain the

contents of the instruction pipeline. The peripheral bus is

stopped, so the peripherals cannot receive data.

To exit power-down core/peripherals mode, the DSP responds

to an interrupt and (after five to six cycles of latency) resumes

executing instructions.

XTAL

CLKIN

ADSP-2199x

Power-Down All Mode

When the ADSP-21992 is in power-down all mode, the DSP

core clock, the peripheral clock, and the PLL are all stopped.

The DSP does not retain the contents of the instruction pipe-

line. The peripheral bus is stopped, so the peripherals cannot

receive data.

Figure 6. External Crystal Connections

To exit power-down core/peripherals mode, the DSP responds

to an interrupt and (after 500 cycles to restabilize the PLL)

resumes executing instructions.

RESET AND POWER-ON RESET (POR)

The RESET pin initiates a complete hardware reset of the

ADSP-21992 when pulled low. The RESET signal must be

asserted when the device is powered up to assure proper initial-

ization. The ADSP-21992 contains an integrated power-on reset

(POR) circuit that provides an output reset signal, POR, from

the ADSP-21992 on power-up and if the power supply voltage

falls below the threshold level. The ADSP-21992 may be reset

CLOCK SIGNALS

The ADSP-21992 can be clocked by a crystal oscillator or a buff-

ered, shaped clock derived from an external clock oscillator. If a

crystal oscillator is used, the crystal should be connected across

the CLKIN and XTAL pins, with two capacitors connected as

shown in Figure 6. Capacitor values are dependent on crystal

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from an external source using the RESET signal, or alterna-

tively, the internal power-on reset circuit may be used by

connecting the POR pin to the RESET pin. During power-up

the RESET line must be activated for long enough to allow the

DSP core’s internal clock to stabilize. The power-up sequence is

defined as the total time required for the crystal oscillator to sta-

bilize after a valid VDD is applied to the processor and for the

internal phase-locked loop (PLL) to lock onto the specific crys-

tal frequency. A minimum of 512 cycles will ensure that the PLL

has locked (this does not include the crystal oscillator

start-up time).

pins must be connected to the same supply. The ideal power-on

sequence for the DSP is to provide power-up of all supplies

simultaneously. If there is going to be some delay in power-up

between the supplies, provide V_DDfirst, then V_{DD_IO}

.

BOOTING MODES

The ADSP-21992 supports a number of different boot modes

that are controlled by the three dedicated hardware boot mode

control pins (BMODE2, BMODE1, and BMODE0). The use of

three boot mode control pins means that up to eight different

boot modes are possible. Of these only five modes are valid on

the ADSP-21992. The ADSP-21992 exposes the boot mecha-

nism to software control by providing a nonmaskable boot

interrupt that vectors to the start of the on-chip ROM memory

block (at address 0xFF0000). A boot interrupt is automatically

initiated following either a hardware initiated reset, via the

RESET pin, or a software initiated reset, via writing to the soft-

ware reset register. Following either a hardware or a software

reset, execution always starts from the boot ROM at address

0xFF0000, irrespective of the settings of the BMODE2,

The RESET input contains some hysteresis. If an RC circuit is

used to generate the RESET signal, the circuit should use an

external Schmitt trigger.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts, and resets all registers to

their default values (where applicable). When RESET is

released, if there is no pending bus request, program control

jumps to the location of the on-chip boot ROM (0xFF0000) and

the booting sequence is performed.

BMODE1, and BMODE0 pins. The dedicated BMODE2,

BMODE1, and BMODE0 pins are sampled at hardware reset.

POWER SUPPLIES

The particular boot mode for the ADSP-21992 associated with

the settings of the BMODE2, BMODE1, BMODE0 pins is

defined in Table 3.

The ADSP-21992 has separate power supply connections for the

internal (V_DDINT) and external (V_DDEXT) power supplies. The

internal supply must meet the 2.5 V requirement. The external

supply must be connected to a 3.3 V supply. All external supply

Table 3. Summary of Boot Modes

Boot Mode

BMODE2

BMODE1

BMODE0

Function

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Illegal–Reserved

Boot from External 8-Bit Memory over EMI

Execute from External 8-Bit Memory

Execute from External 16-Bit Memory

Boot from SPI ≤ 4K Bits

Boot from SPI > 4K Bits

Illegal–Reserved

Rev. A

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Page 14 of 60

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August 2007

ADSP-21992

plexity, this capability can have a significant influence on the

design development schedule by increasing productivity. Statis-

tical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

INSTRUCTION SET DESCRIPTION

The ADSP-21992 assembly language instruction set has an alge-

braic syntax that was designed for ease of coding and

readability. The assembly language, which takes full advantage

of the unique architecture of the processor, offers the following

benefits:

• SHARC assembly language syntax is a superset of and

source code compatible (except for two data registers and

DAG base address registers) with ADSP-21xx family syn-

tax. It may be necessary to restructure ADSP-21xx

programs to accommodate the unified memory space of

the ADSP-21992 and to conform to its interrupt

vector map.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical arith-

metic add instruction, such as AR = AX0 + AY0, resembles

a simple equation.

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The

exceptions are two dual word instructions. One writes

16- or 24-bit immediate data to memory, and the other is

an absolute jump/call with the 24-bit address specified in

the instruction.

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

• Multifunction instructions allow parallel execution of an

arithmetic, MAC, or shift instruction with up to two

fetches or one write to processor memory space during a

single instruction cycle.

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Program flow instructions support a wider variety of con-

ditional and unconditional jumps/calls and a larger set of

conditions on which to base execution of conditional

instructions.

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the command

line switches of the tool

DEVELOPMENT TOOLS

The ADSP-21992 is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The emulator hardware that supports

other SHARC DSPs also fully emulates the ADSP-21992.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The DSP has archi-

tectural features that improve the efficiency of compiled C/C++

code.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

Rev. A

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Page 15 of 60

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August 2007

ADSP-21992

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

applications. The user can also download components from the

Web, drop them into the application and publish component

archives from within VisualDSP++. VCSE supports component

implementation in C/C++ or assembly language.

communications ports and embedded control peripherals, refer

to the ADSP-2199x Mixed Signal DSP Controller Hardware Ref-

erence Manual.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system, view memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the DSP or external memory with the drag

of the mouse, and examine runtime stack and heap usage. The

Expert Linker is fully compatible with existing linker definition

file (LDF), allowing the developer to move between the graphi-

cal and textual environments.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test

access port of the ADSP-21992 processor to monitor and con-

trol the target board processor during emulation. The emulator

provides full speed emulation, allowing inspection and modifi-

cation of memory, registers, and processor stacks. Nonintrusive

in-circuit emulation is assured by the use of the processor JTAG

interface—target system loading and timing are not affected by

the emulator.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC DSP PC plug-in cards. Third-party

software tools include DSP libraries, real-time operating sys-

tems, and block diagram design tools.

DESIGNING AN EMULATOR-COMPATIBLE DSP

BOARD

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG DSP. The emulator uses the

TAP to access the internal features of the DSP, allowing the

developer to load code, set breakpoints, observe variables,

observe memory, and examine registers. The DSP must be

halted to send data and commands, but once an operation has

been completed by the emulator, the DSP system is set running

at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the EE-68: JTAG Emulation Technical Reference on the

Analog Devices website (www.analog.com)—use site search on

“EE-68.” This document is updated regularly to keep pace

with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21992

architecture and functionality. For detailed information on the

ADSP-21992 embedded DSP core architecture, instruction set,

Rev. A

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ADSP-21992

PIN FUNCTION DESCRIPTIONS

ADSP-21992 pin definitions are listed in Table 4. All

ADSP-21992 inputs are asynchronous and can be asserted asyn-

chronously to CLKIN (or to TCK for TRST).

floating internally. PWMTRIP has an internal pull-down, but

should not be left floating to avoid unnecessary PWM

shutdowns.

Unused inputs should be tied or pulled to V_DDEXTor GND,

except for ADDR21–0, DATA15–0, PF7–0, and inputs that have

internal pull-up or pull-down resistors (TRST, BMODE0,

BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, PWMPOL,

PWMSR, and RESET)—these pins can be left floating. These

pins have a logic level hold circuit that prevents input from

The following symbols appear in the Type column of Table 4:

G = ground, I = input, O = output, P = power supply,

B = bidirectional, T = three-state, D = digital, A = analog,

CKG = clock generation pin, PU = internal pull-up,

PD = internal pull-down, and OD = open drain.

Table 4. Pin Descriptions

Name

A19–A0

D15–D0

RD

WR

ACK

BR

BG

BGH

MS0

MS1

MS2

MS3

IOMS

BMS

CLKIN

XTAL

CLKOUT

BYPASS

RESET

POR

BMODE2

BMODE1

BMODE0

TCK

Type

D, OT

D, BT

D, OT

D, I

D, I, PU

D, O

D, OT

D, I, CKG

D, O, CKG

D, O

D, I, PU

D, O

D, I, PU

D, I, PD

D, I, PU

D, I

Function

External Port Address Bus

External Port Data Bus

External Port Read Strobe

External Port Write Strobe

External Port Access Ready Acknowledge

External Port Bus Request

External Port Bus Grant

External Port Bus Grant Hang

External Port Memory Select Strobe 0

External Port Memory Select Strobe 1

External Port Memory Select Strobe 2

External Port Memory Select Strobe 3

External Port IO Space Select Strobe

External Port Boot Memory Select Strobe

Clock Input/Oscillator Input/Crystal Connection 0

Oscillator Output/Crystal Connection 1

Clock Output (HCLK)

PLL Bypass Mode Select

Processor Reset Input

Power on Reset Output

Boot Mode Select Input 2

Boot Mode Select Input 1

Boot Mode Select Input 0

JTAG Test Clock

TMS

TDI

TDO

TRST

EMU

D, I, PU

D, OT

D, I, PU

D, OT, PU

A, I

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

JTAG Test Reset Input

Emulation Status

ADC Input 0

VIN0

VIN1

A, I

ADC Input 1

VIN2

A, I

ADC Input 2

VIN3

A, I

ADC Input 3

VIN4

A, I

ADC Input 4

VIN5

A, I

ADC Input 5

VIN6

A, I

ADC Input 6

VIN7

A, I

ADC Input 7

ASHAN

A, I

Inverting SHA_A Input

Rev. A

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August 2007

ADSP-21992

Table 4. Pin Descriptions (Continued)

Name

BSHAN

CAPT

CAPB

VREF

Type

A, I

A, O

A, I, O

A, I

A, O

Function

Inverting SHA_B Input

Noise Reduction Pin

Voltage Reference Pin (Mode Selected by State of SENSE)

Voltage Reference Select Pin

Common-Mode Level Pin

SENSE

CML

CONVST

CANRX

CANTX

PF15

PF14

PF13

PF12

PF11

PF10

PF9

D, I

ADC Convert Start Input

Controller Area Network (CAN) Receive

Controller Area Network (CAN) Transmit

General-Purpose IO15

General-Purpose IO14

General-Purpose IO13

General-Purpose IO12

General-Purpose IO11

General-Purpose IO10

General-Purpose IO9

D, OT

D, BT, PD

D, BT

PF8

General-Purpose IO8

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS

SCK

General-Purpose IO7/SPI Slave Select Output 7

General-Purpose IO6/SPI Slave Select Output 6

General-Purpose IO5/SPI Slave Select Output 5

General-Purpose IO4/SPI Slave Select Output 4

General-Purpose IO3/SPI Slave Select Output 3

General-Purpose IO2/SPI Slave Select Output 2

General-Purpose IO1/SPI Slave Select Output 1

General-Purpose IO0/SPI Slave Select Input 0

SPI Clock

MISO

MOSI

DT

D, BT

D, OT

D, I

SPI Master In Slave Out Data

SPI Master Out Slave In Data

SPORT Data Transmit

DR

SPORT Data Receive

RFS

TFS

TCLK

D, BT

SPORT Receive Frame Sync

SPORT Transmit Frame Sync

SPORT Transmit Clock

RCLK

D, BT

SPORT Receive Clock

EIA

D, I

Encoder A Channel Input

EIB

D, I

Encoder B Channel Input

EIZ

D, I

Encoder Z Channel Input

EIS

D, I

Encoder S Channel Input

AUX0

AUX1

AUXTRIP

TMR2

TMR1

TMR0

AH

D, O

D, I, PD

D, BT

Auxiliary PWM Channel 0 Output

Auxiliary PWM Channel 1 Output

Auxiliary PWM Shutdown Pin

Timer 0 Input/Output Pin

Timer 1 Input/Output Pin

Timer 2 Input/Output Pin

D, BT

D, O

PWM Channel A HI PWM

AL

D, O

PWM Channel A LO PWM

BH

D, O

PWM Channel B HI PWM

BL

D, O

PWM Channel B LO PWM

CH

D, O

PWM Channel C HI PWM

CL

D, O

PWM Channel C LO PWM

Rev. A

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August 2007

ADSP-21992

Table 4. Pin Descriptions (Continued)

Name

PWMSYNC

PWMPOL

PWMTRIP

PWMSR

AVDD (2 pins)

AVSS (2 pins)

VDDINT (6 pins)

VDDEXT (10 pins)

GND (16 pins)

Type

D, BT

D, I, PU

D, I, PD

D, I, PU

A, P

A, G

D, P

D, G

Function

PWM Synchronization

PWM Polarity

PWM Trip

PWM SR Mode Select

Analog Supply Voltage

Analog Ground

Digital Internal Supply

Digital External Supply

Digital Ground

Rev. A

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ADSP-21992

SPECIFICATIONS

Specifications subject to change without notice.

OPERATING CONDITIONS

Table 5. Recommended Operating Conditions—ADSP-21992BBC

Parameter

V_DDINT

V_DDEXT

AVDD

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

150

75

150

140

+85

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

Input Clock Frequency

Silicon Junction Temperature

Ambient Operating Temperature

V

CCLK

MHz

ЊC

HCLK^{1 2}

0

,

CLKIN³

4

T_JUNC

T_AMB

–40

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLKꢁ2, up to a maximum of a 75 MHz HCLK for the ADSP-21992BBC.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Table 6. Recommended Operating Conditions—ADSP-21992YBC

Parameter

V_DDINT

V_DDEXT

AVDD

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

150

75

150

140

+125

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

Input Clock Frequency

Silicon Junction Temperature

Ambient Operating Temperature

V

CCLK

MHz

ЊC

HCLK^{1, 2}

CLKIN³

0

4

T_JUNC

T_AMB

–40

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLK ꢁ 2, up to a maximum of an 75 MHz HCLK for the ADSP-21992YBC.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Rev. A

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August 2007

ADSP-21992

Table 7. Recommended Operating Conditions—ADSP-21992BST

Parameter

V_DDINT

V_DDEXT

AVDD

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

160

80

160

140

+85

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

Input Clock Frequency

Silicon Junction Temperature

Ambient Operating Temperature

V

CCLK

MHz

ЊC

HCLK^{1, 2}

CLKIN³

0

4

T_JUNC

T_AMB

–40

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLKꢁ2, up to a maximum of a 80 MHz HCLK for the ADSP-21992BST.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Table 8. Recommended Operating Conditions—ADSP-21992YST

Parameter

V_DDINT

V_DDEXT

AVDD

Conditions

Min

2.375

3.135

2.375

0

Typ

2.5

3.3

2.5

Max

2.625

3.465

2.625

100

50

100

140

Unit

V

Internal (Core) Supply Voltage

External (I/O) Supply Voltage

Analog Supply Voltage

DSP Instruction Rate, Core Clock

Peripheral Clock Rate

V

CCLK

MHz

ЊC

HCLK^{1, 2}

CLKIN³

0

Input Clock Frequency

Silicon Junction Temperature

4

T_JUNC

T_AMB

Ambient Operating Temperature

–40

+125

ЊC

¹The HCLK frequency may be made to appear at the dedicated CLKOUT pin of the device. For low power operation, however, the CLKOUT pin can be disabled.

²The peripherals operate at the HCLK rate, which may be selected to be equal to CCLK or CCLKꢁ2, up to a maximum of an 50 MHz HCLK for the ADSP-21992YST.

³In order to attain the correct CCLK and HCLK values, the input clock frequency or crystal frequency depends on the internal operation of the clock generation PLL

circuit and the associated frequency ratio.

⁴The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications. It is ultimately the responsibility of the user to ensure that

the power dissipation of the ADSP-21992 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded.

Rev. A

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August 2007

ADSP-21992

Table 9. Electrical Characteristics—ADSP-21992BBC

Parameter

Conditions

Test Conditions

Min

2.0

2.2

Typ

Max

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

V_DDEXT

0.8

V

V_OH

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

0.4

10

V

I

_OL= 2.0 mA

@ V_DDINT= Maximum,

_IN= 3.6 V

@ V_DDINT= Maximum,

_IN= 3.6 V

μA

V

I_IH

150

10

V

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

I_IL

10

I_IL

10

I_IL

150

10

I_OZH

I_OZL

10

C_I

C_O

I_DD-PEAK

I_DD-TYP

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

Input Pin Capacitance

Output Pin Capacitance

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

f_IN= 1 MHz

10

190

155

145

60

12

6

pF

325

275

250

125

40

30

65

15

mA

46

5

I_AVDD-ADCOFF

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, HCLK = 75 MHz

for the ADSP-21992BBC. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINT= maximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum.

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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ADSP-21992

ELECTRICAL CHARACTERISTICS

Table 10. Electrical Characteristics—ADSP-21992YBC

Parameter

Conditions

Test Conditions

Min

2.0

2.2

Typ

Max

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

V_DDEXT

0.8

V

V_OH

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

I_OL= 2.0 mA

@ V_DDINT= Maximum,

0.4

10

V

μA

V

_IN= 3.6 V

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

150

10

I_IH

I_IL

10

I_IL

10

I_IL

150

10

I_OZH

I_OZL

10

C_I

C_O

I_DD-PEAK

I_DD-TYP

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

Input Pin Capacitance

Output Pin Capacitance

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

f_IN= 1 MHz

10

190

155

145

60

12

6

pF

325

275

250

125

40

30

65

15

mA

46

5

I_AVDD-ADCOFF

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, HCLK = 75 MHz

for the ADSP-21992YBC. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINT= maximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum.

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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ADSP-21992

Table 11. Electrical Characteristics—ADSP-21992BST

Parameter

Conditions

Test Conditions

Min

2.0

2.2

Typ

Max

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= Minimum

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

V_DDEXT

0.8

V

V_OH

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

0.4

10

V

I

_OL= 2.0 mA

@ V_DDINT= Maximum,

_IN= 3.6 V

@ V_DDINT= Maximum,

_IN= 3.6 V

μA

V

I_IH

150

10

V

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

I_IL

10

I_IL

10

I_IL

150

10

I_OZH

I_OZL

10

C_I

C_O

I_DD-PEAK

I_DD-TYP

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

Input Pin Capacitance

Output Pin Capacitance

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

f_IN= 1 MHz

10

300

240

225

90

20

7

pF

350

300

275

150

50

35

65

15

mA

49

7

I_AVDD-ADCOFF

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 160 MHz, HCLK = 80 MHz

for the ADSP-21992BST. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINT= maximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum.

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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ADSP-21992

Table 12. Electrical Characteristics—ADSP-21992YST

Parameter

Conditions

Test Conditions

Min

2.0

2.2

Typ

Max

Unit

V_IH

V_IL

High Level Input Voltage¹

High Level Input Voltage²

High Level Input Voltage^{1, 2}

High Level Output Voltage³

@ V_DDEXT= Maximum

@ V_DDEXT= minimum

@ V_DDEXT= Minimum,

I_OH= –0.5 mA

V_DDEXT

0.8

V

V_OH

2.4

V_OL

I_IH

Low Level Output Voltage³

High Level Input Current⁴

High Level Input Current⁵

High Level Input Current⁶

Low Level Input Current

Three-State Leakage Current⁷

@ V_DDEXT= Minimum,

0.4

10

V

I

_OL= 2.0 mA

@ V_DDINT= Maximum,

_IN= 3.6 V

@ V_DDINT= Maximum,

_IN= 3.6 V

μA

V

I_IH

150

10

V

I_IH

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 0 V

@ V_DDINT= Maximum,

V_IN= 3.6 V

@ V_DDINT= Maximum,

V_IN= 0 V

I_IL

10

I_IL

10

I_IL

150

10

I_OZH

I_OZL

10

C_I

C_O

I_DD-PEAK

I_DD-TYP

I_DD-IDLE

I_DD-STOPCLK

I_DD-STOPALL

I_DD-PDOWN

I_AVDD

Input Pin Capacitance

Output Pin Capacitance

Supply Current (Internal)^{8, 9}

Supply Current (Internal)⁸

Supply Current (Idle)⁸

Supply Current (Power-Down)^{8, 10}

Supply Current (Power-Down)^{8, 11}

Supply Current (Power-Down)^{8, 12}

Analog Supply Current¹³

Analog Supply Current¹²

f_IN= 1 MHz

10

190

155

145

60

12

6

pF

250

210

180

100

40

35

65

15

mA

46

5

I_AVDD-ADCOFF

¹Applies to all input and bidirectional pins.

²Applies to input pins CLKIN, RESET, TRST.

³Applies to all output and bidirectional pins.

⁴Applies to all input only pins.

⁵Applies to input pins with internal pull-down.

⁶Applies to input pins with internal pull-up.

⁷Applies to three-stateable pins.

⁸The I_DDsupply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 100 MHz, HCLK = 50 MHz

for the ADSP-21992YST. I_DDrefers only to the current consumption on the internal power supply lines (V_DDINT). The current consumption at the I/O on the V_DDEXT

power supply is very much dependent on the particular connection of the device in the final system.

⁹I_DD-PEAKrepresents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical

applications are less than specified. Measured at V_DDINT= maximum.

¹⁰IDLE denotes the current consumption during execution of the IDLE instruction. Measured at V_DDINT= maximum.

11

I

represents the processor operation in full power-down mode with both core and peripheral clocks disabled. Measured at V_DDINT= maximum.

represents the power consumption of the analog system. Measured at AVDD = maximum.

DD-PDOWN

12

AVDD

¹³The responsibility lies with the user to ensure that the device is operated in such a manner that the maximum allowable junction temperature is not exceeded.

Rev. A

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ADSP-21992

Table 13. Peripherals Electrical Characteristics—ADSP-21992BBC

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTER

AC Specifications

SNR

Signal-to-Noise Ratio¹

68

66

72

71

–80

–82

0.05

dB

%FSR

SNRD

THD

CTLK

CMRR

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

–66

0.2

PSRR

Accuracy

INL

DNL

Integral Nonlinearity¹

Differential Nonlinearity¹

±0.6

±0.5

12

1.25

0.5

±2.0

±1.25

LSB

Bits

%FSR

No Missing Codes

Zero Error¹

Gain Error¹

2.5

1.5

Input Voltage

V_IN

C_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

pF

Conversion Time

FCLK

t_CONV

ADC Clock Rate

Total Conversion Time All 8 Channels

18.75

773

MHz

ns

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON RESET

V_RST

0.94

0.98

40

100

+0.5

8

1.02

V

mV

μA

mV

kΩ

–2

+2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

mV

V_HYST

50

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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ADSP-21992

Table 14. Peripherals Electrical Characteristics—ADSP-21992BST

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTER

AC Specifications

SNR

Signal-to-Noise Ratio¹

68

72

71

–78

–80

–74

0.05

dB

%FSR

SNRD

THD

CTLK

CMRR

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

–68

–66

0.2

PSRR

Accuracy

INL

DNL

Integral Nonlinearity¹

Differential Nonlinearity¹

±0.6

±0.5

12

1.25

0.5

±2.0

±1.25

LSB

Bits

%FSR

No Missing Codes

Zero Error¹

Gain Error¹

2.5

1.5

Input Voltage

V_IN

C_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

pF

Conversion Time

FCLK

t_CONV

ADC Clock Rate

Total Conversion Time All 8 Channels

20

725

MHz

ns

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON RESET

V_RST

0.94

0.98

40

100

+0.5

8

1.02

V

mV

μA

mV

kΩ

–2

+2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

mV

V_HYST

50

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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ADSP-21992

Table 15. Peripherals Electrical Characteristics—ADSP-21992YBC

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL

CONVERTER

AC Specifications

SNR

Signal-to-Noise Ratio¹

68

66

72

71

–80

–82

0.05

dB

%FSR

SNRD

THD

CTLK

CMRR

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

–66

0.2

PSRR

Accuracy

INL

DNL

Integral Nonlinearity¹

Differential Nonlinearity¹

±0.6

±0.5

12

1.25

0.5

±2.0

±1.25

LSB

Bits

%FSR

No Missing Codes

Zero Error¹

Gain Error¹

2.5

1.5

Input Voltage

V_IN

C_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

pF

Conversion Time

FCLK

t_CONV

ADC Clock Rate

Total Conversion Time All 8 Channels

18.75

773

MHz

ns

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON RESET

V_RST

0.94

0.98

40

100

+0.5

8

1.02

V

mV

μA

mV

kΩ

–2

+2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

mV

V_HYST

50

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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ADSP-21992

Table 16. Peripherals Electrical Characteristics—ADSP-21992YST

Parameter

Description

Min

Typ

Max

Unit

ANALOG-TO-DIGITAL CONVERTER

AC Specifications

SNR

Signal-to-Noise Ratio¹

68

72

71

–80

–82

0.05

dB

%FSR

SNRD

THD

CTLK

CMRR

Signal-to-Noise and Distortion¹

Total Harmonic Distortion¹

Channel-Channel Crosstalk¹

Common-Mode Rejection Ratio¹

Power Supply Rejection Ratio¹

–68

–66

0.2

PSRR

Accuracy

INL

DNL

Integral Nonlinearity¹

Differential Nonlinearity¹

±0.6

±0.5

12

1.25

0.5

±2.0

±1.25

LSB

Bits

%FSR

No Missing Codes

Zero Error¹

Gain Error¹

2.5

1.5

Input Voltage

V_IN

C_IN

Input Voltage Span

Input Capacitance²

2.0

10

V

pF

Conversion Time

FCLK

t_CONV

ADC Clock Rate

Total Conversion Time All 8 Channels

12.5

1160

MHz

ns

VOLTAGE REFERENCE

Internal Voltage Reference³

Output Voltage Tolerance

Output Current

Load Regulation⁴

Power Supply Rejection Ratio

Reference Input Resistance

POWER-ON RESET

V_RST

0.94

0.98

40

100

+0.5

8

1.02

V

mV

μA

mV

kΩ

–2

+2

Reset Threshold Voltage

Hysteresis Voltage

1.4

2.1

V

mV

V_HYST

50

¹In all cases, the input frequency to the ADC system is assumed to be <100 kHz.

²Analog input pins VIN0 to VIN7.

³These specifications are for operation of the internal voltage reference so that SENSE = REFCOM, with the default 1.0 V operating mode.

⁴Operation with full 0.1 mA load current. For optimal operation, it is recommended to buffer the VREF output voltage before using it in other parts of the system.

Rev. A

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ADSP-21992

ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Internal (Core) Supply Voltage¹(V_DDINT

)

–0.3 V to +3.0 V

–0.3 V to +4.6 V

–0.5 V to +5.5 V

200 pF

External (I/O) Supply Voltage¹(V_DDEXT

Input Voltage1, ²(V_IL– V_IH)

Output Voltage Swing^{1, 2}(V_OL– V_OH

Load Capacitance1 (C_L)

)

Core Clock Period1 (t_CCLK

Core Clock Frequency1 (f_CCLK

Peripheral Clock Period1 (t_HCLK

Peripheral Clock Frequency1 (f_HCLK

Storage Temperature Range1 (T_STORE

Lead Temperature (5 seconds)1 (T_LEAD

)

6.25 ns

160 MHz

12.5 ns

80 MHz

–65ЊC to +150ЊC

85ЊC

)

¹Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;

functional operation of the device at these or any other conditions greater than those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

²Except CLKIN and analog pins.

ESD CAUTION

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary circuitry, damage may occur

on devices subjected to high energy ESD. Therefore,

proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

TIMING SPECIFICATIONS

This next section contains timing information for the external

signals of the DSP. Use the exact information given. Do not

attempt to derive parameters from the addition or subtraction

of other information. While addition or subtraction would yield

meaningful results for an individual device, the values given in

this data sheet reflect statistical variations and worst cases. Con-

sequently, parameters cannot be added meaningfully to derive

longer times.

Timing requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Switching characteristics specify how the processor changes its

signals. No control is possible over this timing; circuitry exter-

nal to the processor must be designed for compatibility with

these signal characteristics. Switching characteristics indicate

what the processor will do in a given circumstance. Switching

characteristics can also be used to ensure that any timing

requirement of a device connected to the processor (such as

memory) is satisfied.

Rev. A

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ADSP-21992

half the core clock rate. If the peripheral clock rate is equal to the

core clock rate, the maximum peripheral clock rate is 80 MHz

for the ADSP-21992BST, 75 MHz for ADSP-21992BBC and

ADSP-21992YBC, and 50 MHz for the ADSP-21992YST. The

peripheral clock is supplied to the CLKOUT pins.

Clock In and Clock Out Cycle Timing

Table 17 and Figure 7 describe clock and reset operations. Com-

binations of CLKIN and clock multipliers must not select

core/peripheral clocks in excess of 160 MHz/80 MHz for the

ADSP-21992BST, 150 MHz/75 MHz for both the

ADSP-21992BBC and ADSP-21992YBC, and 100 MHz/50 MHz

for the ADSP-21992YST, when the peripheral clock rate is one-

When changing from bypass mode to PLL mode, allow 512

HCLK cycles for the PLL to stabilize.

Table 17. Clock In and Clock Out Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CK

CLKIN Period^{1, 2}

10

200

ns

μs

ns

t_CKL

t_CKH

t_WRST

t_MSS

t_MSH

t_MSD

t_PFD

CLKIN Low Pulse

4.5

CLKIN High Pulse

4.5

RESET Asserted Pulse Width Low

MSELx/BYPASS Stable Before RESET Deasserted Setup

MSELx/BYPASS Stable After RESET Deasserted Hold

MSELx/BYPASS Stable After RESET Asserted

Flag Output Disable Time After RESET Asserted

200t_CLKOUT

40

1000

200

10

Switching Characteristics

t_CKOD

t_CKO

CLKOUT Delay from CLKIN

CLKOUT Period³

0

5.8

ns

12.5

¹In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t_CK= t_CCLK

²In bypass mode, t_CK= t_CCLK

³CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

.

Rev. A

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ADSP-21992

t_CK

CLKIN

t_CKL

t_CKH

t_WRST

RESET

t_MSD

t_PFD

t_MSS

t_MSH

MSEL6–0

BYPASS

DF

t_CKOD

t_CKO

CLKOUT

Figure 7. Clock In and Clock Out Cycle Timing

Rev. A

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ADSP-21992

Programmable Flags Cycle Timing

Table 18 and Figure 8 describe programmable flag operations.

Table 18. Programmable Flags Cycle Timing

Parameter

Min

Max

Unit

Timing Requirement

t_HFI

Switching Characteristics

t_DFOFlag Output Delay with Respect to CLKOUT

t_HFOFlag Output Hold After CLKOUT High

Flag Input Hold Is Asynchronous

3

ns

7

6

ns

CLKOUT

t_DFO

t_HFO

PF

(OUTPUT)

FLAG OUTPUT

t_HFI

PF

(INPUT)

FLAG INPUT

Figure 8. Programmable Flags Cycle Timing

Rev. A

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ADSP-21992

Timer PWM_OUT Cycle Timing

Table 19 and Figure 9 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and has

an absolute maximum input frequency of 40 MHz.

Table 19. Timer PWM_OUT Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristic

t_HTO

Timer Pulse Width Output¹

12.5

(2³²–1) cycles

ns

¹The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

HCLK

t_HTO

PWM_OUT

Figure 9. Timer PWM_OUT Cycle Timing

Rev. A

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ADSP-21992

at the rising edge of EMI clock. ACK low causes the DSP to wait,

and the DSP requires two EMI clock cycles after ACK goes high

to finish the access. For more information, see the External Port

chapter in the ADSP-2199x DSP Hardware Reference.

External Port Write Cycle Timing

Table 20 and Figure 10 describe external port write operations.

The external port lets systems extend read/write accesses in

three ways: wait states, ACK input, and combined wait states

and ACK. To add waits with ACK, the DSP must see ACK low

Table 20. External Port Write Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements^{1, 2}

t_AKW

ACK Strobe Pulse Width

ACK Delay from XMS Low

12.5

ns

t_DWSAK

0.5t_EMICLK– 1

Switching Characteristics

t_CSWS

t_AWS

t_WSCS

t_WSA

t_WW

Chip Select Asserted to WR Asserted Delay

0.5t_EMICLK– 4

0.5t_EMICLK– 3

0.5t_EMICLK– 4

0.5t_EMICLK– 3

t_EMICLK–2 + W³

ns

Address Valid to WR Setup and Delay

WR Deasserted to Chip Select Deasserted

WR Deasserted to Address Invalid

WR Strobe Pulse Width

t_CDA

t_CDD

t_DSW

t_DHW

t_WWR

WR to Data Enable Access Delay

0

WR to Data Disable Access Delay

0.5t_EMICLK– 3

t_EMICLK+ 1 + W³

3.4

0.5t_EMICLK+ 4

t_EMICLK+ 7 + W³

Data Valid to WR Deasserted Setup

WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 5}

WR Deasserted to Data Invalid Hold Time; E_WHC^{4, 6}

WR Deasserted to WR, RD Asserted

t_EMICLK+3.4

t_HCLK

¹t_EMICLKis the external memory interface clock period. t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

³W = (number of wait states specified in wait register) ꢀ t_EMICLK

⁴Write hold cycle memory select control registers (MS 3 CTL).

⁵Write wait state count (E_WHC) = 0

.

⁶Write wait state count (E_WHC) = 1

Rev. A

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August 2007

ADSP-21992

t_CSWS

t_WSCS

MS3–0

IOMS

BMS

A21–0

t_WW

t_WSA

t_AWS

WR

t_WWR

t_AKW

ACK

t_CDD

t_DHW

t_CDA

t_DSW

t_DWSAK

D15–0

RD

Figure 10. External Port Write Cycle Timing

Rev. A

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August 2007

ADSP-21992

External Port Read Cycle Timing

Table 21 and Figure 11 describe external port read operations.

For additional information on the ACK signal, see the discus-

sion on Page 35.

Table 21. External Port Read Cycle Timing

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements

t_AKW

t_RDA

t_ADA

t_SDA

t_SD

ACK Strobe Pulse Width

t_HCLK

ns

RD Asserted to Data Access Setup

Address Valid to Data Access Setup

Chip Select Asserted to Data Access Setup

Data Valid to RD Deasserted Setup

RD Deasserted to Data Invalid Hold

ACK Delay from XMS Low

t_EMICLK– 5+W³

t_EMICLK+ W³

ns

5

0

t_HRD

t_DRSAK

Switching Characteristics

0.5t_EMICLK– 1

t_CSRS

t_ARS

t_RSCS

t_RW

Chip Select Asserted to RD Asserted Delay

0.5t_EMICLK– 3

0.5t_EMICLK– 2

t_EMICLK–2 + W³

0.5t_HCLK– 2

t_HCLK

ns

Address Valid to RD Setup and Delay

RD Deasserted to Chip Select Deasserted Setup

RD Strobe Pulse Width

t_RSA

t_RWR

RD Deasserted to Address Invalid Setup

RD Deasserted to WR, RD Asserted

¹t_EMICLKis the external memory Interface clock period. t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

³W = (number of wait states specified in wait register) ꢀ t_EMICLK

.

Rev. A

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August 2007

ADSP-21992

t_RSCS

t_CSRS

MS3–0

IOMS

BMS

A21–0

t_RW

t_RSA

t_ARS

RD

t_DRSAK

t_RWR

t_AKW

ACK

t_CDA

t_{H RD}

t_SD

D15–0

t_RDA

t_ADA

t_SDA

WR

Figure 11. External Port Read Cycle Timing

Rev. A

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August 2007

ADSP-21992

External Port Bus Request/Grant Cycle Timing

Table 22 and Figure 12 describe external port bus request and

bus grant operations.

Table 22. External Port Bus Request and Grant Cycle Timing

Parameter^{1, 2}

Min

Max

Unit

Timing Requirements

t_BS

BR Asserted to CLKOUT High Setup

4.6

0

ns

t_BH

CLKOUT High to BR Deasserted Hold Time

Switching Characteristics

t_SD

CLKOUT High to xMS, Address, and RD/WR Disable

0.5t_HCLK+ 1

ns

t_SE

CLKOUT Low to xMS, Address, and RD/WR Enable

CLKOUT High to BG Asserted Setup

0

4

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH Asserted Setup

CLKOUT High to BGH Deasserted Hold Time

¹t_HCLKis the peripheral clock period.

²These are timing parameters that are based on worst-case operating conditions.

Rev. A

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August 2007

ADSP-21992

CLKOUT

t_BS

t_BH

BR

t_SD

t_SE

MS3–0

IOMS

BMS

t_SD

t_SE

A21–0

t_SE

t_SD

WR

RD

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 12. External Port Bus Request and Grant Cycle Timing

Rev. A

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August 2007

ADSP-21992

Serial Port Timing

Table 23 and Figure 13 describe SPORT transmit and receive

operations, while Figure 14 and Figure 15 describe SPORT

frame sync operations.

Table 23. Serial Port^{1, 2}

Parameter

Min

Max

Unit

External Clock Timing Requirements

t_SFSE

TFS/RFS Setup Before TCLK/RCLK³

TFS/RFS Hold After TCLK/RCLK³

Receive Data Setup Before RCLK³

Receive Data Hold After RCLK³

TCLK/RCLK Width

4

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKW

t_SCLK

4

1.5

4

0.5t_HCLK–1

2t_HCLK

TCLK/RCLK Period

Internal Clock Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFS Setup Before TCLK⁴; RFS Setup Before RCLK³

4

3

2

5

ns

TFS/RFS Hold After TCLK/RCLK³

Receive Data Setup Before RCLK³

Receive Data Hold After RCLK³

External or Internal Clock Switching Characteristics

t_DFSE

TFS/RFS Delay After TCLK/RCLK (Internally

Generated FS)⁴

14

ns

t_HOFSE

TFS/RFS Hold After TCLK/RCLK (Internally

Generated FS)⁴

3

4

External Clock Switching Characteristics

t_DDTE

Transmit Data Delay After TCLK⁴

t_HDTE

Transmit Data Hold After TCLK⁴

Internal Clock Switching Characteristics

13.4

ns

t_DDTI

Transmit Data Delay After TCLK⁴

Transmit Data Hold After TCLK⁴

ns

t_HDTI

4

t_SCLKIW

TCLK/RCLK Width

0.5t_HCLK– 3.5

0.5t_HCLK+ 2.5

ns

Enable and Three-State Switching Characteristics⁵

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable from External TCLK⁴

Data Disable from External TCLK⁴

Data Enable from Internal TCLK⁴

Data Disable from External TCLK⁴

0

12.1

13

ns

13

12

External Late Frame Sync Switching Characteristics

t_DDTLFSE

Data Delay from Late External TFS with MCE =1, MFD=0^{6, 7}

Data Enable from Late FS or MCE =1, MFD=0^{6, 7}

10.5

ns

t_DTENLFSE

3.5

¹To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.

²Word selected timing for I²S mode is the same as TFS/RFS timing (normal framing only).

³Referenced to sample edge.

⁴Referenced to drive edge.

⁵Only applies to SPORT.

⁶MCE =1, TFS enable, and TFS valid follow t_DDTENFSand t_DDTLFSE

.

⁷If external RFSD/TFS setup to RCLK/TCLK > 0.5t_LSCK, t_DDTLSCKand t_DTENLSCKapply; otherwise, t_DDTLFSEand t_DTENLFSapply.

Rev. A

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August 2007

ADSP-21992

DATA RECEIVE-INTERNAL CLOCK

DATA RECEIVE-EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

t_SCLKW

SAMPLE

EDGE

t_SCLKIW

RCLK

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_HFSE

t_SFSI

t_HFSI

t_SFSE

RFS

DR

RFS

DR

t_SDRE

t_HDRE

t_SDRI

t_HDRI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT-INTERNAL CLOCK

DATA TRANSMIT-EXTERNAL CLOCK

SAMPLE

EDGE

DRIVE

EDGE

DRIVE

EDGE

t_SCLKW

SAMPLE

EDGE

t_SCLKIW

TCLK

t_DFSE

t_HOFSE

t_DFSE

t_HOFSE

t_SFSI

t_HFSI

t_HFSE

t_SFSE

TFS

DT

TFS

DT

t_DDTI

t_DDTE

t_HDTI

t_HDTE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TCLK (EXT)

TFS (“LATE,” EXT)

TCLK/RCLK

t_DDTEN

t_DDTTE

DT

DRIVE

EDGE

DRIVE

EDGE

TCLK (INT)

TFS (“LATE,” INT)

TCLK/RCLK

t_DDTIN

t_DDTTI

DT

Figure 13. Serial Port

Rev. A

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August 2007

ADSP-21992

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

RCLK

t_{HOSFSE/ I}

t_SFSE/I

RFS

DT

t_{DDTE/ I}

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_{HOSFSE/ I}

t_SFSE/I

TFS

t_DDTE/I

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

DT

t_DDTLFSE

Figure 14. Serial Port—External Late Frame Sync (Frame Sync Setup > 0.5t_SCLK

)

Rev. A

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August 2007

ADSP-21992

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

RCLK

t_SFSE/I

t_{HOFSE/ I}

RFS

t_DDTE/I

t_DTENLFSE

t_{HDTE/ I}

1ST BIT

2ND BIT

DT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

TCLK

t_HOFSE/I

t_{SFSE/ I}

TFS

t_{DDTE/ I}

t_{HDTE/ I}

t_DTENLFSE

1ST BIT

2ND BIT

DT

t_DDTLFSE

Figure 15. Serial Port—External Late Frame Sync (Frame Sync Setup < 0.5t_HCLK

)

Rev. A

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August 2007

ADSP-21992

Serial Peripheral Interface Port—Master Timing

Table 24 and Figure 16 describe SPI port master operations.

Table 24. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPID

t_HSPID

Data Input Valid to SCLK Edge (Data Input Setup)

8

1

ns

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

SPISEL Low to First SCLK Edge

2t_HCLK–3

4t_HCLK–1

2t_HCLK–3

2t_HCLK–2

0

ns

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCLK Edge to SPISEL High

Sequential Transfer Delay

t_SPITDM

t_DDSPID

t_HDSPID

SCLK Edge to Data Output Valid (Data Out Delay)

SCLK Edge to Data Output Invalid (Data Out Hold)

6

5

0

Rev. A

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Page 45 of 60

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August 2007

ADSP-21992

t_SPICHM

SPISEL

(OUTPUT)

t_HDSM

t_SPITDM

t_SPICLK

t_SDSCIM

t_SPICLM

SCLK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCLK

(CPOL = 1)

(OUTPUT)

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

t_SSPID

t_HSPID

CPHA = 1

LSB

VALID

MISO

(INPUT)

MSB

VALID

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

CPHA = 0

MSB

LSB

MISO

VALID

(INPUT)

Figure 16. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. A

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August 2007

ADSP-21992

Serial Peripheral Interface Port—Slave Timing

Table 25 and Figure 17 describe SPI port slave operations.

Table 25. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

Serial Clock High Period

2t_HCLK

4t_HCLK

2t_HCLK

2t_HCLK+ 4

2t_HCLK

1.6

ns

Serial Clock Low Period

Serial Clock Period

Last SPICLK Edge to SPISS Not Asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPISS Assertion to First SPICLK Edge

Data Input Valid to SCLK Edge (Data Input Setup)

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

2.4

Switching Characteristics

t_DSOE

SPISS Assertion to Data Out Active

0

8

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS Deassertion to Data High Impedance

SCLK Edge to Data Out Valid (Data Out Delay)

SCLK Edge to Data Out Invalid (Data Out Hold)

10

Rev. A

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Page 47 of 60

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August 2007

ADSP-21992

SPISS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCLK

(CPOL = 0)

(INPUT)

t_SPICLS

t_SDSCI

t_SPICHS

SCLK

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPIDt_HDSPID

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_SSPID

t_HSPID

t_SSPID

MSB

CPHA = 1

MOSI

LSB

(INPUT)

VALID

t_DDSPID

t_DSOE

t_DSDHI

MISO

(OUTPUT)

LSB

MSB

CPHA = 0

t_SSPID

t_HSPID

MSB

VALID

LSB

VALID

MOSI

(INPUT)

Figure 17. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. A

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Page 48 of 60

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August 2007

ADSP-21992

JTAG Test and Emulation Port Timing

Table 26 and Figure 18 describe JTAG port operations.

Table 26. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low^a

TRST Pulse Width²

4

5

4t_TCK

Switching Characteristics

t_DTDO

t_DSYS

TDO Delay from TCK Low

System Outputs Delay After TCK Low³

8

ns

0

22

¹System outputs = DATA15–0, ADDR21–0, MS3–0, RD, WR, ACK, CLKOUT, BG, PF15–0, DT, TCLK, RCLK, TFS, RFS, BMS.

²50 MHz maximum.

³System inputs = DATA15–0, ADDR21–0, RD, WR, ACK, BR, BG, PF15–0, DR, TCLK, RCLK, TFS, RFS, CLKOUT, RESET.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 18. JTAG Port Timing

Rev. A

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Page 49 of 60

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August 2007

ADSP-21992

• Maximum peripheral speed CCLK = 80 MHz, HCLK =

80 MHz

POWER DISSIPATION

Total power dissipation has two components, one due to inter-

nal circuitry and one due to the switching of external output

drivers. Internal power dissipation is dependent on the instruc-

tion execution sequence and the data operands involved.

• External data memory writes occur every other cycle, a rate

of 1/(4t_HCLK), with 50% of the pins switching

• The bus cycle time is 80 MHz (t_HCLK= 12.5 ns)

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

The P_EXTequation is calculated for each class of pins that can

drive as shown in Table 27.

• Number of output pins that switch during each cycle (O)

• The maximum frequency at which they can switch (f)

• Their load capacitance (C)

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation with

the following formula.

• Their voltage swing (V_DD

)

P_TOTAL= P_EXT+ P_INT

and is calculated by the formula below.

where:

P

_EXTis from Table 27.

P_EXT= O × C × V_DD²× f

_INTis I_DDINTꢀ 2.5 V, using the calculation I_DDINTlisted in

Power Dissipation.

The load capacitance includes the package capacitance (C_INof

the processor). The switching frequency includes driving the

load high and then back low. Address and data pins can drive

high and low at a maximum rate of 1/(2t_CK). The write strobe

can switch every cycle at a frequency of 1/t_CK. Select pins switch

at 1/(2t_CK), but selects can switch on each cycle. For example,

estimate P_EXTwith the following assumptions:

Note that the conditions causing a worst-case P_EXTare different

from those causing a worst-case P_INT. Maximum P_INTcannot

occur while 100% of the output pins are switching from all ones

to all zeros. Note also that it is not common for an application to

have 100% or even 50% of the outputs switching

simultaneously.

• A system with one bank of external data memory—

asynchronous RAM (16-bit)

• One 64K ꢀ 16 RAM chip is used with a load of 10 pF

Table 27. P_EXTCalculation Example

2

Pin Type

Address

MSx

No. of Pins

% Switching

ꢀ C

ꢀ f

ꢀ V_DD

10.9 V

= P_EXT

15

1

50

0

10 pF

20 MHz

40 MHz

20 MHz

80 MHz

= 0.01635 W

= 0.0 W

WR

1

= 0.00436 W

= 0.01744 W

Data

16

1

50

CLKOUT

= 0.00872 W

= 0.04687 W

Rev. A

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Page 50 of 60

|

August 2007

ADSP-21992

TEST CONDITIONS

The DSP is tested for output enable, disable, and hold time.

INPUT

OR

OUTPUT

OUTPUT DISABLE TIME

1.5V

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

to decay by ΔV is dependent on the capacitive load, C_L, and the

load current, I_L. This decay time can be approximated by the

following equation.

Figure 21. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

OUTPUT ENABLE TIME

Output pins are considered to be enabled when they have made

a transition from a high impedance state to when they start driv-

ing. The output enable time t_ENAis the interval from when a

reference signal reaches a high or low voltage level to when the

output has reached a specified high or low trip point, as shown

in the Output Enable/Disable diagram (Figure 19). If multiple

pins (such as the data bus) are enabled, the measurement value

is that of the first pin to start driving.

C_LΔV

I_L

-------------

=

t_DECAY

The output disable time t_DISis the difference between

_MEASUREDand t_DECAYas shown in Figure 19. The time t_MEA-

_SUREDis the interval from when the reference signal switches to

when the output voltage decays ΔV from the measured output

high or output low voltage. The t_DECAYis calculated with test

loads C_Land I_L, and with ΔV equal to 0.5 V.

t

EXAMPLE SYSTEM HOLD TIME CALCULATION

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation at Output Disable Time

on Page 51. Choose ΔV to be the difference between the output

voltage of the ADSP-21992 and the input threshold for the

device requiring the hold time. A typical ΔV will be 0.4 V. C_Lis

the total bus capacitance (per data line), and I_Lis the total leak-

age or three-state current (per data line). The hold time will be

REFERENCE

SIGNAL

t_MEASURED

t_ENA

t_DIS

V_{OH (MEASURED)}

t

_DECAYplus the minimum disable time (i.e., t_DATRWHfor the

V

_{OH (MEASURED)}– ꢂV 2.0V

write cycle).

V_{OL (MEASURED)}+ ꢂV 1.0V

V_{OL (MEASURED)}

t_DECAY

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

Figure 19. Output Enable/Disable

I

OL

TO

OUTPUT

1.5V

50pF

I

OH

Figure 20. Equivalent Device Loading for AC Measurements (Includes All

Fixtures)

Rev. A

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Page 51 of 60

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August 2007

ADSP-21992

PIN CONFIGURATIONS

Table 28 identifies the signal for each CSP_BGA ball number.

Table 29 identifies the CSP_BGA ball number for each signal

name. Table 30 identifies the signal for each LQFP lead.

Table 31 identifies the LQFP lead for each signal name. Table 4

on Page 17 describes each signal.

Rev. A

|

Page 52 of 60

|

August 2007

ADSP-21992

Table 28. 196-Ball CSP_BGA Signal by Ball Number

Ball No.

A1

A2

A3

A4

A5

A6

A7

A8

Signal

nc

DR

DT

RFS

VIN4

BSHAN

VIN0

VIN1

VIN3

PF0/SPISS

PF4/SPISEL4

PF6/SPISEL6

PF7/SPISEL7

nc

SCK

RCLK

TCLK

TFS

VIN6

ASHAN

VIN2

SENSE

CAPB

PF1/SPISEL1

PF5/SPISEL5

PF8

Ball No.

D8

D9

D10

D11

D12

D13

D14

E1

E2

E3

E4

E5

E6

E7

E8

E9

E10

E11

E12

E13

E14

F1

Signal

AVSS

PF3/SPISEL3

AUXTRIP

VDDEXT

AUX1

AUX0

PF15

A16

A17

WR

GND

VDDEXT

nc

GND

EIA

EIB

EIS

A14

Ball No.

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

J1

J2

J3

J4

J5

J6

J7

J8

J9

Signal

A10

A11

MS3

GND

nc

Ball No.

L8

L9

Signal

VDDINT

VDDEXT

GND

BMODE2

BMODE1

CLKIN

A2

L10

L11

L12

L13

L14

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

N1

A9

A3

MS2

A10

A11

A12

A13

A14

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

C1

nc

VDDEXT

TMR0

POR

RESET

A8

GND

VDDEXT

GND

VDDEXT

CANRX

CL

A9

BMS

VDDEXT

nc

GND

TMS

TCK

TDI

A6

AL

PWMPOL

PWMTRIP

BYPASS

BMODE0

A0

A1

D13

D11

D9

F2

F3

F4

F5

F6

F7

F8

A15

BG

GND

nc

N2

N3

N4

N5

N6

N7

N8

J10

J11

J12

J13

J14

K1

PF9

PF13

BR

D7

D5

D3

nc

C2

RD

F9

nc

K2

A7

N9

D1

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

D1

MISO

MOSI

VIN7

VIN5

CAPT

VREF

CML

PF2/SPISEL2

PF10

PF11

PF12

F10

F11

F12

F13

F14

G1

G2

G3

G4

G5

nc

VDDINT

EIZ

TMR2

XTAL

A12

K3

K4

K5

K6

K7

K8

K9

K10

K11

K12

K13

K14

L1

MS0

GND

VDDINT

EMU

TRST

TDO

A4

N10

N11

N12

N13

N14

P1

P2

P3

P4

P5

CH

AH

nc

PWMSYNC

PWMSR

nc

D15

D14

D12

D10

D8

D6

A13

BGH

VDDINT

nc

G6

G7

G8

P6

P7

P8

PF14

A18

nc

D4

D2

A19

G9

nc

L2

A5

P9

D2

D3

D4

D5

D6

IOMS

ACK

AVDD

AVSS

G10

G11

G12

G13

G14

nc

L3

L4

L5

L6

MS1

VDDEXT

VDDINT

VDDEXT

VDDINT

P10

P11

P12

P13

P14

D0

BL

BH

CANTX

nc

GND

TMR1

CONVST

CLKOUT

D7

L7

Rev. A

|

Page 53 of 60

|

August 2007

ADSP-21992

Table 29. 196-Ball CSP_BGA Ball Number by Signal

Signal

A0

A1

A2

A3

A4

A5

A6

A7

Ball No.

N1

N2

M1

M2

L1

L2

K1

K2

Signal

CLKOUT

CML

CONVST

D0

D1

D2

D3

D4

Ball No.

G14

C9

G13

P10

N9

P9

Signal

nc

Ball No.

A1

A14

E6

E7

E8

E9

E10

F5

Signal

PF15

POR

PWMPOL

PWMSYNC

PWMSR

PWMTRIP

RCLK

Ball No.

D14

H13

M11

N13

N14

M12

B2

N8

P8

nc

RD

C2

A8

A9

J1

J2

D5

D6

N7

P7

nc

F6

F7

RESET

RFS

H14

A4

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

ACK

AH

H1

H2

G1

G2

F1

F2

E1

E2

D1

D2

D4

N11

M10

B6

D10

D12

D13

D5

D7

D8

D9

D10

D11

D12

D13

D14

D15

DR

N6

P6

N5

P5

N4

P4

N3

P3

nc

F8

F9

F10

G5

G6

G7

G8

G9

G10

H5

H6

H7

H8

H9

H10

J5

J6

J7

J8

SCK

SENSE

TCK

TCLK

TDI

TDO

TFS

TMR0

TMR1

TMR2

TMS

B1

B8

J13

B3

J14

K14

B4

H12

G12

F13

J12

K13

D11

E5

H11

J4

L4

L6

L9

P2

A2

A3

DT

EIA

EIB

EIS

E12

E13

E14

F12

K12

E4

E11

F4

G11

H4

J11

K4

TRST

AL

VDDEXT

VDDINT

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VREF

ASHAN

AUXTRIP

AUX1

AUX0

AVDD

AVSS

BG

EIZ

EMU

GND

IOMS

MISO

MOSI

MS0

MS1

MS2

MS3

D6

D7

D8

F3

J9

L10

M5

M7

G4

L5

L7

J10

N12

P1

P14

A10

B10

C10

D9

A11

B11

A12

A13

B12

B13

C11

C12

C13

B14

C14

BGH

BL

BH

G3

P11

P12

M14

L13

L12

J3

C1

A6

M13

B9

C7

M8

P13

N10

M9

L14

K5

K6

K7

K8

PF0/SPISS

PF1/SPISEL1

PF2/SPISEL2

PF3/SPISEL3

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8

PF9

PF10

PF11

PF12

BMODE0

BMODE1

BMODE2

BMS

BR

BSHAN

BYPASS

CAPB

CAPT

CANRX

CANTX

CH

L8

K11

F11

A7

A8

B7

A9

A5

C6

B5

C5

C8

E3

F14

K9

K10

L11

M4

M6

D3

C3

C4

K3

L3

M3

H3

CL

CLKIN

PF13

PF14

WR

XTAL

Rev. A

|

Page 54 of 60

|

August 2007

ADSP-21992

Table 30. 176-Lead LQFP Signal by Lead Number

Lead No.

1

2

3

4

5

6

7

8

Signal

nc

VDDEXT

RCLK

SCK

MISO

MOSI

RD

Lead No.

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

Signal

VDDEXT

A4

A3

A2

A1

A0

D15

D14

D13

D12

D11

GND

VDDEXT

GND

VDDINT

D10

Lead No.

89

90

91

92

93

94

95

96

Signal

nc

VDDEXT

BYPASS

BMODE0

BMODE1

BMODE2

nc

GND

VDDINT

EMU

TRST

TDO

TDI

Lead No.

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

Signal

VDDEXT

PF11

PF10

PF9

PF8

PF7/SPISEL7

PF6/SPISEL6

PF5/SPISEL5

PF4/SPISEL4

GND

VDDEXT

PF3/SPISEL3

PF2/SPISEL2

PF1/SPISEL1

PF0/SPISS

GND

VDDINT

AVSS

AVDD

nc

VREF

CML

CAPT

CAPB

SENSE

VIN3

VIN2

VIN1

VIN0

ASHAN

BSHAN

VIN4

9

WR

ACK

BR

97

98

99

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

BG

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

BGH

IOMS

BMS

MS3

GND

VDDEXT

MS2

MS1

MS0

GND

VDDINT

A19

A18

A17

A16

A15

A14

A13

GND

VDDEXT

A12

A11

A10

A9

TMS

TCK

POR

D9

D8

D7

D6

RESET

CLKIN

XTAL

CLKOUT

CONVST

TMR0

GND

VDDEXT

TMR1

TMR2

EIS

GND

VDDINT

EIZ

EIB

EIA

AUXTRIP

AUX1

AUX0

PF15

PF14

PF13

PF12

GND

D5

GND

VDDINT

D4

D3

D2

D1

D0

CANRX

GND

VDDEXT

CL

CH

BL

BH

AL

AH

CANTX

nc

PWMSYNC

PWMPOL

PWMSR

PWMTRIP

GND

VIN5

VIN6

VIN7

AVSS

AVDD

DT

DR

RFS

TFS

A8

A7

A6

A5

GND

nc

TCLK

GND

nc

Rev. A

|

Page 55 of 60

|

August 2007

ADSP-21992

Table 31. 176-Lead LQFP Lead Number by Signal

Signal

A0

A1

Lead No.

50

49

Signal

CAPB

CAPT

CH

Lead No.

156

155

77

Signal

EIS

EIZ

Lead No.

116

119

99

Signal

PWMTRIP

RCLK

Lead No.

87

4

A10

35

EMU

RD

8

A11

A12

A13

A14

A15

A16

A17

A18

A19

A2

A3

A4

A5

A6

34

33

30

29

28

27

26

25

24

48

47

46

40

39

CL

76

IOMS

MISO

MOSI

MS0

MS1

MS2

MS3

nc

14

6

7

21

20

19

16

1

2

42

43

44

83

89

RESET

RFS

SCK

SENSE

TCK

TCLK

TDI

TDO

TFS

TMR0

TMR1

TMR2

TMS

106

172

5

CLKIN

CLKOUT

CML

CONVST

D0

107

109

154

110

72

71

60

55

54

53

52

51

70

157

104

174

102

101

173

111

114

115

103

100

3

D1

D10

D11

D12

D13

D14

D15

D2

nc

TRST

A7

38

D3

69

nc

90

VDDEXT

VDDINT

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VREF

A8

A9

ACK

AH

37

36

10

81

D4

D5

D6

D7

D8

D9

68

65

64

63

62

61

17

22

31

41

56

58

66

74

88

97

112

117

129

142

148

175

171

170

121

120

nc

96

18

32

45

57

75

91

113

133

143

23

130

131

132

152

176

147

146

135

134

128

127

126

125

145

144

141

140

139

138

137

136

105

85

AL

80

ASHAN

AUX0

AUX1

AUXTRIP

AVDD

AVSS

BG

162

124

123

122

151

169

150

168

12

13

79

78

93

94

95

15

11

163

92

73

GND

DR

PF0/SPISS

PF1/SPISEL1

PF10

PF11

PF12

PF13

PF14

PF15

PF2/SPISEL2

PF3/SPISEL3

PF4/SPISEL4

PF5/SPISEL5

PF6/SPISEL6

PF7/SPISEL7

PF8

PF9

POR

PWMPOL

PWMSR

PWMSYNC

59

67

98

118

149

161

160

159

158

164

165

166

167

153

9

BGH

BH

BL

BMODE0

BMODE1

BMODE2

BMS

BR

BSHAN

BYPASS

CANRX

CANTX

DT

EIA

EIB

86

84

WR

XTAL

82

108

Rev. A

|

Page 56 of 60

|

August 2007

ADSP-21992

OUTLINE DIMENSIONS

15.00

BSC

DETAIL B

SQ

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

G

H

J

13.00

BSC

1.00 BSC

K

L

M

N

P

1.85

1.70

1.55

1.00 BSC

TOP VIEW

DETAIL A

13.00 BSC

BOTTOM VIEW

0.75

0.70

0.65

1.10

1.00

0.90

0.55

NOM

1.10

1.00

0.90

0.57

0.52

0.47

0.70

0.60

0.50

0.20

MAX BALL

COPLANARITY

SEATING PLANE

BALL

DIAMETER

DETAIL A

DETAIL B

DIMENSIONS SHOWN IN MILLIMETERS

NOTES:

1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO THE

PACKAGE EDGES.

2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE TO THE

BALL GRID.

3. DIMENSIONS COMPLY WITH JEDEC STANDARD MO-192 VARIATION AAE-1 WITH THE EXCEPTION OF

MAXIMUM HEIGHT.

4. CENTER DIMENSIONS ARE NOMINAL.

Figure 22. 196-Ball CSP_BGA (BC-196-2)

Rev. A

|

Page 57 of 60

|

August 2007

ADSP-21992

26.20

26.00 SQ

25.80

0.75

0.60

0.45

1.60

MAX

133

132

176

1

PIN 1

24.20

24.00 SQ

23.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.15

0.05

89

44

45

SEATING

PLANE

0.08 MAX

88

COPLANARITY

VIEW A

0.27

0.22

0.17

0.50

BSC

VIEW A

ROTATED 90° CCW

LEAD PITCH

DIMENSIONS SHOWN IN MILLIMETERS

176-LEAD LOW PROFILE QUAD FLAT PACKAGE [LQFP] ST-176

NOTES:

1. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION,

WHEN MEASURED IN THE LATERAL DIRECTION.

2. CENTER DIMENSIONS ARE NOMINAL.

3. DIMENSIONS COMPLY WITH JEDEC STANDARD MS-026-BGA

Figure 23. 176-Lead LQFP (ST-176)

Rev. A

|

Page 58 of 60

|

August 2007

ADSP-21992

ORDERING GUIDE

Model

Temperature Range¹Instruction Rate Operating Voltage Package Description Package Option

ADSP-21992BBC

ADSP-21992YBC

ADSP-21992BST

–40ЊC to +85ЊC

–40ЊC to +125ЊC

–40ЊC to +85ЊC

150 MHz

160 MHz

100 MHz

2.5 Int. V/3.3 Ext. V 196-Ball CSP_BGA

2.5 Int. V/3.3 Ext. V 176-Lead LQFP

BC-196-2

ST-176

ADSP-21992BSTZ²–40ЊC to +85ЊC

ADSP-21992YST –40ЊC to +125ЊC

¹Referenced temperature is ambient temperature.

²Z = RoHS Complaint Part

Rev. A

|

Page 59 of 60

|

August 2007

ADSP-21992

registered trademarks are the property of their respective owners.

D03163-0-8/07(A)

Rev. A

|

Page 60 of 60

|

August 2007


型号：	ADSP-21992BSTZ
厂家：	ADI
描述：	Mixed-Signal DSP Controller with CAN 混合信号DSP控制器， CAN 控制器
文件：	总60页 (文件大小：2028K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-21992BSTZ [ADI]

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