ADSP-21MOD980N-000 [ADI]
MultiPort Internet Gateway Processor; 多端口网络网关处理器
| 型号： | ADSP-21MOD980N-000 |
| 厂家： | 
ADI |
| 描述： | MultiPort Internet Gateway Processor |
| 文件： | 总42页 (文件大小：554K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MultiPort Internet
Gateway Processor
a
ADSP-21mod980N
Preliminary Technical Data
PERFORMANCE FEATURES
INTEGRATION FEATURES
Complete Single Device Multi-Port Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each DSP Can Implement two V.34/V.90 Data/Fax
Modem Channels (includes Datapump and
Controller)
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
16 Mbits of On-Chip SRAM, Configured as 9 Mbits of
Program Memory and 7 Mbits of Data Memory
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
352-Ball PBGA with a 35mm
؋
35mm footprint Low Power Version: 640 MIPS Sustained Performance,
12.5 ns Instruction Time @ 1.9 Volts nominal
(internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Low Power Dissipation, 25 mW (typical) per Channel
Powerdown Mode Featuring Low CMOS Standby Power
Dissipation
SYSTEM CONFIGURATION FEATURES
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports 24/32
Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate Reset Pins for Each Internal Processor
21mod980N
Host IDMA
SPORT0
SPORT1
2188N
DSP 1
2188N
DSP 2
2188N
DSP 3
2188N
DSP 4
2188N
DSP 7
2188N
DSP 8
2188N
DSP 6
2188N
DSP 5
CONTROL
Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
REV. PrB 6/2001
This information applies to a product under development. Its characteristics One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
Tel:781/329-4700
Fax:781/326-8703
World Wide Web Site: http://www.analog.com
©Analog Devices,Inc., 2001
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
GENERAL DESCRIPTION
MODEM SOFTWARE
The ADSP-21mod980N is a multi-port Internet gateway
processor optimized for implementation of a complete
V.34/V.90 digital modem. All datapump and controller
functions can be implemented on a single device, offering
the lowest power consumption and highest possible modem
port density.
The following software is available as object code from
Analog Devices Inc.
•
ADSP-21mod Family Dynamic Internet Voice
AccessTM (DIVA) Voice Over Network Solution.
•
ADSP-21mod980-210N Multiport Internet Gateway
Processor Modem Solution.
The ADSP-21mod980N combines the ADSP-2100 Family
base architecture (three computational units, data address
generators, and a program sequencer) with two serial ports,
a 16-bit internal DMA port, a byte DMA port, a program-
mable timer, Flag I/O, extensive interrupt capabilities, and
on-chip program and data memory.
A complete system implementation requires the
ADSP-21mod980N device plus modem or voice software.
The modem software executes general modem control,
command sets, error correction, and data compression,
data modulations (for example, V.34 and V.90), and host
interface functions.The host interface allows system access
to modem statistics, such as call progress, connect speed,
retrain count, symbol rate, and other modulation
parameters.
The ADSP-21mod980N integrates 16 Mbits of on-chip
memory, configured as 384 Kwords (24-bit) of program
RAM, and 448 Kwords (16-bit) of data RAM. Power-down
circuitry is also provided to reduce the average and standby
power consumption of equipment which in turn reduces
equipment cooling requirements. The ADSP-21mod980N
is available in a 35 mm x 35 mm, 352-lead PBGA package.
The modem datapump and controller software reside in
on-chip SRAM and do not require additional memory. You
can configure the ADSP-21mod980N dynamically by
downloading software from the host through the 16-bit
IDMA interface. This SRAM-based architecture provides a
software upgrade path to other applications, such as
voice-over-IP, and to future standards.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-21mod980N operates with a 12.5 ns instruction
cycle time. Every instruction can execute in a single proces-
sor cycle.
The ADSP-21mod980N’s flexible architecture and com-
prehensive instruction set allow the processor to perform
multiple operations in parallel. In one processor cycle, the
ADSP-21mod980N can:
DEVELOPMENT SYSTEM
Analog Devices' wide range of software and hardware devel-
opment tools supports the ADSP-218x N Series. The DSP
tools include an integrated development environment
(IDE), an evaluation kit, and a serial port emulator.
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
VisualDSP® is an integrated development environment,
allowing for fast and easy development, debug and deploy-
ment. The VisualDSP project management environment
lets programmers develop and debug an application. This
environment includes an easy-to-use assembler that is based
on an algebraic syntax; an archiver (librarian/library
builder); a linker; a loader; a cycle-accurate, instruc-
tion-level simulator; a C compiler; and a C run-time library
that includes DSP and mathematical functions.
This takes place while the processor continues to:
•
•
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal
DMA port
•
•
Receive and/or transmit data through the byte DMA
port
Debugging both C and assembly programs with the Visu-
alDSP debugger, programmers can:
Decrement timer
• View mixed C and assembly code (interleaved source and
object information)
• Insert break points
• Set conditional breakpoints on registers, memory, and
stacks
• Trace instruction execution
• Fill and dump memory
• Source level debugging
2
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
The VisualDSP IDE lets programmers define and manage
DSP software development. The dialog boxes and property
pages let programmers configure and manage all of the
ADSP-218x development tools, including the syntax high-
lighting in the VisualDSP editor. This capability controls
how the development tools process inputs and generate
outputs.
The ADSP-218x EZ-ICE ® Emulator provides an easier
and more cost-effective method for engineers to develop
and optimize DSP systems, shortening product develop-
ment cycles for faster time-to-market. The
ADSP-21mod980N integrates on-chip emulation support
with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer
mechanical clearance considerations than other
ADSP-2100 Family EZ-ICEs. The ADSP-21mod980N
device need not be removed from the target system when
using the EZ-ICE, nor are any adapters needed. Due to the
small footprint of the EZ-ICE connector, emulation can be
supported in final board designs.The EZ-ICE performs a
full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and
altered
• PC upload and download functions
• Instruction-level emulation of program booting and
execution
• Complete assembly and disassembly of instructions
• C source-level debugging
ADDITIONAL INFORMATION
This data sheet provides a general overview of
ADSP-21mod980N functionality. For specific information
about the modem processors, refer to the ADSP-2188N
data sheet. For additional information on the architecture
and instruction set of the modem processors, refer to the
ADSP-2100 Family User’s Manual (3rd edition). For more
information about the development tools, refer to the
ADSP-2100 Family Development Tools Data Sheet.
REV. PrB 6/2001
3
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ARCHITECTURE OVERVIEW
Figure 2 on page 4 is a functional block diagram of the
ADSP-21mod980N. It contains eight independent digital
signal processors.
17
DATA<23:8>, A<0>
IAD <15:0>,
IDMA CNTL
CLKIN
20
20
IAD<15:0>, IDMA CNTL
3
PF<0:2>/MODE A:C
2188N
2188N
DSP 4
2188N
DSP 5
2188N
DSP 2
2188N
DSP 6
2188N
DSP 1
2188N
DSP 8
2188N
DSP 7
DSP 3
4
4
SPORT0A
SPORT1
SPORT0B
4
8
EMULATOR
SIGNALS ROUTED TO EACH RESPECTIVE DIE
IDMA CNTL = IAL, IRD, IWR, IACK
8
BR <8:1>
INTERRUPTS = IRQE (PF4), IRQL0(PF5), IRQL1(PF6), IRQ2(PF7)
8
BG <8:1>
8
EMULATOR = EMS, EINT, ELIN, EBR, EBG, ECLK
ELOUT, ERESET
RESET <8:1>
8
CLKOUT <8:1>
SPORT0A, SPORT 0B
8
EE <8:1>
= RFS0, DR0, DT0, SCKL0
8
IS <8:1>
SPORT1 = RFS1, TFS1, DR1, SCKL1
8
TFS0 <8:1>
8
DT1 <8:1>
32
NOTE:
INTERRUPTS <8:1>
1. PWD AND PF3/MODE D ARE TIED HIGH
SUBTOTAL = 177 SIGNAL BALLS
109
GND
44
VDDINT
22
VDDEXT
SUBTOTAL = 175 POWER BALLS
TOTAL = 352 BALLS
Figure 2. ADSP-21mod980N Functional Block Diagram
accessed through a single external pin. Other signals remain
Every modem processor has:
separate and they are accessed through separate external
pins for each processor.
•
•
•
•
A DSP core
256K bytes of RAM
Two serial ports
An IDMA host.
The arrangement of the eight modem processors in the
ADSP-21mod980N makes one basic configuration possi-
ble: a slave configuration. In this configuration, the data
pins of all eight processors connect to a single bus structure.
The signals of each modem processor are accessed through
the external pins of the ADSP-21mod980N. Some signals
are bussed with the signals of the other processors and are
4
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
All eight modem processors have identical functions and
have equal status. Each of the modem processors is con-
nected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in “Memory
Architecture” on page 10). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem pro-
cessor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:
•
•
•
is bidirectional and has a separate, double-buffered
transmit and receive section.
can use an external serial clock or generate its own
serial clock internally.
has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
•
supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding accord-
ing to CCITT recommendation G.711.
•
•
receive and transmit sections can generate unique
interrupts on completing a data word transfer.
can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, pro-
grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config-
ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6 lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
REV. PrB 6/2001
5
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Table 1. Common Mode Pins
Pin Name(s)
# of Pins
Input/Output
Function
RESET
BR
8
I
Processor Reset Input
8
I
Bus Request Input
BG
8
O
I
Bus Grant Output
IRQ2 /
PF7
8
Edge- or Level-Sensitive Interrupt Request1
Programmable I/O Pin
8
I/O
I
IRQL1 /
PF6
8
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
8
I/O
I
IRQL0 /
PF5
8
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
8
I/O
I
IRQE /
PF4
8
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
8
I/O
I
Mode C /
PF2
1
Mode Select Input - Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input - Checked Only During RESET
Programmable I/O Pin During Normal Operation
Mode Select Input - Checked Only During RESET
Programmable I/O Pin During Normal Operation
Clock Input
1
I/O
I
Mode B /
PF1
1
1
I/O
I
Mode A /
PF0
1
1
I/O
I
CLKIN
CLKOUT
SPORT
VDD and GND
EZ-Port
1
8
O
I/O
I
Processor Clock Output
28
175
16
Serial Port I/O Pins2
Power and Ground
I/O
For Emulation Use
1
2
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the ADSP-21mod980N will vector
to the appropriate interrupt vector address when the pin is asserted, either by external devices, or set as a programmable flag.
SPORT configuration determined by the ADSP-21mod980N System Control Register. Software configurable.
MEMORY INTERFACE PINS
The ADSP-21mod980N modem pool is used in Slave
Mode. In Slave Mode, the Modem Processors operate in
host configuration. The operating mode is determined by
the state of the Mode C pin during RESET and cannot be
changed while the modem pool is running. See the “Mem-
ory Architecture” section for more information.
6
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IRQE is edge sensitive. The priorities and vector addresses
of all interrupts are shown in Table on page 7. When the
modem pool is reset, interrupt servicing is disabled.
Table 2. Host Pins (Mode C = 1) Modem Processors 1-8
# of
Pins Output
Input/
Table 3. Interrupt Priority and Interrupt Vector
Addresses
Pin Name
Function
IAD[15:0]
321
1
I/O
O
IDMA Port
Address/Data Bus
Interrupt Vector Address
Source Of Interrupt
(Hex)
A0
Address Pin for Exter-
nal I/O, Program,
Data, or Byte access
RESET (or Power-Up
with PUCR = 1)
0x0000 (Highest Priority)
0x002C
Power Down
(Nonmaskable)
D[23:8]
16
I/O
Data I/O Pins for Pro-
gram, Data Byte and
I/O spaces
IRQ2
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
21
21
21
I
I
I
IDMA Write Enable
IDMA Read Enable
IRQL1
IWR
IRD
IAL
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
IDMA Address Latch
Pin
IS
8
I
IDMA Selects
IACK
21
O
IDMA Port Acknowl-
edge Configurable in
Mode D; Open Drain
BDMA Interrupt
SPORT1 Transmit or
IRQ1
1
There are two distinct IAD buses. One addresses DSPs 1-4 and the other
communicates with DSPs 5-8. See Figure 2 for details.
SPORT1 Receive or
IRQ0
0x0024
INTERRUPTS
Timer
0x0028 (Lowest Priority)
The interrupt controller allows each modem processor in
the modem pool to respond individually to eleven possible
interrupts and RESET with minimum overhead. The
ADSP-21mod980N provides four dedicated external inter-
rupt input pins, IRQ2, IRQL1, IRQL0, and IRQE (shared
with the PF[7:4] pins) for each modem processor. The
ADSP-21mod980N also supports internal interrupts from
the timer, the byte DMA port, the serial port, software, and
the power-down control circuit. The interrupt levels are
internally prioritized and individually maskable (except
power down and RESET). The IRQ2, IRQ1, and IRQ0
input pins can be programmed to be either level- or
edge-sensitive. IRQL0 and IRQL1 are level-sensitive and
LOW POWER OPERATION
The ADSP-21mod980N has three low power modes that
significantly reduce the power dissipation when the device
operates under standby conditions. These modes are:
•
•
•
Power Down
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
POWER DOWN
The ADSP-21mod980N modem pool has a low power fea-
ture that lets the modem pool enter a very low power
dormant state through software control. Here is a brief list
REV. PrB 6/2001
7
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
of power-down features. Refer to the ADSP-2100 Family
User’s Manual, “System Interface” chapter, for detailed
information about the power-down feature.
When the IDLE (n) instruction is used in systems that have
an externally generated serial clock (SCLK), the serial clock
rate may be faster than the modem pool’s reduced internal
clock rate. Under these conditions, interrupts must not be
generated at a faster rate than can be serviced, due to the
additional time the modem pool takes to come out of the
idle state (a maximum of n cycles).
•
Quick recovery from power down. The modem pool
begins executing instructions in as few as 200 CLKIN
cycles.
•
Support for an externally generated TTL or CMOS
processor clock. The external clock can continue run-
ning during power down without affecting the lowest
power rating and 200 CLKIN cycle recovery.
SYSTEM CONFIGURATION
Figure on page 9 shows the hardware interfaces for a typi-
cal multichannel modem configuration with the
•
Power down is initiated by the software power-down
force bit. Interrupt support allows an unlimited num-
ber of instructions to be executed before optionally
powering down.
ADSP-21mod980N. Other system design considerations
such as host processing requirements, electrical loading,
and overall bus timing must all be met. A line interface can
be used to connect the multichannel subscriber or client
data stream to the multichannel serial port of the
ADSP-21mod980N. The IDMA port of the
ADSP-21mod980N is used to give a host processor full
access to the internal memory of the ADSP-21mod980N.
This lets the host dynamically configure the
ADSP-21mod980N by loading code and data into its inter-
nal memory. This configuration also lets the host access
server data directly from the ADSP-21mod980N’s internal
memory. In this configuration, the Modem Processors
should be put into host memory mode where Mode C = 1,
Mode B = 0, and Mode A = 1.
•
•
Context clear/save control allows the modem pool to
continue where it left off or start with a clean context
when leaving the power down state.
The RESET pin also can be used to terminate power
down.
IDLE
When the ADSP-21mod980N is in the Idle Mode, the
modem pool waits indefinitely in a low power state until an
interrupt occurs. When an unmasked interrupt occurs, it is
serviced; execution then continues with the instruction fol-
lowing the IDLE instruction. In Idle mode IDMA, BDMA
and autobuffer cycle steals still occur.
SLOW IDLE
The IDLE instruction is enhanced on the
ADSP-21mod980N to let the modem pool’s internal clock
signal be slowed, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the
normal clock rate, is specified by a selectable divisor given
in the IDLE instruction.
The format of the instruction is:
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the
modem pool fully functional, but operating at the slower
clock rate. While it is in this state, the modem pool’s other
internal clock signals, such as SCLK, CLKOUT, and timer
clock, are reduced by the same ratio. The default form of
the instruction, when no clock divisor is given, is the stan-
dard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows
down the modem pool’s internal clock and thus its response
time to incoming interrupts. The one-cycle response time
of the standard idle state is increased by n, the clock divisor.
When an enabled interrupt is received, the
ADSP-21mod980N will remain in the idle state for up to a
maximum of n modem pool cycles (n = 16, 32, 64, or 128)
before resuming normal operation.
8
6/2001 REV. PrB
PRELIMINARY TECHNICA L DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
T1/E1
LINE
T1/E1
LINE
T1/E1
LINE
INTERFACE
INTERFACE
INTERFACE
SPORT
SPORT
SPORT
21mod980N
21mod980N
21mod980N
ST/CNTL IDMA
ST/CNTL IDMA
ST/CNTL IDMA
Figure 3. Multichannel Modem Configuration
CLOCK SIGNALS
The CLKIN input cannot be halted, changed during oper-
ation, or operated below the specified frequency during
normal operation. The only exception is while the processor
is in the power down state. For additional information, refer
to Chapter 9, ADSP-2100 Family User’s Manual for a
detailed explanation of this power down feature.
The ADSP-21mod980N is clocked by a TTL-compatible
clock signal that runs at half the instruction rate; a 40 MHz
input clock yields a 12.5 ns processor cycle, which is equiv-
alent to 80 MHz. Normally, instructions are executed in a
single processor cycle. All device timing is relative to the
internal instruction clock rate, which is indicated by the
CLKOUT signal when enabled. The clock input signal is
connected to the processor’s CLKIN input.
REV. PrB 6/2001
9
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
A clock output (CLKOUT) signal is generated by the pro-
cessor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
•
•
Figure on page 11 shows Data Memory
Table on page 11 shows the generation of address bits
based on the DMOVLAY values. Access to external
memory is not available
RESET
PM MODE B = 0
The RESET signals initiate a reset of each modem proces-
sor in the ADSP-21mod980N. The RESET signals must be
asserted during the power-up sequence to assure proper ini-
tialization. RESET during initial power-up must be held
long enough to let the internal clocks stabilize. If RESETs
are activated any time after power up, the clocks continue to
run and do not require stabilization time.
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 - 0x1FFF
0x2000 -
ACCESSIBLE WHEN
0x3FFF
PM O VLAY = 0
The power-up sequence is defined as the total time required
for the oscillator circuits to stabilize after a valid VDD is
applied to the processors, and for the internal phase-locked
loops (PLL) to lock onto the specific frequency. A mini-
mum of 2000 CLKIN cycles ensures that the PLLs have
locked, but this does not include the oscillators’ start-up
time. During this power-up sequence, the RESET signals
should be held low. On any subsequent resets, the RESET
signals must meet the minimum pulse width specification,
0x2000 -
0x3FFF
0x2000 -
ACCESSIBLE WHEN
PM O VLAY = 4
0x3FFF
0x2000 -
0x3FFF
ACCESSIBLE WHEN
PM O VLAY = 5
ACCESSIBLE
WHEN
0x2000 -
0x3FFF
tRSP
.
PM O VLAY = 6
The RESET input contains some hysteresis; however, if you
use an RC circuit to generate your RESET signals, the use
of an external Schmidt triggers are recommended.
INTERNAL
MEMORY
ACCESSIBLE
WHEN
PM O VLAY = 7
The RESET for each individual modem processor sets the
internal stack pointers to the empty stack condition, masks
all interrupts and clears the MSTAT register. When a
RESET is released, if there is no pending bus request and
the modem processor is configured for booting, the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000
once boot loading completes.
PROGRAM MEMORY
ADDRESS
MODE B=0
0x3FFF
8K INTERNAL
PMOVLAY =
0, 4, 5, 6, 7
0x2000
0x1FFF
MEMORY ARCHITECTURE
8K
The ADSP-21mod980N provides a variety of memory and
peripheral interface options for Modem Processor 1. The
key functional groups are Program Memory, Data Memory,
Byte Memory, and I/O. Refer to the following figures and
tables for PM and DM memory allocations in the
ADSP-21mod980N.
INTERNAL
0x0000
Figure 4. Program Memory Map
Table 4. PMOVLAY bits
The ADSP-21mod980N modem pool operates in one
memory mode: Slave Mode. The following figures and
tables describe the memory of the ADSP-21mod980N:
PMOVLAY Memory A13
A[12:0]
0, 4, 5, 6, 7 Internal
Not
Applicable
Not Applicable
•
•
Figure on page 10 shows Program Memory
Table on page 10 shows the generation of address bits
based on the PMOVLAY values
10
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
DATA MEMORY
Table 5. DMOVLAY bits
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 - 0x3FFF
DMOVLAY
Memory A13
A[12:0]
0, 4, 5, 6, 7, 8 Internal
Not
Not
0x0000 - 0x1FFF
Applicable
Applicable
0x0000 - 0x1FFF
MEMORY MAPPED REGISTERS (NEW TO THE
ADSP-21MOD980N)
ACCESSIBLE WHEN
DM OVLAY = 0
0x0000 - 0x1FFF
The ADSP-21mod980N has three memory mapped regis-
ters that differ from other ADSP-21xx Family DSPs. See
“Waitstate Control Register” on page 11. See
“Programmable Flag & Composite Select Control Regis-
ter” on page 12. See “System Control Register” on
page 12. The slight modifications to these registers provide
the ADSP-21mod980N’s waitstate and BMS control
features.
ACCESSIBLE WHEN
DM OVLAY = 4
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 5
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 6
0x0000 - 0x1FFF
INTERNAL
MEMORY
ACCESSIBLE WHEN
DM OVLAY = 7
ACCESSIBLE WHEN
DM OVLAY = 8
DATA MEMORY
ADDR
0x3FFF
32 MEMORY
MAPPED
REGISTERS
0x3FE0
0x3FDF
INTERNAL
8160 WORDS
0x2000
0x1FFF
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
Figure 5. Data Memory Map
.
15 14 13 12 11 10
9
1
8
1
7
6
1
5
4
3
1
2
1
1
1
0
1
DM(0x3FFE)
1
1
1
1
1
1
1
1
1
DWAIT
IOWAIT3
IOWAIT 2
IOW AIT1
IOWAIT0
Wait State Mode Select
0 = Normal mode (PWAIT, DWAIT, IOWAIT0-3 = N wait states, ranging from 0 to 7)
1 = 2N+1 mode (PWAIT, DWAIT, IOWAIT0-3 = 2N+1 wait states, ranging from 0 to 15)
Figure 6. Waitstate Control Register
REV. PrB 6/2001
11
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
15 14 13 12 11 10
9
8
1
7
6
0
5
4
3
0
2
0
1
0
0
0
DM(0x3FE6)
0
1
1
1
1
1
1
0
0
0
BMWAIT
CMSSEL
0 = Disable CMS
1 = Enable CMS
PFTYPE
0 = Input
1 = Output
(where bit: 11-IOM, 10-BM, 9-DM, 8-PM)
Figure 7. Programmable Flag1 & Composite Select Control Register
1
Since they are multiplexed within the ADSP-21mod980N, PF[2:0] should be configured as an output for only one processor at a time. Bit [3] of DM
(0x3FE6) must also be 0 to ensure that PF[3] is never an output.
15 14 13 12 11 10
9
0
8
0
7
6
0
5
4
3
0
2
1
1
1
0
1
DM(0x3FFF)
0
0
0
0
0
1
0
0
0
SPORT0 Enable
0 = Disable
1 = Enable
Reserved Set
To 0
RESERVED
SET TO 0
PWAIT
Program Memory
Wait States
SPORT1 Enable
0 = Disable
1 = Enable
SPORT1 Configure
0 = FI, FO, IRQ0, IRQ1, SCLK
1= SPORT1
Disable BMS
0 = Enable BMS
1 = Disable BMS, except when
memory strobes are three-stated
Figure 8. System Control Register
Table 6. ADSP-21mod980N Mode of Operation
MODE C MODE B MODE A Booting Method
IDMA feature is used to load internal memory as desired. Program execution is held off until internal
1
0
1
1
program memory location 0x0000 is written to. Chip is configured in Slave Mode. IACK requires
2
external pulldown.
1
2
Considered standard operating settings. These configurations simplify your design and improve memory management.
IDMA timing details and the correct usage of IACK are described in the ADSP-2100 Family User’s Manual.
SLAVE MODE
INTERNAL MEMORY DMA PORT (IDMA PORT)
This section describes the Slave Mode memory configura-
tion of the Modem Processors.
The IDMA Port provides an efficient way for a host system
and the ADSP-21mod980N to communicate. The port is
used to access the on-chip program memory and data mem-
ory of each modem processor with only one processor cycle
per word overhead. The IDMA port cannot be used, how-
12
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ever, to write to the processor’s memory-mapped control
registers. A typical IDMA transfer process is described as
follows:
specifies an on-chip memory location, the destination type
specifies whether it is a DM or PM access. The falling edge
of the address latch signal latches this value into the
IDMAA register.
1. Host starts IDMA transfer
Once the address is stored, data can then be either read
from, or written to, the ADSP-21mod980N’s on-chip
memory. Asserting the select line (IS) and the appropriate
read or write line (IRD and IWR respectively) signals the
ADSP-21mod980N that a particular transaction is
required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one
additional processor cycle.
2. Host uses IS and IAL control lines to latch either the
DMA starting address (IDMAA) or the PM/DM
OVLAY selection into the processor’s IDMA control
registers.
If IAD [15] = 1, the value of IAD [7:0] represents the
IDMA overlay: IAD[14:8] must be set to 0.
If IAD [15] = 0, the value of IAD [13:0] represents the
starting address of internal memory to be accessed and
IAD [14] reflects PM or DM for access.
Once an access has occurred, the latched address is auto-
matically incremented, and another access can occur.
1. Host uses IS and IRD (or IWR) to read (or write) pro-
cessor internal memory (PM or DM).
Through the IDMAA register, the processor can also spec-
ify the starting address and data format for DMA operation.
Asserting the IDMA port select (IS) and address latch
enable (IAL) directs the ADSP-21mod980N to write the
address onto the IAD [14:0] bus into the IDMA Control
Register. If IAD [15] is set to 0, IDMA latches the address.
If IAD [15] is set to 1, IDMA latches OVLAY memory. The
IDMAA register is memory mapped at address DM
(0x3FE0). Note that the latched address (IDMAA) or over-
lay register cannot be read back by the host. The IDMA
OVERLAY register is memory mapped at address
DM(0x3FE7). See Figure on page 13 for more informa-
tion on IDMA memory mapping. When bit 14 in 0x3FE7
is set to 1, then timing in Figure on page 35 applies for
short reads. When bit 14 in 0x3FE7 is set to zero short
reads use the timing shown in Figure on page 34.
2. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data
bus and supports 24-bit program memory. The IDMA port
is completely asynchronous and can be written to, while the
ADSP-21mod980N is operating at full speed.
The processor memory address is latched and then auto-
matically incremented after each IDMA transaction. An
external device can therefore access a block of sequentially
addressed memory by specifying only the starting address of
the block. This increases throughput as the address does
not have to be sent for each memory access.
IDMA Port access occurs in two phases. The first is the
IDMA Address Latch cycle. When the acknowledge is
asserted, a 14-bit address and 1-bit destination type can be
driven onto the bus by an external device. The address
IDMA OVERLAY
15 14 13 12 11
10
0
9
8
7
6
5
0
4
0
3
2
1
0
DM(0x3FE7)
0
0
0
0
0
0
0
0
0
0
0
0
0
RESERVED
SET TO 0
ID PMOVLAY
ID DMOVLAY
Short Read Only
RESERVED
ALW AYS SET
TO 0
Enable
1 = Enable
0 = Disable
IDMA CONTROL (U=UNDEFINED AT RESET)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM(0x3FE0)
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
IDMAA
ADDRESS
RESERVED
ALW AYS SET
TO 0
IDMAD
Destination memory type:
0=PM
1=DM
Figure 9. IDMA Control/OVLAY Registers
REV. PrB 6/2001
13
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ALW AYS
ALW AYS
ACCESSIBLE
AT ADDRESS
0x0000 - 0x1FFF
ACCESSIBLE
AT ADDRESS
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ACCESSIBLE W HEN
PM OVLAY = 0
ACCESSIBLE W HEN
DM OVLAY = 0
ACCESSIBLE W HEN
PM OVLAY = 4
ACCESSIBLE W HEN
DM OVLAY = 4
ACCESSIBLE W HEN
PM OVLAY = 5
ACCESSIBLE W HEN
DM OVLAY = 5
ACCESSIBLE W HEN
PM OVLAY = 6
ACCESSIBLE W HEN
DM OVLAY = 6
0x0000 - 0x1FFF
ACCESSIBLE W HEN
PM OVLAY = 7
ACCESSIBLE W HEN
DM OVLAY = 7
ACCESSIBLE W HEN
DM OVLAY = 8
Figure 10. Direct Memory Access - PM and DM Memory Maps
14
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA PORT BOOTING
The ADSP-21mod980N boots programs through its Inter-
nal DMA port.When Mode C = 1, Mode B = 0, and Mode
A = 1, the ADSP-21mod980N boots from the IDMA port.
IDMA feature can load as much on-chip memory as
desired. Program execution is held off until on-chip pro-
gram memory location 0 is written to.
FLAG I/O PINS
Each modem processor has eight general purpose program-
mable input/output flag pins. They are controlled by two
memory mapped registers. The PFTYPE register deter-
mines the direction, 1 = output and 0 = input. The
PFDATA register is used to read and write the values on the
pins. Data being read from a pin configured as an input is
synchronized to the ADSP-21mod980N’s clock. Bits that
are programmed as outputs will read the value being out-
put. The PF pins default to input during RESET.
Note: Pins PF0, PF1, and PF2 are also used for device con-
figuration during RESET. Since they are multiplexed
within the ADSP-21mod980N, PF[2:0] should be config-
ured as an output for only one processor at a time.
REV. PrB 6/2001
15
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The EZ-ICE can emulate only one modem processor at a
time. You must include hardware to select which processor
in the ADSP-21mod980N you want to emulate. Figure on
page 16 is a functional representation of the modem proces-
sor selection hardware. You can use one ICE-Port
connector with two ADSP-21mod980N processors without
using additional buffers.
The ADSP-21mod980N has on-chip emulation support
and an ICE-Port, a special set of pins that interface to the
EZ-ICE. These features allow in-circuit emulation without
replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target
systems must have a 14-pin connector to accept the
EZ-ICE’s in-circuit probe, a 14-pin plug.
ADSP-21M OD980N
ELOUT
EBR
EBG
EINT
ELIN
ECLK
EMS
ERESET
BG0
GND
EBG
BG
BR0
1
2
RESET0
EE0
BR
3
4
BG1
EBR
ENT
BR1
RESET1
EE1
5
6
KEY
ELIN
ECLK
EMS
ERESET
BG2
7
8
BR2
ELOUT
EE
RESET2
EE2
9
10
12
14
BG3
11
13
BR3
RESET3
EE3
RESET
BG4
BR4
RESET4
EE4
BG5
BR5
RESET5
EE5
BG6
BR6
RESET6
EE6
BG7
BR7
RESET7
EE7
Figure 11. Selecting a Modem Processor in the ADSP-21mod980N
Issuing the “chip reset” command during emulation causes
the modem processor to perform a full chip reset, including
a reset of its memory mode. Therefore, it is vital that the
mode pins are set correctly PRIOR to issuing a chip reset
command from the emulator user interface. As the mode
pins share functionality with PF[2:0] on the
16
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ADSP-21mod980N, it may be necessary to reset the target
hardware separately to insure the proper mode selection
state on emulator chip reset. See the ADSP-2100 Family
EZ-Tools data sheet for complete information on ICE
products.
Pin spacing should be 0.1
؋
0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to
accept the EZ-ICE probe plug.
1
3
5
7
9
2
The ICE-Port interface consists of the following
ADSP-21mod980N pins:
BG
GND
4
EBG
BR
EBR
6
8
EINT
EE
EBR
EINT
EBG
KEY (NO PIN)
∞
ELIN
ECLK
ERESET
ELIN
EMS
10
12
14
ELOUT
ECLK
11
13
EMS
EE
RESET
ERESET
ELOUT
These ADSP-21mod980N pins must be connected only to
the EZ-ICE connector in the target system. These pins have
no function except during emulation, and do not require
pull-up or pull-down resistors. The traces for these signals
between the ADSP-21mod980N and the connector must
be kept as short as possible—no longer than 3 inches.
TOP VIEW
Figure 12. Target Board Connector for EZ-ICE
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
The following pins are also used by the EZ-ICE:
TARGET MEMOR Y INTERF ACE
•
•
•
•
BR
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
BG
RESET
GND
TARGET SYSTEM INTERFACE SIGNALS
When the EZ-ICE board is installed, the performance on
some system signals change. Design your system to be com-
patible with the following system interface signal changes
introduced by the EZ-ICE board:
The EZ-ICE uses the EE (emulator enable) signal to take
control of the ADSP-21mod980N in the target system.
This causes the processor to use its ERESET, EBR, and
EBG pins instead of the RESET, BR, and BG pins. The BG
output is three-stated. These signals do not need to be
jumper-isolated in your system.
•
EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the RESET signal.
The EZ-ICE connects to your target system via a ribbon
cable and a 14-pin female plug. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target
board.
•
EZ-ICE emulation introduces an 8 ns propagation
delay between your target circuitry and the processor
on the BR signal.
•
•
•
EZ-ICE emulation ignores RESET and BR when
single-stepping.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The EZ-ICE connector (a standard pin strip header) is
shown in Figure on page 17. You must add this connector
to your target board design if you intend to use the EZ-ICE.
Be sure to allow enough room in your system to fit the
EZ-ICE probe onto the 14-pin connector.
EZ-ICE emulation ignores RESET and BR when in
Emulator Space (processor halted).
EZ-ICE emulation ignores the state of target BR in cer-
tain modes. As a result, the target system may take
control of the processor’s external memory bus only if
bus grant (BG) is asserted by the EZ-ICE board’s
processor.
The 14-pin, 2-row pin strip header is keyed at the Pin 7
location—you must remove Pin 7 from the header. The pins
must be 0.025 inch square and at least 0.20 inch in length.
REV. PrB 6/2001
17
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Description
Min
Max
Unit
VDDEXT
VDDINT
VINPUT
TAMB
External supply
Internal supply
Input Voltage
2.98
1.81
3.63
V
2.0
V
VIL= –0.3
0
VIH= +3.6
+70
V
Ambient temperature
°C
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Unit
VIH, Hi-Level Input Voltage1, 2
VIH, Hi-Level CLKIN Voltage
VIL, Lo-Level Input Voltage1, 3
@ VDDINT = max
@ VDDINT = max
@ VDDINT = min
@ VDDEXT = min
1.5
2.0
V
V
V
V
0.7
V
OH, Hi-Level Output Voltage1, 4, 5
2.4
IOH = –0.5 mA
@ VDDEXT = min
VDDEXT
-0.3
V
IOH = –100 µA6
VOL, Lo-Level Output Voltage1, 4, 5
IIH, Hi-Level Input Leakage Current3
IIL, Lo-Level Input Leakage Current3
IOZH, Three-State Leakage Current7
@ VDDEXT = min
0.4
10
10
10
10
V
IOL = 2 mA
@ VDDINT = max
VIN = 3.6V
A
A
A
A
@ VDDINT = max
VIN = 0 V
@ VDDEXT = max
V
IN = 3.6V8
I
OZL, Three-State Leakage Current7
@ VDDEXT = max
VIN = 0 V8
18
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameter
Test Conditions
Min
Typ
Max
Unit
IDD, Supply Current (Idle)
@ VDDINT = 1.9V
tCK = 12.5 ns
50
mA
IDD, Supply Current (Dynamic)
@ VDDINT = 1.9V
t
TAMB = +25°C
200
800
mA
CK = 12.5 ns9
IDD, Supply Current (Powerdown)10
Lowest power mode
µA
pF
CI, Input Pin Capacitance
RESET, BR, IS, TFS0, PF[7:4]
@ VIN = 2.5 V, fIN = 1.0 MHz,
TAMB = +25°C
8
CI, Input Pin Capacitance
IWR, IRD, IAL, DR0, RFS0, SCLK0, IAD [15:0]
@ VIN = 2.5 V, fIN = 1.0 MHz,
TAMB = +25°C
32
64
8
pF
pF
pF
pF
pF
CI, Input Pin Capacitance
TFS1, PF[2:0], CLKIN, DR1, RFS1, SCLK1
@ VIN = 2.5 V, fIN = 1.0 MHz,
TAMB = +25°C
CO, Output Pin Capacitance1, 6, 7, 10, 11
BG, CLKOUT, TFS0, PF[7:4], DT1
@ VIN = 2.5 V, fIN = 1.0 MHz,
TAMB= +25°C
CO, Output Pin Capacitance1, 6, 7, 9, 10
IAD [15:0], DT0, IACK, RFS0, SCLK0
@ VIN = 2.5 V, fIN = 1.0 MHz,
TAMB= +25°C
32
64
CO, Output Pin Capacitance1, 6, 7, 9, 10
@ VIN = 2.5 V, fIN = 1.0 MHz,
SCLK1, TFS1, PF[2:0], DATA [23:8], A0, RFS1
TAMB= +25°C
1
Bidirectional pins: RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD [15:0], PF[2:0], PF[7:4].
Input only pins: RESET, BR, DR0, DR1, IS, IAL,IRD, IWR.
Input only pins: CLKIN, RESET, BR, DR0, DR1.
2
3
4
5
Output pins: BG, A0, DT0, DT1, CLKOUT, IACK.
Although specified for TTL outputs, all ADSP-21mod980N outputs are CMOS-compatible and will drive to VDDEXT and GND, assuming no DC
loads.
6
Guaranteed but not tested.
7
Three-statable pins: DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, IAD[15:0].
0 Volts on BR.
8
9
Vin = 0V and 3V. For typical supply current figures refer to “Power Dissipation” section.
See the ADSP-2100 Family User’s Manual for details.
Output pin capacitance is the capacitive load for any three-stated output pin
10
11
REV. PrB 6/2001
19
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ABSOLUTE MAXIMUM RATINGS
Parameter
Description
Min.
Max
Unit
VDDINT
VDDEXT
Internal Supply Voltage
External Supply Voltage
Input Voltage1
–0.3
+2.5
V
–0.3
+4.6
V
–0.5
+4.6
V
Output Voltage Swing2
Storage Temperature Range
–0.5
VDDEXT + 0.5
+150 °C
V
–65 °C
°C
1
Applies to bidirectional pins (D0:D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1:A13, PF0:PF7) and input only pins (CLKIN, RESET, BR,
DR0, DR1).
2
Applies to output pins (BG, PWDACK, A0, DT0, DT1, CLKOUT).
ESD SENSITIVITY
CAUTION: ESD (electrostatic discharge) sensitive device. Electrostatic charges as high
as 4000V readily accumulate on the human body and test equipment and can discharge
without detection. Although the device features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
20
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Assumptions:
POWER DISSIPATION
Assumptions:
•
•
•
•
External data memory is accessed every fourth cycle
with 50% of the address pins switching.
To determine total power dissipation in a specific applica-
tion, the following equation should be applied for each
output:
C
؋
VDD2 ؋
f External data memory writes occur every fourth cycle
with 50% of the data pins switching.
Each address and data pin has a 64 pF total load at the
pin.
C = load capacitance
f = output switching frequency
Example:
Application operates at VDDEXT = 3.3 V and tCK = 30 ns.
Total Power Dissipation = PINT + (C
؋
VDDEXT2 ؋
f) P
INT= internal power dissipation from Figure 15
In an application where an external host is accessing inter-
nal memory and no other outputs are active, power
dissipation is calculated as follows:
(C
؋
VDDEXT2 ؋
f) is calculated for each output, as in the example in Table 7.
Table 7. Example Power Dissipation Calculation
Parameters
# of Pins
× C (pF)
× VDDEXT2 (V)
× f (MHz)
PD (mW)
Address
8
9
64
64
3.32
3.32
18.8
18.8
104.8
117.9
222.7
Data Output, WR
Total power dissipation for this example is:
PD = PINT + 222.7 mW
REV. PrB 6/2001
21
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
ENVIRONMENTAL CONDITIONS
MO D980N Core POW ER , IDLE
120
110
100
90
Table 8. Thermal Resistance
108m W
96m W
84m W
Rating
Symbol PBGA
Description1
VD D
VD D
=
=
2.0v
1.9v
Thermal Resistance
(Case-to-
Ambient)
θCA
θJA
θJC
23ºC
/W
84m W
76m W
80
VD D
=
1.8v
70
68m W
60
Thermal Resistance
(Junction-to-
Ambient)
28.2ºC
/W
50
55
60
65
70
75
80
85
1/tC K
-
M Hz
Thermal Resistance
(Junction-to-
Case)
5.2ºC
/W
M O D980N Core POW ER, DYNAM IC
475
1
Where the Ambient Temperature Rating (TAMB) is:
440m W
425
375
325
275
225
175
TAMB = TCASE – (PD × θCA
)
TCASE = Case Temperature in °C
375m W
336m W
VD D
=
2.0V
PD = Power Dissipation in W
336m W
V D D
=
=
1.9V
1.8V
V D D
287m W
256m W
55
60
65
70
75
80
85
1/tC K
-
M Hz
Figure 13. Power vs. Frequency
22
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Output Disable Time
TEST CONDITIONS
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 16. The time is the interval from
when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage.
INPUT
1.5V
2.0V
1.5V
OUTPUT
The decay time, tDECAY, is dependent on the capacitive load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
0.8V
Figure 14. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
CL × 0.5V
-------------------------
=
tDECAY
iL
I
OL
from which
tDIS = tMEASURED – tDECAY
TO
OUTPUT
PIN
1.5V
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
50pF
Output Enable Time
I
OH
Output pins are considered to be enabled when they have
made a transition from a high-impedance state to when they
start driving. The output enable time (tENA) is the interval
from when a reference signal reaches a high or low voltage
level to when the output has reached a specified high or low
trip point, as shown in Figure 16. If multiple pins (such as
the data bus) are enabled, the measurement value is that of
the first pin to start driving.
Figure 15. Equivalent Loading for AC Measurements
(Including All Fixtures)
REFERENCE
SIGNAL
tMEASURED
tDIS
tENA
V
V
OH
OH
(MEASURED)
(MEASURED)
V
V
(MEASURED) - 0.5V
(MEASURED) +0.5V
2.0V
1.0V
OH
OL
OUTPUT
V
V
OL
OL
tDECAY
(MEASURED)
(MEASURED)
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
Figure 16. Output Enable/Disable
REV. PrB 6/2001
23
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
TIMING SPECIFICATIONS
30
25
؇
T = 85 C
V
= 0V TO 2.0V
DD
This section contains timing information for the DSP’s
external signals.
20
15
10
5
General Notes
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of oth-
ers. While addition or subtraction would yield meaningful
results for an individual device, the values given in this data
sheet reflect statistical variations and worst cases. Conse-
quently, you cannot meaningfully add up parameters to
derive longer times.
0
50
0
100
150
- pF
200
250
300
C
L
Timing Notes
Figure 17. Typical Output Rise Time vs.Load Capacitance
(at Maximum Ambient Operating Temperature)
Switching characteristics specify how the processor changes
its signals. You have no control over this timing—circuitry
external to the processor must be designed for compatibility
with these signal characteristics. Switching characteristics
tell you what the processor will do in a given circumstance.
You can also use switching characteristics to ensure that any
timing requirement of a device connected to the processor
(such as memory) is satisfied.
18
16
14
12
10
8
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for
a read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
6
4
2
NOMINAL
-2
-4
-6
Frequency Dependency For Timing Specifications
tCK is defined as 0.5 tCKI. The ADSP-21mod980N uses an
input clock with a frequency equal to half the instruction
rate. For example, a 40 MHz input clock (which is equiva-
lent to 25 ns) yields a 12.5 ns processor cycle (equivalent to
80 MHz). tCK values within the range of 0.5 tCKI period
should be substituted for all relevant timing parameters to
obtain the specification value.
0
50
100
150
200
250
C
- pF
L
Figure 18. Typical Output Valid Delay or Hold vs.Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
Example: tCKH = 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns = 4.25
ns
Output Drive Currents
Figure 14 shows typical I-V characteristics for the output
drivers on the ADSP-21mod980N. The curves represent
the current drive capability of the output drivers as a func-
tion of output voltage
Capacitive Loading
Figure 16 and Figure 17 show the capacitive loading char-
acteristics of the ADSP-21mod980N.
24
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Clock and Reset Signals
Table 9. Clock and Reset Signals
Parameter Description
Min.
Max
Unit
Clock signals (Timing Requirements):
tCKI
CLKIN Period
25.0
8
40.0
ns
ns
ns
ns
ns
tCKIL
CLKIN Width Low
CLKIN Width High
CLKIN rise time1
CLKIN fall time
tCKIH
tCKRISE
tCKFALL
8
4
4
Clock signals (Switching Characteristics)2:
tCKL
CLKOUT Width Low
0.5tCK - 3
0.5tCK - 3
0
ns
ns
ns
tCKH
tCKOH
CLKOUT Width High
CLKIN High to CLKOUT High
8
Control Signals (Timing Requirements):
3
tRSP
tMS
tMH
RESET Width Low
5tCK
ns
ns
ns
Mode Setup Before RESET High
Mode Hold After RESET High
4
5
1
2
3
t
and t
are specified between the 10% and 90% points on the signal edge.
CKFALL
CKRISE
If it is not needed by the application, CLKOUT should be disabled to reduce noise (DM(0x3FF3) bit 14).
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including
crystal oscillator start-up time).
REV. PrB 6/2001
25
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(2:0)*
RESET
tMH
tMS
*PF2 is Mode C, PF1 is Mode B, PF0 is Mode A
Figure 19. Clock and Reset Signals
26
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Interrupts and Flags
Table 10. Interrupts and Flags
Parameter Description
Timing Requirements:
Min.
Max
Unit
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25tCK + 10
0.25tCK
ns
ns
tIFH
Switching Characteristics:
tFOH
Flag Output Hold after CLKOUT Low5
tFOD
Flag Output Delay from CLKOUT Low5
0.5tCK - 5
ns
0.5tCK + 4 ns
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be
recognized on the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual for
further information on interrupt servicing.)
2
3
4
5
Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
PFx = PF0, PF1, PF2, PF4, PF5, PF6, PF7.
4
Flag Outputs = PFx, Flag_out .
CLKOUT
tIFH
IRQx
FI
PFx
tIFS
Figure 20. Interrupts and Flags
REV. PrB 6/2001
27
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Serial Ports
Table 11. Serial Ports
Parameter
Description
Min.
Max
Unit
Timing Requirements:
tSCK
tSCS
tSCH
tSCP
SCLK Period
30
4
ns
ns
ns
ns
DR/TFS/RFS Setup before SCLK Low
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
7
12
Switching Characteristics:
tCC
CLKOUT High to SCLKOUT
0.25tCK
0
0.25tCK + 6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCDE
tSCDV
tRH
SCLK High to DT Enable
SCLK High to DT Valid
12
12
TFS/RFSOUT Hold after SCLK High
TFS/RFSOUT Delay from SCLK High
DT Hold after SCLK High
0
tRD
tSCDH
tTDE
tTDV
tSCDD
tRDV
0
0
TFS (Alt) to DT Enable
TFS (Alt) to DT Valid
12
12
12
SCLK High to DT Disable
RFS (Multichannel, Frame Delay Zero to DT Valid
28
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
CLKOUT
SCLK
tCC
tCC
tSCK
tSCP
tSCP
tSCS
tSCH
DR
TFS
RFS
IN
IN
tRD
tRH
RFS
TFS
OUT
OUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
OUT
ALTERNATE
FR AME MO DE
tRDV
RFS
OUT
MUL TIC HA NNE L
M O DE,
FRAM E DE LAY
(M FD
0
tTDE
=
0)
tTDV
TFS
IN
ALTERNATE
FR AME MO DE
tRDV
RFS
IN
M UL TIC HA NNE L
M O DE,
FRAM E DE LAY
(M FD
0
=
0)
Figure 21. Serial Ports
REV. PrB 6/2001
29
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Address Latch
Table 12. IDMA Address Latch
Parameter
Description
Min.
Max
Unit
Timing Requirements:
tIALP
tIASU
tIAH
Duration of Address Latch1, 2, 3
10
5
ns
ns
ns
ns
ns
ns
IAD[15:0] Address Setup before Address Latch End2, 3
IAD[15:0] Address Hold after Address Latch End2, 3
IACK Low before Start of Address Latch2, 3, 4
3
tIKA
0
tIALS
tIALD
Start of Write or Read after Address Latch End2, 3, 4
Address Latch Start after Address Latch End1, 2, 3
3
2
1
2
3
4
Start of Address Latch = IS Low and IAL High.
End of Address Latch = IS High or IAL Low.
For IDMA, please refer to the ADSP-2100 Family User’s Manual.
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD 15-0
tIASU
tIASU
tIAH
tIAH
tIALS
IRD
OR
IWR
Figure 22. IDMA Address Latch
30
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Write, Short Write Cycle
Table 13. IDMA Write, Short Write Cycle
Parameter Description
Timing Requirements:
Min.
Max
Unit
tIKW
tIWP
tIDSU
tIDH
IACK Low before Start of Write1, 2
0
ns
ns
ns
ns
Duration of Write1, 2, 3
10
3
IAD[15:0] Data Setup before End of Write2, 3, 4, 5
IAD[15:0] Data Hold after End of Write2, 3, 4, 5
2
Switching Characteristics:
tIKHW
Start of Write to IACK High
10
ns
1
2
3
4
5
Start of Write = IS Low and IWR Low.
For IDMA, please refer to the ADSP-2100 Family User’s Manual.
End of Write = IS High or IWR High.
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
tIKW
IACK
tIKHW
IS
tIW P
IW R
tIDH
tIDSU
IAD 15-0
DATA
Figure 23. IDMA Write, Short Write Cycle
REV. PrB 6/2001
31
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Write, Long Write Cycle
Table 14. IDMA Write, Long Write Cycle
Parameter
Description
Min.
Max
Unit
Timing Requirements
tIKW
tIKSU
tIKH
IACK Low before Start of Write1
0
ns
ns
ns
IAD[15:0] Data Setup before End of Write2, 3, 4
IAD[15:0] Data Hold after End of Write2, 3, 4
0.5tCK + 5
0
Switching Characteristics:
tIKLW
Start of Write to IACK Low4
tIKHW Start of Write to IACK High
1.5tCK
ns
ns
10
1
2
3
4
Start of Write = IS Low and IWR Low.
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH
.
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH
.
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual.
tIKW
IACK
tIKHW
tIKLW
IS
IW R
tIKSU
tIKH
DATA
IAD 15-0
Figure 24. IDMA Write, Long Write Cycle
32
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Read, Long Read Cycle
Table 15. IDMA Read, Long Read Cycle
Parameter Description
Min.
Max
Unit
Timing Requirements:
tIKR
IACK Low before Start of Read1, 2
tIRK
End of Read after IACK Low2, 3
Switching Characteristics:
0
2
ns
ns
tIKHR
tIKDS
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read1, 2
10
ns
ns
ns
ns
ns
ns
ns
IAD[15:0 Data Setup before IACK Low2
0.5tCK - 2
0
IAD[15:0] Data Hold after End of Read2, 3
IAD[15:0] Data Disabled after End of Read2, 3
IAD[15:0] Previous Data Enabled after Start of Read2
IAD[15:0] Previous Data Valid after Start of Read2
10
10
0
1
tIRDH
IAD[15:0] Previous Data Hold after Start of Read
(DM/PM1)2, 4
2tCK - 5
tCK - 5
2
tIRDH
IAD[15:0] Previous Data Hold after Start of Read (PM2)2, 5
ns
1
2
3
4
5
Start of Read = IS Low and IRD Low.
For IDMA, please refer to the ADSP-2100 Family User’s Manual.
End of Read = IS High or IRD High.
DM read or first half of PM read.
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDS
tIKDH
tIRDE
PREVIOUS
DATA
READ
DATA
IAD 15-0
tIRDV
tIKDD
tIRDH
Figure 25. IDMA Read, Long Read Cycle
REV. PrB 6/2001
33
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Read, Short Read Cycle
Table 16. IDMA Read, Short Read Cycle1
Parameter
Description
Min.
Max
Unit
Timing Requirements:
tIKR
IACK Low before Start of Read2
tIRP Duration of Read
Switching Characteristics:
0
ns
ns
10
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read2, 3
10
10
10
ns
ns
ns
ns
ns
ns
IAD[15:0] Data Hold after End of Read3, 4
0
0
IAD[15:0] Data Disabled after End of Read3, 4
IAD[15:0] Previous Data Enabled after Start of Read3
IAD[15:0] Previous Data Valid after Start of Read3
1
tIRDH
IAD[15:0] Previous Data Hold after Start of Read
(DM/PM1)3,5
2tCK - 5
tCK - 5
2
tIRDH
IAD[15:0] Previous Data Hold after Start of Read (PM2)3, 6
ns
1
2
3
4
5
6
Timing applies to ADSP-21mod980N when Short Read Only mode is disabled. See Table on page 35.
Start of Read = IS Low and IRD Low.
For IDMA, please refer to the ADSP-2100 Family User’s Manual.
End of Read = IS High or IRD High.
DM read or first half of PM read.
Second half of PM read.
IACK
t
IKHR
t
IKR
IS
IR D
t
IRDE
Previous Data
New Read Data
IAD[15:0]
t
IRDV
Figure 26. IDMA Read, Short Read Cycle
34
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
IDMA Read - Short Read Cycle in Short Read Only Mode
Table 17. IDMA Read - Short Read Cycle in Short Read Only Mode1
Parameter
Description
Min.
Max
Unit
Timing Requirements:
tIKR
IACK Low before Start of Read2, 4
tIRP
Duration of Read after IACK Low3, 4
Switching Characteristics:
0
ns
ns
10
tIKHR
tIKDH
tIKDD
tIRDE
tIRDV
IACK High after Start of Read2, 4
10
10
10
ns
ns
ns
ns
ns
IAD[15:0] Previous Data Hold after End of Read3, 4
IAD[15:0] Previous Data Disabled after End of Read3, 4
IAD[15:0] Previous Data Enabled after Start of Read4
IAD[15:0] Previous Data Valid after Start of Read4
0
0
1
Short Read Only is enabled by setting Bit 14 of the IDMA Overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing
to the register or by an external host writing to the register. Disabled by default.
2
3
4
Start of Read = IS Low and IRD Low. Previous data remains until end of read.
End of Read = IS High or IRD High.
For IDMA, please refer to the ADSP-2100 Family User’s Manual.
IACK
t
IKHR
t
IKR
IS
IR D
t
t
IKDH
IRDE
IAD[15:0]
Previous Data
t
t
IKDD
RDV
Figure 27. IDMA Read, Short Read Only Mode
REV. PrB 6/2001
35
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Table 18. Pinout by
Signal Name (Continued)
Table 18. Pinout by
Signal Name (Continued)
Table 18. Pinout by
Signal Name (Continued)
352-BALL PBGA
PACKAGE PINOUT
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
CLKOUT_3
CLKOUT_4
CLKOUT_5
CLKOUT_6
CLKOUT_7
CLKOUT_8
D08
C20
AC1
L24
P4
DT1_4
DT1_5
DT1_6
DT1_7
DT1_8
EBG
AF2
T25
U3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H2
A physical layout of all sig-
nals is shown in the
H3
following tables. Figure on
page 40 shows the signals
on the left side of the device
when viewed from the top.
Figure on page 41 shows
the signals on the right side
of the device when viewed
from the top. The pin num-
ber for each signal is listed
in Table on page 36.
H4
AD13
AE20
F26
G26
J23
H23
H24
H25
H26
N1
AD10
AF15
F23
E25
E24
D26
D25
D24
C26
C25
B26
B24
A25
B23
C23
A24
A23
A22
E1
EBR
D09
ECLK
EE_1
Table 18. Pinout by
Signal Name
D10
M4
N2
D11
EE_2
C13
G23
AE9
T26
Y2
N3
Signal Name
Pin
D12
EE_3
N4
A0
A2
D13
EE_4
R23
R24
T3
BG_1
BG_2
BG_3
BG_4
BG_5
BG_6
BG_7
BG_8
BR_1
F3
D14
EE_5
D14
F25
AC5
R25
R4
D15
EE_6
D16
EE_7
AC13
AE22
J26
T24
U1
D17
EE_8
D18
EINT
ELIN
ELOUT
EMS
U2
D19
J25
U23
U24
U25
U26
W1
AD15
AD25
G4
D20
J24
D21
E23
E26
D19
D20
D23
F1
D22
ERESET
GND
GND
GND
GND
GND
GND
GND
GND
GND
BR_2
B13
G25
AC9
N24
U4
D23
BR_3
DR0A
DR0B
DR1
W2
BR_4
AF22
AE7
P2
W3
BR_5
W4
BR_6
DT0A
DT0B
DT1_1
DT1_2
DT1_3
F2
AF1
AF4
AF8
AF10
AF12
BR_7
AE15
AE26
E3
AF20
P3
F4
BR_8
G2
CLKIN
CLKOUT_1
CLKOUT_2
A12
D21
G3
G1
H1
A10
36
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Table 18. Pinout by
Table 18. Pinout by
Table 18. Pinout by
Table 18. Pinout by
Signal Name (Continued)
Signal Name (Continued)
Signal Name (Continued)
Signal Name (Continued)
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF16
AF17
AF21
AF23
AF26
B2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AD4
AD5
AD7
AD8
AD11
AD12
AD16
AD17
AD21
AD22
AD23
AD24
AE1
GND
A26
AA23
AA24
AA25
AA26
AC4
AC6
AC8
AC10
W23
T4
IAD3_A
IAD3_B
IAD4_A
IAD4_B
IAD5_A
IAD5_B
IAD6_A
IAD6_B
IAD7_A
IAD7_B
IAD8_A
IAD8_B
IAD9_A
IAD9_B
IAL_A
IAL_B
IRD_A
IRD_B
IS_1
D3
GND
W24
C1
GND
GND
W25
D2
GND
GND
W26
V4
B5
GND
B11
B12
B16
B19
B21
B25
C3
GND
M26
Y4
GND
GND
N26
AD6
M23
Y3
IACK_A
IACK_B
IAD0_A
IAD0_B
IAD1_A
IAD1_B
IAD10_A
IAD10_B
IAD11_A
IAD11_B
IAD12_A
IAD12_B
IAD13_A
IAD13_B
IAD14_A
IAD14_B
IAD15_A
IAD15_B
IAD2_A
IAD2_B
AC26
B4
AE2
V26
B1
M24
C8
C5
AE4
C11
C16
C19
C21
C24
D4
AE8
V23
AA2
L26
V3
Y25
C4
AE10
AE12
AE16
AE17
AE21
AE23
AE25
A1
Y24
D6
L23
AA4
M25
E2
IS_2
A14
F24
AA3
V25
AC7
AC16
Y26
D8
IS_3
D5
IS_4
D11
D16
AC12
AC17
AC21
AC23
AD2
AD3
IS_5
AD26
D1
IS_6
A5
IS_7
A11
AC24
E4
IS_8
A16
IWR_A
IWR_B
PF0
A19
AC25
C2
Y23
A6
A20
A21
V24
PF1
B6
REV. PrB 6/2001
37
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Table 18. Pinout by
Table 18. Pinout by
Table 18. Pinout by
Table 18. Pinout by
Signal Name (Continued)
Signal Name (Continued)
Signal Name (Continued)
Signal Name (Continued)
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
Signal Name
Pin
PF2
C6
PF7_6
V2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
C15
C17
D7
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
AE14
AE19
AF14
AF19
B7
PF4_1
PF4_2
PF4_3
PF4_4
PF4_5
PF4_6
PF4_7
PF4_8
PF5_1
PF5_2
PF5_3
PF5_4
PF5_5
PF5_6
PF5_7
PF5-8
PF6_1
PF6_2
PF6_3
PF6_4
PF6_5
PF6_6
PF6_7
PF6_8
PF7_1
PF7_2
PF7_3
PF7_4
PF7_5
M1
PF7_7
AF9
AF18
J1
C10
D18
AC2
L25
T1
PF7_8
RESET_1
RESET_2
RESET_3
RESET_4
RESET_5
RESET_6
RESET_7
RESET_8
RFS0A
D9
D13
C22
AF6
T23
AA1
AC11
AC22
J3
D15
D17
D22
K1
B8
B9
AF7
AD18
M2
B14
K2
B15
K3
B17
D10
C18
AC3
G24
V1
K4
A3
K23
K24
K25
K26
L1
A4
RFS0B
AD20
AE6
P1
AB1
AB2
AB3
AB4
AB23
AB24
AB25
AB26
AE13
AF13
AF24
AF25
B3
RFS1
SCLK0A
SCLK0B
SCLK1
AE11
AE18
M3
AE24
AF5
J2
L2
TFS0_1
TFS0_2
TFS0_3
TFS0_4
TFS0_5
TFS0_6
TFS0_7
TFS0_8
TFS1
L3
B10
B18
AD1
R26
T2
C12
B20
AE5
N23
Y1
L4
A7
A8
A9
A13
A15
A17
AC14
AC15
AC19
AD14
AD19
AD9
AC18
J4
AF11
AC20
AF3
B22
C7
P23
D12
A18
AE3
N25
VDDEXT
VDDEXT
VDDEXT
VDDEXT
P24
P25
C9
P26
C14
38
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Table 18. Pinout by
Signal Name (Continued)
Signal Name
Pin
VDDINT
VDDINT
VDDINT
R1
R2
R3
REV. PrB 6/2001
39
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
Signals by Pin Location—Top View, Left to Right
1
2
3
4
5
6
7
8
9
10
11
12
13
A
GND
A0
VDDINT
VDDINT
GND
VDDINT
IAD0_A
IRD_A
GND
GND
GND
GND
GND
PF0
PF1
PF2
IS_1
VDDEXT VDDEXT VDDEXT CLKOUT_2 GND
DT1_2
GND
VDDEXT
BR_2
B
IAD1_A
IAD4_A
IAD14_A
DR0A
GND
VDDEXT VDDEXT VDDEXT PF6_2
GND
GND
GND
C
IAD2_A
IAD6_A
IAD13_A
GND
VDDEXT IAL_A
VDDEXT IWR_A
VDDEXT PF4_2
VDDEXT PF5_2
TFS0_2 EE_2
D
E
IAD3_A
CLKIN
BG_1
PF7_2
RESET_2
IAD15_A
GND
F
GND
G
H
J
CLKOUT_1 GND
GND
BR_1
GND
GND
GND
GND
RESET_1
VDDEXT
VDDEXT
PF4_1
TFS0_1
RFS0A
PF7_1
K
VDDEXT VDDEXT VDDEXT
VDDEXT VDDEXT VDDEXT
L
M
N
P
PF5_1
GND
PF6_1
GND
EE_1
GND
GND
SCLK0A
VDDINT
PF4_6
DT0A
VDDINT
PF6_6
GND
DT1_1
VDDINT
GND
CLKOUT_6
BG_6
R
T
IACK_A
BR_6
U
V
GND
DT1_6
IAD11_A
GND
PF5_6
PF7_6
GND
IAD6_A
GND
W
Y
GND
TFS0_6
RESET_6
VDDINT
EE_6
IAD9_A
IS_4
IAD7_A
IAD12_A
VDDINT
GND
AA
AB
AC
AD
AE
AF
IAD10_A
VDDINT
VDDINT
PF5_4
GND
CLKOUT_4 PF4_4
BG_4
GND
IS_6
GND
DR1
GND
GND
GND
GND
BR_4
PF6_7
EE_4
GND
RESET_7 GND
EE_7
PF6_4
GND
GND
GND
GND
DT1_4
GND
GND
IAD8_A
RFS1
CLKOUT_7 GND
GND
GND
GND
DT1_7
PF7_4
TFS1
GND
TFS0_4
SCLK1
GND
GND
PF5_7
VDDINT
VDDINT
GND
RESET_4 PF4_7
PF7_7
TFS0_7
1
2
3
4
5
6
7
8
9
10
11
12
13
40
6/2001 REV. PrB
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
OUTLINE DIMENSIONS – 352 PLASTIC BALL GRID ARRAY
Signals by Pin Location—Top View, Left to Right (Continued)
14
15
16
17
18
19
20
21
22
23
24
25
26
IS_2
VDDEXT
GND
GND
GND
GND
VDDEXT PF7_3
VDDEXT PF6_3
VDDEXT PF5_3
VDDEXT PF4_3
GND
GND
GND
GND
GND
GND
GND
D23
D22
D21
D18
GND
D16
A
VDDEXT VDDEXT
VDDEXT VDDEXT
TRS0_3
VDDEXT D19
D17
GND
D15
B
CLKOUT_3 GND
RESET_3
D20
GND
D13
D14
C
BG_2
VDDEXT
GND
DT1_3
VDDEXT GND
D12
D11
D
E
EMS
D08
D10
D09
ERESET
EBG
IS_3
BG_3
BR_3
GND
ELIN
F
EE_3
GND
ECLK
PF5_5
GND
ELOUT
EBR
G
H
J
GND
EINT
VDDEXT VDDEXT
VDDEXT VDDEXT
IAD10_B
K
IAD11_B
IAD8_B
TFS0_5
VDDINT
GND
CLKOUT_5 PF4_5
L
IAD9_B
BR_5
IAD12_B
PF7_5
IAD6_B
IAD7_B
VDDINT
PF6_5
M
N
P
VDDINT
GND
VDDINT
BG_5
R
RESET_5
GND
GND
DT1_5
GND
EE_5
T
GND
GND
U
V
IAD1_B
GND
IAD2_B
IAD3_B
IRD_B
GND
IS_5
IAD0_B
IAD5_B
IS_8
IAD4_B
IAL_B
W
Y
IWR_B
GND
GND
GND
AA
AB
AC
AD
AE
AF
VDDINT
GND
VDDINT
IAD14_B
GND
VDDINT
IAD15_B
BG_8
VDDINT
IACK_B
IAD13_B
BR_8
VDDEXT VDDEXT
VDDEXT BG_7
VDDEXT BR_7
IS_7
GND
GND
GND
GND
PF6_8
PF4_8
PF5_8
PF7_8
VDDEXT TFS0_8
VDDEXT RFS0B
VDDEXT DT1_8
VDDEXT DT0B
GND
GND
GND
GND
RESET_8
GND
GND
GND
GND
EE_8
GND
SCLK0B
VDDINT
GND
VDDEXT CLKOUT_8 GND
DR0B
GND
VDDINT
GND
14
15
16
17
18
19
20
21
22
23
24
25
26
REV. PrB 6/2001
41
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
26
24
22
20
18
16
14
12
10
8
6
4
2
35.00 BSC SQ
25
23
21
19
17
15
13
11
9
7
5
3
1
A
BALL A1
B
INDICATOR
C
D
E
F
G
H
J
K
L
M
N
TOP VIEW
BOTTOM VIEW
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
30.70
1.27 BSC SQ
BALL PITCH
30.00 SQ
29.50
31.75 BSC SQ
DETAIL A
2.62
2.37
2.12
1.22
1.17
1.12
0.70
0.60
0.50
NOTES:
1. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.30
OF THE IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.
2. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.15 OF ITS
IDEAL POSITION RELATIVE TO THE BALL GRID.
0.90
0.70
0.60
0.50
0.20 MAX
SEATING
PLANE
0.75
0.60
BALL DIAMETER
3. CENTER FIGURES ARE NOMINAL UNLESS OTHERWISE NOTED.
DETAIL A
Figure 28. 352-Lead metric Plastic Ball Grid Array (PBGA) (B-352)
ORDERING GUIDE
A complete modem requires the device listed in Table 19
plus a software solution as described in MODEM SOFTWARE
on page 2.
Table 19. Ordering Guide
Ambient Temperature
Package
Description
Part Number
Range
Instruction Rate
Package Option
ADSP-21mod980N-000
0ºC to +70ºC
80 MHz
352-Ball PBGA
B-352
42
6/2001 REV. PrB
相关型号：
ADSP-21MOD980N-210
ADSP-21mod980N-210: MultiPort Internet Gateway Processor Preliminary Data Sheet (Rev. PrB. 9/01)
ETC
ADSP-21MSP55ABS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP55AKS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP56ABS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
ADSP-21MSP56AKS-52
IC 24-BIT, 13 MHz, OTHER DSP, PQFP100, PLASTIC, QFP-100, Digital Signal Processor
ADI
©2020 ICPDF网 联系我们和版权申明