ADSP-BF526_技术文档

Blackfin^®Embedded Processor

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

FEATURES

PERIPHERALS

Up to 600 MHz high-performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

USB 2.0 high speed on-the-go (OTG) with Integrated PHY

IEEE 802.3-compliant 10/100 Ethernet MAC

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Operating Conditions for

ADSP-BF523/525/527 on Page 29 and Operating Condi-

tions for ADSP-BF522/524/526 on Page 27

Programmable on-chip voltage regulator

(ADSP-BF523/525/527 processors only)

Host DMA port (HOSTDP)

Two dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I²S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 54 interrupt inputs

Serial peripheral interface (SPI) compatible port

Two UARTs with IrDA^®support

289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm)

CSP_BGA packages

Two-wire interface (TWI) controller

Eight 32-bit timers/counters with PWM support

32-bit up/down counter with rotary support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), with programmable

hysteresis

NAND flash controller (NFC)

Debug/JTAG interface

On-chip PLL capable of 0.5

؋

to 64

؋

frequency multiplication

MEMORY

132K bytes of on-chip memory:

(See Table 1 on Page 3 for L1 and L3 memory size details)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI, and TWI

memory or from host devices including SPI, TWI, and UART

Code Security with Lockbox^TMSecure Technology

One-Time-Programmable (OTP) Memory

Memory management unit providing memory protection

WATCHDOG TIMER

OTP MEMORY

RTC

VOLTAGE REGULATOR*

JTAG TEST AND EMULATION

PERIPHERAL

COUNTER

SPORT0

SPORT1

UART1

UART0

NFC

ACCESS BUS

INTERRUPT

CONTROLLER

GPIO

PORT F

B

L1 INSTRUCTION

MEMORY

L1 DATA

GPIO

PORT G

DMA

MEMORY

PPI

CONTROLLER

DMA

ACCESS

BUS

EAB

16

SPI

DCB

USB

TIMER7-1

TIMER0

GPIO

PORT H

DEB

BOOT

ROM

EXTERNAL PORT

FLASH, SDRAM CONTROL

EMAC

HOST DMA

TWI

PORT J

*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY

Figure 1. Processor Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrG

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 9

Host DMA Port .................................................... 9

Real-Time Clock ................................................. 10

Watchdog Timer ................................................ 10

Timers ............................................................. 10

Up/Down Counter and Thumbwheel Interface .......... 10

Serial Ports ........................................................ 11

Serial Peripheral Interface (SPI) Port ....................... 11

UART Ports ...................................................... 11

TWI Controller Interface ...................................... 12

10/100 Ethernet MAC .......................................... 12

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 13

USB On-the-go dual-role device controller ............... 14

Code Security with Lockbox Secure Technology ......... 14

Dynamic Power Management ................................ 14

ADSP-BF523/525/527 Voltage Regulation ................ 15

ADSP-BF522/524/526 Voltage Regulation ................ 16

Clock Signals ..................................................... 16

Booting Modes ................................................... 18

Instruction Set Description .................................... 20

Development Tools .............................................. 21

Designing an Emulator-Compatible

Processor Board (Target) ................................... 21

Related Documents .............................................. 21

Lockbox Secure Technology Disclaimer .................... 21

Signal Descriptions ................................................. 22

Specifications ........................................................ 27

Operating Conditions for ADSP-BF522/524/526 ......... 27

Operating Conditions for ADSP-BF523/525/527 ......... 29

Electrical Characteristics ....................................... 31

Absolute Maximum Ratings ................................... 36

ESD Sensitivity ................................................... 37

Package Information ............................................ 37

Timing Specifications ........................................... 38

Output Drive Currents ......................................... 64

Test Conditions .................................................. 67

Environmental Conditions .................................... 71

289-Ball CSP_BGA Ball assignment ............................ 72

208-Ball CSP_BGA Ball assignment ............................ 75

Outline Dimensions ................................................ 78

Surface Mount Design .......................................... 79

Ordering Guide ..................................................... 80

REVISION HISTORY

2/09—Revision PrG:

Numerous small clarifications and corrections throughout

document.

Updated external crystal connections guidelines

in Figure 6 ...................................................... Page 17

Added electrical characteristics ............................ Page 31

Added total power dissipation data ....................... Page 33

Added maximum total source/sink (I_OH/I_OL) current

to absolute maximum ratings .............................. Page 36

Added capacitive loading data ............................. Page 68

Rev. PrG

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February 2009

Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are members of the Blackfin family of products,

incorporating the Analog Devices/Intel Micro Signal Architec-

ture (MSA). Blackfin processors combine a dual-MAC state-of-

the-art signal processing engine, the advantages of a clean,

orthogonal RISC-like microprocessor instruction set, and sin-

gle-instruction, multiple-data (SIMD) multimedia capabilities

into a single instruction-set architecture.

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are completely code compatible with other Blackfin

processors. The ADSP-BF523/525/527 processors offer perfor-

mance up to 600 MHz. The ADSP-BF522/524/526 processors

offer performance up to 400 MHz and reduced static power

consumption. Differences with respect to peripheral combina-

tions are shown in Table 1.

ADSP-BF522/523/524/525/526/527

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

Table 1. Processor Comparison

SYSTEM INTEGRATION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are highly integrated system-on-a-chip solutions for the

next generation of embedded network connected applications.

By combining industry-standard interfaces with a high perfor-

mance signal processing core, cost-effective applications can be

developed quickly, without the need for costly external compo-

nents. The system peripherals include an IEEE-compliant 802.3

10/100 Ethernet MAC, a USB 2.0 high speed OTG controller, a

TWI controller, a NAND flash controller, two UART ports, an

SPI port, two serial ports (SPORTs), eight general purpose 32-

bit timers with PWM capability, a core timer, a real-time clock,

a watchdog timer, a Host DMA (HOSTDP) interface, and a par-

allel peripheral interface (PPI).

Feature

Host DMA

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

2

1

8

1

USB

Ethernet MAC

Internal Voltage Regulator

TWI

SPORTs

UARTs

SPI

PROCESSOR PERIPHERALS

GP Timers

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors contain a rich set of peripherals connected to the core via

several high bandwidth buses, providing flexibility in system

configuration as well as excellent overall system performance

(see the block diagram on Page 1). These Blackfin processors

contain dedicated network communication modules and high

speed serial and parallel ports, an interrupt controller for flexi-

ble management of interrupts from the on-chip peripherals or

external sources, and power management control functions to

tailor the performance and power characteristics of the proces-

sor and system to many application scenarios.

All of the peripherals, except for the general-purpose I/O, TWI,

real-time clock, and timers, are supported by a flexible DMA

structure. There are also separate memory DMA channels dedi-

cated to data transfers between the processor's various memory

spaces, including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along

with activity on all of the on-chip and external peripherals.

Watchdog Timers

RTC

Parallel Peripheral Interface

GPIOs

48 48 48 48 48 48

48K 48K 48K 48K 48K 48K

L1 Instruction SRAM

L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K

L1 Data SRAM

32K 32K 32K 32K 32K 32K

4K 4K 4K 4K 4K 4K

32K 32K 32K 32K 32K 32K

L1 Data SRAM/Cache

L1 Scratchpad

L3 Boot ROM

Maximum Speed Grade¹

Maximum System Clock Speed

Package Options

400 MHz

80 MHz

600 MHz

133 MHz

289-Ball CSP_BGA

208-Ball CSP_BGA

¹Maximum speed grade is not available with every possible SCLK selection.

Rev. PrG

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The ADSP-BF523/525/527 processors include an on-chip volt-

age regulator in support of the processor’s dynamic power

management capability. The voltage regulator provides a range

of core voltage levels when supplied from V_DDEXT. The voltage

regulator can be bypassed at the user's discretion.

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

P3

DAG0

P2

P1

P0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Rev. PrG

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTES)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTES)

0xFFC0 0000

RESERVED

0xFFB0 1000

SCRATCHPAD SRAM (4K BYTES)

0xFFB0 0000

RESERVED

0xFFA1 4000

INSTRUCTION SRAM / CACHE (16K BYTES)

0xFFA1 0000

RESERVED

0xFFA0 C000

INSTRUCTION BANK B SRAM (16K BYTES)

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTES)

0xFFA0 0000

RESERVED

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTES)

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

0xFF90 4000

DATA BANK B SRAM (16K BYTES)

0xFF90 0000

RESERVED

0xFF80 8000

DATA BANK A SRAM / CACHE (16K BYTES)

0xFF80 4000

DATA BANK A SRAM (16K BYTES)

0xFF80 0000

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

RESERVED

0xEF00 8000

BOOT ROM (32K BYTES)

0xEF00 0000

RESERVED

0x2040 0000

ASYNC MEMORY BANK 3 (1M BYTES)

0x2030 0000

ASYNC MEMORY BANK 2 (1M BYTES)

0x2020 0000

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

ASYNC MEMORY BANK 1 (1M BYTES)

0x2010 0000

ASYNC MEMORY BANK 0 (1M BYTES)

0x2000 0000

RESERVED

0x08 00 0000

SDRAM MEMORY (16M BYTES

-128M BYTES)

0x0000 0000

Figure 3. Internal/External Memory Map

Internal (On-Chip) Memory

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

The processor has three blocks of on-chip memory providing

high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 3.

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 132M bytes of

physical memory.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

Rev. PrG

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The SDRAM controller can be programmed to interface to up

to 128M bytes of SDRAM. A separate row can be open for each

SDRAM internal bank and the SDRAM controller supports up

to 4 internal SDRAM banks, improving overall performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

ID, MAC address, etc. Hence generic parts can be shipped

which are then programmed and protected by the developer

within this non-volatile memory.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

NAND Flash Controller (NFC)

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors provide a NAND flash controller (NFC). NAND flash

devices provide high-density, low-cost memory. However,

NAND flash devices also have long random access times, invalid

blocks, and lower reliability over device lifetimes. Because of

this, NAND flash is often used for read-only code storage. In

this case, all DSP code can be stored in NAND flash and then

transferred to a faster memory (such as SDRAM or SRAM)

before execution. Another common use of NAND flash is for

storage of multimedia files or other large data segments. In this

case, a software file system may be used to manage reading and

writing of the NAND flash device. The file system selects mem-

ory segments for storage with the goal of avoiding bad blocks

and equally distributing memory accesses across all address

locations. Hardware features of the NFC include:

Booting

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 18.

Event Handling

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

• Support for page program, page read, and block erase of

NAND flash devices, with accesses aligned to page

boundaries.

• Error checking and correction (ECC) hardware that facili-

tates error detection and correction.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• A single 8-bit external bus interface for commands,

addresses and data.

• Support for SLC (single level cell) NAND flash devices

unlimited in size, with page sizes of 256 and 512 bytes.

Larger page sizes can be supported in software.

• Capability of releasing external bus interface pins during

long accesses.

• RESET – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Support for internal bus requests of 16-bits

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The processor event controller consists of two stages, the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

• DMA engine to transfer data between internal memory and

NAND flash device.

One-Time Programmable Memory

The processor has 64K bits of one-time programmable non-vol-

atile memory that can be programmed by the developer only

one time. It includes the array and logic to support read access

and programming. Additionally, its pages can be write

protected.

OTP enables developers to store both public and private data

on-chip. In addition to storing public and private key data for

applications requiring security, it also allows developers to store

completely user-definable data such as customer ID, product

Rev. PrG

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class

EVT Entry

EMU

0

Emulation/Test Control

Core Event Controller (CEC)

1

RESET

RST

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

2

Nonmaskable Interrupt

Exception

NMI

3

EVX

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General-Purpose Interrupt 7

General-Purpose Interrupt 8

General-Purpose Interrupt 9

General-Purpose Interrupt 10

General-Purpose Interrupt 11

General-Purpose Interrupt 12

General-Purpose Interrupt 13

General-Purpose Interrupt 14

General-Purpose Interrupt 15

8

IVG8

System Interrupt Controller (SIC)

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

General Purpose

Interrupt (at RESET) Peripheral Interrupt ID

Default

Core Interrupt ID

Peripheral Interrupt Event

PLL Wakeup Interrupt

DMA Error 0 (generic)

DMAR0 Block Interrupt

DMAR1 Block Interrupt

DMAR0 Overflow Error

DMAR1 Overflow Error

PPI Error

SIC Registers

IVG7

IVG8

IVG9

IVG10

0

1

2

3

IAR0 IMASK0, ISR0, IWR0

IAR1 IMASK0, ISR0, IWR0

IAR2 IMASK0, ISR0, IWR0

1

2

3

4

5

6

MAC Status

7

SPORT0 Status

8

SPORT1 Status

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Reserved

UART0 Status

UART1 Status

RTC

DMA Channel 0 (PPI/NFC)

DMA 3 Channel (SPORT0 RX)

DMA 4 Channel (SPORT0 TX)

DMA 5 Channel (SPORT1 RX)

DMA 6 Channel (SPORT1 TX)

TWI

DMA 7 Channel (SPI)

DMA8 Channel (UART0 RX)

DMA9 Channel (UART0 TX)

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 3. System Interrupt Controller (SIC) (Continued)

General Purpose

Interrupt (at RESET) Peripheral Interrupt ID

Default

Core Interrupt ID

Peripheral Interrupt Event

DMA10 Channel (UART1 RX)

DMA11 Channel (UART1 TX)

OTP Memory Interrupt

GP Counter

SIC Registers

IVG10

IVG11

IVG12

IVG13

IVG7

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

3

4

5

6

0

3

IAR3 IMASK0, ISR0, IWR0

IAR4 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

DMA1 Channel (MAC RX/HOSTDP)

Port H Interrupt A

DMA2 Channel (MAC TX/NFC)

Port H Interrupt B

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Port G Interrupt A

Port G Interrupt B

MDMA Stream 0

MDMA Stream 1

Software Watchdog Timer

Port F Interrupt A

Port F Interrupt B

SPI Status

NFC Status

IVG7

HOSTDP Status

IVG7

Host Read Done

USB_EINT Interrupt

USB_INT0 Interrupt

USB_INT1 Interrupt

USB_INT2 Interrupt

USB_DMAINT Interrupt

IVG7

IVG10

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

written while in supervisor mode. (Note that general-pur-

pose interrupts can be globally enabled and disabled with

the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

Event Control

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

• CEC interrupt latch register (ILAT) – Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

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The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask registers (SIC_IMASKx) – Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, that peripheral event is

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the processor DMA con-

troller include:

• A single, linear buffer that stops upon completion

• SIC interrupt status registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

• SIC interrupt wakeup enable registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled or in sleep mode when the event is generated.

For more information see Dynamic Power Management on

Page 14.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the processor system. This enables trans-

fers of blocks of data between any of the memories—including

external SDRAM, ROM, SRAM, and flash memory—with mini-

mal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

The processor also has an external DMA controller capability

via dual external DMA request pins when used in conjunction

with the external bus interface unit (EBIU). This functionality

can be used when a high speed interface is required for external

FIFOs and high bandwidth communications peripherals such as

USB 2.0. It allows control of the number of data transfers for

memory DMA. The number of transfers per edge is program-

mable. This feature can be programmed to allow memory DMA

to have an increased priority on the external bus relative to the

core.

HOST DMA PORT

The host port interface allows an external host to be a DMA

master to transfer data in and out of the device. The host device

masters the transactions and the Blackfin is the DMA slave.

The host port is enabled through the PAB interface. Once

enabled, the DMA is controlled by the external host, which can

then program the DMA to send/receive data to any valid inter-

nal or external memory location.

The host port interface controller has the following features.

• Allows external master to configure DMA read/write data

transfers and read port status.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that

support automated data transfers with minimal overhead for

the processor core. DMA transfers can occur between the pro-

cessor's internal memories and any of its DMA-capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interfaces, including

the SDRAM controller and the asynchronous memory control-

ler. DMA-capable peripherals include the Ethernet MAC, NFC,

HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi-

vidual DMA-capable peripheral has at least one dedicated DMA

channel.

• Uses asynchronous memory protocol for external interface.

• 8-/16-bit external data interface to host device.

• Half duplex operation

• Little-/big-endian data transfer.

The processor DMA controller supports both one-dimensional

(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-

fer initialization can be implemented from registers or from sets

of parameters called descriptor blocks.

• Acknowledge mode allows flow control on host

transactions.

• Interrupt mode guarantees a burst of FIFO depth host

transactions.

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Preliminary Technical Data

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine if the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the

Blackfin processor. The RTC peripheral has dedicated power

supply pins so that it can remain powered up and clocked even

when the rest of the processor is in a low-power state. The RTC

provides several programmable interrupt options, including

interrupt per second, minute, hour, or day clock ticks, interrupt

on programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor

from sleep mode upon generation of any RTC wakeup event.

Additionally, an RTC wakeup event can wake up the processor

from deep sleep mode or cause a transition from the hibernate

state.

TIMERS

There are nine general-purpose programmable timer units in

the processors. Eight timers have an external pin that can be

configured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs

to measure the width of the pulses in the data stream to provide

a software auto-baud detect function for the respective serial

channels.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

RTXI

RTXO

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

R1

X1

UP/DOWN COUNTER AND THUMBWHEEL

INTERFACE

C1

C2

A 32-bit up/down counter is provided that can sense 2-bit

quadrature or binary codes as typically emitted by industrial

drives or manual thumb wheels. The counter can also operate in

general-purpose up/down count modes. Then, count direction

is either controlled by a level-sensitive input pin or by two edge

detectors.

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three pins have a programmable debouncing circuit.

SUGGESTED COMPONENTS:

X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 MΩ

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 4. External Components for RTC

An internal signal forwarded to the timer unit enables one timer

to measure the intervals between count events. Boundary regis-

ters enable auto-zero operation or simple system warning by

interrupts when programmable count values are exceeded.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state through generation of a hardware reset, nonmaskable

interrupt (NMI), or general-purpose interrupt, if the timer

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SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA channel,

configurable to support transmit or receive data streams. The

SPI’s DMA channel can only service unidirectional accesses at

any given time.

SERIAL PORTS

The processors incorporate two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

The SPI port’s clock rate is calculated as:

f_SCLK

2 × SPI_BAUD

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

-----------------------------------

SPI Clock Rate =

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

The processors provide two full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

data. A UART port includes support for five to eight data bits,

one or two stop bits, and none, even, or odd parity. Each UART

port supports two modes of operation:

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Each UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The processors have an SPI-compatible port that enables the

processor to communicate with multiple SPI-compatible

devices.

The UART port’s clock rate is calculated as:

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

f_SCLK

16 × UART_Divisor

-----------------------------------------------

UART Clock Rate =

Where the 16-bit UART_Divisor comes from the UART_DLH

(most significant 8 bits) and UART_DLL (least significant

8 bits) registers.

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In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA®) serial infrared

physical layer link specification (SIR) protocol.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

• Programmable Ethernet event interrupt supports any com-

bination of:

TWI CONTROLLER INTERFACE

The processors include a two wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is compatible with the widely used

I²C^®bus standard. The TWI module offers the capabilities of

simultaneous master and slave operation, support for both 7-bit

addressing and multimedia data arbitration. The TWI interface

utilizes two pins for transferring clock (SCL) and data (SDA)

and supports the protocol at speeds up to 400k bits/sec. The

TWI interface pins are compatible with 5 V logic levels.

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at half-

full.

• DMA descriptor error.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

10/100 ETHERNET MAC

The ADSP-BF526 and ADSP-BF527 processors offer the capa-

bility to directly connect to a network by way of an embedded

Fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)

operation. The 10/100 Ethernet MAC peripheral on the proces-

sor is fully compliant to the IEEE 802.3-2002 standard and it

provides programmable features designed to minimize supervi-

sion, bus use, or message processing by the rest of the processor

system.

• Programmable Rx address filters, including a 64-bin

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

• Advanced power management supporting unattended

transfer of Rx and Tx frames and status to/from external

memory via DMA during low-power sleep mode.

• System wakeup from sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters.

Some standard features are:

• Support for 802.3Q tagged VLAN frames.

• Programmable MDC clock rate and preamble suppression.

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• In RMII operation, seven unused pins may be configured

as GPIO pins for other purposes.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

PORTS

Because of the rich set of peripherals, the processor groups the

many peripheral signals to four ports—Port F, Port G, Port H,

and Port J. Most of the associated pins are shared by multiple

signals. The ports function as multiplexer controls.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

General-Purpose I/O (GPIO)

The processor has 48 bidirectional, general-purpose I/O (GPIO)

pins allocated across three separate GPIO modules—PORTFIO,

PORTGIO, and PORTHIO, associated with Port F, Port G, and

Port H, respectively. Port J does not provide GPIO functional-

ity. Each GPIO-capable pin shares functionality with other

processor peripherals via a multiplexing scheme; however, the

GPIO functionality is the default state of the device upon

power-up. Neither GPIO output nor input drivers are active by

• SCLK operating range down to 25 MHz (active and sleep

operating modes).

• Internal loopback from Tx to Rx.

Some advanced features are:

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

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default. Each general-purpose port pin can be individually con-

trolled by manipulation of the port control, status, and interrupt

registers:

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

1. Input mode – Frame syncs and data are inputs into the PPI.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

2. Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

3. Output mode – Frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

register.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF522/524/526 and

ADSP-BF523/525/527 processors control when to read from the

video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a

VSYNC output.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

1. Active video only mode

2. Vertical blanking only mode

3. Entire field mode

Active Video Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

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Vertical Blanking Interval Mode

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Full-On Operating Mode—Maximum Performance

Entire Field Mode

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

Active Operating Mode—Moderate Dynamic Power

Savings

USB ON-THE-GO DUAL-ROLE DEVICE

CONTROLLER

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). If disabled, the PLL

control input must be re-enabled before transitioning to the

full-on or sleep modes.

The USB clock (USB_XI) is provided through a dedicated exter-

nal crystal or crystal oscillator. See Universal Serial Bus (USB)

On-The-Go—Receive and Transmit Timing on Page 54 for

related timing requirements. If using a crystal to provide the

USB clock, use a parallel-resonant, fundamental mode, micro-

processor-grade crystal.

The USB on-the-go dual-role device controller includes a phase

locked loop with programmable multipliers to generate the nec-

essary internal clocking frequency for USB. The multiplier value

should be programmed based on the USB_XI frequency to

achieve the necessary 480 MHz internal clock for USB high

speed operation. For example, for a USB_XI crystal frequency of

24 MHz, the USB_PLLOSC_CTRL register should be pro-

grammed with a multiplier value of 20 to generate a 480 MHz

internal clock.

Table 4. Power Settings

Core

Clock

System

Clock

PLL

Core

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Full On

Active

Enabled No

Enabled Enabled On

Enabled/ Yes

Enabled Enabled On

Disabled

Enabled

CODE SECURITY WITH LOCKBOX SECURE

TECHNOLOGY

A security system consisting of a blend of hardware and soft-

ware provides customers with a flexible and rich set of code

security features with Lockbox secure technology. Key features

include:

Sleep

—

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled

Hibernate Disabled

For more information about PLL controls, see the “Dynamic

Power Management” chapter in the ADSP-BF542x Blackfin

Processor Hardware Reference.

• OTP memory

• Unique chip ID

Sleep Operating Mode—High Dynamic Power Savings

• Code authentication

• Secure mode of operation

The security scheme is based upon the concept of authentica-

tion of digital signatures using standards-based algorithms and

provides a secure processing environment in which to execute

code and protect assets. See Lockbox Secure Technology Dis-

claimer on Page 21.

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity wakes up the processor.

When in the sleep mode, asserting a wakeup enabled in the

SIC_IWRx registers causes the processor to sense the value of

the BYPASS bit in the PLL control register (PLL_CTL). If

BYPASS is disabled, the processor transitions to the full on

mode. If BYPASS is enabled, the processor transitions to the

active mode.

DYNAMIC POWER MANAGEMENT

The processor provides five operating modes, each with a differ-

ent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 volt core supply voltage, the

System DMA access to L1 memory is not supported in

sleep mode.

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

the internal logic of the processor into its own power domain,

separate from the RTC and other I/O, the processor can take

advantage of dynamic power management without affecting the

RTC or other I/O devices. There are no sequencing require-

ments for the various power domains, but all domains must be

powered according to the appropriate Specifications table for

processor Operating Conditions; even if the feature/peripheral

is not used.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the proces-

sor to transition to the Active mode. Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Table 5. Power Domains

Power Domain

V_DDRange

All internal logic, except RTC, Memory, USB, OTP V_DDINT

RTC internal logic and crystal I/O

Memory logic

V_DDRTC

V_DDMEM

V_DDUSB

V_DDOTP

V_DDEXT

Hibernate State—Maximum Static Power Savings

USB PHY logic

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the synchronous peripherals (SCLK). The internal voltage regu-

lator (ADSP-BF523/525/527 only) for the processor can be shut

off by writing b#00 to the FREQ bits of the VR_CTL register.

This setting sets the internal power supply voltage (V_DDINT) to

0 V to provide the lowest static power dissipation. Any critical

information stored internally (for example, memory contents,

register contents, and other information) must be written to a

non-volatile storage device prior to removing power if the pro-

cessor state is to be preserved. Writing b#00 to the FREQ bits

also causes EXT_WAKE0 and EXT_WAKE1 to transition low,

which can be used to signal an external voltage regulator to shut

down.

OTP logic

All other I/O

The dynamic power management feature of the processor

allows both the processor’s input voltage (V_DDINT) and clock fre-

quency (f_CCLK) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Since V_DDEXTand V_DDMEMcan still be supplied in this mode, all

of the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

Power Savings Factor

The Ethernet or USB modules can wake up the internal supply

regulator (ADSP-BF525 and ADSP-BF527 only) or signal an

external regulator to wake up using EXT_WAKE0 or

EXT_WAKE1. If PG15 does not connect as a PHYINT signal to

an external PHY device, PG15 can be pulled low by any other

device to wake the processor up. The processor can also be

woken up by a real-time clock wakeup event or by asserting the

RESET pin. All hibernate wakeup events initiate the hardware

reset sequence. Individual sources are enabled by the VR_CTL

register. The EXT_WAKEx signals are provided to indicate the

occurrence of wakeup events.

As long as V_DDEXTis applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state. State

variables may be held in external SRAM or SDRAM. The SCK-

ELOW bit in the VR_CTL register controls whether or not

SDRAM operates in self-refresh mode, which allows it to retain

its content while the processor is in hibernate and through the

subsequent reset sequence.

2

f_CCLKRED

-------------------------

f_CCLKNOM

V_DDINTRED

-------------------------------

V_DDINTNOM

T_RED

--------------

T_NOM

















=

×

% Power Savings = (1 – Power Savings Factor) × 100%

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

V

T

ADSP-BF523/525/527 VOLTAGE REGULATION

The ADSP-BF523/525/527 provides an on-chip voltage regula-

tor that can generate processor core voltage levels from an

external supply. Figure 5 shows the typical external components

required to complete the power management system. The regu-

lator controls the internal logic voltage levels and is

programmable with the voltage regulator control register

(VR_CTL) in increments of 50 mV. To reduce standby power

Power Savings

As shown in Table 5, the processor supports six different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. By isolating

Rev. PrG

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while keeping I/O power

supplied. While in the hibernate state, all external supplies

(V_DDEXT, V_DDMEM, V_DDUSB, V_DDOTP) can still be applied, eliminat-

ing the need for external buffers. V_DDRTCmust be applied at all

times for correct hibernate operation. The voltage regulator can

be activated from this power down state either through an RTC

wakeup, a USB wakeup, an ethernet wakeup, or by asserting the

RESET pin, each of which then initiates a boot sequence. The

regulator can also be disabled and bypassed at the user’s

discretion.

ADSP-BF522/524/526 VOLTAGE REGULATION

The ADSP-BF522/524/526 processor requires an external volt-

age regulator to power the V_DDINTdomain. To reduce standby

power consumption, the external voltage regulator can be sig-

naled through EXT_WAKE0 or EXT_WAKE1 to remove power

from the processor core. These identical signals are high-true

for power-up and may be connected directly to the low-true

shut down input of many common regulators. While in the

hibernate state, all external supplies (V_DDEXT, V_DDMEM, V_DDUSB

,

V_DDOTP) can still be applied, eliminating the need for external

buffers. V_DDRTCmust be applied at all times for correct hibernate

operation. The external voltage regulator can be activated from

this power down state either through an RTC wakeup, a USB

wakeup, an ethernet wakeup, or by asserting the RESET pin,

each of which then initiates a boot sequence. EXT_WAKE0 or

EXT_WAKE1 indicate a wakeup to the external voltage regula-

tor. The Power Good (PG) input signal allows the processor to

start only after the internal voltage has reached a chosen level. In

this way, the startup time of the external regulator is detected

after hibernation. For a complete description of the Power Good

functionality, refer to the ADSP-BF52x Blackfin Processor Hard-

ware Reference.

SET OF DECOUPLING

CAPACITORS

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

V

DDEXT

(LOW-INDUCTANCE)

V

DDEXT

+

100μF

10μH

100μF

+

100nF

DDINT

+

FDS9431A

SS/PG

10μF

LOW ESR

ZHCS1000 100μF

CLOCK SIGNALS

VR

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

OUT

SHORT AND LOW-

INDUCTANCE WIRE

EXT_WAKE1

SEE H/W REFERENCE,

SYSTEM DESIGN CHAPTER,

TO DETERMINE VALUE

VR

SEL

GND

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

Figure 5. ADSP-BF523/525/527 Voltage Regulator Circuit

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the 500

kΩ range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 6 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

The voltage regulator has two modes set by the VR_SELpin—the

normal pulse width control of an external FET and the external

supply mode which can signal a power down during hibernate

to an external regulator. Set VR_SELto V_DDEXTto use an external

regulator or set VR_SELto GND to use the internal regulator. In

the external mode VR_OUTbecomes EXT_WAKE1. If the internal

regulator is used, EXT_WAKE0 can control other power

sources in the system during the hibernate state. Both signals

are high-true for power-up and may be connected directly to the

low-true shut down input of many common regulators. The

mode of the SS/PG (Soft Start/Power Good) signal also changes

according to the state of VR_SEL. When using an internal regula-

tor, the SS/PG pin is Soft Start, and when using an external

regulator, it is Power Good. The Soft Start feature is recom-

mended to reduce the inrush currents and to reduce V_DDINT

voltage overshoot when coming out of hibernate or changing

voltage levels. The Power Good (PG) input signal allows the

processor to start only after the internal voltage has reached a

chosen level. In this way, the startup time of the external regula-

tor is detected after hibernation. For a complete description of

Soft Start and Power Good functionality, refer to the ADSP-

BF52x Blackfin Processor Hardware Reference.

Rev. PrG

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

SDRAM interface, but it functions as a reference signal in other

timing specifications as well. While active by default, it can be

disabled using the EBIU_SDGCTL and EBIU_AMGCTL

registers.

BLACKFIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“CO ARSE” ADJUSTMENT

CLKOUT

ON-THE-FLY

TO PLL CIRCUITRY

EN

÷ 1, 2, 4, 8

CCLK

CLKBUF

PLL

0.5× to 64×

560 ⍀

CLKIN

VCO

EN

SCLK

÷ 1 to 15

CLKIN

XTAL

330 ⍀*

FOR OVERTONE

OPERATION ONLY:

SCLK ≤ CCLK

SCLK ≤ 133 MHz

18 pF *

Figure 7. Frequency Modification Methods

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0 ⍀.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

Figure 6. External Crystal Connections

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

Table 6. Example System Clock Ratios

Example Frequency Ratios

(MHz)

The CLKBUF pin is an output pin, which is a buffered version

of the input clock. This pin is particularly useful in Ethernet

applications to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the processor. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device. If instead of a crystal, an

external oscillator is used at CLKIN, CLKBUF will not have the

40/60 duty cycle required by some devices. The CLKBUF output

is active by default and can be disabled for power savings rea-

sons using the VR_CTL register.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 0.5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 10×, but it can be modi-

fied by a software instruction sequence.

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

VCO

100

300

500

SCLK

100

50

0001

1:1

0110

6:1

1010

10:1

50

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

Table 7. Core Clock Ratios

Example Frequency Ratios

(MHz)

VCO

300

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages V_DDINT, V_DDEXT, and

300

500

200

V

_DDMEM; the VCO is always permitted to run up to the frequency

specified by the part’s speed grade. The CLKOUT pin reflects

the SCLK frequency to the off-chip world. It is part of the

Rev. PrG

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The maximum CCLK frequency not only depends on the part's

speed grade (see Page 80), it also depends on the applied V_DDINT

voltage. See Table 12 and Table 15 for details. The maximal sys-

tem clock rate (SCLK) depends on the chip package and the

applied V_DDINT, V_DDEXT, and V_DDMEMvoltages (see Table 14 and

Table 17).

kernel performs an 8- or 16-bit boot or starts program exe-

cution at the address provided by the header. By default, all

configuration settings are set for the slowest device possible

(3-cycle hold time, 15-cycle R/W access times, 4-cycle

setup).

The ARDY is not enabled by default, but it can be enabled

through OTP programming. Similarly, all interface behav-

ior and timings can be customized through OTP

programming. This includes activation of burst-mode or

page-mode operation. In this mode, all asynchronous

interface signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2) —

In this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that the boot kernel has to

read from the FIFO must be requested by placing a low

pulse on the DMAR1 pin.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PG1 GPIO

pin to select a single SPI EEPROM/flash device and sub-

mits a read command and successive address bytes (0x00)

until a valid 8-, 16-, 24-, or 32-bit addressable device is

detected. Pull-up resistors are required on the SPISEL1 and

MISO pins. By default, a value of 0x85 is written to the

SPI_BAUD register.

BOOTING MODES

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by four BMODE input pins

dedicated to this purpose. There are two categories of boot

modes. In master boot modes the processor actively loads data

from parallel or serial memories. In slave boot modes the pro-

cessor receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time or

by proper OTP programming at pre-boot time. The BMODE

pins of the reset configuration register, sampled during power-

on resets and software-initiated resets, implement the modes

shown in Table 8.

Table 8. Booting Modes

• Boot from SPI host device (BMODE = 0x4) — The proces-

sor operates in SPI slave mode and is configured to receive

the bytes of the LDR file from an SPI host (master) agent.

The HWAIT signal must be interrogated by the host before

every transmitted byte. A pull-up resistor is required on the

SPISS input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

• Boot from serial TWI memory, EEPROM/flash

(BMODE = 0x5) — The processor operates in master mode

and selects the TWI slave connected to the TWI with the

unique ID 0xA0.

The processor submits successive read commands to the

memory device starting at internal address 0x0000 and

begins clocking data into the processor. The TWI memory

device should comply with the Philips I²C^®Bus Specifica-

tion version 2.1 and should be able to auto-increment its

internal address counter such that the contents of the

memory device can be read sequentially. By default, a

PRESCALE value of 0xA and a TWI_CLKDIV value of

0x0811 are used. Unless altered by OTP settings, an I²C

memory that takes two address bytes is assumed. The

development tools ensure that data booted to memories

that cannot be accessed by the Blackfin core is written to an

intermediate storage location and then copied to the final

destination via memory DMA.

BMODE3–0 Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Idle - No boot

Boot from 8- or 16-bit external flash memory

Boot from 16-bit asynchronous FIFO

Boot from serial SPI memory (EEPROM or flash)

Boot from SPI host device

Boot from serial TWI memory (EEPROM/flash)

Boot from TWI host

Boot from UART0 Host

Boot from UART1 Host

Reserved

Boot from SDRAM

Boot from OTP memory

Boot from 8-bit NAND flash

via NFC using PORTF data pins

1101

Boot from 8-bit NAND flash

via NFC using PORTH data pins

1110

1111

Boot from 16-Bit Host DMA

Boot from 8-Bit Host DMA

• Idle/no boot mode (BMODE = 0x0) — In this mode, the

processor goes into idle. The idle boot mode helps recover

from illegal operating modes, such as when the OTP mem-

ory has been misconfigured.

• Boot from TWI host (BMODE = 0x6) — The TWI host

selects the slave with the unique ID 0x5F.

The processor replies with an acknowledgement and the

host then downloads the boot stream. The TWI host agent

should comply with the Philips I²C Bus Specification

• Boot from 8-bit or 16-bit external flash memory

(BMODE = 0x1) — In this mode, the boot kernel loads the

first block header from address 0x2000 0000, and (depend-

ing on instructions contained in the header) the boot

Rev. PrG

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

version 2.1. An I²C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

• Boot from UART0 host on Port G (BMODE = 0x7) —

Using an autobaud handshake sequence, a boot-stream for-

matted program is downloaded by the host. The host

selects a bit rate within the UART clocking capabilities.

• Boot from 8-bit external NAND flash memory (BMODE =

0xC and BMODE = 0xD) — In this mode, auto detection of

the NAND flash device is performed.

BMODE = 0xC, the processor configures PORTF GPIO

pins PF7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

When performing the autobaud, the UART expects a “@”

(0x40) character (eight bits data, one start bit, one stop bit,

no parity bit) on the UART0RX pin to determine the bit

rate. The UART then replies with an acknowledgement

composed of 4 bytes (0xBF, the value of UART0_DLL, the

value of UART0_DLH, then 0x00). The host can then

download the boot stream. To hold off the host the Blackfin

processor signals the host with the boot host wait

(HWAIT) signal. Therefore, the host must monitor

HWAIT before every transmitted byte.

• Boot from UART1 host on Port F (BMODE = 0x8). Same

as BMODE = 0x7 except that the UART1 port is used.

• Boot from SDRAM (BMODE = 0xA) This is a warm boot

scenario, where the boot kernel starts booting from address

0x0000 0010. The SDRAM is expected to contain a valid

boot stream and the SDRAM controller must be configured

by the OTP settings.

• Boot from OTP memory (BMODE = 0xB) — This provides

a stand-alone booting method. The boot stream is loaded

from on-chip OTP memory. By default, the boot stream is

expected to start from OTP page 0x40 and can occupy all

public OTP memory up to page 0xDF. This is 2560 bytes.

Since the start page is programmable, the maximum size of

the boot stream can be extended to 3072 bytes.

BMODE = 0xD, the processor configures PORTH GPIO

pins PH7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

For correct device operation pull-up resistors are required

on both ND_CE (PH10) and ND_BUSY (PH13) signals. By

default, a value of 0x0033 is written to the NFC_CTL regis-

ter. The booting procedure always starts by booting from

byte 0 of block 0 of the NAND flash device.

NAND flash boot supports the following features:

—Device Auto Detection

—Error Detection & Correction for maximum reliability

—No boot stream size limitation

—Peripheral DMA providing efficient transfer of all data

(excluding the ECC parity data)

—Software-configurable boot mode for booting from

boot streams spanning multiple blocks, including bad

blocks

—Software-configurable boot mode for booting from

multiple copies of the boot stream, allowing for han-

dling of bad blocks and uncorrectable errors

—Configurable timing via OTP memory

Small page NAND flash devices must have a 512-byte page

size, 32 pages per block, a 16-byte spare area size, and a bus

configuration of 8 bits. By default, all read requests from

the NAND flash are followed by four address cycles. If the

NAND flash device requires only three address cycles, the

device must be capable of ignoring the additional address

cycles.

The small page NAND flash device must comply with the

following command set:

—Reset: 0xFF

Table 9. Fourth Byte for Large Page Devices

Bit

D1:D0 Page Size

(excluding spare area)

Parameter

Value Meaning

00

01

10

11

1K byte

2K byte

4K byte

8K byte

D2

Spare Area Size

00

01

8 byte/512 byte

16 byte/512 byte

—Read lower half of page: 0x00

—Read upper half of page: 0x01

—Read spare area: 0x50

D5:D4 Block Size

(excluding spare area)

00

01

10

11

64K byte

128K byte

256K byte

512K byte

For large-page NAND-flash devices, the four-byte elec-

tronic signature is read in order to configure the kernel for

booting, which allows support for multiple large-page

devices. The fourth byte of the electronic signature must

comply with the specification in Table 9.

D6

Bus width

00

01

x8

not supported

D3, D7 Not Used for configuration

Any NAND flash array configuration from Table 9, exclud-

ing 16-bit devices, that also complies with the command set

listed below are directly supported by the boot kernel.

There are no restrictions on the page size or block size as

imposed by the small-page boot kernel.

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

For devices consisting of a five-byte signature, only four are

read. The fourth must comply as outlined above.

Large page devices must support the following command

set:

—Reset: 0xFF

—Read Electronic Signature: 0x90

—Read: 0x00, 0x30 (confirm command)

troller, which then returns using an RTS instruction. The

routine may also by the final application, which will never

return to the boot kernel.

For each of the boot modes, a 16-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the address stored in the EVT1 register.

Prior to booting, the pre-boot routine interrogates the OTP

memory. Individual boot modes can be customized or even dis-

abled based on OTP programming. External hardware,

especially booting hosts, may watch the HWAIT signal to deter-

mine when the pre-boot has finished and the boot kernel starts

the boot process. By programming OTP memory, the user can

also instruct the pre-boot routine to customize the PLL, Internal

Voltage Regulator (ADSP-BF523/525/527 only), SDRAM Con-

troller, and Asynchronous Memory Controller.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

later case. Bits 6-4 in the system reset configuration (SYSCR)

register can be used to bypass the pre-boot routine and/or boot

kernel in case of a software reset. They can also be used to simu-

late a wakeup-from-hibernate boot in the software reset case.

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to configure

the SDRAM controller or to speed up booting by managing the

PLL, clock frequencies, wait states, or serial bit rates.

Large-page devices must not support or react to NAND

flash command 0x50. This is a small-page NAND flash

command used for device auto detection.

By default, the boot kernel will always issue five address

cycles; therefore, if a large page device requires only four

cycles, the device must be capable of ignoring the addi-

tional address cycles.

• Boot from 16-Bit Host DMA (BMODE = 0xE) — In this

mode, the host DMA port is configured in 16-bit Acknowl-

edge mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. After completing the

configuration, the host is required to poll the READY bit in

HOST_STATUS before beginning to transfer data. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to address 0xFFA0 0000. It is the

host's responsibility to ensure that valid code has been

placed at this address. The routine at 0xFFA0 0000 can be a

simple initialization routine to configure internal

The boot ROM also features C-callable function that can be

called by the user application at run time. This enables second-

stage boot or boot management schemes to be implemented

with ease.

resources, such as the SDRAM controller, which then

returns using an RTS instruction. The routine may also by

the final application, which will never return to the boot

kernel.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core

• Boot from 8-Bit Host DMA (BMODE = 0xF) — In this

mode, the Host DMA port is configured in 8-bit interrupt

mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. The host will receive an

interrupt from the HOST_ACK signal every time it is

allowed to send the next FIFO depths worth (sixteen 32-bit

words) of information. When the host sends an HIRQ con-

trol command, the boot kernel issues a CALL instruction to

address 0xFFA0 0000. It is the host's responsibility to

ensure valid code has been placed at this address. The rou-

tine at 0xFFA0 0000 can be a simple initialization routine

to configure internal resources, such as the SDRAM con-

processor resources.

Rev. PrG

|

Page 20 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

RELATED DOCUMENTS

The following publications that describe the ADSP-

BF522/524/526 and ADSP-BF523/525/527 processors (and

related processors) can be ordered from any Analog Devices

sales office or accessed electronically on our website:

• Getting Started With Blackfin Processors

• ADSP-BF52x Blackfin Processor Hardware Reference (vol-

umes 1 and 2)

• Blackfin Processor Programming Reference

• ADSP-BF522/524/526 Blackfin Processor Anomaly List

• ADSP-BF523/525/527 Blackfin Processor Anomaly List

LOCKBOX SECURE TECHNOLOGY DISCLAIMER

Analog Devices products containing Lockbox Secure Technol-

ogy are warranted by Analog Devices as detailed in the Analog

Devices Standard Terms and Conditions of Sale. To our knowl-

edge, the Lockbox Secure Technology, when used in accordance

with the data sheet and hardware reference manual specifica-

tions, provides a secure method of implementing code and data

safeguards. However, Analog Devices does not guarantee that

this technology provides absolute security.

DEVELOPMENT TOOLS

The processor is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other Blackfin processors also fully emulates the

ADSP-BF522/524/526 and ADSP-BF523/525/527 processors.

ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS

ANY AND ALL EXPRESS AND IMPLIED WARRANTIES

THAT THE LOCKBOX SECURE TECHNOLOGY CANNOT

BE BREACHED, COMPROMISED OR OTHERWISE CIR-

CUMVENTED AND IN NO EVENT SHALL ANALOG

DEVICES BE LIABLE FOR ANY LOSS, DAMAGE,

EZ-KIT Lite® Evaluation Board

For evaluation of ADSP-BF522/524/526 and

ADSP-BF523/525/527 processors, use the EZ-KIT Lite boards

available from Analog Devices. Order using part numbers

ADZS-BF526-EZLITE or ADZS-BF527-EZLITE. The boards

come with on-chip emulation capabilities and is equipped to

enable software development. Multiple daughter cards are

available.

DESTRUCTION OR RELEASE OF DATA, INFORMATION,

PHYSICAL PROPERTY OR INTELLECTUAL PROPERTY.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG processor. The

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Rev. PrG

|

Page 21 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

SIGNAL DESCRIPTIONS

Signal definitions for the ADSP-BF522/524/526 and

ADSP-BF523/525/527 processors are listed in Table 10. In order

to maintain maximum function and reduce package size and

ball count, some balls have dual, multiplexed functions. In cases

where ball function is reconfigurable, the default state is shown

in plain text, while the alternate function is shown in italics.

All pins are three-stated during and immediately after reset,

with the exception of the external memory interface, asynchro-

nous and synchronous memory control, and the buffered XTAL

output pin (CLKBUF). On the external memory interface, the

control and address lines are driven high, with the exception of

CLKOUT, which toggles at the system clock rate.

All I/O pins have their input buffers disabled with the exception

of the pins that need pull-ups or pull-downs, as noted in

Table 10.

It is strongly advised to use the available IBIS models to ensure

that a given board design meets overshoot/undershoot and sig-

nal integrity requirements. If no IBIS simulation is performed, it

is strongly recommended to add series resistor terminations for

all Driver Types A, C and D.

The termination resistors should be placed near the processor to

reduce transients and improve signal integrity. The resistance

value, typically 33 Ω or 47 Ω, should be chosen to match the

average board trace impedance.

Additionally, adding a parallel termination to CLKOUT may

prove useful in further enhancing signal integrity. Be sure to

verify overshoot/undershoot and signal integrity specifications

on actual hardware.

Table 10. Signal Descriptions

Driver

Type¹

Signal Name

EBIU

Type Function

ADDR19–1

DATA15–0

ABE1–0/SDQM1–0

AMS3–0

ARDY

O

I/O

O

I

Address Bus

Data Bus

A

Byte Enables/Data Mask

Bank Select

A

Hardware Ready Control

Output Enable

AOE

O

A

B

ARE

Read Enable

AWE

Write Enable

SRAS

SDRAM Row Address Strobe

SDRAM Column Address Strobe

SDRAM Write Enable

SDRAM Clock Enable

SDRAM Clock Output

SDRAM A10 Signal

SDRAM Bank Select

SCAS

SWE

SCKE

CLKOUT

SA10

A

SMS

Rev. PrG

|

Page 22 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 10. Signal Descriptions (Continued)

Driver

Type¹

Signal Name

USB 2.0 HS OTG

USB_DP

Type Function

I/O

I

Data + (This ball should be pulled low when USB is unused or not present.)

F

USB_DM

Data - (This ball should be pulled low when USB is unused or not present.)

USB_XI

USB Crystal Input (This ball should be pulled low when USB is unused or not

present.)

USB_XO

O

I

USB Crystal Output (This ball should be left unconnected when USB is unused F

or not present.)

USB_ID

USB OTG mode (This ball should be pulled low when USB is unused or not

present.)

USB_VREF

USB_RSET

USB_VBUS

I

USB voltage reference (Connect to GND through a 0.1 μF capacitor, or leave

unconnected if USB is unused or not present.)

I

USB resistance set. (This ball should be left unconnected when USB is unused

or not present.)

I/O 5V USB VBUS (USB_VBUS is an output only during initialization of USB OTG

session request pulses. Host mode or OTG type A mode require that an

external voltage source of 5V, at 8mA or more–per the OTG specification–be

applied to VBUS. Other OTG modes require that this external voltage be

disabled. This ball should be pulled low when USB is unused or not present.)

F

Port F: GPIO and Multiplexed Peripherals

PF0/PPI D0/DR0PRI /ND_D0A

I/O

GPIO/PPI Data 0/SPORT0 Primary Receive Data

/NAND Alternate Data 0

C

D

C

D

C

PF1/PPI D1/RFS0/ND_D1A

GPIO/PPI Data 1/SPORT0 Receive Frame Sync

/NAND Alternate Data 1

PF2/PPI D2/RSCLK0/ND_D2A

GPIO/PPI Data 2/SPORT0 Receive Serial Clock

/NAND Alternate Data 2/Alternate Capture Input 0

PF3/PPI D3/DT0PRI/ND_D3A

GPIO/PPI Data 3/SPORT0 Transmit Primary Data

/NAND Alternate Data 3

PF4/PPI D4/TFS0/ND_D4A/TACLK0

PF5/PPI D5/TSCLK0/ND_D5A/TACLK1

PF6/PPI D6/DT0SEC/ND_D6A/TACI0

PF7/PPI D7/DR0SEC/ND_D7A/TACI1

GPIO/PPI Data 4/SPORT0 Transmit Frame Sync

/NAND Alternate Data 4/Alternate Timer Clock 0

GPIO/PPI Data 5/SPORT0 Transmit Serial Clock

/NAND Alternate Data 5/Alternate Timer Clock 1

GPIO/PPI Data 6/SPORT0 Transmit Secondary Data

/NAND Alternate Data 6/Alternate Capture Input 0

GPIO/PPI Data 7/SPORT0 Receive Secondary Data

/NAND Alternate Data 7/Alternate Capture Input 1

PF8/PPI D8/DR1PRI

I/O

GPIO/PPI Data 8/SPORT1 Primary Receive Data

C

D

C

PF9/PPI D9/RSCLK1/SPISEL6

PF10/PPI D10/RFS1/SPISEL7

PF11/PPI D11/TFS1/CZM

PF12/PPI D12/DT1PRI/SPISEL2/CDG

GPIO/PPI Data 9/SPORT1 Receive Serial Clock/SPI Slave Select 6

GPIO/PPI Data 10/SPORT1 Receive Frame Sync/SPI Slave Select 7

GPIO/PPI Data 11/SPORT1 Transmit Frame Sync/Counter Zero Marker

GPIO/PPI Data 12/SPORT1 Transmit Primary Data/SPI Slave Select 2/Counter

Down Gate

PF13/PPI D13/TSCLK1/SPISEL3/CUD

I/O

GPIO/PPI Data 13/SPORT1 Transmit Serial Clock/SPI Slave Select 3/Counter Up

D

Direction

PF14/PPI D14/DT1SEC/UART1TX

I/O

GPIO/PPI Data 14/SPORT1 Transmit Secondary Data/UART1 Transmit

C

PF15/PPI D15/DR1SEC/UART1RX/TACI3

GPIO/PPI Data 15/SPORT1 Receive Secondary Data

/UART1 Receive /Alternate Capture Input 3

Port G: GPIO and Multiplexed Peripherals

Rev. PrG

|

Page 23 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 10. Signal Descriptions (Continued)

Driver

Type¹

Signal Name

Type Function

PG0/HWAIT

I/O

GPIO/Boot Host Wait²

C

PG1/SPISS/SPISEL1

PG2/SCK

GPIO/SPI Slave Select Input/SPI Slave Select 1

C

D

C

GPIO/SPI Clock

PG3/MISO/DR0SECA

PG4/MOSI/DT0SECA

PG5/TMR1/PPI_FS2

PG6/DT0PRIA/TMR2/PPI_FS3

PG7/TMR3/DR0PRIA/UART0TX

PG8/TMR4/RFS0A/UART0RX/TACI4

GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary

GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary

GPIO/Timer1/PPI Frame Sync2

GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3

GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit

GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync

/UART0 Receive/Alternate Capture Input 4

PG9/TMR5/RSCLK0A/TACI5

PG10/TMR6/TSCLK0A/TACI6

I/O

GPIO/Timer5/Sport 0 Alternate Receive Clock

/Alternate Capture Input 5

D

GPIO/Timer 6 /Sport 0 Alternate Transmit

/Alternate Capture Input 6

PG11/TMR7/HOST_WR

I/O

GPIO/Timer7/Host DMA Write Enable

C

PG12/DMAR1/UART1TXA/HOST_ACK

GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge

PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 I/O

GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate

Capture Input 2

PG14/TSCLK0A1/MDC/HOST_RD I/O

GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock

/Host DMA Read Enable

D

C

PG15³/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O

Port H: GPIO and Multiplexed Peripherals

GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII

Management Channel Data Interrupt/Host DMA Chip Enable

PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0

PH1/ND_D1/ERxER/HOST_D1

I/O

GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0

GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1

GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2

GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3

GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4

GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5

GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6

GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7

C

PH2/ND_D2/MDIO/HOST_D2

PH3/ND_D3/ETxEN/HOST_D3

PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O

PH5/ND_D5/ETxD0/HOST_D5

PH6/ND_D6/ERxD0/HOST_D6

PH7/ND_D7/ETxD1/HOST_D7

PH8/SPISEL4/ERxD1/HOST_D8/TACLK2

I/O

GPIO/Alternate Capture Input 2/Ethernet MII or RMII Receive D1/Host DMA D8

/SPI Slave Select 4

PH9/SPISEL5/ETxD2/HOST_D9/TACLK3

I/O

GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9

/Alternate Timer Clock 3

C

PH10/ND_CE/ERxD2/HOST_D10

PH11/ND_WE/ETxD3/HOST_D11

PH12/ND_RE/ERxD3/HOST_D12

PH13/ND_BUSY/ERxCLK/HOST_D13

PH14/ND_CLE/ERxDV/HOST_D14

I/O

GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10

GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11

GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12

GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13

C

GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data

Valid/Host DMA D14

PH15/ND_ALE/COL/HOST_D15

I/O

GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15

C

Rev. PrG

|

Page 24 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 10. Signal Descriptions (Continued)

Driver

Type¹

Signal Name

Type Function

Port J: Multiplexed Peripherals

PJ0: PPI_FS1/TMR0

PJ1: PPI_CLK/TMRCLK

PJ2: SCL

I/O

I

PPI Frame Sync1/Timer0

PPI Clock/Timer Clock

C

I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up

resistor.⁴)

E

PJ3: SDA

I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up

resistor.⁴)

Real Time Clock

RTXI

I

RTC Crystal Input (This ball should be pulled low when not used.)

RTC Crystal Output

RTXO

O

JTAG Port

TCK

I

JTAG Clock

TDO

O

I

JTAG Serial Data Out

C

TDI

JTAG Serial Data In

TMS

I

JTAG Mode Select

TRST

I

JTAG Reset (This ball should be pulled low if the JTAG port is not used.)

Emulation Output

EMU

O

Clock

CLKIN

I

Clock/Crystal Input

Crystal Output

XTAL

O

CLKBUF

Buffered XTAL Output

C

Mode Controls

RESET

I

Reset

NMI

Nonmaskable Interrupt (This ball should be pulled high when not used.)

Boot Mode Strap 3-0

BMODE3–0

ADSP-BF523/525/527 Voltage Regulation I/F

VR_SEL

I

Internal/External Voltage Regulator Select

External FET Drive/Wake up Indication 1

Wake up Indication 0

VR_OUT/EXT_WAKE1

O

I

G

C

EXT_WAKE0

SS/PG

Soft Start/Power Good

ADSP-BF522/524/526 Voltage Regulation I/F

EXT_WAKE1

EXT_WAKE0

PG

O

I

Wake up Indication 1

Wake up Indication 0

Power Good

C

Rev. PrG

|

Page 25 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 10. Signal Descriptions (Continued)

Driver

Type¹

Signal Name

Type Function

ALL SUPPLIES MUST BE POWERED

Power Supplies

See Operating Conditions for ADSP-BF523/525/527 on Page 29,

and see Operating Conditions for ADSP-BF522/524/526 on Page 27.

V_DDEXT

V_DDINT

V_DDRTC

V_DDUSB

V_DDMEM

V_DDOTP

V_PPOTP

V_SS

P

G

I/O Power Supply

Internal Power Supply

Real Time Clock Power Supply

3.3 V USB Phy Power Supply

MEM Power Supply

OTP Power Supply

OTP Programming Voltage

Ground for All Supplies

¹See Output Drive Currents on Page 64 for more information about each driver type.

²HWAIT must be pulled high or low to configure polarity. It is driven as an output and toggle during processor boot. See Booting Modes on Page 18.

³When driven low, this ball can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as MII PHYINT. If the ball is used

for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the ball with a resistor.

⁴Consult version 2.1 of the I²C specification for the proper resistor value.

Rev. PrG

|

Page 26 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

SPECIFICATIONS

Specifications are subject to change without notice.

OPERATING CONDITIONS FOR ADSP-BF522/524/526

Parameter

Conditions

Min

tbd

1.70

2.25

1.70

2.25

Nominal

tbd

1.8, 2.5 or 3.3

Max

tbd

3.6

Unit

V

V_DDINT

V_DDEXT

V_DDRTC

Internal Supply Voltage

External Supply Voltage

RTC Power Supply Voltage

MEM Supply Voltage

1

2

3

V_DDMEM

1.8, 2.5 or 3.3

2.5

V_DDOTP

V_PPOTP

OTP Supply Voltage

2.75

V

OTP Programming Voltage

For Reads

2.25

6.9

3.0

1.1

1.7

2.5

7.0

3.3

2.75

7.1

3.6

V_BUSTWI

0.6

0.7

0.8

V

°C

For Writes⁴

V_DDUSB

V_IH

V_IHTWI

V_IL

V_ILTWI

T_J

USB Supply Voltage⁵

High Level Input Voltage^{6, 7}

High Level Input Voltage

Low Level Input Voltage^{6, 7}

Low Level Input Voltage

Junction Temperature

V_DDEXT/V_DDMEM= 1.90 V

V_DDEXT/V_DDMEM= 2.75 V

V_DDEXT/V_DDMEM= 3.6 V

V_DDEXT= 1.90 V/2.75 V/3.6 V

V_DDEXT/V_DDMEM= 1.7 V

V_DDEXT/V_DDMEM= 2.25 V

V_DDEXT/V_DDMEM= 3.0 V

V_DDEXT= minimum

2.0

8

0.7 x V_BUSTWI

–0.3

0

9

0.3 x V_BUSTWI

+105

289-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

T_J

Junction Temperature

208-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

208-Ball CSP_BGA

0

+105

°C

–40

@ T_AMBIENT= –40°C to +85°C

¹Must remain powered (even if the associated function is not used).

²If not used, power with V_DDEXT

³Balls that use V_DDMEMare DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant

.

to voltages higher than V_DDMEM

.

⁴The V_PPOTPvoltage for writes must only be applied when programming OTP memory. There is a finite amount of cumulative time that this voltage may be applied (dependent

on voltage and junction temperature) over the lifetime of the part. Please see Table 27 on Page 36 for details.

⁵When not using the USB peripheral on the ADSP-BF524/BF526 or terminating V_DDUSBon the ADSP-BF522, V_DDUSBmust be powered by V_DDEXT

.

⁶Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-

BF522/523/524/525/526/527 processors are 3.3 V tolerant (always accept up to 3.6 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply

voltage.

⁷Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL.

⁸The V_IHTWImin and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V_BUSTWImin and max values in Table 11.

⁹SDA and SCL are pulled up to V_BUSTWI. See Table 11.

Rev. PrG

|

Page 27 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE

register. Set this register prior to using the TWI port.

Table 11. TWI_DT Field Selections and V_DDEXT/V_BUSTWI

TWI_DT

V_DDEXTNominal

V_BUSTWIMinimum

V_BUSTWINominal

V_BUSTWIMaximum

Unit

V

–

000 (default)¹

3.3

1.8

2.5

1.8

3.3

1.8

2.5

–

2.97

1.7

2.97

4.5

2.25

–

3.3

1.8

3.3

5

2.5

–

3.63

1.98

3.63

5.5

2.75

–

001

010

011

100

101

110

111 (reserved)

¹Designs must comply with the V_DDEXTand V_BUSTWIvoltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.

ADSP-BF522/524/526 Clock Related Operating Conditions

Table 12 describes the core clock timing requirements for the

ADSP-BF522/524/526 processors. Take care in selecting MSEL,

SSEL, and CSEL ratios so as not to exceed the maximum core

clock and system clock (see Table 14). Table 13 describes phase-

locked loop operating conditions.

Table 12. Core Clock (CCLK) Requirements—ADSP-BF522/524/526 Processors—All Speed Grades¹

Parameter

f_CCLK

Max

400³

350

Unit

MHz

Core Clock Frequency (V_DDINT=tbd²V minimum)

Core Clock Frequency (V_DDINT=tbd⁴V minimum)

Core Clock Frequency (V_DDINT= tbd⁵V minimum)

Core Clock Frequency (V_DDINT= tbd V minimum)

f_CCLK

300

f_CCLK

TBD

f_CCLK

¹See the Ordering Guide on Page 80.

²Preliminary data indicates a value of 1.33 V.

³Applies only to 400 MHz speed grade only. See the Ordering Guide on Page 80.

⁴Preliminary data indicates a value of 1.235 V.

⁵Preliminary data indicates a value of 1.14 V.

Table 13. Phase-Locked Loop Operating Conditions

Parameter

f_VCO

Minimum

Maximum

Speed Grade¹

Unit

MHz

Voltage Controlled Oscillator (VCO) Frequency

50

¹See the Ordering Guide on Page 80.

Table 14. ADSP-BF522/524/526 Processors Maximum SCLK Conditions

Parameter

f_SCLK

V_DDEXT/V_DDMEM= 1.8 V/2.5 V/3.3 V Nominal

Unit

MHz

CLKOUT/SCLK Frequency (V_DDINT≥ tbd V)¹

CLKOUT/SCLK Frequency (V_DDINT< tbd V)

80

f_SCLK

tbd

¹f_SCLKmust be less than or equal to f_CCLKand is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44.

Rev. PrG

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Page 28 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

OPERATING CONDITIONS FOR ADSP-BF523/525/527

Parameter

V_DDINT

Conditions

Min

0.95

1.70

Nominal

Max

1.26

3.6

Unit

V

Internal Supply Voltage¹

External Supply Voltage^{2, 3}

V_DDEXT

Internal Voltage Regulator

Disabled

1.8, 2.5 or 3.3

2.5 or 3.3

V

V_DDEXT

External Supply Voltage^{2, 3}

Internal Voltage Regulator

Enabled

2.25

3.6

V

V_DDRTC

V_DDMEM

V_DDOTP

V_PPOTP

V_DDUSB

V_IH

RTC Power Supply Voltage⁴

MEM Supply Voltage^{2, 5}

OTP Supply Voltage²

OTP Programming Voltage²

USB Supply Voltage⁶

High Level Input Voltage^{7, 8}

High Level Input Voltage

Low Level Input Voltage^{7, 8}

Low Level Input Voltage

Junction Temperature

2.25

1.70

2.25

3.0

3.6

V

°C

1.8, 2.5 or 3.3

2.5

3.3

2.75

3.6

V_DDEXT/V_DDMEM= 1.90 V

V_DDEXT/V_DDMEM= 2.75 V

V_DDEXT/V_DDMEM= 3.6 V

V_DDEXT= 1.90 V/2.75 V/3.6 V

V_DDEXT/V_DDMEM= 1.7 V

V_DDEXT/V_DDMEM= 2.25 V

V_DDEXT/V_DDMEM= 3.0 V

V_DDEXT= minimum

1.1

3.6

V_IH

1.7

3.6

V_IH

2.0

3.6

9

V_IHTWI

V_IL

0.7 x V_BUSTWI

–0.3

0

V_BUSTWI

0.6

V_IL

0.7

V_IL

0.8

10

V_ILTWI

T_J

0.3 x V_BUSTWI

+105

289-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

T_J

Junction Temperature

208-Ball CSP_BGA

@ T_AMBIENT= 0°C to +70°C

0

+105

°C

208-Ball CSP_BGA

–40

@ T_AMBIENT= –40°C to +85°C

¹The voltage regulator can generate V_DDINTat levels of 1.00 V to 1.20 V with –5% to +5% tolerance when VRCTL is programmed with the sysctl API. This specification is only

guaranteed when the API is used.

²Must remain powered (even if the associated function is not used).

³V_DDEXTis the supply to the voltage regulator and GPIO.

⁴If not used, power with V_DDEXT

.

⁵Balls that use V_DDMEMare DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AOE, AMS3–0, ARDY, SA10, SWE, SCAS, CLKOUT, SRAS, SMS, SCKE. These balls are not tolerant

to voltages higher than V_DDMEM

.

⁶When not using the USB peripheral on the ADSP-BF525/BF527 or terminating V_DDUSBon the ADSP-BF523, V_DDUSBmust be powered by V_DDEXT

.

⁷Bidirectional balls (PF15–0, PG15–0, PH15–0) and input balls (RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-

BF522/523/524/525/526/527 processors are 3.3 V tolerant (always accept up to 3.6 V maximum V_IH). Voltage compliance (on outputs, V_OH) is limited by the V_DDEXTsupply

voltage.

⁸Parameter value applies to all input and bidirectional balls, except USB_DP, USB_DM, USB_VBUS, SDA, and SCL.

⁹The V_IHTWImin and max value vary with the selection in the TWI_DT field of the NONGPIO_DRIVE register. See V_BUSTWImin and max values in Table 11 on Page 28.

¹⁰SDA and SCL are pulled up to V_BUSTWI. See Table 11 on Page 28.

Rev. PrG

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Page 29 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

ADSP-BF523/525/527 Clock Related Operating Conditions

Table 15 describes the core clock timing requirements for the

ADSP-BF523/525/527 processors. Take care in selecting MSEL,

SSEL, and CSEL ratios so as not to exceed the maximum core

clock and system clock (see Table 17). Table 16 describes phase-

locked loop operating conditions.

Table 15. Core Clock (CCLK) Requirements—ADSP-BF523/525/527 Processors—All Speed Grades¹

Parameter

f_CCLK

Internal Regulator Setting

Max

600

533

400

Unit

MHz

Core Clock Frequency (V_DDINT=1.14 V minimum)²

Core Clock Frequency (V_DDINT=1.093 V minimum)³

Core Clock Frequency (V_DDINT= 0.95 V minimum)

1.20 V

1.15 V

1.0 V

f_CCLK

¹See the Ordering Guide on Page 80.

²Applies only to 600 MHz speed grades. See the Ordering Guide on Page 80.

³Applies only to 533 MHz and 600 MHz speed grades. See the Ordering Guide on Page 80.

Table 16. Phase-Locked Loop Operating Conditions

Parameter

f_VCO

Minimum

Maximum

Speed Grade¹

Unit

MHz

Voltage Controlled Oscillator (VCO) Frequency

50

¹See the Ordering Guide on Page 80.

Table 17. ADSP-BF523/525/527 Processors Maximum SCLK Conditions

V_DDEXT/V_DDMEM= 1.8 V

Nominal¹

V_DDEXT/V_DDMEM= 2.5 V/3.3 V

Nominal

Parameter

f_SCLK

Unit

MHz

CLKOUT/SCLK Frequency (V_DDINT≥ 1.14 V)²

CLKOUT/SCLK Frequency (V_DDINT< 1.14 V)²

100

133³

100

f_SCLK

¹If either V_DDEXTor V_DDMEMare operating at 1.8V nominal, f_SCLKis constrained to 100MHz.

²f_SCLKmust be less than or equal to f_CCLKand is subject to additional restrictions for SDRAM interface operation. See Table 34 on Page 44.

³Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 34 on Page 44.

Rev. PrG

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Page 30 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

ELECTRICAL CHARACTERISTICS

Table 18. Common Electrical Characteristics For All ADSP-BF522/523/524/525/526/527 Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

V_OH

High Level Output Voltage V_DDEXT/V_DDMEM= 1.7 V,

I_OH= –0.5 mA

1.35

V

V_OH

V_OL

I_IH

High Level Output Voltage V_DDEXT/V_DDMEM= 2.25 V,

I_OH= –0.5 mA

2.0

2.4

V

High Level Output Voltage V_DDEXT/V_DDMEM= 3.0 V,

I_OH= –0.5 mA

V

Low Level Output Voltage

High Level Input Current¹

Low Level Input Current¹

V_DDEXT/V_DDMEM=1.7/2.25/3.0 V,

I_OL= 2.0 mA

0.4

V

V_DDEXT/V_DDMEM=3.6 V,

V_IN= 3.6 V

10.0

μA

I_IL

V_DDEXT/V_DDMEM=3.6 V, V_IN= 0 V

10.0

75.0

10.0

μA

I_IHP

I_OZH

High Level Input Current JTAG²V_DDEXT= 3.6 V, V_IN= 3.6 V

Three-State Leakage Current³V_DDEXT/V_DDMEM= 3.6 V,

V_IN= 3.6 V

I_OZHTWI

I_OZL

Three-State Leakage Current⁴V_DDEXT=3.0 V, V_IN= 5.5 V

10.0

8⁶

μA

pF

Three-State Leakage Current³V_DDEXT/V_DDMEM= 3.6 V, V_IN= 0 V

C_IN

Input Capacitance⁵

f_IN= 1 MHz, T_AMBIENT= 25°C,

V_IN= 2.5 V

5

¹Applies to input balls.

²Applies to JTAG input balls (TCK, TDI, TMS, TRST).

³Applies to three-statable balls.

⁴Applies to bidirectional balls SCL and SDA.

⁵Applies to all signal balls.

⁶Guaranteed, but not tested.

Table 19. Electrical Characteristics For ADSP-BF522/524/526 Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

1

I_DDDEEPSLEEP

V_DDINTCurrent in Deep Sleep V_DDINT= 1.0 V, f_CCLK= 0 MHz,

TBD

mA

Mode

f

_SCLK= 0 MHz, T_J= 25°C,

ASF = 0.00

I_DDSLEEP

I_DD-IDLE

I_DD-TYP

V_DDINTCurrent in Sleep Mode V_DDINT= 1.0 V, f_SCLK= 25 MHz,

T_J= 25°C

TBD

mA

V_DDINTCurrent in Idle

V_DDINT= 1.0 V, f_CCLK= 50 MHz,

T_J= 25°C, ASF = 0.44

V_DDINTCurrent

V_DDINT= 1.0 V, f_CCLK= 400 MHz,

T_J= 25°C, ASF = 1.00

V_DDINTCurrent

V_DDINT= 1.15 V, f_CCLK= 533 MHz,

T_J= 25°C, ASF = 1.00

V_DDINTCurrent

V_DDINT= 1.2 V, f_CCLK= 600 MHz,

T_J= 25°C, ASF = 1.00

Rev. PrG

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Page 31 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 19. Electrical Characteristics For ADSP-BF522/524/526 Processors (Continued)

Parameter

Test Conditions

Min

Typical

Max

Unit

1, 2

I_DDHIBERNATE

Hibernate State Current

V_DDEXT=V_DDMEM=V_DDRTC

=

TBD

μA

V

_DDUSB= 3.30 V,

V_DDOTP=V_PPOTP=2.5 V,

T_J= 25°C, CLKIN = 0 MHz

with voltage regulator off

(V_DDINT= 0 V)

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_J= 25°C

TBD

μA

I_DDUSB-FS

V_DDUSBCurrent in Full/Low

Speed Mode

V_DDUSB= 3.3 V, T_J= 25°C, Full

Speed USB Transmit

mA

I_DDUSB-HS

V_DDUSBCurrent in High Speed V_DDUSB= 3.3 V, T_J= 25°C, High

Mode Speed USB Transmit

TBD

mA

1, 3

I_DDSLEEP

V_DDINITCurrent in Sleep Mode f_CCLK= 0 MHz, f_SCLK> 0 MHz

Table 22 +

mA⁴

(TBD × V_DDINT

×

4

f_SCLK

)

1, 3

I_DDDEEPSLEEP

V_DDINTCurrent in Deep Sleep f_CCLK= 0 MHz, f_SCLK= 0 MHz

Mode

Table 22

mA

3, 5

I_DDINT

V_DDINTCurrent

f

_CCLK> 0 MHz, f_SCLK≥ 0 MHz

Table 22 +

(Table 24 × ASF) +

(TBD × V_DDINT

f_SCLK

×

)

¹See the ADSP-BF522/523/524/525/526/527 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

²Includes current on V_DDEXT, V_DDUSB, V_DDMEM, V_DDOTP, and V_PPOTPsupplies. Clock inputs are tied high or low.

³Guaranteed maximum specifications.

⁴Unit for V_DDINTis V (Volts). Unit for f_SCLKis MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder.

⁵See Table 21 for the list of I_DDINTpower vectors covered.

Table 20. Electrical Characteristics For ADSP-BF523/525/527 Processors

Parameter

Test Conditions

Min

Typical

Max

Unit

1

I_DDDEEPSLEEP

V_DDINTCurrent in Deep Sleep V_DDINT= 1.0 V, f_CCLK= 0 MHz,

10

mA

Mode

f_SCLK= 0 MHz, T_J= 25°C,

ASF = 0.00

I_DDSLEEP

I_DD-IDLE

I_DD-TYP

V_DDINTCurrent in Sleep Mode V_DDINT= 1.0 V, f_SCLK= 25 MHz,

T_J= 25°C

15

49

mA

V_DDINTCurrent in Idle

V_DDINT= 1.0 V, f_CCLK= 50 MHz,

T_J= 25°C, ASF = 0.44

V_DDINTCurrent

V_DDINT= 1.0 V, f_CCLK= 400 MHz,

T_J= 25°C, ASF = 1.00

98

V_DDINTCurrent

V_DDINT= 1.15 V, f_CCLK= 533

MHz,

149

T_J= 25°C, ASF = 1.00

I_DD-TYP

V_DDINTCurrent

V_DDINT= 1.2 V, f_CCLK= 600 MHz,

T_J= 25°C, ASF = 1.00

176

mA

Rev. PrG

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Page 32 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 20. Electrical Characteristics For ADSP-BF523/525/527 Processors (Continued)

Parameter

Test Conditions

Min

Typical

Max

Unit

1, 2

I_DDHIBERNATE

Hibernate State Current

V_DDEXT=V_DDMEM=V_DDRTC

=

40

μA

V

_DDUSB= 3.30 V,

V_DDOTP=V_PPOTP=2.5 V,

T_J= 25°C, CLKIN = 0 MHz

with voltage regulator off

(V_DDINT= 0 V)

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_J= 25°C

20

9

μA

I_DDUSB-FS

V_DDUSBCurrent in Full/Low

Speed Mode

V_DDUSB= 3.3 V, T_J= 25°C,

Full Speed USB Transmit

mA

I_DDUSB-HS

V_DDUSBCurrent in High Speed V_DDUSB= 3.3 V, T_J= 25°C,

Mode High Speed USB Transmit

25

mA

1, 3

I_DDSLEEP

V_DDINITCurrent in Sleep Mode f_CCLK= 0 MHz, f_SCLK> 0 MHz

Table 23 +

mA⁴

(0.43 × V_DDINT

×

4

f_SCLK

)

1, 3

I_DDDEEPSLEEP

V_DDINTCurrent in Deep Sleep f_CCLK= 0 MHz, f_SCLK= 0 MHz

Mode

Table 23

mA

3, 5

I_DDINT

V_DDINTCurrent

f

_CCLK> 0 MHz, f_SCLK≥ 0 MHz

Table 23 +

(Table 25 × ASF) +

(0.43 × V_DDINT

f_SCLK

×

)

¹See the ADSP-BF522/523/524/525/526/527 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

²Includes current on V_DDEXT, V_DDUSB, V_DDMEM, V_DDOTP, and V_PPOTPsupplies. Clock inputs are tied high or low.

³Guaranteed maximum specifications.

⁴Unit for V_DDINTis V (Volts). Unit for f_SCLKis MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder.

⁵See Table 21 for the list of I_DDINTpower vectors covered.

Total Power Dissipation

Total power dissipation has two components:

1. Static, including leakage current

2. Dynamic, due to transistor switching characteristics

The ASF is combined with the CCLK Frequency and V_DDINT

dependent data in Table 24 or Table 25 to calculate this part.

The second part is due to transistor switching in the system

clock (SCLK) domain, which is included in the I_DDINTspecifica-

tion equation.

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. Electrical Characteristics on Page 31 shows the

current dissipation for internal circuitry (V_DDINT). I_DDDEEPSLEEP

specifies static power dissipation as a function of voltage

(V_DDINT) and temperature (see Table 22 or Table 23), and I_DDINT

specifies the total power specification for the listed test condi-

tions, including the dynamic component as a function of voltage

(V_DDINT) and frequency (Table 24 or Table 25).

There are two parts to the dynamic component. The first part is

due to transistor switching in the core clock (CCLK) domain.

This part is subject to an Activity Scaling Factor (ASF) which

represents application code running on the processor core and

L1/L2 memories (Table 21).

Table 21. Activity Scaling Factors (ASF)¹

I_DDINTPower Vector

I_DD-PEAK

Activity Scaling Factor (ASF)

1.29

1.26

1.00

0.88

0.72

0.44

I_DD-HIGH

I_DD-TYP

I_DD-APP

I_DD-NOP

I_DD-IDLE

¹See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors

(EE-297). The power vector information also applies to the ADSP-BF52x

processors.

Rev. PrG

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Page 33 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 22. ADSP-BF522/524/526 Static Current - I_DD-DEEPSLEEP(mA)¹

2

Voltage (V_DDINT

)

T_J(°C)²

–40

–20

0

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

25

40

55

70

85

100

105

¹Values are guaranteed maximum I_DDDEEPSLEEPfor non-automotive 400 MHz speed-grade devices.

²Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/524/526 on Page 27.

Table 23. ADSP-BF523/525/527 Static Current - I_DD-DEEPSLEEP(mA)¹

2

Voltage (V_DDINT

)

T_J(°C)²

–40

–20

0

0.95 V

6.5

1.00 V

7.8

1.05 V

9.3

1.10 V

11.1

1.15 V

13.1

1.20 V

15.4

1.25 V

18.0

1.30 V

21.0

9.0

10.6

15.2

25.4

34.8

47.9

65.6

88.6

118.7

132.1

12.4

17.7

28.9

39.2

53.6

72.9

97.9

130.5

144.7

14.6

17.0

19.8

22.9

26.4

13.2

22.3

30.8

42.9

59.1

80.4

109.3

120.8

20.4

23.5

27.0

30.9

35.3

25

32.8

37.2

42.1

47.6

53.7

40

44.1

49.6

55.7

62.5

70.0

55

59.9

66.9

74.6

83.2

92.6

70

80.8

89.7

99.4

110.2

145.1

189.7

209.3

122.0

159.8

208.1

229.2

85

107.8

143.2

158.8

119.2

157.4

174.2

131.5

172.8

190.9

100

105

¹Values are guaranteed maximum I_DDDEEPSLEEPfor non-automotive 400 MHz speed-grade devices.

²Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/525/527 on Page 29.

Rev. PrG

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Page 34 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 24. ADSP-BF522/524/526 Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹

2

f_CCLK

Voltage (V_DDINT)

TBD V

TBD

(MHz)²

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

TBD V

TBD

400

300

200

100

TBD

¹The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 31.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/524/526 on Page 27.

Table 25. ADSP-BF523/525/527 Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹

2

f_CCLK

Voltage (V_DDINT)

1.10 V

n/a

(MHz)²

0.95 V

n/a

1.00 V

n/a

1.05 V

n/a

1.15 V

130.4

116.7

109.1

88.5

1.20 V

137.6

123.3

115.0

93.5

1.25 V

145.1

129.8

121.3

98.6

1.30 V

152.5

136.4

127.7

103.9

80.0

600

533

500

400

300

200

100

n/a

110.3

103.1

83.6

n/a

97.3

78.9

60.4

41.9

23.6

69.8

53.4

36.9

20.5

74.3

56.9

39.4

22.0

64.1

68.0

71.8

75.8

44.6

47.4

50.1

53.0

56.0

25.3

27.0

28.8

30.6

32.5

¹The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 31.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF523/525/527 on Page 29.

Rev. PrG

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Page 35 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

time for the ADSP-BF522/524/526 processors is shown in

Table 27. The ADSP-BF523/525/527 processors do not have a

similar restriction.

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in the table may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

Table 27. Maximum OTP Memory Programming Time for

ADSP-BF522/524/526 Processors

Temperature (T_J)

VPPOTP Voltage (V) 25°C

85°C

110°C 125°C

6.9

7.0

7.1

tbd sec tbd sec tbd sec tbd sec

2400 sec tbd sec tbd sec tbd sec

1000 sec tbd sec tbd sec tbd sec

Parameter

Rating

Internal Supply Voltage (V_DDINT),

for ADSP-BF523/525/527 processors

–0.3 V to +1.26 V

Internal Supply Voltage (V_DDINT),

for ADSP-BF522/524/526 processors

TBD V to TBD V

–0.3 V to +3.8 V

The Absolute Maximum Ratings table specifies the maximum

total source/sink (I_OH/I_OL) current for a group of pins. Perma-

nent damage can occur if this value is exceeded. To understand

this specification, if pins PH4, PH3, PH2, PH1, and PH0 from

group 1 in the Total Current Pin Groups table, each were sourc-

ing or sinking 2 mA each, the total current for those pins would

be 10 mA. This would allow up to 70 mA total that could be

sourced or sunk by the remaining pins in the group without

damaging the device. For a list of all groups and their pins, see

the Total Current Pin Groups table. Note that the V_OLand V_OL

specifications have separate per-pin maximum current require-

ments, see the Electrical Characteristics For ADSP-

External (I/O) Supply Voltage

(V_DDEXT/V_DDMEM

Input Voltage^{1, 2}

Input Voltage^{1, 2, 3}

Input Voltage^{1, 2, 4}

Output Voltage Swing

)

–0.5 V to +3.6 V

–0.5 V to +5.5 V

–0.5 V to +5.25 V

–0.5 V to

V_DDEXT/V_DDMEM+0.5 V

Load Capacitance⁵

200 pF

I_OH/I_OLCurrent per Pin Group⁶

Storage Temperature Range

Junction Temperature Underbias

80 mA (max)

–65°C to +150°C

+110°C

BF522/524/526 Processors and Electrical Characteristics For

ADSP-BF523/525/527 Processors tables.

¹Applies to 100% transient duty cycle. For other duty cycles see Table 26.

²Applies only when V_DDEXTis within specifications. When V_DDEXTis outside speci-

fications, the range is V_DDEXT0.2 Volts.

Table 28. Total Current Pin Groups

Group Pins in Group

³Applies to balls SCL and SDA.

⁴Applies to balls USB_DP, USB_DM, and USB_VBUS.

1

PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13

PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7

PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1

PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9

PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1

BMODE0, PG3, PG2, PG1, PG0, TDI, TDO, EMU,

TCK, TRST, TMS,

⁵For proper SDRAM controller operation, the maximum load capacitance is 50 pF

(at 3.3 V) or 30 pF (at 2.5 V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0,

CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.

2

3

⁶For more information, see description preceeding Table 28.

4

5

Table 26. Maximum Duty Cycle for Input Transient Voltage¹

6

V_INMin (V)

TBD

V_INMax (V)

TBD

Maximum Duty Cycle

7

100 %

40%

25%

15%

10%

8

DATA15, DATA14, DATA13, DATA12, DATA11, DATA10

DATA9, DATA8, DATA7, DATA6, DATA5, DATA4

DATA3, , DATA2, , DATA1, , DATA0, ADDR19, ADDR18

ADDR17, ADDR16, ADDR15, ADDR14, ADDR13

ADDR12, ADDR11, ADDR10, ADDR9, ADDR8, ADDR7

ADDR6, ADDR5, ADDR4, ADDR3, ADDR2, ADDR1

ABE1, ABE0, SA10, SWE, SCAS, SRAS

9

TBD

10

11

12

13

14

15

16

TBD

¹Applies to all signal balls with the exception of CLKIN, XTAL,

VR_OUT/EXT_WAKE1.

SMS, SCKE, ARDY, AWE, ARE, AOE

AMS3, AMS2, AMS1, AMS0, CLKOUT

When programming OTP memory on the ADSP-

BF522/524/526 processors, the VPPOTP ball must be set to the

write value specified in the Operating Conditions for ADSP-

BF522/524/526 on Page 27. There is a finite amount of cumula-

tive time that the write voltage may be applied (dependent on

voltage and junction temperature) to VPPOTP over the lifetime

of the part. Therefore, maximum OTP memory programming

Rev. PrG

|

Page 36 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary circuitry, damage may occur

on devices subjected to high energy ESD. Therefore,

proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 8 and Table 29 provides

details about the package branding for the ADSP-

BF522/524/526 and ADSP-BF523/525/527 processors. For a

complete listing of product availability, see Ordering Guide on

Page 80.

a

ADSP-BF52x

tppZccc

vvvvvv.x n.n

yyww country_of_origin

B

Figure 8. Product Information on Package

Table 29. Package Brand Information

Brand Key

Field Description

Product Name¹

ADSP-BF52x

t

Temperature Range

Package Type

pp

Z

RoHS Compliant Designation

See Ordering Guide

Assembly Lot Code

Silicon Revision

ccc

vvvvvv.x

n.n

yyww

Date Code

¹See product names in the Ordering Guide on Page 80.

Rev. PrG

|

Page 37 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

TIMING SPECIFICATIONS

Clock and Reset Timing

Table 30 and Figure 9 describe clock and reset operations. Per

the CCLK and SCLK timing specifications in Table 12 to

Table 17, combinations of CLKIN and clock multipliers must

not select core/peripheral clocks in excess of the processor's

speed grade.

Table 30. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CKIN

CLKIN Period

20.0

10.0

100.0

ns

t_CKINL

t_CKINH

t_WRST

CLKIN Low Pulse¹

CLKIN High Pulse¹

RESET Asserted Pulse Width Low²

10.0

11 × t_CKIN

Switching Characteristic

t_BUFDLAY

CLKIN to CLKBUF Delay

10

ns

¹Applies to bypass mode and non-bypass mode.

²Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

t_CKIN

CLKIN

t_CKINL

t_CKINH

t_BUFDLAY

CLKBUF

t_WRST

RESET

Figure 9. Clock and Reset Timing

Rev. PrG

|

Page 38 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Asynchronous Memory Read Cycle Timing

Table 31. Asynchronous Memory Read Cycle Timing

V

_DDMEM= 1.8 V

V_DDMEM= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SDAT

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

2.1

0.9

4.0

0.2

2.1

0.8

4.0

0.2

ns

t_HDAT

t_SARDY

t_HARDY

Switching Characteristics

t_DO

Output Delay After CLKOUT¹

Output Hold After CLKOUT ¹

6.0

ns

t_HO

0.8

¹Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

3 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

ABE, ADDRESS

ADDR19–1

AOE

t_DO

t_HO

ARE

t_HARDY

t_SARDY

t_HARDY

ARDY

t_SARDY

t_SDAT

t_HDAT

DATA15–0

READ

Figure 10. Asynchronous Memory Read Cycle Timing

Rev. PrG

|

Page 39 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Asynchronous Memory Write Cycle Timing

Table 32. Asynchronous Memory Write Cycle Timing

V

_DDMEM= 1.8 V

V_DDMEM= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

4.0

0.2

4.0

0.2

ns

Switching Characteristics

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT ¹

0.0

0.8

0.0

0.8

t_HO

¹Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

ACCESS

EXTENDED

1 CYCLE

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

ABE, ADDRESS

ADDR19–1

t_DO

t_HO

AWE

t_HARDY

t_SARDY

ARDY

t_SARDY

t_ENDAT

t_DDAT

DATA15–0

WRITE DATA

Figure 11. Asynchronous Memory Write Cycle Timing

Rev. PrG

|

Page 40 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

NAND Flash Controller Interface Timing

Table 33 and Figure 12 on Page 41 through Figure 16 on

Page 43 describe NAND Flash Controller Interface operations.

Table 33. NAND Flash Controller Interface Timing

Parameter

Min

Max

Unit

Write Cycle

Switching Characteristics

t_CWL

t_CH

t_CLEWL

t_CLH

t_ALEWL

ND_CE Setup Time to AWE Low

ND_CE Hold Time From AWE High

ND_CLE Setup Time to AWE Low

ND_CLE Hold Time From AWE high

ND_ALE Setup Time to AWE Low

ND_ALE Hold Time From AWE High

AWE Low to AWE high

AWE High to AWE Low

AWE Low to AWE Low

Data Setup Time for a Write Access

Data Hold Time for a Write Access

1.0 × t_SCLK– 4

3.0 × t_SCLK– 4

ns

0.0

2.5 × t_SCLK– 4

0.0

t_ALH

2.5 × t_SCLK– 4

(WR_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

(WR_DLY +5.0) × t_SCLK– 4

(WR_DLY +1.5) × t_SCLK– 4

2.5 × t_SCLK– 4

1

t_WP

t_WHWL

1

t_WC

1

t_DWS

t_DWH

Read Cycle

Switching Characteristics

t_CRL

t_CRH

t_RP

ND_CE Setup Time to ARE Low

ND_CE Hold Time From ARE High

ARE Low to ARE High

ARE High to ARE Low

ARE Low to ARE Low

1.0 × t_SCLK– 4

3.0 × t_SCLK– 4

(RD_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

ns

1

t_RHRL

1

t_RC

(RD_DLY +5.0) × t_SCLK– 4

Timing Requirements

t_DRS

t_DRH

Data Setup Time for a Read Transaction

Data Hold Time for a Read Transaction

8.0²

0.0

ns

Write Followed by Read

Switching Characteristics

t_WHRL

AWE High to ARE Low

5.0 × t_SCLK– 4

ns

¹WR_DLY and RD_DLY are defined in the NFC_CTL register.

²The only parameter that differs from 1.8V to 2.5/3.3V operation is t_DRS, which is 8.0ns at 2.5/3.3V and is 11ns at 1.8V.

t

CH

CWL

ND_CE

ND_CLE

t

CLH

t

CLEWL

t

ALH

ALEWL

ND_ALE

AWE

t

WP

t

DWH

t

DWS

ND_D -D

0

7

Figure 12. NAND Flash Controller Interface Timing - Command Write Cycle

Rev. PrG

|

Page 41 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

t

CWL

ND_CE

t

CLEWL

ALEWL

ND_CLE

ND_ALE

t

ALH

ALEWL

t

WP

t

WHWL

AWE

t

WC

t

DWH

DWS

DWH

DWS

ND_D -D

0

7

Figure 13. NAND Flash Controller Interface Timing - Address Write Cycle

t

CWL

ND_CE

t

CLEWL

ND_CLE

ALEWL

ND_ALE

t

WP

t

WHWL

AWE

t

WC

ARE

t

DWS

DWH

DWS

DWH

ND_D -D

0

7

Figure 14. NAND Flash Controller Interface Timing - Data Write Operation

Rev. PrG

|

Page 42 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

t

CRH

CRL

ND_CE

ND_CLE

ND_ALE

AWE

t

RC

t

RP

t

RHRL

ARE

t

DRS

DRH

DRS

DRH

ND_D -D

0

7

Figure 15. NAND Flash Controller Interface Timing - Data Read Operation

t

CWL

ND_CE

ND_CLE

ND_ALE

t

CLH

CLEWL

t

WP

AWE

t

RP

t

WHRL

ARE

t

DWH

DWS

DWH

DRS

ND_D -D

0

7

Figure 16. NAND Flash Controller Interface Timing - Write Followed by Read Operation

Rev. PrG

|

Page 43 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

SDRAM Interface Timing

Table 34. SDRAM Interface Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDMEM

1.8 V

=

V_DDMEM

2.5/3.3 V

=

V_DDMEM

1.8 V

=

V_DDMEM

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Timing Requirements

t_SSDAT

t_HSDAT

Data Setup Before CLKOUT

Data Hold After CLKOUT

1.5

0.8

1.5

0.8

1.5

1.0

1.5

0.8

ns

Switching Characteristics

t_SCLK

CLKOUT Period¹

12.5

2.5

12.5

2.5

10

2.5

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

CLKOUT Width High

CLKOUT Width Low

2.5

ns

Command, Address, Data Delay After CLKOUT²

Command, Address, Data Hold After CLKOUT²

Data Disable After CLKOUT

4.4

5.0

4.4

5.0

4.0

5.0

4.0 ns

ns

1.0

0.0

1.0

0.0

1.0

0.0

1.0

0.0

4.0 ns

ns

Data Enable After CLKOUT

¹The t_SCLKvalue is the inverse of the f_SCLKspecification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.

²Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

t_SCLK

t_SCLKH

CLKOUT

t_SSDAT

t_SCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA (OUT)

t_DCAD

COMMAND, ADDRESS

(OUT)

t_HCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 17. SDRAM Interface Timing

Rev. PrG

|

Page 44 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

External DMA Request Timing

Table 35 and Figure 18 describe the External DMA Request

operations.

Table 35. External DMA Request Timing

V_DDEXT/V_DDMEM= 1.8 V¹

V_DDEXT/V_DDMEM= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Parameters

t_DR

DMARx Asserted to CLKOUT High Setup

CLKOUT High to DMARx Deasserted Hold Time

DMARx Active Pulse Width

8.0

0.0

6.0

0.0

ns

t_DH

t_DMARACT

t_DMARINACT

1.0 × t_SCLK

1.75 × t_SCLK

1.0 × t_SCLK

1.75 × t_SCLK

DMARx Inactive Pulse Width

¹Because the external DMA control pins are part of the V_DDEXTpower domain and the CLKOUT signal is part of the V_DDMEMpower domain, systems in which V_DDEXTand

V

_DDMEMare NOT equal may require level shifting logic for correct operation.

CLKOUT

t_DR

t_DH

DMAR0/1

(Active Low)

t_DMARACT

t_DMARINACT

DMAR0/1

(Active High)

t_DMARACT

t_DMARINACT

Figure 18. External DMA Request Timing

Rev. PrG

|

Page 45 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Parallel Peripheral Interface Timing

Table 36 and Figure 19 on Page 46, Figure 23 on Page 50, and

Figure 25 on Page 51 describe parallel peripheral interface

operations.

Table 36. Parallel Peripheral Interface Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Timing Requirements

t_PCLKW

t_PCLK

PPI_CLK Width¹

PPI_CLK Period¹

6.4

6.0

ns

25.0

15.0

Timing Requirements - GP Input and Frame Capture Modes

t_SFSPE

External Frame Sync Setup Before PPI_CLK

6.7

ns

(Nonsampling Edge for Rx, Sampling Edge for Tx)

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Hold After PPI_CLK

Receive Data Setup Before PPI_CLK

Receive Data Hold After PPI_CLK

1.0

3.5

1.5

1.0

3.5

1.5

1.0

3.5

1.6

1.0

3.5

1.5

ns

Switching Characteristics - GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

8.8

8.0

8.0 ns

ns

1.7

1.8

1.7

1.8

1.7

1.8

1.7

1.8

8.0 ns

ns

¹PPI_CLK frequency cannot exceed f_SCLK/2

DATA1 IS

DATA0 IS

SAMPLED

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

SDRPE

HDRPE

PPI_DATA

Figure 19. PPI GP Rx Mode with External Frame Sync Timing

Rev. PrG

|

Page 46 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

DATA

DRIVING/

FRAME

SYNC

DRIVING/

FRAME

SYNC

SAMPLING

EDGE

SAMPLING

EDGE

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

t

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

DDTPE

t

HDTPE

PPI_DATA

Figure 20. PPI GP Tx Mode with External Frame Sync Timing

FRAME

DATA0

IS

SAMPLED

SYNC IS

DRIVEN

OUT

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

POLS = 0

PPI_FS1

PPI_FS2

POLS = 1

POLS = 0

t

SDRPE

HDRPE

PPI_DATA

Figure 21. PPI GP Rx Mode with Internal Frame Sync Timing

Rev. PrG

|

Page 47 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

FRAME

SYNC IS

DRIVEN

OUT

DATA0 IS

DRIVEN

OUT

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

POLS = 0

PPI_FS1

PPI_FS2

POLS = 1

POLS = 0

t

DDTPE

t

HDTPE

PPI_DATA

DATA0

Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing

Rev. PrG

|

Page 48 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Serial Ports

Table 37 through Table 40 on Page 51 and Figure 23 on Page 50

through Figure 25 on Page 51 describe serial port operations.

Table 37. Serial Ports—External Clock

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Timing Requirements

t_SFSE

TFSx/RFSx Setup Before TSCLKx/RSCLKx¹

TFSx/RFSx Hold After TSCLKx/RSCLKx¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

TSCLKx/RSCLKx Width

3.0

ns

t_HFSE

t_SDRE

t_HDRE

t_SCLKEW

t_SCLKE

3.0

3.6

3.5

3.0

5.4

7.0

4.5

TSCLKx/RSCLKx Period

18.0

20.0

15.0

Switching Characteristics

t_DFSE

TFSx/RFSx Delay After TSCLKx/RSCLKx

12.0

10.0

10.0 ns

ns

(Internally Generated TFSx/RFSx)²

t_HOFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx

0.0

(Internally Generated TFSx/RFSx)¹

t_DDTE

t_HDTE

Transmit Data Delay After TSCLKx¹

Transmit Data Hold After TSCLKx¹

10.0 ns

ns

¹Referenced to sample edge.

²Referenced to drive edge.

Table 38. Serial Ports—Internal Clock

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFSx/RFSx Setup Before TSCLKx/RSCLKx¹

11.3

–1.5

11.3

–1.5

11.3

–1.5

11.3

–1.5

11.0

–1.5

11.0

–1.5

9.6

–1.5

9.6

ns

TFSx/RFSx Hold After TSCLKx/RSCLKx¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

–1.5

Switching Characteristics

t_SCLKIW

t_SCLKI

t_DFSI

TSCLKx/RSCLKx Width

5.4

4.5

ns

TSCLKx/RSCLKx Period

18.0

20.0

15.0

TFSx/RFSx Delay After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)²

3.0

3.0 ns

t_HOFSI

TFSx/RFSx Hold After TSCLKx/RSCLKx

(Internally Generated TFSx/RFSx)¹

Transmit Data Delay After TSCLKx¹

Transmit Data Hold After TSCLKx¹

−4.0

−1.8

−4.0

−1.8

−1.0

−1.8

−1.0

−1.5

ns

t_DDTI

t_HDTI

3.0 ns

ns

¹Referenced to sample edge.

²Referenced to drive edge.

Rev. PrG

|

Page 49 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

RSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

RFSx

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DRx

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

TSCLKx

TFSx

TSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

TFSx

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DTx

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RSCLKx OR TSCLKx CAN BE USED AS THE ACTIVE SAMPLING EDGE.

Figure 23. Serial Ports

Table 39. Serial Ports—Enable and Three-State

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min

0.0

Max

Min

Max

Min

0.0

Max

Min

Max Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TSCLKx¹

0.0

ns

t_SCLK+1 ns

ns

Data Disable Delay from External TSCLKx¹

Data Enable Delay from Internal TSCLKx¹

Data Disable Delay from Internal TSCLKx¹

10.0

3.0

10.0

3.0

t_SCLK+1

–2.0

t_SCLK+1 ns

¹Referenced to drive edge.

DRIVE

TSCLKx

t_DTENE/I

t_DDTTE/I

DTx

Figure 24. Serial Ports — Enable and Three-State

Rev. PrG

|

Page 50 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 40. Serial Ports — External Late Frame Sync

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External TFSx

10.0

12.0

10.0 ns

ns

or External RFSx in multi-channel mode with MFD = 0^{1, 2}

t_DTENLFSE

Data Enable from External RFSx in multi-channel mode 0.0

with MFD = 0^{1, 2}

0.0

¹When in multi-channel mode, TFSx enable and TFSx valid follow t_DTENLFSEand t_DDTLFSE

.

²If external RFSx/TFSx setup to RSCLKx/TSCLKx > t_SCLKE/2 then t_DDTTE/Iand t_DTENE/Iapply, otherwise t_DDTLFSEand t_DTENLFSEapply.

EXTERNAL RFSx IN MULTI-CHANNEL MODE WITH MCE = 1

DRIVE

SAMPLE

DRIVE

RSCLKx

RFSx

t_SFSE/I

t_HOFSE/I

t_DTENLFSE

1ST BIT

DTx

t_DDTLFSE

LATE EXTERNAL TFSx

DRIVE

SAMPLE

DRIVE

TSCLKx

TFSx

t_HOFSE/I

t_SFSE/I

DTx

1ST BIT

t_DDTLFSE

Figure 25. Serial Ports — External Late Frame Sync

Rev. PrG

|

Page 51 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Serial Peripheral Interface (SPI) Port—Master Timing

Table 41 and Figure 26 describe SPI port master operations.

Table 41. Serial Peripheral Interface (SPI) Port—Master Timing

ADSP-BF522/524/526

V_DDEXT= 1.8 V V_DDEXT= 2.5/3.3 V

ADSP-BF523/525/527

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Min

Max

Min

Max Unit

Timing Requirements

t_SSPIDM

Data Input Valid to SCK Edge (Data

Input Setup)

11.6

–1.5

11.6

–1.5

11.6

–1.5

9.6

ns

t_HSPIDMSCK Sampling Edge to Data Input

Invalid

–1.5

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

SPISELx low to First SCK Edge

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCK Edge to SPISELx High

Sequential Transfer Delay

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

4 × t_SCLK–1.5

2 × t_SCLK–1.5

ns

t_SPITDM

t_DDSPIDMSCK Edge to Data Out Valid (Data

Out Delay)

6

t_HDSPIDMSCK Edge to Data Out Invalid (Data

Out Hold)

–1.0

ns

SPISELx

(OUTPUT)

t_SPICLK

t_HDSM

t_SPITDM

t_SDSCIM

t_SPICHM

t_SPICLM

SCK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCK

(CPOL = 1)

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

CPHA = 1

t_SSPIDM

t_HSPIDM

MISO

(INPUT)

MSB VALID

LSB VALID

t_HDSPIDM

t_DDSPIDM

MOSI

(OUTPUT)

MSB

LSB

CPHA = 0

t_SSPIDM

t_HSPIDM

MISO

(INPUT)

MSB VALID

LSB VALID

Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. PrG

|

Page 52 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 42 and Figure 27 describe SPI port slave operations.

Table 42. Serial Peripheral Interface (SPI) Port—Slave Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT= 1.8 V V_DDEXT= 2.5/3.3 V

Min Max Unit

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Timing Requirements

Min

Max

Min

Max

Min

Max

t_SPICHS

t_SPICLS

t_SPICLK

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

2 × t_SCLK–1.5

ns

4 ×

t_SCLK–1.5

t_HDS

Last SCK Edge to SPISS Not Asserted

Sequential Transfer Delay

SPISS Assertion to First SCK Edge

Data Input Valid to SCK Edge (Data Input

Setup)

2 × t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

2 × t_SCLK–1.5

1.6

ns

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SCK Sampling Edge to Data Input Invalid

1.6

ns

Switching Characteristics

t_DSOE

SPISS Assertion to Data Out Active

SPISS Deassertion to Data High Impedance

SCKEdgeto DataOutValid(Data OutDelay)

SCK Edge to Data Out Invalid (Data Out

Hold)

0

12.0

8.5

10

0

12.0

8.5

10

0

12.0

8.5

10

0

10.3 ns

t_DSDHI

t_DDSPID

t_HDSPID

8

ns

10 ns

ns

0

SPISS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCKx

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

SCKx

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

t_DDSPID

t_DSDHI

MISOx

(OUTPUT)

MSB

LSB

CPHA = 1

t_SSPID

t_HSPID

MOSIx

(INPUT)

MSB VALID

LSB VALID

t_DSOE

t_HDSPID

t_DSDHI

t_DDSPID

MISOx

(OUTPUT)

MSB

LSB

t_HSPID

CPHA = 0

t_SSPID

MOSIx

(INPUT)

MSB VALID

LSB VALID

Figure 27. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. PrG

|

Page 53 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing

Table 43 describes the USB On-The-Go receive and transmit

operations.

Table 43. USB On-The-Go—Receive and Transmit Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT= 1.8 V V_DDEXT

2.5/3.3 V

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Min Max Min Max Min Max Min Max Unit

Timing Requirements

f_USBS

USB_XI Frequency

9

33.3

50

9

33.3

50

9

33.3

50

9

33.3 MHz

50 ppm

FS_USB

USB_XI Clock Frequency Stability

–50

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

Figure 28 describes the UART ports receive and transmit opera-

tions. The maximum baud rate is SCLK/16. There is some

latency between the generation of internal UART interrupts

and the external data operations. These latencies are negligible

at the data transmission rates for the UART.

CLKOUT

(SAMPLE

CLOCK)

UARTx Rx

RECEIVE

DATA(5-8)

STOP

INTERNAL

UARTRECEIVE

INTERRUPT

UARTRECEIVE BIT SET BY

DATA STOP ;

CLEARED BY FIFO READ

START

UARTx Tx

STOP(1-2)

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SETBY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 28. UART Ports—Receive and Transmit Timing

Rev. PrG

|

Page 54 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

General-Purpose Port Timing

Table 44 and Figure 29 describe general-purpose

port operations.

Table 44. General-Purpose Port Timing

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter

Timing Requirement

t_WFI

Switching Characteristics

t_GPODGeneral-Purpose Port Ball Output Delay from

CLKOUT Low

Min

Max

Min

t_SCLK+ 1

0

Max

Min

t_SCLK+ 1

0

Max

Min

t_SCLK+ 1

0

Max Unit

ns

General-Purpose Port Ball Input Pulse Width t_SCLK+ 1

0

9.66

8.2

6.5 ns

CLKOUT

t_GPOD

GPIO OUTPUT

GPIO INPUT

t_WFI

Figure 29. General-Purpose Port Timing

Rev. PrG

|

Page 55 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Timer Cycle Timing

Table 45 and Figure 30 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (f_SCLK/2) MHz.

Table 45. Timer Cycle Timing

ADSP-BF522/524/526

_DDEXT= 1.8 V V_DDEXT= 2.5/3.3 V

ADSP-BF523/525/527

V

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Min

Max

Min

Max Unit

Timing Characteristics

t_WL

Timer Pulse Width Input

t_SCLK

ns

Low (Measured In SCLK

Cycles)¹

t_WH

Timer Pulse Width Input

High (Measured In SCLK

Cycles)¹

t_SCLK

t_TIS

t_TIH

Timer Input Setup Time

Before CLKOUT Low²

5

8.1

–2

6.2

–2

ns

Timer Input Hold Time

After CLKOUT Low²

–2

Switching Characteristics

t_HTOTimer Pulse Width Output

t_SCLK

(2³²–1)t_SCLK

8.1

t_SCLK

(2³²–1)t_SCLKt_SCLK–1 (2³²–1)t_SCLKt_SCLK–1 (2³²–1)t_SCLKns

8.1 ns

(Measured In SCLK Cycles)

t_TOD

Timer Output Update

6

Delay After CLKOUT High

¹The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.

²Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT

t_TOD

TMRX OUTPUT

t_HTO

t_TIS

t_TIH

TMRx INPUT

t_WH,t_WL

Figure 30. Timer Cycle Timing

Rev. PrG

|

Page 56 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Timer Clock Timing

Table 46 and Figure 31 describe timer clock timing.

Table 46. Timer Clock Timing

V

_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Unit

Switching Characteristic

t_TODP

Timer Output Update Delay After PPI_CLK High

12.0

ns

PPI_CLK

t_TODP

TMRx OUTPUT

Figure 31. Timer Clock Timing

Up/Down Counter/Rotary Encoder Timing

Table 47. Up/Down Counter/Rotary Encoder Timing

V_DDEXT= 1.8 V

Min Max

V_DDEXT= 2.5/3.3 V

Parameter

Min

Max

Unit

Timing Requirements

t_WCOUNT

t_CIS

Up/Down Counter/Rotary Encoder Input Pulse Width

t_SCLK+ 1

4.0

t_SCLK+ 1

4.0

ns

Counter Input Setup Time Before CLKOUT Low¹

t_CIH

Counter Input Hold Time After CLKOUT Low1

4.0

¹Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

CLKOUT

t_CIS

t_CIH

CUD/CDG/CZM

t_WCOUNT

Figure 32. Up/Down Counter/Rotary Encoder Timing

Rev. PrG

|

Page 57 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

HOSTDP A/C Timing- Host Read Cycle

Table 48 describe the HOSTDP A/C Host Read Cycle timing

requirements.

Table 48. Host Read Cycle Timing Requirements

ADSP-BF522/524/526,

V_DDEXT= 1.8 V V_DDEXT= 2.5/3.3 V

ADSP-BF523/525/527

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Timing Requirements

Min

Max

Min

Max

Min

Max

Min

4

Max Unit

t_SADRDL

HOST_ADDR and HOST_CE Setup

before HOST_RD falling edge

4

ns

t_HADRDHHOST_ADDR and HOST_CE Hold

after HOST_RD rising edge

2.5

t_RDWL

HOST_RD pulse width low

(ACK mode)

t_DRDYRDL

t_RDYPRD

+

t_DRDYRDL

t_RDYPRD

+

t_DRDYRDL

t_RDYPRD

+

t_DRDYRDL

t_RDYPRD+

+

t_DRDHRDY

1.5 × t_SCLK

+ 8.7

t_DRDHRDY

1.5 × t_SCLK

+ 8.7

t_DRDHRDY

1.5 × t_SCLK

+ 8.7

t_DRDHRDY

1.5 × t_SCLK

+ 8.7

t_RDWL

t_RDWH

HOST_RD pulse width low

(INT mode)

ns

HOST_RD pulse width high or time 2 × t_SCLK

between HOST_RD rising edge and

HOST_WR falling edge

2 × t_SCLK

t_DRDHRDYHOST_RD rising edge delay after

HOST_ACK rising edge (ACK mode)

Switching Characteristics

0

ns

t_SDATRDYData valid prior HOST_ACK rising

edge (ACK mode)

t_DRDYRDLHost_ACK assertion delay after

HOST_RD/HOST_CE (ACK mode)

4.5

3.5

4.5

3.5

ns

1.5 × t_SCLKns

NM¹ns

1.5 × t_SCLK

t_RDYPRD

HOST_ACK low pulse-width for

Read access (ACK mode)

NM¹

t_DDARWHData disable after HOST_RD

9.0

ns

t_ACC

Data valid after HOST_RD falling

edge (INT mode)

1.5 × t_SCLK

1.5 × t_SCLKns

t_HDARWHData hold after HOST_RD rising

edge

1.0

ns

¹NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.

HOST_ADDR

HOST_CE

t_SADRDL

t_HADRDH

t_RDWH

t_RDWL

HOST_RD

t_RDYPRD

HOST_ACK

t_DRDYRDL

t_DRDHRDY

t_SDATRDY

t_DDARWH

t_HDARWH

HOST_D15-0

t_ACC

Figure 33. HOSTDP A/C- Host Read Cycle

Rev. PrG

|

Page 58 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

HOSTDP A/C Timing- Host Write Cycle

Table 49 describes the HOSTDP A/C Host Write Cycle timing

requirements.

Table 49. Host Write Cycle Timing Requirements

ADSP-BF522/524/526

V_DDEXT= 1.8 V V_DDEXT= 2.5/3.3 V

ADSP-BF523/525/527

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Timing Requirements

t_SADWRLHOST_ADDR/HOST_CE Setup

before HOST_WR falling edge

t_HADWRHHOST_ADDR/HOST_CE Hold

after HOST_WR rising edge

Min

Max

Min

Max

Min

Max

Min

4

Max Unit

4

ns

2.5

t_WRWL

HOST_WR pulse width low

(ACK mode)

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL

t_RDYPRD

+

t_DRDYWRL+

t_RDYPRD+

t_DWRHRDY

1.5 × t_SCLK

+ 8.7

t_DWRHRDY

1.5 × t_SCLK

+ 8.7

t_DWRHRDY

1.5 × t_SCLK

+ 8.7

t_DWRHRDY

1.5 × t_SCLK

+ 8.7

HOST_WR pulse width low

(INT mode)

HOST_WR pulse width high

or time between HOST_WR

rising edge and HOST_RD

falling edge

ns

t_WRWH

2 × t_SCLK

t_DWRHRDYHOST_WR rising edge delay

after HOST_ACK rising edge

(ACK mode)

0

ns

t_HDATWHData Hold after HOST_WR

rising edge

t_SDATWHData Setup before HOST_WR

rising edge

2.5

ns

Switching Characteristics

t_DRDYWRLHOST_ACK low delay after

HOST_WR/HOST_CE asserted

(ACK mode)

t_RDYPWRHOST_ACK low pulse-width for

Write access (ACK mode)

1.5 × t_SCLK

1.5 × t_SCLKns

NM¹

NM¹ns

¹NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.

HOST_ADDR

HOST_CE

t_SADWRL

t_HADWRH

t_WRWH

t_WRWL

HOST_WR

t_RDYPWR

HOST_ACK

t_DRDYWRL

t_DWRHRDY

t_SDATWH

t_HDATWH

HOST_D15-0

Figure 34. HOSTDP A/C- Host Write Cycle

Rev. PrG

|

Page 59 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

10/100 Ethernet MAC Controller Timing

Table 50 through Table 55 and Figure 35 through Figure 40

describe the 10/100 Ethernet MAC Controller operations.

Table 50. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter¹

Min

Max

Min

Max

Unit

t_ERXCLKF

ERxCLK Frequency (f_SCLK= SCLK Frequency)

None

25 + 1%

None

25 + 1%

MHz

f_SCLK+ 1%

t_ERXCLKW

t_ERXCLKIS

t_ERXCLKIH

ERxCLK Width (t_ERxCLK= ERxCLK Period)

Rx Input Valid to ERxCLK Rising Edge (Data In Setup)

ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)

t_ERxCLKx 40% t_ERxCLKx 60% t_ERxCLKx 35% t_ERxCLKx 65% ns

7.5

ns

¹MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.

Table 51. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter¹

Min

Max

Min

Max

Unit

t_ETXCLKF

ETxCLK Frequency (f_SCLK= SCLK Frequency)

None

25 + 1%

None

25 + 1%

MHz

f_SCLK+ 1%

t_ETXCLKW

t_ETXCLKOV

t_ETXCLKOH

ETxCLK Width (t_ETxCLK= ETxCLK Period)

ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)

ETxCLK Rising Edge to Tx Output Invalid (Data Out

Hold)

t_ETxCLKx 40% t_ETxCLKx 60% t_ETxCLKx 35% t_ETxCLKx 65% ns

20

ns

0

¹MII outputs synchronous to ETxCLK are ETxD3–0.

Table 52. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

V_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter¹

Min

Max

Min

Max

Unit

t_EREFCLKF

REF_CLK Frequency (f_SCLK= SCLK Frequency)

EREF_CLK Width (t_EREFCLK= EREFCLK Period)

Rx Input Valid to RMII REF_CLK Rising Edge (Data In

Setup)

None

50 + 1%

2 x f_SCLK+ 1%

None

50 + 1%

2 x f_SCLK+ 1%

MHz

t_EREFCLKW

t_EREFCLKIS

t_EREFCLKx 40% t_EREFCLKx 60% t_EREFCLKx 35% t_EREFCLKx 65% ns

4

ns

t_EREFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In

Hold)

2

ns

¹RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.

Table 53. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter¹

Min Max Min Max Min Max Min Max Unit

t_EREFCLKOV

RMII REF_CLK Rising Edge

8.1

7.5

7.5 ns

to Tx Output Valid (Data Out Valid)

t_EREFCLKOH

RMII REF_CLK Rising Edge

2

ns

to Tx Output Invalid (Data Out Hold)

¹RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

Rev. PrG

|

Page 60 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 54. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal

V_DDEXT= 1.8 V

Min Max

V_DDEXT= 2.5/3.3 V

Parameter^{1, 2}

Min

Max

Unit

t_ECOLH

COL Pulse Width High

t_ETxCLKx 1.5

t_ERxCLKx 1.5

t_ETxCLKx 1.5

t_ERxCLKx 1.5

ns

t_ECOLL

COL Pulse Width Low

t_ETxCLKx 1.5

t_ERxCLKx 1.5

t

_ETxCLKx 1.5

ns

t_ERxCLKx 1.5

t_ETxCLKx 1.5

t_ECRSH

t_ECRSL

CRS Pulse Width High

CRS Pulse Width Low

t_ETxCLKx 1.5

ns

¹MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to

both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.

²The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.

Table 55. 10/100 Ethernet MAC Controller Timing: MII Station Management

ADSP-BF522/524/526

ADSP-BF523/525/527

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

V_DDEXT

1.8 V

=

V_DDEXT

2.5/3.3 V

=

Parameter¹

t_MDIOS

Min Max Min Max Min Max Min Max Unit

MDIO Input Valid to MDC Rising Edge (Setup)

MDC Rising Edge to MDIO Input Invalid (Hold)

MDC Falling Edge to MDIO Output Valid

11.5

25

11.5

25

10

25

–1

10

25

–1

ns

t_MDCIH

t_MDCOV

t_MDCOH

MDC Falling Edge to MDIO Output Invalid (Hold)

–1

¹MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple

of the system clock SCLK. MDIO is a bidirectional data line.

t_ERXCLK

ERx_CLK

t_ERXCLKW

ERxD3-0

ERxDV

ERxER

t_ERXCLKIS

t_ERXCLKIH

Figure 35. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

t_ETXCLK

MII TxCLK

t_ETXCLKW

t_ETXCLKOH

ETxD3-0

ETxEN

t_ETXCLKOV

Figure 36. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Rev. PrG

|

Page 61 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

t_REFCLK

RMII _REF_CLK

t_REFCLKW

ERxD1-0

ERxDV

ERxER

t_REFCLKIS

t_REFCLKIH

Figure 37. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

t_REFCLK

RMII _REF_CLK

t_REFCLKOH

ETxD1-0

ETxEN

t_REFCLKOV

Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

MII CRS, COL

t_ECRSH

t_ECOLH

t_ECRSL

t_ECOLL

Figure 39. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal

MDC (OUTPUT)

MDIO (OUTPUT)

t_MDCOH

t_MDCOV

MDIO (INPUT)

t_MDIOSt_MDCIH

Figure 40. 10/100 Ethernet MAC Controller Timing: MII Station Management

Rev. PrG

|

Page 62 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

JTAG Test And Emulation Port Timing

Table 56 and Figure 41 describe JTAG port operations.

Table 56. JTAG Port Timing

V

_DDEXT= 1.8 V

V_DDEXT= 2.5/3.3 V

Parameter

Min

Max

Min

Max

Unit

Timing Parameters

t_TCK

TCK Period

20

4

20

4

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse Width²(measured in TCK cycles)

ns

4

ns

12

5

12

5

ns

4

TCK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

12

10

12

ns

¹System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, TCK, TRST, RESET, NMI, BMODE3–0.

²50 MHz Maximum

³System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0,

TDO, EMU.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 41. JTAG Port Timing

Rev. PrG

|

Page 63 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

OUTPUT DRIVE CURRENTS

Figure 42 through Figure 56 show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF523/525/527

and ADSP-BF522/524/526 processors.

The curves represent the current drive capability of the output

drivers. See Table 10 on Page 22 for information about which

driver type corresponds to a particular ball.

240

200

V_DDEXT= 3.6V @ – 40

°C

V_DDEXT= 3.6V @ – 40

°C

200

160

120

80

160

120

80

V_DDEXT= 3.3V @ 25

°C

V_DDEXT= 3.3V @ 25

°C

V_DDEXT= 3.0V @ 105°C

V

OH

V

OH

40

0

– 40

– 80

– 120

– 160

– 80

V

OL

V

OL

– 120

– 160

– 200

– 240

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 45. Driver Type B Current (3.3V V_DDEXT/V_DDMEM

)

Figure 42. Driver Type A Current (3.3V V_DDEXT/V_DDMEM

)

160

120

80

160

120

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

°

C

°C

V

_DDEXT= 2.25V @ 105°C

V

_DDEXT= 2.25V @ 105°C

80

40

V

OH

V

OH

0

– 40

– 80

– 40

– 80

V

OL

– 120

– 160

– 200

V

OL

– 120

– 160

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 46. Driver Type B Current (2.5V V_DDEXT/V_DDMEM

)

Figure 43. Driver Type A Current (2.5V V_DDEXT/V_DDMEM

)

80

60

80

60

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

_DDEXT= 1.7V @ 105°C

°C

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

_DDEXT= 1.7V @ 105°C

°C

°

C

°

C

V

40

20

40

20

V

OH

V

OH

0

– 20

– 40

– 60

V

OL

– 40

– 60

– 80

– 100

0.5

1.0

SOURCE VOLTAGE (V)

1.5

0.5

1.0

SOURCE VOLTAGE (V)

1.5

Figure 44. Driver Type A Current (1.8V V_DDEXT/V_DDMEM

)

Figure 47. Driver Type B Current (1.8V V_DDEXT/V_DDMEM)

Rev. PrG

|

Page 64 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

100

80

160

120

V_DDEXT= 3.6V @ – 40

V_DDEXT= 3.3V @ 25

_DDEXT= 3.0V @ 105

°

C

V_DDEXT= 3.6V @ – 40

°C

°

C

V_DDEXT= 3.3V @ 25°C

60

40

V

°C

V_DDEXT= 3.0V @ 105°C

80

40

0

V

OH

20

0

– 20

– 40

– 80

V

OL

– 60

– 80

V

OL

– 120

– 160

– 100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 48. Driver Type C Current (3.3V V_DDEXT/V_DDMEM

)

Figure 51. Driver Type D Current (3.3V V_DDEXT/V_DDMEM

)

80

120

100

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

°C

60

40

20

°C

80

60

V

_DDEXT= 2.25V @ 105°C

V

_DDEXT= 2.25V @ 105°C

40

V

OH

V

20

OH

0

– 20

– 40

– 60

– 80

– 100

– 120

– 20

– 40

– 60

V

OL

– 80

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 49. Drive Type C Current (2.5V V_DDEXT/V_DDMEM

)

Figure 52. Driver Type D Current (2.5V V_DDEXT/V_DDMEM

)

40

30

60

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

_DDEXT= 1.7V @ 105°C

°C

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

°C

°

C

°

C

40

20

V

V_DDEXT= 1.7V @ 105°C

20

10

V

OH

V

OH

0

– 20

– 40

– 60

– 10

V

OL

– 20

– 30

V

OL

– 40

0.5

1.0

SOURCE VOLTAGE (V)

1.5

0.5

1.0

1.5

SOURCE VOLTAGE (V)

Figure 50. Driver Type C Current (1.8V V_DDEXT/V_DDMEM

)

Figure 53. Driver Type D Current (1.8V V_DDEXT/V_DDMEM

)

Rev. PrG

|

Page 65 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

60

V_DDEXT= 3.6V @ – 40

°C

50

V_DDEXT= 3.3V @ 25

°C

40

30

V_DDEXT= 3.0V @ 105°C

20

10

0

– 10

– 20

– 30

– 40

– 50

– 60

V

OL

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 54. Driver Type E Current (3.3V V_DDEXT/V_DDMEM

)

40

30

V_DDEXT= 2.75V @ – 40

V_DDEXT= 2.5V @ 25

_DDEXT= 2.25V @ 105°C

°C

V

20

10

0

–10

– 20

– 30

– 40

V

OL

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 55. Driver Type E Current (2.5V V_DDEXT/V_DDMEM

)

20

15

V_DDEXT= 1.9V @ – 40

V_DDEXT= 1.8V @ 25

_DDEXT= 1.7V @ 105°C

°C

°

C

V

10

5

0

– 5

V

OL

– 10

– 15

– 20

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE VOLTAGE (V)

Figure 56. Driver Type E Current (1.8V V_DDEXT/V_DDMEM

)

Rev. PrG

|

Page 66 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Output Disable Time Measurement

TEST CONDITIONS

Output balls are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t_DISis the

difference between t_{DIS_MEASURED}and t_DECAYas shown on the left

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 57

shows the measurement point for AC measurements (except

output enable/disable). The measurement point V_MEASis

side of Figure 58.

V

_DDEXT/2 or V_DDMEM/2 for V_DDEXT/V_DDMEM(nominal) = 1.8 V/2.5

t_DIS= t_{DIS_MEASURED}– t_DECAY

V/3.3 V.

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load C_Land the load current I_L. This decay

time can be approximated by the equation:

INPUT

OR

OUTPUT

V

MEAS

t_DECAY= (C_LΔV) ⁄ I_L

Figure 57. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

The time t_DECAYis calculated with test loads C_Land I_L, and with

ΔV equal to 0.25 V for V_DDEXT/V_DDMEM(nominal) = 2.5 V/3.3 V

and 0.15 V for V_DDEXT/V_DDMEM(nominal) = 1.8V.

The time t_{DIS_MEASURED}is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Output Enable Time Measurement

Output balls are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time t_ENAis the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 58.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ΔV

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. C_Lis

the total bus capacitance (per data line), and I_Lis the total leak-

age or three-state current (per data line). The hold time will be

t_DECAYplus the various output disable times as specified in the

Timing Specifications on Page 38 (for example t_DSDATfor an

SDRAM write cycle as shown in SDRAM Interface Timing on

Page 44).

REFERENCE

SIGNAL

t_{DIS_MEASURED}

t_{ENA_MEASURED}

t_DIS

V_OH

t_ENA

V_OH(MEASURED)

(MEASURED)

V_OH(MEASURED) ؊ ⌬V

V_OL(MEASURED) + ⌬V

V_TRIP(HIGH)

V_TRIP(LOW)

V_OL

V_OL(MEASURED)

(MEASURED)

t_DECAY

t_TRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 58. Output Enable/Disable

The time t_{ENA_MEASURED}is the interval, from when the reference

signal switches, to when the output voltage reaches V_TRIP(high)

or V_TRIP(low). For V_DDEXT/V_DDMEM(nominal) = 1.8V, V_TRIP

(high) is 1.05V, and V_TRIP(low) is 0.75V. For V_DDEXT/V_DDMEM

(nominal) = 2.5V, V_TRIP(high) is 1.5V and V_TRIP(low) is 1.0V.

For V_DDEXT/V_DDMEM(nominal) = 3.3V, V_TRIP(high) is 1.9V, and

V

_TRIP(low) is 1.4V. Time t_TRIPis the interval from when the out-

put starts driving to when the output reaches the V_TRIP(high) or

V_TRIP(low) trip voltage.

Time t_ENAis calculated as shown in the equation:

t_ENA= t_{ENA_MEASURED}– t_TRIP

If multiple balls (such as the data bus) are enabled, the measure-

ment value is that of the first ball to start driving.

Rev. PrG

|

Page 67 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all balls (see Figure 59). V_LOADis equal

to (V_DDEXT/V_DDMEM) /2. The graphs of Figure 60 through

Figure 71 show how output rise time varies with capacitance.

The delay and hold specifications given should be derated by a

factor derived from these figures. The graphs in these figures

may not be linear outside the ranges shown.

TESTER PIN ELECTRONICS

50:

V

LOAD

T1

DUT

OUTPUT

45:

70:

ZO = 50:ꢀ(impedance)

TD = 4.04 r 1.18 ns

50:

0.5pF

4pF

2pF

400:

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 59. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. PrG

|

Page 68 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

9

12

8

t_RISE

10

8

7

t_RISE

6

t_FALL

5

6

4

2

4

3

2

t_RISE= 1.8V @ 25°C

1

0

t_FALL= 1.8V @ 25

°C

t_FALL= 1.8V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 63. Driver Type B Typical Rise and Fall Times (10%–90%) versus

Figure 60. Driver Type A Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

8

7

6

5

6

5

t_RISE

t_FALL

4

3

t_FALL

4

3

2

1

2

1

t_RISE= 2.5V @ 25°C

t_FALL= 2.5V @ 25

°C

t_FALL= 2.5V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) versus

Figure 64. Driver Type B Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (2.5V V_DDEXT/V_DDMEM

)

6

5

4

5

4

t_RISE

t_FALL

3

2

1

3

2

1

t_RISE= 3.3V @ 25°C

t_FALL= 3.3V @ 25

°C

t_FALL= 3.3V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 62. Driver Type A Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (3.3V V_DDEXT/V_DDMEM

Figure 65. Driver Type B Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (3.3V V_DDEXT/V_DDMEM

)

Rev. PrG

|

Page 69 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

25

14

12

10

8

t_RISE

20

t_RISE

t_FALL

15

t_FALL

6

10

4

2

5

t_RISE= 1.8V @ 25

°C

t_RISE= 1.8V @ 25°C

t_FALL= 1.8V @ 25

°C

t_FALL= 1.8V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 66. Driver Type C Typical Rise and Fall Times (10%–90%) versus

Figure 69. Driver Type D Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (1.8V V_DDEXT/V_DDMEM

)

Load Capacitance (1.8V V_DDEXT/V_DDMEM)

10

9

16

14

8

12

10

7

t_RISE

6

5

t_FALL

8

6

4

2

4

3

2

1

t_RISE= 2.5V @ 25°C

t_FALL= 2.5V @ 25

°C

t_FALL= 2.5V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 70. Driver Type D Typical Rise and Fall Times (10%–90%) versus

Figure 67. Driver Type C Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (2.5V V_DDEXT/V_DDMEM

)

14

8

7

6

5

4

12

10

8

t_RISE

t_FALL

6

3

4

2

1

t_RISE= 3.3V @ 25°C

t_FALL= 3.3V @ 25

°C

t_FALL= 3.3V @ 25

°C

0

50

100

150

200

0

50

100

150

200

LOAD CAPACITANCE (pF)

Figure 68. Driver Type C Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (3.3V V_DDEXT/V_DDMEM

Figure 71. Driver Type D Typical Rise and Fall Times (10%–90%) versus

Load Capacitance (3.3V V_DDEXT/V_DDMEM

)

Rev. PrG

|

Page 70 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 58. Thermal Characteristics (BC-289-2)

ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application

printed circuit board use:

Parameter Condition

Typical Unit

θ_JA

0 linear m/s air flow

34.5

31.1

29.8

20.3

8.8

؇C/W

θ_JMA

θ_JB

1 linear m/s air flow

2 linear m/s air flow

T_J= T_CASE+ (Ψ_JT× P_D)

where:

θ_JC

T_J= Junction temperature (؇C)

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

0.24

0.44

0.53

T

_CASE= Case temperature (؇C) measured by customer at top

center of package.

Ψ_JT= From Table 58

P_D= Power dissipation — For a description, see Total Power

Dissipation on Page 33.

Values of θ_JAare provided for package comparison and printed

circuit board design considerations. θ_JAcan be used for a first

order approximation of T_Jby the equation:

T_J= T_A+ (θ_JA× P_D)

where:

T_A= Ambient temperature (؇C)

Values of θ_JCare provided for package comparison and printed

circuit board design considerations when an external heat sink

is required.

Values of θ_JBare provided for package comparison and printed

circuit board design considerations.

In Table 58, airflow measurements comply with JEDEC stan-

dards JESD51-2 and JESD51-6, and the junction-to-board

measurement complies with JESD51-8. The junction-to-case

measurement complies with MIL-STD-883 (Method 1012.1).

All measurements use a 2S2P JEDEC test board.

Table 57. Thermal Characteristics (BC-208-1)

Parameter Condition

Typical Unit

θ_JA

0 linear m/s air flow

23.20

20.20

19.20

13.05

6.92

؇C/W

θ_JMA

θ_JB

1 linear m/s air flow

2 linear m/s air flow

θ_JC

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

0.18

0.27

0.32

Rev. PrG

|

Page 71 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

289-BALL CSP_BGA BALL ASSIGNMENT

Table 59 lists the CSP_BGA balls by signal mnemonic.

Table 60 on Page 73 lists the CSP_BGA by ball number.

Table 59. 289-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Signal

Ball Signal

No.

Ball Signal Ball Signal Ball Signal

No. No. No.

P1 GND N9 VPPOTP AB11 PH12

Ball Signal Ball Signal

Ball

No.

T7

U7

U8

No.

ABE0/SDQM0 AB9 DATA9

ABE1/SDQM1 AC9 DATA10

M23 V_DDEXT

N22 V_DDEXT

N23 V_DDEXT

P22 V_DDEXT

N17 V_DDMEM

P17 V_DDMEM

R17 V_DDMEM

T17 V_DDMEM

U17 V_DDMEM

B5 V_DDMEM

H8 V_DDMEM

H9 V_DDMEM

H10 V_DDMEM

H11 V_DDMEM

H12 V_DDMEM

H13 V_DDOTP

H14 V_DDRTC

H15 V_DDUSB

H16 V_DDUSB

J8 NC

J16 VR_OUT/EXT_WAKE1 AC18

K8 VR_SEL/V_DDEXT

K16 XTAL

L8

L16

M8

M16

N8

N16

P8

P16

R8

R16

T8

P2 GND N10 PF0

R2 GND N11 PF1

N1 GND N12 PF2

N2 GND N13 PF3

M2 GND N14 PF4

M1 GND N15 PF5

J2 GND P9 PF6

AC19 GND P10 PF7

A1 GND P11 PF8

A23 GND P12 PF9

A7 PH13

B8 PH14

A8 PH15

B9 PPI_CLK/TMRCLK A6 V_DDEXT

B11 PPI_FS1/TMR0 B7 V_DDINT

B10 RESET

B12 RTXI

B13 RTXO

B16 SA10

A20 SCAS

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

AMS1

AMS2

AMS3

AOE

ARDY

ARE

AWE

BMODE0

BMODE1

BMODE2

BMODE3

CLKBUF

CLKIN

CLKOUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

AB8 DATA11

AC8 DATA12

AB7 DATA13

AC7 DATA14

AC6 DATA15

AB6 EMU

AB4 EXT_WAKE0

AB5 GND

AC5 GND

AC4 GND

AB3 GND¹

AC3 GND

AB2 GND¹

AC2 GND

AA2 GND¹

W2 GND

Y2 GND

AA1 GND

AB1 GND

AC17 GND

AB16 GND

AC16 GND

AB15 GND

AC15 GND

AC14 GND

AB17 GND

AB14 GND

G2 GND

F2 GND

E1 GND

E2 GND

AB19 GND

R23 GND

AB18 GND

Y1 GND

V2 GND

W1 GND

U2 GND

V1 GND

U1 GND

T2 GND

T1 GND

R1 GND

U9

U10

U11

U12

U13

U14

U15

U16

AC12

W23

W22

Y23

G23

V22 V_DDINT

U23 V_DDINT

V23 V_DDINT

AC10 V_DDINT

AC11 V_DDINT

AB13 V_DDINT

B22 V_DDINT

C22 V_DDINT

AC13 V_DDINT

AB12 V_DDINT

AC20 V_DDINT

AB10 V_DDINT

L1 V_DDINT

J1 V_DDINT

K1 V_DDINT

L2 V_DDINT

K2 V_DDINT

AB21 V_DDINT

AA22 V_DDINT

Y22 V_DDINT

AC21 V_DDINT

AB20 V_DDINT

AC22 V_DDINT

AB23 V_DDINT

AA23 V_DDINT

G7 V_DDINT

G8 V_DDINT

G9 V_DDINT

G10 V_DDINT

G11 V_DDINT

G12 V_DDINT

G13 V_DDINT

B6 GND P13 PF10 B15 SCKE

G16 GND P14 PF11 B17 SCL

G17 GND P15 PF12 B18 SDA

H17 GND R9 PF13 B19 SMS

H22 GND R10 PF14 A9 SRAS

J22 GND R11 PF15 A10 SS/PG

J9 GND R12 PG0

J10 GND R13 PG1

J11 GND R14 PG2

J12 GND R15 PG3

J13 GND T22 PG4

J14 GND AC1 PG5

J15 GND AC23 PG6

K9 NC A15 PG7

K10 NC A16 PG8

K11 NC A17 PG9

H2 SWE

G1 TCK

H1 TDI

F1 TDO

D1 TMS

D2 TRST

C2 USB_DM

B1 USB_DP

C1 USB_ID

B2 USB_RSET

AB22

P23

K12 NC A18 PG10 B4 USB_VBUS

K13 NC A19 PG11 B3 USB_VREF

K14 NC A21 PG12 A2 USB_XI

K15 NC A22 PG13 A3 USB_XO

L9 NC B20 PG14 A4 V_DDEXT

L10 NC B21 PG15 A5 V_DDEXT

T9

T10

T11

T12

T13

T14

T15

T16

L11 NC B23 PH0

L12 NC C23 PH1

L13 NC D22 PH2

L14 NC D23 PH3

L15 NC E22 PH4

M9 NC E23 PH5

M10 NC F22 PH6

M11 NC F23 PH7

M12 NC G22 PH8

M13 NC H23 PH9

A11 V_DDEXT

A12 V_DDEXT

A13 V_DDEXT

B14 V_DDEXT

A14 V_DDEXT

K23 V_DDEXT

K22 V_DDEXT

L23 V_DDEXT

L22 V_DDEXT

T23 V_DDEXT

G14 V_DDMEMJ7

G15 V_DDMEMK7

H7 V_DDMEML7

J17 V_DDMEMM7

K17 V_DDMEMN7

L17 V_DDMEMP7

M17 V_DDMEMR7

M14 NC J23 PH10 M22 V_DDEXT

M15 NMI U22 PH11 R22 V_DDEXT

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.

¹For ADSP-BF52xC compatibility, connect this ball to V_DDEXT

.

Rev. PrG

|

Page 72 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 60. 289-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal Ball Signal Ball Signal

Ball Signal

No.

A1 GND

A2 PG12

A3 PG13

A4 PG14

A5 PG15

B23 NC

C1 PG8

C2 PG6

C22 SDA

C23 NC

H22 GND

H23 NC

J1 TDI

L22 PH8

L23 PH7

P22 PH15

P23 XTAL

U22 NMI

U23 RTXI

AC5 ADDR9

AC6 ADDR5

AC7 ADDR4

AC8 ADDR2

AC9 ABE1/SDQM1

AC10 SA10

AC11 SCAS

AC12 V_DDOTP

AC13 SMS

AC14 ARDY

AC15 AOE

AC16 AMS2

AC17 AMS0

AC18 VR_OUT/EXT_WAKE1

AC19 EXT_WAKE0

AC20 SS/PG

AC21 USB_RSET

AC22 USB_VREF

AC23 GND

M1 DATA15 R1 DATA8 V1 DATA4

M2 DATA14 R2 DATA11 V2 DATA1

M7 V_DDMEMR7 V_DDMEMV22 RESET

J2 EMU

J7 V_DDMEM

J8 V_DDINT

J9 GND

J10 GND

J11 GND

J12 GND

J13 GND

J14 GND

J15 GND

J16 V_DDINT

J17 V_DDEXT

J22 GND¹

J23 NC

K1 TDO

K2 TRST

K7 V_DDMEM

K8 V_DDINT

K9 GND

K10 GND

K11 GND

K12 GND

K13 GND

K14 GND

K15 GND

K16 V_DDINT

K17 V_DDEXT

K22 PH6

K23 PH5

L1 TCK

A6 PPI_CLK/TMRCLK D1 PG4

M8 V_DDINT

M9 GND

M10 GND

M11 GND

M12 GND

M13 GND

M14 GND

M15 GND

M16 V_DDINT

M17 V_DDEXT

M22 PH10

M23 PH12

R8 V_DDINT

R9 GND

R10 GND

R11 GND

R12 GND

R13 GND

R14 GND

R15 GND

R16 V_DDINT

R17 V_DDEXT

R22 PH11

V23 RTXO

A7 PF0

A8 PF2

A9 PF14

A10 PF15

A11 PH0

A12 PH1

A13 PH2

A14 PH4

A15 NC

A16 NC

A17 NC

A18 NC

A19 NC

A20 PF9

A21 NC

A22 NC

A23 GND

B1 PG7

B2 PG9

B3 PG11

B4 PG10

B5 V_DDINT

B6 GND

D2 PG5

D22 NC

D23 NC

E1 BMODE2

E2 BMODE3

E22 NC

E23 NC

F1 PG3

W1 DATA2

W2 ADDR16

W22 V_DDUSB

W23 V_DDRTC

Y1 DATA0

Y2 ADDR17

Y22 USB_ID

Y23 V_DDUSB

F2 BMODE1

F22 NC

F23 NC

AA1 ADDR18

AA2 ADDR15

R23 CLKIN AA22 USB_DP

G1 PG1

N1 DATA12 T1 DATA7 AA23 USB_XO

N2 DATA13 T2 DATA6 AB1 ADDR19

N7 V_DDMEMT7 V_DDMEMAB2 ADDR13

G2 BMODE0

G7 V_DDEXT

G8 V_DDEXT

G9 V_DDEXT

G10 V_DDEXT

G11 V_DDEXT

G12 V_DDEXT

G13 V_DDEXT

G14 V_DDEXT

G15 V_DDEXT

G16 GND¹

N8 V_DDINT

N9 GND

N10 GND

N11 GND

N12 GND

N13 GND

N14 GND

N15 GND

N16 V_DDINT

N17 V_DDEXT

N22 PH13

N23 PH14

T8 V_DDINT

T9 V_DDINT

T10 V_DDINT

T11 V_DDINT

T12 V_DDINT

T13 V_DDINT

T14 V_DDINT

T15 V_DDINT

T16 V_DDINT

T17 V_DDEXT

T22 GND

T23 PH9

AB3 ADDR11

AB4 ADDR7

AB5 ADDR8

AB6 ADDR6

AB7 ADDR3

AB8 ADDR1

AB9 ABE0/SDQM0

AB10 SWE

AB11 VPPOTP

AB12 SRAS

AB13 SCKE

B7 PPI_FS1/TMR0 G17 GND

B8 PF1

B9 PF3

B10 PF5

B11 PF4

B12 PF6

B13 PF7

B14 PH3

B15 PF10

B16 PF8

B17 PF11

B18 PF12

B19 PF13

B20 NC

G22 NC

G23 NC

AB14 AWE

H1 PG2

H2 PG0

H7 V_DDEXT

H8 V_DDINT

H9 V_DDINT

H10 V_DDINT

H11 V_DDINT

H12 V_DDINT

H13 V_DDINT

H14 V_DDINT

H15 V_DDINT

H16 V_DDINT

H17 GND¹

P1 DATA9 U1 DATA5 AB15 AMS3

P2 DATA10 U2 DATA3 AB16 AMS1

P7 V_DDMEMU7 V_DDMEMAB17 ARE

L2 TMS

L7 V_DDMEM

L8 V_DDINT

L9 GND

L10 GND

L11 GND

L12 GND

L13 GND

L14 GND

L15 GND

L16 V_DDINT

L17 V_DDEXT

P8 V_DDINT

P9 GND

P10 GND

P11 GND

P12 GND

P13 GND

P14 GND

P15 GND

P16 V_DDINT

P17 V_DDEXT

U8 V_DDMEMAB18 CLKOUT

U9 V_DDMEMAB19 CLKBUF

U10 V_DDMEMAB20 USB_VBUS

U11 V_DDMEMAB21 USB_DM

U12 V_DDMEMAB22 VR_SEL/V_DDEXT

U13 V_DDMEMAB23 USB_XI

U14 V_DDMEMAC1 GND

U15 V_DDMEMAC2 ADDR14

U16 V_DDMEMAC3 ADDR12

U17 V_DDEXT

B21 NC

B22 SCL

AC4 ADDR10

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.

¹For ADSP-BF52xC compatibility, connect this ball to V_DDEXT

.

Rev. PrG

|

Page 73 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Figure 72 shows the top view of the BC-289-2 CSP_BGA ball

configuration. Figure 73 shows the bottom view of the BC-289-

2 CSP_BGA ball configuration.

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

TOP VIEW

M

N

P

KEY:

R

T

V

GND

I/O

NC

V

DDINT

U

V

W

Y

DDEXT

DDMEM

AA

AB

AC

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Figure 72. 289-Ball CSP_BGA Ball Configuration (Top View)

A1 BALL

PAD CORNER

A

B

C

D

E

BOTTOM VIEW

F

G

H

KEY:

J

K

V

GND

I/O

NC

V

L

DDINT

M

N

DDEXT

DDMEM

P

R

T

U

V

W

Y

AA

AB

AC

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Figure 73. 289-Ball CSP_BGA Ball Configuration (Bottom View)

Rev. PrG

|

Page 74 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

208-BALL CSP_BGA BALL ASSIGNMENT

Table 61 lists the CSP_BGA balls by signal mnemonic.

Table 62 on Page 76 lists the CSP_BGA by ball number.

Table 61. 208-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Signal

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball

No.

ABE0/SDQM0 V19 DATA2

ABE1/SDQM1 V20 DATA3

Y7

W7 GND

Y6 GND

W6 GND

Y5 GND

W5 GND

Y4 GND

W4 GND

Y3 GND

W3 GND

Y2 GND

GND

L12 PG6

L13 PG7

M9 PG8

M10 PG9

M11 PG10

M12 PG11

M13 PG12

N9 PG13

N10 PG14

N11 PG15

N12 PH0

N13 PH1

M2 SS/PG

G19 V_DDINT

T20 V_DDMEM

P14

L8

L1

L2

K1

K2

J1

SWE

TCK

ADDR01

ADDR02

ADDR03

ADDR04

ADDR05

ADDR06

ADDR07

ADDR08

ADDR09

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

W20 DATA4

W19 DATA5

Y19 DATA6

W18 DATA7

Y18 DATA8

W17 DATA9

Y17 DATA10

W16 DATA11

Y16 DATA12

W15 DATA13

Y15 DATA14

W14 DATA15

Y14 EMU

V2

R1

T1

V_DDMEM

M7

M8

N7

TDI

TDO

TMS

TRST

U2 V_DDMEM

U1 V_DDMEM

F20 V_DDMEM

E20 V_DDMEM

C20 V_DDMEM

N8

J2

P7

H1 USB_DM

H2 USB_DP

G1 USB_ID

P8

P9

P10

P11

R20

A16

D19

G20

H20

F19

A10

A7

B7

A8

B8

A9

B9

USB_RSET D20 V_DDMEM

USB_VBUS E19 V_DDOTP

USB_VREF H19 V_DDRTC

W2 GND

W1 GND

Y1

PH2

V1

T2

GND

NMI

Y20 PH3

B19 PH4

USB_XI

USB_XO

V_DDEXT

A19 V_DDUSB

A18 V_DDUSB

W13 EXT_WAKE0 J20 VPPOTP L19 PH5

G7 VR_OUT/EXT_WAKE1

Y13 GND

W12 GND

Y12 GND

W11 GND

Y11 GND

J19 GND

K19 GND

M19 GND

L20 GND

N20 GND

P19 GND

M20 GND

N19 GND

Y10 GND

W10 GND

A1

PF0

F1

E1

E2

PH6

PH7

PH8

B10 V_DDEXT

B11 V_DDEXT

A12 V_DDEXT

B12 V_DDEXT

A13 V_DDEXT

B13 V_DDEXT

B14 V_DDEXT

B15 V_DDEXT

B16 V_DDEXT

B17 V_DDEXT

G8 VR_SEL/V_DDEXT

A17 PF1

A20 PF2

B20 PF3

H9 PF4

H10 PF5

H11 PF6

H12 PF7

H13 PF8

G9 XTAL

G10

G11

H7

D1 PH9

D2 PH10

C1

C2

B1

B2

PH11

PH12

PH13

PH14

H8

AMS1

J7

AMS2

J8

AMS3

K7

AOE

J9

PF9

A2 PH15

B3

A3 PPI_FS1/TMR0

B5 RESET

A5 RTXI

B6 RTXO

A6 SA10

K8

ARDY

J10 PF10

J11 PF11

J12 PF12

J13 PF13

PPI_CLK/TMRCLK G2 V_DDEXT

F2 V_DDINT

L7

ARE

G12

G13

G14

H14

J14

AWE

B18 V_DDINT

A14 V_DDINT

A15 V_DDINT

U19 V_DDINT

U20 V_DDINT

P20 V_DDINT

BMODE0

BMODE1

BMODE2

BMODE3

CLKBUF

CLKIN

K9

PF14

Y9

GND

K10 PF15

K11 PG0

K12 PG1

K13 PG2

W9 GND

C19 GND

A11 GND

K20 GND

R2

P1

P2

SCAS

SCKE

SCL

K14

L14

M14

N14

P12

P13

A4

B4

V_DDINT

CLKOUT

DATA0

L9

PG3

N1 SDA

N2 SMS

M1 SRAS

Y8

GND

L10 PG4

L11 PG5

R19 V_DDINT

T19 V_DDINT

DATA1

W8 GND

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.

Rev. PrG

|

Page 75 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

Table 62. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

Ball Signal

No.

A1

A2

A3

A4

A5

A6

A7

A8

A9

GND

PF9

B19 NMI

B20 GND

H13 GND

L19 VPPOTP

L20 AMS3

M1 PG5

R1

R2

TDI

Y3

Y4

Y5

Y6

Y7

Y8

Y9

DATA10

DATA8

DATA6

DATA4

DATA2

DATA0

BMODE2

H14 V_DDINT

PG0

PF11

SCL

C1

C2

PF5

PF6

H19 USB_VREF

H20 VR_OUT/EXT_WAKE1

R19 SMS

M2 PG6

R20 V_DDOTP

PF13

PF15

PH0

PH2

PH4

C19 CLKBUF

C20 USB_ID

J1

J2

J7

J8

J9

PG11

PG12

V_DDEXT

GND

M7 V_DDMEM

M8 V_DDMEM

M9 GND

M10 GND

M11 GND

M12 GND

M13 GND

M14 V_DDINT

M19 AMS2

M20 ARE

T1

T2

TDO

EMU

D1

D2

PF3

PF4

T19 SRAS

T20 SWE

Y10 BMODE0

Y11 ADDR19

Y12 ADDR17

Y13 ADDR15

Y14 ADDR13

Y15 ADDR11

Y16 ADDR9

Y17 ADDR7

Y18 ADDR5

Y19 ADDR3

Y20 GND

D19 V_DDUSB

U1

U2

TRST

TMS

A10 XTAL

A11 CLKIN

A12 PH8

A13 PH10

A14 RTXI

A15 RTXO

A16 V_DDRTC

A17 GND

D20 USB_RSET

J10 GND

E1

E2

PF1

PF2

J11 GND

U19 SA10

U20 SCAS

J12 GND

E19 USB_VBUS

E20 USB_DP

J13 GND

V1

V2

DATA15

TCK

J14 V_DDINT

J19 AMS0

J20 EXT_WAKE0

F1

F2

PF0

N1

N2

N7

N8

N9

PG3

V19 ABE0/SDQM0

V20 ABE1/SDQM1

W1 DATA14

W2 DATA13

W3 DATA11

W4 DATA9

PPI_FS1/TMR0

PG4

F19 VR_SEL/V_DDEXT

K1

K2

K7

PG9

V_DDMEM

GND

A18 USB_XO F20 USB_DM

PG10

V_DDEXT

GND

A19 USB_XI

A20 GND

G1

G2

G7

G8

G9

PG15

PPI_CLK/TMRCLK K8

N10 GND

N11 GND

N12 GND

N13 GND

N14 V_DDINT

N19 AWE

N20 AOE

B1

B2

B3

B4

B5

B6

B7

B8

B9

PF7

V_DDEXT

K9

W5 DATA7

PF8

K10 GND

K11 GND

K12 GND

K13 GND

K14 V_DDINT

K19 AMS1

K20 CLKOUT

W6 DATA5

PF10

SDA

PF12

PF14

PH1

PH3

PH5

W7 DATA3

G10 V_DDEXT

G11 V_DDEXT

G12 V_DDINT

G13 V_DDINT

G14 V_DDINT

G19 SS/PG

G20 V_DDUSB

W8 DATA1

W9 BMODE3

W10 BMODE1

W11 ADDR18

W12 ADDR16

W13 ADDR14

W14 ADDR12

W15 ADDR10

W16 ADDR8

W17 ADDR6

W18 ADDR4

W19 ADDR2

W20 ADDR1

P1

P2

P7

P8

P9

PG1

PG2

L1

L2

L7

L8

L9

PG7

V_DDMEM

B10 PH6

B11 PH7

B12 PH9

B13 PH11

B14 PH12

B15 PH13

B16 PH14

B17 PH15

B18 RESET

PG8

H1

H2

H7

H8

H9

PG13

PG14

V_DDEXT

GND

V_DDEXT

V_DDMEM

GND

P10 V_DDMEM

P11 V_DDMEM

P12 V_DDINT

P13 V_DDINT

P14 V_DDINT

P19 ARDY

P20 SCKE

L10 GND

L11 GND

L12 GND

L13 GND

L14 V_DDINT

H10 GND

H11 GND

H12 GND

Y1

Y2

GND

DATA12

NOTE: In this table, BOLD TYPE indicates the sole signal/function for that ball on ADSP-BF522/524/526 processors.

Rev. PrG

|

Page 76 of 80

|

February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Figure 74 shows the top view of the CSP_BGA ball configura-

tion. Figure 75 shows the bottom view of the CSP_BGA

ball configuration.

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

KEY:

VDDINT

VDDEXT

GND

I/O

U

V

W

Y

VDDMEM

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

TOP VIEW

Figure 74. 208-Ball CSP_BGA Ball Configuration (Top View)

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

KEY:

VDDINT

VDDEXT

GND

I/O

U

V

W

Y

VDDMEM

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

BOTTOM VIEW

Figure 75. 208-Ball CSP_BGA Ball Configuration (Bottom View)

Rev. PrG

|

Page 77 of 80

|

February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

OUTLINE DIMENSIONS

Dimensions in Figure 76, 289-Ball CSP_BGA (BC-289-2) are

shown in millimeters.

0.5 BSC

BALL

PITCH

12.00 BSC SQ

11.00 BSC SQ

A1 BALL

PAD CORNER

CL

A1 BALL

PAD CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

CL

P

R

T

U

V

W

Y

AA

AB

AC

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

TOP VIEW

BOTTOM VIEW

1.40

1.26

1.11

0.20 MIN

DETAIL A

SIDE VIEW

NOTES

0.08 MAX

COPLANARITY

1. DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIES WITH JEDEC REGISTERED OUTLINE

MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT

AND BALL HEIGHT.

SEATING PLANE

0.35

DETAIL A

3. MINIMUM BALL HEIGHT 0.20

BALL DIAMETER

0.30

0.25

Figure 76. 289-Ball CSP_BGA (BC-289-2)

Rev. PrG

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Page 78 of 80

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February 2009

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

17.10

17.00 SQ

16.90

A1 CORNER

INDEX AREA

20 18 16 14 12 10

19 17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

E

F

A1 BALL

CORNER

G

H

J

15.20

BSC SQ

K

L

M

N

P

R

T

0.80

BSC

U

V

W

Y

TOP VIEW

DETAIL A

BOTTOM VIEW

*

1.36

1.26

1.16

1.75

1.61

1.46

DETAIL A

0.35 NOM

0.30 MIN

*

0.50

0.45

0.40

COPLANARITY

0.12

SEATING

PLANE

BALL

DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH

EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER.

Figure 77. 208-Ball CSP_BGA (BC-208-2)

SURFACE MOUNT DESIGN

Table 63 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface Mount Design and Land Pattern

Standard.

Table 63. Surface Mount Design Supplement

Package

289-Ball CSP_BGA

208-Ball CSP_BGA

Ball Attach Type

Solder Mask Defined

Solder Mask Opening

0.26 mm diameter

0.40 mm diameter

Ball Pad Size

0.35 mm diameter

0.50 mm diameter

Rev. PrG

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Page 79 of 80

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February 2009

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

ORDERING GUIDE

Table 64. ADSP-BF523/525/527 Processors

Temperature

Package Instruction Operating Voltage

Option Rate (Max) (Nom)

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

Model

ADSP-BF523KBCZ-6

Range¹

Package Description

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

0ºC to +70ºC

BC-289-2 600 MHz

BC-289-2 533 MHz

BC-289-2 600 MHz

BC-289-2 533 MHz

BC-289-2 600 MHz

BC-289-2 533 MHz

BC-208-2 600 MHz

BC-208-2 533 MHz

BC-208-2 600 MHz

BC-208-2 533 MHz

BC-208-2 600 MHz

BC-208-2 533 MHz

ADSP-BF523KBCZ-5

ADSP-BF525KBCZ-6

ADSP-BF525KBCZ-5

ADSP-BF527KBCZ-6

ADSP-BF527KBCZ-5

0ºC to +70ºC

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.2 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

1.15 V internal², 1.8 V, 2.5 V, or 3.3 V I/O

ADSP-BF523KBCZ-6A 0ºC to +70ºC

ADSP-BF523BBCZ-5A –40ºC to +85ºC 208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

ADSP-BF525KBCZ-6A 0ºC to +70ºC

208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

ADSP-BF525BBCZ-5A –40ºC to +85ºC 208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

ADSP-BF527KBCZ-6A 0ºC to +70ºC

208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

ADSP-BF527BBCZ-5A –40ºC to +85ºC 208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

¹Referenced temperature is ambient temperature.

2

ꢀis is the nominal voltage required to run at the nominal instruction rate. Lesser frequencies may require lower operating voltages. Please see Table 12 and Table 15 for details.

Table 65. ADSP-BF522/524/526 Processors

Temperature

Range¹

Package Instruction Operating Voltage

Option Rate (Max) (Nom)

Model

Package Description

ADSP-BF526KBCZ-4X 0ºC to +70ºC

289-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

BC-289-2 400 MHz

BC-208-2 400 MHz

BC-208-2 300 MHz

tbd V internal, 1.8 V, 2.5 V, or 3.3 V I/O

ADSP-BF526BBCZ-4AX –40ºC to +85ºC 208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

ADSP-BF526BBCZ-3AX –40ºC to +85ºC 208-Ball Chip Scale Package Ball

Grid Array (CSP_BGA)

tbd V internal, 1.8 V, 2.5 V, or 3.3 V I/O

¹Referenced temperature is ambient temperature.

registered trademarks are the property of their respective owners.

PR06675-0-2/09(PrG)

Rev. PrG

|

Page 80 of 80

|

February 2009


型号：	ADSP-BF526
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器
文件：	总80页 (文件大小：4702K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF526 [ADI]

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