ADSP-BF526C [ADI]
低功耗Blackfin处理器，配有高级外设和嵌入式立体声音频编解码器;
| 型号： | ADSP-BF526C |
| 厂家： | 
ADI |
| 描述： | 低功耗Blackfin处理器，配有高级外设和嵌入式立体声音频编解码器 编解码器 |
| 文件： | 总12页 (文件大小：835K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Blackfin®
Embedded Processor
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
PERIPHERALS
Preliminary Technical Data
FEATURES
Up to 600 MHz high-performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
tbd V to tbd V core VDD with on-chip voltage regulation
1.8V, 2.5V, or 3.3V I/O operation
Refer to the published ADSP-BF522/ADSP-BF525/ADSP-
BF527 Revision PrB datasheet for additional peripherals
CODEC FEATURES
Stereo 24-bit A/D and D/A converters
DAC
100 dB (A-weighted) signal-to-noise ratio at 3.3 V
95 dB (A-weighted) signal-to-noise ratio at 1.8 V
ADC
90 dB (A-weighted) signal-to-noise ratio at 3.3 V
85dB (A-weighted) signal-to-noise ratio at 1.8 V
Audio sample rates
Embedded low power audio CODEC
289-ball MBGA package
MEMORY
132K bytes of on-chip memory:
48K bytes of instruction SRAM
16K bytes of instruction SRAM/cache
32K bytes of data SRAM
32K bytes of data SRAM/cache
8 kHz, 44.1 kHz or 88.2 kHz–XTI/MCLK frequency 11.2896
MHz (256 × FS) or 16.9344 MHz (384 × FS)
8 kHz, 32 kHz, 48 kHz or 96 kHz–XTI/MCLK frequency
12.288 MHz (256 × FS) or 18.432 MHz (384 × FS)
Highly efficient headphone amplifier
Complete stereo/mono or microphone/line interface
Normal and USB modes programmed under software control
Low power
8 mW stereo playback (1.8 V all power supplies)
20 mW record and playback (1.8 V all power supplies))
Low supply voltages
1.8 V to 3.6 V analog supply range
1.8 V to 3.6 V digital supply range
4K bytes of scratchpad SRAM
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Nand flash controller
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
One-time programmable memory for security
Two dual-channel memory DMA controllers
Memory management unit providing memory protection
OTP
WATCHDOG TIMER
RTC
JTAG TEST AND EMULATION
VOLTAGE REGULATOR
PERIPHERAL ACCESS
BUS
INTERRUPT
CONTROLLER
TWI
B
SPORT1-0
CODEC
NAND
L1
L1
DATA
MEMORY
DMA
CONTROLLER
INSTRUCTION
MEMORY
PPI
PORTS
UART 0-1
SPI
DMA
EXTERNAL
BUS
USB
16
DMA CORE BUS
EXTERNAL ACCESS BUS
TIMERS 0-7
BOOT
ROM
EXTERNAL PORT
FLASH, SDRAM CONTROL
EMAC/HDMA
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2007 Analog Devices, Inc. All rights reserved.
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
REVISION HISTORY
6/07—Revision PrB: Changes from PrA to PrB
Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assign-
ment (Alphabetically by Signal) ................................... 7
Corrects SS/PG and VRSEL 289-Ball Mini-BGA Ball Assign-
ment (Numerically by Ball Number) ............................. 8
3/07—Revision PrA: Initial Version
Rev. PrB
| Page 2 of 12 | June 2007
Preliminary Technical Data
GENERAL DESCRIPTION
This document describes the differences between the ADSP-
BF522C/ADSP-BF525C/ADSP-BF527C and the ADSP-
BF522/ADSP-BF525/ADSP-BF527 standard product. Please
refer to the published ADSP-BF522/ADSP-BF525/ADSP-BF527
Revision PrC datasheet for general description and specifica-
tions. This document only describes the exceptions to that
datasheet.
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
In normal mode, the XMI/MCLK oscillator is set up according
to the desired sample rates of the ADC and DAC. For ADC or
DAC sampling rates of 8 kHz, 32 kHz, 48 kHz or 96 kHz, MCLK
frequencies of either 12.288 MHz (256 × FS) or 18.432 MHz
(384 × FS) can be used. For ADC or DAC sampling rates of
8 kHz, 44.1 kHz or 88.2 kHz, MCLK frequencies of either
11.2896 MHz (256 × FS) or 16.9344 MHz (384 × FS) can be
used.
In USB mode, the XTI/MCLK frequency is only 12MHz allow-
ing for ADC and DAC sampling rates of 8 kHz, 44.1 kHz or 88.2
kHz.
The CODEC can operate with power supplies as low as 1.8 V for
the analog part and 1.8 V for digital port. The maximum voltage
is 3.6 V for all power supplies.
The ADSP-BF522C/ADSP-BF525C/ADSP-BF527C adds a ste-
reo CODEC to the standard product and changes the package
labeling.
STEREO CODEC
The CODEC in the ADSP-BF522C/ADSP-BF525C/ADSP-
BF527C is a low power, high quality stereo audio CODEC for
portable digital audio application. It features two 24-bit A/D
converter channels and two 24-bit D/A converter channels.
The device is controlled by a 2- or 3-wire serial interface which
provides access to all features including volume controls, mutes
and extensive power management facilities.
ATTENUATOR
MICBIAS
ATTENUATOR
RHPOUT
RLINEIN
ADC
MUX
+
+
ROUT
DAC
DAC
DIGITAL
FILTERS
MICIN
LOUT
LHPOUT
MUX
ADC
LLINEIN
ATTENUATOR
ATTENUATOR
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
XTI/MCLK XTO CCLKOUT DACDAT ADCDAT BCLK ADCLRC DACLRC
CMODE CSB CSDA CSCL
Figure 2. Audio CODEC Block Diagram
Rev. PrB
| Page 3 of 12 | June 2007
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
PIN DESCRIPTIONS
The ADSP-BF522C/ADSP-BF525C/ADSP-BF527C processor
adds CODEC signals as listed in Table 1.
Table 1. Pin Descriptions
Pin Name
CCLKOUT
BCLK
Type Function
Pull-Up/Down
O
CODEC Clock Output
None
Internal Pull-down1
I/O CODEC Digital Audio Bit Clock
DACDAT
DACLRC
ADCDAT
ADCLRC
CMODE
CSB
I
CODEC DAC Sample Rate Left/Right Clock
I/O CODEC I/O DAC Sample Rate Left/Right Clock
CODEC ADC Digital Audio Data Output
I/O CODEC ADC Sample Rate Left/Right Clock
None
Internal Pull-down1
O
None
Internal Pull-down1
Internal Pull-up1
Internal Pull-up1
None
I
I
CODEC Control Interface Selection
CODEC MPU Chip Select/MPU Interface Address Selection
CSDA
I/O CODEC MPU Data Input
CSCL
I
CODEC MPU Clock
None
XTI/MCLK
XTO
I
CODEC Crystal Input/MPU Clock Input
CODEC Crystal Output
None
O
O
O
O
O
O
O
I
None
LHPOUT
RHPOUT
LOUT
CODEC Left Channel Headphone Output (Analog Output)
CODEC Right Channel Headphone Output (Analog Output)
CODEC Left Channel Line Output (Analog Output)
CODEC Right Channel Line Output (Analog Output)
CODEC Mid-rail Reference Decoupling Point (Analog Output)
CODEC Electret Microphone Bias (Analog Output)
CODEC Microphone Input; (Analog Input, AC Coupled)
CODEC Right Channel Line Input (Analog Input, AC Coupled)
CODEC Left Channel Line Input (Analog Input, AC Coupled)
CODEC Digital Core Ground
None
None
None
ROUT
None
VMID
None
MICBIAS
MICIN
None
None
RLINEIN
LLINEIN
GND
I
None
I
None
P
P
P
P
P
N/A
AVDD
CODEC Analog VDD
N/A
AGND
CODEC Analog Ground
N/A
HPVDD
HPGND
CODEC Headphone VDD (Analog)
N/A
CODEC Headphone Ground
N/A
1 Pull-up/pull-down is only present when the control register interface ACTIVE = 0 to conserve power.
Rev. PrB
| Page 4 of 12 | June 2007
Preliminary Technical Data
SPECIFICATIONS
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter
CVDD
AVDD
HPVDD
VILC
VIHC
VOLC
VOHC
TJ
Conditions
Min
1.8
1.8
1.8
Typical Max
Unit
V
V
V
V
V
V
V
°C
Digital Core VDD
Analog VDD
3.6
3.6
3.6
Headphone VDD (Analog)
CODEC Low Level Input Voltage1
CODEC High Level Input Voltage1
CODEC Low Level Output Voltage1
CODEC Low Level Output Voltage1
Junction Temperature
0.3 × CVDD
0.7 × CVDD
0.1 × CVDD
+105
0.9 × CVDD
0
289-Ball Chip Scale Ball Grid Array (Mini-BGA)
@ TAMBIENT = 0°C to +70°C
1 Parameter value applies to digital signal pins (ADCDAT, ADCLRC, BCLK, CSB, CCLKOUT, CMODE, DACDAT, DACLRC, CSCL, CSDA, XTI/MCLK, XTO).
ELECTRICAL CHARACTERISTICS
Parameter
Line Input to ADC
SNR
SNR
DR
Conditions
Min
tbd
tbd
Typical
Max
Unit
Signal to Noise Ratio
Signal to Noise Ratio
Dynamic Range
A-weighted, 0 dB Gain @ FS = 48 kHz
A-weighted, 0 dB Gain @ FS = 96 kHz
A-weighted, –60 dB Full Scale Input
85
85
88
–76
dB
dB
dB
dB
THD
Total Harmonic Distortion –1 dB Input, 0 dB Gain
tbd
Microphone Input to ADC
0 dB Gain, FS = 48 kHz, 40 kΩ Source Impedance
A-weighted, 0 dB Gain
A-weighted, –60 dB Full Scale Input
SNR
DR
Signal to Noise Ratio
Dynamic Range
80
70
–55
dB
dB
dB
THD
Total Harmonic Distortion 0 dB Input, 0 dB Gain
Line Output for DAC Playback Only Load = 10 kΩ, 50 pF
SNR
SNR
DR
THD
THD
Signal to Noise Ratio
Signal to Noise Ratio
Dynamic Range
Total Harmonic Distortion 1 kHz, 0 dB
Total Harmonic Distortion 1 kHz, –3 dB
A-weighted, 0 dB Gain @ FS = 48 kHz
A-weighted, 0 dB Gain @ FS = 96 kHz
A-weighted, –60 dB Full Scale Input
tbd
tbd
95
93
90
–80
–90
dB
dB
dB
dB
dB
tbd
tbd
Analog Line Input to Line Output Load = 10 k Ω, 50 pF, No Gain on Input, Bypass Mode
SNR
THD
THD
Signal to Noise Ratio
Total Harmonic Distortion 1 kHz, 0 dB
Total Harmonic Distortion 1 kHz, –3 dB
tbd
90
–83
–92
dB
dB
dB
Stereo Headphone Output
PO
PO
SNR
THD
THD
Maximum Output Power RL = 32 Ω
Maximum Output Power RL = 16 Ω
Signal to Noise Ratio A-weighted
Total Harmonic Distortion 1 kHz, –5 dB, RL = 32 Ω, Full Scale Input
Total Harmonic Distortion 1 kHz,–2 dB, RL = 32 Ω, Full Scale Input
9
mW
mW
dB
dB
dB
18
95
–62
tbd
tbd
tbd
tbd
Microphone Input to Headphone Output Side Tone Mode
SNR Signal to Noise Ratio
90
dB
Rev. PrB
| Page 5 of 12 | June 2007
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
DIGITAL FILTER CHARACTERISTICS
Parameter
Conditions
Min
Typical
Max
Unit
ADC Filter
Passband
Passband
Passband Ripple
Stopband
Stopband Attenuation
High Pass Filter Corner Frequency
High Pass Filter Corner Frequency
High Pass Filter Corner Frequency
DAC Filter
0.05 dB
–6 dB
tbd × FS
tbd × FS
tbd
0.5 × FS
dB
tbd × FS
tbd
F > 0.5465 × FS
–3 dB
–0.5 dB
dB
Hz
Hz
Hz
3.7
10.4
21.6
–0.1 dB
Passband
Passband
Passband Ripple
Stopband
Stopband Attenuation
0.03 dB
–6 dB
tbd × FS
tbd × FS
tbd
0.5 × FS
dB
dB
tbd × FS
tbd
F > 0.5465 × FS
PACKAGE INFORMATION
The information presented in Figure 3 and Table 2 provides
details about the package branding for the ADSP-
BF522C/ADSP-BF525C/ADSP-BF527C processor. For a com-
plete listing of product availability, see Ordering Guide on
Page 12.
a
ADSP-BF525C
tppZccc
vvvvvv.x n.n
yyww country_of_origin
B
Figure 3. Product Information on Package
Table 2. Package Brand Information
Brand Key
Field Description
Temperature Range
Package Type
t
pp
Z
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ccc
vvvvvv.x
n.n
yyww
Rev. PrB
| Page 6 of 12 | June 2007
Preliminary Technical Data
289-BALL MINI-BGA PINOUT
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Table 3 lists the mini-BGA pinout by signal mnemonic. Table 4
on Page 8 lists the mini-BGA pinout by ball number.
Table 3. 289-Ball Mini-BGA Ball Assignment (Alphabetically by Signal)
Signal
Ball Signal
No.
Ball Signal Ball Signal
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
Ball
No.
No.
No.
ABE0/SDQM0 AB9 CSB
ABE1/SDQM1 AC9 CSCL
D23 GND
B23 GND
C23 GND
A18 GND
A17 GND
L14 PF5
L15 PF6
M9 PF7
M10 PF8
M11 PF9
M12 PF10
M13 PF11
M14 PF12
M15 PF13
N9 PF14
N10 PF15
N11 PG0
N12 PG1
N13 PG2
N14 PG3
N15 PG4
B10 RESET
B12 RHPOUT
B13 RLINEIN
B16 ROUT
A20 RTXI
B15 RTXO
B17 SA10
B18 SCAS
B19 SCKE
A9 SCL
A10 SDA
H2 SMS
G1 SRAS
H1 SS/PG
F1 SWE
V22 VDDEXT R17 VDDMEM U8
B21 VDDEXT T17 VDDMEM U9
F23 VDDEXT U17 VDDMEM U10
G22 VDDINT B5 VDDMEM U11
U23 VDDINT H8 VDDMEM U12
V23 VDDINT H9 VDDMEM U13
AC10 VDDINT H10 VDDMEM U14
AC11 VDDINT H11 VDDMEM U15
AB13 VDDINT H12 VDDMEM U16
B22 VDDINT H13 VDDOTP AC12
C22 VDDINT H14 VDDRTC W23
AC13 VDDINT H15 VDDUSB W22
AB12 VDDINT H16 VDDUSB Y23
ADCDAT
ADCLRC
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
AGND
AGND
AMS0
AMS1
AMS2
AMS3
AOE
ARDY
ARE
AVDD
AVDD
AWE
BCLK
A16 CSDA
A15 DACDAT
AB8 DACLRC
AC8 DATA0
AB7 DATA1
AC7 DATA2
AC6 DATA3
AB6 DATA4
AB4 DATA5
AB5 DATA6
AC5 DATA7
AC4 DATA8
AB3 DATA9
AC3 DATA10
AB2 DATA11
AC2 DATA12
AA2 DATA13
W2 DATA14
Y1
V2
GND
GND
W1 GND
U2
V1
U1
T2
T1
R1
P1
P2
R2
GND
GND
GND
GND
GND
GND
GND
GND
GND
AC20 VDDINT J8 VMID
AB10 VDDINT J16 VROUT
G23
AC18
AB22
P23
D1 TCK
D2 TDI
C2 TDO
B1 TMS
L1
J1
VDDINT K8 VRSEL
VDDINT K16 XTAL
P9
PG5
N1 GND
N2 GND
M2 GND
M1 GND
P10 PG6
P11 PG7
P12 PG8
P13 PG9
P14 PG10
P15 PG11
K1
L2
K2
VDDINT L8 XTI/MCLK A22
VDDINT L16 XTO
VDDINT M8
A21
C1 TRST
Y2
AA1 EMU
AB1 EXT_WAKE AC19 GND
DATA15
B2 USB_DM
B4 USB_DP
B3 USB_ID
A2 USB_RSET
A3 USB_VBUS
A4 USB_VREF
A5 USB_XTALIN
AB21 VDDINT M16
AA22 VDDINT N8
Y22 VDDINT N16
AC21 VDDINT P8
AB20 VDDINT P16
AC22 VDDINT R8
AB23 VDDINT R16
J2
GND
G17 GND
H22 GND
AC17 GND
AB16 GND
AC16 GND
AB15 GND
AC15 GND
AC14 GND
AB17 GND
G16 GND
J22 GND
AB14 GND
A19 GND
A1
GND
R9
PG12
A23 GND
R10 PG13
R11 PG14
R12 PG15
R13 PH0
R14 PH1
R15 PH2
T22 PH3
AC1 PH4
AC23 PH5
B6
J9
GND
GND
J10 GND
J11 GND
J12 GND
J13 GND
J14 GND
J15 GND
A11 USB_XTALOUT AA23 VDDINT T8
A12 VDDEXT
A13 VDDEXT
B14 VDDEXT
A14 VDDEXT
K23 VDDEXT
K22 VDDEXT
L23 VDDEXT
L22 VDDEXT
T23 VDDEXT
M22 VDDEXT
R22 VDDEXT
M23 VDDEXT
N22 VDDEXT
N23 VDDEXT
P22 VDDEXT
G7
G8
G9
VDDINT T9
VDDINT T10
VDDINT T11
G10 VDDINT T12
G11 VDDINT T13
G12 VDDINT T14
G13 VDDINT T15
G14 VDDINT T16
G15 VDDMEM J7
K9
K10 LLINEIN E23 PH7
K11 LOUT F22 PH8
K12 MICBIAS H23 PH9
LHPOUT B20 PH6
BMODE0
BMODE1
BMODE2
BMODE3
CCLKOUT
CLKBUF
CLKIN
G2
F2
E1
E2
D22 GND
AB19 GND
R23 GND
AB18 GND
E22 GND
GND
GND
GND
GND
K13 MICIN
K14 NMI
K15 OTPVPP AB11 PH12
J23 PH10
U22 PH11
H7
VDDMEM K7
H17 VDDMEM L7
J17 VDDMEM M7
K17 VDDMEM N7
L17 VDDMEM P7
M17 VDDMEM R7
N17 VDDMEM T7
P17 VDDMEM U7
L9
PF0
A7
B8
A8
B9
PH13
PH14
PH15
L10 PF1
L11 PF2
L12 PF3
L13 PF4
CLKOUT
CMODE
PPICLK/TMRCLK A6 VDDEXT
B7 VDDEXT
B11 PPIFS1/TMR0
Rev. PrB
| Page 7 of 12 | June 2007
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
Table 4. 289-Ball Mini-BGA Ball Assignment (Numerically by Ball Number)
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
Ball Signal
No.
A1 GND
A2 PG12
A3 PG13
A4 PG14
A5 PG15
B23 CSCL
C1 PG8
C2 PG6
C22 SDA
C23 CSDA
H22 AGND
H23 MICBIAS L23 PH7
J1 TDI
J2 EMU
J7 VDDMEM M7 VDDMEM R7 VDDMEM V22 RESET
J8 VDDINT M8 VDDINT R8 VDDINT V23 RTXO
L22 PH8
P22 PH15
P23 XTAL
R1 DATA8
R2 DATA11
U22 NMI
U23 RTXI
AC5 ADDR9
AC6 ADDR5
AC7 ADDR4
AC8 ADDR2
AC9 ABE1/SDQM1
AC10 SA10
M1 DATA15
M2 DATA14
V1
V2
DATA4
DATA1
A6 PPICLK/TMRCLK D1 PG4
A7 PF0
A8 PF2
A9 PF14
A10 PF15
A11 PH0
A12 PH1
A13 PH2
A14 PH4
A15 ADCLRC
A16 ADCDAT
A17 DACLRC
A18 DACDAT
A19 BCLK
A20 PF9
D2 PG5
D22 CCLKOUT J10 GND
D23 CSB J11 GND
E1 BMODE2 J12 GND
E2 BMODE3 J13 GND
J9 GND
M9 GND
M10 GND
M11 GND
M12 GND
M13 GND
M14 GND
M15 GND
R9 GND
R10 GND
R11 GND
R12 GND
R13 GND
R14 GND
R15 GND
W1 DATA2
AC11 SCAS
AC12 VDDOTP
AC13 SMS
AC14 ARDY
AC15 AOE
AC16 AMS2
AC17 AMS0
AC18 VROUT
AC19 EXT_WAKE
AC20 SS/PG
AC21 USB_RSET
W2 ADDR16
W22 VDDUSB
W23 VDDRTC
Y1
Y2
DATA0
ADDR17
E22 CMODE
E23 LLINEIN
F1 PG3
J14 GND
J15 GND
Y22 USB_ID
J16 VDDINT M16 VDDINT R16 VDDINT Y23 VDDUSB
F2 BMODE1 J17 VDDEXT M17 VDDEXT R17 VDDEXT AA1 ADDR18
F22 LOUT
F23 RLINEIN J23 MICIN
G1 PG1 K1 TDO
G2 BMODE0 K2 TRST
J22 AVDD
M22 PH10
M23 PH12
N1 DATA12
N2 DATA13
R22 PH11
R23 CLKIN
T1 DATA7
T2 DATA6
AA2 ADDR15
AA22 USB_DP
AA23 USB_XTALOUT AC22 USB_VREF
AB1 ADDR19 AC23 GND
G7 VDDEXT K7 VDDMEM N7 VDDMEM T7 VDDMEM AB2 ADDR13
G8 VDDEXT K8 VDDINT N8 VDDINT T8 VDDINT AB3 ADDR11
A21 XTO
A22 XTI/MCLK
A23 GND
B1 PG7
G9 VDDEXT K9 GND
G10 VDDEXT K10 GND
G11 VDDEXT K11 GND
G12 VDDEXT K12 GND
G13 VDDEXT K13 GND
G14 VDDEXT K14 GND
G15 VDDEXT K15 GND
N9 GND
N10 GND
N11 GND
N12 GND
N13 GND
N14 GND
N15 GND
T9 VDDINT AB4 ADDR7
T10 VDDINT AB5 ADDR8
T11 VDDINT AB6 ADDR6
T12 VDDINT AB7 ADDR3
T13 VDDINT AB8 ADDR1
T14 VDDINT AB9 ABE0/SDQM0
T15 VDDINT AB10 SWE
B2 PG9
B3 PG11
B4 PG10
B5 VDDINT
B6 GND
B7 PPIFS1/TMR0
B8 PF1
B9 PF3
B10 PF5
B11 PF4
G16 AVDD
G17 AGND
G22 ROUT
G23 VMID
H1 PG2
K16 VDDINT N16 VDDINT T16 VDDINT AB11 OTPVPP
K17 VDDEXT N17 VDDEXT T17 VDDEXT AB12 SRAS
K22 PH6
K23 PH5
L1 TCK
L2 TMS
N22 PH13
N23 PH14
P1 DATA9
P2 DATA10
T22 GND
T23 PH9
AB13 SCKE
AB14 AWE
AB15 AMS3
AB16 AMS1
U1 DATA5
U2 DATA3
H2 PG0
B12 PF6
B13 PF7
H7 VDDEXT L7 VDDMEM P7 VDDMEM U7 VDDMEM AB17 ARE
H8 VDDINT L8 VDDINT P8 VDDINT U8 VDDMEM AB18 CLKOUT
B14 PH3
B15 PF10
B16 PF8
B17 PF11
B18 PF12
B19 PF13
B20 LHPOUT
B21 RHPOUT
B22 SCL
H9 VDDINT L9 GND
H10 VDDINT L10 GND
H11 VDDINT L11 GND
H12 VDDINT L12 GND
H13 VDDINT L13 GND
H14 VDDINT L14 GND
H15 VDDINT L15 GND
P9 GND
P10 GND
P11 GND
P12 GND
P13 GND
P14 GND
P15 GND
U9 VDDMEM AB19 CLKBUF
U10 VDDMEM AB20 USB_VBUS
U11 VDDMEM AB21 USB_DM
U12 VDDMEM AB22 VRSEL
U13 VDDMEM AB23 USB_XTALIN
U14 VDDMEM AC1 GND
U15 VDDMEM AC2 ADDR14
H16 VDDINT L16 VDDINT P16 VDDINT U16 VDDMEM AC3 ADDR12
H17 VDDEXT L17 VDDEXT P17 VDDEXT U17 VDDEXT AC4 ADDR10
Rev. PrB
| Page 8 of 12 | June 2007
Preliminary Technical Data
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Figure 5 shows the top view of the mini-BGA ball configuration.
Figure 4 shows the bottom view of the mini-BGA
ball configuration.
Table 5. Thermal Characteristics (BC-289)
Parameter Condition
Typical Unit
θJA
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
tbd
tbd
tbd
tbd
tbd
؇C/W
؇C/W
؇C/W
؇C/W
؇C/W
θJMA
θJMA
θJB
θJC
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
KEY:
R
T
V
V
GND
AGND
DDINT
U
V
I/O
V
W
Y
DDEXT
DDMEM
AVDD
AA
AB
AC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
TOP VIEW
Figure 4. 289-Ball Mini-BGA Ball Configuration (Top View)
Rev. PrB
| Page 9 of 12 | June 2007
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
KEY:
U
V
W
Y
V
GND
I/O
AGND
DDINT
AA
AB
AC
V
V
DDEXT
DDMEM
AVDD
23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOTTOM VIEW
9
8
7
6
5
4
3
2
1
Figure 5. 289-Ball Mini-BGA Ball Configuration (Bottom View)
Rev. PrB
| Page 10 of 12 | June 2007
Preliminary Technical Data
OUTLINE DIMENSIONS
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Dimensions in the outline dimension figures are shown in
millimeters.
289-BALL MINI BGA
(BC-289-2)
0.5 BSC
BALL
PITCH
12.00 BSC SQ
11.00 BSC SQ
A1 BALL
PAD CORNER
CL
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
CL
P
R
T
U
V
W
Y
AA
AB
AC
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
TOP VIEW
BOTTOM VIEW
1.40
1.26
1.11
0.20 MIN
DETAIL A
SIDE VIEW
NOTES
0.08 MAX
COPLANARITY
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT
AND BALL HEIGHT.
SEATING PLANE
0.35
DETAIL A
3. MINIMUM BALL HEIGHT 0.20
BALL DIAMETER
0.30
0.25
Figure 6. 289-Ball Chip Scale Package Ball Grid Array (Mini-BGA)
SURFACE MOUNT DESIGN
Table 6 is provided as an aid to PCB design. For industry-
standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat-
tern Standard.
Table 6. BGA Data for Use with Surface Mount Design
Package
Ball Attach Type
Solder Mask Opening
Ball Pad Size
289-Ball Chip Scale Package Ball Grid Array (Mini-BGA)
Solder Mask Defined
0.26 mm diameter
0.35 mm diameter
Rev. PrB
| Page 11 of 12 | June 2007
ADSP-BF522C/ADSP-BF525C/ADSP-BF527C
Preliminary Technical Data
ORDERING GUIDE
Temperature
Package Instruction Operating Voltage
Option Rate (Max) (Nom)
Model
Range1
Package Description
ADSPBF527KBCZENGC1 0ºC to +70ºC 289-Ball Chip Scale Package Ball Grid Array BC-289 600 MHz
(Mini-BGA)
tbd V internal, 1.8 V or 3.3 V I/O
1 Referenced temperature is ambient temperature.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06876-0-6/07(PrB)
Rev. PrB
| Page 12 of 12 | June 2007
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