ADSP-BF527BBCZ-5AX_技术文档

Blackfin^®Embedded Processor

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

FEATURES

PERIPHERALS

Up to 600 MHz high-performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

USB 2.0 high speed on-the-go (OTG) with Integrated PHY

IEEE 802.3-compliant 10/100 Ethernet MAC

Parallel peripheral interface (PPI), supporting ITU-R 656

video data formats

RISC-like register and instruction model for ease of

programming and compiler-friendly support

Advanced debug, trace, and performance monitoring

Accepts a wide range of supply voltages for internal and I/O

operations. See Operating Conditions for

ADSP-BF523/525/527 on Page 29 and Operating Condi-

tions for ADSP-BF522/524/526 on Page 27

Programmable on-chip voltage regulator

(ADSP-BF523/525/527 processors only)

Host DMA port (HOSTDP)

Two dual-channel, full-duplex synchronous serial ports

(SPORTs), supporting eight stereo I²S channels

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 54 interrupt inputs

Serial peripheral interface (SPI) compatible port

Two UARTs with IrDA^®support

289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm)

CSP_BGA packages

Two-wire interface (TWI) controller

Eight 32-bit timers/counters with PWM support

32-bit up/down counter with rotary support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), with programmable

hysteresis

NAND flash controller (NFC)

Debug/JTAG interface

On-chip PLL capable of 0.5

؋

to 64

؋

frequency multiplication

MEMORY

132K bytes of on-chip memory:

(See Table 1 on Page 3 for L1 and L3 memory size details)

External memory controller with glueless support for SDRAM

and asynchronous 8-bit and 16-bit memories

Flexible booting options from external flash, SPI, and TWI

memory or from host devices including SPI, TWI, and UART

Code Security with Lockbox^TMSecure Technology

One-Time-Programmable (OTP) Memory

Memory management unit providing memory protection

WATCHDOG TIMER

OTP MEMORY

RTC

VOLTAGE REGULATOR*

JTAG TEST AND EMULATION

PERIPHERAL

COUNTER

SPORT0

SPORT1

UART1

UART0

NFC

ACCESS BUS

INTERRUPT

CONTROLLER

GPIO

PORT F

B

L1 INSTRUCTION

MEMORY

L1 DATA

GPIO

PORT G

DMA

MEMORY

PPI

CONTROLLER

DMA

ACCESS

BUS

EAB

16

SPI

DCB

USB

TIMER7-1

TIMER0

GPIO

PORT H

DEB

BOOT

ROM

EXTERNAL PORT

FLASH, SDRAM CONTROL

EMAC

HOST DMA

TWI

PORT J

*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY

Figure 1. Processor Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrE

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low-Power Architecture ............................. 3

System Integration ................................................ 3

Processor Peripherals ............................................. 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 9

Host DMA Port .................................................... 9

Real-Time Clock ................................................. 10

Watchdog Timer ................................................ 10

Timers ............................................................. 10

Up/Down Counter and Thumbwheel Interface .......... 10

Serial Ports ........................................................ 11

Serial Peripheral Interface (SPI) Port ....................... 11

UART Ports ...................................................... 11

USB On-The-Go Dual-Role Device Controller ........... 12

TWI Controller Interface ...................................... 12

10/100 Ethernet MAC .......................................... 12

Ports ................................................................ 12

Parallel Peripheral Interface (PPI) ........................... 13

Code Security with Lockbox Secure Technology ......... 14

Dynamic Power Management ................................ 14

ADSP-BF523/525/527 Voltage Regulation ................ 15

ADSP-BF522/524/526 Voltage Regulation ................ 16

Clock Signals ..................................................... 16

Booting Modes ................................................... 18

Instruction Set Description .................................... 20

Development Tools .............................................. 21

Designing an Emulator-Compatible

Processor Board (Target) ................................... 21

Related Documents .............................................. 21

Lockbox Secure Technology Disclaimer .................... 21

Signal Descriptions ................................................. 22

Specifications ........................................................ 26

Operating Conditions for ADSP-BF522/524/526 ......... 26

Operating Conditions for ADSP-BF523/525/527 ......... 28

Electrical Characteristics ....................................... 30

Absolute Maximum Ratings ................................... 31

ESD Sensitivity ................................................... 31

Package Information ............................................ 31

Timing Specifications ........................................... 32

Output Drive Currents ......................................... 57

Power Dissipation ............................................... 59

Test Conditions .................................................. 59

Environmental Conditions .................................... 62

289-Ball CSP_BGA Ball assignment ............................ 63

208-Ball CSP_BGA Ball assignment ............................ 66

Outline Dimensions ................................................ 69

Surface Mount Design .......................................... 70

Ordering Guide ..................................................... 71

REVISION HISTORY

06/08—Revision PrE:

Changes to processor specifications (starting on Page 27). Major

changes include:

Numerous small clarifications and corrections throughout

document.

• Added NFC timing ...................................................Page 36

• Changes to SPI timing .............................................Page 47

• Added UART timing ...............................................Page 49

• Added Up/Down Counter timing ..........................Page 51

• Changes to HOSTDP timing ............Page 52 and Page 53

Changes to ball assignment tables .........Page 64 and Page 67

Changes to voltage regulator in Block Diagram..........Page 1

Changes to processor comparison data ......Table 1 on Page 3

Changes to hibernate state description................... Page 15

Changes to voltage regulator description ................ Page 16

Changes to booting modes description................... Page 18

Changes to signal descriptions ............ Table 10 on Page 23

Added Lockbox Secure Technology Disclaimer ....... Page 21

Rev. PrE

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Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are members of the Blackfin family of products,

incorporating the Analog Devices/Intel Micro Signal Architec-

ture (MSA). Blackfin processors combine a dual-MAC state-of-

the-art signal processing engine, the advantages of a clean,

orthogonal RISC-like microprocessor instruction set, and sin-

gle-instruction, multiple-data (SIMD) multimedia capabilities

into a single instruction-set architecture.

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are completely code compatible with other Blackfin

processors. The ADSP-BF523/525/527 processors offer perfor-

mance up to 600 MHz. The ADSP-BF522/524/526 processors

offer performance up to 400 MHz and reduced static power

consumption. Differences with respect to peripheral combina-

tions are shown in Table 1.

ADSP-BF522/523/524/525/526/527

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

PORTABLE LOW-POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. They are produced with a low power and low

voltage design methodology and feature on-chip dynamic

power management, which is the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. This capability can result in a substantial reduc-

tion in power consumption, compared with just varying the

frequency of operation. This allows longer battery life for

portable appliances.

Table 1. Processor Comparison

SYSTEM INTEGRATION

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors are highly integrated system-on-a-chip solutions for the

next generation of embedded network connected applications.

By combining industry-standard interfaces with a high perfor-

mance signal processing core, cost-effective applications can be

developed quickly, without the need for costly external compo-

nents. The system peripherals include an IEEE-compliant 802.3

10/100 Ethernet MAC, a USB 2.0 high speed OTG controller, a

TWI controller, a NAND flash controller, two UART ports, an

SPI port, two serial ports (SPORTs), eight general purpose 32-

bit timers with PWM capability, a core timer, a real-time clock,

a watchdog timer, a Host DMA (HOSTDP) interface, and a par-

allel peripheral interface (PPI).

Feature

Host DMA

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

–

1

2

1

8

1

2

1

8

1

USB

Ethernet MAC

Internal Voltage Regulator

TWI

SPORTs

UARTs

SPI

PROCESSOR PERIPHERALS

GP Timers

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors contain a rich set of peripherals connected to the core via

several high bandwidth buses, providing flexibility in system

configuration as well as excellent overall system performance

(see the block diagram on Page 1). These Blackfin processors

contain dedicated network communication modules and high

speed serial and parallel ports, an interrupt controller for flexi-

ble management of interrupts from the on-chip peripherals or

external sources, and power management control functions to

tailor the performance and power characteristics of the proces-

sor and system to many application scenarios.

All of the peripherals, except for the general-purpose I/O, TWI,

real-time clock, and timers, are supported by a flexible DMA

structure. There are also separate memory DMA channels dedi-

cated to data transfers between the processor's various memory

spaces, including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along

with activity on all of the on-chip and external peripherals.

Watchdog Timers

RTC

Parallel Peripheral Interface

GPIOs

48 48 48 48 48 48

48K 48K 48K 48K 48K 48K

L1 Instruction SRAM

L1 Instruction SRAM/Cache 16K 16K 16K 16K 16K 16K

L1 Data SRAM

32K 32K 32K 32K 32K 32K

4K 4K 4K 4K 4K 4K

32K 32K 32K 32K 32K 32K

L1 Data SRAM/Cache

L1 Scratchpad

L3 Boot ROM

Maximum Speed Grade¹

Maximum System Clock Speed

Package Options

400 MHz

80 MHz

600 MHz

133 MHz

289-Ball CSP_BGA

208-Ball CSP_BGA

¹Maximum speed grade is not available with every possible SCLK selection.

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The ADSP-BF523/525/527 processors include an on-chip volt-

age regulator in support of the processor’s dynamic power

management capability. The voltage regulator provides a range

of core voltage levels when supplied from V_DDEXT. The voltage

regulator can be bypassed at the user's discretion.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, the Blackfin processor core contains two

16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,

four video ALUs, and a 40-bit shifter. The computation units

process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

P3

DAG0

P2

P1

P0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation

are supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). If the second ALU is used,

quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

length, and base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 516M bytes of

physical memory.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external

memory spaces.

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTES)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTES)

0xFFC0 0000

RESERVED

0xFFB0 1000

SCRATCHPAD SRAM (4K BYTES)

0xFFB0 0000

RESERVED

0xFFA1 4000

INSTRUCTION SRAM / CACHE (16K BYTES)

0xFFA1 0000

RESERVED

0xFFA0 C000

INSTRUCTION BANK B SRAM (16K BYTES)

0xFFA0 8000

INSTRUCTION BANK A SRAM (32K BYTES)

0xFFA0 0000

RESERVED

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTES)

0xFF90 4000

DATA BANK B SRAM (16K BYTES)

0xFF90 0000

RESERVED

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

0xFF80 8000

DATA BANK A SRAM / CACHE (16K BYTES)

0xFF80 4000

DATA BANK A SRAM (16K BYTES)

0xFF80 0000

RESERVED

0xEF00 8000

BOOT ROM (32K BYTES)

0xEF00 0000

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

RESERVED

0x2040 0000

ASYNC MEMORY BANK 3 (1M BYTES)

0x2030 0000

ASYNC MEMORY BANK 2 (1M BYTES)

0x2020 0000

ASYNC MEMORY BANK 1 (1M BYTES)

0x2010 0000

ASYNC MEMORY BANK 0 (1M BYTES)

0x2000 0000

RESERVED

0x08 00 0000

SDRAM MEMORY (16M BYTES

-128M BYTES)

0x0000 0000

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

Figure 3. Internal/External Memory Map

Internal (On-Chip) Memory

The processor has three blocks of on-chip memory providing

high-bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both cache and SRAM functional-

ity. This memory block is accessed at full processor speed.

MEMORY ARCHITECTURE

The Blackfin processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 3.

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

OTP enables developers to store both public and private data

on-chip. In addition to storing public and private key data for

applications requiring security, it also allows developers to store

completely user-definable data such as customer ID, product

ID, MAC address, etc. Hence generic parts can be shipped

which are then programmed and protected by the developer

within this non-volatile memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The SDRAM controller can be programmed to interface to up

to 128M bytes of SDRAM. A separate row can be open for each

SDRAM internal bank and the SDRAM controller supports up

to 4 internal SDRAM banks, improving overall performance.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks are only contiguous if each is fully populated

with 1M byte of memory.

I/O Memory Space

The processor does not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory-mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

NAND Flash Controller (NFC)

The ADSP-BF522/524/526 and ADSP-BF523/525/527 proces-

sors provide a NAND flash controller (NFC). NAND flash

devices provide high-density, low-cost memory. However,

NAND flash devices also have long random access times, invalid

blocks, and lower reliability over device lifetimes. Because of

this, NAND flash is often used for read-only code storage. In

this case, all DSP code can be stored in NAND flash and then

transferred to a faster memory (such as SDRAM or SRAM)

before execution. Another common use of NAND flash is for

storage of multimedia files or other large data segments. In this

case, a software file system may be used to manage reading and

writing of the NAND flash device. The file system selects mem-

ory segments for storage with the goal of avoiding bad blocks

and equally distributing memory accesses across all address

locations. Hardware features of the NFC include:

• Support for page program, page read, and block erase of

NAND flash devices, with accesses aligned to page

boundaries.

• Error checking and correction (ECC) hardware that facili-

tates error detection and correction.

• A single 8-bit external bus interface for commands,

addresses and data.

• Support for SLC (single level cell) NAND flash devices

unlimited in size, with page sizes of 256 and 512 bytes.

Larger page sizes can be supported in software.

Booting

The processor contains a small on-chip boot kernel, which con-

figures the appropriate peripheral for booting. If the processor is

configured to boot from boot ROM memory space, the proces-

sor starts executing from the on-chip boot ROM. For more

information, see Booting Modes on Page 18.

Event Handling

The event controller on the processor handles all asynchronous

and synchronous events to the processor. The processor pro-

vides event handling that supports both nesting and

prioritization. Nesting allows multiple event service routines to

be active simultaneously. Prioritization ensures that servicing of

a higher-priority event takes precedence over servicing of a

lower-priority event. The controller provides support for five

different types of events:

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• RESET – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Exceptions – Events that occur synchronously to program

flow (in other words, the exception is taken before the

instruction is allowed to complete). Conditions such as

data alignment violations and undefined instructions cause

exceptions.

• Capability of releasing external bus interface pins during

long accesses.

• Support for internal bus requests of 16-bits

• DMA engine to transfer data between internal memory and

NAND flash device.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input signals, timers, and other

peripherals, as well as by an explicit software instruction.

One-Time Programmable Memory

The processor has 64K bits of one-time programmable non-vol-

atile memory that can be programmed by the developer only

one time. It includes the array and logic to support read access

and programming. Additionally, its pages can be write

protected.

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The processor event controller consists of two stages, the core

event controller (CEC) and the system interrupt controller

(SIC). The core event controller works with the system interrupt

controller to prioritize and control all system events. Conceptu-

ally, interrupts from the peripherals enter into the SIC and are

then routed directly into the general-purpose interrupts of the

CEC.

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class

EVT Entry

EMU

0

Emulation/Test Control

1

RESET

RST

2

Nonmaskable Interrupt

Exception

NMI

3

EVX

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

Core Event Controller (CEC)

7

General-Purpose Interrupt 7

General-Purpose Interrupt 8

General-Purpose Interrupt 9

General-Purpose Interrupt 10

General-Purpose Interrupt 11

General-Purpose Interrupt 12

General-Purpose Interrupt 13

General-Purpose Interrupt 14

General-Purpose Interrupt 15

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority

interrupts (IVG15–14) are recommended to be reserved for

software interrupt handlers, leaving seven prioritized interrupt

inputs to support the peripherals of the processor. Table 2

describes the inputs to the CEC, identifies their names in the

event vector table (EVT), and lists their priorities.

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

System Interrupt Controller (SIC)

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the processor provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the interrupt assignment

registers (SIC_IARx). Table 3 describes the inputs into the SIC

and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

General Purpose

Interrupt (at RESET) Peripheral Interrupt ID

Default

Core Interrupt ID

Peripheral Interrupt Event

PLL Wakeup Interrupt

DMA Error 0 (generic)

DMAR0 Block Interrupt

DMAR1 Block Interrupt

DMAR0 Overflow Error

DMAR1 Overflow Error

PPI Error

SIC Registers

IVG7

IVG8

IVG9

IVG10

0

1

2

3

IAR0 IMASK0, ISR0, IWR0

IAR1 IMASK0, ISR0, IWR0

IAR2 IMASK0, ISR0, IWR0

1

2

3

4

5

6

MAC Status

7

SPORT0 Status

8

SPORT1 Status

9

Reserved

10

11

12

13

14

15

16

17

18

19

20

Reserved

UART0 Status

UART1 Status

RTC

DMA Channel 0 (PPI/NFC)

DMA 3 Channel (SPORT0 RX)

DMA 4 Channel (SPORT0 TX)

DMA 5 Channel (SPORT1 RX)

DMA 6 Channel (SPORT1 TX)

TWI

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Preliminary Technical Data

Table 3. System Interrupt Controller (SIC) (Continued)

General Purpose

Interrupt (at RESET) Peripheral Interrupt ID

Default

Core Interrupt ID

Peripheral Interrupt Event

DMA 7 Channel (SPI)

DMA8 Channel (UART0 RX)

DMA9 Channel (UART0 TX)

DMA10 Channel (UART1 RX)

DMA11 Channel (UART1 TX)

OTP Memory Interrupt

GP Counter

SIC Registers

IVG10

IVG11

IVG12

IVG13

IVG7

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

3

4

5

6

0

3

IAR2 IMASK0, ISR0, IWR0

IAR3 IMASK0, ISR0, IWR0

IAR4 IMASK1, ISR1, IWR1

IAR5 IMASK1, ISR1, IWR1

IAR6 IMASK1, ISR1, IWR1

DMA1 Channel (MAC RX/HOSTDP)

Port H Interrupt A

DMA2 Channel (MAC TX/NFC)

Port H Interrupt B

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

Timer 6

Timer 7

Port G Interrupt A

Port G Interrupt B

MDMA Stream 0

MDMA Stream 1

Software Watchdog Timer

Port F Interrupt A

Port F Interrupt B

SPI Status

NFC Status

IVG7

HOSTDP Status

IVG7

Host Read Done

USB_EINT Interrupt

USB_INT0 Interrupt

USB_INT1 Interrupt

USB_INT2 Interrupt

USB_DMAINT Interrupt

IVG7

IVG10

event has been accepted into the system. This register is

updated automatically by the controller, but it may be writ-

ten only when its corresponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – Controls the

masking and unmasking of individual events. When a bit is

set in the IMASK register, that event is unmasked and is

processed by the CEC when asserted. A cleared bit in the

IMASK register masks the event, preventing the processor

from servicing the event even though the event may be

latched in the ILAT register. This register may be read or

Event Control

The processor provides a very flexible mechanism to control the

processing of events. In the CEC, three registers are used to

coordinate and control events. Each register is 16 bits wide.

• CEC interrupt latch register (ILAT) – Indicates when

events have been latched. The appropriate bit is set when

the processor has latched the event and cleared when the

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ADSP-BF522/523/524/525/526/527

written while in supervisor mode. (Note that general-pur-

pose interrupts can be globally enabled and disabled with

the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

ler. DMA-capable peripherals include the Ethernet MAC, NFC,

HOSTDP, USB, SPORTs, SPI port, UARTs, and PPI. Each indi-

vidual DMA-capable peripheral has at least one dedicated DMA

channel.

The processor DMA controller supports both one-dimensional

(1-D) and two-dimensional (2-D) DMA transfers. DMA trans-

fer initialization can be implemented from registers or from sets

of parameters called descriptor blocks.

The SIC allows further control of event processing by providing

three pairs of 32-bit interrupt control and status registers. Each

register contains a bit corresponding to each of the peripheral

interrupt events shown in Table 3 on Page 7.

• SIC interrupt mask registers (SIC_IMASKx) – Control the

masking and unmasking of each peripheral interrupt event.

When a bit is set in these registers, that peripheral event is

unmasked and is processed by the system when asserted. A

cleared bit in the register masks the peripheral event, pre-

venting the processor from servicing the event.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Examples of DMA types supported by the processor DMA con-

troller include:

• A single, linear buffer that stops upon completion

• SIC interrupt status registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

• SIC interrupt wakeup enable registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled or in sleep mode when the event is generated.

For more information see Dynamic Power Management on

Page 14.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the processor system. This enables trans-

fers of blocks of data between any of the memories—including

external SDRAM, ROM, SRAM, and flash memory—with mini-

mal processor intervention. Memory DMA transfers can be

controlled by a very flexible descriptor-based methodology or

by a standard register-based autobuffer mechanism.

The processor also has an external DMA controller capability

via dual external DMA request pins when used in conjunction

with the external bus interface unit (EBIU). This functionality

can be used when a high speed interface is required for external

FIFOs and high bandwidth communications peripherals such as

USB 2.0. It allows control of the number of data transfers for

memory DMA. The number of transfers per edge is program-

mable. This feature can be programmed to allow memory DMA

to have an increased priority on the external bus relative to the

core.

HOST DMA PORT

The host port interface allows an external host to be a DMA

master to transfer data in and out of the device. The host device

masters the transactions and the Blackfin is the DMA slave.

The host port is enabled through the PAB interface. Once

enabled, the DMA is controlled by the external host, which can

then program the DMA to send/receive data to any valid inter-

nal or external memory location.

The host port interface controller has the following features.

• Allows external master to configure DMA read/write data

transfers and read port status.

DMA CONTROLLERS

The processor has multiple, independent DMA channels that

support automated data transfers with minimal overhead for

the processor core. DMA transfers can occur between the pro-

cessor's internal memories and any of its DMA-capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interfaces, including

the SDRAM controller and the asynchronous memory control-

• Uses asynchronous memory protocol for external interface.

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Preliminary Technical Data

• 8-/16-bit external data interface to host device.

• Half duplex operation

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

• Little-/big-endian data transfer.

• Acknowledge mode allows flow control on host

transactions.

• Interrupt mode guarantees a burst of FIFO depth host

transactions.

RTXI

RTXO

R1

X1

C1

C2

REAL-TIME CLOCK

The real-time clock (RTC) provides a robust set of digital watch

features, including current time, stopwatch, and alarm. The

RTC is clocked by a 32.768 kHz crystal external to the

Blackfin processor. The RTC peripheral has dedicated power

supply pins so that it can remain powered up and clocked even

when the rest of the processor is in a low-power state. The RTC

provides several programmable interrupt options, including

interrupt per second, minute, hour, or day clock ticks, interrupt

on programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

SUGGESTED COMPONENTS:

X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 MΩ

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 4. External Components for RTC

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed

value, with one-second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the processor

from sleep mode upon generation of any RTC wakeup event.

Additionally, an RTC wakeup event can wake up the processor

from deep sleep mode or cause a transition from the hibernate

state.

WATCHDOG TIMER

The processor includes a 32-bit timer that can be used to imple-

ment a software watchdog function. A software watchdog can

improve system availability by forcing the processor to a known

state through generation of a hardware reset, nonmaskable

interrupt (NMI), or general-purpose interrupt, if the timer

expires before being reset by software. The programmer initial-

izes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the pro-

grammed value. This protects the system from remaining in an

unknown state where software, which would normally reset the

timer, has stopped running due to an external noise condition

or software error.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the processor peripherals. After a reset,

software can determine if the watchdog was the source of the

hardware reset by interrogating a status bit in the watchdog

timer control register.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

TIMERS

There are nine general-purpose programmable timer units in

the processors. Eight timers have an external pin that can be

configured either as a pulse width modulator (PWM) or timer

output, as an input to clock the timer, or as a mechanism for

measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the sev-

eral other associated PF pins, an external clock input to the

PPI_CLK input pin, or to the internal SCLK.

The timer units can be used in conjunction with the two UARTs

to measure the width of the pulses in the data stream to provide

a software auto-baud detect function for the respective serial

channels.

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The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the eight general-purpose programmable timers,

a ninth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer, or buffers,

through DMA.

UP/DOWN COUNTER AND THUMBWHEEL

INTERFACE

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

A 32-bit up/down counter is provided that can sense 2-bit

quadrature or binary codes as typically emitted by industrial

drives or manual thumb wheels. The counter can also operate in

general-purpose up/down count modes. Then, count direction

is either controlled by a level-sensitive input pin or by two edge

detectors.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The processors have an SPI-compatible port that enables the

processor to communicate with multiple SPI-compatible

devices.

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three pins have a programmable debouncing circuit.

An internal signal forwarded to the timer unit enables one timer

to measure the intervals between count events. Boundary regis-

ters enable auto-zero operation or simple system warning by

interrupts when programmable count values are exceeded.

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (serial clock, SCK). An SPI

chip select input pin (SPISS) lets other SPI devices select the

processor, and seven SPI chip select output pins (SPISEL7–1) let

the processor select other SPI devices. The SPI select pins are

reconfigured general-purpose I/O pins. Using these pins, the

SPI port provides a full-duplex, synchronous serial interface,

which supports both master/slave modes and multimaster

environments.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA channel,

configurable to support transmit or receive data streams. The

SPI’s DMA channel can only service unidirectional accesses at

any given time.

SERIAL PORTS

The processors incorporate two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

The SPI port’s clock rate is calculated as:

f_SCLK

2 × SPI_BAUD

-----------------------------------

SPI Clock Rate =

Where the 16-bit SPI_BAUD register contains a value of 2

to 65,535.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-bit

first or least-significant-bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

UART PORTS

The processors provide two full-duplex universal asynchronous

receiver/transmitter (UART) ports, which are fully compatible

with PC-standard UARTs. Each UART port provides a simpli-

fied UART interface to other peripherals or hosts, supporting

full-duplex, DMA-supported, asynchronous transfers of serial

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without

additional latencies.

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data. A UART port includes support for five to eight data bits,

one or two stop bits, and none, even, or odd parity. Each UART

port supports two modes of operation:

utilizes two pins for transferring clock (SCL) and data (SDA)

and supports the protocol at speeds up to 400k bits/sec. The

TWI interface pins are compatible with 5 V logic levels.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double-buffered on both transmit and receive.

Additionally, the TWI module is fully compatible with serial

camera control bus (SCCB) functionality for easier control of

various CMOS camera sensor devices.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

Each UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK/16) bits per second.

10/100 ETHERNET MAC

The ADSP-BF526 and ADSP-BF527 processors offer the capa-

bility to directly connect to a network by way of an embedded

Fast Ethernet Media Access Controller (MAC) that supports

both 10-BaseT (10M bits/sec) and 100-BaseT (100M bits/sec)

operation. The 10/100 Ethernet MAC peripheral on the proces-

sor is fully compliant to the IEEE 802.3-2002 standard and it

provides programmable features designed to minimize supervi-

sion, bus use, or message processing by the rest of the processor

system.

Some standard features are:

• Support of MII and RMII protocols for external PHYs.

• Full duplex and half duplex modes.

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

• Data framing and encapsulation: generation and detection

of preamble, length padding, and FCS.

The UART port’s clock rate is calculated as:

f_SCLK

16 × UART_Divisor

• Media access management (in half-duplex operation): col-

lision and contention handling, including control of

retransmission of collision frames and of back-off timing.

• Flow control (in full-duplex operation): generation and

detection of PAUSE frames.

• Station management: generation of MDC/MDIO frames

for read-write access to PHY registers.

• SCLK operating range down to 25 MHz (active and sleep

operating modes).

• Internal loopback from Tx to Rx.

Some advanced features are:

• Buffered crystal output to external PHY for support of a

single crystal system.

• Automatic checksum computation of IP header and IP

payload fields of Rx frames.

• Independent 32-bit descriptor-driven Rx and Tx DMA

channels.

• Frame status delivery to memory via DMA, including

frame completion semaphores, for efficient buffer queue

management in software.

• Tx DMA support for separate descriptors for MAC header

and payload to eliminate buffer copy operations.

• Convenient frame alignment modes support even 32-bit

alignment of encapsulated Rx or Tx IP packet data in mem-

ory after the 14-byte MAC header.

-----------------------------------------------

UART Clock Rate =

Where the 16-bit UART_Divisor comes from the UART_DLH

(most significant 8 bits) and UART_DLL (least significant

8 bits) registers.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

The capabilities of the UARTs are further extended with sup-

port for the infrared data association (IrDA®) serial infrared

physical layer link specification (SIR) protocol.

USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER

The USB OTG controller provides a low-cost connectivity solu-

tion for consumer mobile devices such as cell phones, digital

still cameras and MP3 players, allowing these devices to transfer

data using a point-to-point USB connection without the need

for a PC host. The USBDRC module can operate in a traditional

USB peripheral-only mode as well as the host mode presented

in the On-The-Go (OTG) supplement to the USB 2.0 Specifica-

tion. In host mode, the USB module supports transfers at high-

speed (480Mbps), full-speed (12Mbps), and low-speed

(1.5Mbps) rates. Peripheral-only mode supports the high- and

full-speed transfer rates.

TWI CONTROLLER INTERFACE

The processors include a two wire interface (TWI) module for

providing a simple exchange method of control data between

multiple devices. The TWI is compatible with the widely used

I²C^®bus standard. The TWI module offers the capabilities of

simultaneous master and slave operation, support for both 7-bit

addressing and multimedia data arbitration. The TWI interface

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• Programmable Ethernet event interrupt supports any com-

bination of:

toggle pin values, and one register is written in order to

specify a pin value. Reading the GPIO status register allows

software to interrogate the sense of the pins.

• Any selected Rx or Tx frame status conditions.

• PHY interrupt condition.

• Wakeup frame detected.

• Any selected MAC management counter(s) at half-

full.

• DMA descriptor error.

• GPIO interrupt mask registers – The two GPIO interrupt

mask registers allow each individual GPIO pin to function

as an interrupt to the processor. Similar to the two GPIO

control registers that are used to set and clear individual

pin values, one GPIO interrupt mask register sets bits to

enable interrupt function, and the other GPIO interrupt

mask register clears bits to disable interrupt function.

GPIO pins defined as inputs can be configured to generate

hardware interrupts, while output pins can be triggered by

software interrupts.

• 47 MAC management statistics counters with selectable

clear-on-read behavior and programmable interrupts on

half maximum value.

• Programmable Rx address filters, including a 64-bin

address hash table for multicast and/or unicast frames, and

programmable filter modes for broadcast, multicast, uni-

cast, control, and damaged frames.

• Advanced power management supporting unattended

transfer of Rx and Tx frames and status to/from external

memory via DMA during low-power sleep mode.

• GPIO interrupt sensitivity registers – The two GPIO inter-

rupt sensitivity registers specify whether individual pins are

level- or edge-sensitive and specify—if edge-sensitive—

whether just the rising edge or both the rising and falling

edges of the signal are significant. One register selects the

type of sensitivity, and one register selects which edges are

significant for edge-sensitivity.

• System wakeup from sleep operating mode upon magic

packet or any of four user-definable wakeup frame filters.

• Support for 802.3Q tagged VLAN frames.

• Programmable MDC clock rate and preamble suppression.

• In RMII operation, seven unused pins may be configured

as GPIO pins for other purposes.

PARALLEL PERIPHERAL INTERFACE (PPI)

The processor provides a parallel peripheral interface (PPI) that

can connect directly to parallel A/D and D/A converters, video

encoders and decoders, and other general-purpose peripherals.

The PPI consists of a dedicated input clock pin, up to three

frame synchronization pins, and up to 16 data pins. The input

clock supports parallel data rates up to half the system clock rate

and the synchronization signals can be configured as either

inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bidirectional data transfer with up to 16 bits of

data. Up to three frame synchronization signals are also pro-

vided. In ITU-R 656 mode, the PPI provides half-duplex

bidirectional transfer of 8- or 10-bit video data. Additionally,

on-chip decode of embedded start-of-line (SOL) and start-of-

field (SOF) preamble packets is supported.

PORTS

Because of the rich set of peripherals, the processor groups the

many peripheral signals to four ports—Port F, Port G, Port H,

and Port J. Most of the associated pins are shared by multiple

signals. The ports function as multiplexer controls.

General-Purpose I/O (GPIO)

The processor has 48 bidirectional, general-purpose I/O (GPIO)

pins allocated across three separate GPIO modules—PORTFIO,

PORTGIO, and PORTHIO, associated with Port F, Port G, and

Port H, respectively. Port J does not provide GPIO functional-

ity. Each GPIO-capable pin shares functionality with other

processor peripherals via a multiplexing scheme; however, the

GPIO functionality is the default state of the device upon

power-up. Neither GPIO output nor input drivers are active by

default. Each general-purpose port pin can be individually con-

trolled by manipulation of the port control, status, and interrupt

registers:

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

1. Input mode – Frame syncs and data are inputs into the PPI.

2. Frame capture mode – Frame syncs are outputs from the

PPI, but data are inputs.

• GPIO direction control register – Specifies the direction of

each individual GPIO pin as input or output.

3. Output mode – Frame syncs and data are outputs from the

PPI.

• GPIO control and status registers – The processor employs

a “write one to modify” mechanism that allows any combi-

nation of individual GPIO pins to be modified in a single

instruction, without affecting the level of any other GPIO

pins. Four control registers are provided. One register is

written in order to set pin values, one register is written in

order to clear pin values, one register is written in order to

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

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Preliminary Technical Data

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit and 10-bit

through 16-bit data, programmable in the PPI_CONTROL

register.

CODE SECURITY WITH LOCKBOX SECURE

TECHNOLOGY

A security system consisting of a blend of hardware and soft-

ware provides customers with a flexible and rich set of code

security features with Lockbox secure technology. Key features

include:

• OTP memory

• Unique chip ID

• Code authentication

• Secure mode of operation

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(for frame capture for example). The ADSP-BF522/524/526 and

ADSP-BF523/525/527 processors control when to read from the

video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a

VSYNC output.

Output Mode

The security scheme is based upon the concept of authentica-

tion of digital signatures using standards-based algorithms and

provides a secure processing environment in which to execute

code and protect assets. See Lockbox Secure Technology Dis-

claimer on Page 21.

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

DYNAMIC POWER MANAGEMENT

ITU-R 656 Mode Descriptions

The processor provides four operating modes, each with a dif-

ferent performance/power profile. In addition, dynamic power

management provides the control functions to dynamically alter

the processor core supply voltage, further reducing power dissi-

pation. When configured for a 0 volt core supply voltage, the

processor enters the hibernate state. Control of clocking to each

of the processor peripherals also reduces power consumption.

See Table 4 for a summary of the power settings for each mode.

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

1. Active video only mode

2. Vertical blanking only mode

3. Entire field mode

Active Video Mode

Full-On Operating Mode—Maximum Performance

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in PPI_COUNT register).

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the power-up default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Active Operating Mode—Moderate Dynamic Power

Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured

L1 memories.

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. Data is transferred to or from the

synchronous channels through eight DMA engines that work

autonomously from the processor core.

Table 4. Power Settings

Core

Clock

System

Clock

PLL

Core

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Full On

Active

Enabled No

Enabled/ Yes

Disabled

Enabled Enabled On

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Table 4. Power Settings (Continued)

The Ethernet or USB modules can wake up the internal supply

regulator (ADSP-BF525 and ADSP-BF527 only) or signal an

external regulator to wake up using EXT_WAKE0 or

EXT_WAKE1. If PG15 does not connect as a PHYINT signal to

an external PHY device, PG15 can be pulled low by any other

device to wake the processor up. The processor can also be

woken up by a real-time clock wakeup event or by asserting the

RESET pin. All hibernate wakeup events initiate the hardware

reset sequence. Individual sources are enabled by the VR_CTL

register. The EXT_WAKEx signals are provided to indicate the

occurrence of wakeup events.

Core

Clock

System

Clock

PLL

Core

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Sleep

Enabled

—

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

Deep Sleep Disabled

Hibernate

Disabled

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity wakes up the processor.

When in the sleep mode, asserting a wakeup enabled in the

SIC_IWRx registers causes the processor to sense the value of

the BYPASS bit in the PLL control register (PLL_CTL). If

BYPASS is disabled, the processor transitions to the full on

mode. If BYPASS is enabled, the processor transitions to the

active mode.

As long as V_DDEXTis applied, the VR_CTL register maintains its

state during hibernation. All other internal registers and memo-

ries, however, lose their content in the hibernate state. State

variables may be held in external SRAM or SDRAM. The SCK-

ELOW bit in the VR_CTL register controls whether or not

SDRAM operates in self-refresh mode, which allows it to retain

its content while the processor is in hibernate and through the

subsequent reset sequence.

Power Savings

System DMA access to L1 memory is not supported in

sleep mode.

As shown in Table 5, the processor supports six different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions. By isolating

the internal logic of the processor into its own power domain,

separate from the RTC and other I/O, the processor can take

advantage of dynamic power management without affecting the

RTC or other I/O devices. There are no sequencing require-

ments for the various power domains, but all domains must be

powered according to the appropriate Specifications table for

processor Operating Conditions; even if the feature/peripheral

is not used.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

such as the RTC, may still be running but cannot access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, an RTC asynchronous interrupt causes the proces-

sor to transition to the Active mode. Assertion of RESET while

in deep sleep mode causes the processor to transition to the full

on mode.

Table 5. Power Domains

Power Domain

V_DDRange

All internal logic, except RTC, Memory, USB, OTP V_DDINT

RTC internal logic and crystal I/O

Memory logic

V_DDRTC

V_DDMEM

V_DDUSB

V_DDOTP

V_DDEXT

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all of

the synchronous peripherals (SCLK). The internal voltage regu-

lator (ADSP-BF523/525/527 only) for the processor can be shut

off by writing b#00 to the FREQ bits of the VR_CTL register.

This setting sets the internal power supply voltage (V_DDINT) to

0 V to provide the lowest static power dissipation. Any critical

information stored internally (for example, memory contents,

register contents, and other information) must be written to a

non-volatile storage device prior to removing power if the pro-

cessor state is to be preserved. Writing b#00 to the FREQ bits

also causes EXT_WAKE0 and EXT_WAKE1 to transition low,

which can be used to signal an external voltage regulator to shut

down.

USB PHY logic

OTP logic

All other I/O

The dynamic power management feature of the processor

allows both the processor’s input voltage (V_DDINT) and clock fre-

quency (f_CCLK) to be dynamically controlled.

The power dissipated by a processor is largely a function of its

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation, while reducing the

voltage by 25% reduces dynamic power dissipation by more

than 40%. Further, these power savings are additive, in that if

the clock frequency and supply voltage are both reduced, the

power savings can be dramatic, as shown in the following

equations.

Since V_DDEXTand V_DDMEMcan still be supplied in this mode, all

of the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

still have power applied without drawing unwanted current.

Rev. PrE

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The voltage regulator has two modes set by the VR_SELpin—the

normal pulse width control of an external FET and the external

supply mode which can signal a power down during hibernate

to an external regulator. Set VR_SELto V_DDEXTto use an external

regulator or set VR_SELto GND to use the internal regulator. In

the external mode VR_OUTbecomes EXT_WAKE1. If the internal

regulator is used, EXT_WAKE0 can control other power

sources in the system during the hibernate state. Both signals

are high-true for power-up and may be connected directly to the

low-true shut down input of many common regulators. The

mode of the SS/PG (Soft Start/Power Good) signal also changes

according to the state of VR_SEL. When using an internal regula-

tor, the SS/PG pin is Soft Start, and when using an external

regulator, it is Power Good. The Soft Start feature is recom-

mended to reduce the inrush currents and to reduce V_DDINT

voltage overshoot when coming out of hibernate or changing

voltage levels. The Power Good (PG) input signal allows the

processor to start only after the internal voltage has reached a

chosen level. In this way, the startup time of the external regula-

tor is detected after hibernation. For a complete description of

Soft Start and Power Good functionality, refer to the ADSP-

BF52x Blackfin Processor Hardware Reference.

Power Savings Factor

2

f_CCLKRED

-------------------------

f_CCLKNOM

V_DDINTRED

-------------------------------

V_DDINTNOM

T_RED

--------------

T_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

% Power Savings = (1 – Power Savings Factor) × 100%

where the variables in the equations are:

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

V

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

T

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

ADSP-BF523/525/527 VOLTAGE REGULATION

The ADSP-BF523/525/527 provides an on-chip voltage regula-

tor that can generate processor core voltage levels from an

external supply. Figure 5 shows the typical external components

required to complete the power management system. The regu-

lator controls the internal logic voltage levels and is

ADSP-BF522/524/526 VOLTAGE REGULATION

The ADSP-BF522/524/526 processor requires an external volt-

age regulator to power the V_DDINTdomain. To reduce standby

power consumption, the external voltage regulator can be sig-

naled through EXT_WAKE0 or EXT_WAKE1 to remove power

from the processor core. These identical signals are high-true

for power-up and may be connected directly to the low-true

shut down input of many common regulators. While in the

programmable with the voltage regulator control register

(VR_CTL) in increments of 50 mV. To reduce standby power

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while keeping I/O power

supplied. While in the hibernate state, all external supplies

(V_DDEXT, V_DDMEM, V_DDUSB, V_DDOTP) can still be applied, eliminat-

ing the need for external buffers. V_DDRTCmust be applied at all

times for correct hibernate operation. The voltage regulator can

be activated from this power down state either through an RTC

wakeup, a USB wakeup, an ethernet wakeup, or by asserting the

RESET pin, each of which then initiates a boot sequence. The

regulator can also be disabled and bypassed at the user’s

discretion.

hibernate state, all external supplies (V_DDEXT, V_DDMEM, V_DDUSB

,

V_DDOTP) can still be applied, eliminating the need for external

buffers. V_DDRTCmust be applied at all times for correct hibernate

operation. The external voltage regulator can be activated from

this power down state either through an RTC wakeup, a USB

wakeup, an ethernet wakeup, or by asserting the RESET pin,

each of which then initiates a boot sequence. EXT_WAKE0 or

EXT_WAKE1 indicate a wakeup to the external voltage regula-

tor. The Power Good (PG) input signal allows the processor to

start only after the internal voltage has reached a chosen level. In

this way, the startup time of the external regulator is detected

after hibernation. For a complete description of the Power Good

functionality, refer to the ADSP-BF52x Blackfin Processor Hard-

ware Reference.

SET OF DECOUPLING

CAPACITORS

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

V

DDEXT

(LOW-INDUCTANCE)

V

DDEXT

+

100μF

10μH

100μF

+

100nF

DDINT

CLOCK SIGNALS

+

FDS9431A

The processor can be clocked by an external crystal, a sine wave

input, or a buffered, shaped clock derived from an external

clock oscillator.

SS/PG

10μF

LOW ESR

ZHCS1000 100μF

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

VR

OUT

SHORT AND LOW-

INDUCTANCE WIRE

EXT_WAKE1

SEE H/W REFERENCE,

SYSTEM DESIGN CHAPTER,

TO DETERMINE VALUE

VR

SEL

GND

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

Figure 5. ADSP-BF523/525/527 Voltage Regulator Circuit

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 6. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins. The on-

chip resistance between CLKIN and the XTAL pin is in the 500

kΩ range. Further parallel resistors are typically not recom-

mended. The two capacitors and the series resistor shown in

Figure 6 fine tune phase and amplitude of the sine frequency.

The capacitor and resistor values shown in Figure 6 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 7, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 0.5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 10×, but it can be modi-

fied by a software instruction sequence.

On-the-fly frequency changes can be effected by simply writing

to the PLL_DIV register. The maximum allowed CCLK and

SCLK rates depend on the applied voltages V_DDINT, V_DDEXT, and

V_DDMEM; the VCO is always permitted to run up to the frequency

specified by the part’s speed grade. The CLKOUT pin reflects

the SCLK frequency to the off-chip world. It is part of the

SDRAM interface, but it functions as a reference signal in other

timing specifications as well. While active by default, it can be

disabled using the EBIU_SDGCTL and EBIU_AMGCTL

registers.

BLACKFIN

CLKOUT

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“CO ARSE” ADJUSTMENT

TO PLL CIRCUITRY

ON-THE-FLY

EN

CLKBUF

÷ 1, 2, 4, 8

CCLK

PLL

0.5× to 64×

CLKIN

EN

VCO

SCLK

÷ 1 to 15

CLKIN

XTAL

330⍀*

FOR OVERTONE

OPERATION ONLY:

SCLK ≤ CCLK

SCLK ≤ 133 MHz

18 pF*

Figure 7. Frequency Modification Methods

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

Figure 6. External Crystal Connections

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 6. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

Table 6. Example System Clock Ratios

The CLKBUF pin is an output pin, which is a buffered version

of the input clock. This pin is particularly useful in Ethernet

applications to limit the number of required clock sources in the

system. In this type of application, a single 25 MHz or 50 MHz

crystal may be applied directly to the processor. The 25 MHz or

50 MHz output of CLKBUF can then be connected to an exter-

nal Ethernet MII or RMII PHY device. If instead of a crystal, an

external oscillator is used at CLKIN, CLKBUF will not have the

40/60 duty cycle required by some devices. The CLKBUF output

is active by default and can be disabled for power savings rea-

sons using the VR_CTL register.

Example Frequency Ratios

(MHz)

VCO

100

Signal Name Divider Ratio

SSEL3–0

VCO/SCLK

SCLK

100

50

0001

1:1

0110

6:1

300

1010

10:1

500

50

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ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

pins of the reset configuration register, sampled during power-

on resets and software-initiated resets, implement the modes

shown in Table 8.

Table 8. Booting Modes

BMODE3–0 Description

Table 7. Core Clock Ratios

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

Idle - No boot

Example Frequency Ratios

Boot from 8- or 16-bit external flash memory

Boot from 16-bit asynchronous FIFO

Boot from serial SPI memory (EEPROM or flash)

Boot from SPI host device

Boot from serial TWI memory (EEPROM/flash)

Boot from TWI host

(MHz)

VCO

300

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

300

500

200

Boot from UART0 Host

Boot from UART1 Host

The maximum CCLK frequency not only depends on the part's

speed grade (see Page 72), it also depends on the applied V_DDINT

voltage. See Table 12 and Table 15 for details. The maximal sys-

tem clock rate (SCLK) depends on the chip package and the

applied V_DDINT, V_DDEXT, and V_DDMEMvoltages (see Table 14 and

Table 17).

Reserved

Boot from SDRAM

Boot from OTP memory

Boot from 8-bit NAND flash

via NFC using PORTF data pins

BOOTING MODES

1101

Boot from 8-bit NAND flash

via NFC using PORTH data pins

The processor has several mechanisms (listed in Table 8) for

automatically loading internal and external memory after a

reset. The boot mode is defined by four BMODE input pins

dedicated to this purpose. There are two categories of boot

modes. In master boot modes the processor actively loads data

from parallel or serial memories. In slave boot modes the pro-

cessor receives data from external host devices.

The boot modes listed in Table 8 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest meaningful configuration settings. Default settings

can be altered via the initialization code feature at boot time or

by proper OTP programming at pre-boot time. The BMODE

1110

1111

Boot from 16-Bit Host DMA

Boot from 8-Bit Host DMA

• Idle/no boot mode (BMODE = 0x0) — In this mode, the

processor goes into idle. The idle boot mode helps recover

from illegal operating modes, such as when the OTP mem-

ory has been misconfigured.

• Boot from 8-bit or 16-bit external flash memory

(BMODE = 0x1) — In this mode, the boot kernel loads the

first block header from address 0x2000 0000, and (depend-

ing on instructions contained in the header) the boot

kernel performs an 8- or 16-bit boot or starts program exe-

cution at the address provided by the header. By default, all

configuration settings are set for the slowest device possible

(3-cycle hold time, 15-cycle R/W access times, 4-cycle

setup).

The ARDY is not enabled by default, but it can be enabled

through OTP programming. Similarly, all interface behav-

ior and timings can be customized through OTP

programming. This includes activation of burst-mode or

page-mode operation. In this mode, all asynchronous

interface signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2) —

In this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that the boot kernel has to

read from the FIFO must be requested by placing a low

pulse on the DMAR1 pin.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3) — 8-, 16-, 24-, or 32-bit addressable

devices are supported. The processor uses the PG1 GPIO

pin to select a single SPI EEPROM/flash device and sub-

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Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

mits a read command and successive address bytes (0x00)

until a valid 8-, 16-, 24-, or 32-bit addressable device is

detected. Pull-up resistors are required on the SPISEL1 and

MISO pins. By default, a value of 0x85 is written to the

SPI_BAUD register.

• Boot from SDRAM (BMODE = 0xA) This is a warm boot

scenario, where the boot kernel starts booting from address

0x0000 0010. The SDRAM is expected to contain a valid

boot stream and the SDRAM controller must be configured

by the OTP settings.

• Boot from SPI host device (BMODE = 0x4) — The proces-

sor operates in SPI slave mode and is configured to receive

the bytes of the LDR file from an SPI host (master) agent.

The HWAIT signal must be interrogated by the host before

every transmitted byte. A pull-up resistor is required on the

SPISS input. A pull-down on the serial clock (SCK) may

improve signal quality and booting robustness.

• Boot from OTP memory (BMODE = 0xB) — This provides

a stand-alone booting method. The boot stream is loaded

from on-chip OTP memory. By default, the boot stream is

expected to start from OTP page 0x40 and can occupy all

public OTP memory up to page 0xDF. This is 2560 bytes.

Since the start page is programmable, the maximum size of

the boot stream can be extended to 3072 bytes.

• Boot from serial TWI memory, EEPROM/flash

(BMODE = 0x5) — The processor operates in master mode

and selects the TWI slave connected to the TWI with the

unique ID 0xA0.

Table 9. Fourth Byte for Large Page Devices

Bit

D1:D0 Page Size

(excluding spare area)

Parameter

Value Meaning

00

01

10

11

1K byte

2K byte

4K byte

8K byte

The processor submits successive read commands to the

memory device starting at internal address 0x0000 and

begins clocking data into the processor. The TWI memory

device should comply with the Philips I²C^®Bus Specifica-

tion version 2.1 and should be able to auto-increment its

internal address counter such that the contents of the

memory device can be read sequentially. By default, a

PRESCALE value of 0xA and a TWI_CLKDIV value of

0x0811 are used. Unless altered by OTP settings, an I²C

memory that takes two address bytes is assumed. The

development tools ensure that data booted to memories

that cannot be accessed by the Blackfin core is written to an

intermediate storage location and then copied to the final

destination via memory DMA.

D2

Spare Area Size

00

01

8 byte/512 byte

16 byte/512 byte

D5:D4 Block Size

(excluding spare area)

00

01

10

11

64K byte

128K byte

256K byte

512K byte

D6

Bus width

00

01

x8

not supported

D3, D7 Not Used for configuration

• Boot from TWI host (BMODE = 0x6) — The TWI host

selects the slave with the unique ID 0x5F.

The processor replies with an acknowledgement and the

host then downloads the boot stream. The TWI host agent

should comply with the Philips I²C Bus Specification

version 2.1. An I²C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

• Boot from UART0 host on Port G (BMODE = 0x7) —

Using an autobaud handshake sequence, a boot-stream for-

matted program is downloaded by the host. The host

selects a bit rate within the UART clocking capabilities.

• Boot from 8-bit external NAND flash memory (BMODE =

0xC and BMODE = 0xD) — In this mode, auto detection of

the NAND flash device is performed.

BMODE = 0xC, the processor configures PORTF GPIO

pins PF7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

BMODE = 0xD, the processor configures PORTH GPIO

pins PH7:0 for the NAND data pins and PORTH pins

PH15:10 for the NAND control signals.

For correct device operation pull-up resistors are required

on both ND_CE (PH10) and ND_BUSY (PH13) signals. By

default, a value of 0x0033 is written to the NFC_CTL regis-

ter. The booting procedure always starts by booting from

byte 0 of block 0 of the NAND flash device.

When performing the autobaud, the UART expects a “@”

(0x40) character (eight bits data, one start bit, one stop bit,

no parity bit) on the UART0RX pin to determine the bit

rate. The UART then replies with an acknowledgement

composed of 4 bytes (0xBF, the value of UART0_DLL, the

value of UART0_DLH, then 0x00). The host can then

download the boot stream. To hold off the host the Blackfin

processor signals the host with the boot host wait

(HWAIT) signal. Therefore, the host must monitor

HWAIT before every transmitted byte.

• Boot from UART1 host on Port F (BMODE = 0x8). Same

as BMODE = 0x7 except that the UART1 port is used.

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Preliminary Technical Data

NAND flash boot supports the following features:

—Device Auto Detection

—Error Detection & Correction for maximum reliability

—No boot stream size limitation

—Peripheral DMA providing efficient transfer of all data

(excluding the ECC parity data)

—Software-configurable boot mode for booting from

boot streams spanning multiple blocks, including bad

blocks

• Boot from 16-Bit Host DMA (BMODE = 0xE) — In this

mode, the host DMA port is configured in 16-bit Acknowl-

edge mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. After completing the

configuration, the host is required to poll the READY bit in

HOST_STATUS before beginning to transfer data. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to address 0xFFA0 0000. It is the

host's responsibility to ensure that valid code has been

placed at this address. The routine at 0xFFA0 0000 can be a

simple initialization routine to configure internal

resources, such as the SDRAM controller, which then

returns using an RTS instruction. The routine may also by

the final application, which will never return to the boot

kernel.

—Software-configurable boot mode for booting from

multiple copies of the boot stream, allowing for han-

dling of bad blocks and uncorrectable errors

—Configurable timing via OTP memory

Small page NAND flash devices must have a 512-byte page

size, 32 pages per block, a 16-byte spare area size, and a bus

configuration of 8 bits. By default, all read requests from

the NAND flash are followed by four address cycles. If the

NAND flash device requires only three address cycles, the

device must be capable of ignoring the additional address

cycles.

• Boot from 8-Bit Host DMA (BMODE = 0xF) — In this

mode, the Host DMA port is configured in 8-bit interrupt

mode, with little endian data formatting. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the Host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the Host DMA Port. The host will receive an

interrupt from the HOST_ACK signal every time it is

allowed to send the next FIFO depths worth (sixteen 32-bit

words) of information. When the host sends an HIRQ con-

trol command, the boot kernel issues a CALL instruction to

address 0xFFA0 0000. It is the host's responsibility to

ensure valid code has been placed at this address. The rou-

tine at 0xFFA0 0000 can be a simple initialization routine

to configure internal resources, such as the SDRAM con-

troller, which then returns using an RTS instruction. The

routine may also by the final application, which will never

return to the boot kernel.

For each of the boot modes, a 16-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the address stored in the EVT1 register.

Prior to booting, the pre-boot routine interrogates the OTP

memory. Individual boot modes can be customized or even dis-

abled based on OTP programming. External hardware,

especially booting hosts, may watch the HWAIT signal to deter-

mine when the pre-boot has finished and the boot kernel starts

the boot process. By programming OTP memory, the user can

The small page NAND flash device must comply with the

following command set:

—Reset: 0xFF

—Read lower half of page: 0x00

—Read upper half of page: 0x01

—Read spare area: 0x50

For large-page NAND-flash devices, the four-byte elec-

tronic signature is read in order to configure the kernel for

booting, which allows support for multiple large-page

devices. The fourth byte of the electronic signature must

comply with the specification in Table 9.

Any NAND flash array configuration from Table 9, exclud-

ing 16-bit devices, that also complies with the command set

listed below are directly supported by the boot kernel.

There are no restrictions on the page size or block size as

imposed by the small-page boot kernel.

For devices consisting of a five-byte signature, only four are

read. The fourth must comply as outlined above.

Large page devices must support the following command

set:

—Reset: 0xFF

—Read Electronic Signature: 0x90

—Read: 0x00, 0x30 (confirm command)

Large-page devices must not support or react to NAND

flash command 0x50. This is a small-page NAND flash

command used for device auto detection.

By default, the boot kernel will always issue five address

cycles; therefore, if a large page device requires only four

cycles, the device must be capable of ignoring the addi-

tional address cycles.

Rev. PrE

|

Page 20 of 72

|

August 2008

Preliminary Technical Data

ADSP-BF522/523/524/525/526/527

also instruct the pre-boot routine to customize the PLL, Internal

Voltage Regulator (ADSP-BF523/525/527 only), SDRAM Con-

troller, and Asynchronous Memory Controller.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

later case. Bits 6-4 in the system reset configuration (SYSCR)

register can be used to bypass the pre-boot routine and/or boot

kernel in case of a software reset. They can also be used to simu-

late a wakeup-from-hibernate boot in the software reset case.

DEVELOPMENT TOOLS

The processor is supported with a complete set of

CROSSCORE® software and hardware development tools,

including Analog Devices emulators and VisualDSP++® devel-

opment environment. The same emulator hardware that

supports other Blackfin processors also fully emulates the

ADSP-BF522/524/526 and ADSP-BF523/525/527 processors.

EZ-KIT Lite® Evaluation Board

For evaluation of ADSP-BF523/525/527 processors, use the

ADSP-BF527 EZ-KIT Lite board available from Analog Devices.

Order part number ADZS-BF527-EZLITE. The board comes

with on-chip emulation capabilities and is equipped to enable

software development. Multiple daughter cards are available.

An ADSP-BF526 EZ-KIT Lite board is under development.

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to configure

the SDRAM controller or to speed up booting by managing the

PLL, clock frequencies, wait states, or serial bit rates.

The boot ROM also features C-callable function that can be

called by the user application at run time. This enables second-

stage boot or boot management schemes to be implemented

with ease.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD (TARGET)

The Analog Devices family of emulators are tools that every sys-

tem developer needs in order to test and debug hardware and

software systems. Analog Devices has supplied an IEEE 1149.1

JTAG Test Access Port (TAP) on each JTAG processor. The

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on

system timing.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core

processor resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see (EE-68) Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.analog.com)—

use site search on “EE-68.” This document is updated regularly

to keep pace with improvements to emulator support.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded

in 16 bits.


型号：	ADSP-BF527BBCZ-5AX
厂家：	ADI
描述：	IC 0-BIT, 133 MHz, OTHER DSP, PBGA208, 17 X 17 MM, MO-205AM, CSPBGA-289, Digital Signal Processor
文件：	总72页 (文件大小：1642K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF527BBCZ-5AX [ADI]

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