ADSP-BF527KBCZ-6C2 [ADI]
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| 型号： | ADSP-BF527KBCZ-6C2 |
| 厂家： | 
ADI |
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Blackfin Embedded
Processor with Codec
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
PROCESSOR FEATURES
EMBEDDED CODEC FEATURES
Up to 600 MHz high performance Blackfin processor
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See operating conditions in the published
ADSP-BF52x processor data sheet.
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527processors only)
Embedded low power audio codec
Stereo, 24-bit ADCs and DACs
DAC SNR: 100 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Stereo line input and monaural microphone input
Low power
7 mW stereo playback (1.8 V supply)
14 mW record and playback (1.8 V supply)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V min
Digital I/O: 1.8 V to 3.6 V
289-ball (12 mm x 12 mm) CSP_BGA package
132K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
256 × fS /384 × fS oversampling rate in normal mode;
250 × fS/272 × fS oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
PERIPHERALS
Memory management unit providing memory protection
2 dual-channel memory DMA controllers
See the published ADSP-BF52x processor data sheet for
additional peripherals
WATCHDOG TIMER
OTP MEMORY
RTC
VOLTAGE REGULATOR*
JTAG TEST AND EMULATION
PERIPHERAL
COUNTER
SPORT0
SPORT1
ACCESS BUS
INTERRUPT
CONTROLLER
GPIO
PORT F
UART1
UART0
NFC
B
L1 INSTRUCTION
MEMORY
L1 DATA
MEMORY
GPIO
DMA
PPI
PORT G
CONTROLLER
DMA
ACCESS
BUS
EAB
16
CODEC
SPI
DCB
USB
TIMER7-1
TIMER0
GPIO
PORT H
DEB
BOOT
ROM
EXTERNAL PORT
FLASH, SDRAM CONTROL
EMAC
HOST DMA
TWI
PORT J
*REGULATOR AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS ONLY
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2010 Analog Devices, Inc. All rights reserved.
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
TABLE OF CONTENTS
Processor Features ................................................... 1
Embedded Codec Features ......................................... 1
Peripherals ............................................................. 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Codec Description ................................................ 3
ADC and DAC ..................................................... 4
ADC High-Pass and DAC De-Emphasis Filters ............ 4
Analog Audio Interfaces ......................................... 4
Stereo Line and Monaural Microphone Inputs .......... 4
Bypass and Sidetone Paths to Output ...................... 5
Line and Headphone Outputs ............................... 5
Digital Audio Interface ........................................... 6
Recording Mode ................................................ 8
Playback Mode .................................................. 8
Digital Audio Data Sampling Rate .......................... 8
Software Control Interface .................................... 11
Codec Pin Descriptions ........................................... 12
Register Details ..................................................... 15
Bit Descriptions .................................................. 16
Specifications ........................................................ 21
Operating Conditions ........................................... 21
Codec Electrical Characteristics .............................. 21
Absolute Maximum Ratings ................................... 23
ESD Sensitivity ................................................... 23
Package Information ............................................ 23
Power Consumption ............................................ 24
Timing Specifications ........................................... 25
TWI Timing ................................................... 25
SPI Timing ..................................................... 26
Digital Audio Interface Slave Mode Timing ............ 27
Digital Audio Interface Master Mode Timing .......... 28
System Clock Timing ........................................ 29
Digital Filter Characteristics ................................ 30
Converter Filter Response ..................................... 30
Digital De-Emphasis ............................................ 31
289-Ball CSP_BGA Ball Assignment ........................ 32
Outline Dimensions ................................................ 35
Ordering Guide ..................................................... 36
REVISION HISTORY
3/10—Rev. 0 to Rev. A
Revised the following figures.
Recommended Application Circuit Using SPI Control .... 13
Recommended Application Circuit Using TWI Control .. 14
Added Sampling Rate = 48 kHz to all figures in
Converter Filter Response ........................................ 30
Revised Ordering Guide .......................................... 36
Rev. A
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ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
GENERAL DESCRIPTION
This document describes the differences between the
ADSP-BF52xC and the ADSP-BF52x standard Blackfin® prod-
uct. Please refer to the published ADSP-BF52x data sheet for
general description and specifications. This document only
describes the differences from that data sheet.
The codec software-programmable stereo output options
provide the programmer with many application possibilities
because the device can be used as a headphone driver or as a
speaker driver. Its volume control functions provide a large
range of gain control of the audio signal.
The ADSP-BF52xC processors add a low power, high quality
stereo audio codec for portable digital audio applications with
one set of stereo programmable gain amplifier (PGA) line
inputs and one monaural microphone input. It features two 24-
bit analog-to-digital converter (ADC) channels and two 24-bit
digital-to-analog (DAC) converter channels.
The codec can operate as a master or a slave. It supports various
master clock frequencies, including 12 MHz or 24 MHz for USB
devices; standard 256 × fS or 384 × fS based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sam-
pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,
24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
CODEC DESCRIPTION
The ADSP-BF52xC codec contains a central clock source, called
the codec master clock (CODEC_MCLK) that produces a refer-
ence clock for all internal audio data processing and synch-
ronization. When using an external clock source to drive the
CODEC_MCLK pin, care should be taken to select a clock
source with less than 50 ps of jitter. Without careful generation
of the CODEC_MCLK signal, the digital audio quality
will suffer.
To enable the codec to generate the central reference clock
in a system, connect a crystal oscillator between the XTI/
CODEC_MCLK input pin and the XTO output pin.
The codec can operate at power supplies as low as 1.8 V for the
analog circuitry and as low as 1.8 V for the digital circuitry. The
maximum voltage supply is 3.6 V for all supplies.
CSB
CSDA CSCL CMODE
AVDD
CONTROL INTERFACE
HPVDD
HPGND
VMID
CODEC
AGND
MUTE
ATTEN/
MUTE
VOLUME/
MUTE
HEADPHONE
DRIVER
MICBIAS
RLINEIN
RHPOUT
VOLUME
VOLUME
MUTE
MUTE
MUX
MUX
ADC
ADC
DAC
DAC
MUTE
MUTE
Σ
Σ
ROUT
LOUT
MIC
BOOST
DIGITAL
FILTERS
MICIN
MUTE
MUTE
LLINEIN
HEADPHONE
DRIVER
VOLUME/
MUTE
LHPOUT
ATTEN/
MUTE
MUTE
OSCPD
OSC
CLKOUT
DIVIDER
CLKIN
DIVIDER
DIGITAL AUDIO INTERFACE
XTO
Figure 1. Codec Block Diagram
Rev. A
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ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
To allow an external device to generate the central reference
clock, apply the external clock signal directly through the XTI/
CODEC_MCLK input pin. In this configuration, the oscillator
circuit of the codec can be powered down by using the OSCPD
bit (Register R6, Bit D5) to reduce power consumption.
To accommodate applications with very high frequency master
clocks, the internal core reference clock of the codec can be set
to either CODEC_MCLK or CODEC_MCLK divided by 2. This
is enabled by adjusting the setting of the CLKDIV2 bit (Register
R8, Bit D6). The CODEC_CLKOUT pin can also drive external
clock sources with either the codec clock signal or codec clock
divided by 2 by enabling the CLKODIV2 bit (Register R8,
Bit D7).
ANALOG AUDIO INTERFACES
The codec includes stereo single-ended line inputs and a mon-
aural microphone input to the on-board ADC. Either the line
inputs or the microphone input, but not both simultaneously,
can be connected to the ADC by setting the INSEL bit (Register
R4, Bit D2).
The codec also includes line and headphone outputs from the
on-board DAC. The line or microphone inputs can be routed
and mixed directly to the output terminals.
Stereo Line and Monaural Microphone Inputs
The single-ended stereo line inputs (RLINEIN and LLINEIN)
are internally biased to VMID by way of a voltage divider
between AVDD and AGND (see Figure 2). The line input signal
can be connected to the internal ADC and, if desired, routed
directly to the outputs via the bypass path by using the BYPASS
bit (Register R4, Bit D3).
ADC AND DAC
The codec contains a pair of oversampling Σ-Δ ADCs. The
maximum ADC full-scale input level is 1.0 Vrms when
AVDD = 3.3 V. If the input signal to the ADC exceeds this
level, data overloading occurs and causes audible distortion.
The ADC can accept analog audio input from either the stereo
line inputs or the monaural microphone input. Note that the
ADC can only accept input from a single source, so the pro-
grammer must choose either the line inputs or the microphone
input using the INSEL bit (Register R4, Bit D2). The digital data
from the ADC output, once converted, is processed using the
ADC filters.
RLINEIN
or
LLINEIN
AVDD
–
+
ADC
OR
BYPASS
VMID
Complementary to the Σ-Δ ADC channels, the codec contains a
pair of oversampling DACs that convert the digital audio data
from the internal DAC filters into an analog audio signal. The
DAC output can also be muted by setting the DACMU bit (Reg-
ister R5, Bit D3) in the control register.
INTERNAL CIRCUITRY
AGND
Figure 2. Line Input to ADC
The line input volume can be adjusted from –34.5 dB to +33 dB
in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0
to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits. By
default the volume is independently adjustable for both right
and left line inputs. However, if the LRINBOTH or RLINBOTH
bit is programmed, both LINVOL and RINVOL are loaded with
the same value. The programmer can also set the LINMUTE
(Register R0, Bit D7) and RINMUTE (Register R1, Bit D7) bits
to mute the line input signal to the ADC.
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The ADC and DAC employ separate digital filters that perform
24-bit signal processing. The digital filters are used for both
record and playback modes and are optimized for each individ-
ual sampling rate used.
For recording mode operations, the unprocessed data from the
ADC enters the ADC filters and is converted to the appropriate
sampling frequency, then is output to the digital audio interface.
For playback mode operations, the DAC filters convert the digi-
tal audio interface data to oversampled data using a sampling
rate selected by the programmer. The oversampled data is pro-
cessed by the DAC and sent to the analog output mixer by
enabling the DACSEL (Register R4, Bit D4).
Programmers have the option of setting up the device so that
any dc offset in the input source signal is automatically detected
and removed. To accomplish this, enable the digital high-pass
filter (see Table 22 on Page 30 for characteristics) contained in
the ADC digital filters by using the ADCHPD bit (Register R5,
Bit D0).
The high impedance, low capacitance monaural microphone
input pin (MICIN, shown in Figure 3 ) has two gain stages and a
microphone bias level (MICBIAS) that is internally biased to the
VMID voltage level by way of a voltage divider between AVDD
and AGND. The microphone input signal can be connected to
the internal ADC and, if desired, routed directly to the outputs
via the sidetone path by using the SIDETONE bit (Register R4,
Bit D5).
In addition, programmers can implement digital de-emphasis
by using the DEEMPH bits (Register R5, Bit D1 and Bit D2).
Rev. A
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ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
selected level of attenuation occurs after the initial microphone
50kΩ
signal amplification from the microphone first and second stage
gains.
R
10kΩ
EXT
0dB/20dB/40dB
GAIN BOOST
MICIN
Line and Headphone Outputs
The DAC outputs, the microphone (the sidetone path), and the
line inputs (the bypass path) are summed at an output mixer
(see Figure 4). This output signal is then applied to both the ste-
reo line outputs and stereo headphone outputs.
AVDD
ADC
OR
SIDETONE
VMID
BYPASS
LINE
INPUT
INTERNAL CIRCUITRY
AGND
SIDETONE
Figure 3. Microphone Input to ADC
MICROPHONE
INPUT
The first gain stage is composed of a low noise operational
amplifier set to an inverting configuration with integrated
50 kΩ feedback and 10 kΩ input resistors. The default micro-
phone input signal gain is 14 dB. An external resistor (REXT) can
be connected in series with the MICIN pin to reduce the first-
stage gain of the microphone input signal to as low as 0 dB by
using the following equation:
DACSEL
DAC
LINE OUTPUT
AND
OUTPUT
HEADPHONE
OUTPUT
AVDD
Microphone Input Gain = 50 kΩ/(10 kΩ + REXT
)
The second-stage gain of the microphone signal path is derived
from the internal microphone boost circuitry. The available set-
tings are 0 dB, 20 dB, and 40 dB and are controlled by the
MICBOOST (Register R4, Bit D0) and MICBOOST2 (Register
R4, Bit D8) bits. To achieve 20 dB of secondary gain boost, the
programmer can select either MICBOOST or MICBOOST2. To
achieve 40 dB of secondary microphone signal gain, the pro-
grammer must select both MICBOOST and MICBOOST2.
VMID
INTERNAL CIRCUITRY
AGND
Figure 4. Output Signal Chain
The codec has a set of efficient headphone amplifier outputs,
LHPOUT and RHPOUT, that are able to drive 16 Ω or 32 Ω
headphones (shown in Figure 5).
The MUTEMIC bit (Register R4, Bit D1) mutes the microphone
input signal to the ADC.
When using either the line or microphone inputs, the maximum
full-scale input to the ADC is 1.0 V rms when AVDD = 3.3 V.
Do not apply an input voltage larger than full-scale to avoid
overloading the ADC, which causes distortion of sound and
deterioration of audio quality. For best sound quality in both
microphone and line inputs, gain should be carefully configured
so that the ADC receives a signal equal to its full-scale. This
maximizes the signal-to-noise ratio for best total audio quality.
DAC/
SIDETONE/
BYPASS
AVDD
–
+
RHPOUT
or
LHPOUT
VMID
Bypass and Sidetone Paths to Output
The line and microphone inputs can be routed and mixed
directly to the output terminals by programming the SIDET-
ONE (Register R4, Bit D5) and BYPASS (Register R4, Bit D3)
registers. In both modes, the analog input signal is routed
directly to the output terminals and is not digitally converted.
The bypass signal at the output mixer is the same level as the
output of the PGA associated with each line input.
The sidetone signal at the output mixer can be attenuated from
–6 dB to –15 dB in steps of –3 dB by configuring the SIDEATT
(Register R4, Bit D6 and Bit D7) control register bits. The
INTERNAL CIRCUITRY
AGND
Figure 5. Headphone Output
Like the line inputs, the LHPOUT and RHPOUT volumes, by
default, are independently adjusted by setting the LHPVOL
(Register R2, Bit D0 to Bit D6) and RHPVOL (Register R3, Bit
D0 to Bit D6) bits of the headphone output control registers.
The headphone outputs can be muted by writing codes less than
0110000 to the LHPVOL and RHPVOL bits.
Rev. A
| Page 5 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
The programmer can simultaneously load the volume control of
both channels by writing to the LRHPBOTH (Register R2, Bit
D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- or
right-channel DAC volume registers.
The maximum output level of the headphone outputs is
1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audi-
ble pops and clicks, the headphone and line outputs are held at
the VMID dc voltage level when the device is set to standby
mode or when the headphone outputs are muted.
The stereo line outputs of the codec, the LOUT and ROUT pins,
can drive a load impedance of 10 kΩ and 50 pF. The line output
signal levels are not adjustable at the output mixer, which has a
fixed gain of 0 dB. The maximum output level of the line out-
puts is 1.0 V rms when AVDD = 3.3 V.
DIGITAL AUDIO INTERFACE
The digital audio input can support the following digital audio
communication protocols: right-justified mode, left-justified
mode, I2S mode, and frame sync mode. See Figure 6 on Page 6
through Figure 10 on Page 7.
The mode selection is performed by writing to the FORMAT
bits of the digital audio interface register (Register R7, Bit D1
and Bit D0). All modes are MSB first and operate with data of 16
to 32 bits.
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
CODEC_BCLK
ADCDAT/
DACDAT
1
2
3
4
N
X
X
1
2
3
N
X
X
X = DON’T CARE.
Figure 6. Left-Justified Audio Input Mode
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
CODEC_BCLK
ADCDAT/
DACDAT
X
X
N
4
3
2
1
X
X
N
4
3
2
1
X = DON’T CARE.
Figure 7. Right-Justified Audio Input Mode
Rev. A
| Page 6 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
CODEC_BCLK
ADCDAT/
DACDAT
X
1
2
3
4
N
X
N
X
X
1
2
3
X = DON’T CARE.
Figure 8. I2S Audio Input Mode
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
CODEC_BCLK
1
2
3
N
1
2
3
N
X
X
X
ADCDAT/
DACDAT
X = DON’T CARE.
Figure 9. Frame Sync/PCM Mode Audio Input (Submode 1) [Bit LRP = 0]
1/fS
LEFT CHANNEL
RIGHT CHANNEL
ADCLRC/
DACLRC
CODEC_BCLK
X
1
2
3
N
1
2
3
N
X
X
ADCDAT/
DACDAT
X = DON’T CARE.
Figure 10. Frame Sync/PCM Mode Audio Input (Submode 2) [Bit LRP = 1]
Rev. A
| Page 7 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Recording Mode
The digital audio interface sends the ADC digital filter data to
the ADCDAT output pin for recording. The ADCDAT data
stream multiplexes the left- and right-channel audio data in the
time domain. The ADCLRC clock signal separates left- and
right-channel digital audio frames on the ADCDAT lines.
The CODEC_BCLK signal clocks the digital audio data within
the frames. The CODEC_BCLK signal is either an input or an
output depending on whether the codec is in master or slave
mode. During a recording operation, ADCDAT and ADCLRC
must be synchronous to the CODEC_BCLK signal to avoid data
corruption.
Playback Mode
The digital audio interface receives data on the DACDAT input
pin for playback. The digital audio data stream on the DACDAT
pin is time-domain-multiplexed left and right channel audio
data. The DACLRC clock signal separates left and right channel
digital audio frames on the DACDAT lines.
The CODEC_BCLK signal clocks the digital audio data within
the frames. The CODEC_BCLK signal is either an input or an
output depending on whether the codec is in master or slave
mode. During a playback operation, DACDAT and DACLRC
must be synchronous to the CODEC_BCLK signal to avoid data
corruption.
Digital Audio Data Sampling Rate
To accommodate a wide variety of commonly used DAC and
ADC sampling rates, the codec allows for two modes of opera-
tion, normal and USB, selected by the USB bit (Register R8,
Bit D0).
The sampling rate is generated as a fixed divider from the
CODEC_MCLK signal. Because all audio processing references
the CODEC_MCLK signal, corruption of this signal will corrupt
the quality of the audio at the codec output. The ADCLRC/
ADCDAT/CODEC_BCLK or DACLRC/DACDAT/
CODEC_BCLK signals must be synchronized with
CODEC_MCLK in the digital audio interface circuit.
CODEC_MCLK must be faster or equal to the CODEC_BCLK
frequency to guarantee that no data is lost during data synchro-
nization. The CODEC_BCLK frequency should be greater than
the sampling rate × word length × 2. Ensuring that the
CODEC_BCLK frequency is greater than this, guarantees that
all valid data bits are captured by the digital audio interface cir-
cuitry. For example, if a 32 kHz digital audio sampling rate with
a 32-bit word length is desired, CODEC_BCLK = 2.048 MHz.
Rev. A
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ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Normal Mode
In normal mode, the codec supports digital audio sampling
rates from 8 kHz to 96 kHz. Normal mode supports 256 × fS and
384 × fS based clocks. To select the desired sampling rate, the
programmer must set the appropriate sampling rate register in
the SR control bits (Register R8, Bit D2 to Bit D5) and match
this selection to the core clock frequency that is pulsed on the
CODEC_MCLK pin. See Table 1 for sampling rates in
normal mode.
Table 1. Sampling Rate Lookup Table, Normal Mode (USB Disabled)
CODEC_MCLK CODEC_MCLK ADC Sampling Rate
(CLKDIV2 = 0) (CLKDIV2 = 1) (ADCLRC)
DAC Sampling Rate
(DACLRC)
USB SR [3:0] BOSR CODEC_BCLK
(MS = 1)1
12.288 MHz
24.576 MHz
8 kHz (CODEC_MCLK/1536)
8 kHz (CODEC_MCLK/1536)
12 kHz (CODEC_MCLK/1024)
16 kHz (CODEC_MCLK/768)
24 kHz (CODEC_MCLK/512)
32 kHz (CODEC_MCLK/384)
48 kHz (CODEC_MCLK/256)
48 kHz (CODEC_MCLK/256)
96 kHz (CODEC_MCLK/128)
8 kHz (CODEC_MCLK/1536)
48 kHz (CODEC_MCLK/256)
12 kHz (CODEC_MCLK/1024)
16 kHz (CODEC_MCLK/768)
24 kHz (CODEC_MCLK/512)
32 kHz (CODEC_MCLK/384)
8 kHz (CODEC_MCLK/1536)
48 kHz (CODEC_MCLK/256)
96 kHz (CODEC_MCLK/128)
0
0
0
0
0
0
0
0
0
0011
0010
0100
0101
1110
0110
0001
0000
0111
1011
1010
1100
1101
1001
1000
1111
0011
0010
0100
0101
1110
0110
0000
0001
0111
1011
1010
1100
1101
1001
1000
1111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/2
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/4
CODEC_MCLK/2
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/3
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/6
CODEC_MCLK/3
11.2896 MHz 22.5792 MHz 8.0182 kHz (CODEC_MCLK/1408) 8.0182 kHz (CODEC_MCLK/1408) 0
8.0182 kHz (CODEC_MCLK/1408) 44.1 kHz (CODEC_MCLK/256)
11.025 kHz (CODEC_MCLK/1024) 11.025 kHz (CODEC_MCLK/1024) 0
0
22.05 kHz (CODEC_MCLK/512)
44.1 kHz (CODEC_MCLK/256)
44.1 kHz (CODEC_MCLK/256)
88.2 kHz (CODEC_MCLK/128)
8 kHz (CODEC_MCLK/2304)
8 kHz (CODEC_MCLK/2304)
12 kHz (CODEC_MCLK/1536)
16 kHz (CODEC_MCLK/1152)
24 kHz (CODEC_MCLK/768)
32 kHz (CODEC_MCLK/576)
48 kHz (CODEC_MCLK/384)
48 kHz (CODEC_MCLK/384)
96 kHz (CODEC_MCLK/192)
22.05 kHz (CODEC_MCLK/512)
8.0182 kHz (CODEC_MCLK/1408) 0
0
44.1 kHz (CODEC_MCLK/256)
88.2 kHz (CODEC_MCLK/128)
8 kHz (CODEC_MCLK/2304)
48 kHz (CODEC_MCLK/384)
12 kHz (CODEC_MCLK/1536)
16 kHz (CODEC_MCLK/1152)
24 kHz (CODEC_MCLK/768)
32 kHz (CODEC_MCLK/576)
48 kHz (CODEC_MCLK/384)
8 kHz (CODEC_MCLK/2304)
96 kHz (CODEC_MCLK/192)
0
0
0
0
0
0
0
0
0
0
0
18.432 MHz
36.864 MHz
16.9344 MHz 33.8688 MHz 8.0182 kHz (CODEC_MCLK/2112) 8.0182 kHz (CODEC_MCLK/2112) 0
8.0182 kHz (CODEC_MCLK/2112) 44.1 kHz (CODEC_MCLK/384)
11.025 kHz (CODEC_MCLK/1536) 11.025 kHz (CODEC_MCLK/1536) 0
0
22.05 kHz (CODEC_MCLK/768)
44.1 kHz (CODEC_MCLK/384)
44.1 kHz (CODEC_MCLK/384)
88.2 kHz (CODEC_MCLK/192)
22.05 kHz (CODEC_MCLK/768)
8.0182 kHz (CODEC_MCLK/2112) 0
44.1 kHz (CODEC_MCLK/384)
88.2 kHz (CODEC_MCLK/192)
0
0
0
1
CODEC_BCLK frequency is for master mode and slave right-justified mode only.
Rev. A
| Page 9 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
USB Mode
12 MHz, or to support 24 MHz if the CLKDIV2 control register
bit is activated. The programmer must set the appropriate sam-
pling rate in the SR control bits (Register R8, Bit D2 to Bit D5).
See Table 2 for sampling rates in USB mode.
In USB mode, the codec supports digital audio sampling rates
from 8 kHz to 96 kHz. USB mode is enabled on the codec
to support the common universal serial bus (USB) clock rate of
Table 2. Sampling Rate Lookup Table, USB Mode (USB Enabled)
CODEC_MCLK CODEC_MCLK ADC Sampling Rate
(CLKDIV2 = 0) (CLKDIV2 = 1) (ADCLRC)
DAC Sampling Rate
(DACLRC)
USB SR [3:0] BOSR CODEC_BCLK
(MS = 1)1
12.000 MHz
24.000 MHz
8 kHz (CODEC_MCLK/1500)
8 kHz (CODEC_MCLK/1500)
8.0214 kHz (CODEC_MCLK/1496) 8.0214 kHz (CODEC_MCLK/1496)
8.0214 kHz (CODEC_MCLK/1496) 44.118 kHz (CODEC_MCLK/272)
11.0259 kHz (CODEC_MCLK/1088) 11.0259 kHz (CODEC_MCLK/1088) 1
12 kHz (CODEC_MCLK/1000)
16 kHz (CODEC_MCLK/750)
22.0588 kHz (CODEC_MCLK/544) 22.0588 kHz (CODEC_MCLK/544)
24 kHz (CODEC_MCLK/500)
32 kHz (CODEC_MCLK/375)
44.118 kHz (CODEC_MCLK/272) 8.0214 kHz (CODEC_MCLK/1496)
44.118 kHz (CODEC_MCLK/272) 44.118 kHz (CODEC_MCLK/272)
48 kHz (CODEC_MCLK/250)
48 kHz (CODEC_MCLK/250)
8 kHz (CODEC_MCLK/1500)
48 kHz (CODEC_MCLK/250)
1
1
1
1
0011
0010
1011
1010
1100
1000
1010
1101
1110
0110
1001
1000
0001
0000
1111
0111
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
CODEC_MCLK
12 kHz (CODEC_MCLK/1000)
16 kHz (CODEC_MCLK/750)
1
1
1
1
1
1
1
1
1
1
1
24 kHz (CODEC_MCLK/500)
32 kHz (CODEC_MCLK/375)
8 kHz (CODEC_MCLK/1500)
48 kHz (CODEC_MCLK/250)
88.235 kHz (CODEC_MCLK/136) 88.235 kHz (CODEC_MCLK/136)
96 kHz (CODEC_MCLK/125) 96 kHz (CODEC_MCLK/125)
1
CODEC_BCLK frequency is for master mode and slave right-justified mode only.
Rev. A
| Page 10 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
When 2-wire (TWI) mode is selected, CSDA generates the serial
control data-word; CSCL clocks the serial data; and CSB deter-
mines the TWI device address. If the CSB pin is set to 0, the
address selected is 0011010; if 1, the address is 0011011.
When 3-wire (SPI) mode is selected, CSDA generates the con-
trol data-word, CSCL clocks the control data-word into the
codec, and CSB latches in the control data-word.
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the
programmer-selectable control registers and can operate with a
2-wire (TWI) or 3-wire (SPI) interface, depending on the setting
of the CMODE pin. If the CMODE pin is set to 0, the 2-wire
interface is selected; if 1, the 3-wire interface is selected.
Within each control register is a control data-word consisting of
16 bits, MSB first. Bit B15 to Bit B9 are the register map address,
and Bit B8 to Bit B0 are register data for the associated register
map.
CSB
CSCL
B15
B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B0
CSDA
REGISTER MAP
ADDRESS
REGISTER
DATA
Figure 11. Codec SPI Serial Interface
CSDA
CSCL
S
1 – 7
8
9
1 – 7
8
9
1 – 7
8
9
P
START
ADDR
R/W
ACK
SUBADDRESS ACK
DATA
ACK
STOP
Figure 12. Codec TWI Serial Interface
WRITE
S
S
A7 ... A1 A0 A(S) B15 ... B9 B8 A(S) B7 ... B0 A(S)
P
SEQUENCE
0
DEVICE
REGISTER
ADDRESS
REGISTER
DATA
ADDRESS
READ
A7 ... A1 A0 A(S)
0
B15 ... B9
0
A(S)
S
A7 ... A1 A0 A(S)
1
B7 ... B0 A(M)
...
0
B8 A(M)
0
P
SEQUENCE
DEVICE
REGISTER
ADDRESS
DEVICE
REGISTER
DATA
ADDRESS
ADDRESS
(SLAVE DRIVE)
S/P = START/STOP BIT.
2
A0 = I C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
A(M) = ACKNOWLEDGE BY MASTER.
A(M) = ACKNOWLEDGE BY MASTER (INVERSION).
Figure 13. Codec TWI Write and Read Sequences
Rev. A
| Page 11 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
CODEC PIN DESCRIPTIONS
Table 3 shows the signals added to the ADSP-BF52xC processor
for the embedded codec. Please refer to the published
ADSP-BF52x data sheet for descriptions of other signals for the
processor.
Table 3. Codec Pin Descriptions
Pin Name
Codec
Type Function
Pull-Up/Down
CODEC_CLKOUT
CODEC_BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
CMODE
CSB
O
I/O
I
Codec Clock Output
None
Internal Pull-down1
Codec Digital Audio Bit Clock
Codec Digital Audio Data (DAC) Input
Codec DAC Sample Rate Left/Right Clock
Codec ADC Digital Audio Data Output
Codec ADC Sample Rate Left/Right Clock
Codec Control Interface Selection
None
Internal Pull-down1
I/O
O
I/O
I
None
Internal Pull-down1
Internal Pull-up1
Internal Pull-up1
None
I
Codec Chip Select Interface Address Selection
Codec Data Input
CSDA
I/O
I/O
I
CSCL
Codec Data Clock
None
XTI/CODEC_MCLK
XTO
Codec Crystal Input/ Clock Input
None
O
O
O
O
O
O
O
I
Codec Crystal Output
None
LHPOUT
RHPOUT
LOUT
Codec Left Channel Headphone Output (Analog Output)
Codec Right Channel Headphone Output (Analog Output)
Codec Left Channel Line Output (Analog Output)
Codec Right Channel Line Output (Analog Output)
Codec Mid-rail Reference Decoupling Point (Analog Output)
Codec Electret Microphone Bias (Analog Output)
Codec Microphone Input; (Analog Input, AC Coupled)
Codec Right Channel Line Input (Analog Input, AC Coupled)
Codec Left Channel Line Input (Analog Input, AC Coupled)
Codec Analog VDD
None
None
None
ROUT
None
VMID
None
MICBIAS
MICIN
None
None
RLINEIN
LLINEIN
AVDD
I
None
I
None
P
N/A
AGND
P
Codec Analog Ground
N/A
CVDD
P
Codec Digital VDD
N/A
HPVDD
HPGND
P
Codec Analog Headphone VDD
N/A
P
Codec Headphone Ground
N/A
1 To conserve power, the pull-up/pull-down is only present when the control register interface is active (= 0).
Rev. A
| Page 12 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Figure 14 on Page 13 and Figure 15 on Page 14 describe alterna-
tive external connections for SPI or TWI control of the
ADSP-BF52xC codec. The figures are the same except for the
shaded area in each.
ADSP-BF52XC
1 ꢁF
+
LLINEIN
100
10
XTI/CODEC_MCLK
XTO
Kꢀ
Mꢀ
220 pF
X1
1 ꢁF
+
RLINEIN
100
Kꢀ
10
Mꢀ
220 pF
CODEC
CP
CP
680ꢀ
MICBIAS
MICIN
DACLRC
DACDAT
ADCDAT
+
RMIC
47 Kꢀ
ADCLRC
HPVDD
CODEC_BCLK
HPVDD
HPGND
+
10 ꢁF
0.1 ꢁF
AVDD
+
BLACKFIN
PROCESSOR
AVDD
AGND
LOUT
RSCLKx
10 ꢁF
0.1 ꢁF
1 ꢁF
RFSx
DRxPRI
DTxPRI
TFSx
100 ꢀ
47 Kꢀ
+
SPISELx
MOSI
SCK
1 ꢁF
100 ꢀ
+
ROUT
SDA
SCL
47 Kꢀ
47 Kꢀ
220 ꢁF
+
LHPOUT
CSCL
CSDA
220 ꢁF
CSB
+
RHPOUT
47 Kꢀ
10 Kꢀ
CMODE
AVDD
CODEC_CLKOUT
VMID
100 ꢀ
SPI
0.1 ꢁF
+
10 ꢁF
Figure 14. Recommended Application Circuit Using SPI Control
Rev. A
| Page 13 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
ADSP-BF52XC
1 ꢁF
+
LLINEIN
100
10
XTI/CODEC_MCLK
XTO
Kꢀ
Mꢀ
220 pF
X1
1 ꢁF
+
RLINEIN
100
Kꢀ
10
Mꢀ
220 pF
CODEC
CP
CP
680ꢀ
MICBIAS
MICIN
DACLRC
DACDAT
ADCDAT
+
RMIC
47 Kꢀ
ADCLRC
HPVDD
CODEC_BCLK
HPVDD
HPGND
+
10 ꢁF
0.1 ꢁF
AVDD
+
BLACKFIN
PROCESSOR
AVDD
AGND
LOUT
RSCLKx
10 ꢁF
0.1 ꢁF
1 ꢁF
RFSx
DRxPRI
DTxPRI
TFSx
100 ꢀ
47 Kꢀ
+
SPISELx
AVDD
R
MOSI
SEE VERSION 2.1 OF
THE I2C SPECIFICATION
FOR THE PROPER
SCK
R
1 ꢁF
100 ꢀ
RESISTOR VALUE.
+
ROUT
SDA
SCL
47 Kꢀ
47 Kꢀ
220 ꢁF
+
LHPOUT
CSCL
CSDA
220 ꢁF
+
10 Kꢀ
CSB
AVDD
RHPOUT
47 Kꢀ
10 Kꢀ
CMODE
CODEC_CLKOUT
VMID
100 ꢀ
TWI
0.1 ꢁF
+
10 ꢁF
Figure 15. Recommended Application Circuit Using TWI Control
Rev. A
| Page 14 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
REGISTER DETAILS
Register
Address
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 0 Left-Channel ADC
Input Volume on Page 16
0x00
LRINBOTH LINMUTE
0
LINVOL
Default = 010010111
Register 1 Right-Channel ADC
Input Volume on Page 17
0x01
RLINBOTH RINMUTE
0
RINVOL
Default = 010010111
Register 2 Left-Channel DAC
Volume on Page 17
0x02 LRHPBOTH
0x03 RLHPBOTH
0x04 MICBOOST2
LZCEN
RZCEN
LHPVOL
Default = 001111001
RHPVOL
Default = 001111001
Register 3 Right-Channel DAC
Volume on Page 18
Register 4 Analog Audio Path
on Page 18
SIDEATT[1:0]
SIDETONE DACSEL BYPASS INSEL MUTEMIC MICBOOST
Default = 000001010
Register 5 Digital Audio Path
on Page 19
0x05
0x06
0x07
0
0
0
0
0
0
HPOR DACMU DEEMPH[1:0]
ADC HPD
Default = 000001000
Register6PowerManagement
on Page 19
POWEROFF CLKOUTPD OSCPD
OUTPD DACPD ADCPD MICPD LINEINPD
Default = 010011111
LRSWAP LRP
Register 7 Digital Audio I/F on
Page 20
BCLKINV
MS
WL[1:0]
FORMAT[1:0]
Default = 000001010
SR[3:0]
Register 8 Sampling Rate on
Page 20
0x08
0x09
0x0F
0
0
CLKODIV2 CLKDIV2
BOSR
USB
Default = 000000000
Register 9 Active on Page 20
0
0
0
0
0
0
0
ACTIVE
Default = 000000000
Register 10 Software Reset on
Page 20
RESET
Default = 000000000
Figure 16. Register Mapping
Rev. A
| Page 15 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
BIT DESCRIPTIONS
Table 4 through Table 14 on Page 20 describe each bit in the
control registers.
Table 4. Register 0 Left-Channel ADC Input Volume
Bit Name
Bits
Description
Settings
LRINBOTH
B8
Left-to-right line input ADC
data load control
0 = disable simultaneous loading of left-channel
ADC data to right-channel register (default)
1 = enable simultaneous loading of left-channel
ADC data to right-channel register
LINMUTE
LINVOL
B7
Left-channel input mute
0 = disable mute
1 = enable mute on data path to ADC (default)
00 0000 = –34.5 dB
… 1.5 dB step up
B[5:0] Left-channel PGA volume control
01 0111 = 0 dB (default)
… 1.5 dB step up
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Rev. A
| Page 16 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Table 5. Register 1 Right-Channel ADC Input Volume
Bit Name
Bits
Description
Settings
RLINBOTH
B8
Right-to-left line input ADC
data load control
0 = disable simultaneous loading of right-channel
ADC data to left-channel register (default)
1 = enable simultaneous loading of right-channel
ADC data to left-channel register
RINMUTE
RINVOL
B7
Right-channel input mute
0 = disable mute
1 = enable mute on data path to ADC (default)
00 0000 = –34.5 dB
… 1.5 dB step up
B[5:0] Right-channel PGA volume control
01 0111 = 0 dB (default)
… 1.5 dB step up
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB
Table 6. Register 2 Left-Channel DAC Volume
Bit Name
Bits
Description
Settings
LRHPBOTH B8
Left-to-right headphone volume
load control
0 = disable simultaneous loading of left-channel
headphone volume data to right-channel register (default)
1 = enable simultaneous loading of left-channel
headphone volume data to right-channel register
LZCEN
B7
Left-channel zero cross detect enable
0 = disable (default)
1 = enable
LHPVOL
B[6:0] Left-channel headphone volume control
000 0000 to 010 1111 = mute
011 0000 = –73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps up to
111 1111 = +6 dB
Rev. A
| Page 17 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Table 7. Register 3 Right-Channel DAC Volume
Bit Name
Bits
Description
Settings
RLHPBOTH
B8
Right-to-left headphone volume load control
0 = disable simultaneous loading of right-channel
headphone volume data to left-channel register (default)
1 = enable simultaneous loading of right-channel
headphone volume data to left-channel register
RZCEN
B7
Right-channel zero cross detect enable
0 = disable (default)
1 = enable
RHPVOL [6:0] B[6:0] Right-channel headphone volume control
000 0000 to 010 1111 = mute
011 0000 = –73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps up to
111 1111 = +6 dB
Table 8. Register 4 Analog Audio Path
Bit Name
Bits Description
Settings
MICBOOST2
B8
Additional microphone amplifier gain booster control
0 = 0 dB (default)
1 = 20 dB
SIDEATT[1:0]
B[7:6] Microphone sidetone gain control
00 = –6 dB (default)
01 = –9 dB
10 = –12 dB
11 = –15 dB
SIDETONE
DACSEL
BYPASS
B5
B4
B3
Sidetone enable. Allow attenuated microphone
signal to be mixed at device output terminal
0 = sidetone disable (default)
1 = sidetone enable
DAC select—allow DAC output to be
mixed at device output terminal
0 = do not select DAC (default)
1 = select DAC
Bypass select—allow line input signal to be mixed
at device output terminal
0 = bypass disable
1 = bypass enable (default)
INSEL
B2
B1
B0
Line input or microphone input select to ADC
Microphone mute control to ADC
0 = line input select to ADC (default)
1 = microphone input select to ADC
0 = mute on data path to ADC disable
1 = mute on data path to ADC enable (default)
0 = 0 dB (default)
MUTEMIC
MICBOOST
Primary microphone amplifier gain booster control
1 = 20 dB
Rev. A
| Page 18 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Table 9. Register 5 Digital Audio Path
Bit Name
Bits
Description
Settings
HPOR
B4
Store dc offset when high-pass filter is disabled
0 = clear offset (default)
1 = store offset
DACMU
B3
DAC digital mute
0 = no mute (signal active)
1 = mute (default)
DEEMPH[1:0]
B[2:1] De-emphasis control
00 = no de-emphasis (default)
01 = 32 kHz sampling rate
10 = 44.1 kHz sampling rate
11 = 48 kHz sampling rate
0 = ADC high-pass filter enable (default)
1 = ADC high-pass filter disable
ADCHPD
B0
ADC high-pass filter control
Table 10. Register 6 Power Management
Bit Name
Bits
Description
Settings
POWEROFF
B7
Whole chip power-down control
0 = power-up
1 = power-down (default)
0 = power-up (default)
1 = power-down
CLKOUTPD
OSCPD
B6
B5
B4
B3
B2
B1
B0
Clock output power-down control
Crystal power-down control
Output power-down control
DAC power-down control
0 = power-up (default)
1 = power-down
OUTPD
0 = power-up
1 = power-down (default)
0 = power-up
DACPD
1 = power-down (default)
0 = power-up
ADCPD
MICPD
ADC power-down control
1 = power-down (default)
0 = power-up
Microphone input power-down control
Line input power-down control
1 = power-down (default)
0 = power-up
LINEINPD
1 = power-down (default)
Rev. A
| Page 19 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Table 11. Register 7 Digital Audio I/F
Bit Name
Bits Description
Settings
BCLKINV
B7
B6
B5
B4
CODEC_BCLK inversion control
0 = CODEC_BCLK not inverted (default)
1 = CODEC_BCLK inverted
MS
Master mode enable
0 = enable slave mode (default)
1 = enable master mode
LRSWAP
LRP
Swap DAC data control
0 = output left- and right-channel data as normal (default)
1 = swap left- and right-channel DAC data in audio interface
Polarity control for clocks in right-justified,
left-justified, and I2S modes
0 = normal DACLRC and ADCLRC (default),
or processor Submode 1
1 = invert DACLRC and ADCLRC polarity, or processor Submode 2
WL [1:0]
B[3:2] Data-word length control
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
FORMAT [1:0] B[1:0] Digital audio input format control
00 = right justified
01 = left justified
10 = I2S mode (default)
11 = processor mode
Table 12. Register 8 Sampling Rate
Bit Name
Bits
Description
Settings
CLKODIV2
B7
CODEC_CLKOUT divider select
0 = CODEC_CLKOUT is codec clock (default)
1 = CODEC_CLKOUT is codec clock divided by 2
0 = codec clock is CODEC_MCLK (default)
1= codec clock is CODEC_MCLK divided by 2
See Table 1 on Page 9 and Table 2 on Page 10
USB mode:
CLKDIV2
B6
Codec clock divide select
SR [3:0]
BOSR
B[5:2]
B1
Clock setting condition
Base oversampling rate
0 = support for 250 × fS based clock (default)
1 = support for 272 × fS based clock
Normal mode:
0 = support for 256 × fS based clock (default)
1 = support for 384 × fS based clock
0 = normal mode enable (default)
1 = USB mode enable
USB
B0
USB mode select
Table 13. Register 9 Active
Bit Name
Bit
Description
Settings
ACTIVE
B0
Digital core activation control
0 = disable digital core (default)
1 = activate digital core
Table 14. Register 10 Software Reset
Bit Name Bit Description
Settings
RESET [8:0] B[8:0] Write all 0s to this register to set all registers to their default settings.
Other data written to this register has no effect.
0 = reset (default)
Rev. A
| Page 20 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
SPECIFICATIONS
TAmbient = 25°C, AVDD = VDDEXT = 3.3 V, HPVDD = 3.3 V,
1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data,
unless otherwise noted.
OPERATING CONDITIONS
See operating conditions in the published ADSP-BF52xC
data sheet.
Parameter
AVDD1
Conditions
Min
1.8
Typical
3.3
Max Unit
3.6
3.6
V
V
HPVDD
1.8
3.3
1 Note that AVDD must equal HPVDD.
CODEC ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Min Typical
Max Unit
Line Input
Input Signal Level (0 dB)
Input Impedance
AVDD/3.3
200
V(rms)
PGA gain = 0 dB
kΩ
PGA gain = +33 dB
PGA gain = –34.5 dB
10
kΩ
480
kΩ
Input Capacitance
10
pF
Signal-to-Noise Ratio (A-Weighted)
PGA gain = 0 dB, AVDD = 3.3 V
PGA gain = 0 dB, AVDD = 1.8 V
–1 dBFS input, AVDD = 3.3 V
–1 dBFS input, AVDD = 1.8 V
82
87
84
dB
dB
Total Harmonic Distortion (THD)
–80 –84
–71
dB
–60 dB
dB
Channel Separation1
Programmable Gain
Gain Step
80
–34.5 0
1.5
+33.5 dB
dB
Mute Attenuation
–80
dB
Microphone Input
Input Signal Level
1
V(rms)
Signal-to-Noise Ratio (A-Weighted)
Total Harmonic Distortion
Microphone gain = 0 dB (RSOURCE = 40 kΩ)
–1 dBFS input, 0 dB gain, AVDD = 3.3 V
–1 dBFS input, 0 dB gain, AVDD = 1.8 V
85
–75
–65
50
80
10
10
dB
dB
dB
dB
dB
kΩ
pF
Power Supply Rejection Ratio
Mute Attenuation
Input Resistance
Input Capacitance
Microphone Bias
Bias Voltage
0.75 × AVDD
V
Bias Current Source
Noise in the Signal Bandwidth
3
mA
20 Hz to 20 kHz
40
nV/√Hz
Rev. A
| Page 21 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Parameter
Conditions
Min Typical
Max Unit
Line Output
DAC
–1 dBFS input DAC + line output
Full-Scale Output
AVDD/3.3
V(rms)
Signal-to-Noise Ratio (A-Weighted)
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
90
85
95
dB
dB
88
THD + N
–80
–80
50
–70 dB
–70 dB
dB
Power Supply Rejection Ratio
Channel Separation
80
dB
Headphone Output
Full-Scale Output Voltage
Maximum Output Power
AVDD/3.3
30
V(rms)
RL = 32 Ω
mW
mW
dB
RL = 16 Ω
60
Signal-to-Noise Ratio (A-Weighted)
THD + N
AVDD = 3.3 V
AVDD = 1.8 V
HPOUT = 10 mW
HPOUT = 20 mW
90
80
94
85
dB
–65
–60
50
dB
dB
Power Supply Rejection Ratio
Mute Attenuation
dB
80
dB
LIne Input To Line Output
Full-Scale Output Voltage
Signal-to-Noise Ratio (A-Weighted)
AVDD/3.3
92
V(rms)
dB
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
86
dB
Total Harmonic Distortion
–80
dB
–80
dB
Power Supply Rejection
50
dB
Microphone Input To Headphone Output
Full-Scale Output Voltage
AVDD/3.3
V(rms)
dB
Signal-to-Noise Ratio (A-Weighted)
AVDD = 3.3 V
AVDD = 1.8 V
94
88
50
dB
Power Supply Rejection Ratio
Programmable Attenuation
Gain Step
dB
6
15
dB
3
dB
Mute Attenuation
80
dB
1 Guaranteed but not tested.
Rev. A
| Page 22 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
ABSOLUTE MAXIMUM RATINGS
See absolute maximum ratings in the published ADSP-BF52x
processor data sheet.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
PACKAGE INFORMATION
The information presented in Figure 17 and Table 15 provides
details about the package branding for the ADSP-BF52xC pro-
cessor. For a complete listing of product availability, see
Ordering Guide on Page 36.
a
ADSP-BF527KBCZ6C2X
tppZccc
vvvvvv.x n.n
yyww country_of_origin
B
Figure 17. Product Information on Package
Table 15. Package Brand Information
Brand Key
Field Description
Temperature Range
Package Type
t
pp
Z
Lead Free Option
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ccc
vvvvvv.x
n.n
yyww
Rev. A
| Page 23 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
POWER CONSUMPTION
These current consumption values are for the codec alone.
Please refer to the published ADSP-BF52x processor data sheet
for the additional current consumption of the Blackfin
processor.
Table 16. Power Consumption
Mode
(1.8V)
(3.3V)
1
1
AVDD HPVDD VDDEXT AVDD HPVDD VDDEXT Unit
Record and Playback
Playback Only
Oscillator Enabled
External Clock
Record Only
0
0
0
0
0
0
0
0
7.4
1.5
6.3
14.8
2.0
12.0
mA
0
0
0
1
0
1
0
0
0
0
1
1
1
1
1
1
3.1
2.9
1.30
1.2
3.0
3.0
4.7
4.7
2.0
2.0
6.1
6.1
mA
mA
Line Oscillator
Line Clock
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
2.4
2.5
3.6
3.6
N/A
N/A
N/A
N/A
3.7
3.8
1.9
1.8
4.3
4.3
9.4
9.4
N/A
N/A
N/A
N/A
7.4
7.4
3.6
3.6
mA
mA
mA
mA
Microphone 1
Microphone 2
Sidetone
(Microphone-to-Headphone Output)
Internally Generated Clock
External Clock
0
0
0
0
0
1
0
0
1
1
1
1
0
0
1
1
2.3
2.3
1.0
1.0
2.0
2.0
7.9
7.9
2.0
2.0
4.0
4.0
mA
mA
Analog Bypass
(Line Input or Line Output)
Internally Generated Line
External Line
0
0
0
0
0
1
0
0
1
1
1
1
1
1
0
0
0.9
0.9
1.0
1.0
2.0
2.0
1.8
1.8
2.0
2.0
4.0
4.0
mA
mA
Power-Down
Clock Stopped
1
1
1
1
1
1
1
1
3.1
6.3
3.8
9.4
6.3
12.3
μA
1 VDDEXT here refers to the total of the codec's DCVDD and DBVDD signals and does not include VDDExt supplies in the Blackfin device.
Rev. A
| Page 24 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
TIMING SPECIFICATIONS
TWI Timing
Table 17. TWI Timing
Parameter
Test Conditions1 Min Max Unit
tSCS
tSCH
tPH
tPL
Start condition setup time
Start condition hold time
CSCL pulse width high
CSCL pulse width low
CSCL frequency
600
600
600
1.3
0
ns
ns
ns
μs
fSCL
tDS
tDH
tRT
526 kHz
ns
Data setup time
100
Data hold time
900 ns
300 ns
300 ns
ns
CSDA and CSCL rise time
CSDA and CSCL fall time
Stop condition setup time
tFT
tHCS
600
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
t
t
SCH
HCS
CSDA
t
DS
t
SCS
t
t
PH
PL
CSCL
t
t
t
RT
DH
FT
Figure 18. TWI Timing
Rev. A
| Page 25 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
SPI Timing
Table 18. SPI Timing
Parameter
tDSU
Test Conditions1 Min Max Unit
CSDA to CSCL setup time
CSCL to CSDA hold time
CSCL pulse width high
20
20
20
20
60
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDHO
tSCH
tSCL
CSCL pulse width low
tSCS
CSCL rising edge to CSB rising edge
CSB rising to CSCL rising
CSB pulse width high
tCSS
tCSH
tCSL
CSB pulse width low
tPS
Pulse width of spikes to be suppressed
5
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
t
CSH
t
CSL
CSB
t
t
t
SCS
SCH
SCL
t
CSS
CSCL
CSDA
t
DSU
t
DHO
Figure 19. SPI Timing
Rev. A
| Page 26 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Digital Audio Interface Slave Mode Timing
Table 19. Digital Audio Interface Slave Mode Timing
Parameter
tDS
Test Conditions1 Min Max Unit
DACDAT setup time from CODEC_BCLK rising edge
DACDAT hold time from CODEC_BCLK rising edge
ADCLRC/DACLRC setup time to CODEC_BCLK rising edge
ADCLRC/DACLRC hold time to CODEC_BCLK rising edge
ADCDAT propagation delay from CODEC_BCLK falling edge (external load of 70 pF)
CODEC_BCLK pulse width high
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tLRSU
tLRH
tDD
30
tBCH
25
25
50
tBCL
CODEC_BCLK pulse width low
tBCY
CODEC_BCLK cycle time
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
t
t
BCH
BCL
CODEC_BCLK
t
BCY
DACLRC/
ADCLRC
t
t
LRSU
LRH
t
DS
DACDAT
ADCDAT
t
DH
t
DD
Figure 20. Digital Audio Interface Slave Mode Timing
Rev. A
| Page 27 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Digital Audio Interface Master Mode Timing
Table 20. Digital Audio Interface Master Mode Timing
Parameter
tDST
Test Conditions1 Min
Max
Unit
ns
DACDAT setup time to CODEC_BCLK rising edge
DACDAT hold time to CODEC_BCLK rising edge
ADCLRC/DACLRC propagation delay from CODEC_BCLK falling edge
ADCDAT propagation delay from CODEC_BCLK falling edge
CODEC_BCLK rising time (10 pF load)
30
10
tDHT
ns
tDL
10
10
ns
tDDA
ns
tBCLKR
tBCLKF
tBCLKDS
10
10
ns
CODEC_BCLK falling time (10 pF load)
ns
CODEC_BCLK duty cycle (normal and USB mode)
45:55 55:45
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
CODEC_BCLK
t
DL
DACLRC/
ADCLRC
t
t
DHT
DST
DACDAT
ADCDAT
t
DDA
Figure 21. Digital Audio Interface Master Mode Timing
Rev. A
| Page 28 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
System Clock Timing
Table 21. System Clock Timing
Parameter
tXTIY
Test Conditions1 Min
Max
Unit
XTI/CODEC_MCLK system clock cycle time
72
ns
tMCLKDS
tXTIH
XTI/CODEC_MCLK duty cycle
40:60
60:40
XTI/CODEC_MCLK system clock pulse width high
XTI/CODEC_MCLK system clock pulse width low
CODEC_CLKOUT propagation delay from XTI/CODEC_MCLK falling edge
CLKODIV2 propagation delay from XTI/CODEC_MCLK falling edge
32
32
20
20
ns
ns
ns
ns
tXTIL
tCOP
tCOPDIV2
1 AVDD, HPVDD, VDDEXT = 3.3 V, AGND = 0 V, TA = +25°C, Slave Mode, fS = 48 kHz, XTI/CODEC_MCLK = 256 × fS unless otherwise stated.
t
XTIH
t
COP
CODEC_MCLK/XTI
t
XTIL
t
XTIY
CODEC_CLKOUT
CODEC_CLKOUT/2
t
COPDIV2
Figure 22. System (CODEC_MCLK) Clock Timing
Rev. A
| Page 29 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Digital Filter Characteristics
Table 22. Digital Filter Characteristics
Parameter
ADC FILTER
Pass Band
Conditions
Min
Typical Max
Unit
0.04 dB
–6 dB
0
0.445 × fS Hz
0.5 × fS
Hz
dB
Hz
dB
Hz
Hz
Hz
Pass Band Ripple
Stop Band
0.04
0.555 × fS
–61
Stop Band Attenuation
f > 0.567 × fS
High-Pass Filter Corner Frequency –3 dB
3.7
–0.5 dB
10.4
21.6
–0.1 dB
DAC FILTER
Pass Band
0.04 dB
–6 dB
0
0.445 × fS Hz
Hz
0.5 × fS
Pass Band Ripple
Stop Band
0.04
dB
Hz
dB
0.555 × fS
–61
Stop Band Attenuation
Codec Clock Tolerance
Frequency Range
Jitter Tolerance
f > 0.565 × fS
8.0
13.8
MHz
pS
50
CONVERTER FILTER RESPONSE
0.05
0.04
0.03
0.02
0.01
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
−0.01
−0.02
−0.03
−0.04
−0.05
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS)
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
FREQUENCY (fS)
Figure 24. ADC Digital Filter Ripple, Sampling Rate = 48 kHz
Figure 23. ADC Digital Filter Frequency Response, Sampling Rate = 48 kHz
Rev. A
| Page 30 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
0
0
−1
–10
−2
–20
−3
–30
−4
−5
–40
–50
–60
–70
–80
–90
–100
−6
−7
−8
−9
−10
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
4
8
12
16
20
FREQUENCY (fS)
FREQUENCY (kHz)
Figure 25. DAC Digital Filter Frequency Response, Sampling Rate = 48 kHz
Figure 28. De-Emphasis Frequency Response, Sampling Rate = 44.1 kHz
0.05
0.04
0.03
0.02
0.01
0
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−0.01
−0.02
−0.03
−0.04
−0.05
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (fS)
0
4
8
12
16
20
24
FREQUENCY (kHz)
Figure 26. DAC Digital Filter Ripple, Sampling Rate = 48 kHz
Figure 29. De-Emphasis Frequency Response, Sampling Rate = 48 kHz
DIGITAL DE-EMPHASIS
0.4
0.3
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
0
4
8
12
16
FREQUENCY (kHz)
0
4
8
12
16
Figure 30. De-Emphasis Error, Sampling Rate = 32 kHz
FREQUENCY (kHz)
Figure 27. De-Emphasis Frequency Response, Sampling Rate = 32 kHz
Rev. A
| Page 31 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
289-BALL CSP_BGA BALL ASSIGNMENT
0.4
Signals added or changed to the ADSP-BF52xC processor for
0.3
the embedded codec are shown in Table 23 and Table 24. Please
refer to the published ADSP-BF52x processor data sheet for
descriptions of additional signals for the processor.
0.2
0.1
Table 23. 289-Ball CSP_BGA Ball Assignment
0
(Alphabetically)
−0.1
Signal
Ball No. Signal
Ball No.
G17
G161
B20
−0.2
−0.3
−0.4
ADCDAT
ADCLRC
AGND
A16
A15
H22
J221
E22
A19
HPGND
HPVDD
LHPOUT
LLINEIN
LOUT
0
4
8
12
16
20
AVDD
E23
FREQUENCY (kHz)
CMODE
CODEC_BCLK
F22
Figure 31. De-Emphasis Error, Sampling Rate = 44.1 kHz
MICBIAS
MICIN
H23
J23
0.4
0.3
CODEC_CLKOUT D22
CSB
D23
B23
C23
H171
A18
A17
RHPOUT
RLINEIN
ROUT
B21
CSCL
F23
0.2
CSDA
G22
G23
0.1
CVDD
DACDAT
DACLRC
VMID
0
XTI/CODEC_MCLK A22
XTO A21
−0.1
−0.2
−0.3
−0.4
1 For ADSP-BF52x processor (without internal codec) compatibility,
connect this ball to VDDEXT
.
Table 24. 289-Ball CSP_BGA Ball Assignment
(Numerically)
0
4
8
12
16
20
24
FREQUENCY (kHz)
Ball No. Signal
Ball No. Signal
Figure 32. De-Emphasis Error, Sampling Rate = 48 kHz
A15
A16
A17
A18
A19
A21
A22
B20
B21
B23
C23
D22
D23
ADCLRC
ADCDAT
DACLRC
DACDAT
CODEC_BCLK
XTO
E22
E23
F22
F23
G161
G17
CMODE
LLINEIN
LOUT
RLINEIN
HPVDD
HPGND
ROUT
XTI/CODEC_MCLK G22
LHPOUT
RHPOUT
CSCL
G23
H171
H22
H23
VMID
CVDD
AGND
MICBIAS
AVDD
CSDA
CODEC_CLKOUT J221
CSB J23
MICIN
1 For ADSP-BF52x processor (without internal codec) compatibility,
connect this ball to VDDEXT
.
Rev. A
|
Page 32 of 36
|
March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Figure 33 shows the top view of the ADSP-BF52xC processor
ball configuration.
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
TOP VIEW
KEY:
V
V
GND
I/O
DDINT
V
DDEXT
DDMEM
BALLS THAT HAVE CHANGED USAGE ON THE
ADSP-BF522C/523C/524C/525C/526C/527C:
CODEC I/O
AVDD
AGND
HPVDD
HPGND
Figure 33. ADSP-BF52xC Processor Ball Configuration (Top View)
Rev. A
| Page 33 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Figure 34 shows the bottom view of the ADSP-BF52xC proces-
sor ball configuration.
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
23 22 21 20 19 18 17 16 15 14 13 12 11 10
BOTTOM VIEW
9
8
7
6
5
4
3
2
1
KEY:
V
V
GND
DDINT
I/O
V
DDEXT
DDMEM
BALLS THAT HAVE CHANGED USAGE ON THE
ADSP-BF522C/523C/524C/525C/526C/527C:
CODEC I/O
AVDD
AGND
HPVDD
HPGND
Figure 34. ADSP-BF52xC Processor Ball Configuration (Bottom View)
Rev. A
| Page 34 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
OUTLINE DIMENSIONS
Dimensions in Figure 35, 289-Ball CSP_BGA (BC-289-2) are
shown in millimeters.
0.5 BSC
BALL
PITCH
12.00 BSC SQ
11.00 BSC SQ
CL
A1 BALL
PAD CORNER
A1 BALL
PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
CL
P
R
T
U
V
W
Y
AA
AB
AC
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
TOP VIEW
BOTTOM VIEW
1.40
1.26
1.11
0.20 MIN
DETAIL A
SIDE VIEW
NOTES
0.08 MAX
COPLANARITY
1. DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIES WITH JEDEC REGISTERED OUTLINE
MO-195, VARIATION AJ AND EXCEPTION TO PACKAGE HEIGHT
AND BALL HEIGHT.
3. MINIMUM BALL HEIGHT 0.20
SEATING PLANE
0.35
0.30
0.25
DETAIL A
BALL DIAMETER
Figure 35. 289-Ball CSP_BGA (BC-289-2)
Rev. A
| Page 35 of 36 | March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
ORDERING GUIDE
Temperature
Range2
Instruction
Rate (Max)
Package
Option
Model1
Package Description
ADSP-BF522KBCZ-3C2
ADSP-BF522KBCZ-4C2
ADSP-BF523KBCZ-5C2
ADSP-BF523KBCZ-6C2
ADSP-BF524KBCZ-3C2
ADSP-BF524KBCZ-4C2
ADSP-BF525KBCZ-5C2
ADSP-BF525KBCZ-6C2
ADSP-BF526KBCZ-3C2
ADSP-BF526KBCZ-4C2
ADSP-BF527KBCZ-5C2
ADSP-BF527KBCZ-6C2
1 Z = RoHS Compliant Part.
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
300 MHz
400 MHz
533 MHz
600 MHz
300 MHz
400 MHz
533 MHz
600 MHz
300 MHz
400 MHz
533 MHz
600 MHz
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
289-Ball Chip Scale Package Ball Grid Array (CSP_BGA)
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
BC-289-2
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 21 for junction temperature (TJ)
specification which is the only temperature specification.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06876-0-3/10(A)
Rev. A
| Page 36 of 36 | March 2010
相关型号：
ADSP-BF527KBCZ-6X
IC 0-BIT, 133 MHz, OTHER DSP, PBGA289, 12 X 12 MM, MO-195AJ, CSPBGA-289, Digital Signal Processor
ADI
ADSP-BF531SBBC-400
IC 16-BIT, 40 MHz, OTHER DSP, PBGA160, ROHS COMPLIANT, MO-205AE, CSBGA-160, Digital Signal Processor
ADI
ADSP-BF531SBBCZ400
16-BIT, 40 MHz, OTHER DSP, PBGA160, ROHS COMPLIANT, MO-205AE, CSBGA-160
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