ADSP-BF531SBBC-400_技术文档

PRELIMINARY TECHNICAL DATA

B

a

Embedded Processor

ADSP-BF531/BF532/BF533

Preliminary Technical Data

FEATURES

Up to 600 MHz High-Performance Blackfin Processor

Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video

ALUs, 40-Bit Shifter

RISC-Like Register and Instruction Model for Ease of

Programming and Compiler-Friendly Support

Advanced Debug, Trace, and Performance- Monitoring

0.7 V to 1.2 V Core V_DDwith On-chip Voltage Regulation

3.3 V-Tolerant I/O

External Memory Controller with Glueless Support for

SDRAM, SRAM, FLASH, and ROM

Flexible Memory Booting Options From SPI, External

Memory, or Internal ROM

PERIPHERALS

Parallel Peripheral Interface (PPI)/GPIO,

Supporting ITU-R 656 Video Data Formats

Two Dual-Channel, Full-Duplex Synchronous Serial

Ports, Supporting Eight Stereo I²S Channels

12 Channel DMA Controller

SPI-compatible Port

Three Timer/Counters with PWM Support

UART with Support for IrDA®

Event Handler

160-Ball Mini-BGA and 176-Lead LQFP Packages

MEMORY

Up to 148K Bytes of On-Chip Memory:

16K Bytes of Instruction SRAM/Cache

64K Bytes of Instruction SRAM

32K Bytes of Instruction ROM

32K Bytes of Data SRAM/Cache

32K Bytes of Data SRAM

Real-Time Clock

Watchdog Timer

4K Bytes of Scratchpad SRAM

Two Dual-Channel Memory DMA Controllers

Memory Management Unit Providing Memory

Protection

Debug/JTAG Interface

On-Chip PLL Capable of 1x To 63x Frequency

Multiplication

FUNCTIONAL BLOCK DIAGRAM

EVENT

JTAG TEST AND

EMULATION

CONTROLLER/

CORE TIMER

WATCHDOG TIMER

REAL TIME CLOCK

UART PORT

VOLTAGE

REGULATOR

B

IrDA

®

L1

INSTRUCTION

MEMORY

L1

DATA

MEMORY

MMU

TIMER0, TIMER1,

TIMER2

CORE / SYSTEM BUS INTERFACE

PPI / GPIO

DMA

CONTROLLER

SERIAL PORTS (2)

SPI PORT

BOOT ROM

EXTERNAL PORT

FLASH, SDRAM

CONTROL

REV. PrA

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©Analog Devices,Inc., 2003

assumes no obligation regarding future manufacturing unless otherwise Fax:781/326-8703

agreed to in writing.

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ADSP-BF53x

March 2003

GENERAL NOTE

clean, orthogonal RISC-like microprocessor instruction set, and

single-instruction, multiple-data (SIMD) multimedia capabili-

ties into a single instruction-set architecture.

This data sheet provides preliminary information for the Black-

fin^TMprocessors.¹

The ADSP-BF53x Processors are completely code and pin com-

patible, differing only with respect to their performance and on-

chip memory. Specific performance and memory configurations

are shown in Table 1.

GENERAL DESCRIPTION

TheADSP-BF53xProcessorsaremembersoftheBlackfinfamily

ofproducts, incorporatingtheAnalogDevices/IntelMicroSignal

Architecture (MSA). Blackfin processors combine a dual-MAC

state-of-the-art signal processing engine, the advantages of a

Table 1. Processor Comparison

ADSP-BF531

ADSP-BF532

ADSP-BF533

Maximum performance

Instruction SRAM/Cache

Instruction SRAM

Instruction ROM

Data SRAM/Cache

Data SRAM

400 MHz/ 800 MMACs

16K bytes

32K bytes

16K bytes

400 MHz/ 800 MMACs

16K bytes

32K bytes

600 MHz/ 1200 MMACs

16K bytes

64K bytes

32K bytes

4K bytes

Scratchpad

4K bytes

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like programma-

bility, multimedia support and leading-edge signal processing in

one integrated package.

Clock, and a Watchdog Timer. This set of functions satisfies a

wide variety of typical system support needs and is augmented

by the system expansion capabilities of the part. In addition to

these general-purpose peripherals, the ADSP-BF53x Processor

contains high-speed serial and parallel ports for interfacing to a

variety of audio, video, and modem codec functions; an interrupt

controllerforflexiblemanagementofinterruptsfromtheon-chip

peripherals or external sources; and power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

Portable Low-Power Architecture

Blackfin processors provide world-class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature Dynamic Power

Management, the ability to vary both the voltage and frequency

of operation to significantly lower overall power consumption.

Varying the voltage and frequency can result in a substantial

reduction in power consumption, compared with just varying the

frequency of operation. This translates into longer battery life for

portable appliances.

All of the peripherals, except for general-purpose I/O, Real-Time

Clock, and timers, are supported by a flexible DMA structure.

There is also a separate memory DMA channel dedicated to data

transfers between the processor's various memory spaces,

including external SDRAM and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along with

activity on all of the on-chip and external peripherals.

System Integration

The ADSP-BF53x Processors are highly integrated system-on-

a-chipsolutions for the next generation of digitalcommunication

and consumer multimedia applications. By combining industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a UART port, an SPI port, two serial ports (SPORTs),

four general purpose timers (three with PWM capability), a real-

time clock, a watchdog timer, and a Parallel Peripheral Interface.

The ADSP-BF53x Processor includes an on-chip voltage

regulator in support of the ADSP-BF53x Processor Dynamic

Power Management capability. The voltage regulator provides a

range of core voltage levels from a single 2.25 V to 3.6 V input.

The voltage regulator can be bypassed at the user's discretion.

Blackfin Processor Core

As shown in Figure 1 on page 3, the Blackfin processor core

contains two16-bitmultipliers, two40-bit accumulators, two40-

bit ALUs, four video ALUs, and a 40-bit shifter. The computa-

tion units process 8-bit, 16-bit, or 32-bit data from the register

file.

ADSP-BF53x Processor Peripherals

The ADSP-BF53x Processor contains a rich set of peripherals

connectedtothecoreviaseveralhighbandwidthbuses,providing

flexibility in system configuration as well as excellent overall

system performance (see the block diagram on Page 1). The

general-purpose peripherals include functions such as UART,

Timers with PWM (Pulse Width Modulation) and pulse mea-

surement capability, general purpose flag I/O pins, a Real-Time

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

¹Blackfin is a trademark of Analog Devices, Inc.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

2

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ADSP-BF53x

Each MAC can perform a 16-bit by 16-bit multiply in each cycle,

accumulating the results into the 40-bit accumulators. Signed

and unsigned formats, rounding, and saturation are supported.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

The program sequencer controls the flow of instruction execu-

tion, includinginstructionalignmentanddecoding. Forprogram

flow control, the sequencer supports PC relative and indirect

conditional jumps (with static branch prediction), and subrou-

tine calls. Hardware is provided to support zero-overhead

looping. The architecture is fully interlocked, meaning that the

programmer need not manage the pipeline when executing

instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit Index, Modify,

Length, and Base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

For certain instructions, two 16-bit ALU operations can be

performedsimultaneouslyonregisterpairs(a16-bithighhalfand

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

ADDRESS ARITHMETIC UNIT

SP

FP

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG0

DAG1

P5

P4

P3

SEQUENCER

P2

P1

P0

ALIGN

DECODE

R7

R6

LOOP BUFFER

R5

R4

16

8

CONTROL

UNIT

R3

R2

R1

R0

BARREL

SHIFTER

40

A0

A1

DATA ARITHMETIC UNIT

Figure 1. Blackfin Processor Core

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The Memory Manage-

ment Unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

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ADSP-BF53x

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The architecture provides three modes of operation: User mode,

Supervisor mode, and Emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while Supervisor mode has

unrestricted access to the system and core resources.

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

TheBlackfin processor instructionsethas been optimized sothat

16-bit opcodes represent the most frequently used instructions,

resulting in excellent compiled code density. Complex DSP

instructions are encoded into 32-bit opcodes, representing fully

featured multifunction instructions. Blackfin processors support

a limited multi-issue capability, where a 32-bit instruction can be

issued in parallel with two 16-bit instructions, allowing the pro-

grammer to use many of the core resources in a single instruction

cycle.

INSTRUCTION SRAM / CACHE (16K BYTE)

INSTRUCTION SRAM (64K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

The Blackfin processor assembly language uses an algebraic

syntax for ease of coding and readability. The architecture has

been optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

Memory Architecture

The ADSP-BF53x Processor views memory as a single unified

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers,occupyseparatesectionsofthiscommonaddressspace.

The memory portions of this address space are arranged in a

hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 2 on page 4, Figure 3 on page 5,

and Figure 4 on page 5.

SDRAM MEMORY (16M BYTE - 128M BYTE)

Figure 2. ADSP-BF533 Internal/External Memory Map

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

The L1 memory system is the primary highest-performance

memory available to the Blackfin processor. The off-chip

memory system, accessed through the External Bus Interface

Unit (EBIU), provides expansion with SDRAM, flash memory,

and SRAM, optionally accessing up to 132M bytes of physical

memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including FLASH, EPROM, ROM, SRAM, and

memory mapped I/O devices.

The memory DMA controller provides high-bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal memory and the external memory

spaces.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM.

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully populated

with 1M byte of memory.

Internal (On-chip) Memory

TheADSP-BF53xProcessorhasthreeblocksofon-chipmemory

providing high-bandwidth access to the core.

The first is the L1 instruction memory, consisting of up to

80K bytes SRAM, of which 16K bytes can be configured as a

four-way set-associative cache. This memory is accessed at full

processor speed.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into

memory-mapped registers (MMRs) at addresses near the top of

the 4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for setup

The second on-chip memory block is the L1 data memory, con-

sisting of up to two banks of up to 32K bytes each. Each memory

bank is configurable, offering both Cache and SRAM function-

ality. This memory block is accessed at full processor speed.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-BF53x

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

INSTRUCTION SRAM (32K BYTE)

INSTRUCTION ROM (32K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

RESERVED

0xFFA1 0000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xFFA1 0000

0xFFA0 C000

0xFFA0 8000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

INSTRUCTION SRAM (16K BYTE)

INSTRUCTION ROM (32K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

RESERVED

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

RESERVED

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE)

ASYNC MEMORY BANK 2 (1M BYTE)

ASYNC MEMORY BANK 1 (1M BYTE)

ASYNC MEMORY BANK 0 (1M BYTE)

RESERVED

SDRAM MEMORY (16M BYTE - 128M BYTE)

Figure 3. ADSP-BF532 Internal/External Memory Map

Figure 4. ADSP-BF531 Internal/External Memory Map

and control of the on-chip peripherals outside of the core. The

MMRs are accessible only in supervisor mode and appear as

reserved space to on-chip peripherals.

• Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signalto theprocessor. TheNMIeventisfrequently

used as a power-down indicator to initiate an orderly

shutdown of the system.

Booting

The ADSP-BF53xProcessorcontainsasmallboot kernel, which

configures the appropriate peripheral for booting. If the ADSP-

BF53x Processor is configured to boot from boot ROM memory

space, the processor starts executing from the on-chip boot

ROM. For more information, see Booting Modes on Page 13.

• Exceptions– Events that occursynchronously to program

flow (i.e., the exception will be taken before the instruc-

tion is allowed to complete). Conditions such as data

alignment violations and undefined instructions cause

exceptions.

Event Handling

The event controller on the ADSP-BF53x Processor handles all

asynchronous and synchronous events to the processor. The

ADSP-BF53x Processor provides event handling that supports

both nesting and prioritization. Nesting allows multiple event

service routines to be active simultaneously. Prioritization

ensures that servicing of a higher-priority event takes precedence

over servicing of a lower-priority event. The controller provides

support for five different types of events:

• Interrupts–Eventsthatoccurasynchronouslytoprogram

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The ADSP-BF53x Processor Event Controller consists of two

stages, the Core Event Controller (CEC) and the System

Interrupt Controller (SIC). The Core Event Controller works

with the System Interrupt Controller to prioritize and control all

system events. Conceptually, interrupts from the peripherals

enter into the SIC, and are then routed directly into the general-

purpose interrupts of the CEC.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

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Core Event Controller (CEC)

Table 3. System Interrupt Controller (SIC) (Continued)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF53x Processor. Table 2

describes the inputs to the CEC, identifies their names in the

Event Vector Table (EVT), and lists their priorities.

Peripheral Interrupt Event

Default Mapping

DMA Channel 2 (SPORT 0 TX)

DMA Channel 3 (SPORT 1 RX)

DMA Channel 4 (SPORT 1 TX)

DMA Channel 5 (SPI)

DMA Channel 6 (UART RX)

DMA Channel 7 (UART TX)

Timer 0

Timer 1

Timer 2

PF Interrupt A

PF Interrupt B

DMA Channels 8 and 9

(Memory DMA Stream 1)

DMA Channels 10 and 11

(Memory DMA Stream 0)

Software Watchdog Timer

IVG9

IVG10

IVG11

IVG12

IVG13

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest)

Event Class

EVT Entry

0

Emulation/Test

Control

EMU

1

2

Reset

Non-Maskable

Interrupt

RST

NMI

IVG13

3

4

Exception

Reserved

EVX

-

Event Control

5

6

7

8

Hardware Error

Core Timer

General Interrupt 7

General Interrupt 8

General Interrupt 9

IVHW

IVTMR

IVG7

IVG8

IVG9

The ADSP-BF53x Processor provides the user with a very

flexible mechanism to control the processing of events. In the

CEC, three registers are used to coordinate and control events.

Each register is 16 bits wide:

9

• CEC Interrupt Latch Register (ILAT) – The ILAT

register indicates when events have been latched. The

appropriate bit is set when the processor has latched the

event and cleared when the event has been accepted into

the system. This register is updated automatically by the

controller, butitmay bewritten only whenitscorrespond-

ing IMASK bit is cleared.

10

11

12

13

14

15

General Interrupt 10 IVG10

General Interrupt 11 IVG11

General Interrupt 12 IVG12

General Interrupt 13 IVG13

General Interrupt 14 IVG14

General Interrupt 15 IVG15

• CEC Interrupt Mask Register (IMASK) – The IMASK

registercontrolsthemaskingandunmaskingofindividual

events. When a bit is set in the IMASK register, that event

is unmasked and will be processed by the CEC when

asserted. A cleared bit in the IMASK register masks the

event, preventing the processor from servicing the event

eventhoughtheeventmaybelatchedintheILATregister.

This register may be read or written while in supervisor

mode. (Note that general-purpose interrupts can be

globally enabled and disabled with the STI and CLI

instructions, respectively.)

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF53x Processor provides a default

mapping, the user can alter the mappings and priorities of

interrupt events by writing the appropriate values into the

Interrupt Assignment Registers (IAR). Table 3 describes the

inputs into the SIC and the default mappings into the CEC.

Table 3. System Interrupt Controller (SIC)

• CEC Interrupt Pending Register(IPEND)–TheIPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automati-

cally by the controller but may be read while in supervisor

mode.

Peripheral Interrupt Event

Default Mapping

PLL Wakeup

DMA Error

PPI Error

SPORT 0 Error

SPORT 1 Error

SPI Error

IVG7

IVG8

IVG9

UART Error

Real-Time Clock

DMA Channel 0 (PPI)

DMA Channel 1 (SPORT 0 RX)

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ADSP-BF53x

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 6.

The ADSP-BF53x Processor DMA controller supports both 1-

dimensional (1D) and 2-dimensional (2D) DMA transfers.

DMA transfer initialization can be implemented from registers

or from sets of parameters called descriptor blocks.

• SIC Interrupt Mask Register (SIC_IMASK)– This

register controls the masking and unmasking of each

peripheralinterruptevent. Whenabitissetintheregister,

that peripheral event is unmasked and will be processed

by the system when asserted. A cleared bit in the register

maskstheperipheralevent, preventingtheprocessorfrom

servicing the event.

The2DDMAcapabilitysupportsarbitraryrowandcolumnsizes

up to 64K elements by 64K elements, and arbitrary row and

column step sizes up to +/- 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is espe-

cially useful in video applications where data can be de-

interleaved on the fly.

• SIC Interrupt Status Register (SIC_ISR) – As multiple

peripherals can be mapped to a single event, this register

allows the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit

indicates the peripheral is not asserting the event.

Examples of DMA types supported by the ADSP-BF53x

Processor DMA controller include:

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By

enabling the corresponding bit in this register, a periph-

eral can be configured to wake up the processor, should

the core be idled when the event is generated. (see

Dynamic Power Management on Page 10.)

• 2-D DMA using an array of descriptors, specifying only

the base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are

two memory DMA channels provided for transfers between the

various memories of the ADSP-BF53x Processor system. This

enables transfers of blocks of data between any of the memories—

including external SDRAM, ROM, SRAM, and flash memory—

with minimal processor intervention. Memory DMA transfers

canbecontrolledbyaveryflexibledescriptor-basedmethodology

or by a standard register-based autobuffer mechanism.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND

register contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the processor

pipeline. At this point the CEC will recognize and queue the next

rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clockcycles;however,thelatencycanbemuchhigher,depending

on the activity within and the state of the processor.

Real-Time Clock

The ADSP-BF53x Processor Real-Time Clock (RTC) provides

a robust set of digital watch features, including current time,

stopwatch, and alarm. The RTC is clocked by a 32.768 KHz

crystal external to the ADSP-BF53x Processor. The RTC

peripheral has dedicated power supply pins so that it can remain

powered up and clocked even when the rest of the processor is in

a low-power state. The RTC provides several programmable

interrupt options, including interrupt per second, minute, hour,

or day clock ticks, interrupt on programmable stopwatch count-

down, or interrupt at a programmed alarm time.

DMA Controllers

The32.768 KHzinputclockfrequencyisdivideddowntoa1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and an 32,768-day counter.

The ADSP-BF53x Processor has multiple, independent DMA

controllers that support automated data transfers with minimal

overhead for the processor core. DMA transfers can occur

between the ADSP-BF53x Processor's internal memories and

any of its DMA-capable peripherals. Additionally, DMA

transfers can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interfaces, including the SDRAM controller and the

asynchronous memory controller. DMA-capable peripherals

include the SPORTs, SPI port, UART, and PPI. Each individual

DMA-capable peripheral has at least one dedicated DMA

channel.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of that

day.

The stopwatch function counts down from a programmed value,

with one-second resolution. When the stopwatch is enabled and

the counter underflows, an interrupt is generated.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Like the other peripherals, the RTC can wake up the ADSP-

BF53x Processor from a low-power state upon generation of any

RTC wakeup event.

The timer units can be used in conjunction with the UART to

measure the width of the pulses in the data stream to provide an

auto-baud detect function for a serial channel.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

The timers can generate interrupts to the processor core

providing periodic events for synchronization, either to the

system clock or to a count of external signals.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internalprocessorclockandistypicallyusedasasystemtickclock

for generation of operating system periodic interrupts.

RTXI

RTXO

R1

X1

C1

C2

Serial Ports (SPORTs)

The ADSP-BF53x Processor incorporates twodual-channel syn-

chronous serial ports (SPORT0 and SPORT1) for serial and

multiprocessor communications. The SPORTs support the

following features:

SUGGESTED C OMPONENTS:

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12 pF LOAD (SURFACE MOUNT PACKAG E)

C1 = 22 pF

C2 = 22 pF

R1 = 10MV

• I²S capable operation.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FO R DETAILS. C1 AND C2

SPECIFICATIO NS ASSUME BO ARD TRACE CAPACITANCE OF 3 pF.

• Bidirectional operation – Each SPORT has two sets of

independent transmit and receive pins, enabling eight

channels of I²S stereo audio.

Figure 5. External Components for RTC

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

otherprocessorcomponentsandshiftregistersforshifting

data in and out of the data registers.

Watchdog Timer

The ADSP-BF53x Processor includes a 32-bit timer that can be

used to implement a software watchdog function. A software

watchdog can improve system availability by forcing the

processor to a known state through generation of a hardware

reset, non-maskable interrupt (NMI), or general-purpose inter-

rupt, if the timer expires before being reset by software. The

programmer initializes the count value of the timer, enables the

appropriate interrupt, then enables the timer. Thereafter, the

software must reload the counter before it counts to zero from

the programmed value. This protects the system from remaining

in an unknown state where software, which would normally reset

thetimer, has stopped runningdueto anexternalnoisecondition

or software error.

• Clocking – Each transmit and receive port can either use

an external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most-significant-

bit first or least-significant-bit first.

• Framing – Each transmit and receive port can run with

or without frame sync signals for each data word. Frame

sync signals can be generated internally or externally,

active high or low, and with either of two pulsewidths and

early or late frame sync.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF53x Processor peripherals.

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

watchdog timer control register.

• Companding in hardware – Each SPORT can perform

A-law or µ-law compandingaccordingto ITU recommen-

dation G.711. Companding can be selected on the

transmit and/or receive channel of the SPORT without

additional latencies.

The timer is clocked by the system clock (SCLK), at a maximum

• DMA operations with single-cycle overhead – Each

SPORT can automatically receive and transmit multiple

buffers of memory data. The processor can link or chain

sequences of DMA transfers between a SPORT and

memory.

frequency of f_SCLK

.

Timers

There are four general-purpose programmable timer units in the

ADSP-BF53x Processor. Three timers have an external pin that

can be configured either as a Pulse Width Modulator (PWM) or

timer output, as an input to clock the timer, or as a mechanism

for measuring pulse widths and periods of external events. These

timers can be synchronized to an external clock input to the PF1

pin,anexternalclockinputtothePPI_CLKpin,ortotheinternal

SCLK.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability – Each SPORT supports 128

channelsoutofa1024-channelwindowandiscompatible

with the H.100, H.110, MVIP-90, and HMVIP

standards.

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

8

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ADSP-BF53x

Serial Peripheral Interface (SPI) Port

The ADSP-BF53x Processor has an SPI-compatible port that

enables the processor to communicate with multiple SPI-com-

patible devices.

The UART port's baud rate (see Figure 7), serial data format,

error code generation and status, and interrupts are

programmable:

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSI, and Master Input-

Slave Output, MISO) and a clock pin (Serial Clock, SCK). An

SPI chip select input pin (SPISS) lets other SPI devices select the

(f_SCLK/16) bits per second.

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured

to generate maskable interrupts to the processor.

processor, and seven SPI chip select output pins (SPISEL7–1

)

let the processor select other SPI devices. The SPI select pins are

reconfigured Programmable Flag pins. Using these pins, the SPI

port provides a full-duplex, synchronous serial interface, which

supports both master/slave modes and multimaster

environments.

f_SCLK

----------------

UART Clock Rate =

16 × D

where D = 1 to 65,536

Figure 7. UART Clock Rate Calculation

The SPI port’s baud rate and clock phase/polarities are program-

mable (see Figure 6), and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

In conjunction with the general-purpose timer functions,

autobaud detection is supported.

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

f_SCLK

--------------------------------------

SPI Clock Rate =

2 × SPIBAUD

Programmable Flags (PFx)

The ADSP-BF53x Processor has 16 bi-directional, general-

purpose Programmable Flag (PF15–0) pins. Each programma-

ble flag can be individually controlled by manipulation of the flag

control, status and interrupt registers:

where SPIBAUD = 2 to 65,535

Figure 6. SPI Clock Rate Calculation

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sampling

of data on the two serial data lines.

• Flag Direction Control Register – Specifies the direction

of each individual PFx pin as input or output.

• Flag Control and Status Registers – The ADSP-BF53x

Processor employs a “write one to modify” mechanism

that allows any combination of individual flags to be

modifiedinasingleinstruction,withoutaffectingthelevel

of any other flags. Four control registers are provided.

One register is written in order to set flag values, one

register is written in order to clear flag values, one register

is written in order to toggle flag values, and one register

is written in order to specify a flag value. Reading the flag

status register allows software to interrogate the sense of

the flags.

UART Port

The ADSP-BF53x Processor provides a full-duplex Universal

Asynchronous Receiver/Transmitter (UART) port, which is fully

compatible with PC-standard UARTs. The UART port provides

a simplified UART interface to other peripherals or hosts, sup-

porting full-duplex, DMA-supported, asynchronous transfers of

serial data. The UART port includes support for 5 to 8 data bits,

1 or 2 stop bits, and none, even, or odd parity. The UART port

supports two modes of operation:

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• Flag Interrupt Mask Registers – The two Flag Interrupt

Mask Registers allow each individual PFx pin to function

as an interrupt to the processor. Similar to the two Flag

Control Registers that are used to set and clear individual

flag values, one Flag Interrupt Mask Register sets bits to

enable interrupt function, and the other Flag Interrupt

Mask register clears bits to disable interrupt function.

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive.

These DMA channels have lower default priority than

mostDMAchannelsbecauseoftheirrelativelylowservice

rates.

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Output Mode

PFx pins defined as inputs can be configured to generate

hardware interrupts, while output PFx pins can be

triggered by software interrupts.

This mode is used for transmitting video or other data with up to

three output frame syncs. Typically, a single frame sync is appro-

priate for data converter applications, whereas two or three frame

syncs could be used for sending video with hardware signaling.

• Flag Interrupt Sensitivity Registers – The two Flag

Interrupt Sensitivity Registers specify whether individual

PFx pins are level- or edge-sensitive and specify—if edge-

sensitive—whether just the rising edge or both the rising

and falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects

which edges are significant for edge-sensitivity.

ITU -R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct sub-modes are supported:

• Active Video Only Mode

• Vertical Blanking Only Mode

• Entire Field Mode

Parallel Peripheral Interface

The ADSP-BF53x Processor provides a Parallel Peripheral

Interface (PPI) that can connect directly to parallel A/D and D/A

converters, video encoders and decoders, and other general

purpose peripherals. The PPI consists of a dedicated input clock

pin, up to 3 frame synchronization pins, and up to 16 data pins.

The input clock supports parallel data rates up to f_SCLK/2 MHz,

andthesynchronizationsignalscanbeconfiguredaseitherinputs

or outputs.

Active Video Only Mode

This mode is used when only the active video portion of a field

is of interest and not any of the blanking intervals. The PPI will

not read in any data between the End of Active Video (EAV) and

Start of Active Video (SAV) preamble symbols, or any data

present during the vertical blanking intervals. In this mode, the

controlbytesequencesarenotstoredtomemory;theyarefiltered

by the PPI. After synchronizing to the start of Field 1, the PPI

will ignore incoming samples until it sees an SAV code. The user

specifies the number of active video lines per frame (in

PPI_Count register).

The PPI supports a variety of general purpose and ITU-R 656

modes of operation. In general purpose mode, the PPI provides

half-duplex, bi-directionaldatatransferwithupto16bitsofdata.

Up to 3 frame synchronization signals are also provided. In ITU-

R656mode, thePPIprovideshalf-duplex, bi-directionaltransfer

of 8- or 10-bit video data. Additionally, on-chip decode of

embeddedstart-of-line(SOL)andstart-of-field(SOF)preamble

packets is supported.

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

General Purpose Mode Descriptions

Entire Field Mode

The GP modes of the PPI are intended to suit a wide variety of

data capture and transmission applications. Three distinct sub-

modes are supported:

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and

vertical blanking intervals. Data transfer starts immediately after

synchronization to Field 1.

• Input Mode - Frame Syncs and data are inputs into the

PPI.

• FrameCaptureMode-Frame Syncsare outputs fromthe

PPI, but data are inputs.

Dynamic Power Management

The ADSP-BF53x Processor provides four operating modes,

each with a different performance/power profile. In addition,

Dynamic Power Management provides the control functions to

dynamically alter the processor core supply voltage, further

reducing power dissipation. Control of clocking to each of the

ADSP-BF53x Processor peripherals also reduces power con-

sumption. See Table 4 for a summary of the power settings for

each mode.

• Output Mode - Frame Syncs and data are outputs from

the PPI.

Input Mode

This mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation ofdata reads. The number ofinput data samples is user-

programmable and defined by the contents of the PPI_Count

register. Data widths of 8, 10, 11, 12, 13, 14, 15 and 16-bits are

supported, as programmed by the PPI_CONTROL register.

Full-On Operating Mode – Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This is

the power-up default execution state in which maximum perfor-

mance can be achieved. The processor core and all enabled

peripherals run at full speed.

Frame Capture Mode

This mode allows the video source(s) to act as a slave (e.g., for

frame capture). The ADSP-BF53x Processor controls when to

read from the video source(s). PPI_FS1 is an HSYNC output

and PPI_FS2 is a VSYNC output.

Active Operating Mode – Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and

system clock (SCLK) run atthe input clock(CLKIN) frequency.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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10

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ADSP-BF53x

In this mode, the CLKIN to CCLK multiplier ratio can be

changed, although the changes are not realized until the Full-On

mode is entered. DMA access is available to appropriately con-

figured L1 memories.

separate from the RTC and other I/O, the processor can take

advantageofDynamicPowerManagement,withoutaffectingthe

RTC or other I/O devices.

Table 5. Power Domains

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

Power Domain

VDD Range

All internal logic, except RTC

RTC internal logic and crystal I/O

All other I/O

V_DDINT

V_DDRTC

V_DDEXT

Table 4. Power Settings

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in power dissipation, while reducing

the voltage by 25% reduces power dissipation by more than 40%.

Further, these power savings are additive, in that if the clock

frequencyandsupplyvoltagearebothreduced, thepowersavings

can be dramatic.

Full On

Active

Sleep

Enabled

No Enabled Enabled

Enabled/Disabled Yes Enabled Enabled

Enabled

–

Disabled Enabled

Disabled Disabled

Deep Sleep Disabled

Sleep Operating Mode – High Power Savings

The Dynamic Power Management feature of the ADSP-BF53x

Processor allows both the processor’s input voltage (V_DDINT) and

clock frequency (f_CCLK) to be dynamically controlled.

The Sleep mode reduces power dissipation by disabling the clock

to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Typically an

external event or RTC activity will wake up the processor. When

in the Sleep mode, assertion of wakeup will cause the processor

to sense the value of the BYPASS bit in the PLL Control register

(PLL_CTL). If BYPASSis disabled, theprocessorwilltransition

to the Full On mode. If BYPASS is enabled, the processor will

transition to the Active mode.

As explained above, the savings in power dissipation can be

modeled by the following equations:

Power Savings Factor

2

f_CCLKRED

----------------------------

f_CCLKNOM

V_DDINTRED

----------------------------------

V_DDINTNOM

T_RED

----------------

T_NOM

















=

×

When in the Sleep mode, system DMA access to L1 memory is

not supported.

% Power Savings = (1 – Power Savings Factor) × 100%

Deep Sleep Operating Mode – Maximum Power Savings

The Deep Sleep mode maximizes power savings by disabling the

clocks to the processor core (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals, such as the

RTC, may still be running but will not be able to access internal

resources or external memory. This powered-down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in Deep

Sleep mode, assertion of RESET or the RTC asynchronous

interrupt causes the processor to transition to the Full On mode.

where the variables in the equations are:

• f_CCLKNOMis the nominal core clock frequency

• f_CCLKREDis the reduced core clock frequency

• V_DDINTNOMis the nominal internal supply voltage

• V_DDINTREDis the reduced internal supply voltage

• T_NOMis the duration running at f_CCLKNOM

• T_REDis the duration running at f_CCLKRED

Power Savings

As shown in Table 5, theADSP-BF53xProcessor supportsthree

different power domains. The use of multiple power domains

maximizes flexibility, while maintaining compliance with

industry standards and conventions. By isolating the internal

logic of the ADSP-BF53x Processor into its own power domain,

Voltage Regulation

The ADSP-BF53x Processor provides an on-chip voltage

regulator that can generate processor core voltage levels (0.7V to

1.2V) from an external 2.25 V to 3.6 V supply. Figure 8 shows

the typical external components required to complete the power

management system. The regulator controls the internal logic

voltage levels and is programmable with the Voltage Regulator

Control Register (VR_CTL) in increments of 50 mV. The

regulator can also be disabled and bypassed at the user’s

discretion.

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DYNAMIC MODIFICATION

REQUIRES PLL SEQUENCING

DYNAMIC MODIFICATION

ON-THE-FLY

V_DDEXT

2.25V - 3.6V

INPUT VOLTAGE

RANGE

CCLK

SCLK

÷ 1, 2, 4, 8

÷ 1:15

10 µH

0.1 µF

ZHCS1000

PLL

1× - 63×

V_DDINT

CLKIN

VCO

NDS8434

100 µF

1 µF

SCLK ≤ CCLK

VR_OUT1-0

SCLK ≤ 133 MHZ

EXTERNAL COMPONENTS

Figure 10. Frequency Modification Methods

NOTE: VR_OUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

intotheSSEL fields define a divideratiobetween the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 6 illustrates typical system clock ratios:

Figure 8. Voltage Regulator Circuit

Clock Signals

The ADSP-BF53x Processor can be clocked by an external

crystal, a sine wave input, or a buffered, shaped clock derived

from an external clock oscillator.

Table 6. Example System Clock Ratios

Example Frequency

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the specified

frequency during normal operation. This signal is connected to

the processor’s CLKIN pin. When an external clock is used, the

XTAL pin must be left unconnected.

Signal

Name

Divider

Ratio

Ratios (MHz)

SSEL3–0

VCO/SCLK VCO

SCLK

0001

0110

1010

1:1

6:1

10:1

100

300

500

100

50

Alternatively, because the ADSP-BF53x Processor includes an

on-chip oscillator circuit, an external crystal may be used. The

crystal should be connected across the CLKIN and XTAL pins,

with two capacitors connected as shown in Figure 9. Capacitor

values are dependent on crystal type and should be specified by

the crystal manufacturer. A parallel-

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock

frequency to its maximum of f_SCLK. The SSEL value can be

changed dynamically without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV).

resonant, fundamental frequency, microprocessor-grade crystal

should be used.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 7. This programmable core clock capability is useful for

fast core frequency modifications.

XTAL

CLKOUT

CLKIN

DSP

Table 7. Core Clock Ratios

Example Frequency

Signal

Name

Divider

Ratio

Ratios

Figure 9. External Crystal Connections

CSEL1–0

VCO/CCLK VCO

CCLK

As shown in Figure 10 on page 12, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user programmable 1x to 63x multiplication

factor (bounded by specified minimum and maximum VCO fre-

quencies). The default multiplier is 10x, but it can be modified

byasoftwareinstructionsequence.On-the-flyfrequencychanges

can be effected by simply writing to the PLL_DIV register.

00

01

10

11

1:1

2:1

4:1

8:1

300

500

200

300

150

125

25

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ADSP-BF53x

Booting Modes

To augment the boot modes, a secondary software loader is

provided that adds additional booting mechanisms. This

secondary loader provides the capability to boot from 16-bit

FLASH memory, fast FLASH, variable baud rate, and other

sources.

The ADSP-BF53x Processor has three mechanisms (listed in

Table 8) for automatically loading internal L1 instruction

memory after a reset. A fourth mode is provided to execute from

external memory, bypassing the boot sequence.

Instruction Set Description

Table 8. Booting Modes

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and read-

ability. The instructions have been specifically tuned to provide

a flexible, densely encoded instruction set that compiles to a very

small final memory size. The instruction set also provides fully

featured multifunction instructions that allow the programmer

tousemanyoftheprocessorcoreresourcesinasingleinstruction.

Coupled with many features more often seen on microcontrol-

lers, this instruction set is very efficient when compiling C and

C++ source code. In addition, the architecture supports both

user (algorithm/application code) and supervisor (O/S kernel,

device drivers, debuggers, ISRs) modes of operation, allowing

multiple levels of access to core processor resources.

BMODE1–0

Description

00

Execute from 16-bit external memory

(Bypass Boot ROM)

Boot from 8-bit flash

Boot from SPI serial ROM (8-bit

address range)

Boot from SPI serial ROM (16-bit

address range)

01

10

11

The BMODE pins of the Reset Configuration Register, sampled

during power-on resets and software-initiated resets, implement

the following modes:

The assembly language, which takes advantage of the processor’s

unique architecture, offers the following advantages:

• Execute from 16-bit external memory – Execution

starts from address 0x2000 0000 with 16-bit packing.

The boot ROM is bypassed in this mode. All configu-

ration settings are set for the slowest device possible

(3-cycle hold time; 15-cycle R/W access times; 4-cycle

setup).

• Seamlessly integrated DSP/CPU features are optimized

for both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• Boot from 8-bit external FLASH memory – The 8-bit

FLASH boot routine located in boot ROM memory

space is set up using Asynchronous Memory Bank 0.

All configuration settings are set for the slowest device

possible (3-cycle hold time; 15-cycle R/W access times;

4-cycle setup).

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-

field manipulation, insertion, and extraction; integer

operations on 8-, 16-, and 32-bit data-types; and separate

user and supervisor stack pointers.

• Boot from SPI serial EEPROM (8-bit addressable) –

The SPI uses the PF2 output pin to select a single SPI

EPROM device, submits a read command at address

0x00, and begins clocking data into the beginning of L1

instruction memory. An 8-bit addressable SPI-compat-

ible EPROM must be used.

• Code density enhancements, which include intermixing

of 16- and 32-bit instructions (no mode switching, no

code segregation). Frequently used instructions are

encoded in 16 bits.

• Boot from SPI serial EEPROM (16-bit addressable) –

The SPI uses the PF2 output pin to select a single SPI

EPROM device, submits a read command at address

0x0000, and begins clocking data into the beginning of

L1 instruction memory. A 16-bit addressable SPI-com-

patible EPROM must be used.

Development Tools

The ADSP-BF53x Processor is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The same emulator hardware that

supports other Blackfin DSPs also fully emulates the ADSP-

BF53x Processor.

For each of the boot modes, an 10-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

efficiency. The compiler has been developed for efficient transla-

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

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ADSP-BF53x

March 2003

tion of C/C++ code to processor assembly. The processor has

architectural features that improve the efficiency of compiled

C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. TheVDKis integrated intothe VisualDSP++ devel-

opment environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gener-

ation of various VDK based objects, and visualizing the system

state, when debugging an application that uses the VDK.

TheVisualDSP++debuggerhasanumberofimportantfeatures.

Data visualization is enhanced by a plotting package that offers

a significant level of flexibility. This graphical representation of

user data enables the programmer to quickly determine the per-

formance of an algorithm. As algorithms grow in complexity, this

capability can have increasing significance on the designer’s

development schedule, increasing productivity. Statistical

profiling enables the programmer to non intrusively poll the

processor as it is running the program. This feature, unique to

VisualDSP++, enables the software developer to passively gather

important code execution metrics without interrupting the real-

timecharacteristicsoftheprogram.Essentially,thedevelopercan

identify bottlenecks in software quickly and efficiently. By using

the profiler, the programmer can focus on those areas in the

program that impact performance and take corrective action.

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of substan-

tial functionality) to quickly and reliably assemble software

applications. Download components from the Web and drop

them into the application. Publish component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of

codeanddataontheembeddedsystem. Viewmemoryutilization

in a color-coded graphical form, easily move code and data to

different areas of the processor or external memory with the drag

ofthemouse,examineruntimestackandheapusage.TheExpert

Linker is fully compatible with existing Linker Definition File

(LDF), allowing the developer to move between the graphical

and textual environments.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information).

• Insert breakpoints.

Analog Devices emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-BF53x Processor processor to monitor

and control the target board processor during emulation. The

emulator provides full speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Non

intrusive in-circuit emulation is assured by the use of the proces-

sor’s JTAG interface—the emulator does not affect target system

loading or timing.

• Set conditional breakpoints on registers, memory,

and stacks.

• Trace instruction execution.

• Perform linear or statistical profiling of program

execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the Blackfin processor family. Hardware tools

include Blackfin processor PC plug-in cards. Third party

softwaretoolsincludeDSPlibraries,real-timeoperatingsystems,

and block diagram design tools.

• Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

Designing an Emulator-Compatible Processor

Board (Target)

• Control how the development tools process inputs and

generate outputs.

The Analog Devices family of emulators are tools that every

system developer needs to test and debug hardware and software

systems.AnalogDeviceshassuppliedanIEEE1149.1JTAGTest

Access Port (TAP) on each JTAG processor. The emulator uses

the TAP to access the internal features of the processor, allowing

the developer to load code, set breakpoints, observe variables,

observe memory, and examine registers. The processor must be

halted to send data and commands, but once an operation has

been completed by the emulator, the processor system is set

running at full speed with no impact on system timing.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resourcemanagementtailoredspecificallytoaddressthememory

and timing constraints of DSP programming. These capabilities

enableengineerstodevelopcodemoreeffectively,eliminatingthe

need to start from the very beginning, when developing new

application code. The VDK features include Threads, Critical

andUnscheduledregions,Semaphores,Events,andDeviceflags.

The VDK also supports Priority-based, Preemptive, Coopera-

tive, and Time-Sliced scheduling approaches. In addition, the

VDK was designed to be scalable. If the application does not use

a specific feature, the support code for that feature is excluded

from the target system.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

14

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PRELIMINARY TECHNICAL DATA

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ADSP-BF53x

PIN DESCRIPTIONS

ADSP-BF53x Processor pin definitions are listed in Table 9.

For details on target board design issues including mechanical

layout, singleprocessorconnections, multiprocessorscanchains,

signal buffering, signal termination, and emulator pod logic, see

In order to maintain maximum functionality and reduce package

size and pin count, some pins have dual, multiplexed functional-

ity. In cases where pin functionality is reconfigurable, the default

state is shown in plain text, while alternate functionality is shown

in italics.

the EE-68: Analog Devices JTAG Emulation Technical Reference on

the Analog Devices web site (www.analog.com)—use site search

on “EE-68.” This document is updated regularly to keep pace

with improvements to emulator support.

Table 9. Pin Descriptions

Pin Name

I/O Function

Memory Interface

ADDR19–1

DATA15–0

ABE1–0/SDQM1–0

BR¹

O

Address Bus for Async/Sync Access

I/O Data Bus for Async/Sync Access

O

I

O

Byte Enables/Data Masks for Async/Sync Access

Bus Request

Bus Grant

BG

BGH

Bus Grant Hang

Asynchronous Memory Control

AMS3–0

ARDY²

AOE

ARE

AWE

O

I

O

Bank Select

Hardware Ready Control

Output Enable

Read Enable

Write Enable

Synchronous Memory Control

SRAS

SCAS

SWE

SCKE

CLKOUT

SA10

O

Row Address Strobe

Column Address Strobe

Write Enable

Clock Enable

Clock Output

A10 Pin

SMS

Bank Select

Timers

TMR0

I/O Timer 0

TMR1/PPI_FS1

TMR2/PPI_FS2

I/O Timer 1/PPI Frame Sync1

I/O Timer 2/PPI Frame Sync2

Parallel Peripheral Interface Port/GPIO

PF0/SPISS

I/O Programmable Flag 0/SPI Slave Select Input

PF1/SPISEL1/TMRCLK

PF2/SPISEL2

PF3/SPISEL3/PPI_FS3

PF4/SPISEL4/PPI15

PF5/SPISEL5/PPI14

PF6/SPISEL6/PPI13

PF7/SPISEL7/PPI12

PF8/PPI11

I/O Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference

I/O Programmable Flag 2/SPI Slave Select Enable 2

I/O Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync 3

I/O Programmable Flag 4/SPI Slave Select Enable 4 / PPI 15

I/O Programmable Flag 5/SPI Slave Select Enable 5 / PPI 14

I/O Programmable Flag 6/SPI Slave Select Enable 6 / PPI 13

I/O Programmable Flag 7/SPI Slave Select Enable 7 / PPI 12

I/O Programmable Flag 8/PPI 11

PF9/PPI10

I/O Programmable Flag 9/PPI 10

PF10/PPI9

I/O Programmable Flag 10/PPI 9

PF11/PPI8

I/O Programmable Flag 11/PPI 8

PF12/PPI7

I/O Programmable Flag 12/PPI 7

PF13/PPI6

I/O Programmable Flag 13/PPI 6

PF14/PPI5

I/O Programmable Flag 14/PPI 5

PF15/PPI4

I/O Programmable Flag 15/PPI 4

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

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Table 9. Pin Descriptions (Continued)

Pin Name

I/O Function

I/O PPI3–0

PPI3–0

PPI_CLK

Serial Ports

RSCLK0

RFS0

I

PPI Clock

I/O SPORT0 Receive Serial Clock

I/O SPORT0 Receive Frame Sync

DR0PRI

DR0SEC

TSCLK0

TFS0

I

SPORT0 Receive Data Primary

SPORT0 Receive Data Secondary

I/O SPORT0 Transmit Serial Clock

I/O SPORT0 Transmit Frame Sync

DT0PRI

DT0SEC

RSCLK1

RFS1

O

SPORT0 Transmit Data Primary

SPORT0 Transmit Data Secondary

I/O SPORT1 Receive Serial Clock

I/O SPORT1 Receive Frame Sync

DR1PRI

DR1SEC

TSCLK1

TFS1

I

SPORT1 Receive Data Primary

SPORT1 Receive Data Secondary

I/O SPORT1 Transmit Serial Clock

I/O SPORT1 Transmit Frame Sync

DT1PRI

DT1SEC

O

SPORT1 Transmit Data Primary

SPORT1 Transmit Data Secondary

SPI Port

MOSI

MISO

SCK

I/O Master Out Slave In

I/O Master In Slave Out

I/O SPI Clock

UART Port

RX

I

UART Receive

TX

O

UART Transmit

Real Time Clock

RTXI²

RTXO

I

O

RTC Crystal Input

RTC Crystal Output

JTAG Port

TCK

I

JTAG Clock

TDO

TDI

TMS

TRST

EMU

O

I

O

JTAG Serial Data Out

JTAG Serial Data In

JTAG Mode Select

JTAG Reset

Emulation Output

Clock

CLKIN

XTAL

I

O

Clock/Crystal Input

Crystal Output

Mode Controls

RESET

I

Reset

NMI²

Non-maskable Interrupt

Boot Mode Strap

BMODE1–0

Voltage Regulator

VROUT1-0

O

External FET Drive

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

16

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ADSP-BF53x

Table 9. Pin Descriptions (Continued)

Pin Name

I/O Function

Supplies

V_DDEXT

V_DDINT

V_DDRTC

GND

P

G

I/O Power Supply

Core Power Supply

Real Time Clock Power Supply

External Ground

¹This pin should always be pulled HIGH when not used.

²This pin should always be pulled LOW when not used.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter ¹

Parameter

Minimum Nominal

Maximum

Unit

V_DDINT

V_DDEXT

V_DDRTC

V_IH

V_IL

T_AMBIENT

Internal Supply Voltage

External Supply Voltage

0.7

1.2

1.26

V

2.25

2.0

2.5 or 3.3 3.6

Real Time Clock Power Supply Voltage

High Level Input Voltage², @ V_DDEXT=maximum

Low Level Input Voltage², @ V_DDEXT=minimum

Ambient Operating Temperature

Industrial

3.6

0.6

–0.3

-40

0

85

70

ºC

Commercial

¹Specifications subject to change without notice.

²The ADSP-BF53x Processor is 3.3 V tolerant (always accepts up to 3.6 V maximum V_IH), but voltage compliance (on outputs, V_OH) depends on the input

V_DDEXT, because V_OH(maximum) approximately equals V_DDEXT(maximum). This 3.3 V tolerance applies to bi-directional pins (DATA15-0, TMR2-0,

PF15-0, PPI3-0, RSCLK1-0, TSCLK1-0, RFS1-0, TFS1-0, MOSI, MISO, SCK) and input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC,

DR1PRI, DR1SEC, RX, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE1-0).

ELECTRICAL CHARACTERISTICS

Parameter¹

Test Conditions

Minimum

Maximum

Unit

V_OH

High Level Output Voltage²

Low Level Output Voltage²

High Level Input Current³

Low Level Input Current⁴

@ V_DDEXT=3.0V,

I_OH= –0.5 mA

@ V_DDEXT=3.0V,

I_OL= 2.0 mA

@ V_DDEXT=maximum,

V_IN= V_DDmaximum

@ V_DDEXT=maximum,

V_IN= 0 V

2.4

V

V_OL

I_IH

0.4

V

TBD

µA

pF

I_IL

I_OZH

I_OZL

C_IN

Three-State Leakage Current⁴@ V_DDEXT= maximum,

V_IN= V_DDmaximum

Three-State Leakage Current⁵@ V_DDEXT= maximum,

V_IN= 0 V

Input Capacitance^{5, 6}

f_IN= 1 MHz,

T_CASE= 25°C,

V_IN= 2.5 V

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins.

³Applies to input pins.

⁴Applies to three-statable pins.

⁵Applies to all signal pins.

⁶Guaranteed, but not tested.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-BF53x

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage¹(V_DDINT) . . . . . . –0.3 V to +1.5 V

External (I/O) Supply Voltage¹(V_DDEXT) . . . . . . . –0.3 V to +4.0 V

Input Voltage¹. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V

Output Voltage Swing¹. . . . . . . . . . . . . . –0.5 V to V_DDEXT+0.5 V

Load Capacitance^1,2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF

Core Clock (CCLK)¹

ADSP-BF533 . . . . . . . . . . . . . . . . . . . . . . . . .600 MHz

ADSP-BF532/BF531. . . . . . . . . . . . . . . . . . . .400 MHz

Peripheral Clock (SCLK)¹. . . . . . . . . . . . . . . . . . . . . .133 MHz

Storage Temperature Range¹. . . . . . . . . . . . . . –65ºC to +150ºC

Lead Temperature (5 seconds)¹. . . . . . . . . . . . . . . . . . . . . 185ºC

¹Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any other

conditions greater than those indicated in the operational sections of this specification

is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

²For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at

3.3V) or 30 pF (at 2.5V) for ADDR, DATA, ABE/SDQM, CLKOUT, SCKE, SA10,

SRAS, SCAS, SWE, and SMS.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-BF53x Processor features proprietary ESD protection

circuitry, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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ADSP-BF53x

TIMING SPECIFICATIONS

March 2003

Table 10 and Table 12 describe the timing requirements for the ADSP-BF53x Processor clocks. Take care in selecting MSEL, SSEL,

and CSEL ratios so as not to exceed the maximum core clock, system clock and Voltage Controlled Oscillator (VCO) operating

frequencies, as described in ABSOLUTE MAXIMUM RATINGS. Table 12 describes Phase-Locked Loop operating conditions.

Table 10. Core and System Clock Requirements—ADSP-BF533

Parameter

Minimum

Maximum Unit

t_CCLK1.2

t_CCLK1.1

t_CCLK1.0

t_CCLK0.9

t_CCLK0.8

t_CCLK0.7

t_SCLK

Core Cycle Period (V_DDINT=1.2 V–5%)

Core Cycle Period (V_DDINT=1.1 V–5%)

Core Cycle Period (V_DDINT=1.0 V–5%)

Core Cycle Period (V_DDINT=0.9 V–5%)

Core Cycle Period (V_DDINT=0.8 V–5%)

Core Cycle Period (V_DDINT=0.7 V–5%)

System Clock Period

1.67

TBD

ns

Maximum of (7.5 or t_CCLKNN

)

Table 11. Core and System Clock Requirements—ADSP-BF532/531

Parameter

Minimum

Maximum Unit

t_CCLK1.2

t_CCLK1.1

t_CCLK1.0

t_CCLK0.9

t_CCLK0.8

t_CCLK0.7

t_SCLK

Core Cycle Period (V_DDINT=1.2 V–5%)

Core Cycle Period (V_DDINT=1.1 V–5%)

Core Cycle Period (V_DDINT=1.0 V–5%)

Core Cycle Period (V_DDINT=0.9 V–5%)

Core Cycle Period (V_DDINT=0.8 V–5%)

Core Cycle Period (V_DDINT=0.7 V–5%)

System Clock Period

2.5

TBD

ns

Maximum of (7.5 or t_CCLKNN

)

Table 12. Phase-Locked Loop Operating Conditions

Parameter

Minimum

Maximum

Maximum CCLK

Unit

Voltage Controlled Oscillator (VCO) Frequency

50

MHz

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Clock and Reset Timing

Table 13 and Figure 11 describe clock and reset operations. Per ABSOLUTE MAXIMUM RATINGS on Page 19, combinations of

CLKIN and clock multipliers must not select core/peripheral clocks in excess of 600/133 MHz.

Table 13. Clock and Reset Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_CKIN

CLKIN Period

30.0

10.0

11 t_CKIN

100.0

ns

t_CKINL

t_CKINH

t_WRST

CLKIN Low Pulse¹

CLKIN High Pulse¹

RESET Asserted Pulsewidth Low²

Switching Characteristics

t_SCLK

CLKOUT Period³

7.5

ns

¹Applies to bypass mode and non-bypass mode.

²Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while

RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

³The figure below shows a x2 ratio between t_CKINand t_SCLK, but the ratio has many programmable options. For more information, see the System Design

chapter of the ADSP-BF533 Processor Hardware Reference.

t_CKIN

CLKIN

t_CKINL

t_CKINH

t_WRST

RESET

t_SCLKD

t_SCLK

CLKOUT

Figure 11. Clock and Reset Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Asynchronous Memory Read Cycle Timing

Table 14. Asynchronous Memory Read Cycle Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SDAT

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

2.1

0.8

5.5

0.0

ns

t_HDAT

t_SARDY

t_HARDY

Switching Characteristic

t_DO

t_HO

Output Delay After CLKOUT¹

Output Hold After CLKOUT ¹

6.0

ns

0.8

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

3 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

t_SDAT

t_HDAT

DATA15–0

READ

AOE

t_DO

ARE

t_HARDY

t_SARDY

t_HARDY

ARDY

Figure 12. Asynchronous Memory Read Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Asynchronous Memory Write Cycle Timing

Table 15. Asynchronous Memory Write Cycle Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SARDY

t_HARDY

t_DDAT

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

DATA15–0 Disable After CLKOUT

DATA15–0 Enable After CLKOUT

5.5

0.0

ns

6.0

t_ENDAT

1.0

Switching Characteristic

t_DO

t_HO

Output Delay After CLKOUT¹

Output Hold After CLKOUT ¹

ns

0.8

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

ACCESS

EXTENDED

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED WRITE

ACCESS 2 CYCLES

HOLD

1 CYCLE

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

t_ENDAT

t_DDAT

DATA15–0

WRITE DATA

AWE

t_SARDY

t_HARDY

ARDY

Figure 13. Asynchronous Memory Write Cycle Timing

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SDRAM Interface Timing

Table 16. SDRAM Interface Timing

Parameter

Minimum

Maximum

Unit

Timing Requirement

t_SSDAT

DATA Setup Before CLKOUT

2.1

0.8

ns

t_HSDAT

DATA Hold After CLKOUT

Switching Characteristic

t_SCLK

CLKOUT Period

CLKOUT Width High

CLKOUT Width Low

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

Command, ADDR, Data Delay After CLKOUT¹

Command, ADDR, Data Hold After CLKOUT¹

Data Disable After CLKOUT

6.0

0.8

1.0

Data Enable After CLKOUT

¹Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

t_SCLK

t_SCLKH

CLKOUT

t_SSDAT

t_SCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 14. SDRAM Interface Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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External Port Bus Request and Grant Cycle Timing

Table 17 and Figure 15 describe external port bus request and bus grant operations.

Table 17. External Port Bus Request and Grant Cycle Timing

Parameter^{, 1, 2}

Minimum

Maximum

Unit

Timing Requirements

t_BS

t_BH

BR asserted to CLKOUT high setup

CLKOUT high to BR de-asserted hold time

4.6

0.0

ns

Switching Characteristics

t_SD

t_SE

CLKOUT high to xMS, address, and RD/WR disable

CLKOUT low to xMS, address, and RD/WR enable

4.3

4.0

2.2

2.4

ns

t_DBGCLKOUT high to BG asserted setup

t_EBGCLKOUT high to BG de-asserted hold time

t_DBHCLKOUT high to BGH asserted setup

t_EBHCLKOUT high to BGH de-asserted hold time

¹These are preliminary timing parameters that are based on worst-case operating conditions.

²The pad loads for these timing parameters are 20 pF.

CLKOUT

t_BS

t_BH

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 15. External Port Bus Request and Grant Cycle Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Parallel Peripheral Interface Timing

Table 18 and Figure 16 on page 26, Figure 17 on page 27, and Figure 18 on page 27describe Parallel Peripheral Interface operations.

Table 18. Parallel Peripheral Interface Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_PCLKW

PPI_CLK Width

GP Frame Capture and GP Input Modes

GP Output Mode

6.0

10.0

ns

t_PCLK

PPI_CLK Period¹

GP Frame Capture and GP Input Modes

GP Output Mode

15.0

25.0

ns

Timing Requirements - GP Input and Frame Capture Modes

t_SDRE

t_HDRE

t_IDFSE

t_IFS1D

Receive Data Setup Before PPI_CLK²

Receive Data Hold After PPI_CLK²

FS Input Delay After PPI_CLK

3.0

ns

3.0

65535

Delay Between FS1 Assertion and Valid Data (Input Mode) 0

PPI_CLK periods

Switching Characteristics - GP Output and Frame Capture Modes

t_ODFSE

t_DDTE

Output FS Delay After PPI_CLK³

Transmit Data Delay After PPI_CLK³

(GP Output Mode)

12.0

ns

t_HDTE

t_OFS1D

t_FS12

Transmit Data Hold After PPI_CLK³

Delay Between FS1 Assertion and Valid Data

Delay Between FS2 and FS1 Assertion⁴

5.0

1

0

ns

65536

PPI_CLK periods

¹PPI_CLK frequency cannot exceed f_SCLK/2

²Referenced to sample edge.

³Referenced to drive edge.

⁴FS2 period must be an integer multiple of FS1 period.

t_{P CL K}

t_{PCLK W}

PPI_CLK

t_{OF S1D}

t_{ODFS E}

PPI_FS1

t_{HD TE}

ELEMENT N-1

ELEMENT N

ELEMENT 1

PPIX

t_{D DTE}

NOTES: CLOCK AND FRAME SYNC POLARITIES ARE PROGRAMMABLE. PPI_DELAY = 0 IN THIS FIGURE.

ELEMENT 1 IS THE FIRST DATA WORD FRAMED BY THE PPI_FS1 EDGE SHOWN. ELEMENT N BELONGS

TO THE PRE VIOUS FRAM E.

Figure 16. GP Output Mode and Frame Capture Timing

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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PP I_CLK

t_{IF S 1 D}

t_{ID FSE}

P PI_FS1

PPIX

t_{SD R E}

ELEMENT N

ELEMENT 1

ELEMENT 2

t_{H D R E}

NOTE S: CLOCK AND FRAME SYNC P OLARITIES ARE PROGRAMMABLE. P PI_DE LAY = 0 IN THIS FIG URE .

ELEMENT 1 IS THE FIRST DATA W ORD FRAMED BY THE PP I_FS 1 E DG E SHOW N. E LE ME NT N BE LONGS

TO THE PRE VIOUS FRAM E.

Figure 17. GP Input Timing

t_{PCL K}

t_PCLKW

PPI_CLK

PPI_FS1

t_FS12

PPI_FS2

PPI_FS3

Figure 18. General Purpose Frame Capture and Output Mode Timing

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Serial Ports

Table 19. Serial Ports—External Clock

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SFSE

t_HFSE

t_SDRE

t_HDRE

t_SCLKEW

t_SCLKE

TFS/RFS Setup Before TSCLK/RSCLK¹

3.0

4.5

15.0

ns

TFS/RFS Hold After TSCLK/RSCLK¹

Receive Data Setup Before RSCLK¹

Receive Data Hold After RSCLK¹

TSCLK/RSCLK Width

TSCLK/RSCLK Period

¹Referenced to sample edge.

Table 20. Serial Ports—Internal Clock

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

t_SCLKEW

t_SCLKE

TFS/RFS Setup Before TSCLK/RSCLK¹

6.0

0.0

6.0

0.0

4.5

15.0

ns

TFS/RFS Hold After TSCLK/RSCLK¹

Receive Data Setup Before RSCLK¹

Receive Data Hold After RSCLK¹

TSCLK/RSCLK Width

TSCLK/RSCLK Period

¹Referenced to sample edge.

Table 21. Serial Ports—External Clock

Parameter

Minimum Maximum Unit

Switching Characteristics

t_DFSETFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)¹

t_HOFSETFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)¹

t_DDTETransmit Data Delay After TSCLK¹

10.0

ns

0.0

t_HDTETransmit Data Hold After TSCLK¹

¹Referenced to drive edge.

Table 22. Serial Ports—Internal Clock

Parameter

Minimum Maximum Unit

Switching Characteristics

t_DFS

t_HOFS

t_DDT

t_HDT

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)¹

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)¹

Transmit Data Delay After TSCLK¹

4.0

ns

I

0.0

I

Transmit Data Hold After TSCLK¹

0.0

4.5

I

t_SCLKIWTSCLK/RSCLK Width

¹Referenced to drive edge.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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Table 23. Serial Ports—Enable and Three-State

Parameter

Minimum

Maximum

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TSCLK¹

Data Disable Delay from External TSCLK¹

Data Enable Delay from Internal TSCLK

Data Disable Delay from Internal TSCLK¹

5.0

2.0

ns

12.0

5.0

¹Referenced to drive edge.

Table 24. External Late Frame Sync

Parameter

Minimum Maximum Unit

Switching Characteristics

t_DDTLFSEData Delay from Late External TFS or External RFS with MCE = 1, MFD = 0^1,2

t_DTENLFSEData Enable from late FS or MCE = 1, MFD = 0^1,2

10.5

ns

3.5

¹MCE = 1, TFS enable and TFS valid follow t_DDTENFSand t_DDTLFSE

²If external RFS/TFS setup to RSCLK/TSCLK > t_SCLKE/2 then t_DDTLSCKand t_DTENLSCKapply, otherwise t_DDTLFSEand t_DTENLFSapply.

.

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DATA RECEIVE- INTERNAL CLOCK

DATA RECEIVE- EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

RSCLK

t_DFSE

t_HOFSE

RFS

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

RFS

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DR

DATA TRANSMIT- INTERNAL CLOCK

DATA TRANSMIT- EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

TSCLK

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

TFS

DT

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK / RSCLK

t_DDTTE

t_DDTEN

DT

DRIVE

EDGE

DRIVE

EDGE

TSCLK (INT)

TFS ("LATE", INT.)

TSCLK / RSCLK

t_DDTIN

t_DDTTI

DT

Figure 19. Serial Ports

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EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

RSCLK

RFS

t_HOFSE/I

t_SFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

1ST BIT

2ND BIT

DT

t_DDTLFSE

LATE EXTERNAL TFS

DRIVE

SAMPLE

DRIVE

TSCLK

TFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_DDTENFS

t_HDTE/I

DT

1ST BIT

2ND BIT

t_DDTLFSE

Figure 20. External Late Frame Sync (Frame Sync Setup < t_SCLKE/2)

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EXTERNAL RFS WITH MCE=1, MFD=0

DRIVE

SAMPLE

DRIVE

RSCLK

RFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_HDTE/I

t_DTENLSCK

1ST BIT

DT

2ND BIT

t_DDTLSCK

LATE EXTERNAL TFS

DRIVE

SAMPLE

DRIVE

TSCLK

TFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_HDTE/I

t_DTENLSCK

DT

1ST BIT

2ND BIT

t_DDTLSCK

Figure 21. External Late Frame Sync (Frame Sync Setup > t_SCLKE/2)

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Serial Peripheral Interface (SPI) Port—Master Timing

Table 25 and Figure 22 describe SPI port master operations.

Table 25. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SSPID

t_HSPID

Data input valid to SCK edge (data input setup)

SCK sampling edge to data input invalid

6.0

0

ns

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

t_SPITDM

t_DDSPID

t_HDSPID

SPISELx low to first SCK edge (x=0 or 1)

Serial clock high period

Serial clock low period

Serial clock period

Last SCK edge to SPISELx high (x=0 or 1)

Sequential transfer delay

SCK edge to data out valid (data out delay)

SCK edge to data out invalid (data out hold)

2t_SCLK-1.5

4t_SCLK-1.5

2t_SCLK-1.5

0

ns

6

5

0

SPISELx

(OUTPUT)

t_SPICLK

t_HDSM

t_SPITDM

t_SDSCIM

t_SPICHM

t_SPICLM

SCK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCK

(CPOL = 1)

(OUTPUT)

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

CPHA=1

t_SSPID

t_HSPID

t_SSPID

t_HSPID

MISO

(INPUT)

MSB VALID

LSB VALID

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

CPHA=0

t_SSPID

t_HSPID

MISO

(INPUT)

MSB VALID

LSB VALID

Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing

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Serial Peripheral Interface (SPI) Port—Slave Timing

Table 26 and Figure 23 describe SPI port slave operations.

Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

Serial clock high period

Serial clock low period

Serial clock period

Last SCK edge to SPISS not asserted

Sequential Transfer Delay

SPISS assertion to first SCK edge

Data input valid to SCK edge (data input setup)

SCK sampling edge to data input invalid

2t_SCLK-1.5

4t_SCLK-1.5

2t_SCLK-1.5

1.6

ns

1.6

Switching Characteristics

t_DSOE

SPISS assertion to data out active

0

8

10

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS deassertion to data high impedance

SCK edge to data out valid (data out delay)

SCK edge to data out invalid (data out hold)

SPISS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCK

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

SCK

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

MSB

t_DDSPID

t_DSDHI

LSB

MISO

(OUTPUT)

t_HSPID

t_SSPID

CPHA=1

t_SSPID

t_HSPID

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOE

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_HSPID

CPHA=0

t_SSPID

MOSI

(INPUT)

MSB VALID

LSB VALID

Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing

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Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing

Figure 24 describes UART port receive and transmit operations. The maximum baud rate is SCLK/16. As shown in Figure 24 there

is some latency between the generation internal UART interrupts and the external data operations. These latencies are negligible at

the data transmission rates for the UART.

CLKOUT

(SAMPLE CLOCK)

RXD

DATA(5–8)

STOP

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

START

TXD

DATA(5–8)

STOP (1–2)

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 24. UART Port—Receive and Transmit Timing

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Timer Cycle Timing

Table 27 and Figure 25 describe timer expired operations. The input signal is asynchronous in “width capture mode” and “external

clock mode” and has an absolute maximum input frequency of f_SCLK/2 MHz.

Table 27. Timer Cycle Timing

Parameter

Minimum

Maximum

Unit

Timing Characteristics

t_WL

Timer Pulsewidth Input Low¹

Timer Pulsewidth Input High¹

1

SCLK cycles

t_WH

Switching Characteristic

t_HTO

Timer Pulsewidth Output²

1

(2³²–1)

SCLK cycles

¹The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in

PWM output mode.

²The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

CLKOUT

t_HTO

TMRx

(PWM OUTPUT MODE)

TMRx

t_WL

t_WH

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

Figure 25. Timer PWM_OUT Cycle Timing

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Programmable Flags Cycle Timing

Table 28 and Figure 26 describe programmable flag operations.

Table 28. Programmable Flags Cycle Timing

Parameter

Minimum

Maximum

Unit

ns

Timing Requirement

t_WFI

Switching Characteristic

t_DFOFlag output delay from CLKOUT low

Flag input pulsewidth

t_SCLK+ 1

6

ns

CLKOUT

t_DFO

PF (OUTPUT)

FLAG OUTPUT

t_WFI

PF (INPUT)

FLAG INPUT

Figure 26. Programmable Flags Cycle Timing

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JTAG Test And Emulation Port Timing

Table 29 and Figure 27 describe JTAG port operations.

Table 29. JTAG Port Timing

Parameter

Minimum

Maximum

Unit

Timing Parameters

t_TCK

TCK Period

20

4

5

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulsewidth²

ns

4

TCK cycles

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

12

ns

0

¹System Inputs=DATA15-0, ARDY, TMR2-0, PF15-0, PPI_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC,

MOSI, MISO, SCK, RX, RESET, NMI, BMODE1-0, BR, PP3-0.

²50 MHz Maximum

³System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2-0, PF15-

0, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3-0.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 27. JTAG Port Timing

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160-LEAD BGA PINOUT

Table 30 lists the BGA pinout by signal name. Table 31 on Page 40 lists the pinout by lead number.

Table 30. 160-Lead BGA Lead Assignment (Alphabetically by Signal)

Lead

Signal

Number

Signal

Number

Signal

Number

Signal

Number

ABE0

ABE1

H13

H12

J14

DATA12

DATA13

DATA14

DATA15

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DR0PRI

DR0SEC

DR1PRI

DR1SEC

DT0PRI

DT0SEC

DT1PRI

DT1SEC

EMU

GND

M5

N5

P5

P4

P9

M8

N8

P8

M7

N7

P7

M6

K1

J2

G3

F3

GND

MISO

MOSI

NMI

PF0

L6

L8

SCK

SCKE

SMS

SRAS

SWE

TCK

TDI

TDO

TFS0

TFS1

TMR0

TMR1

TMR2

TMS

TRST

D1

B13

C13

D13

D12

P2

M3

N3

H3

E1

L2

M1

K2

N2

N1

J1

F1

K3

A1

C7

C12

D5

D9

F12

G4

J4

J12

L7

L11

P1

D6

E4

E11

J11

L4

ADDR1

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

AMS0

L10

M4

M10

P14

E2

D3

B10

D2

C1

A4

A5

B5

M13

M14

N14

N13

N12

M11

N11

P13

P12

P11

K14

L14

J13

K13

L13

K12

L12

M12

E14

F14

F13

G12

G13

E13

G14

H14

P10

N10

N4

PF1

PF10

PF11

PF12

PF13

PF14

PF15

PF2

PF3

PF4

PF5

PF6

PF7

PF8

PF9

PPI0

PPI1

PPI2

PPI3

PPI_CLK

RESET

RFS0

RFS1

RSCLK0

RSCLK1

RTXI

RTXO

RX

B6

A6

C6

C2

C3

B1

B2

B3

B4

A2

A3

C8

B8

A7

B7

C9

C10

J3

G2

L1

G1

A9

A8

L3

E12

C14

TSCLK0

TSCLK1

TX

H1

H2

F2

VDDEXT

VDDINT

VDDRTC

VROUT0

VROUT1

XTAL

E3

M2

A10

A14

B11

C4

AMS1

AMS2

AMS3

AOE

ARDY

ARE

AWE

BG

C5

C11

D4

D7

D8

D10

D11

F4

F11

G11

H4

H11

K4

K11

L5

BGH

BMODE0

BMODE1

BR

CLKIN

CLKOUT

DATA0

DATA1

DATA10

DATA11

P3

D14

A12

B14

M9

N9

N6

L9

B9

A13

B12

A11

GND

SA10

SCAS

P6

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Table 31. 160-Lead BGA Lead Assignment (Numerically by Lead Number)

Lead

Number Signal

Lead

Number Signal

Lead

Number Signal

Lead

Number Signal

A1

A2

A3

A4

A5

A6

A7

A8

VDDEXT

PF8

PF9

PF10

PF11

PF14

PPI2

RTXO

RTXI

GND

XTAL

CLKIN

VROUT0

GND

PF4

PF5

PF6

PF7

PF12

PF13

PPI3

PPI1

VDDRTC

NMI

GND

VROUT1

SCKE

CLKOUT

PF1

C13

C14

D1

D2

D3

D4

D5

D6

D7

SMS

SCAS

SCK

PF0

MOSI

GND

VDDEXT

VDDINT

GND

VDDEXT

GND

SWE

SRAS

BR

TFS1

MISO

DT1SEC

VDDINT

SA10

ARDY

AMS0

TSCLK1

DT1PRI

DR1SEC

GND

H1

H2

H3

H4

H11

H12

H13

H14

J1

DT0PRI

DT0SEC

TFS0

GND

ABE1

ABE0

AWE

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

N13

N14

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

TDI

GND

DATA12

DATA9

DATA6

DATA3

DATA0

GND

ADDR15

ADDR9

ADDR10

ADDR11

TRST

A9

TSCLK0

DR0SEC

RFS0

A10

A11

A12

A13

A14

B1

B2

B3

B4

B5

D8

D9

J2

J3

J4

D10

D11

D12

D13

D14

E1

E2

E3

E4

E11

E12

E13

E14

F1

F2

F3

F4

F11

F12

F13

F14

G1

G2

G3

G4

G11

G12

G13

G14

VDDEXT

VDDINT

VDDEXT

ADDR4

ADDR1

DR0PRI

TMR2

TX

J11

J12

J13

J14

K1

K2

K3

K4

K11

K12

K13

K14

L1

L2

L3

L4

L5

L6

L7

L8

L9

TMS

TDO

BMODE0

DATA13

DATA10

DATA7

DATA4

DATA1

BGH

ADDR16

ADDR14

ADDR13

ADDR12

VDDEXT

TCK

BMODE1

DATA15

DATA14

DATA11

DATA8

DATA5

DATA2

BG

ADDR19

ADDR18

ADDR17

GND

B6

B7

B8

B9

GND

ADDR7

ADDR5

ADDR2

RSCLK0

TMR0

RX

VDDINT

GND

VDDEXT

GND

VDDINT

GND

VDDEXT

ADDR8

ADDR6

ADDR3

TMR1

EMU

B10

B11

B12

B13

B14

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

GND

PF2

PF3

VDDEXT

AMS2

AMS1

RSCLK1

RFS1

DR1PRI

VDDEXT

GND

PF15

VDDEXT

PPI0

PPI_CLK

RESET

GND

VDDEXT

L10

L11

L12

L13

L14

M1

M2

AMS3

AOE

ARE

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

40

REV. PrA

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

March 2003

ADSP-BF53x

1

2

3

4

5

6

7

8

9

10 11 12 13 14

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY:

V

GND

I/O

DDINT

DDRTC

V

DDEXT

ROUT

Figure 28. 160-Ball Metric BGA Pin Configuration (Top

View)

14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

KEY:

V

GND

DDINT

DDRTC

ROUT

V

I/O

DDEXT

Figure 29. 160-Ball Metric BGA Pin Configuration (Bottom

View)

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

41

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

OUTLINE DIMENSIONS

March 2003

ADSP-BF53x

Dimensions in the outline dimension figure on Page 42 are

shown in millimeters.

160-Lead Metric Plastic Ball Grid Array (mini-BGA)

(BC-160)

12.00 BSC SQ

A1 CORNER

INDEX AREA

1

14 12 10

13 11

8

6

4

2

9

7

5

3

A

B

C

D

E

F

BALL A1

INDICATOR

10.40

BSC

SQ

G

H

J

K

L

M

N

P

TOP VIEW

0.80 BSC

BALL PITCH

BOTTOM VIEW

0.85 MIN

1.70

MAX

DETAIL A

SEATING

PLANE

0.12

MAX

COPLANARITY

0.55

0.50

0.45

0.40 NOM

(NOTE 3)

NOTES

1. DIMENSIONS ARE IN MILLIMETERS.

BALL DIAMETER

2. COMPLIES WITH JEDEC REGISTERED OUTLINE

MO-205, VARIATION AE.

DETAIL A

3. MINIMUM BALL HEIGHT 0.25.

176-LEAD LQFP (ST-176-1)

26.00 BSC SQ

24.00 BSC SQ

0.75

0.60

0.45

133

132

176

1

PIN 1

0.27

0.22 TYP

0.17

SEATING

PLANE

0.08 MAX LEAD

COPLANARITY

0.15

0.05

89

1.45

1.40

1.35

44

45

88

1.60 MAX

0.50 BSC

LEAD PITCH

DETAIL A

TOP VIEW (PINS DOWN)

NOTES:

1. DIMENSIONS IN MILLIMETERS.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS

IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

42

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

ORDERING GUIDE

March 2003

ADSP-BF53x

Table 32.

Ambient Temperature Maximum

Part Number

Range

Instruction Rate Operating Voltage

ADSP-BF533SKBC-600

ADSP-BF533SBBC-500

ADSP-BF532SBBC-400

ADSP-BF532SBST-300

0ºC to 70ºC

600 MHz

500 MHz

400 MHz

300 MHz

0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

-40ºC to 85ºC

ADSP-BF531SBBC-400

ADSP-BF531SBST-300

-40ºC to 85ºC

400 MHz

300 MHz

0.7 V to 1.2 V internal, 2.5 V or 3.3 V I/O

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

43

PRELIMINARY TECHNICAL DATA

For current information contact Analog Devices at 800/262-5643

March 2003

ADSP-BF53x

This information applies to a product under development. Its characteristics and specifications are subject to change with-

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

REV. PrA

44


型号：	ADSP-BF531SBBC-400
厂家：	ADI
描述：	IC 16-BIT, 40 MHz, OTHER DSP, PBGA160, ROHS COMPLIANT, MO-205AE, CSBGA-160, Digital Signal Processor 时钟外围集成电路
文件：	总44页 (文件大小：649K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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