ADSP-BF535PKB-350_技术文档

®

Blackfin

a

Embedded Processor

ADSP-BF535

Memory Management Unit for Memory Protection

Glueless External Memory Controllers

Synchronous SDRAM Support

KEY FEATURES

350 MHz High Performance Blackfin Processor Core

Two 16-Bit MACs, Two 40-Bit ALUs, One 40-Bit Shifter,

Four 8-Bit Video ALUs, and Two 40-Bit Accumulators

RISC-Like Register and Instruction Model for Ease of

Programming and Compiler Friendly Support

Advanced Debug, Trace, and Performance Monitoring

1.0 V–1.6 V Core V_DDwith Dynamic Power Management

3.3 V I/O

Asynchronous with SRAM, Flash, ROM Support

PERIPHERALS

32-Bit, 33 MHz, 3.3 V, PCI 2.2 Compliant Bus Interface

with Master and Slave Support

Integrated USB 1.1 Compliant Device Interface

260-Ball PBGA Package

Two UARTs, One with IrDA^®

Two SPI Compatible Ports

MEMORY

Two Full-Duplex Synchronous Serial Ports (SPORTs)

Four Timer/Counters, Three with PWM Support

Sixteen Bidirectional Programmable Flag I/O Pins

Watchdog Timer

Real-Time Clock

On-Chip PLL with 1

؋

to 31

؋

Frequency Multiplier

308K Bytes of On-Chip Memory:

16K Bytes of Instruction L1 SRAM/Cache

32K Bytes of Data L1 SRAM/Cache

4K Bytes of Scratch Pad L1 SRAM

256K Bytes of Full Speed, Low Latency L2 SRAM

Memory DMA Controller

FUNCTIONAL BLOCK DIAGRAM

INTERRUPT

CONTROLLER/

TIMER

JTAG TEST AND

EMULATION

WATCHDOG TIMER

32

REAL-TIME CLOCK

B

L1

UART PORT 0

IrDA

MMU

INSTRUCTION

MEMORY

DATA

MEMORY

256K BYTES L2 SRAM

UART PORT 1

64

TIMER0, TIMER1,

TIMER2

32

SYSTEM BUS

INTERFACE UNIT

PROGRAMMABLE

FLAGS

32

USB INTERFACE

SERIAL PORTS (2)

DMA

CONTROLLER

SPI PORTS (2)

BOOT ROM

32

PCI BUS INTERFACE

EXTERNAL PORT

FLASH SDRAM

CONTROL

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. How-

ever, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registered trademarks are the property of their respective

owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel:781/329-4700

Fax:781/326-8703

www.analog.com

.

ADSP-BF535

TABLE OF CONTENTS

Programmable Flags Cycle Timing . . . . . . . . . . . 25

Timer PWM_OUT Cycle Timing . . . . . . . . . . . . 26

Asynchronous Memory Write Cycle Timing . . . . 27

Asynchronous Memory Read Cycle Timing . . . . . 28

SDRAM Interface Timing . . . . . . . . . . . . . . . . . . 29

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Serial Peripheral Interface (SPI) Port

—Master Timing . . . . . . . . . . . . . . . . . . . . . . . 32

Serial Peripheral Interface (SPI) Port

—Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . 33

Universal Asynchronous Receiver-Transmitter

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2

Portable Low Power Architecture . . . . . . . . . . . . . . . 2

System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

ADSP-BF535 Peripherals . . . . . . . . . . . . . . . . . . . . . 3

Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . 4

Internal (On-Chip) Memory . . . . . . . . . . . . . . . . . . 5

External (Off-Chip) Memory . . . . . . . . . . . . . . . . . 5

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . 5

Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Event Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Core Event Controller (CEC) . . . . . . . . . . . . . . . . 6

System Interrupt Controller (SIC) . . . . . . . . . . . . . 6

Event Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Memory Control . . . . . . . . . . . . . . . . . . . . . 8

PC133 SDRAM Controller . . . . . . . . . . . . . . . . . . 8

Asynchronous Controller . . . . . . . . . . . . . . . . . . . . 8

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

PCI Host Function . . . . . . . . . . . . . . . . . . . . . . . . . 8

PCI Target Function . . . . . . . . . . . . . . . . . . . . . . . 8

USB Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Ports (Sports) . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . 10

UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Programmable Flags (PFX) . . . . . . . . . . . . . . . . . . . 11

Dynamic Power Management . . . . . . . . . . . . . . . . . 11

Full On Operating Mode

(UART) Port—Receive and Transmit Timing . 34

JTAG Test and Emulation Port Timing . . . . . . . . 35

Output Drive Currents . . . . . . . . . . . . . . . . . . . . 36

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Output Enable Time . . . . . . . . . . . . . . . . . . . . 37

Output Disable Time . . . . . . . . . . . . . . . . . . . . 37

Example System Hold Time Calculation . . . . . 37

Environmental Conditions . . . . . . . . . . . . . . . . . . 38

260-Ball PBGA Pinout . . . . . . . . . . . . . . . . . . . . . . 39

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 44

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 44

GENERAL DESCRIPTION

The ADSP-BF535 processor is a member of the Blackfin

processor family of products, incorporating the Micro Signal

Architecture (MSA), jointly developed by Analog Devices, Inc.

and Intel Corporation. The architecture combines a dual MAC

state-of-the-art signal processing engine, the advantages of a

clean, orthogonal RISC-like microprocessor instruction set, and

Single-Instruction, Multiple Data (SIMD) multimedia capabili-

ties into a single instruction set architecture.

– Maximum Performance . . . . . . . . . . . . . . . . . 11

Active Operating Mode

– Moderate Power Savings . . . . . . . . . . . . . . . . 11

Sleep Operating Mode

– High Power Savings . . . . . . . . . . . . . . . . . . . . 11

Deep Sleep Operating Mode

– Maximum Power Savings . . . . . . . . . . . . . . . . 12

Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Peripheral Power Control . . . . . . . . . . . . . . . . . . . 13

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Instruction Set Description . . . . . . . . . . . . . . . . . . . 14

Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 15

EZ-KITLite™ forADSP-BF535 Blackfin Processor 16

Designing an Emulator Compatible

By integrating a rich set of industry leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like programma-

bility, multimedia support, and leading edge signal processing in

one integrated package.

Portable Low Power Architecture

Blackfin processors provide world class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature dynamic power

management, the ability to independently vary both the voltage

and frequency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

substantial reduction in power consumption, by comparison to

just varying the frequency of operation. This translates into

longer battery life for portable appliances.

Processor Board (Target) . . . . . . . . . . . . . . . . . 16

Additional Information . . . . . . . . . . . . . . . . . . . . . . 16

PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 17

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 21

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 22

ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 22

TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 23

Clock and Reset Timing . . . . . . . . . . . . . . . . . . . . 24

System Integration

The ADSP-BF535 Blackfin processor is a highly integrated

system-on-a-chip solution for the next generation of digital com-

munication and portable Internet appliances. By combining

industry-standard interfaces with a high performance signal

processing core, users can develop cost-effective solutions

quickly without the need for costly external components. The

ADSP-BF535 Blackfin processor system peripherals include

UARTs, SPIs, SPORTs, general-purpose Timers, a Real-Time

–2–

REV. A

ADSP-BF535

Clock, Programmable Flags, Watchdog Timer, and USB and

PCI buses for glueless peripheral expansion.

All of the peripherals, except for programmable flags, real-time

clock,andtimers,aresupportedbyaflexibleDMAstructurewith

individual DMA channels integrated into the peripherals. There

is also a separate memory DMA channel dedicated to data

transfers between the various memory spaces including external

SDRAM and asynchronous memory, internal Level 1 and Level

2 SRAM, and PCI memory spaces. Multiple on-chip 32-bit

buses, running at up to 133 MHz, provide adequate bandwidth

to keep the processor core running along with activity on all of

the on-chip and external peripherals.

ADSP-BF535 Peripherals

The ADSP-BF535 Blackfin processor contains a rich set of

peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance. See Functional Block

Diagram on Page 1. The base peripherals include general-

purpose functions such as UARTs, timers with PWM (Pulse

Width Modulation) and pulse measurement capability, general-

purpose flag I/O pins, a real-time clock, and a watchdog timer.

This set of functions satisfies a wide variety of typical system

support needs and is augmented by the system expansion capa-

bilities of the part. In addition to these general-purpose

peripherals, the ADSP-BF535 Blackfin processor contains high

speed serial ports for interfaces to a variety of audio and modem

CODEC functions. It also contains an event handler for flexible

management of interrupts from the on-chip peripherals and

external sources. And it contains power management control

functions to tailor the performance and power characteristics of

the processor and system to many application scenarios.

Processor Core

As shown in Figure 1, the Blackfin processor core contains two

multiplier/accumulators (MACs), two 40-bit ALUs, four video

ALUs, and a single shifter. The computational units process

8-bit, 16-bit, or 32-bit data from the register file.

Each MAC performs a 16-bit by 16-bit multiply in every cycle,

with an accumulation to a 40-bit result, providing 8 bits of

extended precision.

The ALUs perform a standard set of arithmetic and logical oper-

ations.WithtwoALUscapableofoperatingon16-or32-bitdata,

the flexibility of the computation units covers the signal process-

ing requirements of a varied set of application needs. Each of the

two 32-bit input registers can be regarded as two 16-bit halves,

soeachALUcanaccomplishveryflexiblesingle16-bitarithmetic

operations. By viewing the registers as pairs of 16-bit operands,

dual 16-bit or single 32-bit operations can be accomplished in a

singlecycle. Quad16-bitoperationscanbeaccomplishedsimply,

by taking advantage of the second ALU. This accelerates the per

cycle throughput.

The on-chip peripherals can be easily augmented in many system

designs with little or no glue logic due to the inclusion of several

interfaces providing expansion on industry-standard buses.

These include a 32-bit, 33 MHz, V2.2 compliant PCI bus, SPI

serial expansion ports, and a device type USB port. These enable

the connection of a large variety of peripheral devices to tailor the

system design to specific applications with a minimum of design

complexity.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG0

DAG1

P2

P1

P0

SEQUENCE R

ALIGN

DECODE

R7

R6

LOOP BUFFER

R5

R4

16

8

CONTROL

UNIT

R3

R2

R1

R0

BARREL

SHIFTER

40

A0

A1

DATA ARITHMETIC UNIT

Figure 1. Processor Core

REV. A

–3–

ADSP-BF535

Thepowerful40-bitshifterhasextensivecapabilitiesforperform-

ing shifting, rotating, normalization, extraction, and for

depositing data.

address spaces, and I/O control registers, occupy separate

sections of this common address space. The memory portions of

this address space are arranged in a hierarchical structure to

provide a good cost/performance balance with very fast, low

latency memory as cache or SRAM very close to the processor;

and larger, lower cost, and lower performance memory systems

farther away from the processor. See Figure 2.

The data for the computational units is found in a multiported

register file of sixteen 16-bit entries or eight 32-bit entries.

A powerful program sequencer controls the flow of instruction

execution, including instruction alignment and decoding. The

sequencer supports conditional jumps and subroutine calls, as

well as zero-overhead looping. A loop buffer stores instructions

locally, eliminating instruction memory accesses for tightly

looped code.

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTE)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTE)

0xFFC0 0000

RESERVED

0xFFB0 1000

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from memory. The DAGs

share a register file containing four sets of 32-bit Index, Modify,

Length, and Base registers. Eight additional 32-bit registers

provide pointers for general indexing of variables and stack

locations.

SCRATCHPAD SRAM (4K BYTE)

0xFFB0 0000

RESERVED

0xFFA0 4000

INSTRUCTION SRAM (16K BYTE)

0xFFA0 0000

RESERVED

0xFF90 4000

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. Level 2 (L2) memories are other

memories, on-chip or off-chip, that may take multiple processor

cycles to access. At the L1 level, the instruction memory holds

instructions only. The two data memories hold data, and a

dedicatedscratchpaddatamemorystoresstackandlocalvariable

information. At the L2 level, there is a single unified memory

space, holding both instructions and data.

DATA BANK B SRAM (16K BYTE)

0xFF90 0000

RESERVED

0xFF80 4000

DATA BANK A SRAM (16K BYTE)

0xFF80 0000

RESERVED

0xF003 FFFF

L2 SRAM MEMORY (256K BYTE)

0xF000 0000

RESERVED

0xEF00 0000

PCI CONFIG SPACE PORT (4 BYTE)

0xEEFF FFFC

PCI CONFIG REGISTERS (64K BYTE)

0xEEFF FF00

In addition, the L1 instruction memory and L1 data memories

may be configured as either Static RAMs (SRAMs) or caches.

The Memory Management Unit (MMU) provides memory pro-

tection for individual tasks that may be operating on the core and

may protect system registers from unintended access.

RESERVED

0xEEFE FFFF

PCI IO SPACE (64K BYTE)

0xEEFE 0000

RESERVED

0xE7FF FFFF

PCI MEMORY SPACE (128M BYTE)

0xE000 0000

The architecture provides three modes of operation: user mode,

supervisormode,andEmulationmode. Usermodehasrestricted

access to certain system resources, thus providing a protected

software environment, while supervisor mode has unrestricted

access to the system and core resources.

RESERVED

0x2FFF FFFF

ASYNC MEMORY BANK 3 (64M BYTE)

0x2C00 0000

ASYNC MEMORY BANK 2 (64M BYTE)

0x2800 0000

ASYNC MEMORY BANK 1 (64M BYTE)

0x2400 0000

TheBlackfin processor instructionsethas been optimized sothat

16-bit op-codes represent the most frequently used instructions,

resulting in excellent compiled code density. Complex DSP

instructions are encoded into 32-bit op-codes, representing fully

featured multifunction instructions. Blackfin processors support

a limited multiple issue capability, where a 32-bit instruction can

be issued in parallel with two 16-bit instructions, allowing the

programmer to use many of the core resources in a single

instruction cycle.

ASYNC MEMORY BANK 0 (64M BYTE)

0x2000 0000

SDRAM MEMORY BANK 3

(16M BYTE - 128M BYTE)¹

0x1800 0000

SDRAM MEMORY BANK 2

(16M BYTE - 128M BYTE)¹

0x1000 0000

SDRAM MEMORY BANK 1

(16M BYTE - 128M BYTE)¹

0x0800 0000

SDRAM MEMORY BANK 0

(16M BYTE - 128M BYTE)¹

0x0000 0000

¹THE ADDRESSES SHOWN FOR THE SDRAM BANKS REFLECT A FULLY

POPULATED SDRAM ARRAY WITH 512M BYTES OF MEMORY. IF ANY BANK

CONTAINS LESS THAN 128M BYTES OF MEMORY, THAT BANK WOULD

EXTEND ONLY TO THE LENGTH OF THE REAL MEMORY SYSTEMS, AND THE

END ADDRESS WOULD BECOME THE START ADDRESS OF THE NEXT BANK.

THIS WOULD CONTINUE FOR ALL FOUR BANKS, WITH ANY REMAINING SPACE

BETWEEN THE END OF MEMORY BANK 3 AND THE BEGINNING OF ASYNC

MEMORY BANK 0, AT ADDRESS 0x2000 0000, TREATED AS RESERVED

ADDRESS SPACE.

The Blackfin processor assembly language uses an algebraic

syntax for ease of coding and readability. The architecture has

been optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

Memory Architecture

The ADSP-BF535 Blackfin processor views memory as a single

unified 4 Gbyte address space, using 32-bit addresses. All

resources, including internal memory, external memory, PCI

Figure 2. Internal/External Memory Map

–4–

REV. A

ADSP-BF535

The L1 memory system is the primary highest performance

memoryavailabletotheBlackfinprocessorcore.TheL2memory

provides additional capacity with slightly lower performance.

Lastly, the off-chip memory system, accessed through the

External Bus Interface Unit (EBIU), provides expansion with

SDRAM, flash memory, and SRAM, optionally accessing more

than 768M bytes of external physical memory.

64 Mbyte segment regardless of the size of the devices used so

that these banks will only be contiguous if fully populated with

64M bytes of memory.

PCI

The PCI bus defines three separate address spaces, which are

accessed through windows in the ADSP-BF535 Blackfin

processor memory space. These spaces are PCI memory, PCI

I/O, and PCI configuration.

The memory DMA controller provides high bandwidth data-

movement capability. It can perform block transfers of code or

data between the internal L1/L2 memories and the external

memory spaces (including PCI memory space).

In addition, the PCI interface can either be used as a bridge from

the processor core as the controlling CPU in the system, or as a

host port where another CPU in the system is the host and the

ADSP-BF535 is functioning as an intelligent I/O device on the

PCI bus.

Internal (On-Chip) Memory

The ADSP-BF535 Blackfin processor has four blocks of on-chip

memory providing high bandwidth access to the core.

When the ADSP-BF535 Blackfin processor acts as the system

controller, it views the PCI address spaces through its mapped

windows and can initialize all devices in the system and maintain

a map of the topology of the environment.

The first is the L1 instruction memory consisting of 16K bytes

of 4-Way set-associative cache memory. In addition, the memory

may be configured as an SRAM. This memory is accessed at full

processor speed.

The PCI memory region is a 4 Gbyte space that appears on the

PCI bus and can be used to map memory I/O devices on the bus.

The ADSP-BF535 Blackfin processor uses a 128 Mbyte window

in memory space to see a portion of the PCI memory space. A

base address register is provided to position this window

anywhere in the 4 Gbyte PCI memory space while its position

with respect to the processor addresses remains fixed.

The second on-chip memory block is the L1 data memory, con-

sisting of two banks of 16K bytes each. Each L1 data memory

bank can be configured as one Way of a 2-Way set-associative

cache or as an SRAM, and is accessed at full speed by the core.

The third memory block is a 4K byte scratch pad RAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM (it cannot be configured as cache memory and is

not accessible via DMA).

The PCI I/O region is also a 4 Gbyte space. However, most

systems and I/O devices only use a 64 Kbyte subset of this space

for I/Omappedaddresses. TheADSP-BF535 Blackfin processor

implements a 64K byte window into this space along with a base

address register which can be used to position it anywhere in the

PCI I/O address space, while the window remains at the same

address in the processor's address space.

The fourth on-chip memory system is the L2 SRAM memory

array which provides 256K bytes of high speed SRAM at the full

bandwidth of the core, and slightly longer latency than the L1

memory banks. The L2 memory is a unified instruction and data

memory and can hold any mixture of code and data required by

the system design.

PCI configuration space is a limited address space, which is used

for system enumeration and initialization. This address space is

a very low performance communication mode between the

processor and PCI devices. The ADSP-BF535 Blackfin

processor provides a one-value window to access a single data

value at any address in PCI configuration space. This window is

fixed and receives the address of the value, and the value if the

operation is a write. Otherwise, the device returns the value into

the same address on a read operation.

The Blackfin processor core has a dedicated low latency 64-bit

wide datapath port into the L2 SRAM memory.

External (Off-Chip) Memory

External memory is accessed via the External Bus Interface Unit

(EBIU). This interface provides a glueless connection to up to

four banks of synchronous DRAM (SDRAM) as well as up to

four banks of asynchronous memory devices including flash,

EPROM, ROM, SRAM, and memory-mapped I/O devices.

I/O Memory Space

The PC133 compliant SDRAM controller can be programmed

to interface to up to four banks of SDRAM, with each bank

containingbetween16M bytesand 128M bytesprovidingaccess

to up to 512M bytes of SDRAM. Each bank is independently

programmable and is contiguous with adjacent banks regardless

of the sizes of the different banks or their placement. This allows

flexible configuration and upgradability of system memory while

allowing the core to view all SDRAM as a single, contiguous,

physical address space.

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space.

On-chip I/O devices have their control registers mapped into

memory-mapped registers (MMRs) at addresses near the top of

the 4 Gbyte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for setup

and control of the on-chip peripherals outside of the core. The

core MMRs are accessible only by the core and only in supervisor

mode and appear as reserved space by on-chip peripherals, as

well as external devices accessing resources through the PCI bus.

The system MMRs are accessible by the core in supervisor mode

and can be mapped as either visible or reserved to other devices,

depending on the system protection model desired.

The asynchronous memory controller can also be programmed

to control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

REV. A

–5–

ADSP-BF535

Booting

support the peripherals of the ADSP-BF535 Blackfin processor.

Table 1 describes the inputs to the CEC, identifies their names

in the Event Vector Table (EVT), and lists their priorities.

The ADSP-BF535 Blackfin processor contains a small boot

kernel, which configures the appropriate peripheral for booting.

If the ADSP-BF535 Blackfin processor is configured to boot from

boot ROM memory space, the processor starts executing from

the on-chip boot ROM. For more information, see Booting

Modes on Page 14.

Table 1. Core Event Controller (CEC)

Priority

(0 is Highest) Event Class

EVT Entry

Event Handling

0

1

2

3

4

5

6

7

Emulation/Test

Reset

Non-Maskable

Exceptions

Global Enable

Hardware Error

Core Timer

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

EMU

RST

NMI

EVX

The event controller on the ADSP-BF535 Blackfin processor

handles all asynchronous and synchronous events to the proces-

sor. The ADSP-BF535 Blackfin processor provides event

handling that supports both nesting and prioritization. Nesting

allowsmultipleeventserviceroutinestobeactivesimultaneously.

Prioritization ensures that servicing of a higher-priority event

takes precedence over servicing of a lower priority event. The

controller provides support for five different types of events:

IVHW

IVTMR

IVG7

IVG8

IVG9

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

8

9

• Emulation—An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

10

11

12

13

14

15

• Reset—This event resets the processor.

• Non-MaskableInterrupt(NMI)—TheNMIeventcanbe

generated by the software watchdog timer or by the NMI

inputsignaltothe processor. TheNMIevent isfrequently

used as a power-down indicator to initiate an orderly

shutdown of the system.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

AlthoughtheADSP-BF535Blackfinprocessorprovidesadefault

mapping, the user can alter the mappings and priorities of

interrupt events by writing the appropriate values into the

Interrupt Assignment Registers (IAR). Table 2 describes the

inputs into the SIC and the default mappings into the CEC.

• Exceptions—Eventsthatoccursynchronouslytoprogram

flow, for example, the exception will be taken before the

instruction is allowed to complete. Conditions such as

data alignment violations, undefined instructions, and so

on, cause exceptions.

• Interrupts—Events that occur asynchronously to

program flow. They are caused by timers, peripherals,

input pins, explicit software instructions, and so on.

Table 2. System Interrupt Controller (SIC)

Each event has an associated register to hold the return address

and an associated return-from-event instruction. The state of the

processor is saved on the supervisor stack, when an event is

triggered.

Peripheral Interrupt

Event

Peripheral

Interrupt ID Mapping

Default

Real-Time Clock

Reserved

0

1

IVG7

The ADSP-BF535 Blackfin processor event controller consists

of two stages, the Core Event Controller (CEC) and the System

Interrupt Controller (SIC). The Core Event Controller works

with the System Interrupt Controller to prioritize and control all

system events. Conceptually, interrupts from the peripherals

enter into the SIC, and are then routed directly into the general-

purpose interrupts of the CEC.

USB

2

IVG7

IVG8

IVG9

PCI Interrupt

SPORT 0 Rx DMA

SPORT 0 Tx DMA

SPORT 1 Rx DMA

SPORT 1 Tx DMA

SPI 0 DMA

3

4

5

6

7

8

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

SPI 1 DMA

UART 0 Rx

UART 0 Tx

UART 1 Rx

UART 1 Tx

Timer 0

Timer 1

Timer 2

9

IVG9

10

11

12

13

14

15

16

17

18

IVG10

IVG11

IVG12

GPIO Interrupt A

GPIO Interrupt B

–6–

REV. A

ADSP-BF535

Table 2. System Interrupt Controller (SIC) (continued)

event source triggered the interrupt. A set bit indicates

the peripheral is asserting the interrupt, a cleared bit

indicates the peripheral is not asserting the event.

Peripheral Interrupt

Event

Peripheral

Interrupt ID Mapping

Default

• SIC Interrupt Wakeup Enable Register (SIC_IWR)—By

enabling the corresponding bit in this register, each

peripheral can be configured to wake up the processor,

should the processor be in a powered down mode when

theeventisgenerated.(SeeDynamicPowerManagement

on Page 11.)

Memory DMA

Software Watchdog Timer

Reserved

Software Interrupt 1

Software Interrupt 2

19

20

26–21

27

28

IVG13

IVG14

IVG15

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur

simultaneously, before or during interrupt processing for an

interrupt event already detected on this interrupt input. The

IPEND register contents are monitored by the SIC as the

interrupt acknowledgement.

Event Control

The ADSP-BF535 Blackfin processor provides the user with a

very flexible mechanism to control the processing of events. In

the CEC, three registers are used to coordinate and control

events. Each of the registers is 16 bits wide, and each bit repre-

sents a particular event class:

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the processor

pipeline.Atthispoint,theCECwillrecognizeandqueuethenext

rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clockcycles;however,thelatencycanbemuchhigher,depending

on the activity within and the mode of the processor.

• CEC Interrupt Latch Register (ILAT)—The ILAT

register indicates when events have been latched. The

appropriate bit is set when the processor has latched the

event and cleared when the event has been accepted into

the system. This register is updated automatically by the

controller but may be read while in supervisor mode.

• CEC Interrupt Mask Register (IMASK)—The IMASK

registercontrolsthemaskingandunmaskingofindividual

events. When a bit is set in the IMASK register, that event

is unmasked and will be processed by the CEC when

asserted. A cleared bit in the IMASK register masks the

event thereby preventing the processor from servicing the

event even though the event may be latched in the ILAT

register. Thisregistermaybereadfromorwrittentowhile

in supervisor mode. (Note that general-purpose inter-

rupts can be globally enabled and disabled with the STI

and CLI instructions, respectively.)

DMA Controllers

TheADSP-BF535Blackfinprocessorhasmultiple, independent

DMA controllers that support automated data transfers with

minimaloverheadfortheBlackfinprocessorcore.DMAtransfers

can occur between the ADSP-BF535 Blackfin processor's

internal memories and any of its DMA-capable peripherals.

Additionally, DMA transfers can be accomplished between any

of the DMA-capable peripherals and external devices connected

to the external memory interfaces, including the SDRAM con-

troller, the asynchronous memory controller and the PCI bus

interface. DMA-capable peripherals include the SPORTs, SPI

ports, UARTs, and USB port. Each individual DMA-capable

peripheralhas atleastone dedicatedDMAchannel. DMA to and

from PCI is accomplished by the memory DMA channel.

• CEC Interrupt Pending Register (IPEND)—The

IPEND register keeps track of all nested events. A set bit

in the IPEND register indicates the event is currently

active or nested at some level. This register is updated

automatically by the controller but may be read while in

supervisor mode.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 2.

To describe each DMA sequence, the DMA controller uses a set

of parameters called a descriptor block. When successive DMA

sequences are needed, these descriptor blocks can be linked or

chained together, so the completion of one DMA sequence auto-

initiates and starts the next sequence. The descriptor blocks

include full 32-bit addresses for the base pointers for source and

destination, enabling access to the entire ADSP-BF535 Blackfin

processor address space.

• SIC Interrupt Mask Register (SIC_IMASK)—This

register controls the masking and unmasking of each

peripheralinterruptevent. Whenabitissetintheregister,

that peripheral event is unmasked and will be processed

by the system when asserted. A cleared bit in the register

masks the peripheral event thereby preventing the

processor from servicing the event.

In addition to the dedicated peripheral DMA channels, there is

a separate memory DMA channel provided for transfers between

the various memories of the ADSP-BF535 Blackfin processor

system. This enables transfers of blocks of data between any of

the memories, including on-chip Level 2 memory, external

SDRAM, ROM, SRAM, and flash memory, and PCI address

spaces with little processor intervention.

• SIC Interrupt Status Register (SIC_ISTAT)—As

multiple peripherals can be mapped to a single event, this

registerallowsthesoftwaretodeterminewhichperipheral

REV. A

–7–

ADSP-BF535

External Memory Control

processor core and on-chip peripherals and an external PCI bus.

The PCI interface of the ADSP-BF535 Blackfin processor

supports two PCI functions:

The External Bus Interface Unit (EBIU) on the ADSP-BF535

Blackfin processor provides a high performance, glueless

interface to a wide variety of industry-standard memory devices.

The controller is made up of two sections: the first is an SDRAM

controller for connection of industry-standard synchronous

DRAM devices and DIMMs (Dual Inline Memory Module),

while thesecond is an asynchronousmemory controller intended

to interface to a variety of memory devices.

• AhosttoPCIbridgefunction, inwhichtheADSP-BF535

Blackfin processor resources (the processor core, internal

and external memory, and the memory DMA controller)

provide the necessary hardware components to emulate

a host computer PCI interface, from the perspective of a

PCI target device.

• APCItargetfunction,inwhichanADSP-BF535Blackfin

processor based intelligent peripheral can be designed to

easily interface to a Revision 2.2 compliant PCI bus.

PC133 SDRAM Controller

The SDRAM controller provides an interface to up to four

separate banks of industry-standard SDRAM devices or

DIMMs, at speeds up to f_SCLK. Fully compliant with the PC133

SDRAM standard, each bank can be configured to contain

between 16M bytes and 128M bytes of memory.

PCI Host Function

As the PCI host, the ADSP-BF535 Blackfin processor provides

the necessary PCI host (platform) functions required to support

and control a variety of off-the-shelf PCI I/O devices (for

example,Ethernetcontrollers,busbridges,andsoon)inasystem

in which the ADSP-BF535 Blackfin processor is the host.

The controller maintains all of the banks as a contiguous address

space so that the processor sees this as a single address space,

even if different size devices are used in the different banks. This

enables a system design where theconfiguration can be upgraded

after delivery with either similar or different memories.

Note that the Blackfin processor architecture defines only

memory space (no I/O or configuration address spaces). The

three address spaces of PCI space (memory, I/O, and configura-

tion space) are mapped into the flat 32-bit memory space of the

ADSP-BF535 Blackfin processor. Because the PCI memory

space is as large as the ADSP-BF535 Blackfin processor memory

address space, a windowed approach is employed, with separate

windows in the ADSP-BF535 Blackfin processor address space

used for accessing the three PCI address spaces. Base address

registers are provided so that these windows can be positioned to

view any range in the PCI address spaces while the windows

remainfixedinpositionintheADSP-BF535Blackfinprocessor’s

address range.

Asetofprogrammabletimingparametersisavailabletoconfigure

the SDRAM banks to support slower memory devices. The

memory banks can be configured as either 32 bits wide for

maximum performance and bandwidth or 16 bits wide for

minimum device count and lower system cost.

All four banks share common SDRAM control signals and have

their own bank select lines providing a completely glueless

interface for most system configurations.

The SDRAM controller address, data, clock, and command pins

can drive loads up to 50 pF. For larger memory systems, the

SDRAM controller externalbuffer timingshould be selected and

external buffering should be provided so that the load on the

SDRAM controller pins does not exceed 50 pF.

For devices on the PCI bus viewing the ADSP-BF535 Blackfin

processor’s resources, several mapping registers are provided to

enable resources to be viewed in the PCI address space. The

ADSP-BF535 Blackfin processor’s external memory space,

internal L2, and some I/O MMRs can be selectively enabled as

memory spaces that devices on the PCI bus can use as targets for

PCI memory transactions.

Asynchronous Controller

The asynchronous memory controller provides a configurable

interface for up to four separate banks of memory or I/O devices.

Each bank can be independently programmed with different

timing parameters, enabling connection to a wide variety of

memory devices including SRAM, ROM, and flash EPROM, as

well as I/O devices that interface with standard memory control

lines. Each bank occupies a 64 Mbyte window in the processor’s

address space but, if not fully populated, these windows are not

made contiguous by the memory controller logic. The banks can

also be configured as 16-bit wide or 32-bit wide buses for ease of

interfacing to a range of memories and I/O devices tailored either

to high performance or to low cost and power.

PCI Target Function

As a PCI target device, the PCI host processor can configure the

ADSP-BF535Blackfinprocessorsubsystemduringenumeration

of the PCI bus system. Once configured, the ADSP-BF535

Blackfin processor subsystem acts as an intelligent I/O device.

When configured as a target device, the PCI controller uses the

memory DMA controller to perform DMA transfers as required

by the PCI host.

USB Device

PCI Interface

The ADSP-BF535 Blackfin processor provides a USB 1.1

compliant device type interface to support direct connection to

a host system. The USB core interface provides a flexible pro-

grammable environment with up to eight endpoints. Each

endpointcansupportalloftheUSB data types including control,

bulk, interrupt, and isochronous. Each endpoint provides a

memory-mapped buffer for transferring data to the application.

The ADSP-BF535 Blackfin processor USB port has a dedicated

The ADSP-BF535 Blackfin processor provides a glueless logical

and electrical, 33 MHz, 3.3 V, 32-bit PCI (Peripheral

Component Interconnect), Revision 2.2 compliant interface.

The PCI interface is designed for a 3 V signalling environment.

The PCI interface provides a bus bridge function between the

–8–

REV. A

ADSP-BF535

DMA controller and interrupt input to minimize processor

polling overhead and to enable asynchronous requests for CPU

attention only when transfer management is required.

the processor toa known state, via generationofa hardwarereset,

non-maskable interrupt (NMI), or general-purpose interrupt, if

thetimerexpiresbeforebeingresetbysoftware. Theprogrammer

initializes the count value of the timer, enables the appropriate

interrupt, then enables the timer. Thereafter, the software must

reload the counter before it counts to zero from the programmed

value. This protects the system from remaining in an unknown

state where software, which would normally reset the timer, has

stopped running because of external noise conditions or a

software error.

The USB device requires an external 48 MHz oscillator. The

value of SCLK must always exceed 48 MHz for proper USB

operation.

Real-Time Clock

The ADSP-BF535 Blackfin processor Real-Time Clock (RTC)

provides a robust set of digital watch features, including current

time,stopwatch,andalarm.TheRTCisclockedbya32.768 kHz

crystal external to the ADSP-BF535 Blackfin processor. The

RTC peripheral has dedicated power supply pins, so that it can

remain powered up and clocked, even when the rest of the

processor is in a low power state. The RTC provides several

programmableinterruptoptions,includinginterruptpersecond,

minute, ordayclockticks, interruptonprogrammablestopwatch

countdown, or interrupt at a programmed alarm time.

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

timer control register, which is set only upon a watchdog

generated reset.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

Timers

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 6-bit second counter, a 6-bit minute counter,

a 5-bit hours counter, and an 8-bit day counter.

There are four programmable timer units in the ADSP-BF535

Blackfin processor. Three general-purpose timers have an

external pin that can be configured either as a Pulse-Width

Modulator (PWM) or timer output, as an input to clock the

timer, or for measuring pulse widths of external events. Each of

the three general-purpose timer units can be independently pro-

grammed as a PWM, internally or externally clocked timer, or

pulse width counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: one is for a time of

day, the second is for a day and time of that day.

The general-purpose timer units can be used in conjunction with

the UARTs to measure the width of the pulses in the data stream

to provide an autobaud detect function for a serial channel.

The stopwatch function counts down from a programmed value,

with one minute resolution. When the stopwatch is enabled and

the counter underflows, an interrupt is generated.

The general-purpose timers can generate interrupts to the

processor core providing periodic events for synchronization,

either to the processor clock or to a count of external signals.

Like the other peripherals, the RTC can wake up the ADSP-

BF535 Blackfin processor from a low power state upon

generation of any interrupt.

In addition to the three general-purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internalprocessorclock(CCLK)and is typicallyusedasasystem

tick clock for the generation of operating system periodic

interrupts.

Connect RTC pins XTALI and XTALO with external compo-

nents, as shown in Figure 3.

XTAL1

XTAL0

Serial Ports (Sports)

X1

TheADSP-BF535Blackfinprocessorincorporatestwocomplete

synchronous serial ports (SPORT0 and SPORT1) for serial and

multiprocessor communications. The SPORTs support these

features:

C1

C2

• Bidirectional operation—Each SPORT has independent

SUGGESTED COMPONENTS:

transmit and receive pins.

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12pF LOAD (SURFACE-MOUNT PACKAGE)

• Buffered (8-deep) transmit and receive ports—Each port

has a data register for transferring data-words to and from

otherprocessorcomponentsandshiftregistersforshifting

data in and out of the data registers.

C1 = 22pF

C2 = 22pF

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.

• Clocking—Each transmit and receive port can either use

an external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131070) Hz to (f_SCLK/2) Hz.

Figure 3. External Components for RTC

Watchdog Timer

• Word length—Each SPORT supports serial data-words

from 3 to 16 bits in length transferred in a format of most

significant bit first or least significant bit first.

The ADSP-BF535 Blackfin processor includes a 32-bit timer,

which can be used to implement a software watchdog function.

A software watchdog can improve system availability by forcing

REV. A

–9–

ADSP-BF535

• Framing—Each transmit and receive port can run with or

without frame sync signals for each data-word. Frame

sync signals can be generated internally or externally,

active high or low, with either of two pulse widths and

early or late frame sync.

During transfers, the SPI ports simultaneously transmit and

receive by serially shifting data in and out on two serial data lines.

The serial clock line synchronizes the shifting and sampling of

data on the two serial data lines.

In master mode, the processor performs the following sequence

to set up and initiate SPI transfers:

• Companding in hardware—Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the

transmit and/or receive channel of the SPORT without

additional latencies.

1. Enables and configures the SPI port’s operation (data

size and transfer format).

2. Selects the target SPI slave with an SPIxSELy output pin

(reconfigured programmable flag pin).

• DMA operations with single-cycle overhead—Each

SPORT can automatically receive and transmit multiple

buffers of memory data. The Blackfin processor can link

or chain sequences of DMA transfers between a SPORT

and memory. The chained DMA can be dynamically

allocated and updated through the descriptor blocks that

set up the chain.

3. Defines one or more TCBs in the processor’s memory

space (optional in DMA mode only).

4. Enables the SPI DMA engine and specifies transfer

direction (optional in DMA mode only).

5. Reads or writes the SPI port receive or transmit data

buffer (in non-DMA mode only).

• Interrupts—Each transmit and receive port generates an

interrupt upon completing the transfer of a data-word or

after transferring an entire data buffer or buffers through

the DMA.

The SCKx line generates the programmed clock pulses

for simultaneously shifting data out on MOSIx and

shifting data in on MISOx. In the DMA mode only,

transfers continue until the SPI DMA word count transi-

tions from 1 to 0.

• Multichannel capability—Each SPORT supports 128

channels and is compatible with the H.100, H.110,

MVIP-90, and HMVIP standards.

In slave mode, the processor performs the following sequence to

set up the SPI port to receive data from a master transmitter:

1. Enables and configures the SPI slave port to match the

operation parameters set up on the master (data size and

transfer format) SPI transmitter.

Serial Peripheral Interface (SPI) Ports

The ADSP-BF535 Blackfin processor has two SPI compatible

ports that enable the processor to communicate with multiple

SPI compatible devices.

2. Defines and generates a receive TCB in the processor’s

memory space to interrupt at the end of the data transfer

(optional in DMA mode only).

The SPI interface uses three pins for transferring data: two data

pins (Master Output-Slave Input, MOSIx, and Master Input-

Slave Output, MISOx) and a clock pin (Serial Clock, SCKx).

Two SPI chip select input pins (SPISSx) let other SPI devices

select the processor, and fourteen SPI chip select output pins

(SPIxSEL7–1)lettheprocessorselectotherSPIdevices.TheSPI

select pins are reconfigured programmable flag pins. Using these

pins, the SPI ports provide a full duplex, synchronous serial inter-

face, which supports both master and slave modes and

multimaster environments.

3. Enables the SPI DMA engine for a receive access

(optional in DMA mode only).

4. Starts receiving data on the appropriate SPI SCKx edges

after receiving an SPI chip select on an SPISSx input pin

(reconfigured programmable flag pin) from a master.

In DMA mode only, reception continues until the SPI DMA

word count transitions from 1 to 0. The processor can continue,

by queuing up the next command TCB.

EachSPIport’sbaudrateandclockphase/polaritiesareprogram-

mable (see Figure 4), and each has an integrated DMA

controller, configurable to support transmit or receive data

streams. The SPI’s DMA controller can only service unidirec-

tional accesses at any given time.

A slave mode transmit operation is similar, except the processor

specifies the data buffer in memory from which to transmit data,

generates and relinquishes control of the transmit TCB, and

begins filling the SPI port’s data buffer. If the SPI controller is

not ready to transmit, it can transmit a “zero” word.

f_SCLK

SPI Clock Rate = ------------------------------------

2 × SPIBAUD

UART Port

The ADSP-BF535 Blackfin processor provides two full-duplex

Universal Asynchronous Receiver/Transmitter (UART) ports

(UART0 and UART1) fully compatible with PC-standard

UARTs. The UART ports provide a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA-sup-

ported, asynchronous transfers of serial data. Each UART port

Figure 4. SPI Clock Rate Calculation

–10–

REV. A

ADSP-BF535

includes support for 5 to 8 data bits; 1 or 2 stop bits; and none,

even, or odd parity. The UART ports support two modes of

operation.

• Flag Interrupt Mask Registers—The two flag interrupt

mask registers allow each individual PFx pin to function

as an interrupt to the processor. Similar to the two flag

control registers that are used to set and clear individual

flag values, one flag interrupt mask register sets bits to

enable interrupt function, and the other flag interrupt

maskregisterclearsbitstodisableinterruptfunction. PFx

pins defined as inputs can be configured to generate

hardware interrupts, while output PFx pins can be con-

figured to generate software interrupts.

• PIO(ProgrammedI/O)—Theprocessorsendsorreceives

data by writing or reading I/O-mapped UATX or UARX

registers, respectively. The data is double-buffered on

both transmit and receive.

• DMA (Direct Memory Access)—The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. The

DMA channels have lower priority than most DMA

channels because of their relatively low service rates.

• Flag Interrupt Sensitivity Registers—The two flag

interrupt sensitivity registers specify whether individual

PFx pins are level- or edge-sensitive and specify (if edge-

sensitive) whether just the rising edge or both the rising

and falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects

which edges are significant for edge-sensitivity.

Each UART port’s baud rate (see Figure 5), serial data format,

error code generation and status, and interrupts are

programmable:

Dynamic Power Management

• Bit rates ranging from (f_SCLK/1048576) to (f_SCLK/16) bits

The ADSP-BF535 Blackfin processor provides four operating

modes, each with a different performance/power dissipation

profile. In addition, dynamic power management provides the

controlfunctions, with the appropriateexternalpower regulation

capability to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

of the ADSP-BF535 Blackfin processor peripherals also reduces

power dissipation. See Table 3 for a summary of the power

settings for each mode.

per second

• Data formats from 7 to 12 bits per frame

• Both transmit and receive operations can be configured

to generate maskable interrupts to the processor.

f_SCLK

UART Clock Rate = -----------------

16 × D

Figure 5. UART Clock Rate Calculation

Autobaud detection is supported, in conjunction with the

general-purpose timer functions.

Full On Operating Mode

– Maximum Performance

In the full on mode, the PLL is enabled, and is not bypassed,

providing the maximum operational frequency. This is the

normal execution state in which maximum performance can be

achieved. The processor core and all enabled peripherals run at

full speed.

The capabilities of UART0 are further extended with support for

the Infrared Data Association (IrDA Serial Infrared Physical

Layer Link Specification (SIR) protocol.

Programmable Flags (PFX)

The ADSP-BF535 Blackfin processor has 16 bidirectional,

general-purposeI/Oprogrammableflag(PF15–0)pins.Thepro-

grammable flag pins have special functions for clock multiplier

selection, SROM boot mode, and SPI port operation. For more

information, see Serial Peripheral Interface (SPI) Ports on

Page 10 and Clock Signals on Page 13. Each programmable flag

canbeindividuallycontrolledbymanipulationoftheflagcontrol,

status, and interrupt registers.

Active Operating Mode

– Moderate Power Savings

In the active mode, the PLL is enabled, but bypassed. The input

clock (CLKIN) is used to generate the clocks for the processor

core (CCLK) and peripherals (SCLK). When the PLL is

bypassed, CCLK runs at one-half the CLKIN frequency. Signif-

icant power savings can be achieved with the processor running

at one-half the CLKIN frequency. In this mode, the PLL multi-

plication ratio can be changed by setting the appropriate values

in the SSEL fields of the PLL control register (PLL_CTL).

• Flag Direction Control Register—Specifies the direction

of each individual PFx pin as input or output.

• Flag Control and Status Registers—Rather than forcing

the software to use a read-modify-write process to control

the setting of individual flags, the ADSP-BF535 Blackfin

processor employs a “write one to set” and “write one to

clear” mechanism that allows any combination of individ-

ualflagstobesetorclearedinasingleinstruction, without

affecting the level of any other flags. Two control registers

are provided, one register is written to in order to set flag

values while another register is written to in order to clear

flagvalues. Readingtheflagstatusregisterallowssoftware

to interrogate the sense of the flags.

When in the active mode, system DMA access to appropriately

configured L1 memory is supported.

Sleep Operating Mode

– High Power Savings

The sleep mode reduces power dissipation by disabling the clock

to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Any inter-

rupt, typically via some external event or RTC activity, will wake

up the processor. When in sleep mode, assertion of any interrupt

will cause the processor to sense the value of the bypass bit

REV. A

–11–

ADSP-BF535

(BYPASS) in the PLL Control register (PLL_CTL). If bypass is

disabled, the processor transitions to the full on mode. If bypass

is enabled, the processor transitions to the Active mode.

The DEEPSLEEP output is asserted in this mode.

Mode Transitions

The available mode transitions diagrammed in Figure 6 are

accomplished either by the interrupt events described in the

following sections or by programming the PLLCTL register with

the appropriate values and then executing the PLL programming

sequence.

When in Sleep mode, system DMA access to L1 memory is not

supported.

Deep Sleep Operating Mode

– Maximum Power Savings

The deep sleep mode maximizes power savings by disabling the

clocks to the processor core (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals, such as the

RTC, may still be running but will not be able to access internal

resources or external memory. This powered down mode can

only be exited by assertion of the reset interrupt (RESET) or by

an asynchronous interrupt generated by the RTC. When in deep

sleep mode, assertion of RESET causes the processor to sense

the value of the BYPASS pin. If bypass is disabled, the processor

will transition to full on mode. If bypass is enabled, the processor

will transition to active mode. When in deep sleep mode,

assertion of the RTC asynchronous interrupt causes the

processor to transition to the full on mode, regardless of the value

of the BYPASS pin.

This instruction sequence takes the processor to a known idle

state with the interrupts disabled. Note that all DMA activity

should be disabled during mode transitions.

Table 3. Operating Mode Power Settings

PLL

Core Clock System Clock

Mode

PLL

Bypassed (CCLK)

(SCLK)

Full On

Active

Sleep

Enabled No

Enabled Yes

Enabled Yes or No Disabled

Disabled Disabled

Enabled

Disabled

Deep +

SLEEP

WAKEUP AND

STOPCK = 1

AND PDWN = 0

WAKEUP AND

BYPASS = 0

STOPCK = 1

AND PDWN = 0

BYPASS = 1

BYPASS = 0

AND PLL_OFF = 0

AND STOPCK = 0

AND PDWN = 0

ACTIVE

FULL-ON

BYPASS = 1

AND STOPCK = 0

AND PDWN = 0

RTC_WAKEUP

PDWN = 1

DEEP

SLEEP

HARDWARE

RESET

MSEL = NEW

AND PLL_OFF = 0

AND BYPASS = 1

MSEL = NEW

AND PLL_OFF = 0

AND BYPASS = 0

RESET

Figure 6. Mode Transitions

Power Savings

Table 4. Power Domains

Power Domain

As shown in Table 4, the ADSP-BF535 Blackfin processor

supportsfivedifferentpowerdomains. Theuseofmultiplepower

domains maximizes flexibility, while maintaining compliance

withindustrystandardsandconventions.Byisolatingtheinternal

logic of the ADSP-BF535 Blackfin processor into its own power

domain, separate from the PLL, RTC, PCI, and other I/O, the

processor can take advantage of dynamic power management,

without affecting the PLL, RTC, or other I/O devices.

V

_DDRange

All internal logic, except PLL and RTC

Analog PLL internal logic

RTC internal logic and crystal I/O

PCI I/O

V_DDINT

V_DDPLL

V_DDRTC

V_DDPCIEXT

V_DDEXT

All other I/O

–12–

REV. A

ADSP-BF535

Clock Signals

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in power dissipation, while reducing

the voltage by 25% reduces power dissipation by more than 40%.

Further, these power savings are additive, in that if the clock

frequency and power are both reduced, the power savings are

dramatic.

The ADSP-BF535 Blackfin processor can be clocked by a sine

wave input or a buffered shaped clock derived from an external

clock oscillator.

If a buffered, shaped clock is used, this external clock connects

to the processor CLKIN pin. The CLKIN input cannot be

halted, changed, or operated below the specified frequency

during normal operation. This clock signal should be a 3.3 V

LVTTL compatible signal. The processor provides a user-pro-

Dynamic Power Management allows both the processor’s input

voltage (V_DDINT) and clock frequency (f_CCLK) to be dynamically

and independently controlled.

grammable 1

؋

to 31

؋

multiplication of the input clock to

support external-to-internal clock ratios. The MSEL6–0,

BYPASS, and DF pins decide the PLL multiplication factor at

reset. At run time, the multiplication factor can be controlled in

software. The combination of pull-up and pull-down resistors in

Figure 7 sets up a core clock ratio of 6:1, which, for example,

produces a 150 MHz core clock from the 25 MHz input. For

other clock multiplier settings, see the ADSP-BF535 Blackfin

As previously explained, the savings in power dissipation can be

modeled by the following equation:

2

f_CCLKRED

-------------------------

f_CCLKNOM

V_DDINTRED

------------------------------

V_DDINTNOM

Power Dissipation Factor =

×

where:

Processor Hardware Reference

.

f_CCLKNOMis the nominal core clock frequency (300 MHz)

f_CCLKREDis the reduced core clock frequency

V_DDINTNOMis the nominal internal supply voltage (1.5 V)

V_DDINTREDis the reduced internal supply voltage

CLKIN

CLKOUT

MSEL0 (PF0)

As an example of how significant the power savings of Dynamic

Power Management are when both frequency and voltage are

reduced, consider an example where the frequency is reduced

fromitsnominalvalueto50 MHzandthevoltageisreducedfrom

its nominal value to 1.2 V. At this reduced frequency and voltage,

the processor dissipates about 10% of the power dissipated at

nominal frequency and voltage.

ADSP-BF535

BLACKFIN PROCESSOR

V_DD

MSEL1 (PF1)

V_DD

MSEL2 (PF2)

MSEL3 (PF3)

THE PULL-UP/PULL-DOWN

RESISTORS ON THE MSEL,

DF, AND BYPASS PINS SELECT

THE CORE CLOCK RATIO.

Peripheral Power Control

The ADSP-BF535 Blackfin processor provides additional power

controlcapabilitybyallowingdynamicschedulingofclockinputs

to each of the peripherals. Clocking to each of the peripherals

listed below can be enabled or disabled by appropriately setting

the peripheral’s control bit in the peripheral clock enable register

(PLL_IOCK). ThePeripheralClockEnableRegisterallowsindi-

vidual control for each of these peripherals:

HERE, THE SELECTION (6:1)

AND 25MHz INPUT CLOCK

PRODUCE A 150MHz CORE CLOCK.

MSEL4 (PF4)

MSEL5 (PF5)

MSEL6 (PF6)

DF (PF7)

• PCI

• EBIU controller

• Programmable flags

• MemDMA controller

• SPORT 0

BYPASS

RESET

RESET SOURCE

• SPORT 1

• SPI 0

• SPI 1

Figure 7. Clock Ratio Example

• UART 0

• UART 1

All on-chip peripherals operate at the rate set by the system clock

(SCLK). The systemclockfrequency isprogrammableby means

of the SSEL pins. At run time the system clock frequency can be

controlled in software by writing to the SSEL fields in the PLL

control register (PLL_CTL). The values programmed into the

• Timer 0, Timer 1, Timer 2

• USB CLK

REV. A

–13–

ADSP-BF535

SSEL fields define a divide ratio between the core clock (CCLK)

and the system clock. Table 5 illustrates the system clock ratios.

The system clock is supplied to the CLKOUT_SCLK0 pin.

• Boot from SPI serial EEPROM (8-bit addressable)—

The SPI0 uses PF10 output pin to select a single SPI

EPROM device, submits a read command at address

0x00, and begins clocking data into the beginning of L2

memory.An8-bitaddressableSPIcompatibleEPROM

must be used.

Table 5. System Clock Ratios

Signal

Name

Divider

Ratio

Example Frequency

Ratios (MHz)

• Boot from SPI serial EEPROM (16-bit addressable)—

The SPI0 uses PF10 output pin to select a single SPI

EPROM device, submits a read command at address

0x0000, and begins clocking data into the beginning of

L2 memory. A 16-bit addressable SPI compatible

EPROM must be used.

SSEL1– 0 CCLK/SCLK CCLK

SCLK

00

01

10

11

2:1

2.5:1

3:1

266

275

300

133

110

100

75

4:1

For each of the boot modes described above, a four-byte value is

first read from the memory device. This value is used to specify

a subsequent number of bytes to be read into the beginning of

L2 memory space. Once each of the loads is complete, the

processor jumps to the beginning of L2 space and begins

execution.

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock

frequency to its maximum of f_SCLK. The reset value of the

SSEL1–0 isdeterminedbysamplingtheSSEL1andSSEL0pins

during reset. The SSEL value can be changed dynamically by

writing the appropriate values to the PLL control register

(PLL_CTL), as described in the ADSP-BF535 Blackfin Processor

In addition, the reset configuration register can be set by appli-

cationcodetobypassthenormalbootsequenceduringasoftware

reset. For this case, the processor jumps directly to the beginning

of L2 memory space.

Hardware Reference

.

Booting Modes

To augment the boot modes, a secondary software loader is

provided that adds additional booting mechanisms. This

secondaryloaderprovidesthecapabilitytobootfromPCI, 16-bit

flash memory, fast flash, variable baud rate, and so on.

The ADSP-BF535 has three mechanisms (listed in Table 6) for

automatically loading internal L2 memory after a reset. A fourth

mode is provided to execute from external memory, bypassing

the boot sequence.

Instruction Set Description

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and read-

ability. The instructions have been specifically tuned to provide

a flexible, densely encoded instruction set that compiles to a very

small final memory size. The instruction set also provides fully

featured multifunction instructions that allow the programmer

tousemanyoftheprocessorcoreresourcesinasingleinstruction.

Coupled with many features more often seen on microcontrol-

lers, this instruction set is very efficient when compiling C and

C++ source code. In addition, the architecture supports both a

user (algorithm/application code) and a supervisor (O/S kernel,

device drivers, debuggers, ISRs) mode of operations, allowing

multiple levels of access to core processor resources.

Table 6. Booting Modes

BMODE2–0 Description

000

Execute from 16-bit external memory

(Bypass Boot ROM)

001

010

Boot from 8-bit flash

Boot from SPI0 serial ROM

(8-bit address range)

011

Boot from SPI0 serial ROM

(16-bit address range)

Reserved

100 –111

The BMODE pins of the reset configuration register, sampled

during power-on resets and software initiated resets, implement

these modes:

The assembly language, which takes advantage of the processor’s

unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized

for both 8-bit and 16-bit operations.

• Execute from 16-bit external memory—Execution

starts from address 0x2000000 with 16-bit packing.

The boot ROM is bypassed in this mode.

• Asuperpipelinedmultiissueload/storemodifiedHarvard

architecture, which supports two 16-bit MAC or four 8-

bit ALU + two load/store + two pointer updates per cycle.

• Bootfrom8-bitexternalflashmemory—The8-bitflash

boot routine located in boot ROM memory space is set

up using asynchronous Memory Bank 0. All configura-

tion settings are set for the slowest device possible

(3-cycle hold time; 15-cycle R/W access times; 4-cycle

setup).

• All registers, I/O, and memory are mapped into a unified

4 Gbyte memory space providing a simplified program-

ming model.

–14–

REV. A

ADSP-BF535

• Microcontroller features, such as arbitrary bit and bit-

field manipulation, insertion, and extraction; integer

operations on 8-, 16-, and 32-bit data-types; and separate

user and kernel stack pointers.

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all development tools,

including color syntax highlighting in the VisualDSP++ editor.

These capabilities permit programmers to:

• Code density enhancements, which include intermixing

of 16- and 32-bit instructions (no mode switching, no

code segregation). Frequently used instructions are

encoded as 16-bits.

• Control how the development tools process inputs and

Development Tools

generate outputs

The ADSP-BF535 Blackfin processor is supported with a

complete set of software and hardware development tools,

including Analog Devices emulators and the VisualDSP++™

development environment. The same emulator hardware that

supports other Analog Devices JTAG processors, also fully

emulates the ADSP-BF535 Blackfin processor.

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resourcemanagementtailoredspecificallytoaddressthememory

and timing constraints of embedded, real-time programming.

These capabilities enable engineers to develop code more effec-

tively,eliminatingtheneedtostartfromtheverybeginning,when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

anddevice flags. TheVDKalsosupportspriority-based, preemp-

tive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ run-time library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient transla-

tion of C/C++ code to Blackfin processor assembly. The Blackfin

processor has architectural features that improve the efficiency of

compiled C/C++ code.

Because the VDK is a library, a developer can decide whether to

use it or not. TheVDKis integrated intothe VisualDSP++ devel-

opment environment, but can also be used via standard

TheVisualDSP++debuggerhasanumberofimportantfeatures.

Data visualization is enhanced by a plotting package that offers

a significant level of flexibility. This graphical representation of

user data enables the programmer to quickly determine the per-

formance of an algorithm. As algorithms grow in complexity, this

capability can have increasing significance on the designer’s

development schedule, increasing productivity. Statistical

profiling enables the programmer to nonintrusively poll the

processor as it is running the program. This feature, unique to

VisualDSP++, enables the software developer to passively gather

important code execution metrics without interrupting the real-

timecharacteristicsoftheprogram.Essentially,thedevelopercan

identify bottlenecks in software quickly and efficiently. By using

the profiler, the programmer can focus on those areas in the

program that impact performance and take corrective action.

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gener-

ation of various VDK based objects, and visualizing the system

state, when debugging an application that uses the VDK.

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of substan-

tial functionality) to quickly and reliably assemble software

applications. Download components from the Web and drop

them into the application. Publish component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of

codeanddataontheembeddedsystem. Viewmemoryutilization

in a color-coded graphical form, easily move code and data to

different areas of the processor or external memory with the drag

of the mouse, examine run-time stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the

graphical and textual environments.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved

source and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory, and

stacks

Analog Devices emulators use the IEEE 1149.1 JTAG test access

port of the ADSP-BF535 Blackfin processor to monitor and

control the target board processor during emulation. The

emulator provides full speed emulation, allowing inspection and

modification of memory, registers, and processor stacks. Nonin-

trusively in-circuit emulation is assured by the use of the

processor’s JTAG interface—the emulator does not affect target

system loading or timing.

• Trace instruction execution

• View the internal pipeline to further optimize peripherals

• Perform linear or statistical profiling of program

execution

• Fill, dump, and graphically plot the contents of memory

VisualDSP++ is a trademark of Analog Devices, Inc.

REV. A

–15–

ADSP-BF535

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide range

of tools supporting the Blackfin processor family. Third Party

softwaretoolsincludeDSPlibraries,real-timeoperatingsystems,

and block diagram design tools.

emulator uses the TAP to access the internal features of the pro-

cessor, allowing the developer to load code, set breakpoints,

observe variables, observe memory, and examine registers. The

processor must be halted to send data and commands, but once

an operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

EZ-KIT Lite

™ for ADSP-BF535 Blackfin Processor

The EZ-KIT Lite provides developers with a cost-effective

method for initial evaluation of the ADSP-BF535 Blackfin pro-

cessor. The EZ-KIT Lite includes a desktop evaluation board

and fundamental debugging software to facilitate architecture

evaluations via a PC hosted toolset. With the EZ-KIT Lite, users

can learn more about Analog Devices hardware and software

development tools and prototype applications. The EZ-KIT Lite

includes an evaluation suite of the VisualDSP++ development

environment with C/C++ compiler, assembler, and linker. The

VisualDSP++softwareincludedwiththekitislimitedinprogram

memory size and limited to use with the EZ-KIT Lite product.

To use these emulators, the target’s design must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including single

processor connections, multiprocessor scan chains, signal buff-

ering, signal termination, and emulator pod logic, see the EE-68:

Analog Devices JTAG Emulation Technical Reference on the Analog

Devices website (www.analog.com)—use site search on

“EE-68”. This document is updated regularly to keep pace with

improvements to emulator support.

Additional Information

Designing an Emulator Compatible

Processor Board (Target)

The Analog Devices family of emulators are tools that every

system developer needs to test and debug hardware and software

systems.AnalogDeviceshassuppliedanIEEE1149.1JTAGTest

Access Port (TAP) on the ADSP-BF535 Blackfin processor. The

This data sheet provides a general overview of the ADSP-BF535

Blackfin processor architecture and functionality. For detailed

information on the Blackfin processor family core architecture

and instruction set, refer to the ADSP-BF535 Blackfin Processor

Hardware Reference and the Blackfin Processor Instruction Set

Reference

.

EZ-KIT Lite is a trademark of Analog Devices, Inc.

–16–

REV. A

ADSP-BF535

PIN DESCRIPTIONS

ADSP-BF535 Blackfin processor pin definitions are listed in

Table 7. The following pins are asynchronous: ARDY, PF15–0,

USB_CLK, NMI, TRST, RESET, PCI_CLK, XTALI,

XTALO.

Table 7. Pin Descriptions

Type Function

ADDR25–2

DATA31–0

O/T External address bus.

I/O/T External data bus. (Pin has a logic-level hold circuit that prevents the input from floating

internally.)

ABE3–0/SDQM3–0

AMS3–0

ARDY¹

O/T Asynchronous memory byte enables SDRAM data masks.

O/T Chip selects for asynchronous memories.

I

Acknowledge signal for asynchronous memories.

AOE

O/T Memory output enable for asynchronous memories.

ARE

AWE

CLKOUT/SCLK1

O

Read enable for asynchronous memories.

Write enable for asynchronous memories.

SDRAM clock output pin. Same frequency and timing as SCLK0. Provided to reduce

capacitance loading on SCLK0. Connect to SDRAM’s CK pin.

SDRAM clock output pin 0. Switches at system clock frequency. Connect to the

SDRAM’s CK pin.

SCLK0

O

SCKE

SA10

O/T SDRAM clock enable pin. Connect to SDRAM’s CKE pin.

O/T SDRAM A10 pin. SDRAM interface uses this pin to retain control of the SDRAM device

during host bus requests. Connect to SDRAM’s A10 pin.

SRAS

SCAS

SWE

O/T SDRAM row address strobe pin. Connect to SDRAM’s RAS pin.

O/T SDRAM column address select pin. Connect to SDRAM’s CAS pin.

O/T SDRAM write enable pin. Connect to SDRAM’s WE or W buffer pin.

O/T Memory select pin of external memory bank configured for SDRAM. Connect to

SDRAM’s chip select pin.

SMS3–0

TMR0

TMR1

TMR2

I/O/T Timer 0 pin. Functions as an output pin in PWMOUT mode and as an input pin in

WIDTH_CNT and EXT_CLK modes.

I/O/T Timer 1 pin. Functions as an output pin in PWMOUT mode and as an input pin in

WIDTH_CNT and EXT_CLK modes.

I/O/T Timer 2 pin. Functions as an output pin in PWMOUT mode and as an input pin in

WIDTH_CNT and EXT_CLK modes.

PF15/SPI1SEL7

PF14/SPI0SEL7

PF13/SPI1SEL6

PF12/SPI0SEL6

PF11/SPI1SEL5

PF10/SPI0SEL5

I/O/T Programmable flag pin. SPI output select pin.

I/O/T Programmable flag pin. SPI output select pin (used during SPI boot).

PF9/SPI1SEL4/SSEL1 I/O

Programmable flag pin. SPI output select pin. Sampled during reset to determine core

clock to system clock ratio.

PF8/SPI0SEL4/SSEL0 I/O

Programmable flag pin. SPI output select pin. Sampled during reset to determine core

clock to system clock ratio.

PF7/SPI1SEL3/DF

I/O

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. DF = 1 is for high frequency clock and divides

the input clock by 2. DF = 0 passes input clock directly to PLL phase detector.

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

PF6/SPI0SEL3/MSEL6 I/O

PF5/SPI1SEL2/MSEL5 I/O

Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state

REV. A

–17–

ADSP-BF535

Table 7. Pin Descriptions (continued)

Type Function

PF4/SPI0SEL2/MSEL4 I/O

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

PF3/SPI1SEL1/MSEL3 I/O

PF2/SPI0SEL1/MSEL2 I/O

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

Programmable flag pin. SPI output select pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

Programmable flag pin. SPI slave select input pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

Programmable flag pin. SPI slave select input pin. Sensed for configuration state during

hardware reset, used to configure the PLL. Selects CK to CLKIN ratio.

PF1/SPISS1/MSEL1

PF0/SPISS0/MSEL0

I/O

RSCLK0

RFS0

I/O/T Receive serial clock for SPORT0.

I/O/T Receive frame synchronization for SPORT0.

DR0

I

Serial data receive for SPORT0.

TSCLK0

TFS0

I/O/T Transmit serial clock for SPORT0.

I/O/T Transmit frame synchronization for SPORT0.

DT0

O

Serial data transmit for SPORT0.

RSCLK1

RFS1

I/O/T Receive serial clock for SPORT1.

I/O/T Receive frame synchronization for SPORT1.

DR1

I

Serial data receive for SPORT1.

TSCLK1

TFS1

I/O/T Transmit serial clock for SPORT1.

I/O/T Transmit frame synchronization for SPORT1.

DT1

O

Serial data transmit for SPORT1.

MOSI0

I/O

Master out slave in pin for SPI0. Supplies the output data from the master device and

receives the input data to a slave device.

MISO0

I/O

Master in slave out pin for SPI0. Supplies the output data from the slave device and

receives the input data to the master device.

SCK0

MOSI1

I/O

Clock line for SPI0. Master device output clock signal. Slave device input clock signal.

Master out slave in pin for SPI1. Supplies the output data from the master device and

receives the input data to a slave device.

MISO1

I/O

Master in slave out pin for SPI1. Supplies the output data from the slave device and

receives the input data to the master device.

SCK1

RX0

I/O

I

Clock line for SPI1. Master device output clock signal. Slave device input clock signal.

UART0 receive pin.

TX0

RX1

O

I

UART0 transmit pin.

UART1 receive pin.

TX1

O

I

O

I

UART1 transmit pin.

USB clock.

USB_CLK

XVER_DATA

DPLS

DMNS

TXDPLS

TXDMNS

TXEN

SUSPEND

NMI

Single ended receive data output from USB transceiver to the USBD module.

Differential D+ receive data output from the USB transceiver to the UBD module.

Differential D- receive data output from the USB transceiver to the USBD module.

Transmitted D+ from the USBD module to the USB transceiver.

Transmitted D- from the USBD module to the USB transceiver.

Transmit enable from the USBD module to the USB transceiver.

Suspend mode enable output from the USBD module to the USB transceiver.

Non-maskable interrupt.

TCK

I

JTAG clock.

TDO

O/T JTAG serial data out.

TDI

TMS

I

JTAG serial data in.

Test mode select.

Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state

–18–

REV. A

ADSP-BF535

Table 7. Pin Descriptions (continued)

Type Function

TRST

I

JTAG reset.

RESET

When this pin is asserted to logic zero level for at least 10 CLKIN cycles, a hardware reset

is initiated. The minimum pulse width for power-on reset is 40 µs.

Clock in.

Dedicated mode pin. May be permanently strapped to V_DDor V_SS. Bypasses the on-chip

PLL.

CLKIN1

BYPASS

I

DEEPSLEEP

BMODE2–0

O

I

Denotes that the Blackfin processor core is in Deep Sleep mode.

Dedicated mode pin. May be permanently strapped to V_DDor V_SS. Configures the boot

mode that is employed following hardware reset or software reset.

PCI_AD31–0

PCI_CBE3–0

PCI_FRAME

I/O/T PCI address and data bus.

I/O/T PCI byte enables.

I/O/T PCI frame signal. Used by PCI initiators for signalling the beginning and end of a PCI

transaction.

PCI_IRDY

PCI_TRDY

PCI_DEVSEL

PCI_STOP

PCI_PERR

PCI_PAR

I/O/T PCI initiator ready signal.

I/O/T PCI target ready signal.

I/O/T PCI device select signal. Asserted by targets of PCI transactions to claim the transaction.

I/O/T PCI stop signal.

I/O/T PCI parity error signal.

I/O/T PCI parity signal.

PCI_REQ

O

PCI request signal. Used for requesting the use of the PCI bus.

PCI_SERR

PCI_RST

I/O/T PCI system error signal. Requires a pull-up on the system board.

I/O/T PCI reset signal.

PCI_GNT

PCI_IDSEL

I

PCI grant signal. Used for granting access to the PCI bus.

PCI initialization device select signal. Individual device selects for targets of PCI config-

uration transactions.

PCI_LOCK

I

PCI lock signal. Used to lock a target or the entire PCI bus for use by the master that

asserts the lock.

PCI_CLK

I

PCI clock.

PCI_INTA

I/O/T PCI interrupt A line on PCI bus. Asserted by the ADSP-BF535 Blackfin processor as a

device-to-signal an interrupt to the system processor. Monitored by the ADSP-BF535

when acting as the system processor.

PCI_INTB

PCI_INTC

PCI_INTD

I

PCI interrupt B line. Monitored by ADSP-BF535 Blackfin processor when acting as the

system processor.

PCI interrupt C line. Monitored by the ADSP-BF535 Blackfin processor when acting as

the system processor.

PCI interrupt D line. Monitored by the ADSP-BF535 Blackfin processor when acting as

the system processor.

XTAL1

XTAL0

EMU

I

O

Real-Time Clock oscillator input.

Real-Time Clock oscillator output.

Emulator acknowledge, open drain. Must be connected to the ADSP-BF535 Blackfin

processor emulator target board connector only.

PLL power supply (1.5 V nominal).

Real-Time Clock power supply (3.3 V nominal).

I/O (except PCI) power supply (3.3 V nominal).

PCI I/O power supply (3.3 V nominal).

V_DDPLL

V_DDRTC

V_DDEXT

V_DDPCIEXT

V_DDINT

GND

P

G

Internal power supply (1.5 V nominal).

Power supply return.

Type column symbols: G = Ground, I = Input, O = Output, P = Power supply, T = Three-state

REV. A

–19–

ADSP-BF535

Unused Pins

Table 8 shows recommendations for tying off unused pins. All

pins that are not listed in the table should be left floating.

Table 8. Recommendations for Tying Off Unused Pins

Tie Off

ARDY

V_DDEXT

BMODE2–0

BYPASS

V_DDEXTor GND

V

_DDEXTor GND

DMNS

DPLS

GND

DR0

DR1

V

_DDEXTor GND

NMI

GND

PCI_AD31–0

PCI_CB3–0

PCI_CLK

V_DDEXT

GND

PCI_DEVSEL

PCI_FRAME

PCI_GNT

PCI_IDSEL

PCI_INTA

PCI_INTB

PCI_INTC

PCI_INTD

PCI_IRDY

PCI_LOCK

PCI_PAR

V_DDEXT

GND

V_DDEXT

PCI_PERR

PCI_RST

V_DDEXT

PCI_STOP

PCI_SERR

PCI_TRDY

PF0/SPISS0/MSEL0

PF1/SPISS1/MSEL1

PF2/SPI0SEL1/MSEL2

V_DDEXT

V_DDEXTor GND (10 kΩpull-up/pull-down required)

V

_DDEXTor GND (10 kΩpull-up/pull-down required)

PF3/SPI1SEL1/MSEL3 V_DDEXTor GND (10 kΩpull-up/pull-down required)

PF4/SPI0SEL2/MSEL4 _DDEXTor GND (10 kΩpull-up/pull-down required)

PF5/SPI1SEL2/MSEL5 V_DDEXTor GND (10 kΩpull-up/pull-down required)

V

PF6/SPI0SEL3/MSEL6

PF7/SPI1SEL3/DF

PF8/SPI0SEL4/SSEL0

V

_DDEXTor GND (10 kΩpull-up/pull-down required)

V_DDEXTor GND (10 kΩpull-up/pull-down required)

_DDEXTor GND (10 kΩpull-up/pull-down required)

V

PF9/SPI1SEL4/SSEL1 V_DDEXTor GND (10 kΩpull-up/pull-down required)

RX0

RX1

TCK

V_DDEXTor GND

V_DDEXT

TDI

V_DDEXT

TMS

V_DDEXT

TRST

GND

USB_CLK

V_DDPCIEXT

V_DDRTC

XTAL1

XVER_DATA

GND

V_DDEXT

V_DDEXTor GND

GND

–20–

REV. A

ADSP-BF535

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

Min

Nominal Max

Unit

V_DDINT

Internal (Core) Supply Voltage¹

ADSP-BF535PKB-350

0.95

3.15

1.425

2.60

1.6

1.5

3.3

1.5

3.3

1.65

1.575

3.45

1.575

3.45

V

ADSP-BF535PKB-300

ADSP-BF535PBB-300

ADSP-BF535PBB-200

V_DDEXT

V_DDPLL

V_DDRTC

V_DDPCIEXT

V_IH

External (I/O) Supply Voltage¹

PLL Power Supply Voltage¹

Real-Time Clock Power Supply Voltage¹

PCI I/O Power Supply Voltage¹

High Level Input Voltage², @ V_DDEXT=max

Low Level Input Voltage², @ V_DDEXT= min

High Level Input Voltage³, @ V_DDEXT=max

High Level Input Voltage⁴, @ V_DDPCIEXT=max

Low Level Input Voltage⁴, @ V_DDPCIINT=min

Ambient Operating Temperature

Commercial

3.15

2.2

–0.3

2.4

0.5

؋

V_DDPCIEXT

–0.5

V_DDEXT+0.5

+0.6

V_DDEXT+0.5

V_DDPCIEXT+0.5

+0.3

؋

V_DDPCIEXT

V

V_IL

V_IHUSBCLK

V_IHPCI

V_ILPCI

T_A

V

ºC

0

–40

70

+85

Industrial

Specifications subject to change without notice.

¹There is no requirement for sequencing of the voltage supplies on powerup, however, the supply regulators must be able to provide the required current

I_DDRESETat all times. See Table 26.

²Applies to input and bidirectional pins, except PCI and USB_CLK.

³Applies to USB_CLK.

⁴Applies to PCI input and bidirectional pins: PCI_AD31– 0, PCI_CBE3–0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP,

PCI_PERR, PCI_PAR, PCI_SERR, PCI_RST, PCI_GNT, PCI_IDSEL, PCI_LOCK, PCI_CLK, PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

V_OH

V_OL

High Level Output Voltage¹

@ V_DDEXT= min, I_OH= –0.5 mA 2.4

@ V_DDEXT= max, I_OL= 2.0 mA

V

Low Level Output Voltage¹

0.4

V_OHPCIPCI High Level Output Voltage²@ V_DDPCIEXT= min, I_OH= –0.5 mA 0.9

؋

V_DDPCIEXT

V_OLPCIPCI Low Level Output Voltage²@ V_DDPCIEXT= max, I_OL= 2.0 mA

0.1

؋

V_DDPCIEXT

I_IH

I_IL

I_OZH

I_OZL

C_IN

High Level Input Current³

Low Level Input Current³

Three-State Leakage Current⁴

Input Capacitance^{5, 6}

@ V_DDEXT= max, V_IN= V_DDmax

@ V_DDEXT= max, V_IN= 0 V

@ V_DDEXT= max, V_IN= V_DDmax

@ V_DDEXT= max, V_IN= 0 V

f_IN= 1 MHz,

10

5

µA

pF

T_A= 25°C, V_IN= 2.5 V

Specifications subject to change without notice.

¹Applies to output and bidirectional pins, except PCI.

²Applies to PCI output and bidirectional pins: PCI_AD31–0, PCI_CBE3–0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP,

PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA.

³Applies to input pins.

⁴Applies to three-statable pins.

⁵Applies to all signal pins.

⁶Guaranteed but not tested.

REV. A

–21–

ADSP-BF535

ABSOLUTE MAXIMUM RATINGS

Internal (Core) Supply Voltage (V_DDINT)¹.–0.3 V to +1.65 V

External (I/O) Supply Voltage (V_DDEXT)¹. . .–0.3 V to +4.0 V

Input Voltage¹. . . . . . . . . . . . . . . . –0.5 V to V_DDEXT+0.5 V

Output Voltage Swing¹. . . . . . . . . –0.5 V to V_DDEXT+0.5 V

Load Capacitance^{1, 2}. . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Core Clock: ¹

ADSP-BF535PKB-350 . . . . . . . . . . . . . . . . . 350 MHz

ADSP-BF535PKB-300 . . . . . . . . . . . . . . . . . 300 MHz

ADSP-BF535PBB-300 . . . . . . . . . . . . . . . . . 300 MHz

ADSP-BF535PBB-200 . . . . . . . . . . . . . . . . . 200 MHz

System Clock (SCLK)¹. . . . . . . . . . . . . . . . . . . . 133 MHz

Storage Temperature Range¹. . . . . . . . . . –65ºC to +150ºC

¹Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these

or any other conditions greater than those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

²For proper SDRAM controller operation, the maximum load capacitance is 50 pF

for ADDR, DATA, ABE3–0/SDQM3–0, CLKOUT/SCLK1, SCLK0, SCKE,

SA10, SRAS, SCAS, SWE, and SMS3-0.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V

readily accumulate on the human body and test equipment and can discharge without

detection. Although the ADSP-BF535 features proprietary ESD protection circuitry,

permanent damage may occur on devices subjected to high energy electrostatic

discharges. Therefore, proper ESD precautions are recommended to avoid perfor-

mance degradation or loss of functionality.

–22–

REV. A

ADSP-BF535

TIMING SPECIFICATIONS

Table 9 and Table 10 describe the timing requirements for the

ADSP-BF535 Blackfin processor clocks. Take care in selecting

MSEL and SSEL ratios so as not to exceed the maximum core

clock, system clock and Voltage Controlled Oscillator (VCO)

operating frequencies, as described in Absolute Maximum

Ratings on Page 22. Table 10 describes phase-locked loop

operating conditions.

Table 9. Core Clock Requirements

Parameter

Min

Max

Unit

t_CCLK1.6

t_CCLK1.5

t_CCLK1.4

t_CCLK1.3

t_CCLK1.2

t_CCLK1.1

t_CCLK1.0

Core Cycle Period (V_DDINT=1.6 V–50 mV)

Core Cycle Period (V_DDINT=1.5 V–5%)

Core Cycle Period (V_DDINT=1.4 V–5%)

Core Cycle Period (V_DDINT=1.3 V–5%)

Core Cycle Period (V_DDINT=1.2 V–5%)

Core Cycle Period (V_DDINT=1.1 V–5%)

Core Cycle Period (V_DDINT=1.0 V–5%)

2.86

3.33

3.70

4.17

4.76

5.56

6.67

200

ns

Table 10. Phase-Locked Loop Operating Conditions

Parameter

Min

Nominal Max

Unit

Operating Voltage

1.425

1.5

1.575

120

60

120

400

1

V

ps

MHz

ps/mV

Jitter, Rising Edge to Rising Edge, Per Output¹

Jitter, Rising Edge to Falling Edge, Per Output¹

Skew, Rising Edge to Rising Edge, Any Two Outputs¹

Voltage Controlled Oscillator (VCO) Frequency¹

40

V

_DDPLLInduced Jitter¹

¹Guaranteed but not tested.

REV. A

–23–

ADSP-BF535

Clock and Reset Timing

Table 11 and Figure 8 describe clock and reset operations. Per

ABSOLUTE MAXIMUM RATINGS on Page 22, combina-

tions of CLKIN and clock multipliers must not select core and

system clocks in excess of 350/300/200 MHz and 133 MHz,

respectively.

Table 11. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CKIN

t_CKINL

t_CKINH

t_WRST

t_MSD

CLKIN Period

25.0

10.0

11

؋

t_CKIN

100.0

ns

CLKIN Low Pulse¹

CLKIN High Pulse¹

RESET Asserted Pulse Width Low²

Delay from RESET Asserted to MSELx, SSELx, BYPASS,

and DF Valid³

15.0

t_MSS

t_MSH

MSELx/SSELx/DF/BYPASS Stable Setup Before RESET 2

؋

t_CKIN

ns

Deasserted⁴

MSELx/SSELx/DF/BYPASS Stable Hold After RESET

2

؋

t_CKIN

Deasserted

Switching Characteristics

t_PFD

Flag Output Disable Time After RESET Asserted

15.0

ns

¹Applies to Bypass mode and Non-bypass mode.

²Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while

RESET is asserted, assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).

³SSELx, MSELx and DF values can change from this point, but the values must be valid.

⁴SSELx, MSELx and DF values must be held from this time, until the hold time expires.

t_{C K IN}

CLKIN

t_{C K IN H}

t_{C K IN L}

t_{W R S T}

RESET

t_{MS D}

t_{MS S}

t_{M S H}

t_{P F D}

SSEL1–0

MSEL6–0

BYPASS

DF

Figure 8. Clock and Reset Timing

–24–

REV. A

ADSP-BF535

Programmable Flags Cycle Timing

Table 12 and Figure 9 describe programmable flag operations.

Table 12. Programmable Flags Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

t_HFIES

Edge Sensitive Flag Input Hold is Asynchronous

3.0

ns

t_HFILS

Level Sensitive Flag Input Hold

t_SCLK+3

Switching Characteristics

t_DFOFlag Output Delay with Respect to SCLK

t_HFO

6.0

ns

Flag Output Hold After SCLK High

SCLK

t_DFO

t_HFO

PF (OUTPUT)

FLAG

OUTPUT

t_HFIxS

PF (INPUT)

FLAG INPUT

Figure 9. Programmable Flags Cycle Timing

REV. A

–25–

ADSP-BF535

Timer PWM_OUT Cycle Timing

Table 13 and Figure 10 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and has

an absolute maximum input frequency of f_SCLK،2.

Table 13. Timer PWM_OUT Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_HTO

Timer Pulse Width Output¹

7.5

(2³²–1) cycles

ns

¹The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

SCLK

t_HTO

PWM_OUT

Figure 10. Timer PWM_OUT Cycle Timing

–26–

REV. A

ADSP-BF535

Asynchronous Memory Write Cycle Timing

Table 14 and Figure 11 describe Asynchronous Memory Write

Cycle timing.

Table 14. Asynchronous Memory Write Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

4.0

–1.0

ns

Switching Characteristics

t_DDAT

t_ENDAT

t_DO

DATA31–0 Disable After CLKOUT

6.0

7.0

ns

DATA31–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

1.0

0.8

t_HO

¹Output pins include AMS3–0, ABE3–0, ADDR25–2, DATA31–0, AOE, AWE.

ACCESS

EXTENDED

1 CYCLE

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE3–0

BE, ADDRESS

ADDR25–2

t_DO

t_HO

AWE

t_HARDY

t_SARDY

ARDY

t_SARDY

t_ENDAT

t_DDAT

DATA31–0

WRITE DATA

Figure 11. Asynchronous Memory Write Cycle Timing

REV. A

–27–

ADSP-BF535

Asynchronous Memory Read Cycle Timing

Table 15 and Figure 12 describe Asynchronous Memory Read

Cycle timing.

Table 15. Asynchronous Memory Read Cycle Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

DATA31–0 Setup Before CLKOUT

DATA31–0 Hold After CLKOUT

ARDY Setup Before CLKOUT

ARDY Hold After CLKOUT

2.1

2.6

4.0

–1.0

ns

t_HDAT

t_SARDY

t_HARDY

Switching Characteristics

t_DO

t_HO

Output Delay After CLKOUT¹

Output Hold After CLKOUT ¹

7.0

ns

0.8

¹Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

3 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE3–0

BE, ADDRESS

ADDR25–2

AOE

t_DO

t_HO

ARE

t_HARDY

t_SARDY

t_HARDY

ARDY

t_SARDY

t_SDAT

t_HDAT

DATA31–0

READ

Figure 12. Asynchronous Memory Read Cycle Timing

–28–

REV. A

ADSP-BF535

SDRAM Interface Timing

For proper SDRAM controller operation, the maximum load

capacitance is 50 pF for ADDR, DATA, ABE3–0/SDQM3–0

,

CLKOUT/SCLK1,SCLK0,SCKE,SA10,SRAS,SCAS,SWE,

and SMS3-0

.

Table 16. SDRAM Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSDAT

DATA Setup Before SCLK0/SCLK1

2.1

2.8

ns

t_HSDAT

DATA Hold After SCLK0/SCLK1

Switching Characteristics

t_SCLK

SCLK0/SCLK1 Period

SCLK0/SCLK1 Width High

SCLK0/SCLK1 Width Low

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

Command, ADDR, Data Delay After SCLK0/SCLK1¹

Command, ADDR, Data Hold After SCLK0/SCLK1¹

Data Disable After SCLK0/SCLK1

6.0

0.8

1.0

Data Enable After SCLK0/SCLK1

¹Command pins include: SRAS, SCAS, SWE, SDQM3–0, SMS, SA10, and SCKE.

t_SCLKH

t_SCLK

SCLK0/

SCLK1

t_SSDAT

t_HSDAT

t_SCLKL

DATA

(IN)

t_DSDAT

t_HCAD

t_DCAD

t_ENSDAT

DATA

(OUT)

t_DCAD

CMND1

ADDR

(OUT)

t_HCAD

NOTE 1: COMMAND = SRAS, SCAS, SWE, SDQM3–0, SMS, SA10, AND SCKE.

Figure 13. SDRAM Interface Timing

REV. A

–29–

ADSP-BF535

Serial Ports

Table 17 through Table 22 and Figure 14 describe Serial Port

timing.

Table 17. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

t_HFSE

t_SDRE

t_HDRE

t_SCLKWE

t_SCLKE

TFS/RFS Setup Before TCLK/RCLK¹

TFS/RFS Hold After TCLK/RCLK¹

Receive Data Setup Before RCLK¹

Receive Data Hold Before RCLK¹

TCLK/RCLK Width

3.0

ns

(0.5

؋

t_SCLKE) – 1

2

؋

t_SCLK

TCLK/RCLK Period

¹Referenced to sample edge.

Table 18. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

TFS/RFS Setup Before TCLK/RCLK¹

7.0

2.0

7.0

4.0

ns

t_HFSI

t_SDRI

t_HDRI

TFS/RFS Hold After TCLK/RCLK¹

Receive Data Setup Before RCLK¹

Receive Data Hold Before RCLK¹

¹Referenced to sample edge.

Table 19. Serial Ports—External or Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSE

t_HOFSE

RFS Delay After RCLK (Internally Generated RFS)¹

10.0

ns

RFS Hold After RCLK (Internally Generated RFS)¹

3.0

¹Referenced to drive edge.

Table 20. Serial Ports—External Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSE

TFS Delay After TCLK (Internally Generated TFS)¹

10.0

ns

t_HOFSE

t_DDTE

t_HDTE

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

3.0

Transmit Data Hold After TCLK¹

¹Referenced to drive edge.

Table 21. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Switching Characteristics

t_DFSI

TFS Delay After TCLK (Internally Generated TFS)¹

6.0

8.0

ns

t_HOFSI

t_DDTI

t_HDTI

t_SCLKWI

TFS Hold After TCLK (Internally Generated TFS)¹

Transmit Data Delay After TCLK¹

Transmit Data Hold After TCLK¹

TCLK/RCLK Width

0.0

0.5

؋

t_SCLK

¹Referenced to drive edge.

–30–

REV. A

ADSP-BF535

Table 22. Serial Ports—Enable and Three-State (Multichannel Mode Only)

Parameter

Min

Max

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TCLK¹

Data Disable Delay from External TCLK¹

Data Enable Delay from Internal TCLK¹

Data Disable Delay from Internal TCLK¹

3.0

2.0

ns

12.0

¹Referenced to drive edge and TCLK is tied to RCLK.

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKWI

t_SCLKWE

RCLK

t_DFSE

t_SFSE

t_HFSE

t_HOFSE

t_SFSI

t_HFSI

t_HOFSE

RFS

DR

RFS

DR

t_HDRE

t_SDRI

t_HDRI

t_SDRE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT—INTERNAL CLOCK

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKWI

t_SCLKWE

TCLK

t_DFSI

t_DFSE

t_SFSE

t_HFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

TFS

DT

TFS

DT

t_DDTE

t_DDTI

t_HDTE

t_HDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE

TCLK (EXT)

TFS (“LATE”, EXT)

TCLK/RCLK

t_DTENE

t_DDTTE

DT

DRIVE EDGE

TCLK (INT)

TFS (“LATE”, INT)

TCLK/RCLK

t_DTENI

t_DDTTI

DT

Figure 14. Serial Ports

REV. A

–31–

ADSP-BF535

Serial Peripheral Interface (SPI) Port

—Master Timing

Table 23 and Figure 15 describe SPI port master operations.

Table 23. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPID

t_HSPID

Data Input Valid to SCK Edge (Data Input Setup)

SCK Sampling Edge to Data Input Invalid

6.5

1.6

ns

Switching Characteristics

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

t_HDSM

t_SPITDM

t_DDSPID

t_HDSPID

SPIxSEL Low to First SCK Edge (x=0 or 1)

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SCK Edge to SPIxSEL High (x=0 or 1)

Sequential Transfer Delay

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

(2

؋

t_SCLK) – 3

(2

؋

t_SCLK) – 3

(2

؋

t_SCLK) – 3

4

؋

t_SCLK

(2

؋

t_SCLK) – 3

2

؋

t_SCLK

ns

0.0

6.0

5.0

SPIxSEL

(OUTPUT)

(x = 0 OR 1)

t_{SD SCIM}t_{SPICH M}

t_{SPIC LM}

t_SPICLK

t_HDSM

t_SPITDM

SCK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_{SPICH M}

SCK

(CPOL = 1)

(OUTPUT)

t_DDSPID

t_{H DSPID}

MOSI

(OUTPUT)

MSB

LSB

t_SSPID

CPHA = 1

t_SSPID

t_HSPID

MISO

(INPUT)

MSB

VALID

LSB

VALID

t_DDSPID

t_HDSPID

MOSI

(OUTPUT)

MSB

LSB

CPHA = 0

t_SSPID

t_HSPID

MSB

LSB

MISO

(INPUT)

VALID

Figure 15. Serial Peripheral Interface (SPI) Port—Master Timing

–32–

REV. A

ADSP-BF535

Serial Peripheral Interface (SPI) Port

—Slave Timing

Table 24 and Figure 16 describe SPI port slave operations.

Table 24. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

Serial Clock High Period

Serial Clock Low Period

Serial Clock Period

Last SPICLK Edge to SPISS Not Asserted

Sequential Transfer Delay

SPISS Assertion to First SCK Edge

Data Input Valid to SCK Edge (Data Input Setup)

SCK Sampling Edge to Data Input Invalid

2t_SCLK

4t_SCLK

2t_SCLK

1.6

ns

1.6

Switching Characteristics

t_DSOE

SPISS Assertion to Data Out Active

0.0

6.0

6.5

7.0

6.5

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPISS Deassertion to Data High Impedance

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

SPISSx

(INPUT)

t_SPICHS

t_SPICLS

t_DDSPID

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCK

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICHS

SCK

(CPOL = 1)

(INPUT)

t_DSOE

t_HDSPID

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_HSPID

CPHA = 1

t_SSPID

t_HSPID

MSB

VALID

LSB

VALID

MOSI

(INPUT)

t_DSOE

t_DSDHI

t_DDSPID

MSB

MISO

(OUTPUT)

LSB

CPHA = 0

t_SSPID

t_HSPID

MSB

LSB

MOSI

VALID

(INPUT)

Figure 16. Serial Peripheral Interface (SPI) Port—Slave Timing

REV. A

–33–

ADSP-BF535

Universal Asynchronous Receiver-Transmitter (UART)

Port—Receive and Transmit Timing

Figure 17 describes UART port receive and transmit operations.

The maximum baud rate is SCLK/16. As shown in Figure 17,

there is some latency between the generation of internal UART

interrupts and the external data operations. These latencies are

negligible at the data transmission rates for the UART.

SCLK

(SAMPLE

CLOCK)

DATA(5–8)

RxD

STOP

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA

STOP; CLEARED BY FIFO READ

START

DATA(5–8)

STOP (1–2)

TxD

AS DATA

WRITTEN TO

BUFFER

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 17. UART Port—Receive and Transmit Timing

–34–

REV. A

ADSP-BF535

JTAG Test and Emulation Port Timing

Table 25 and Figure 18 describe JTAG port operations.

Table 25. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

t_TCK

TCK Period

20.0

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK Low¹

System Inputs Hold After TCK Low¹

TRST Pulse Width²

4.0

5.0

4.0

0.0

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

7.0

15.0

ns

¹System Inputs=DATA31-0, ADDR25-2, ARDY, TMR2-0, PF15-0, RSCLK0, RFS0, DR0, TSCLK0, TFS0, RSCLK1, RFS1, DR1, TSCLK1, TFS1,

MOSI0, MISO0, SCK0, MOSI1, MISO1, SCK1, RX0, RX1, USB_CLK, XVER_DATA, DPLS, DMNS, NMI, RESET, BYPASS, BMODE2-0,

PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY, PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_SERR, PCI_RST,

PCI_GNT, PCI_IDSEL, PCI_LOCK, PCI_CLK, PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD.

²50 MHz max.

³System Outputs=DATA31-0, ADDR25-2, ABE3-0/SDQM3-0, AOE, ARE, AWE, SCAS, CLKOUT/SCLK1, SCLK0, SCKE, SA10, SWE, SMS3-0,

SRAS, TMR2-0, PF15-0, RSCLK0, RFS0, TSCLK0, TFS0, DT0, RSCLK1, RFS1, TSCLK1, TFS1, DT1, MOSI0, MISO0, SCK0, MOSI1, MISO1,

SCK1, TX0, TX1, TXDPLS, TXDMNS, TXEN, SUSPEND, DEEPSLEEP, PCI_AD31-0, PCI_CBE3-0, PCI_FRAME, PCI_IRDY, PCI_TRDY,

PCI_DEVSEL, PCI_STOP, PCI_PERR, PCI_PAR, PCI_REQ, PCI_SERR, PCI_RST, PCI_INTA, EMU.

t_{T C K}

TCK

t_{S T A P}

t_{H T A P}

TM S

TDI

t_{D T D O}

T DO

t_{S S Y S}

t_{H S Y S}

SYSTEM

INPUTS

t_{D SY S}

SYSTEM

O UTPUTS

t_{T R S T W}

T RST

Figure 18. JTAG Port Timing

REV. A

–35–

ADSP-BF535

Output Drive Currents

200

150

100

50

Figure 19 through Figure 21 show typical current-voltage char-

acteristics for the output drivers of the ADSP-BF535 Blackfin

processor. The curves represent the current drive capability of

the output drivers as a function of output voltage. Figure 19

V

(V

= 3.45V, ؊45°C)

OH

DDEXT

V

(V

= 3.45V, 0°C)

OH

DDEXT

V

(V

= 3.3V, +25°C)

DDEXT

OH

V

(V

= 3.15V,

OH

DDEXT

+105°C)

applies to the ABE3–0, SDQM3–0, ADDR25–2, AMS3–0

,

AOE ARE AWE, CLKOUT, SCLK1, DATA31–0, DT1–0,

EMU, MISO1–0, MOSI1–0, PF15–0, RFS1–0, RSCLK1–0,

SA10, SCAS, SCK1–0, SCKE, SCLK0, DEEPSLEEP,

,

V

(V

= 2.5V, +85°C)

OH

DDEXT

0

؊50

V

(V

= 3.15V, +105°C)

OL

DDEXT

V

(V

= 2.5V, +85°C)

= 3.3V, +25°C)

OL

DDEXT

(V

V

OL

DDEXT

SMS3–0, SRAS, SUSPEND, SWE, TDO, TFS1–0, TMR2–0,

TSCLK1–0, TX1–0, TXDMNS, TXDPLS, TXEN, and

؊100

XTAL0 pins. Figure 20 applies to the PCI_AD31–0,

؊150

؊200

V

(V

= 3.45V, 0°C)

DDEXT

OL

V

(V

= 3.45V, ؊45°C)

OL

PCI_CBE3–0

,

PCI_DEVSEL

,

PCI_FRAME

,

PCI_INTA

,

DDEXT

PCI_IRDY, PCI_PAR, PCI_PERR

PCI_STOP, and PCI_TRDY pins. Figure 21 applies to the

PCI_REQ pin.

,

PCI_RST

,

PCI_SERR,

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE (V ) VOLTAGE – V

O

Figure 21. PCI_REQ Output Drive Current

Power Dissipation

200

V_OH(V_DDEXT= 3.45V, ؊40°C)

Total power dissipation has two components: one due to internal

circuitry (P_INT) and one due to the switching of external output

drivers (P_EXT). Table 26 shows the power dissipation for internal

circuitry(V_DDINT). Internalpowerdissipationisdependentonthe

instruction execution sequence and the data operands involved.

Table 27 shows the power dissipation for the phase-locked loop

(PLL) circuitry (V_DDPLL).

V_OH(V_DDEXT= 3.45V, 0°C)

150

V_OH(V_DDEXT= 3.3V, +25°C)

V_OH(V_DDEXT= 3.15V, +105°C)

100

V_OH(V_DDEXT= 2.5V, +85°C)

50

V_OL(V_DDEXT= 2.5V, +85°C)

0

V_OL(V_DDEXT= 3.15V, +105°C)

V_OL(V_DDEXT= 3.3V, +25°C)

؊50

The external component of total power dissipation is caused by

the switching of output pins. Its magnitude depends on:

؊100

• Maximum frequency (f₀) at which all output pins can

switch during each cycle

V_OL(V_DDEXT= 3.45V, 0°C)

V_OL(V_DDEXT= 3.45V, ؊40°C)

؊150

؊200

• Their load capacitance (C₀) of all switching pins

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SOURCE (V_O) VOLTAGE – V

• Their voltage swing (V_DDEXT

)

The external component is calculated using:

Figure 19. Output Drive Current

200

150

100

V

(V

= 3.45V, ؊45°C)

OH

DDEXT

(V

2

V

= 3.45V, 0°C)

P_EXT= V_DDEXT

×

C₀× f₀

OH

DDEXT

∑

V

(V

= 3.3V, +25°C)

OH

DDEXT

V

(V

= 3.15V, +105°C)

DDEXT

OH

V

(V

= 2.5V,

OH

DDEXT

+85°C)

50

0

Table 26. Internal Power Dissipation

Test Conditions¹

V

(V

= 3.45V, 0°C)

DDEXT

OL

V

(V

= 3.15V, +105°C)

OL

DDEXT

V

؊50

؊100

f_CCLK

100 MHz 200 MHz 300 MHz 350 MHz

V_DDINT= V_DDINT= V_DDINT= V_DDINT

=

f_CCLK

=

f_CCLK

=

f_CCLK=

(V

= 2.5V, +85°C)

OL

DDEXT

=

؊150

؊200

Parameter 1.0 V

1.2 V

1.5 V

1.6 V

Unit

2

I_DDTYP

I_DDEFR

96.0

114.0

15.0

206.0

248.0

29.0

5.0

255.0

387.0

463.0

52.0

8.2

485.3

498.0

579.0

62.0

9.8

651.0

mA

V

(V

= 3.45V, ؊45°C)

OL

؊250

؊300

DDEXT

V

3

(V

= 3.3V, +25°C)

OL

DDEXT

4

I_DDSLEEP

I_DDDEEPSLEEP4.0

I_DDRESET

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4

SOURCE (V ) VOLTAGE – V

O

5

132.0

Figure 20. PCI 33 MHz Output Drive Current

¹I_DDdata is specified for typical process parameters. All data at 25ºC.

²Processor executing 75% dual Mac, 25% ADD with moderate data bus

activity.

³Implementation of Enhanced Full Rate (EFR) GSM algorithm.

⁴See the ADSP-BF535 Blackfin Processor Hardware Reference Manual for

definitions of Sleep and Deep Sleep operating modes.

⁵I_DDis specified for when the device is in the reset state.

–36–

REV. A

ADSP-BF535

Table 27. PLL Power Dissipation

Parameter Test Conditions

The output disable time t_DISis the difference between

t_{DIS_MEASURED}and t_DECAYas shown in Figure 22. The time

t_{DIS_MEASURED}is the interval from when the reference signal

Typical Unit

4.0 mA

I_DDPLL

V_DDPLL=1.5 V, 25ºC

switchestowhentheoutputvoltagedecays

output high or output low voltage. The time t_DECAYis calculated

with test loads C_Land I_L, and with V equal to 0.5 V.

∆Vfromthemeasured

The frequency f includes driving the load high and then back low.

For example: DATA31–0 pins can drive high and low at a

∆

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-BF535 Blackfin proces-

sor’s output voltage and the input threshold for the device

maximum rate of 1/(2

؋

t_SCLK) while in SDRAM burst mode.

A typical power consumption can now be calculated for these

conditions by adding a typical internal power dissipation:

P_TOTAL= P_EXT+ (I_DD× V_DDINT

)

requiring the hold time. A typical ∆V will be 0.4 V. C_Lis the total

bus capacitance (perdata line), and I_Lis the total leakageor three-

state current (per data line). The hold time will be t_DECAYplus the

minimum disable time (for example, t_DSDATfor an SDRAM write

cycle).

Note that the conditions causing a worst-case P_EXTdiffer from

those causing a worst-case P_INT. Maximum P_INTcannot occur

while 100% of the output pins are switching from all ones (1s) to

all zeros (0s). Note, as well, that it is not common for an appli-

cation to have 100% or even 50% of the outputs switching

simultaneously.

Test Conditions

All timing parameters appearingin this data sheet weremeasured

under the conditions described in this section.

REFERENCE

SIGNAL

t_{DIS_MEASURED}

t_ENA-MEASURED

Output Enable Time

t_DIS

V_OH

t_ENA

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving. The output enable time t_ENAis the interval from the

point when a reference signal reaches a high or low voltage level

tothepointwhentheoutputstartsdrivingasshownintheOutput

Enable/Disable diagram (Figure 22). The time t_{ENA_MEASURED}is

the interval from when the reference signal switches to when the

output voltage reaches 2.0 V (output high) or 1.0 V (output low).

Time t_TRIPis the interval from when the output starts driving to

when the output reaches the 1.0 V or 2.0 V trip voltage. Time

t_ENAis calculated as shown in the equation:

V_OH

(MEASURED)

V_OH(MEASURED) ؊ ⌬V

V_OL(MEASURED) + ⌬V

2.0V

1.0V

(MEASURED)

V_OL

(MEASURED)

t_DECAY

t_TRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

Figure 22. Output Enable/Disable

t_ENA= t_{ENA_MEASURED}– t_TRIP

50⍀

TO

OUTPUT

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

1.5V

30pF

Output Disable Time

Outputpinsareconsideredtobedisabledwhentheystopdriving,

go into a high impedance state, and start to decay from their

output high or low voltage. The time for the voltage on the bus

Figure 23. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

to decay by ∆V is dependent on the capacitive load, C_Land the

load current, I_L. This decay time can be approximated by the

equation:

INPUT

OR

1.5V

OUTPUT

t_DECAY= (C_L∆V) ⁄ I_L

Figure 24. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

REV. A

–37–

ADSP-BF535

Environmental Conditions

where:

_A= Ambient temperature (؇C)

The ADSP-BF535 is offered in a 260-ball PBGA package.

T

Todeterminethejunctiontemperatureontheapplicationprinted

circuit board use:

Values of θ_JCare provided for package comparison and printed

circuit board design considerations when an external heatsink is

required.

Values of θ_JBare provided for package comparison and printed

circuit board design considerations.

T_J= T_CASE+ (Ψ_JT× P_D)

where:

In Table 28, airflow measurements comply with JEDEC

standards JESD51-2 and JESD51-6, and the junction-to-board

measurement complies with JESD51-8. The junction-to-case

measurement complies with MIL-STD-883 (Method 1012.1).

All measurements use a 2S2P JEDEC test board.

T_J= Junction temperature (

؇

C)

T_CASE= Case temperature (

؇C) measured by customer at top

center of package.

Ψ_T= From Table 28

J

Table 28. Thermal Characteristics

P_D= Power dissipation (see Power Dissipation on Page 36 for the

method to calculate P_D

)

Parameter Condition

Typical Unit

Values of θ_JAare provided for package comparison and printed

circuit board design considerations. θ_JAcan be used for a first

order approximation of T_Jby the equation:

θ_J

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

23.8

20.8

19.8

9.95

9.35

0.30

؇C/W

A

MA

B

C

T_J= T_A+ (θ_JA× P_D)

Ψ_T

J

0 linear m/s air flow

–38–

REV. A

ADSP-BF535

260-Ball PBGA Pinout

Table 29 lists the PBGA pinout by signal name. Table 30 on

Page 41 lists the pinout by pin number.

Table 29. 260-Ball PBGA Pin Assignment (Alphabetically by Signal)

Signal

R02 GND

P03 GND

U01 GND

U02 GND

T02 GND

V02 GND

V03 GND

R04 GND

U03 GND

T03 GND

T04 GND

U04 GND

Signal

ABE0/SDQM0

ABE1/SDQM1

ABE2/SDQM2

ABE3/SDQM3

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

E02

B01

G03

H07

A06

B06

D06

C06

A05

B05

A04

C05

D05

B04

A01

C04

D04

A03

B03

A02

C03

D03

B02

C02

E03

C01

F03

D02

F02

D01

H03

G02

E01

R01

F01

G01

B14

A14

B13

C12

D09

H01

N02

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

DATA16

DATA17

DATA18

DATA19

DATA20

DATA21

DATA22

DATA23

DATA24

DATA25

DATA26

DATA27

DATA28

DATA29

DATA30

DATA31

DMNS

DPLS

DR0

DR1

DT0

DT1

EMU

GND

K08

K09

K10

K11

K12

L07

L08

L09

L10

L11

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_CBE0

PCI_CBE1

PCI_CBE2

M16

N17

P17

P15

N16

R17

P16

F16

F15

E16

D17

D14

C16

C17

C18

B18

C14

B15

A15

D13

E15

A16

C15

D15

D16

D18

B16

A17

B17

U08

R08

T08

V10

U09

R09

T09

R11

T11

U11

V12

T12

R12

U12

V13

T13

B09

U13

ADDR7

ADDR8

ADDR9

M07 PCI_CBE3

M09 PCI_CLK

M10 PCI_DEVSEL

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

ADDR20

ADDR21

ADDR22

ADDR23

ADDR24

ADDR25

AMS0

AMS1

AMS2

AMS3

AOE

ARDY

ARE

AWE

BMODE0

BMODE1

BMODE2

BYPASS

CLKIN1

CLKOUT/SCLK1

DATA0

DATA1

DATA2

DATA3

DATA4

V04 GND

V05 MISO0

R05 MISO1

T05 MOSI0

U05 MOSI1

V06 N/C

R06 N/C

U06 N/C

T06 N/C

V07 NMI

V08 PCI_AD0

U07 PCI_AD1

R07 PCI_AD2

T07 PCI_AD3

V09 PCI_AD4

D08 PCI_AD5

C09 PCI_AD6

V14 PCI_AD7

U15 PCI_AD8

R14 PCI_AD9

V17 PCI_AD10

A13 PCI_AD11

C13 PCI_AD12

H02 PCI_AD13

H08 PCI_AD14

H10 PCI_AD15

H11 PCI_AD16

T16

U18

U16

T17

A18

R03

V01

V18

B11

E17

E18

G16

F17

F18

G18

G17

H18

J18

PCI_FRAME

PCI_GNT

PCI_IDSEL

PCI_INTA

PCI_INTB

PCI_INTC

PCI_INTD

PCI_IRDY

PCI_LOCK

PCI_PAR

PCI_PERR

PCI_REQ

PCI_RST

PCI_SERR

PCI_STOP

PCI_TRDY

PF0/SPISS0/MSEL0

PF1/SPISS1/MSEL1

PF2/SPI0SEL1/MSEL2

PF3/SPI1SEL1/MSEL3

PF4/SPI0SEL2/MSEL4

PF5/SPI1SEL2/MSEL5

PF6/SPI0SEL3/MSEL6

H17

K18

H16

L18

J17

M18 PF7/SPI1SEL3/DF

K17

J16

K16

N18

P18

L17

L16

R18

T18

PF8/SPI0SEL4/SSEL0

PF9/SPI1SEL4/SSEL1

PF10/SPI0SEL5

PF11/SPI1SEL5

PF12/SPI0SEL6

PF13/SPI1SEL6

PF14/SPI0SEL7

PF15/SPI1SEL7

RESET

J07

J08

J09

J10

J11

J12

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

M03 GND

T01

P02

N03

GND

K02 PCI_AD23

K07 PCI_AD24

M17 RFS0

REV. A

–39–

ADSP-BF535

Table 29. 260-Ball PBGA Pin Assignment (Alphabetically by Signal) (continued)

Signal

RFS1

V16

R13

U14

A07

B08

SWE

TCK

TDI

TDO

TFS0

J03

USB_CLK

G07

E04

G04

G08

J01

V_DDINT

V_DDPCIEXT

L12

M08

M11

M12

N04

N15

H15

J15

K15

L15

M15

G09

U10

A10

V11

R10

T10

A09

RSCLK0

RSCLK1

RX0

RX1

SA10

SCAS

SCK0

SCK1

SCKE

SCLK0

DEEPSLEEP

SMS0

SMS1

SMS2

SMS3

SRAS

SUSPEND

D10 V_DDEXT

C11 V_DDEXT

D11 V_DDEXT

T14 V_DDEXT

R15 V_DDEXT

B07 V_DDEXT

C07 V_DDEXT

D07 V_DDEXT

A12 V_DDEXT

B12 V_DDEXT

V15 V_DDINT

T15 V_DDINT

A08 V_DDINT

C08 V_DDINT

G10 V_DDINT

B10 V_DDINT

C10 V_DDINT

M01 TFS1

J02

J04

L03

U17

R16

L01

K01

D12

TMR0

TMR1

TMR2

TMS

TRST

TSCLK0

K04

L04

M04 V_DDPCIEXT

P04

F04

G11

G12

G15

H04

H09

H12

V_DDPCIEXT

V_DDPLL

V_DDRTC

V_SSPLL

V_SSRTC

XTAL1

XTAL0

XVER_DATA

M02 TSCLK1

P01

N01

K03

L02

A11

TX0

TX1

TXDMNS

TXDPLS

TXEN

–40–

REV. A

ADSP-BF535

Table 30. 260-Ball PBGA Pin Assignment (Numerically by Pin Number)

Pin Signal Pin Signal Pin Signal

Signal

A01 ADDR12

A02 ADDR17

A03 ADDR15

A04 ADDR8

A05 ADDR6

A06 ADDR2

A07 RX0

D12 DEEPSLEEP

D13 PCI_INTD

D14 PCI_CLK

D15 PCI_PERR

D16 PCI_REQ

D17 PCI_CBE3

D18 PCI_RST

E01 AOE

K01 SCLK0

K02 GND

K03 SMS3

K04 V_DDEXT

K07 GND

K08 GND

K09 GND

K10 GND

R08 PF1/SPISS1/MSEL1

R09 PF5/SPI1SEL2/MSEL5

R10 XTAL1

R11 PF7/SPI1SEL3/DF

R12 PF12/SPI0SEL6

R13 RSCLK0

R14 DT0

R15 TFS1

A08 TX0

A09 XVER_DATA

A10 V_SSPLL

A11 SUSPEND

A12 TMS

E02 ABE0/SDQM0

E03 ADDR22

E04 V_DDEXT

E15 PCI_IRDY

E16 PCI_CBE2

E17 PCI_AD0

E18 PCI_AD1

F01 ARE

F02 AMS0

F03 ADDR24

F04 V_DDINT

F15 PCI_CBE1

F16 PCI_CBE0

F17 PCI_AD3

F18 PCI_AD4

G01 AWE

K11 GND

K12 GND

K15 V_DDPCIEXT

K16 PCI_AD17

K17 PCI_AD15

K18 PCI_AD10

R16 SCK1

R17 PCI_AD30

R18 PCI_AD22

T01 DATA2

T02 DATA9

T03 DATA14

T04 DATA15

T05 DATA20

T06 DATA25

T07 DATA30

T08 PF2/SPI0SEL1/MSEL2

T09 PF6/SPI0SEL3/MSEL6

T10 XTAL0

T11 PF8/SPI0SEL4/SSEL0

T12 PF11/SPI1SEL5

T13 PF15/SPI1SEL7

T14 TFS0

T15 TSCLK1

T16 MISO0

T17 MOSI1

T18 PCI_AD23

U01 DATA7

A13 EMU

A14 BMODE1

A15 PCI_INTC

A16 PCI_LOCK

A17 PCI_STOP

A18 N/C

B01 ABE1/SDQM1

B02 ADDR20

B03 ADDR16

B04 ADDR11

B05 ADDR7

B06 ADDR3

B07 TMR0

L01

L02

L03

L04

L07

L08

L09

L10

L11

L12

L15

L16

L17

L18

SCKE

SRAS

SCAS

V_DDEXT

GND

V_DDINT

G02 AMS3

G03 ABE2/SDQM2

G04 V_DDEXT

G07 USB_CLK

G08 V_DDEXT

G09 V_DDPLL

V_DDPCIEXT

PCI_AD21

PCI_AD20

PCI_AD12

B08 RX1

B09 RESET

B10 TXDPLS

B11 NMI

M01 SA10

M02 SMS0

B12 TRST

B13 BMODE2

B14 BMODE0

B15 PCI_INTB

B16 PCI_SERR

B17 PCI_TRDY

B18 PCI_IDSEL

C01 ADDR23

C02 ADDR21

C03 ADDR18

C04 ADDR13

C05 ADDR9

C06 ADDR5

C07 TMR1

G10 TXDMNS

G11 V_DDINT

G12 V_DDINT

M03 DATA1

M04 V_DDEXT

M07 GND

M08 V_DDINT

M09 GND

U02 DATA8

U03 DATA13

U04 DATA16

U05 DATA21

U06 DATA24

U07 DATA28

U08 PF0/SPISS0/MSEL0

U09 PF4/SPI0SEL2/MSEL4

U10 V_DDRTC

U11 PF9/SPI1SEL4/SSEL1

U12 PF13/SPI1SEL6

U13 RFS0

G15 V_DDINT

G16 PCI_AD2

G17 PCI_AD6

G18 PCI_AD5

H01 CLKOUT/SCLK1

H02 GND

H03 AMS2

H04 V_DDINT

H07 ABE3/SDQM3

H08 GND

M10 GND

M11 V_DDINT

M12 V_DDINT

M15 V_DDPCIEXT

M16 PCI_AD25

M17 PCI_AD24

M18 PCI_AD14

N01 SMS2

U14 RSCLK1

C08 TX1

C09 DPLS

C10 TXEN

C11 TDI

C12 BYPASS

C13 GND

H09 V_DDINT

H10 GND

H11 GND

H12 V_DDINT

H15 V_DDPCIEXT

H16 PCI_AD11

N02 DATA0

N03 DATA4

N04 V_DDINT

N15 V_DDINT

N16 PCI_AD29

N17 PCI_AD26

U15 DR1

U16 MOSI0

U17 SCK0

U18 MISO1

V01 N/C

V02 DATA10

REV. A

–41–

ADSP-BF535

Table 30. 260-Ball PBGA Pin Assignment (Numerically by Pin Number) (continued)

Signal

C14 PCI_INTA

C15 PCI_PAR

C16 PCI_DEVSEL

C17 PCI_FRAME

C18 PCI_GNT

D01 AMS1

D02 ADDR25

D03 ADDR19

D04 ADDR14

D05 ADDR10

D06 ADDR4

D07 TMR2

H17 PCI_AD9

H18 PCI_AD7

N18 PCI_AD18

V03 DATA11

V04 DATA17

V05 DATA18

V06 DATA22

V07 DATA26

V08 DATA27

V09 DATA31

V10 PF3/SPI1SEL1/MSEL3

V11 V_SSRTC

V12 PF10/SPI0SEL5

V13 PF14/SPI0SEL7

V14 DR0

V15 TSCLK0

V16 RFS1

P01

P02

P03

P04

P15

P16

P17

P18

R01

R02

R03

R04

R05

R06

R07

SMS1

DATA3

DATA6

V_DDEXT

PCI_AD28

PCI_AD31

PCI_AD27

PCI_AD19

ARDY

DATA5

N/C

DATA12

DATA19

DATA23

DATA29

J01

J02

J03

J04

J07

J08

J09

J10

J11

J12

J15

J16

J17

J18

V_DDEXT

SWE

V_DDEXT

GND

D08 DMNS

D09 CLKIN1

D10 TCK

V_DDPCIEXT

PCI_AD16

PCI_AD13

PCI_AD8

V17 DT1

V18 N/C

D11 TDO

–42–

REV. A

ADSP-BF535

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18

A

B

C

D

E

F

KEY:

V_DDRTC

V_SSRTC

V_DDPLL

V_SSPLL

V_DDINT

V_DDEXT

GND

I/O

G

H

J

V_DDPCIEXT

K

L

M

N

P

R

T

U

V

Figure 25. 260-Ball Metric PBGA Pin Configuration (Top View)

18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

KEY:

V_DDINT

GND

V_DDEXT

V_DDPCIEXT

V_DDPLL

I/O

V_DDRTC

G

H

J

V_SSRTC

V_SSPLL

K

L

M

N

P

R

T

U

V

Figure 26. 260-Ball Metric PBGA Pin Configuration (Bottom View)

REV. A

–43–

ADSP-BF535

OUTLINE DIMENSIONS

19.00 BSC SQ

18 16 14 12 10

17 15 13 11

8

6

4

2

9

7

5

3

1

A

C

E

G

J

B

D

F

BALL A1

INDICATOR

17.05

16.95 SQ

16.85

H

K

M

P

T

17.00

BSC

SQ

L

N

R

U

1.00

BSC

V

TOP VIEW

1.00 BSC

BALL PITCH

DETAIL A

BOTTOM VIEW

2.50

MAX

0.65

0.45

1.22

MAX

NOTES

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. THE ACTUAL POSITION OF THE BALL GRID

IS WITHIN 0.25 MM OF ITS IDEAL POSITION

RELATIVE TO THE PACKAGE EDGES.

3. THE ACTUAL POSITION OF EACH BALL IS

WITHIN 0.10 MM OF ITS IDEAL POSITION RELATIVE

TO THE BALL GRID.

4. CENTER DIMENSIONS ARE NOMINAL.

5. COMPLIANT TO JEDEC REGISTERED OUTLINE

MS-034, VARIATION AAG-1.

0.20

MAX, TYP

0.70

0.60

0.50

0.40

MIN

SEATING

PLANE

BALL DIAMETER

DETAIL A

Figure 27. 260-Ball Metric Plastic Ball Grid Array (PBGA) (B-260)

ORDERING GUIDE

Part Number

Temperature Range (Ambient)

Instruction Rate

Operating Voltage (V)

ADSP-BF535PKB-350

ADSP-BF535PKB-300

ADSP-BF535PBB-300

ADSP-BF535PBB-200

0ºC to +70ºC

–40ºC to +85ºC

350 MHz

300 MHz

200 MHz

1.0 V to 1.6 V internal, 3.3 V I/O

1.0 V to 1.5 V internal, 3.3 V I/O

Revision History

Location

Page

9/04—Data Sheet Changed from REV. 0 to REV. A

Changes to Clock Signals Section ........................................................................................................................ 13

Changes to Recommended Operating Conditions Footnote References ................................................................. 21

Changes to Electrical Characteristics ................................................................................................................... 21

Change to Table 11 ............................................................................................................................................ 24

Change to Figure 11............................................................................................................................................ 27

Change to Figure 12 ........................................................................................................................................... 28

Change to Output Drive Currents Section ............................................................................................................ 36

Replaced Figures 19, 20, and 21 .......................................................................................................................... 36

Changes to Power Dissipation Section ................................................................................................................. 36

Change to Table 26 ............................................................................................................................................ 36

–44–

REV. A


型号：	ADSP-BF535PKB-350
厂家：	ADI
描述：	Blackfin Embedded Processor Blackfin嵌入式处理器
文件：	总44页 (文件大小：1386K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF535PKB-350 [ADI]

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