ADSP-BF542MBBCZ-5M_技术文档

Blackfin

Embedded Processor

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

FEATURES

PERIPHERALS

Up to 600 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs

RISC-like register and instruction model

Wide range of operating voltages and flexible booting

options

High speed USB On-the-Go (OTG) with integrated PHY

SD/SDIO controller

ATA/ATAPI-6 controller

Up to 4 synchronous serial ports (SPORTs)

Up to 3 serial peripheral interfaces (SPI-compatible)

Up to 4 UARTs, two with automatic H/W flow control

Up to 2 CAN (controller area network) 2.0B interfaces

Up to 2 TWI (2-wire interface) controllers

8- or 16-bit asynchronous host DMA interface

Multiple enhanced parallel peripheral interfaces (EPPIs),

supporting ITU-R BT.656 video formats and 18-/24-bit LCD

connections

Media transceiver (MXVR) for connection to a MOST network

Pixel compositor for overlays, alpha blending, and color

conversion

Up to eleven 32-bit timers/counters with PWM support

Real-time clock (RTC) and watchdog timer

Up/down counter with support for rotary encoder

Up to 152 general-purpose I/O (GPIOs)

Programmable on-chip voltage regulator

400-ball CSP_BGA, RoHS compliant package

MEMORY

Up to 324K bytes of on-chip memory comprised of

instruction SRAM/cache; dedicated instruction SRAM; data

SRAM/cache; dedicated data SRAM; scratchpad SRAM

External sync memory controller supporting either DDR

SDRAM or mobile DDR SDRAM

External async memory controller supporting 8-/16-bit async

memories and burst flash devices

NAND flash controller

4 memory-to-memory DMA pairs, 2 with ext. requests

Memory management unit providing memory protection

Code security with Lockbox secure technology and 128-bit

AES/ARC4 data encryption

On-chip PLL capable of 0.5× to 64× frequency multiplication

Debug/JTAG interface

One-time-programmable (OTP) memory

VOLTAGE

REGULATOR

JTAG TEST AND

EMULATION

WATCHDOG

TIMER

CAN (0-1)

RTC

OTP

TWI (0-1)

HOST DMA

UART (0-1)

UART (2-3)

SPI (0-1)

PAB 16

TIMERS(0-10)

INTERRUPTS

B

COUNTER

KEYPAD

L2

SRAM

L1

INSTR ROM

L1

DATA SRAM

INSTR SRAM

SPI (2)

32-BIT DMA

16-BIT DMA

MXVR

DAB1 32

DAB0 16

DCB 32

EAB 64

DEB 32

SPORT (2-3)

SPORT (0-1)

SD / SDIO

USB

EXTERNAL PORT

NOR, DDR, MDDR

BOOT

ROM

ATAPI

EPPI (0-2)

DDR/MDDR

16

ASYNC

16

NAND FLASH

CONTROLLER

PIXEL

COMPOSITOR

Figure 1. ADSP-BF549 Functional Block Diagram

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

TABLE OF CONTENTS

General Description ................................................. 3

Low Power Architecture ......................................... 4

System Integration ................................................ 4

Blackfin Processor Peripherals ................................. 4

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 6

DMA Controllers ................................................ 10

Real-Time Clock ................................................. 11

Watchdog Timer ................................................ 12

Timers ............................................................. 12

Up/Down Counter and Thumbwheel Interface .......... 12

Serial Ports (SPORTs) .......................................... 12

Serial Peripheral Interface (SPI) Ports ...................... 13

UART Ports (UARTs) .......................................... 13

Controller Area Network (CAN) ............................ 13

TWI Controller Interface ...................................... 14

Ports ................................................................ 14

Pixel Compositor (PIXC) ...................................... 14

Enhanced Parallel Peripheral Interface (EPPI) ........... 14

USB On-the-Go Dual-Role Device Controller ............ 15

ATA/ATAPI-6 Interface ....................................... 15

Keypad Interface ................................................. 15

Secure Digital (SD)/SDIO Controller ....................... 16

Code Security .................................................... 16

Media Transceiver MAC Layer (MXVR) .................. 16

Dynamic Power Management ................................ 16

Voltage Regulation .............................................. 18

Clock Signals ..................................................... 18

Booting Modes ................................................... 19

Instruction Set Description .................................... 22

Development Tools .............................................. 23

EZ-KIT Lite Evaluation Board ............................. 23

Designing an Emulator-Compatible Processor Board ... 23

MXVR Board Layout Guidelines ............................. 23

Related Documents .............................................. 24

Lockbox Secure Technology Disclaimer .................... 24

Pin Descriptions .................................................... 25

Specifications ........................................................ 34

Operating Conditions ........................................... 34

Electrical Characteristics ....................................... 36

Absolute Maximum Ratings ................................... 40

ESD Sensitivity ................................................... 41

Package Information ............................................ 41

Timing Specifications ........................................... 42

Output Drive Currents ......................................... 86

Test Conditions .................................................. 88

Capacitive Loading .............................................. 88

Typical Rise and Fall Times ................................... 89

Thermal Characteristics ........................................ 91

400-Ball CSP_BGA Package ...................................... 92

Outline Dimensions ................................................ 98

Surface-Mount Design .......................................... 98

Automotive Products .............................................. 99

Ordering Guide ................................................... 100

REVISION HISTORY

2/10—Rev. B to Rev. C

Added V_IHTWIand V_ILTWIdata to Operating Conditions ...... 34

Added I_OH/I_OLper pin group data to

Absolute Maximum Ratings .................................................... 40

Added Table 23 (Total Current Pin Groups) ........................ 40

Revised all timing diagrams for clarity/consistency in Timing

Specifications ........................................................ 42

Updated specifications (reference PCN 09_0173) in the Clock

and Reset Timing section to accurately describe processor cold-

startup/reset timing.................................................. 42

Added t_SCLKIWand t_SCLKdata to Table 42 (Serial Ports—Internal

Clock) ..................................................................61

Added Figure 34 (Serial Port Start-Up with External Clock and

Frame Sync) and Figure 36 (Serial Ports—Enable and Three-

State) ............................................................................................62

To view product/process change notifications (PCNs) related to

this data sheet revision, please visit the processor's product page

on the www.analog.com website and use the View PCN link.

Added t_SUDTEand t_SUDREdata to Table 41 (Serial Ports—External

Clock) .................................................................. 61

Rev. C

|

Page 2 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

GENERAL DESCRIPTION

The ADSP-BF54x Blackfin^®processors are members of the

Blackfin family of products, incorporating the Analog Devices/

Intel Micro Signal Architecture (MSA). Blackfin processors

combine a dual-MAC state-of-the-art signal processing engine,

the advantages of a clean, orthogonal RISC-like microprocessor

instruction set, and single-instruction, multiple-data (SIMD)

multimedia capabilities into a single instruction-set

architecture.

Specific peripherals for ADSP-BF54x Blackfin processors are

shown in Table 2.

Table 2. Specific Peripherals for ADSP-BF54x Processors

Module

Specific performance, memory configurations, and features of

ADSP-BF54x Blackfin processors are shown in Table 1.

EBIU (async)

NAND flash controller

ATAPI

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

Table 1. ADSP-BF54x Processor Features

Processor

Features

Host DMA port (HOSTDP)

SD/SDIO controller

EPPI0

EPPI1

Lockbox^{® 1}code security

128-bit AES/ ARC4 data encryption

SD/SDIO controller

Pixel compositor

18- or 24-bit EPPI0 with LCD

16-bit EPPI1, 8-bit EPPI2

Host DMA port

1

2

3

4

1

–

2

3

4

1

–

2

3

4

1

–

1

–

2

3

1

–

1

–

1

–

1

2

3

1

8

EPPI2

SPORT0

SPORT1

SPORT2

SPORT3

SPI0

SPI1

NAND flash controller

ATAPI

SPI2

UART0

High Speed USB OTG

Keypad interface

MXVR

UART1

UART2

UART3

CAN ports

High Speed USB OTG

CAN0

TWI ports

SPI ports

CAN1

UART ports

TWI0

SPORTs

TWI1

Up/Down counter

Timers

Timer 0–7

Timer 8–10

Up/Down counter

Keypad interface

MXVR

11 11 11 11

152 152 152 152 152

General-Purpose I/O pins

Memory

Configura-

tions

L1 Instruction SRAM/Cache 16 16 16 16 16

L1 Instruction SRAM

L1 Data SRAM/Cache

L1 Data SRAM

L1 Scratchpad SRAM

L1 ROM²

48 48 48 48 48

32 32 32 32 32

(K Bytes)

GPIOs

4

64 64 64 64 64

L2

128 128 128 64

–

4

L3 Boot ROM²

4

Maximum Core Instruction Rate (MHz) 533 533 600 533 600

¹Lockbox is a registered trademark of Analog Devices, Inc.

²This ROM is not customer-configurable.

Rev. C

|

Page 3 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The ADSP-BF54x Blackfin processors are completely code- and

pin-compatible. They differ only with respect to their perfor-

mance, on-chip memory, and selection of I/O peripherals.

Specific performance, memory, and feature configurations are

shown in Table 1.

memory spaces, including external DDR (either standard or

mobile, depending on the device) and asynchronous memory.

Multiple on-chip buses running at up to 133 MHz provide

enough bandwidth to keep the processor core running along

with activity on all of the on-chip and external peripherals.

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next-generation applications that require RISC-like program-

mability, multimedia support, and leading-edge signal

processing in one integrated package.

The ADSP-BF54x Blackfin processors include an on-chip volt-

age regulator in support of the dynamic power management

capability. The voltage regulator provides a range of core volt-

age levels when supplied from V_DDEXT. The voltage regulator can

be bypassed at the user’s discretion.

LOW POWER ARCHITECTURE

BLACKFIN PROCESSOR CORE

Blackfin processors provide world-class power management

and performance. Blackfin processors are designed in a low

power and low voltage design methodology and feature on-chip

dynamic power management, the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. Reducing both voltage and frequency can result

in a substantial reduction in power consumption as compared

to reducing only the frequency of operation. This translates into

longer battery life for portable appliances.

As shown in Figure 2 on Page 5, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-, 16-, or 32-bit data from the register file.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

SYSTEM INTEGRATION

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ADSP-BF54x Blackfin processors are highly integrated

system-on-a-chip solutions for the next generation of embed-

ded network connected applications. By combining industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a high speed USB OTG (On-the-Go) controller with

integrated PHY, CAN 2.0B controllers, TWI controllers, UART

ports, SPI ports, serial ports (SPORTs), ATAPI controller,

SD/SDIO controller, a real-time clock, a watchdog timer, LCD

controller, and multiple enhanced parallel peripheral interfaces.

The ALUs perform a traditional set of arithmetic and logical

operations on 16- or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations,

16-bit and 8-bit adds with clipping, 8-bit average operations,

and 8-bit subtract/absolute value/accumulate (SAA) operations.

Also provided are the compare/select and vector search

instructions.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero-over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

BLACKFIN PROCESSOR PERIPHERALS

The ADSP-BF54x processors contain a rich set of peripherals

connected to the core via several high bandwidth buses, provid-

ing flexibility in system configuration as well as excellent overall

system performance (see Figure 1 on Page 1). The general-

purpose peripherals include functions such as UARTs, SPI,

TWI, timers with pulse width modulation (PWM) and pulse

measurement capability, general-purpose I/O pins, a real-time

clock, and a watchdog timer. This set of functions satisfies a

wide variety of typical system support needs and is augmented

by the system expansion capabilities of the part. The ADSP-

BF54x processors contain dedicated network communication

modules and high speed serial and parallel ports, an interrupt

controller for flexible management of interrupts from the on-

chip peripherals or external sources, and power management

control functions to tailor the performance and power charac-

teristics of the processor and system to many application

scenarios.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit index, modify,

All of the peripherals, except for general-purpose I/O, CAN,

TWI, real-time clock, and timers, are supported by a flexible

DMA structure. There are also separate memory DMA channels

dedicated to data transfers between the processor's various

Rev. C

|

Page 4 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

length, and base registers (for circular buffering), and eight

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

additional 32-bit pointer registers (for C-style indexed stack

manipulation).

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The memory manage-

ment unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1 32

DA0 32

32

PREG

32

RAB

SD 32

LD1 32

LD0 32

ASTAT

32

SEQUENCER

ALIGN

R7.H

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R7.L

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Rev. C

|

Page 5 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

MEMORY ARCHITECTURE

0xFFFF FFFF

The ADSP-BF54x processors view memory as a single unified

CORE MMR REGISTERS (2M BYTES)

4G byte address space, using 32-bit addresses. All resources,

including internal memory, external memory, and I/O control

registers, occupy separate sections of this common address

space. The memory portions of this address space are arranged

in a hierarchical structure to provide a good cost/performance

balance of some very fast, low-latency on-chip memory as cache

or SRAM, and larger, lower-cost and performance off-chip

memory systems. See Figure 3 on Page 6.

0x

FFE0 0000

SYSTEM MMR REGISTERS (2M BYTES)

RESERVED

0xFFC0 0000

0x

FFB0 1000

SCRATCHPAD SRAM (4K BYTES)

RESERVED

0xFFB0 0000

0xFFA2 4000

0xFFA1 4000

L1 ROM (64K BYTE)

INSTRUCTION SRAM / CACHE (16K BYTES)

RESERVED

0x

FFA1 0000

The on-chip L1 memory system is the highest-performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the external bus interface unit

(EBIU), provides expansion with flash memory, SRAM, and

double-rate SDRAM (standard or mobile DDR), optionally

accessing up to 768M bytes of physical memory.

Most of the ADSP-BF54x Blackfin processors also include an L2

SRAM memory array which provides up to 128K bytes of high

speed SRAM, operating at one half the frequency of the core and

with slightly longer latency than the L1 memory banks (for

information on L2 memory in each processor, see Table 1). The

L2 memory is a unified instruction and data memory and can

hold any mixture of code and data required by the system

design. The Blackfin cores share a dedicated low latency 64-bit

data path port into the L2 SRAM memory.

C000

FFA0

INSTRUCTION BANK B SRAM (16K BYTES)

FFA0 8000

FFA0 0000

INSTRUCTION BANK A SRAM (32K BYTES)

RESERVED

0x

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTES)

DATA BANK B SRAM (16K BYTES)

0x

FF90 4000

FF90 0000

0x

RESERVED

0xFF80 8000

DATA BANK A SRAM / CACHE (16K BYTES)

0x

FF80 4000

FF80 0000

DATA BANK A SRAM (16K BYTES)

RESERVED

0x

0xFEB2 0000

L2 SRAM (128K BYTES)

x

0 FEB0 0000

RESERVED

0xEF00 1000

BOOT ROM (4K BYTES)

0x

EF00 0000

RESERVED

The memory DMA controllers (DMAC1 and DMAC0) provide

high-bandwidth data-movement capability. They can perform

block transfers of code or data between the internal memory

and the external memory spaces.

0x3000 0000

0x2C00 0000

0x2800 0000

0x2400 0000

ASYNC MEMORY BANK 3 (64M BYTES)

ASYNC MEMORY BANK 2 (64M BYTES)

ASYNC MEMORY BANK 1 (64M BYTES)

ASYNC MEMORY BANK 0 (64M BYTES)

Internal (On-Chip) Memory

0x

2000 0000

RESERVED

The ADSP-BF54x processors have several blocks of on-chip

memory providing high bandwidth access to the core.

The first block is the L1 instruction memory, consisting of

64K bytes of SRAM, of which 16K bytes can be configured as a

four-way set-associative cache or as SRAM. This memory is

accessed at full processor speed.

The second on-chip memory block is the L1 data memory, con-

sisting of 64K bytes of SRAM, of which 32K bytes can be

configured as a two-way set-associative cache or as SRAM. This

memory block is accessed at full processor speed.

TOP OF LAST

DDR PAGE

DDR MEM BANK 1 (8M BYTES to 256M BYTES)

DDR MEM BANK 0 (8M BYTES to 256M BYTES)

0000 0000

0x

Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549

Internal/External Memory Map¹

¹ForADSP-BF544processors, L2SRAMis64KBytes(0xFEB0000–0xFEB0FFFF).

For ADSP-BF542 processors, there is no L2 SRAM.

External (Off-Chip) Memory

The third memory block is a 4K byte scratchpad SRAM, which

runs at the same speed as the L1 memories. It is only accessible

as data SRAM and cannot be configured as cache memory.

The fourth memory block is the factory programmed L1

instruction ROM, operating at full processor speed. This ROM

is not customer-configurable.

The fifth memory block is the L2 SRAM, providing up to 128K

bytes of unified instruction and data memory, operating at one

half the frequency of the core.

Finally, there is a 4K byte boot ROM connected as L3 memory.

It operates at full SCLK rate.

Through the external bus interface unit (EBIU), the

ADSP-BF54x Blackfin processors provide glueless connectivity

to external 16-bit wide memories, such as DDR and mobile

DDR SDRAM, SRAM, NOR flash, NAND flash, and FIFO

devices. To provide the best performance, the bus system of the

DDR and mobile DDR interface is completely separate from the

other parallel interfaces. Furthermore, the DDR controller sup-

ports either standard DDR memory or mobile DDR memory.

See the Ordering Guide on Page 100 for details. Throughout

this document, references to “DDR” are intended to cover both

the standard and mobile DDR standards.

Rev. C

|

Page 6 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The DDR memory controller can gluelessly manage up to two

• Support for SLC (single level cell) NAND flash devices

unlimited in size, with page sizes of 256 bytes and 512

bytes. Larger page sizes can be supported in software.

• The ability to release external bus interface pins during

long accesses.

• Support for internal bus requests of 16 bits or 32 bits.

• A DMA engine to transfer data between internal memory

and a NAND flash device.

banks of double-rate synchronous dynamic memory (DDR and

mobile DDR SDRAM). The 16-bit interface operates at the

SCLK frequency, enabling a maximum throughput of 532M

bytes/s. The DDR and mobile DDR controller is augmented

with a queuing mechanism that performs efficient bursts into

the DDR and mobile DDR. The controller is an industry stan-

dard DDR and mobile DDR SDRAM controller with each bank

supporting from 64M bit to 512M bit device sizes and 4-, 8-, or

16-bit widths. The controller supports up to 256M bytes per

external bank. With 2 external banks, the controller supports up

to 512M bytes total. Each bank is independently programmable

and is contiguous with adjacent banks regardless of the sizes of

the different banks or their placement.

One-Time-Programmable Memory

The ADSP-BF54x Blackfin processors have 64K bits of one-

time-programmable (OTP) non-volatile memory that can be

programmed by the developer only one time. It includes the

array and logic to support read access and programming. Addi-

tionally, its pages can be write protected.

OTP enables developers to store both public and private data

on-chip. In addition to storing public and private key data for

applications requiring security, it also allows developers to store

completely user-definable data such as a customer ID, product

ID, or a MAC address. By using this feature, generic parts can be

shipped, which are then programmed and protected by the

developer within this non-volatile memory. The OTP memory

can be accessed through an API provided by the on-chip ROM.

Traditional 16-bit asynchronous memories, such as SRAM,

EPROM, and flash devices, can be connected to one of the four

64M byte asynchronous memory banks, represented by four

memory select strobes. Alternatively, these strobes can function

as bank-specific read or write strobes preventing further glue

logic when connecting to asynchronous FIFO devices. See the

Ordering Guide on Page 100 for a list of specific products that

provide support for DDR memory.

In addition, the external bus can connect to advanced flash

device technologies, such as:

• Page-mode NOR flash devices

• Synchronous burst-mode NOR flash devices

• NAND flash devices

Customers should consult the Ordering Guide when selecting a

specific ADSP-BF54x component for the intended application.

Products that provide support for mobile DDR memory are

noted in the ordering guide footnotes.

I/O Memory Space

The ADSP-BF54x Blackfin processors do not define a separate

I/O space. All resources are mapped through the flat 32-bit

address space. On-chip I/O devices have their control registers

mapped into memory-mapped registers (MMRs) at addresses

near the top of the 4G byte address space. These are separated

into two smaller blocks, one containing the control MMRs for

all core functions and the other containing the registers needed

for setup and control of the on-chip peripherals outside of the

core. The MMRs are accessible only in supervisor mode and

appear as reserved space to on-chip peripherals.

NAND Flash Controller (NFC)

The ADSP-BF54x Blackfin processors provide a NAND Flash

Controller (NFC) as part of the external bus interface. NAND

flash devices provide high-density, low-cost memory. However,

NAND flash devices also have long random access times, invalid

blocks, and lower reliability over device lifetimes. Because of

this, NAND flash is often used for read-only code storage. In

this case, all DSP code can be stored in NAND flash and then

transferred to a faster memory (such as DDR or SRAM) before

execution. Another common use of NAND flash is for storage

of multimedia files or other large data segments. In this case, a

software file system may be used to manage reading and writing

of the NAND flash device. The file system selects memory seg-

ments for storage with the goal of avoiding bad blocks and

equally distributing memory accesses across all address loca-

tions. Hardware features of the NFC include:

Booting

The ADSP-BF54x Blackfin processors contain a small on-chip

boot kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF54x Blackfin processors are configured

to boot from boot ROM memory space, the processor starts exe-

cuting from the on-chip boot ROM. For more information, see

Booting Modes on Page 19.

Event Handling

The event controller on the ADSP-BF54x Blackfin processors

handles all asynchronous and synchronous events to the proces-

sors. The ADSP-BF54x Blackfin processors provide event

handling that supports both nesting and prioritization. Nesting

allows multiple event service routines to be active simulta-

neously. Prioritization ensures that servicing of a

• Support for page program, page read, and block erase of

NAND flash devices, with accesses aligned to page

boundaries.

• Error checking and correction (ECC) hardware that facili-

tates error detection and correction.

• A single 8-bit or 16-bit external bus interface for com-

mands, addresses, and data.

Rev. C

|

Page 7 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

higher-priority event takes precedence over servicing of a lower-

priority event. The controller provides support for five different

types of events:

• Emulation. An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

Table 3. Core Event Controller (CEC)

Priority

(0 is Highest)

0

Event Class

Emulation/Test Control EMU

Reset RST

Nonmaskable Interrupt NMI

EVT Entry

1

2

• Reset. This event resets the processor.

3

Exception

EVX

• Non-maskable interrupt (NMI). The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Exceptions. Events that occur synchronously to program

flow (that is, the exception is taken before the instruction is

allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

• Interrupts. Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

System Interrupt Controller (SIC)

The ADSP-BF54x Blackfin processor event controller consists

of two stages, the core event controller (CEC) and the system

interrupt controller (SIC). The core event controller works with

the system interrupt controller to prioritize and control all sys-

tem events. Conceptually, interrupts from the peripherals enter

into the SIC and are then routed directly into the general-pur-

pose interrupts of the CEC.

The system interrupt controller provides the mapping and rout-

ing of events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF54x Blackfin processors provide a

default mapping, the user can alter the mappings and priorities

of interrupt events by writing the appropriate values into the

interrupt assignment registers (SIC_IARx). Table 4 describes

the inputs into the SIC and the default mappings into the CEC.

Core Event Controller (CEC)

Table 4. System Interrupt Controller (SIC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest-priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF54x Blackfin processors.

Table 3 describes the inputs to the CEC, identifies their names

in the event vector table (EVT), and lists their priorities.

Peripheral IRQ

Source

IRQ

GP IRQ

Core

ID (at Reset) IRQ ID

PLL Wakeup IRQ

0

1

IVG7

IVG8

IVG9

IVG10

0

1

2

3

DMAC0 Status (Generic)

EPPI0 Error IRQ

2

SPORT0 Error IRQ

3

SPORT1 Error IRQ

4

SPI0 Status IRQ

5

UART0 Status IRQ

6

Real-Time Clock IRQ

DMA12 IRQ (EPPI0)

DMA0 IRQ (SPORT0 RX)

DMA1 IRQ (SPORT0 TX)

DMA2 IRQ (SPORT1 RX)

DMA3 IRQ (SPORT1 TX)

DMA4 IRQ (SPI0)

7

8

9

10

11

12

13

Rev. C

|

Page 8 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 4. System Interrupt Controller (SIC) (Continued)

Peripheral IRQ

Source

IRQ

GP IRQ

Core

Peripheral IRQ

Source

IRQ

GP IRQ

Core

ID (at Reset) IRQ ID

DMA6 IRQ (UART0 RX)

DMA7 IRQ (UART0 TX)

Timer 8 IRQ

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

IVG10

IVG11

IVG12

IVG13

IVG7

3

4

5

6

0

2

3

4

6

4

MXVR Asynchronous Packet IRQ

EPPI1 Error IRQ

EPPI2 Error IRQ

UART3 Status IRQ

Host DMA Status

Reserved

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

IVG11

IVG7

4

0

1

4

IVG7

Timer 9 IRQ

IVG7

Timer 10 IRQ

IVG7

Pin IRQ 0 (PINT0)

IVG7

Pin IRQ 1 (PINT1)

Pixel Compositor (PIXC) Status IRQ

NFC Status IRQ

ATAPI Status IRQ

CAN1 Status IRQ

DMAR0 Block IRQ

DMAR1 Block IRQ

DMAR0 Overflow Error IRQ

DMAR1 Overflow Error IRQ

DMA15 IRQ (PIXC IN0)

DMA16 IRQ (PIXC IN1)

DMA17 IRQ (PIXC OUT)

DMA22 IRQ (SDH/NFC)

Counter (CNT) IRQ

Keypad (KEY) IRQ

CAN1 RX IRQ

IVG7

MDMA Stream 0 IRQ

MDMA Stream 1 IRQ

Software Watchdog Timer IRQ

DMAC1 Status (Generic)

SPORT2 Error IRQ

IVG7

SPORT3 Error IRQ

IVG7

MXVR Synchronous Data IRQ

SPI1 Status IRQ

IVG7

IVG8

SPI2 Status IRQ

IVG7

IVG8

UART1 Status IRQ

IVG7

IVG8

UART2 Status IRQ

IVG7

IVG8

CAN0 Status IRQ

IVG7

IVG8

DMA18 IRQ (SPORT2 RX)

DMA19 IRQ (SPORT2 TX)

DMA20 IRQ (SPORT3 RX)

DMA21 IRQ (SPORT3 TX)

DMA13 IRQ (EPPI1)

DMA14 IRQ (EPPI2, Host DMA)

DMA5 IRQ (SPI1)

IVG9

IVG8

IVG9

IVG11

IVG9

CAN1 TX IRQ

IVG9

SDH Mask 0 IRQ

SDH Mask 1 IRQ

Reserved

IVG9

IVG10

IVG11

IVG13

IVG11

USB_INT0 IRQ

DMA23 IRQ (SPI2)

USB_INT1 IRQ

DMA8 IRQ (UART1 RX)

DMA9 IRQ (UART1 TX)

DMA10 IRQ (ATAPI RX)

DMA11 IRQ (ATAPI TX)

TWI0 IRQ

USB_INT2 IRQ

USB_DMAINT IRQ

OTPSEC IRQ

Reserved

TWI1 IRQ

Reserved

CAN0 Receive IRQ

CAN0 Transmit IRQ

MDMA Stream 2 IRQ

MDMA Stream 3 IRQ

MXVR Status IRQ

Reserved

Timer 0 IRQ

Timer 1 IRQ

MXVR Control Message IRQ

Timer 2 IRQ

Rev. C

|

Page 9 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 4. System Interrupt Controller (SIC) (Continued)

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

Peripheral IRQ

Source

IRQ

GP IRQ

Core

ID (at Reset) IRQ ID

• SIC interrupt wakeup enable registers (SIC_IWRx). By

enabling the corresponding bit in this register, a peripheral

can be configured to wake up the processor, should the

core be idled or in Sleep mode when the event is generated.

(For more information, see Dynamic Power Management

on Page 16.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Timer 3 IRQ

89

90

91

92

93

94

95

IVG11

IVG12

4

5

Timer 4 IRQ

Timer 5 IRQ

Timer 6 IRQ

Timer 7 IRQ

Pin IRQ 2 (PINT2)

Pin IRQ 3 (PINT3)

Event Control

The ADSP-BF54x Blackfin processors provide the user with a

very flexible mechanism to control the processing of events. In

the CEC, three registers are used to coordinate and control

events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT). The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may be written only when its corresponding IMASK bit

is cleared.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected. (Detection requires two core clock cycles.) The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC recognizes and queues the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

DMA CONTROLLERS

• CEC interrupt mask register (IMASK). The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and is processed by the CEC when asserted. A

cleared bit in the IMASK register masks the event, prevent-

ing the processor from servicing the event even though the

event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. Note that

general-purpose interrupts can be globally enabled and dis-

abled with the STI and CLI instructions, respectively.

• CEC interrupt pending register (IPEND). The IPEND reg-

ister keeps track of all nested events. A set bit in the IPEND

register indicates that the event is currently active or nested

at some level. This register is updated automatically by the

controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 4 on Page 8.

• SIC interrupt mask registers (SIC_IMASKx). These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in a register, that periph-

eral event is unmasked and is processed by the system

when asserted. A cleared bit in the register masks the

peripheral event, preventing the processor from servicing

the event.

ADSP-BF54x Blackfin processors have multiple, independent

DMA channels that support automated data transfers with min-

imal overhead for the processor core. DMA transfers can occur

between the ADSP-BF54x processors’ internal memories and

any of the DMA-capable peripherals. Additionally, DMA trans-

fers can be accomplished between any of the DMA-capable

peripherals and external devices connected to the external

memory interfaces, including DDR and asynchronous memory

controllers.

While the USB controller and MXVR have their own dedicated

DMA controllers, the other on-chip peripherals are managed by

two centralized DMA controllers, called DMAC1 (32-bit) and

DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA

controller manages 12 independent peripheral DMA channels,

as well as two independent memory DMA streams. The

DMAC1 controller masters high-bandwidth peripherals over a

dedicated 32-bit DMA access bus (DAB32). Similarly, the

DMAC0 controller masters most serial interfaces over the 16-bit

DAB16 bus. Individual DMA channels have fixed access prior-

ity on the DAB buses. DMA priority of peripherals is managed

by a flexible peripheral-to-DMA channel assignment scheme.

All four DMA controllers use the same 32-bit DCB bus to

exchange data with L1 memory. This includes L1 ROM, but

excludes scratchpad memory. Fine granulation of L1 memory

and special DMA buffers minimize potential memory conflicts

when the L1 memory is accessed simultaneously by the core.

Similarly, there are dedicated DMA buses between the external

bus interface unit (EBIU) and the three DMA controllers

(DMAC1, DMAC0, and USB) that arbitrate DMA accesses to

external memories and the boot ROM.

• SIC interrupt status registers (SIC_ISRx). As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

Rev. C

|

Page 10 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The ADSP-BF54x Blackfin processors’ DMA controllers sup-

configuration words in order to send/receive data to any valid

internal or external memory location. The host DMA port con-

troller includes the following features:

• Allows an external master to configure DMA read/write

data transfers and read port status

• Uses a flexible asynchronous memory protocol for its

external interface

• Allows an 8- or 16-bit external data interface to the host

device

port both 1-dimensional (1D) and 2-dimensional (2D) DMA

transfers. DMA transfer initialization can be implemented from

registers or from sets of parameters called descriptor blocks.

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

• Supports half-duplex operation

Examples of DMA types supported by the ADSP-BF54x

Blackfin processors’ DMA controllers include:

• A single, linear buffer that stops upon completion

• Supports little/big endian data transfers

• Acknowledge mode allows flow control on host

transactions

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• Interrupt mode guarantees a burst of FIFO depth host

transactions

• 1D or 2D DMA using a linked list of descriptors

• 2D DMA using an array of descriptors, specifying only the

base DMA address within a common page

REAL-TIME CLOCK

The ADSP-BF54x Blackfin processors’ real-time clock (RTC)

provides a robust set of digital watch features, including current

time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz

crystal external to the ADSP-BF54x Blackfin processors. The

RTC peripheral has dedicated power supply pins so that it can

remain powered up and clocked even when the rest of the pro-

cessor is in a low-power state. The RTC provides several

programmable interrupt options, including interrupt per sec-

ond, minute, hour, or day clock ticks, interrupt on

programmable stopwatch countdown, or interrupt at a pro-

grammed alarm time.

The 32.768 kHz input clock frequency is divided down to a 1 Hz

signal by a prescaler. The counter function of the timer consists

of four counters: a 60-second counter, a 60-minute counter, a

24-hour counter, and a 32,768-day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms. The first alarm is

for a time of day. The second alarm is for a day and time of

that day.

The stopwatch function counts down from a programmed value

with one-second resolution. When the stopwatch is enabled and

the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the

ADSP-BF54x processor from sleep mode upon generation of

any RTC wakeup event. Additionally, an RTC wakeup event can

wake up the ADSP-BF54x processors from deep sleep mode,

and it can wake up the on-chip internal voltage regulator from

the hibernate state.

In addition to the dedicated peripheral DMA channels, the

DMAC1 and DMAC0 controllers each feature two memory

DMA channel pairs for transfers between the various memories

of the ADSP-BF54x Blackfin processors. This enables transfers

of blocks of data between any of the memories—including

external DDR, ROM, SRAM, and flash memory—with minimal

processor intervention. Like peripheral DMAs, memory DMA

transfers can be controlled by a very flexible descriptor-based

methodology or by a standard register-based autobuffer

mechanism.

The memory DMA channels of the DMAC1 controller

(MDMA2 and MDMA3) can be controlled optionally by the

external DMA request input pins. When used in conjunction

with the External Bus Interface Unit (EBIU), this handshaked

memory DMA (HMDMA) scheme can be used to efficiently

exchange data with block-buffered or FIFO-style devices con-

nected externally. Users can select whether the DMA request

pins control the source or the destination side of the memory

DMA. It allows control of the number of data transfers for

memory DMA. The number of transfers per edge is program-

mable. This feature can be programmed to allow memory DMA

to have an increased priority on the external bus relative to the

core.

Host DMA Port Interface

The host DMA port (HOSTDP) facilitates a host device external

to the ADSP-BF54x Blackfin processors to be a DMA master

and transfer data back and forth. The host device always masters

the transactions, and the processor is always a DMA slave

device.

The HOSTDP is enabled through the peripheral access bus.

Once the port has been enabled, the transactions are controlled

by the external host. The external host programs standard DMA

Rev. C

|

Page 11 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 4.

The timer units can be used in conjunction with the four

UARTs and the CAN controllers to measure the width of the

pulses in the data stream to provide a software auto-baud detect

function for the respective serial channels.

The timers can generate interrupts to the processor core, pro-

viding periodic events for synchronization to either the system

clock or to a count of external signals.

In addition to the general-purpose programmable timers,

another timer is also provided by the processor core. This extra

timer is clocked by the internal processor clock and is typically

used as a system tick clock for generation of periodic operating

system interrupts.

RTXI

RTXO

R1

X1

C1

C2

SUGGESTED COMPONENTS:

ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 M:

UP/DOWN COUNTER AND THUMBWHEEL

INTERFACE

A 32-bit up/down counter is provided that can sense the 2-bit

quadrature or binary codes typically emitted by industrial drives

or manual thumb wheels. The counter can also operate in

general-purpose up/down count modes. Then count direction is

either controlled by a level-sensitive input pin or by two edge

detectors.

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 4. External Components for RTC

WATCHDOG TIMER

A third input can provide flexible zero marker support and can

alternatively be used to input the push-button signal of thumb

wheels. All three pins have a programmable debouncing circuit.

An internal signal forwarded to the timer unit enables one timer

to measure the intervals between count events. Boundary regis-

ters enable auto-zero operation or simple system warning by

interrupts when programmable count values are exceeded.

The ADSP-BF54x processors include a 32-bit timer that can be

used to implement a software watchdog function. A software

watchdog can improve system reliability by forcing the proces-

sor to a known state through generation of a hardware reset,

non-maskable interrupt (NMI), or general-purpose interrupt if

the timer expires before being reset by software. The program-

mer initializes the count value of the timer, enables the

appropriate interrupt, and then enables the timer. Thereafter,

the software must reload the counter before it counts to zero

from the programmed value. This protects the system from

remaining in an unknown state where software, which would

normally reset the timer, has stopped running due to an external

noise condition or software error.

SERIAL PORTS (SPORTS)

The ADSP-BF54x Blackfin processors incorporate up to four

dual-channel synchronous serial ports (SPORT0, SPORT1,

SPORT2, and SPORT3) for serial and multiprocessor commu-

nications. The SPORTs support the following features:

• I²S capable operation.

• Bidirectional operation. Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling up to eight

channels of I²S stereo audio.

• Buffered (8-deep) transmit and receive ports. Each port has

a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

• Clocking. Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

• Word length. Each SPORT supports serial data words from

3 to 32 bits in length, transferred most-significant-bit first

or least-significant-bit first.

• Framing. Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF54x processors’ peripher-

als. After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

watchdog timer control register.

The timer is clocked by the system clock (SCLK) at a maximum

frequency of f_SCLK

.

TIMERS

There are up to two timer units in the ADSP-BF54x Blackfin

processors. One unit provides eight general-purpose program-

mable timers, and the other unit provides three. Each timer has

an external pin that can be configured either as a pulse width

modulator (PWM) or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input on the TMRx pins, an external clock

TMRCLK input pin, or to the internal SCLK.

Rev. C

|

Page 12 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

• Companding in hardware. Each SPORT can perform

includes support for five to eight data bits, one or two stop bits,

and none, even, or odd parity. Each UART port supports two

modes of operation:

• PIO (programmed I/O). The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA (direct memory access). The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. Each UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates. Flexi-

ble interrupt timing options are available on the transmit

side.

Each UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/1,048,576) to

(f_SCLK) bits per second.

• Supporting data formats from seven to 12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• DMA operations with single-cycle overhead. Each SPORT

can receive and transmit multiple buffers of memory data

automatically. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

• Interrupts. Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

• Multichannel capability. Each SPORT supports 128 chan-

nels out of a 1024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF54x Blackfin processors have up to three SPI-

compatible ports that allow the processor to communicate with

multiple SPI-compatible devices.

Each SPI port uses three pins for transferring data: two data pins

(master output slave input, SPIxMOSI, and master input-slave

output, SPIxMISO) and a clock pin (serial clock, SPIxSCK). An

SPI chip select input pin (SPIxSS) lets other SPI devices select

the processor, and three SPI chip select output pins per SPI port

SPIxSELy let the processor select other SPI devices. The SPI

select pins are reconfigured general-purpose I/O pins. Using

these pins, the SPI ports provide a full-duplex, synchronous

serial interface, which supports both master/slave modes and

multimaster environments.

The SPI port’s baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. The

SPI’s DMA controller can only service unidirectional accesses at

any given time.

The UART port’s clock rate is calculated as

f

SCLK

-----------------------------------------------------------------------------

UART Clock Rate =

(1 – EDBO)

16

× UART_Divisor

Where the 16-bit UART divisor comes from the UARTx_DLH

register (most significant 8 bits) and UARTx_DLL register (least

significant eight bits), and the EDBO is a bit in the

UARTx_GCTL register.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

UART1 and UART3 feature a pair of UARTxRTS (request to

send) and UARTxCTS (clear to send) signals for hardware flow

purposes. The transmitter hardware is automatically prevented

from sending further data when the UARTxCTS input is de-

asserted. The receiver can automatically de-assert its

UARTxRTS output when the enhanced receive FIFO exceeds a

certain high-water level. The capabilities of the UARTs are fur-

ther extended with support for the Infrared Data Association

(IrDA®) Serial Infrared Physical Layer Link Specification (SIR)

protocol.

The SPI port’s clock rate is calculated as

f

SCLK

-----------------------------------

SPI Clock Rate =

2 × SPI_BAUD

Where the 16-bit SPI_BAUD register contains a value of

2 to 65,535.

During transfers, the SPI port transmits and receives simulta-

neously by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

CONTROLLER AREA NETWORK (CAN)

The ADSP-BF54x Blackfin processors offer up to two CAN con-

trollers that are communication controllers that implement the

controller area network (CAN) 2.0B (active) protocol. This pro-

tocol is an asynchronous communications protocol used in both

industrial and automotive control systems. The CAN protocol is

well suited for control applications due to its capability to com-

municate reliably over a network since the protocol

UART PORTS (UARTS)

The ADSP-BF54x Blackfin processors provide up to four full-

duplex universal asynchronous receiver/transmitter (UART)

ports. Each UART port provides a simplified UART interface to

other peripherals or hosts, supporting full-duplex, DMA-sup-

ported, asynchronous transfers of serial data. A UART port

incorporates CRC checking, message error tracking, and fault

node confinement.

Rev. C

|

Page 13 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The ADSP-BF54x Blackfin processors’ CAN controllers offer

the following features:

• 32 mailboxes (8 receive only, 8 transmit only, 16 config-

urable for receive or transmit).

• Dedicated acceptance masks for each mailbox.

• Additional data filtering on first two bytes.

• Support for both the standard (11-bit) and extended (29-

bit) identifier (ID) message formats.

• Support for remote frames.

• Active or passive network support.

• CAN wakeup from hibernation mode (lowest static power

consumption mode).

General-Purpose I/O (GPIO)

Every pin in Port A to Port J can function as a GPIO pin, result-

ing in a GPIO pin count up to 154. While it is unlikely that all

GPIO pins will be used in an application, as all pins have multi-

ple functions, the richness of GPIO functionality guarantees

unrestrictive pin usage. Every pin that is not used by any func-

tion can be configured in GPIO mode on an individual basis.

After reset, all pins are in GPIO mode by default. Since neither

GPIO output nor input drivers are active by default, unused

pins can be left unconnected. GPIO data and direction control

registers provide flexible write-one-to-set and write-one-to-

clear mechanisms so that independent software threads do not

need to protect against each other because of expensive read-

modify-write operations when accessing the same port.

• Interrupts, including: TX complete, RX complete, error

and global.

Pin Interrupts

Every port pin on ADSP-BF54x Blackfin processors can request

interrupts in either an edge-sensitive or a level-sensitive manner

with programmable polarity. Interrupt functionality is decou-

pled from GPIO operation. Four system-level interrupt

channels (PINT0, PINT1, PINT2 and PINT3) are reserved for

this purpose. Each of these interrupt channels can manage up to

32 interrupt pins. The assignment from pin to interrupt is not

performed on a pin-by-pin basis. Rather, groups of eight pins

(half ports) can be flexibly assigned to interrupt channels.

Every pin interrupt channel features a special set of 32-bit mem-

ory-mapped registers that enables half-port assignment and

interrupt management. This not only includes masking, identi-

fication, and clearing of requests, it also enables access to the

respective pin states and use of the interrupt latches regardless

of whether the interrupt is masked or not. Most control registers

feature multiple MMR address entries to write-one-to-set or

write-one-to-clear them individually.

The electrical characteristics of each network connection are

very demanding, so the CAN interface is typically divided into

two parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

ADSP-BF54x Blackfin processors’ CAN module represents only

the controller part of the interface. The controller interface sup-

ports connection to 3.3 V high speed, fault-tolerant, single-wire

transceivers.

An additional crystal is not required to supply the CAN clock, as

the CAN clock is derived from the processor system clock

(SCLK) through a programmable divider.

TWI CONTROLLER INTERFACE

The ADSP-BF54x Blackfin processors include up to two 2-wire

interface (TWI) modules for providing a simple exchange

method of control data between multiple devices. The modules

are compatible with the widely used I²C bus standard. The TWI

modules offer the capabilities of simultaneous master and slave

operation and support for both 7-bit addressing and multime-

dia data arbitration. Each TWI interface uses two pins for

transferring clock (SCLx) and data (SDAx), and supports the

protocol at speeds up to 400K bits/sec. The TWI interface pins

are compatible with 5 V logic levels.

Additionally, the ADSP-BF54x Blackfin processors’ TWI mod-

ules are fully compatible with serial camera control bus (SCCB)

functionality for easier control of various CMOS camera sensor

devices.

PIXEL COMPOSITOR (PIXC)

The pixel compositor (PIXC) provides image overlays with

transparent-color support, alpha blending, and color space con-

version capabilities for output to TFT LCDs and NTSC/PAL

video encoders. It provides all of the control to allow two data

streams from two separate data buffers to be combined,

blended, and converted into appropriate forms for both LCD

panels and digital video outputs. The main image buffer pro-

vides the basic background image, which is presented in the

data stream. The overlay image buffer allows the user to add

multiple foreground text, graphics, or video objects on top of

the main image or video data stream.

PORTS

Because of their rich set of peripherals, the ADSP-BF54x

Blackfin processors group the many peripheral signals to ten

ports—referred to as Port A to Port J. Most ports contain 16

pins, though some have fewer. Many of the associated pins are

shared by multiple signals. The ports function as multiplexer

controls. Every port has its own set of memory-mapped regis-

ters to control port muxing and GPIO functionality.

ENHANCED PARALLEL PERIPHERAL INTERFACE

(EPPI)

The ADSP-BF54x Blackfin processors provide up to three

enhanced parallel peripheral interfaces (EPPIs), supporting data

widths up to 24 bits. The EPPI supports direct connection to

TFT LCD panels, parallel analog-to-digital and digital-to-ana-

log converters, video encoders and decoders, image sensor

modules and other general-purpose peripherals.

Rev. C

|

Page 14 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The following features are supported in the EPPI module:

• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,

16 bits, 18 bits, and 24 bits per clock.

• Bidirectional and half-duplex port.

• Clock can be provided externally or can be generated

internally.

• Various framed and non-framed operating modes. Frame

syncs can be generated internally or can be supplied by an

external device.

• Various general-purpose modes with zero to three frame

syncs for both receive and transmit directions.

• ITU-656 status word error detection and correction for

ITU-656 receive modes.

• ITU-656 preamble and status word decode.

The USB clock (USB_XI) is provided through a dedicated exter-

nal crystal or crystal oscillator. See Table 62 for related timing

requirements. If using a fundamental mode crystal to provide

the USB clock, connect the crystal between USB_XI and

USB_XO with a circuit similar to that shown in Figure 7. Use a

parallel-resonant, fundamental mode, microprocessor-grade

crystal. If a third-overtone crystal is used, follow the circuit

guidelines outlined in Clock Signals on Page 18 for third-over-

tone crystals.

The USB On-the-Go dual-role device controller includes a

Phase Locked Loop with programmable multipliers to generate

the necessary internal clocking frequency for USB. The multi-

plier value should be programmed based on the USB_XI clock

frequency to achieve the necessary 480 MHz internal clock for

USB high speed operation. For example, for a USB_XI crystal

frequency of 24 MHz, the USB_PLLOSC_CTRL register should

be programmed with a multiplier value of 20 to generate a 480

MHz internal clock.

• Three different modes for ITU-656 receive modes: active

video only, vertical blanking only, and entire field mode.

ATA/ATAPI-6 INTERFACE

• Horizontal and vertical windowing for GP 2 and 3 frame

sync modes.

• Optional packing and unpacking of data to/from 32 bits

from/to 8, 16 and 24 bits. If packing/unpacking is enabled,

endianness can be changed to change the order of pack-

ing/unpacking of bytes/words.

• Optional sign extension or zero fill for receive modes.

• During receive modes, alternate even or odd data samples

can be filtered out.

• Programmable clipping of data values for 8-bit transmit

modes.

• RGB888 can be converted to RGB666 or RGB565 for trans-

mit modes.

The ATAPI interface connects to CD/DVD and HDD drives

and is ATAPI-6 compliant. The controller implements the

peripheral I/O mode, the multi-DMA mode, and the Ultra

DMA mode. The DMA modes enable faster data transfer and

reduced host management. The ATAPI controller supports

PIO, multi-DMA, and ultra DMA ATAPI accesses. Key features

include:

• Supports PIO modes 0, 1, 2, 3, 4

• Supports multiword DMA modes 0, 1, 2

• Supports ultra DMA modes 0, 1, 2, 3, 4, 5 (up to UDMA

100)

• Programmable timing for ATA interface unit

• Supports CompactFlash cards using true IDE mode

• Various de-interleaving/interleaving modes for receiv-

ing/transmitting 4:2:2 YCrCb data.

• FIFO watermarks and urgent DMA features.

• Clock gating by an external device asserting the clock gat-

ing control signal.

• Configurable LCD data enable (DEN) output available on

Frame Sync 3.

By default, the ATAPI_A0-2 address signals and the

ATAPI_D0-15 data signals are shared on the asynchronous

memory interface with the asynchronous memory and NAND

flash controllers. The data and address signals can be remapped

to GPIO ports F and G, respectively, by setting

PORTF_MUX[1:0] to b#01.

KEYPAD INTERFACE

USB ON-THE-GO DUAL-ROLE DEVICE

CONTROLLER

The keypad interface is a 16-pin interface module that is used to

detect the key pressed in a 8 × 8 (maximum) keypad matrix. The

size of the input keypad matrix is programmable. The interface

is capable of filtering the bounce on the input pins, which is

common in keypad applications. The width of the filtered

bounce is programmable. The module is capable of generating

an interrupt request to the core once it identifies that any key

has been pressed.

The interface supports a press-release-press mode and infra-

structure for a press-hold mode. The former mode identifies a

press, release and press of a key as two consecutive presses of the

same key, whereas the latter mode checks the input key’s state in

periodic intervals to determine the number of times the same

The USB OTG dual-role device controller (USBDRC) provides

a low-cost connectivity solution for consumer mobile devices

such as cell phones, digital still cameras, and MP3 players,

allowing these devices to transfer data using a point-to-point

USB connection without the need for a PC host. The USBDRC

module can operate in a traditional USB peripheral-only mode

as well as the host mode presented in the On-the-Go (OTG)

supplement to the USB 2.0 specification. In host mode, the USB

module supports transfers at high speed (480 Mbps), full speed

(12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only

mode supports the high and full speed transfer rates.

Rev. C

|

Page 15 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

key is meant to be pressed. It is possible to detect when multiple

keys are pressed simultaneously and to provide limited key reso-

lution capability when this happens.

Interrupts are generated when a user-defined amount of syn-

chronous data has been sent or received by the processor or

when asynchronous packets or control messages have been sent

or received.

SECURE DIGITAL (SD)/SDIO CONTROLLER

The SD/SDIO controller is a serial interface that stores data at a

data rate of up to 10M bytes per second using a 4-bit data line.

The SD/SDIO controller supports the SD memory mode only.

The interface supports all the power modes and performs error

checking by CRC.

The MXVR peripheral can wake up the ADSP-BF549 Blackfin

processor from sleep mode when a wakeup preamble is received

over the network or based on any other MXVR interrupt event.

Additionally, detection of network activity by the MXVR can be

used to wake up the ADSP-BF549 Blackfin processor from the

hibernate state. These features allow the ADSP-BF549 processor

to operate in a low-power state when there is no network activ-

ity or when data is not currently being received or transmitted

by the MXVR.

The MXVR clock is provided through a dedicated external crys-

tal or crystal oscillator. The frequency of the external crystal or

crystal oscillator can be 256 Fs, 384 Fs, 512 Fs, or 1024 Fs for

Fs = 38 kHz, 44.1 kHz, or 48 kHz. If using a crystal to provide

the MXVR clock, use a parallel-resonant, fundamental mode,

microprocessor-grade crystal.

CODE SECURITY

An OTP/security system, consisting of a blend of hardware and

software, provides customers with a flexible and rich set of code

security features with Lockbox^®secure technology. Key features

include:

• OTP memory

• Unique chip ID

• Code authentication

• Secure mode of operation

The security scheme is based upon the concept of authentica-

tion of digital signatures using standards-based algorithms and

provides a secure processing environment in which to execute

code and protect assets. See Lockbox Secure Technology Dis-

claimer on Page 24.

DYNAMIC POWER MANAGEMENT

The ADSP-BF54x Blackfin processors provide five operating

modes, each with a different performance/power profile. In

addition, dynamic power management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

of the ADSP-BF54x Blackfin processors’ peripherals also

reduces power consumption. See Table 5 for a summary of the

power settings for each mode.

MEDIA TRANSCEIVER MAC LAYER (MXVR)

The ADSP-BF549 Blackfin processors provide a media trans-

ceiver (MXVR) MAC layer, allowing the processor to be

connected directly to a MOST^®¹network through an FOT. See

Figure 5 on Page 17 for an example of a MXVR MOST

connection.

The MXVR is fully compatible with industry-standard standal-

one MOST controller devices, supporting 22.579 Mbps or

24.576 Mbps data transfer. It offers faster lock times, greater jit-

ter immunity, and a sophisticated DMA scheme for data

transfers. The high speed internal interface to the core and L1

memory allows the full bandwidth of the network to be utilized.

The MXVR can operate as either the network master or as a net-

work slave.

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing the capability to run at the maximum operational fre-

quency. This is the power-up default execution state in which

maximum performance can be achieved. The processor core

and all enabled peripherals run at full speed.

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. DMA

access is available to appropriately configured L1 memories.

The MXVR supports synchronous data, asynchronous packets,

and control messages using dedicated DMA channels that oper-

ate autonomously from the processor core moving data to and

from L1 and/or L2 memory. Synchronous data is transferred to

or from the synchronous data physical channels on the MOST

bus through eight programmable DMA channels. The synchro-

nous data DMA channels can operate in various modes

including modes that trigger DMA operation when data pat-

terns are detected in the receive data stream. Furthermore, two

DMA channels support asynchronous traffic, and two others

support control message traffic.

In the active mode, it is possible to disable the control input to

the PLL by setting the PLL_OFF bit in the PLL control register.

This register can be accessed with a user-callable routine in the

on-chip ROM called bfrom_SysControl(). For more informa-

tion, see the “Dynamic Power Management” chapter in the

ADSP-BF54x Blackfin Processor Hardware Reference. If dis-

abled, the PLL must be re-enabled before transitioning to the

full-on or sleep modes.

¹MOST is a registered trademark of Standard Microsystems, Corp.

Rev. C

|

Page 16 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

5.0V

1.25V

600Z

MOST FOT

RXVCC

RXGND

VDDINT

ADSP-BF549

10k6

GND

PG11/MTXON

MOST

600Z

NETWORK

600Z

TXVCC

TXGND

XN4114

VDDMP

MF

0.01

0.1MF

276

TX_DATA

RX_DATA

STATUS

PH5/MTX

PH6/MRX

GNDMP

0 6

MXO

MXI

PH7/MRXON

24.576MHz

PC4/RFS0

MFS

6

33

L/RCLK

MCLK

AUDIO DAC

336

PC1/MMCLK

PC5/MBCLK

MLF_P

MLF_M

BCLK

AUDIO

R1

CHANNELS

C2

330 6 1%

PC3/TSCLK0

PC7/RSCLK0

330pF

2% PPS

C1

MF

0.047

SDATA

PC2/DT0PRI

2% PPS

Figure 5. MXVR MOST Connection

Table 5. Power Settings

such as the RTC, may still be running but will not be able to

access internal resources or external memory. This

powered-down mode can only be exited by assertion of the reset

interrupt (RESET) or by an asynchronous interrupt generated

by the RTC. In deep sleep mode, an asynchronous RTC inter-

rupt causes the processor to transition to the active mode.

Assertion of RESET while in deep sleep mode causes the proces-

sor to transition to the full on mode.

Full On

Active

Enabled

No

Enabled Enabled On

Enabled/ Yes

Disabled

Hibernate State—Maximum Static Power Savings

Sleep

Enabled

-

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by using the

Deep Sleep Disabled

Hibernate Disabled

bfrom_SysControl() function in the on-chip ROM. This sets the

internal power supply voltage (V_DDINT) to 0 V to provide the

greatest power savings mode. Any critical information stored

internally (memory contents, register contents, and so on) must

be written to a non-volatile storage device prior to removing

power if the processor state is to be preserved.

Since V_DDEXTis still supplied in this mode, all of the external

pins three-state, unless otherwise specified. This allows other

devices that may be connected to the processor to have power

still applied without drawing unwanted current.

The internal supply regulator can be woken up by CAN, by the

MXVR, by the keypad, by the up/down counter, by the USB,

and by some GPIO pins. It can also be woken up by a real-time

clock wakeup event or by asserting the RESET pin. Waking up

from hibernate state initiates the hardware reset sequence.

With the exception of the VR_CTL and the RTC registers, all

internal registers and memories lose their content in hibernate

state. State variables may be held in external SRAM or DDR

memory.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling

the clock to the processor core (CCLK). The PLL and system

clock (SCLK), however, continue to operate in this mode. Typi-

cally an external event or RTC activity will wake up the

processor. In the sleep mode, assertion of a wakeup event

enabled in the SIC_IWRx register causes the processor to sense

the value of the BYPASS bit in the PLL control register

(PLL_CTL). If BYPASS is disabled, the processor transitions to

the full on mode. If BYPASS is enabled, the processor transi-

tions to the active mode.

In the sleep mode, system DMA access to L1 memory is not

supported.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes dynamic power savings by dis-

abling the clocks to the processor core (CCLK) and to all

synchronous peripherals (SCLK). Asynchronous peripherals,

Rev. C

|

Page 17 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Power Domains

2.7V TO 3.6V

INPUT VOLTAGE

RANGE

SET OF DECOUPLING

CAPACITORS

V

DDVR

As shown in Table 6, the ADSP-BF54x Blackfin processors sup-

port different power domains. The use of multiple power

domains maximizes flexibility while maintaining compliance

with industry standards and conventions. By isolating the inter-

nal logic of the ADSP-BF54x Blackfin processors into its own

power domain separate from the RTC and other I/O, the pro-

cessors can take advantage of dynamic power management

without affecting the RTC or other I/O devices. There are no

sequencing requirements for the various power domains.

(LOW-INDUCTANCE)

V

DDVR

10μH

100nF

DDINT

+

100μF

FDS9431A

100μF

10μF

LOW ESR

ZHCS1000

VR

OUT

Table 6. Power Domains

SHORT AND LOW-

INDUCTANCE WIRE

Power Domain

VDD Range

V_DDINT

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

All internal logic, except RTC, DDR, and USB

RTC internal logic and crystal I/O

DDR external memory supply

USB internal logic and crystal I/O

Internal voltage regulator

MXVR PLL and logic

GND

V_DDRTC

V_DDDDR

V_DDUSB

V_DDVR

Figure 6. Voltage Regulator Circuit

CLOCK SIGNALS

V_DDMP

The ADSP-BF54x Blackfin processors can be clocked by an

external crystal, a sine wave input, or a buffered, shaped clock

derived from an external clock oscillator.

If an external clock is used, it should be a TTL-compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF54x Blackfin processors

include an on-chip oscillator circuit, an external crystal may be

used. For fundamental frequency operation, use the circuit

shown in Figure 7. A parallel-resonant, fundamental frequency,

microprocessor-grade crystal is connected across the CLKIN

and XTAL pins. The on-chip resistance between CLKIN and the

XTAL pin is in the 500 kΩ range. Typically, further parallel

resistors are not recommended. The two capacitors and the

series resistor shown in Figure 7 fine-tune phase and amplitude

of the sine frequency. The 1MOhm pull-up resistor on the

XTAL pin guarantees that the clock circuit is properly held inac-

tive when the processor is in the hibernate state.

The capacitor and resistor values shown in Figure 7 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. System designs should

verify the customized values based on careful investigations on

multiple devices over temperature range.

All other I/O

V_DDEXT

VOLTAGE REGULATION

The ADSP-BF54x Blackfin processors provide an on-chip volt-

age regulator that can generate processor core voltage levels

from an external supply (see specifications in Operating Condi-

tions on Page 34). Figure 6 on Page 18 shows the typical

external components required to complete the power manage-

ment system. The regulator controls the internal logic voltage

levels and is programmable with the voltage regulator control

register (VR_CTL) in increments of 50 mV. This register can be

accessed using the bfrom_SysControl() function in the on-chip

ROM. To reduce standby power consumption, the internal volt-

age regulator can be programmed to remove power to the

processor core while keeping I/O power supplied. While in

hibernate state, V_DDEXT, V_DDRTC, V_DDDDR, V_DDUSB, and V_DDVRcan

still be applied, eliminating the need for external buffers. The

voltage regulator can be activated from this power-down state

by assertion of the RESET pin, which then initiates a boot

sequence. The regulator can also be disabled and bypassed at the

user’s discretion. For all 600 MHz speed grade models and all

automotive grade models, the internal voltage regulator must

not be used and V_DDVRmust be tied to V_DDEXT. For additional

information regarding design of the voltage regulator circuit,

see Switching Regulator Design Considerations for the ADSP-

BF533 Blackfin Processors (EE-228).

Rev. C

|

Page 18 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

All on-chip peripherals are clocked by the system clock (SCLK).

BLACKFIN

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 7 illustrates typical system clock ratios. The default

ratio is 4.

CLKOUT

CLKBUF

TO PLL CIRCUITRY

EN

700ꢀ

EN

V

DDEXT

Table 7. Example System Clock Ratios

XTAL

CLKIN

*

0 ꢀ

1Mꢀ

Example Frequency Ratios

(MHz)

VCO

200

Signal Name Divider Ratio

18 pF*

FOR OVERTONE

OPERATION ONLY

SSEL3–0

VCO/SCLK

SCLK

100

50

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

0010

2:1

0110

6:1

300

Figure 7. External Crystal Connections

1010

10:1

500

50

A third-overtone crystal can be used at frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone by adding a tuned inductor circuit as

shown in Figure 7. A design procedure for third-overtone oper-

ation is discussed in detail in an Application Note, Using Third

Overtone Crystals (EE-168).

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 8 on Page 19, the core clock

(CCLK) and system peripheral clock (SCLK) are derived from

the input clock (CLKIN) signal. An on-chip PLL is capable of

multiplying the CLKIN signal by a programmable 0.5× to 64×

multiplication factor (bounded by specified minimum and max-

imum VCO frequencies). The default multiplier is 8×, but it can

be modified by a software instruction sequence. This sequence

is managed by the bfrom_SysControl() function in the on-chip

ROM.

Note that the divisor ratio must be chosen to limit the system

clock frequency to its maximum of f_SCLK. The SSEL value can be

dynamically changed without any PLL lock latencies by writing

the appropriate values to the PLL divisor register (PLL_DIV)

using the bfrom_SysControl() function in the on-chip ROM.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 8. The default ratio is 1. This programmable core clock

capability is useful for fast core frequency modifications.

The maximum CCLK frequency not only depends on the part’s

speed grade, it also depends on the applied V_DDINTvoltage. See

Table 13 on Page 35 for details.

Table 8. Core Clock Ratios

On-the-fly CCLK and SCLK frequency changes can be applied

by using the bfrom_SysControl() function in the on-chip ROM.

Whereas the maximum allowed CCLK and SCLK rates depend

on the applied voltages V_DDINTand V_DDEXT, the VCO is always

permitted to run up to the frequency specified by the part’s

speed grade.

The CLKOUT pin reflects the SCLK frequency to the off-chip

world. It functions as a reference for many timing specifications.

While inactive by default, it can be enabled using the

EBIU_AMGCTL register.

Example Frequency Ratios

(MHz)

VCO

300

Signal Name Divider Ratio

CSEL1–0

VCO/CCLK

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

300

500

200

BOOTING MODES

The ADSP-BF54x Blackfin processors have many mechanisms

(listed in Table 9) for automatically loading internal and exter-

nal memory after a reset. The boot mode is specified by four

BMODE input pins dedicated to this purpose. There are two

categories of boot modes: master and slave. In master boot

DYNAMIC MODIFICATION

ON-THE-FLY

DYNAMIC MODIFICATION

REQUIRES PLL SEQUENCING

CCLK

SCLK

1, 2, 4, 8

ꢁ

PLL

0.5x - 64x

CLKIN

VCO

ꢁ 1:15

Note: For CCLK and SCLK specifications, see Table 16.

Figure 8. Frequency Modification Methods

Rev. C

|

Page 19 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

modes, the processor actively loads data from parallel or serial

memories. In slave boot modes, the processor receives data

from an external host device.

performs an 8- or 16-bit boot or starts program execution

at the address provided by the header. By default, all con-

figuration settings are set for the slowest device possible (3-

cycle hold time; 15-cycle R/W access times; 4-cycle setup).

Table 9. Booting Modes

The ARDY pin is not enabled by default. It can, however,

be enabled by OTP programming. Similarly, all interface

behavior and timings can be customized through OTP pro-

gramming. This includes activation of burst-mode or page-

mode operation. In this mode, all asynchronous interface

signals are enabled at the port muxing level.

• Boot from 16-bit asynchronous FIFO (BMODE = 0x2)—In

this mode, the boot kernel starts booting from address

0x2030 0000. Every 16-bit word that the boot kernel has to

read from the FIFO must be requested by a low pulse on

the DMAR1 pin.

• Boot from serial SPI memory, EEPROM or flash

(BMODE = 0x3)—8-, 16-, 24- or 32-bit addressable devices

are supported. The processor uses the PE4 GPIO pin to

select a single SPI EEPROM or flash device and uses SPI0

to submit a read command and successive address bytes

(0x00) until a valid 8-, 16-, 24-, or 32-bit addressable device

is detected. Pull-up resistors are required on the SPI0SEL1

and SPI0MISO pins. By default, a value of 0x85 is written to

the SPI0_BAUD register.

• Boot from SPI host device (BMODE = 0x4)—The proces-

sor operates in SPI slave mode (using SPI0) and is

configured to receive the bytes of the .LDR file from an SPI

host (master) agent. The HWAIT signal must be interro-

gated by the host before every transmitted byte. A pull-up

resistor is required on the SPI0SS input. A pull-down resis-

tor on the serial clock (SPI0SCK) may improve signal

quality and booting robustness.

• Boot from serial TWI memory, EEPROM or flash

(BMODE = 0x5)—The processor operates in master mode

(using TWI0) and selects the TWI slave with the unique ID

0xA0. The processor submits successive read commands to

the memory device starting at two-byte internal address

0x0000 and begins clocking data into the processor. The

TWI memory device should comply with Philips I²C Bus

Specification version 2.1 and have the capability to auto-

increment its internal address counter such that the con-

tents of the memory device can be read sequentially. By

default, a prescale value of 0xA and CLKDIV value of

0x0811 is used. Unless altered by OTP settings, an I²C

memory that takes two address bytes is assumed. Develop-

ment tools ensure that data that is booted to memories that

cannot be accessed by the Blackfin core is written to an

intermediate storage place and then copied to the final des-

tination via memory DMA.

BMODE3–0 Description

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Idle-no boot

Boot from 8- or 16-bit external flash memory

Boot from 16-bit asynchronous FIFO

Boot from serial SPI memory (EEPROM or flash)

Boot from SPI host device

Boot from serial TWI memory (EEPROM or flash)

Boot from TWI host

Boot from UART host

Reserved

Boot from DDR SDRAM/Mobile DDR SDRAM

Boot from OTP memory

Reserved

Boot from 8- or16-bit NANDflash memory via NFC

Boot from 16-bit host DMA

Boot from 8-bit host DMA

The boot modes listed in Table 9 provide a number of mecha-

nisms for automatically loading the processor’s internal and

external memories after a reset. By default, all boot modes use

the slowest allowed configuration settings. Default settings can

be altered via the initialization code feature at boot time or by

proper OTP programming at pre-boot time. Some boot modes

require a boot host wait (HWAIT) signal, which is a GPIO out-

put signal that is driven and toggled by the boot kernel at boot

time. If pulled high through an external pull-up resistor, the

HWAIT signal behaves active high and will be driven low when

the processor is ready for data. Conversely, when pulled low,

HWAIT is driven high when the processor is ready for data.

When the boot sequence completes, the HWAIT pin can be

used for other purposes. By default, HWAIT functionality is on

GPIO port B (PB11). However, if PB11 is otherwise utilized in

the system, an alternate boot host wait (HWAITA) signal can be

enabled on GPIO port H (PH7) by programming the

OTP_ALTERNATE_HWAIT bit in the PBS00L OTP

memory page.

The BMODE pins of the reset configuration register, sampled

during power-on resets and software-initiated resets, imple-

ment the following modes:

• Idle-no boot mode (BMODE = 0x0)—In this mode, the

processor goes into the idle state. The idle boot mode helps

to recover from illegal operating modes, in case the OTP

memory is misconfigured.

• Boot from TWI host (BMODE = 0x6)—The TWI host

agent selects the slave with the unique ID 0x5F. The proces-

sor (using TWI0) replies with an acknowledgement, and

the host can then download the boot stream. The TWI host

agent should comply with Philips I²C Bus Specification ver-

• Boot from 8- or 16-bit external flash memory—

(BMODE = 0x1)—In this mode, the boot kernel loads the

first block header from address 0x2000 0000 and, depend-

ing on instructions contained in the header, the boot kernel

Rev. C

|

Page 20 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

sion 2.1. An I²C multiplexer can be used to select one

processor at a time when booting multiple processors from

a single TWI.

If the NAND flash device requires only three address

cycles, then the device must be capable of ignoring the

additional address cycle.

• Boot from UART host (BMODE = 0x7)—In this mode, the

processor uses UART1 as the booting source. Using an

autobaud handshake sequence, a boot-stream-formatted

program is downloaded by the host. The host agent selects

a bit rate within the UART’s clocking capabilities.

When performing the autobaud, the UART expects an “@”

(0x40) character (eight data bits, one start bit, one stop bit,

no parity bit) on the UART1RX pin to determine the bit

rate. It then replies with an acknowledgement, which is

composed of four bytes (0xBF, the value of UART1_DLL,

the value of UART1_DLH, and finally 0x00). The host can

then download the boot stream. The processor deasserts

the UART1RTS output to hold off the host; UART1CTS

functionality is not enabled at boot time.

The small page NAND flash device must comply with the

following command set:

Reset: 0xFF

Read lower half of page: 0x00

Read upper half of page: 0x01

Read spare area: 0x50

For large page NAND flash devices, the 4-byte electronic

signature is read in order to configure the kernel for boot-

ing. This allows support for multiple large page devices.

The fourth byte of the electronic signature must comply

with the specifications in Table 10.

Any configuration from Table 10 that also complies with

the command set listed below is directly supported by the

boot kernel. There are no restrictions on the page size or

block size as imposed by the small-page boot kernel.

• Boot from (DDR) SDRAM (BMODE = 0xA)—In this

mode, the boot kernel starts booting from address

0x0000 0010. This is a warm boot scenario only. The

SDRAM is expected to contain a valid boot stream and the

SDRAM controller must have been configured by the OTP

settings.

Table 10. Byte 4 Electronic Signature Specification

• Boot from 8-bit and 16-bit external NAND flash memory

(BMODE = 0xD)—In this mode, auto detection of the

NAND flash device is performed. The processor configures

PORTJ GPIO pins PJ1 and PJ2 to enable the ND_CE and

ND_RB signals, respectively. For correct device operation,

pull-up resistors are required on both ND_CE (PJ1) and

ND_RB (PJ2) signals. By default, a value of 0x0033 is writ-

ten to the NFC_CTL register. The booting procedure

always starts by booting from byte 0 of block 0 of the

NAND flash device. In this boot mode, the HWAIT signal

does not toggle. The respective GPIO pin remains in the

high-impedance state.

NAND flash boot supports the following features:

• Device auto detection

• Error detection and correction for maximum

reliability

Page Size

(excluding spare

area)

D1:D0 00

1K bytes

01

10

11

2K bytes

4K bytes

8K bytes

Spare Area Size

D2

0

8 bytes/512 bytes

16bytes/512bytes

64K bytes

128K bytes

256K bytes

512K bytes

x8

1

Block Size

(excluding spare

area)

D5:4

00

01

10

11

0

• No boot stream size limitation

Bus Width

D6

• Peripheral DMA via channel 22, providing efficient

transfer of all data (excluding the ECC parity data)

1

x16

Not Used for

Configuration

D3, D7

• Software-configurable boot mode for booting from

boot streams expanding multiple blocks, including

bad blocks

Large page devices must support the following command set:

• Software-configurable boot mode for booting from

multiple copies of the boot stream allowing for han-

dling of bad blocks and uncorrectable errors

Reset: 0xFF

• Configurable timing via OTP memory

Read Electronic Signature: 0x90

Read: 0x00, 0x30 (confirm command)

Small page NAND flash devices must have a 512-byte page

size, 32 pages per block, a 16-byte spare area size and a bus

configuration of eight bits. By default, all read requests

from the NAND flash are followed by four address cycles.

Large page devices must not support or react to NAND flash

command 0x50. This is a small page NAND flash command

used for device auto detection.

Rev. C

|

Page 21 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

By default, the boot kernel will always issue five address cycles;

therefore, if a large page device requires only four cycles, the

device must be capable of ignoring the additional address cycle.

SDRAM controller, which then returns using an RTS

instruction. The routine may also be the final application,

which will never return to the boot kernel.

16-bit NAND flash memory devices must only support the issu-

ing of command and address cycles via the lower eight bits of

the data bus. Devices that use the full 16-bit bus for command

and address cycles are not supported.

• Boot from OTP memory (BMODE = 0xB)—This provides

a standalone booting method. The boot stream is loaded

from on-chip OTP memory. By default, the boot stream is

expected to start from OTP page 0x40 and can occupy all

public OTP memory up to page 0xDF (2560 bytes). Since

the start page is programmable, the maximum size of the

boot stream can be extended to 3072 bytes.

• Boot from 16-bit host DMA (BMODE = 0xE)—In this

mode, the host DMA port is configured in 16-bit acknowl-

edge mode with little endian data format. Unlike other

modes, the host is responsible for interpreting the boot

stream. It writes data blocks individually into the host

DMA port. Before configuring the DMA settings for each

block, the host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the host DMA port. After completing the

For each of the boot modes, a 16-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the address stored in the EVT1 register.

Prior to booting, the pre-boot routine interrogates the OTP

memory. Individual boot modes can be customized or disabled

based on OTP programming. External hardware, especially

booting hosts, may monitor the HWAIT signal to determine

when the pre-boot has finished and the boot kernel starts the

boot process. However, the HWAIT signal does not toggle in

NAND boot mode. By programming OTP memory, the user

can instruct the preboot routine to also customize the PLL, volt-

age regulator, DDR controller, and/or asynchronous memory

interface controller.

The boot kernel differentiates between a regular hardware reset

and a wakeup-from-hibernate event to speed up booting in the

later case. Bits 6-4 in the system reset configuration (SYSCR)

register can be used to bypass the pre-boot routine and/or boot

kernel in case of a software reset. They can also be used to simu-

late a wakeup-from-hibernate boot in the software reset case.

configuration, the host is required to poll the READY bit in

HOST_STATUS before beginning to transfer data. When

the host sends an HIRQ control command, the boot kernel

issues a CALL instruction to address 0xFFA0 0000. It is the

host’s responsibility to ensure valid code has been placed at

this address. The routine at address 0xFFA0 0000 can be a

simple initialization routine to configure internal

resources, such as the SDRAM controller, which then

returns using an RTS instruction. The routine may also be

the final application, which will never return to the boot

kernel.

The boot process can be further customized by “initialization

code.” This is a piece of code that is loaded and executed prior to

the regular application boot. Typically, this is used to configure

the DDR controller or to speed up booting by managing PLL,

clock frequencies, wait states, and/or serial bit rates.

The boot ROM also features C-callable function entries that can

be called by the user application at run time. This enables sec-

ond-stage boot or booting management schemes to be

implemented with ease.

INSTRUCTION SET DESCRIPTION

• Boot from 8-bit host DMA (BMODE = 0xF)—In this

mode, the host DMA port is configured in 8-bit interrupt

mode with little endian data format. Unlike other modes,

the host is responsible for interpreting the boot stream. It

writes data blocks individually to the host DMA port.

Before configuring the DMA settings for each block, the

host may either poll the ALLOW_CONFIG bit in

HOST_STATUS or wait to be interrupted by the HWAIT

signal. When using HWAIT, the host must still check

ALLOW_CONFIG at least once before beginning to con-

figure the host DMA port. The host will receive an

interrupt from the HOST_ACK signal every time it is

allowed to send the next FIFO depth’s worth (sixteen 32-bit

words) of information. When the host sends an HIRQ con-

trol command, the boot kernel issues a CALL instruction to

address 0xFFA0 0000. It is the host's responsibility to

ensure valid code has been placed at this address. The rou-

tine at address 0xFFA0 0000 can be a simple initialization

routine to configure internal resources, such as the

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

Rev. C

|

Page 22 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

The assembly language, which takes advantage of the proces-

(EE-68) on the Analog Devices web site under

sor’s unique architecture, offers the following advantages:

www.analog.com/ee-notes. This document is updated regularly

to keep pace with improvements to emulator support.

• Seamlessly integrated DSP/MCU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified-Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU + two

load/store + two pointer updates per cycle.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data-types; and separate user and

supervisor stack pointers.

MXVR BOARD LAYOUT GUIDELINES

The MXVR Loop Filter RC network is connected between the

MLF_P and MLF_M pins in the following manner:

Capacitors:

• C1: 0.047 µF (PPS type, 2% tolerance recommended)

• C2: 330 pF (PPS type, 2% tolerance recommended)

Resistor:

• R1: 330 Ω (1% tolerance)

The RC network should be located physically close to the

MLF_P and MLF_M pins on the board.

The RC network should be shielded using GND_MPtraces.

Avoid routing other switching signals near the RC network to

avoid crosstalk.

• Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

MXI driven with external clock oscillator IC:

DEVELOPMENT TOOLS

• MXI should be driven with the clock output of a clock

oscillator IC running at a frequency of 49.152 MHz or

45.1584 MHz.

The ADSP-BF54x Blackfin processors are supported with a

complete set of CROSSCORE® software and hardware develop-

ment tools, including Analog Devices emulators and

VisualDSP++® development environment. The same emulator

hardware that supports other Blackfin processors also fully

emulates the ADSP-BF54x Blackfin processors.

• MXO should be left unconnected.

• Avoid routing other switching signals near the oscillator

and clock output trace to avoid crosstalk. When not possi-

ble, shield traces with ground.

EZ-KIT Lite Evaluation Board

MXI/MXO with external crystal:

• The crystal must be a fundamental mode crystal running at

a frequency of 49.152 MHz or 45.1584 MHz.

• The crystal and load capacitors should be placed physically

close to the MXI and MXO pins on the board.

• Board trace capacitance on each lead should not be more

than 3 pF.

• Trace capacitance plus load capacitance should equal the

load capacitance specification for the crystal.

• Avoid routing other switching signals near the crystal and

components to avoid crosstalk. When not possible, shield

traces and components with ground.

For evaluation of ADSP-BF54x Blackfin processors, use the

ADSP-BF548 EZ-KIT Lite^®board available from Analog

Devices. Order part number ADZS-BF548-EZLITE. The board

comes with on-chip emulation capabilities and is equipped to

enable software development. Multiple daughter cards are

available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG processor. The emulator uses

the TAP to access the internal features of the processor, allow-

ing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor is

set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

V

_DDMP/GND_MP—MXVR PLL power domain:

• Route V_DDMPand GND_MPwith wide traces or as isolated

power planes.

• Drive V_DDMPto same level as V_DDINT

• Place a ferrite bead between the V_DDINTpower plane and the

V_DDMPpin for noise isolation.

.

• Locally bypass V_DDMPwith 0.1 µF and 0.01 µF decoupling

capacitors to GND_MP

.

• Avoid routing switching signals near to V_DDMPand GND_MP

traces to avoid crosstalk.

Rev. C

|

Page 23 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Fiber optic transceiver (FOT) connections:

• Keep the traces between the ADSP-BF549 processor and

the FOT as short as possible.

• The receive data trace connecting the FOT receive data

output pin to the ADSP-BF549 PH6/MRX input pin should

have a 0 Ω series termination resistor placed close to the

FOT receive data output pin. Typically, the edge rate of the

FOT receive data signal driven by the FOT is very slow, and

further degradation of the edge rate is not desirable.

• The transmit data trace connecting the ADSP-BF549

PH5/MTX output pin to the FOT transmit data input pin

should have a 27 Ω series termination resistor placed close

to the ADSP-BF549 PH5/MTX pin.

• The receive data trace and the transmit data trace between

the ADSP-BF549 processor and the FOT should not be

routed close to each other in parallel over long distances to

avoid crosstalk.

RELATED DOCUMENTS

The following publications that describe the ADSP-BF54x

Blackfin processors (and related processors) can be ordered

from any Analog Devices sales office or accessed electronically

on www.analog.com:

• ADSP-BF54x Blackfin Processor Hardware Reference, Vol-

ume 1 and Volume 2

• Blackfin Processor Programming Reference

• ADSP-BF542/BF544/BF547/BF548/BF549

Blackfin Anomaly List

LOCKBOX SECURE TECHNOLOGY DISCLAIMER

Analog Devices products containing Lockbox Secure Technol-

ogy are warranted by Analog Devices as detailed in the Analog

Devices Standard Terms and Conditions of Sale. To our knowl-

edge, the Lockbox secure technology, when used in accordance

with the data sheet and hardware reference manual specifica-

tions, provides a secure method of implementing code and data

safeguards. However, Analog Devices does not guarantee that

this technology provides absolute security. ACCORDINGLY,

ANALOG DEVICES HEREBY DISCLAIMS ANY AND ALL

EXPRESS AND IMPLIED WARRANTIES THAT THE LOCK-

BOX SECURE TECHNOLOGY CANNOT BE BREACHED,

COMPROMISED, OR OTHERWISE CIRCUMVENTED AND

IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR

ANY LOSS, DAMAGE, DESTRUCTION, OR RELEASE OF

DATA, INFORMATION, PHYSICAL PROPERTY, OR INTEL-

LECTUAL PROPERTY.

Rev. C

|

Page 24 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

PIN DESCRIPTIONS

ADSP-BF54x Blackfin processors’ pin multiplexing scheme is

listed in Table 11 and the pin definitions are listed in Table 12.

Table 11. Pin Multiplexing

Primary Pin

Function

(Number of

First Peripheral

Function

Second Peripheral

Function

Third Peripheral

Function

Fourth Peripheral

Function

Pins)^{1, 2}

Interrupt Capability

Port A

GPIO (16 pins)

SPORT2 (8 pins)

SPORT3 (8 pins)

TMR4 (1 pin)

TMR5 (1 pin)

TMR6 (1 pin)

TMR7 (1 pin)

TACI7 (1 pin)

TACLK7–0 (8 pins)

Interrupts (16 pins)

Port B

GPIO (15 pins)

TWI1 (2 pins)

UART2 or 3 CTL (2 pins)

UART2 (2 pins)

TACI2-3 (2 pins)

HWAIT (1 pin)

Interrupts (15 pins)

UART3 (2 pins)

SPI2 SEL1-3 (3 pins)

SPI2 (3 pins)

TMR0–2 (3 pins)

TMR3 (1 pin)

Port C

GPIO (16 pins)

SPORT0 (8 pins)

SDH (6 pins)

MXVR MMCLK, MBCLK

(2 pins)

Interrupts (8 pins)³

Interrupts (8 pins)

Port D

GPIO (16 pins)

PPI1 D0–15 (16 pins) Host D0–15 (16 pins) SPORT1 (8 pins)

PPI2 D0–7 (8 pins)

PPI0 D18– 23 (6 pins) Interrupts (8 pins)

Keypad

Interrupts (8 pins)

Row 0–3

Col 0–3 (8 pins)

Port E

GPIO (16 pins)

SPI0 (7 pins)

Keypad

TACI0 (1 pin)

Row 4–6

Col 4–7 (7 pins)

UART0 TX (1 pin)

Keypad R7 (1 pin)

UART0 RX (1 pin)

UART0 or 1 CTL (2 pins)

PPI1 CLK,FS (3 pins)

TWI0 (2 pins)

Port F

GPIO (16 pins)

PPI0 D0–15 (16 pins) ATAPI D0-15A

Interrupts (8 pins)

Port G

GPIO (16 pins)

PPI0 CLK,FS (3 pins)

DATA 16–17 (2 pins)

TMRCLK (1 pin)

ATAPI A0-2A

Interrupts (8 pins)

SPI1 SEL1–3 (3 pins)

SPI1 (4 pins)

Host CTL (3 pins)

PPI2 CLK,FS (3 pins)

CZM (1 pin)

MXVR MTXON (1 pin) TACI4-5 (2 pins)

CAN0 (2 pins)

CAN1 (2 pins)

Rev. C

|

Page 25 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 11. Pin Multiplexing (Continued)

Primary Pin

Function

(Number of

First Peripheral

Function

Second Peripheral

Function

Third Peripheral

Function

Fourth Peripheral

Function

Pins)^{1, 2}

Interrupt Capability

Port H

GPIO (14 pins)

UART1 (2 pins)

PPI0-1_FS3 (2 pins)

TMR8 (1 pin)

TACI1 (1 pin)

Interrupts (8 pins)

ATAPI_RESET (1 pin)

HOST_ADDR (1 pin)

PPI2_FS3 (1 pin)

TMR9 (1 pin)

Counter Down/Gate

(1 pin)

HOST_ACK (1 pin)

TMR10 (1 pin)

Counter Up/Dir

(1 pin)

MXVR MRX, MTX,

MRXON/GPW

(3 pins)⁴

DMAR 0–1 (2 pins)

TACI8–10 (3 pins)

TACLK8–10 (3 pins)

HWAITA

AMC Addr 4-9 (6 pins)

Interrupts (6 pins)

Port I

GPIO (16 pins)

Async Addr10–25

(16 pins)

Interrupts (8 pins)

Port J

GPIO (14 pins)

Async CTL and MISC

Interrupts (8 pins)

Interrupts (6 pins)

¹Port connections may be inputs or outputs after power up depending on the model and boot mode chosen.

²All port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system.

³A total of 32 interrupts at once are available from ports C through J, configurable in byte-wide blocks.

⁴GPW functionality available when MXVR is not present or unused.

ADSP-BF54x processor pin definitions are listed in Table 12. To

see the pin multiplexing scheme, see Table 11.

Table 12. Pin Descriptions

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port A: GPIO/SPORT2–3/TMR4–7

PA0/ TFS2

PA1/ DT2SEC /TMR4

PA2/ DT2PRI

PA3/ TSCLK2

PA4/ RFS2

I/O GPIO/SPORT2 Transmit Frame Sync

I/O GPIO/SPORT2 Transmit Data Secondary/Timer 4

I/O GPIO/SPORT2 Transmit Data Primary

I/O GPIO/SPORT2 Transmit Serial Clock

I/O GPIO/SPORT2 Receive Frame Sync

C

A

C

A

C

A

C

PA5/ DR2SEC/TMR5

PA6/ DR2PRI

I/O GPIO/SPORT2 Receive Data Secondary/Timer 5

I/O GPIO/SPORT2 Receive Data Primary

PA7/ RSCLK2/TACLK0

PA8/ TFS3/TACLK1

PA9/ DT3SEC /TMR6

PA10/ DT3PRI /TACLK2

PA11/ TSCLK3/TACLK3

PA12/ RFS3/TACLK4

PA13/ DR3SEC/TMR7/TACLK5

PA14/ DR3PRI/TACLK6

PA15/ RSCLK3/TACLK7 and TACI7

I/O GPIO/SPORT2 Receive Serial Clock/Alternate Input Clock 0

I/O GPIO/SPORT3 Transmit Frame Sync/Alternate Input Clock 1

I/O GPIO/SPORT3 Transmit Data Secondary/Timer 6

I/O GPIO/SPORT3 Transmit Data Primary/Alternate Input Clock 2

I/O GPIO/SPORT3 Transmit Serial Clock/Alternate Input Clock 3

I/O GPIO/SPORT3 Receive Frame Sync/Alternate Input Clock 4

I/O GPIO/SPORT3 Receive Data Secondary/Timer 7/Alternate Input Clock 5

I/O GPIO/SPORT3 Receive Data Primary/Alternate Input Clock 6

I/O GPIO/SPORT3 Receive Serial Clock/Alt Input Clock 7 and Alt Capture Input 7 A

Rev. C

|

Page 26 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3

PB0/SCL1

PB1/SDA1

I/O GPIO/TWI1 Serial Clock (Open-drain output: requires a pull-up resistor.) E

I/O GPIO/TWI1 Serial Data (Open-drain output: requires a pull-up resistor.) E

PB2/UART3RTS

PB3/UART3CTS

PB4/UART2TX

PB5/UART2RX/TACI2

PB6/UART3TX

PB7/UART3RX/TACI3

PB8/SPI2SS/TMR0

PB9/SPI2SEL1/TMR1

PB10 SPI2SEL2/TMR2

PB11/SPI2SEL3/TMR3/ HWAIT

PB12/SPI2SCK

PB13/SPI2MOSI

PB14/SPI2MISO

Port C: GPIO/SPORT0/SD Controller/MXVR (MOST)

PC0/TFS0

PC1/DT0SEC /MMCLK

PC2/DT0PRI

PC3/TSCLK0

PC4/RFS0

PC5/DR0SEC/MBCLK

PC6/DR0PRI

PC7/RSCLK0

PC8/SD_D0

PC9/SD_D1

PC10/SD_D2

I/O GPIO/UART3 Request to Send

I/O GPIO/UART3 Clear to Send

I/O GPIO/UART2 Transmit

I/O GPIO/UART2 Receive/Alternate Capture Input 2

I/O GPIO/UART3 Transmit

I/O GPIO/UART3 Receive/Alternate Capture Input 3

I/O GPIO/SPI2 Slave Select Input/Timer 0

I/O GPIO/SPI2 Slave Select Enable 1/Timer 1

I/O GPIO/SPI2 Slave Select Enable 2/Timer 2

I/O GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait

I/O GPIO/SPI2 Clock

C

A

C

I/O GPIO/SPI2 Master Out Slave In

I/O GPIO/SPI2 Master In Slave Out

I/O GPIO/SPORT0 Transmit Frame Sync

I/O GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock

I/O GPIO/SPORT0 Transmit Data Primary

I/O GPIO/SPORT0 Transmit Serial Clock

I/O GPIO/SPORT0 Receive Frame Sync

I/O GPIO/SPORT0 Receive Data Secondary/MXVR Bit Clock

I/O GPIO/SPORT0 Receive Data Primary

I/O GPIO/SPORT0 Receive Serial Clock

I/O GPIO/SD Data Bus

I/O GPIO/SD Clock Output

C

A

C

A

PC11/SD_D3

PC12/SD_CLK

PC13/SD_CMD

I/O GPIO/SD Command

Rev. C

|

Page 27 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port D: GPIO/PPI0–2/SPORT 1/Keypad/Host DMA

PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18

PD1/PPI1_D1/HOST_D9/ DT1SEC /PPI0_D19

PD2/PPI1_D2/HOST_D10/ DT1PRI /PPI0_D20

PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21

PD4/PPI1_D4/HOST_D12/RFS1/PPI0_D22

PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23

PD6/PPI1_D6/HOST_D14/DR1PRI

PD7/PPI1_D7/HOST_D15/RSCLK1

PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0

PD9/PPI1_D9/HOST_D1/PPI2_D1/KEY_ROW1

PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2

PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3

PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0

PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1

PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2

PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3

Port E: GPIO/SPI0/UART0-1/PPI1/TWI0/Keypad

PE0/SPI0SCK/KEY_COL7³

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Frame Sync/PPI0 Data

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Secondary/PPI0 Data C

C

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Data Primary/PPI0 Data

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Transmit Serial Clock/PPI0 Data

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Frame Sync/PPI0 Data

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Secondary/PPI0 Data

I/O GPIO/PPI1 Data/Host DMA/SPORT1 Receive Data Primary

I/O GPIO/PPI1 Data /Host DMA/SPORT1 Receive Serial Clock

I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Row Input

I/O GPIO/PPI1 Data/Host DMA/PPI2 Data/Keypad Column Output

C

A

C

A

I/O GPIO/SPI0 Clock/Keypad Column Output

I/O GPIO/SPI0 Master In Slave Out/Keypad Row Input

I/O GPIO/SPI0 Master Out Slave In/Keypad Column Output

I/O GPIO/SPI0 Slave Select Input/Keypad Row Input

I/O GPIO/SPI0 Slave Select Enable 1/Keypad Column Output

I/O GPIO/SPI0 Slave Select Enable 2/Keypad Row Input

I/O GPIO/SPI0 Slave Select Enable 3/Keypad Column Output

I/O GPIO/UART0 Transmit/Keypad Row Input

I/O GPIO/UART0 Receive/Alternate Capture Input 0

I/O GPIO/UART1 Request to Send

A

C

A

PE1/SPI0MISO/KEY_ROW6³

PE2/SPI0MOSI/KEY_COL6

PE3/SPI0SS/KEY_ROW5

PE4/SPI0SEL1/KEY_COL³

PE5/SPI0SEL2/KEY_ROW4

PE6/SPI0SEL3/KEY_COL4

PE7/UART0TX/KEY_ROW7

PE8/UART0RX/TACI0

PE9/UART1RTS

PE10/UART1CTS

PE11/PPI1_CLK

PE12/PPI1_FS1

I/O GPIO/UART1 Clear to Send

I/O GPIO / PPI1Clock

I/O GPIO/PPI1 Frame Sync 1

I/O GPIO/PPI1 Frame Sync 2

PE13/PPI1_FS2

PE14/SCL0

PE15/SDA0

I/O GPIO/TWI0 Serial Clock (Open-drain output: requires a pull-up resistor.) E

I/O GPIO/TWI0 Serial Data (Open-drain output: requires a pull-up resistor.) E

Rev. C

|

Page 28 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port F: GPIO/PPI0/Alternate ATAPI Data

PF0/PPI0_D0/ATAPI_D0A

PF1/PPI0_D1/ATAPI_D1A

PF2/PPI0_D2/ATAPI_D2A

PF3/PPI0_D3/ATAPI_D3A

PF4/PPI0_D4/ATAPI_D4A

PF5/PPI0_D5/ATAPI_D5A

PF6/PPI0_D6/ATAPI_D6A

PF7/PPI0_D7/ATAPI_D7A

PF8/PPI0_D8/ATAPI_D8A

PF9/PPI0_D9/ATAPI_D9A

PF10/PPI0_D10/ATAPI_D10A

PF11/PPI0_D11/ATAPI_D11A

PF12/PPI0_D12/ATAPI_D12A

PF13/PPI0_D13/ATAPI_D13A

PF14/PPI0_D14/ATAPI_D14A

PF15/PPI0_D15/ATAPI_D15A

I/O GPIO/PPI0 Data/Alternate ATAPI Data

A

Port G: GPIO/PPI0/SPI1/PPI2/Up-Down

Counter/CAN0–1/Host DMA/MXVR (MOST)/ATAPI

PG0/PPI0_CLK/TMRCLK

PG1/PPI0_FS1

PG2/PPI0_FS2/ATAPI_A0A

PG3/PPI0_D16/ATAPI_A1A

PG4/PPI0_D17/ATAPI_A2A

PG5/SPI1SEL1/HOST_CE/PPI2_FS2/CZM

I/O GPIO/PPI0 Clock/External Timer Reference

I/O GPIO/PPI0 Frame Sync 1

I/O GPIO/PPI0 Frame Sync 2/Alternate ATAPI Address

I/O GPIO/PPI0 Data/Alternate ATAPI Address

A

I/O GPIO/SPI1SlaveSelect/HostDMAChipEnable/PPI2 FrameSync2/Counter A

Zero Marker

PG6/SPI1SEL2/HOST_RD/PPI2_FS1

PG7/SPI1SEL3/HOST_WR/PPI2_CLK

PG8/SPI1SCK

PG9/SPI1MISO

PG10/SPI1MOSI

PG11/SPI1SS/MTXON

PG12/CAN0TX

PG13/CAN0RX/TACI4

PG14/CAN1TX

I/O GPIO/SPI1 Slave Select/ Host DMA Read/PPI2 Frame Sync 1

I/O GPIO/SPI1 Slave Select/Host DMA Write/PPI2 Clock

I/O GPIO/SPI1 Clock

I/O GPIO/SPI1 Master In Slave Out

I/O GPIO/SPI1 Master Out Slave In

I/O GPIO/SPI1 Slave Select Input/MXVR Transmit Phy On

I/O GPIO/CAN0 Transmit

I/O GPIO/CAN0 Receive/Alternate Capture Input 4

I/O GPIO/CAN1 Transmit

A

C

A

PG15/CAN1RX/TACI5

I/O GPIO/CAN1 Receive/Alternate Capture Input 5

Rev. C

|

Page 29 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port H:

GPIO/AMC/EXTDMA/UART1/PPI0–2/ATAPI/Up-

Down Counter/TMR8-10/Host DMA/MXVR (MOST)

PH0/UART1TX/PPI1_FS3_DEN

I/O GPIO/UART1 Transmit/PPI1 Frame Sync 3

A

PH1/UART1RX/PPI0_FS3_DEN/TACI1

PH2/ATAPI_RESET /TMR8/PPI2_FS3_DEN

PH3/HOST_ADDR/TMR9/CDG

I/O GPIO/UART 1 Receive/ PPI0 Frame Sync 3/Alternate Capture Input 1

I/O GPIO/ATAPI Interface Hard Reset Signal/Timer 8/PPI2 Frame Sync 3

I/O GPIO/HOST Address/Timer 9/Count Down and Gate

I/O GPIO/HOST Acknowledge/Timer 10/Count Up and Direction

PH4/HOST_ACK/TMR10/CUD

PH5/MTX/DMAR0/TACI8 and TACLK8

PH6/MRX/DMAR1/TACI9 and TACLK9

I/O GPIO/MXVR Transmit Data/Ext. DMA Request/Alt Capt. In. 8 /Alt In. Clk 8 C

I/O GPIO/MXVR Receive Data/Ext. DMA Request/Alt Capt. In. 9 /Alt In. Clk 9

A

PH7/MRXON/GPW/TACI10 and TACLK10/HWAITA^4,5I/O GPIO/MXVR Receive Phy On /Alt Capt. In. 10 /Alt In. Clk 10/Alternate Boot A

Host Wait

PH8/A4⁶

I/O GPIO/Address Bus for Async Access

A

PH9/A5⁶

PH10/A6⁶

PH11/A7⁶

PH12/A8⁶

PH13/A9⁶

Port I: GPIO/AMC

PI0/A10⁶

I/O GPIO/Address Bus for Async Access

I/O GPIO/Address Bus for Async Access/ NOR clock

A

PI1/A11⁶

PI2/A12⁶

PI3/A13⁶

PI4/A14⁶

PI5/A15⁶

PI6/A16⁶

PI7/A17⁶

PI8/A18⁶

PI9/A19⁶

PI10/A20⁶

PI11/A21⁶

PI12/A22⁶

PI13/A23⁶

PI14/A24⁶

PI15/A25/NR_CLK⁶

Rev. C

|

Page 30 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

Port J: GPIO/AMC/ATAPI

PJ0 / ARDY/WAIT

PJ1 / ND_CE⁷

PJ2 / ND_RB

PJ3 / ATAPI_DIOR

PJ4 / ATAPI_DIOW

PJ5 / ATAPI_CS0

PJ6 / ATAPI_CS1

PJ7 / ATAPI_DMACK

PJ8 / ATAPI_DMARQ

PJ9 / ATAPI_INTRQ

PJ10 / ATAPI_IORDY

PJ11 / BR⁸

I/O GPIO/ Async Ready/NOR Wait

I/O GPIO/NAND Chip Enable

I/O GPIO/NAND Ready Busy

I/O GPIO/ATAPI Read

A

I/O GPIO/ATAPI Write

I/O GPIO/ATAPI Chip Select/Command Block

I/O GPIO/ATAPI Chip Select

I/O GPIO/ATAPI DMA Acknowledge

I/O GPIO/ATAPI DMA Request

I/O GPIO/Interrupt Request from the Device

I/O GPIO/ATAPI Ready Handshake

I/O GPIO/Bus Request

PJ12 / BG⁶

PJ13 / BGH⁶

I/O GPIO/Bus Grant

I/O GPIO/Bus Grant Hang

DDR Memory Interface

DA0–12

DBA0–1

DQ0–15

DQS0–1

DQM0–1

DCLK0–1

DCS0–1

DCLKE⁹

DRAS

DCAS

DWE

DDR_VREF

O

DDR Address Bus

DDR Bank Active Strobe

D

I/O DDR Data Bus

I/O DDR Data Strobe

O

I

DDR Data Mask for Reads and Writes

DDR Output Clock

DDR Complementary Output Clock

DDR Chip Selects

DDR Clock Enable

DDR Row Address Strobe

DDR Column Address Strobe

DDR Write Enable

DDR Voltage Reference

DDR_VSSR

I

DDR Voltage Reference Shield (Must be connected to GND.)

Asynchronous Memory Interface

A1-3

D0-15/ND_D0-15/ATAPI_D0-15

AMS0–3

O

Address Bus for Async and ATAPI Addresses

A

I/O Data Bus for Async, NAND and ATAPI Accesses

O

Bank Selects (Pull high with a resistor when used as chip select.)

Byte Enables:Data Masks for Asynchronous Access/NAND Command

ABE0 /ND_CLE

Latch Enable

ABE1/ND_ALE

O

Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch A

Enable

AOE/NR_ADV

ARE

AWE

O

Output Enable/NOR Address Data Valid

Read Enable/NOR Output Enable

Write Enable

A

ATAPI Controller Pins

ATAPI_PDIAG

I

Determines if an 80-pin cable is connected to the host. (Pull high or low

when unused.)

Rev. C

|

Page 31 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

I/O¹Function (First/Second/Third/Fourth)

High Speed USB OTG Pins

USB_DP

USB_DM

I/O USB D+ Pin (Pull low when unused.)

I/O USB D- Pin (Pull low when unused.)

USB_XI

USB_XO

USB_ID¹⁰

C

I

Clock XTAL Input (Pull high or low when unused.)

Clock XTAL Output (Leave unconnected when unused.)

USB OTG ID Pin (Pull high when unused.)

USB_VBUS¹¹

USB_VREF

I/O USB VBUS Pin (Pull high or low when unused.)

A

USB Voltage Reference (Connect to GND through a 0.1 mF capacitor or

leave unconnected when not used.)

USB_RSET

A

USB Resistance Set (Connect to GND through an unpopulated

resistor pad.)

MXVR (MOST) Interface

MFS

MLF_P

MLF_M

MXI

O

A

C

MXVR Frame Sync (Leave unconnected when unused.)

MXVR Loop Filter Plus (Leave unconnected when unused.)

MXVR Loop Filter Minus (Leave unconnected when unused.)

MXVR Crystal Input (Pull high or low when unused.)

MXVR Crystal Output (Pull high or low when unused.)

C

MXO

Mode Control Pins

BMODE0–3

I

Boot Mode Strap 0–3

JTAG Port Pins

TDI

TDO

TRST

TMS

I

O

I

JTAG Serial Data In

JTAG Serial Data Out

JTAG Reset (Pull low when unused.)

JTAG Mode Select

C

I

TCK

EMU

I

O

JTAG Clock

Emulation Output

Voltage Regulator

VR_OUT0, VR_OUT

1

O

External FET/BJT Drivers (Always connect together to reduce signal

impedance.)

Real Time Clock

RTXO

RTXI

C

RTC Crystal Output (Leave unconnected when unused.)

RTC Crystal Input (Pull high or low when unused.)

Clock (PLL) Pins

CLKIN

CLKOUT

XTAL

CLKBUF

EXT_WAKE

RESET

C

O

C

O

I

Clock/Crystal Input

Clock Output

Crystal Output

Buffered Oscillator Output

External Wakeup from Hibernate Output

Reset

B

C

A

NMI

I

Non-maskable Interrupt (Pull high when unused.)

Supplies

V_DDINT

P

Internal Power Supply

External Power Supply

External DDR Power Supply

External USB Power Supply

RTC Clock Supply

12

V_DDEXT

V_DDDDR

V_DDUSB

12

V_DDRTC

Rev. C

|

Page 32 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 12. Pin Descriptions (Continued)

Driver

Type²

Pin Name

V_DDVR

I/O¹Function (First/Second/Third/Fourth)

13

P

Internal Voltage Regulator Power Supply (Connect to V_DDEXT

when unused.)

GND

V_DDMP

G

P

Ground

12

MXVR PLL Power Supply. (Must be driven to same level as V_DDINT. Connect

to V_DDINTwhen unused or when MXVR is not present.)

MXVR PLL Ground (Connect to GND when unused or when MXVR is not

present.)

12

GND_MP

G

¹I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.

²Refer to Table 61 on Page 86 through Table 70 on Page 87 for driver types.

³To use the SPI memory boot, SPI0SCK should have a pulldown, SPI0MISO should have a pullup, and SPI0SEL1 is used as the CS with a pullup.

⁴HWAIT/HWAITA should be pulled high or low to configure polarity. See Booting Modes on Page 19.

⁵GPW functionality is available when MXVR is not present or unused.

⁶This pin should not be used as GPIO if booting in mode 1.

⁷This pin should always be enabled as ND_CE in software and pulled high with a resistor when using NAND flash.

⁸This pin should always be enabled as BR in software and pulled high to enable asynchronous access.

⁹This pin must be pulled low through a 10kOhm resistor if self-refresh mode is desired during hibernate state or deep-sleep mode.

¹⁰If the USB is used in device mode only, the USB_ID pin should be either pulled high or left unconnected.

¹¹This pin is an output only during initialization of USB OTG session request pulses. Therefore, host mode or OTG type A mode requires that an external voltage source of

5 V, at 8 mA or more per the OTG specification, be applied to this pin. Other OTG modes require that this external voltage be disabled.

¹²To ensure proper operation, the power pins should be driven to their specified level even if the associated peripheral is not used in the application.

¹³This pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to V_DDEXT. Otherwise it should be powered according to the

VDDVR specification. For automotive grade models, the internal voltage regulator must not be used and this pin must be tied to V_DDEXT

.

Rev. C

|

Page 33 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

SPECIFICATIONS

Component specifications are subject to change without notice.

OPERATING CONDITIONS

Parameter

V_DDINT

Conditions

Min

0.9

Nominal

Max

1.43

1.38

1.31

3.6

Unit

V

1, 2

Internal Supply Voltage

External Supply Voltage

USB External Supply Voltage

MXVR PLL Supply Voltage

Nonautomotive grade models

Automotive grade models

Mobile DDR SDRAM models

Nonautomotive 3.3 V I/O

Nonautomotive 2.5 V I/O

Automotive grade models

1.0

V

1.14

2.7

V

3

V_DDEXT

3.3

2.5

3.3

V

2.25

2.7

2.75

3.6

V

V_DDUSB

V_DDMP

3.0

3.6

V

Nonautomotive grade models

Automotive grade models

0.9

1.43

1.38

3.6

V

1.0

V

V_DDRTC

V_DDDDR

Real Time Clock Supply Voltage Nonautomotive grade models

Real Time Clock Supply Voltage Automotive grade models

2.25

2.7

V

3.3

2.6

3.6

V

DDR Memory Supply Voltage

DDR SDRAM models

2.5

2.7

V

Mobile DDR SDRAM models

1.8

1.875

3.3

1.95

3.6

V

4

V_DDVR

Internal Voltage Regulator

Supply Voltage

2.7

V

V_IH

High Level Input Voltage^{5, 6}

High Level Input Voltage⁷

High Level Input Voltage⁸

High Level Input Voltage ^{9, 13}

High Level Input Voltage¹⁰

Low Level Input Voltage^{5, 11}

Low Level Input Voltage¹²

Low Level Input Voltage⁷

Low Level Input Voltage^{9, 13}

DDR_VREF Pin Input Voltage

V_DDEXT= maximum

2.0

3.6

V

V_IHDDR

DDR SDRAM models

Mobile DDR SDRAM models

V_DDEXT= maximum

V_{DDR_VREF}+ 0.15

V_{DDR_VREF}+ 0.125

2.0

V_DDDDR+ 0.3

12

V_IH5V

5.5

V_IHTWI

V_IHUSB

V_IL

V_DDEXT= maximum

0.7 x V_DDEXT

5.5

5.25

V_DDEXT= minimum

–0.3

0.6

V_IL5V

3.3 V I/O, V_DDEXT= minimum

2.5 V I/O, V_DDEXT= minimum

DDR SDRAM models

0.8

0.6

–0.3

V_ILDDR

–0.3

V_{DDR_VREF}– 0.15

Mobile DDR SDRAM models

–0.3

V_{DDR_VREF}– 0.125 V

V_ILTWI

–0.3

0.3 x V_DDEXT

V

V_{DDR_VREF}

0.49 x V_DDDDR

0.50 x

V_DDDDR

0.51 x V_DDDDR

T_J¹⁴

Junction Temperature

(400/533 MHz)

400-Ball Chip Scale Package Ball

–40

0

+105

+90

^ºC

Grid Array (CSP_BGA) @T_AMBIENT

=

–40^ºC to +85^ºC

Junction Temperature (600 MHz) 400-Ball Chip Scale Package Ball

^ºC

Grid Array (CSP_BGA) @T_AMBIENT

=

0^ºC to +70^ºC

¹See Table 13 on Page 35 for frequency/voltage specifications.

²V_DDINTmaximum is 1.10 V during one-time-programmable (OTP) memory programming operations.

³V_DDEXTminimum is 3.0 V and maximum is 3.6 V during OTP memory programming operations.

⁴Use of the internal voltage regulator is not supported on 600 MHz speed grade models or on automotive grade models. An external voltage regulator must be used.

⁵Bidirectional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input pins (ATAPI_PDIAG, USB_ID, TCK, TDI,

TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0) of the ADSP-BF54x Blackfin processors are 3.3 V-tolerant (always accept up to 3.6 V maximum V_IH). Voltage

compliance (on outputs, V_OH) is limited by the V_DDEXTsupply voltage. The regulator can generate V_DDINTat levels of 0.90 V to 1.30 V with -5% to +5% tolerance.

⁶Parameter value applies to all input and bidirectional pins except PB1-0, PE15-14, PG15–11, PH7-6, DQ0-15, and DQS0-1.

Rev. C

|

Page 34 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

⁷Parameter value applies to pins DQ0–15 and DQS0–1.

⁸PB1-0, PE15-14, PG15-11, and PH7-6 are 5.0 V-tolerant (always accept up to 5.5 V maximum V_IHwhen power is applied to V_DDEXTpins). Voltage compliance (on output

V_OH) is limited by V_DDEXTsupply voltage.

⁹SDA and SCL are 5.0V tolerant (always accept up to 5.5V maximum V_IH). Voltage compliance on outputs (V_OH) is limited by the _VDDEXTsupply voltage.

¹⁰Parameter value applies to USB_DP, USB_DM, and USB_VBUS pins. See Absolute Maximum Ratings on Page 40.

¹¹Parameter value applies to all input and bidirectional pins, except PB1-0, PE15-14, PG15–11, and PH7-6.

¹²Parameter value applies to pins PG15–11 and PH7-6.

¹³Parameter value applies to pins PB1-0 and PE15-14. Consult the I²C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.

¹⁴T_Jmust be in the range: 0°C < T_J< 55°C during OTP memory programming operations.

Table 13 and Table 16 describe the voltage/frequency require-

ments for the ADSP-BF54x Blackfin processors’ clocks. Take

care in selecting MSEL, SSEL, and CSEL ratios so as not to

exceed the maximum core clock and system clock. Table 15

describes the phase-locked loop operating conditions.

Table 13. Core Clock Requirements—533 MHz and 600 MHz Speed Grade¹

Parameter

f_CCLK

Condition

Internal Regulator Setting²

Max

600

533

500

444

400

333

Unit

MHz

Core Clock Frequency

V_DDINT= 1.30 V minimum

V_DDINT= 1.20 V minimum

V_DDINT= 1.14 V minimum

N/A²

f_CCLK

1.25 V

1.20 V

f_CCLK

V_DDINT= 1.045 V minimum 1.10 V

f_CCLK

V_DDINT= 0.95 V minimum

V_DDINT= 0.90 Vminimum

1.00 V

0.95 V

f_CCLK

¹See the Ordering Guide on Page 100.

²Use of an internal voltage regulator is not supported on automotive grade and 600 MHz speed grade models

Table 14. Core Clock Requirements—400 MHz Speed Grade¹

Parameter

f_CCLK

Condition

Internal Regulator Setting²Max

Unit

Core Clock Frequency

V_DDINT= 1.14 V minimum

V_DDINT= 1.045 V minimum

V_DDINT= 0.95 V minimum

V_DDINT= 0.90 V minimum

1.20 V

1.10 V

1.00 V

0.95 V

400

364

333

300

MHz

f_CCLK

¹See Ordering Guide on Page 100

²Use of an internal voltage regulator is not supported on automotive grade models

Table 15. Phase-Locked Loop Operating Conditions

Parameter

f_VCO

Min

50

Max

Maximum f_CCLK

Unit

MHz

Voltage Controlled Oscillator (VCO) Frequency

Table 16. System Clock Requirements

DDR SDRAM Models Mobile DDR SDRAM Models

Parameter Condition

Max

133²

100

Min

120³

N/A⁴

Max

133²

N/A⁴

Unit

MHz

f_SCLK

V_DDINT≥ 1.14 V¹

f_SCLK

V_DDINT< 1.14 V¹

¹f_SCLKmust be less than or equal to f_CCLK

.

²Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 26 on Page 43.

³Rounded number. Actual test specification is SCLK period of 8.33 ns.

⁴V_DDINTmust be greater than or equal to 1.14 V for mobile DDR SDRAM models. See Operating Conditions on Page 34.

Rev. C

|

Page 35 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ELECTRICAL CHARACTERISTICS

Nonautomotive 400 MHz¹

All Other Devices²

Parameter

Test Conditions

Min

Typ

Max

Min

Typ

Max

Unit

V_OH

High Level Output

V_DDEXT= 2.7 V,

2.4

V

Voltage for 3.3 V I/O³I_OH= –0.5 mA

High Level Output

V_DDEXT= 2.25 V,

2.0

V

Voltage for 2.5 V I/O³I_OH= –0.5 mA

V_OHDDR

High Level Output

Voltage for DDR

SDRAM⁴

V_DDDDR= 2.5 V,

I_OH= –8.1 mA

1.74

High Level Output

Voltage for Mobile

DDR SDRAM⁴

V_DDDDR= 1.8 V,

I_OH= –0.1 mA

1.62

V

V_OL

Low Level Output

V_DDEXT= 2.7 V,

0.4

V

Voltage for 3.3 V I/O³I_OL= 2.0 mA

Low Level Output

V_DDEXT= 2.25 V,

I_OL= 2.0 mA

Voltage for 2.5 V I/O³

V_OLDDR

Low Level Output

Voltage for DDR

SDRAM⁴

V_DDDDR= 2.5 V,

I_OL= 8.1 mA

0.56

Low Level Output

Voltage for Mobile

DDR SDRAM⁴

V_DDDDR= 1.8 V,

I_OL= 0.1 mA

0.18

V

I_IH

High Level Input

Current⁵

V_DDEXT=3.6 V,

V_IN= V_INMax

10.0

50.0

30.0

10.0

50.0

30.0

μA

I_IHP

High Level Input

Current⁶

V_DDEXT=3.6 V,

V_IN= V_INMax

I_{IHDDR_VREF}

High Level Input

Current for DDR

SDRAM⁷

V_DDDDR=2.7 V,

V_IN= 0.51 × V_DDDDR

High Level Input

Current for Mobile

DDR SDRAM⁷

V_DDDDR=1.95 V,

V_IN= 0.51 × V_DDDDR

30.0

μA

8

I_IL

Low Level Input

Current

V_DDEXT=3.6 V, V_IN= 0 V

10.0

8¹²

10.0

8¹²

μA

pF

9

I_OZH

Three-State Leakage V_DDEXT=3.6 V,

Current¹⁰

V_IN= V_INMax

11

I_OZL

Three-State Leakage V_DDEXT=3.6 V, V_IN= 0 V

Current¹⁰

C_IN

Input Capacitance¹²f_IN= 1 MHz,

T_AMBIENT= 25°C,

4¹²

22

4¹²

37

V_IN= 2.5 V

13

I_DDDEEPSLEEP

V_DDINTCurrent in Deep V_DDINT= 1.0 V,

mA

Sleep Mode

f_CCLK= 0 MHz,

f_SCLK= 0 MHz,

T_J= 25°C, ASF = 0.00

I_DDSLEEP

V_DDINTCurrent in Sleep V_DDINT= 1.0 V,

Mode _SCLK= 25 MHz,

T_J= 25°C

V_DDINTCurrent in Idle V_DDINT= 1.0 V,

_CCLK= 50 MHz,

35

44

50

59

mA

f

I_DD-IDLE

f

T_J= 25°C,

ASF = 0.47

Rev. C

|

Page 36 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Nonautomotive 400 MHz¹

All Other Devices²

Parameter

Test Conditions

Min

Typ

Max

Min

Typ

Max

Unit

I_DD-TYP

V_DDINTCurrent

V_DDINT= 1.10 V,

145

178

mA

f

_CCLK= 300 MHz,

f_SCLK= 25 MHz,

T_J= 25°C,

ASF = 1.00

I_DD-TYP

V_DDINT= 1.20 V,

f_CCLK= 400 MHz,

f_SCLK= 25 MHz,

T_J= 25°C,

199

239

301

360

60

mA

µA

ASF = 1.00

V_DDINT= 1.25 V,

f_CCLK= 533 MHz,

f_SCLK= 25 MHz,

T_J= 25°C,

ASF = 1.00

V_DDINT= 1.35 V,

f

_CCLK= 600 MHz,

f_SCLK= 25 MHz,

T_J= 25°C,

ASF = 1.00

13, 14

I_DDHIBERNATE

Hibernate State

Current

V_DDEXT= V_DDVR= V_DDUSB

= 3.30 V,

60

V_DDDDR= 2.5 V,

T_J= 25°C,

CLKIN= 0 MHz with

voltage regulator off

(V_DDINT= 0 V)

I_DDRTC

V_DDRTCCurrent

V_DDRTC= 3.3 V, T_J= 25°C

V_DDUSB= 3.3 V,

20

9

20

9

µA

mA

I_DDUSB-FS

V_DDUSBCurrent in

Full/Low Speed Mode T_J= 25°C, Full Speed

USB Transmit

I_DDUSB-HS

V_DDUSBCurrent in High V_DDUSB= 3.3 V,

25

mA

Speed Mode

T_J= 25°C, High Speed

USB Transmit

13, 15

I_DDDEEPSLEEP

V_DDINTCurrent in Deep f_CCLK= 0 MHz,

Sleep Mode f_SCLK= 0 MHz

V_DDINITCurrent in Sleep f_CCLK= 0 MHz,

Table 17

Table 18 mA

13, 15

I_DDSLEEP

I_DDDEEPSLEEP

I_DDDEEPSLEEPmA¹⁶

Mode

f_SCLK> 0 MHz

+ (0.77 ×

V_DDINT

×

V_DDINT×

16

f_SCLK

)

f_SCLK

)

15, 17

I_DDINT

V_DDINTCurrent

f_CCLK> 0 MHz,

f_SCLK> 0 MHz

I_DDSLEEP

(Table 20

× ASF)

+

I_DDSLEEP+ mA

(Table 20

× ASF)

¹Applies to all nonautomotive 400 MHz speed grade models. See Ordering Guide.

²Applies to all 533 MHz and 600 MHz speed grade models and automotive 400 MHz speed grade models. See Ordering Guide.

³Applies to output and bidirectional pins, except USB_VBUS and the pins listed in table note 4.

⁴Applies to pins DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE.

⁵Applies to all input pins except JTAG inputs.

⁶Applies to JTAG input pins (TCK, TDI, TMS, TRST).

⁷Applies to DDR_VREF pin.

⁸Absolute value.

⁹For DDR pins (DQ0-15, DQS0-1), test conditions are V_DDDDR= Maximum, V_IN= V_DDDDRMaximum.

¹⁰Applies to three-statable pins.

¹¹For DDR pins (DQ0-15, DQS0-1), test conditions are V_DDDDR= Maximum, V_IN= 0V.

¹²Guaranteed, but not tested

Rev. C

|

Page 37 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

¹³See the ADSP-BF54x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.

¹⁴Includes current on V_DDEXT, V_DDUSB, V_DDVR, and V_DDDDRsupplies. Clock inputs are tied high or low.

¹⁵Guaranteed maximum specifications.

¹⁶Unit for V_DDINTis V (volts). Unit for f_SCLKis MHz. Example: 1.2 V, 133 MHz would be 0.77 × 1.2 × 133 = 122.9 mA added to I_DDDEEPSLEEP

.

¹⁷See Table 19 for the list of I_DDINTpower vectors covered.

Total power dissipation has two components:

• Static, including leakage current

• Dynamic, due to transistor switching characteristics

Many operating conditions can also affect power dissipation,

including temperature, voltage, operating frequency, and pro-

cessor activity. Electrical Characteristics on Page 36 shows the

current dissipation for internal circuitry (V_DDINT). I_DDDEEPSLEEP

specifies static power dissipation as a function of voltage

(V_DDINT) and temperature (see Table 17 and Table 18), and

I_DDINTspecifies the total power specification for the listed test

conditions, including the dynamic component as a function of

voltage (V_DDINT) and frequency (Table 20).

There are two parts to the dynamic component. The first part is

due to transistor switching in the core clock (CCLK) domain.

This part is subject to an activity scaling factor (ASF) which rep-

resents application code running on the processor core and

L1/L2 memories (Table 19). The ASF is combined with the

CCLK frequency and V_DDINTdependent data in Table 20 to cal-

culate this part. The second part is due to transistor switching in

the system clock (SCLK) domain, which is included in the I_DDINT

specification equation.

Table 17. Static Current—Nonautomotive 400 MHz Speed Grade Devices (mA)¹

2

Voltage (V_DDINT

)

T_J(°C)²0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.38 V 1.40 V 1.43 V

-40

0

11.9

20.1

31.2

47.0

58.6

80.7

107.0

153.9

171.7

13.5

22.3

34.2

51.0

63.1

86.6

114.3

163.0

181.5

15.5

24.7

37.5

55.5

68.3

93.0

122.5

173.3

192.7

17.7

20.3

23.3

26.8

30.6

35.0

39.9

43.2

45.5

49.5

27.8

31.1

34.9

39.3

44.2

49.6

55.7

59.8

62.5

67.2

25

45

55

70

85

100

105

41.3

45.6

50.3

55.7

61.7

68.2

75.4

80.3

83.6

88.6

60.6

66.0

72.0

78.8

86.1

94.2

102.9

122.0

158.7

202.7

272.4

299.3

108.9

128.4

166.4

211.8

283.4

308.7

112.8

132.8

171.6

218.0

290.8

314.9

118.2

140.0

179.5

226.7

300.6

325.7

74.1

80.3

87.1

94.9

103.0

136.0

175.3

239.0

263.6

112.0

146.8

188.5

255.1

280.9

100.2

131.5

184.8

205.1

108.1

141.2

197.0

218.3

116.7

151.7

210.0

232.4

125.9

163.1

224.1

247.5

¹Values are guaranteed maximum I_DDDEEPSLEEPfor nonautomotive 400 MHz speed-grade devices.

²Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 34.

Table 18. Static Current—Automotive 400 MHz and All 533 MHz/600 MHz Speed Grade Devices (mA)¹

2

Voltage (V_DDINT

)

T_J(°C)²

-40

0

0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.38 V 1.40 V 1.43 V

19.7

22.1

24.8

27.9

31.4

35.4

39.9

45.0

50.6

57.0

61.2

64.0

70.4

45.2

49.9

55.2

61.3

67.9

75.3

83.5

92.6

102.6

169.2

247.6

299.7

394.3

516.5

654.8

711.1

113.6

185.4

269.6

325.9

427.7

557.5

704.7

763.9

121.0

196.1

284.0

343.1

449.4

584.2

737.0

798.5

125.8

203.3

293.6

354.6

463.9

602.0

758.5

821.6

135.0

218.0

312.0

374.0

489.0

629.0

793.0

864.0

25

80.0

87.5

96.2

105.8

160.7

197.7

264.1

350.2

452.1

494.3

116.4

175.3

214.9

285.8

378.5

486.9

531.7

127.9

191.2

233.8

309.4

408.9

524.4

571.9

140.4

208.6

254.2

334.8

442.1

564.8

614.9

154.1

227.3

276.1

363.5

477.9

608.2

661.5

45

124.2

154.6

209.8

281.8

366.5

403.8

134.8

167.2

225.6

301.3

390.5

428.3

147.1

181.7

243.9

323.5

419.4

459.5

55

70

85

100

105

¹Values are guaranteed maximum I_DDDEEPSLEEPfor automotive 400 MHz and all 533 MHz and 600 MHz speed grade devices.

²Valid temperature and voltage ranges are model-specific. See Operating Conditions on Page 34.

Rev. C

|

Page 38 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 19. Activity Scaling Factors¹

I_DDINTPower Vector

I_DD-PEAK

Activity Scaling Factor (ASF)

1.29

1.24

1.00

0.87

0.74

0.47

I_DD-HIGH

I_DD-TYP

I_DD-APP

I_DD-NOP

I_DD-IDLE

¹See Estimating Power for ADSP-BF534/BF536/BF537 Blackfin Processors

(EE-297). The power vector information also applies to the ADSP-

BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 processors.

Table 20. Dynamic Current in CCLK Domain (mA, with ASF = 1.0)¹

2

Voltage (V_DDINT

)

f_CCLK

(MHz)²

100

0.90 V 0.95 V 1.00 V 1.05 V 1.10 V 1.15 V 1.20 V 1.25 V 1.30 V 1.35 V 1.38 V 1.40 V 1.43 V

29.7

55.3

80.8

N/A

31.6

58.9

85.8

112.2

N/A

33.9

62.5

91.0

119.4

N/A

35.7

66.0

96.0

125.5

N/A

37.9

70.0

101.3

132.4

N/A

40.5

42.9

45.5

48.2

50.8

52.0

53.5

54.6

200

74.0

78.3

82.5

86.7

91.3

93.3

95.6

97.6

300

107.0

139.6

171.9

N/A

112.8

146.9

180.6

191.9

N/A

118.7

154.6

189.9

201.6

N/A

124.6

162.3

199.1

211.5

233.1

130.9

170.0

205.7

218.0

241.4

133.8

173.8

210.3

222.8

246.7

137.0

177.8

213.0

225.7

252.7

140.0

181.6

217.6

230.5

258.1

400

500

533

N/A

600

N/A

¹Thevaluesarenotguaranteedasstand-alonemaximum specifications. They mustbecombined withstatic current per theequations ofElectrical Characteristics onPage 36.

²Valid frequency and voltage ranges are model-specific. See Operating Conditions on Page 34.

Rev. C

|

Page 39 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

the Total Current Pin Groups table. Note that the V_OLand V_OH

ABSOLUTE MAXIMUM RATINGS

specifications have separate per-pin maximum current require-

ments, see the Electrical Characteristics table.

Stresses greater than those listed in Table 21 may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reli-

ability. Table 22 details the maximum duty cycle for input

transient voltage.

Table 23. Total Current Pin Groups

Group Pins in Group

1

2

3

PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10,

PA11

PA12, PA13, PA14, PA15, PB8, PB9, PB10, PB11, PB12,

PB13, PB14

Table 21. Absolute Maximum Ratings

PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, BMODE0,

BMODE1, BMODE2, BMODE3

Internal (Core) Supply Voltage (V_DDINT) –0.3 V to +1.43 V

External (I/O) Supply Voltage (V_DDEXT) –0.3 V to +3.8 V

4

TCK, TDI, TDO, TMS, TRST, PD14, EMU

PD8, PD9, PD10, PD11, PD12, PD13, PD15

PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7

PE11, PE12, PE13, PF12, PF13, PF14, PF15, PG3, PG4

PF4, PF5, PF6, PF7, PF8, PF9, PF10, PF11

PF0, PF1, PF2, PF3, PG0, PG1, PG2

PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7

PH5, PH6, PH7

Input Voltage^{1, 2, 3}

–0.5 V to +3.6 V

–0.5 V to V_DDEXT+0.5 V

40 mA (max)

5

Output Voltage Swing

I_OH/I_OLCurrent per Single Pin⁴

6

7

I

_OH/I_OLCurrent per Pin Group⁴

80 mA (max)

8

Storage Temperature Range

–65^ºC to +150^ºC

9

Junction Temperature Underbias

+125^ºC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

¹AppliestoallbidirectionalandinputonlypinsexceptPB1-0, PE15-14, PG15–11,

and PH7-6, where the absolute maximum input voltage range is –0.5 V to

+5.5 V.

A1, A2, A3

²Pins USB_DP, USB_DM, and USB_VBUS are 5 V-tolerant when VDDUSB is

powered according to the operating conditions table. If VDDUSB supply

voltage does not meet the specification in the operating conditions table, these

pins could suffer long-term damage when driven to +5 V. If this condition is

seen in the application, it can be corrected with additional circuitry to use the

external host to power only the V_DDUSBpins. Contact factory for application

detail and reliability information.

PH8, PH9, PH10, PH11, PH12, PH13

PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7

PI8, PI9, PI10, PI11, PI12, PI13, PI14, PI15

AMS0, AMS1, AMS2, AMS3, AOE, CLKBUF, NMI

CLKIN, XTAL, RESET, RTXI, RTXO, ARE, AWE

D0, D1, D2, D3, D4, D5, D6, D7

³Applies only when V_DDEXTis within specifications. When V_DDEXTis outside speci-

fications, the range is V_DDEXT0.2 V.

⁴For more information, see description preceding Table 23.

D8, D9, D10, D11, D12

D13, D14, D15, ABE0, ABE1

Table 22. Maximum Duty Cycle for Input¹Transient Voltage

EXT_WAKE, CLKOUT, PJ11, PJ12, PJ13

PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, ATAPI_PDIAG

PJ8, PJ9, PJ10, PE7, PG12, PG13

V_INMax (V)²

3.63

V_INMin (V)

–0.33

Maximum Duty Cycle

100%

48%

30%

20%

10%

8%

PE0, PE1, PE2, PE4, PE5, PE6, PE8, PE9, PE10, PH3, PH4

3.80

–0.50

PH0, PH2, PE14, PE15, PG5, PG6, PG7, PG8, PG9, PG10,

PG11

3.90

–0.60

4.00

–0.70

26

PC8, PC9, PC10, PC11, PC12, PC13, PE3, PG14, PG15, PH1

4.10

–0.80

4.20

–0.90

4.30

–1.00

5%

¹Does not apply to CLKIN. Absolute maximum for pins PB1-0, PE15-14, PG15-

11, and PH7-6 is +5.5V.

²Only one of the listed options can apply to a particular design.

The Absolute Maximum Ratings table specifies the maximum

total source/sink (I_OH/I_OL) current for a group of pins. Perma-

nent damage can occur if this value is exceeded. To understand

this specification, if pins PA4, PA3, PA2, PA1 and PA0 from

group 1 in the Total Current Pin Groups table were sourcing or

sinking 2 mA each, the total current for those pins would be

10 mA. This would allow up to 70 mA total that could be

sourced or sunk by the remaining pins in the group without

damaging the device. For a list of all groups and their pins, see

Rev. C

|

Page 40 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive device.

Charged devices and circuit boards can discharge

without detection. Although this product features

patented or proprietary protection circuitry, damage

may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to

avoid performance degradation or loss of functionality.

PACKAGE INFORMATION

The information presented in Figure 9 and Table 24 provides

information related to specific product features. For a complete

listing of product offerings, see the Ordering Guide on

Page 100.

a

ADSP-BF54x(M)

tppZ-cc

vvvvvv.x-q n.n

# yywwcountry_of_origin

B

Figure 9. Product Information on Package

Table 24. Package Information

Brand Key

Description

BF54x

x = 2, 4, 7, 8 or 9

(M)

Mobile DDR Indicator (optional)

Temperature Range

Package Type

t

pp

Z

RoHS Compliant part

See Ordering Guide

Assembly Lot Code

Silicon Revision

cc

vvvvvv.x-q

n.n

#

RoHS Compliant Designation

Date Code

yyww

Rev. C

|

Page 41 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

TIMING SPECIFICATIONS

Timing specifications are detailed in this section.

Clock and Reset Timing

Table 25 and Figure 10 describe Clock Input and Reset Timing.

Table 26 and Figure 11 describe Clock Out Timing.

Table 25. Clock Input and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

t_CKIN

CLKIN Period^{1, 2, 3, 4}

20.0

8.0

100.0

ns

t_CKINL

t_CKINH

t_BUFDLAY

t_WRST

CLKIN Low Pulse²

CLKIN High Pulse²

8.0

CLKIN to CLKBUF Delay

RESET Asserted Pulsewidth Low⁵

RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)^6,7,8,96100 t_CKIN+ 7900 t_SCLK

RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)^7,10,116100 t_CKIN

10

11 t_CKIN

t_RHWFT

7000 t_CKIN

¹Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f_VCO, f_CCLK, and f_SCLKsettings discussed in Table 16 and Table 13 on Page 35.

²Applies to PLL bypass mode and PLL non-bypass mode.

³CLKIN frequency and duty cycle must not change on the fly.

⁴If the DF bit in the PLL_CTL register is set, then the maximum t_CKINperiod is 50 ns.

⁵Applies after power-up sequence is complete. See Table 27 and Figure 12 for more information about power-up reset timing.

⁶Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming.

⁷Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 t_CKIN(typically).

⁸Applies only to boot modes BMODE=1, 2, 4, 6, 7, 10, 11, 14, 15.

⁹Use default t_SCLKvalue unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new t_SCLKvalue and add PLL_LOCKCNT settle time.

¹⁰When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the

HWAIT or HWAITA to simulate reset output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high performance

mode during reset.

¹¹Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot mode

BMODE = 0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease.

t_CKIN

CLKIN

t_BUFDLAY

t_CKINL

t_CKINH

t_BUFDLAY

CLKBUF

RESET

t_WRST

t_RHWFT

HWAIT (A)

Figure 10. Clock and Reset Timing

Rev. C

|

Page 42 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 26. Clock Out Timing

Parameter

Min

Max

Unit

Switching Characteristics

t_SCLK

CLKOUT Period^1,2

7.5

2.5

ns

t_SCLKH

t_SCLKL

CLKOUT Width High

CLKOUT Width Low

¹The t_SCLKvalue is the inverse of the f_SCLKspecification. Reduced supply voltages affect the best-case value of 7.5 ns listed here.

²The t_SCLKvalue does not account for the effects of jitter.

t_SCLK

CLKOUT

t_SCLKL

t_SCLKH

Figure 11. CLKOUT Interface Timing

Table 27. Power-Up Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

t_{RST_IN_PWR}RESET Deasserted After the V_DDINT, V_DDEXT, V_DDDDR,V_DDUSB,V_DDRTC,V_DDVR,V_DDMP, and 3500 × t_CKIN

ns

CLKIN Pins Are Stable and Within Specification

t_{RST_IN_PWR}

RESET

CLKIN

V

DD_SUPPLIES

In Figure 12, V_{DD_SUPPLIES}is V_DDINT, V_DDEXT, V_DDDDR, V_DDUSB, V_DDRTC, V_DDVR, and V_DDMP

.

Figure 12. Power-Up Reset Timing

Rev. C

|

Page 43 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Asynchronous Memory Read Cycle Timing

Table 28 and Table 29 on Page 45 and Figure 13 and Figure 14

on Page 45 describe asynchronous memory read cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 28. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

DATA15–0 Setup Before CLKOUT

5.0

0.8

5.0

0.0

ns

t_HDAT

t_SARDY

t_HARDY

DATA15–0 Hold After CLKOUT

ARDY Setup Before the Falling Edge of CLKOUT

ARDY Hold After the Falling Edge of CLKOUT

Switching Characteristics

t_DO

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

6.0

ns

t_HO

0.3

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.

SETUP

PROGRAMMED READ

ACCESS EXTENDED

3 CYCLES

HOLD

2 CYCLES

ACCESS 4 CYCLES

1 CYCLE

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

ADDR19–1

AOE

ARE

t_DO

t_HO

t_HARDY

t_SARDY

t_HARDY

ARDY

t_SARDY

t_SDAT

t_HDAT

DATA 15–0

Figure 13. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Rev. C

|

Page 44 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 29. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

t_HDAT

t_DANR

t_HAA

DATA15–0 Setup Before CLKOUT

5.0

0.8

ns

DATA15–0 Hold After CLKOUT

ARDY Negated Delay from AMSx Asserted¹

(S + RA – 2) × t_SCLKns

ARDY Asserted Hold After ARE Negated

0.0

0.3

ns

Switching Characteristics

t_DO

Output Delay After CLKOUT²

Output Hold After CLKOUT²

6.0

ns

t_HO

¹S = number of programmed setup cycles, RA = number of programmed read access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and ARE.

SETUP

PROGRAMMED READ

ACCESS 4 CYCLES

ACCESS EXTENDED

3 CYCLES

HOLD

2 CYCLES

1 CYCLE

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

ADDR19–1

AOE

ARE

t_DO

t_HO

t_DANR

t_HAA

ARDY

t_SDAT

t_HDAT

DATA 15–0

Figure 14. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Rev. C

|

Page 45 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Asynchronous Memory Write Cycle Timing

Table 30 and Table 31 on Page 47 and Figure 15 and Figure 16

on Page 47 describe asynchronous memory write cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 30. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

Switching Characteristics

ARDY Setup Before the Falling Edge of CLKOUT

5.0

0.0

ns

ARDY Hold After the Falling Edge of CLKOUT

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

0.0

0.3

t_HO

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, and AWE.

PROGRAMMED ACCESS

SETUP

2 CYCLES

WRITE ACCESS EXTEND HOLD

2 CYCLES

1 CYCLE 1 CYCLE

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

ADDR19–1

t_DO

t_HO

AWE

t_SARDYt_HARDY

ARDY

t_HARDY

t_ENDAT

t_SARDY

t_DDAT

DATA 15–0

Figure 15. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Rev. C

|

Page 46 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 31. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_DANW

t_HAA

Switching Characteristics

ARDY Negated Delay from AMSx Asserted¹

(S + WA – 2) × t_SCLKns

ARDY Asserted Hold After AWE Negated

0.0

ns

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT²

Output Hold After CLKOUT²

0.0

0.3

t_HO

¹S = number of programmed setup cycles, WA = number of programmed write access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, and AWE.

PROGRAMMED

WRITE ACCESS

2 CYCLES

ACCESS

EXTENDED

2 CYCLES

SETUP

2 CYCLES

HOLD

1 CYCLE

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

ADDR19–1

t_DO

t_HO

AWE

t_DANW

t_HAA

ARDY

t_ENDAT

t_DDAT

DATA 15–0

Figure 16. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Rev. C

|

Page 47 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing

Table 32 and Figure 17 describe DDR SDRAM/mobile DDR

SDRAM clock and control cycle timing.

Table 32. DDR SDRAM/Mobile DDR SDRAM Clock and Control Cycle Timing

DDR SDRAM

Min

Mobile DDR SDRAM

Parameter

Max

Min

Max

Unit

Switching Characteristics

1

t_CK

t_CH

t_CL

DCK0-1 Period

7.50

0.45

1.00

2.20

7.50

0.45

1.00

2.30

8.33

0.55

ns

t_CK

ns

DCK0-1 High Pulse Width

0.55

DCK0-1 Low Pulse Width

2,3

t_AS

t_AH

Address and Control Output SETUP Time Relative to CK

Address and Control Output HOLD Time Relative to CK

Address and Control Output Pulse Width

2,3

t_OPW

¹The t_CKspecification does not account for the effects of jitter.

²Address pins include DA0-12 and DBA0-1.

³Control pins include DCS0-1, DCLKE, DRAS, DCAS, and DWE.

t_CK

t_CH

t_CL

DCK0-1

t_AS

t_AH

ADDRESS

CONTROL

t_OPW

NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE.

ADDRESS = DA0-12 AND DBA0-1.

Figure 17. DDR SDRAM /Mobile DDR SDRAM Clock and Control Cycle Timing

Rev. C

|

Page 48 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

DDR SDRAM/Mobile DDR SDRAM Timing

Table 33 and Figure 18/Figure 19 describe DDR

SDRAM/mobile DDR SDRAM read cycle timing.

Table 33. DDR SDRAM/Mobile DDR SDRAM Read Cycle Timing

DDR SDRAM

Min

Mobile DDR SDRAM

Parameter

Max

Min

Max

Unit

Timing Requirements

t_AC

Access Window of DQ0-15 to DCK0-1

–1.25

+1.25

0.90

0.0

6.00

0.85

ns

t_DQSCK

t_DQSQ

Access Window of DQS0-1 to DCK0-1

DQS0-1 to DQ0-15 Skew, DQS0-1 to Last

DQ0-15 Valid

t_QH

DQ0-15 to DQS0-1 Hold, DQS0-1 to First

DQ0-15 to Go Invalid

t_CK/2 – 1.25¹

t_CK/2 – 1.75²

0.9

t_CK/2 – 1.25

ns

t_RPRE

t_RPST

DQS0-1 Read Preamble

DQS0-1 Read Postamble

1.1

0.6

0.9

0.4

1.1

0.6

t_CK

0.4

¹For 7.50 ns ≤ t_CK< 10 ns.

²For t_CK≥ 10 ns.

t

DQSCK

DCK0-1

t

AC

DQS0-1

DQ0-15

t

RPST

RPRE

Dn

Dn+1

Dn+2

Dn+3

t

DQSQ

t

QH

Figure 18. DDR SDRAM Controller Read Cycle Timing

t

DQSCK

DCK0-1

t

AC

t

RPST

RPRE

DQS0-1

DQ0-15

Dn

Dn+1

Dn+2

Dn+3

t

DQSQ

t

QH

Figure 19. Mobile DDR SDRAM Controller Read Cycle Timing

Rev. C

|

Page 49 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing

Table 34 and Figure 20 describe DDR SDRAM/mobile DDR

SDRAM write cycle timing.

Table 34. DDR SDRAM/Mobile DDR SDRAM Write Cycle Timing

DDR SDRAM

Min

Mobile DDR SDRAM

Parameter

Max

Min

Max

Unit

Switching Characteristics

t_DQSS

t_DS

Write CMD to First DQS0-1

0.75

0.90

0.20

0.35

0.25

0.40

1.25

0.75

0.90

0.20

0.40

0.25

0.40

1.75

1.25

t_CK

ns

t_CK

ns

DQ0-15/DQM0-1 Setup to DQS0-1

DQ0-15/DQM0-1 Hold to DQS0-1

DQS0-1 Falling to DCK0-1 Rising (DQS0-1 Setup)

DQS0-1 Falling from DCK0-1 Rising (DQS0-1 Hold)

DQS0-1 High Pulse Width

t_DH

t_DSS

t_DSH

t_DQSH

t_DQSL

t_WPRE

t_WPST

t_DOPW

0.60

DQS0-1 Low Pulse Width

DQS0-1 Write Preamble

DQS0-1 Write Postamble

0.60

DQ0-15 and DQM0-1 Output Pulse Width (for Each) 1.75

DCK0-1

t

DSS

DSH

t

DQSS

DQS0-1

t

WPRE

t

WPST

DQSL

DQSH

t

DOPW

Dn

DQ0-15/DQM0-1

CONTROL

Dn+1

Dn+2

Dn+3

t

DH

DS

Write CMD

NOTE: CONTROL = DCS0-1, DCLKE, DRAS, DCAS, AND DWE.

Figure 20. DDR SDRAM /Mobile DDR SDRAM Controller Write Cycle Timing

Rev. C

|

Page 50 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

External Port Bus Request and Grant Cycle Timing

Table 35 and Table 36 on Page 52 and Figure 21 and Figure 22

on Page 52 describe external port bus request and grant cycle

operations for synchronous and for asynchronous BR.

Table 35. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Parameter

Min

Max

Unit

Timing Requirements

t_BS

t_BH

BR Asserted to CLKOUT Low Setup

5.0

0.0

ns

CLKOUT Low to BR Deasserted Hold Time

Switching Characteristics

t_SD

CLKOUT Low to AMSx, Address, and ARE/AWE Disable

5.0

4.0

3.6

ns

t_SE

CLKOUT Low to AMSx, Address, and ARE/AWE Enable

CLKOUT Low to BG Asserted Output Delay

CLKOUT Low to BG Deasserted Output Hold

CLKOUT Low to BGH Asserted Output Delay

CLKOUT Low to BGH Deasserted Output Hold

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT

t_BH

t_BS

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR 19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Rev. C

|

Page 51 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 36. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Parameter

Min

Max

Unit

Timing Requirements

t_WBR

BR Pulsewidth

2 x t_SCLK

ns

Switching Characteristics

t_SD

CLKOUT Low to AMSx, Address, and ARE/AWE Disable

5.0

4.0

3.6

ns

t_SE

CLKOUT Low to AMSx, Address, and ARE/AWE Enable

CLKOUT Low to BG Asserted Output Delay

CLKOUT Low to BG Deasserted Output Hold

CLKOUT Low to BGH Asserted Output Delay

CLKOUT Low to BGH Deasserted Output Hold

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT

t_WBR

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR 19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 22. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Rev. C

|

Page 52 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

NAND Flash Controller Interface Timing

Table 37 and Figure 23 on Page 54 through Figure 27 on

Page 56 describe NAND flash controller interface operations.

Table 37. NAND Flash Controller Interface Timing

Parameter

Min

Max

Unit

Write Cycle

Switching Characteristics

t_CWL

t_CH

t_CLHWL

t_CLH

t_ALLWL

ND_CE Setup Time to AWE Low

ND_CE Hold Time from AWE High

ND_CLE Setup Time High to AWE Low

ND_CLE Hold Time from AWE High

ND_ALE Setup Time Low to AWE Low

ND_ALE Hold Time from AWE High

AWE Low to AWE High

1.0 × t_SCLK– 4

3.0 × t_SCLK– 4

0.0

ns

2.5 × t_SCLK– 4

0.0

t_ALH

2.5 × t_SCLK– 4

(WR_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

(WR_DLY +5.0) × t_SCLK– 4

(WR_DLY +1.5) × t_SCLK– 4

2.5 × t_SCLK– 4

1

t_WP

t_WHWL

AWE High to AWE Low

1

t_WC

AWE Low to AWE Low

1

t_DWS

Data Setup Time for a Write Access

Data Hold Time for a Write Access

t_DWH

Read Cycle

Switching Characteristics

t_CRL

t_CRH

ND_CE Setup Time to ARE Low

1.0 × t_SCLK– 4

3.0 × t_SCLK– 4

(RD_DLY +1.0) × t_SCLK– 4

4.0 × t_SCLK– 4

(RD_DLY + 5.0) × t_SCLK– 4

ns

ND_CE Hold Time from ARE High

ARE Low to ARE High

1

t_RP

t_RHRL

ARE High to ARE Low

1

t_RC

ARE Low to ARE Low

Timing Requirements

t_DRSData Setup Time for a Read Transaction

t_DRHData Hold Time for a Read Transaction

8.0

0.0

ns

Write Followed by Read

Switching Characteristic

t_WHRL

AWE High to ARE Low

5.0 × t_SCLK– 4

ns

¹WR_DLY and RD_DLY are defined in the NFC_CTL register.

Rev. C

|

Page 53 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

t_CWL

t_CH

ND_CE

ND_CLE

t_CLEWL

t_ALEWL

t_CLH

t_ALH

ND_ALE

AWE

t_WP

t_DWH

t_DWS

ND_DATA

In Figure 23, ND_DATA is ND_D0–D15.

Figure 23. NAND Flash Controller Interface Timing—Command Wri Cycle

t_CWL

ND_CE

ND_CLE

ND_ALE

t_CLEWL

t_ALH

t_ALEWL

t_WP

t_WHWL

AWE

t_WC

t_DWS

t_DWH

t_DWS

t_DWH

ND_DATA

In Figure 24, ND_DATA is ND_D0–D15.

Figure 24. NAND Flash Controller Interface Timing—Address Write Cycle

Rev. C

|

Page 54 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

t_CWL

ND_CE

t_CLEWL

ND_CLE

ND_ALE

t_ALEWL

t_WP

t_WC

AWE

t_WP

t_WHWL

t_DWS

t_DWH

t_DWS

t_DWH

ND_DATA

In Figure 25, ND_DATA is ND_D0–D15.

Figure 25. NAND Flash Controller Interface Timing—Data Write Operation

t_CRL

t_CRH

ND_CE

ND_CLE

ND_ALE

t_RP

t_RC

ARE

t_RP

t_RHRL

t_DRS

t_DRH

t_DRS

t_DRH

ND_DATA

In Figure 26, ND_DATA is ND_D0–D15.

Figure 26. NAND Flash Controller Interface Timing—Data Read Operation

Rev. C

|

Page 55 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

t_CLWL

ND_CE

ND_CLE

t_CLEWL

t_CLH

t_WP

AWE

ARE

t_WHRL

t_RP

t_DWS

t_DWH

t_DRS

t_DRH

ND_DATA

In Figure 27, ND_DATA is ND_D0–D15.

Figure 27. NAND Flash Controller Interface Timing—Write Followed by Read Operation

Rev. C

|

Page 56 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Synchronous Burst AC Timing

Table 38 and Figure 28 on Page 57 describe Synchronous Burst

AC operations.

Table 38. Synchronous Burst AC Timing

Parameter

Min

Max

Unit

Timing Requirements

t_NDS

t_NDH

t_NWS

t_NWH

DATA15-0 Setup Before NR_CLK

DATA15-0 Hold After NR_CLK

WAIT Setup Before NR_CLK

WAIT Hold After NR_CLK

4.0

2.0

8.0

0.0

ns

Switching Characteristics

t_NDOAMSx, ABE1-0, ADDR19-1, NR_ADV, NR_OE Output Delay After NR_CLK

t_NHO

6.0

ns

ABE1-0, ADDR19-1 Output Hold After NR_CLK

–3.0

NR_CLK

t

NDO

AMSx

NHO

NDO

ABE1-0

t

NHO

ADDR19-1

DATA15-0

t

NDH

t

NDS

Dn

Dn+1 Dn+2 Dn+3

t

NDO

t

NDO

NR_ADV

t

NWS

NWH

WAIT

t

NDO

t

NDO

NR_OE

NOTE: NR_CLK dotted line represents a free running version of NR_CLK that is not visible on the NR_CLK pin.

Figure 28. Synchronous Burst AC Interface Timing

Rev. C

|

Page 57 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

External DMA Request Timing

Table 39 and Figure 29 describe the external DMA request tim-

ing operations.

Table 39. External DMA Request Timing

Parameter

Timing Parameters

t_DR

Min

Max

Unit

DMARx Asserted to CLKOUT High Setup

CLKOUT High to DMARx Deasserted Hold Time

DMARx Active Pulse Width

6.0

ns

t_DH

0.0

t_DMARACT

1.0 × t_SCLK

1.75 × t_SCLK

t_DMARINACT

DMARx Inactive Pulse Width

CLKOUT

t_DS

t_DH

DMAR0/1

(ACTIVE LOW)

t_DMARACT

t_DMARINACT

DMAR0/1

(ACTIVE HIGH)

Figure 29. External DMA Request Timing

Rev. C

|

Page 58 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Enhanced Parallel Peripheral Interface Timing

Table 40 and Figure 32 on Page 60, Figure 30 on Page 59,

Figure 33 on Page 60, and Figure 31 on Page 59 describe

enhanced parallel peripheral interface timing operations.

Table 40. Enhanced Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_PCLKW

t_PCLK

PPIx_CLK Width

PPIx_CLK Period

6.0

ns

13.3

Timing Requirements—GP Input and Frame Capture Modes

t_SFSPE

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Setup Before PPIx_CLK

External Frame Sync Hold After PPIx_CLK

Receive Data Setup Before PPIx_CLK

Receive Data Hold After PPIx_CLK

0.9

1.9

1.6

1.5

ns

Switching Characteristics—GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPIx_CLK

Internal Frame Sync Hold After PPIx_CLK

Transmit Data Delay After PPIx_CLK

Transmit Data Hold After PPIx_CLK

10.5

9.9

ns

2.4

DATA0 IS

DATA1 IS

SAMPLED

PPI_CLK

t_PCLKW

t_SFSPE

t_HFSPE

t_PCLK

PPI_FS1/2

PPI_DATA

t_SDRPE

t_HDRPE

Figure 30. EPPI GP Rx Mode with External Frame Sync Timing

DATA DRIVING/

FRAME SYNC

DATA DRIVING/

FRAME SYNC

SAMPLING EDGE

PPI_CLK

PPI_FS1/2

PPI_DATA

t_SFSPE

t_HFSPE

t_PCLKW

t_PCLK

t_DDTPE

t_HDTPE

Figure 31. EPPI GP Tx Mode with External Frame Sync Timing

Rev. C

|

Page 59 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

FRAME

SYNC IS

DRIVEN

OUT

DATA0 IS

SAMPLED

PPI_CLK

PPI_FS1/2

PPI_DATA

t_DFSPE

t_PCLKW

t_HOFSPE

t_PCLK

t_SDRPE

t_HDRPE

Figure 32. EPPI GP Rx Mode with Internal Frame Sync Timing

FRAME

SYNC IS

DRIVEN

OUT

DATA0 IS

DRIVEN

OUT

t_PCLK

PPI_CLK

PPI_FS1/2

PPI_DATA

t_DFSPE

t_PCLKW

t_HOFSPE

t_DDTPE

t_HDTPE

Figure 33. EPPI GP Tx Mode with Internal Frame Sync Timing

Rev. C

|

Page 60 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Serial Ports Timing

Table 41 through Table 44 on Page 63 and Figure 34 on Page 62

through Figure 37 on Page 63 describe serial port operations.

Table 41. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

3.0

ns

t_HFSE

TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

Receive Data Setup Before RSCLKx¹

Receive Data Hold After RSCLKx¹

3.0

t_SDRE

3.0

t_HDRE

t_SCLKEW

t_SCLKE

t_RCLKE

t_SUDTE

t_SUDRE

3.0

TSCLKx/RSCLKx Width

4.5

TSCLKx/RSCLKx Period

RSCLKx Period²

15.0

11.1

4 × t_SCLKE

4 × t_RCLKE

Start-Up Delay From SPORT Enable To First External TFSx

Start-Up Delay From SPORT Enable To First External RFSx

Switching Characteristics

t_DFSE

t_HOFSE

t_DDTE

t_HDTE

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)³

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)³

Transmit Data Delay After TSCLKx³

10.0

ns

0.0

Transmit Data Hold After TSCLKx³

¹Referenced to sample edge.

²For serial port receive with external clock and external frame sync only.

³Referenced to drive edge.

Table 42. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

t_HFSI

t_SDRI

t_HDRI

TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)¹

Receive Data Setup Before RSCLKx¹

10.0

–1.5

10.0

–1.5

ns

Receive Data Hold After RSCLKx¹

Switching Characteristics

t_DFSI

TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)²

Transmit Data Delay After TSCLKx²

3.0

ns

t_HOFSI

t_DDTI

–1.0

t_HDTI

Transmit Data Hold After TSCLKx²

–2.0

4.5

t_SCLKIW

TSCLKx/RSCLKx Width

¹Referenced to sample edge.

²Referenced to drive edge.

Rev. C

|

Page 61 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

TSCLKx

(INPUT)

t_SUDTE

TFSx

(INPUT)

RSCLKx

(INPUT)

t_SUDRE

RFSx

(INPUT)

FIRST

TSCLKx/RSCLKx

EDGE AFTER

SPORT ENABLED

Figure 34. Serial Port Start-Up with External Clock and Frame Sync

DATA RECEIVE—INTERNAL CLOCK

DATA RECEIVE—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

DRIVE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKIW

t_SCLKEW

RSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_HOFSE

RFSx

(OUTPUT)

t_SFSI

t_HFSI

t_SFSE

t_HFSE

RFSx

(INPUT)

t_HDRE

t_SDRI

t_HDRI

t_SDRE

DRx

DATA TRANSMIT—INTERNAL CLOCK

DRIVE EDGE

DATA TRANSMIT—EXTERNAL CLOCK

DRIVE EDGE SAMPLE EDGE

SAMPLE EDGE

t_SCLKE

t_SCLKIW

t_SCLKEW

TSCLKx

t_DFSI

t_DFSE

t_HOFSI

t_HOFSE

TFSx

(OUTPUT)

t_SFSI

t_HFSI

t_SFSE

t_HFSE

TFSx

(INPUT)

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DTx

Figure 35. Serial Ports

Rev. C

|

Page 62 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 43. Serial Ports—Enable and Three-State

Parameter

Min

0

Max

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TSCLKx¹

ns

Data Disable Delay from External TSCLKx^{1, 2}

Data Enable Delay from Internal TSCLKx¹

Data Disable Delay from Internal TSCLKx^{1, 2}

10.0

3.0

–2.0

¹Referenced to drive edge.

²Applicable to multichannel mode only.

DRIVE EDGE

TSCLKx

DTx

t_DTENE/I

t_DDTTE/I

Figure 36. Serial Ports—Enable and Three-State

Table 44. Serial Ports—External Late Frame Sync

Parameter

Min

Max

10.0

Unit

Switching Characteristics

t_DDTLFSE

Data Delay from Late External TFSx or External RFSx in multi-channel mode with MFD = 01^{1, 2}

Data Enable from External RFSx in multi-channel mode with MFD = 0^{1, 2}

ns

t_DTENLFSE

0

¹In multichannel mode, TFSx enable and TFSx valid follow t_DTENLFSand t_DDTLFSE

.

²If external RFS/TFS setup to RSCLK/TSCLK > t_SCLKE/2, then t_DDTE/Iand t_DTENE/Iapply; otherwise t_DDTLFSEand t_DTENLFSapply.

EXTERNAL RFSx IN MULTI-CHANNEL MODE

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

RSCLKx

RFSx

t_SFSE/I

t_HOFSE/I

t_DDTLFSE

t_DTENLFSE

DTx

1ST BIT

LATE EXTERNAL TFSx

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

TSCLKx

t_SFSE/I

t_HOFSE/I

TFSx

t_DDTLFSE

DTx

1ST BIT

Figure 37. Serial Ports—External Late Frame Sync

Rev. C

|

Page 63 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Serial Peripheral Interface (SPI) Port—Master Timing

Table 45 and Figure 38 describe SPI port master operations.

Table 45. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SPIxSCK Edge (Data Input Setup)

9.0

ns

SPIxSCK Sampling Edge to Data Input Invalid

–1.5

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

SPIxSELy Low to First SPIxSCK Edge

2t_SCLK–1.5

4t_SCLK–1.5

2t_SCLK–1.5

ns

SPIxSCK High Period

SPIxSCK Low Period

SPIxSCK Period

t_HDSM

Last SPIxSCK Edge to SPIxSELy High

Sequential Transfer Delay

t_SPITDM

t_DDSPIDM

t_HDSPIDM

SPIxSCK Edge to Data Out Valid (Data Out Delay)

SPIxSCK Edge to Data Out Invalid (Data Out Hold)

6

–1.0

SPIxSELy

(OUTPUT)

t_SDSCIM

t_SPICLM

t_SPICHM

t_SPICLK

t_HDSM

t_SPITDM

SPIxSCK

(OUTPUT)

t_HDSPIDM

t_DDSPIDM

SPIxMOSI

(OUTPUT)

t_SSPIDM

CPHA = 1

t_HSPIDM

SPIxMISO

(INPUT)

t_HDSPIDM

t_DDSPIDM

SPIxMOSI

(OUTPUT)

t_SSPIDM

t_HSPIDM

CPHA = 0

SPIxMISO

(INPUT)

Figure 38. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. C

|

Page 64 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 46 and Figure 39 describe SPI port slave operations.

Table 46. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

SPIxSCK High Period

2t_SCLK–1.5

4t_SCLK

ns

SPIxSCK Low Period

SPIxSCK Period

Last SPIxSCK Edge to SPIxSS Not Asserted

Sequential Transfer Delay

2t_SCLK–1.5

1.6

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPIxSS Assertion to First SPIxSCK Edge

Data Input Valid to SPIxSCK Edge (Data Input Setup)

SPIxSCK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

t_DSOE

SPIxSS Assertion to Data Out Active

0

8

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPIxSS Deassertion to Data High Impedance

SPIxSCK Edge to Data Out Valid (Data Out Delay)

SPIxSCK Edge to Data Out Invalid (Data Out Hold)

8

10

0

SPIxSS

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

t_SPICLK

t_HDS

t_SPITDS

SPIxSCK

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

t_DDSPID

t_DSDHI

SPIxMISO

(OUTPUT)

CPHA = 1

t_SSPID

t_HSPID

SPIxMOSI

(INPUT)

t_DSOE

t_HDSPID

t_DDSPID

t_DSDHI

SPIxMISO

(OUTPUT)

t_HSPID

CPHA = 0

t_SSPID

SPIxMOSI

(INPUT)

Figure 39. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. C

|

Page 65 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Universal Asynchronous Receiver-Transmitter

(UART) Ports—Receive and Transmit Timing

The UART ports have a maximum baud rate of SCLK/16. There

is some latency between the generation of internal UART inter-

rupts and the external data operations. These latencies are

negligible at the data transmission rates for the UART. For more

information, see the ADSP-BF54x Blackfin Processor Hardware

Reference.

General-Purpose Port Timing

Table 47 and Figure 40 describe general-purpose

port operations.

Table 47. General-Purpose Port Timing

Parameter

Timing Requirement

t_WFI

Min

Max

Unit

ns

General-Purpose Port Pin Input Pulse Width

t_SCLK+ 1

–0.3

Switching Characteristics

t_GPODGeneral-Purpose Port Pin Output Delay from CLKOUT Low

6

ns

CLKOUT

GPIO OUTPUT

GPIO INPUT

t_GPOD

t_WFI

Figure 40. General-Purpose Port Timing

Rev. C

|

Page 66 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Timer Cycle Timing

Table 48 and Figure 41 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (f_SCLK/2) MHz.

Table 48. Timer Cycle Timing

Parameter

Min

Max

Unit

Timing Characteristics

t_WL

t_WH

t_TIS

t_TIH

Timer Pulse Width Input Low¹

t_SCLK+1

6.5

ns

Timer Pulse Width Input High¹

Timer Input Setup Time Before CLKOUT Low²

Timer Input Hold Time After CLKOUT Low²

–1

Switching Characteristics

t_HTO

Timer Pulse Width Output

1×t_SCLK

(2³²– 1)×t_SCLKns

ns

t_TOD

Timer Output Delay After CLKOUT High

6

¹The minimum pulse widths apply for TMRx signals in width capture and external clock modes.

²Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs.

CLKOUT

t_TOD

TMRx OUTPUT

t_TIS

t_TIH

t_HTO

TMRx INPUT

t_WH,t_WL

Figure 41. Timer Cycle Timing

Rev. C

|

Page 67 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Up/Down Counter/Rotary Encoder Timing

Table 49 and Figure 42 describe up/down counter/rotary

encoder timing.

Table 49. Up/Down Counter/Rotary Encoder Timing

Parameter

Min

Max

Unit

Timing Requirements

t_WCOUNT

t_CIS

CUD/CDG/CZM Input Pulse Width

t_SCLK+ 1

7.2

ns

CUD/CDG/CZM Input Setup Time Before CLKOUT High¹

t_CIH

CUD/CDG/CZM Input Hold Time After CLKOUT High¹

0.0

¹Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.

CLKOUT

t_CIS

t_CIH

CUD/CDG/CZM

t_WCOUNT

Figure 42. Up/Down Counter/Rotary Encoder Timing

Rev. C

|

Page 68 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

SD/SDIO Controller Timing

Table 50 and Figure 43 describe SD/SDIO controller timing.

Table 51 and Figure 44 describe SD/SDIO controller (high-

speed mode) timing.

Table 50. SD/SDIO Controller Timing

Parameter

Min

Max

Unit

Timing Requirements

t_ISU

t_IH

SD_Dx and SD_CMD Input Setup Time

SD_Dx and SD_CMD Input Hold Time

7.2

2

ns

Switching Characteristics

f_PP

f_OD

t_WL

t_WH

SD_CLK Frequency During Data Transfer Mode¹

SD_CLK Frequency During Identification Mode

SD_CLK Low Time

0

20

400

MHz

kHz

ns

100²

15

SD_CLK High Time

ns

t_TLH

t_THL

SD_CLK Rise Time

SD_CLK Fall Time

SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode

SD_Dx and SD_CMD Output Delay Time During Identification Mode

10

14

50

ns

t_ODLY

¹t_PP=1/f_PP

–1

²Spec can be 0 kHz, meaning to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.

V_{OH (MIN)}

t_PP

SD_CLK

t_THL

t_TLH

t_ISU

t_IH

V_{OL (MAX)}

t_WL

t_WH

INPUT

t_ODLY

OUTPUT

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

Figure 43. SD/SDIO Controller Timing

Rev. C

|

Page 69 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 51. SD/SDIO Controller Timing (High Speed Mode)

Parameter

Min

Max

Unit

Timing Requirements

t_ISU

t_IH

SD_Dx and SD_CMD Input Setup Time

SD_Dx and SD_CMD Input Hold Time

7.2

2

ns

Switching Characteristics

f_PP

t_WL

t_WH

SD_CLK Frequency During Data Transfer Mode¹

SD_CLK Low Time

0

9.5

40

MHz

ns

SD_CLK High Time

t_TLH

t_THL

t_ODLY

t_OH

SD_CLK Rise Time

SD_CLK Fall Time

SD_Dx and SD_CMD Output Delay Time During Data Transfer Mode

SD_Dx and SD_CMD Output Hold Time

3

2

ns

2.5

¹t_PP=1/f_PP

V_{OH (MIN)}

t_PP

SD_CLK

INPUT

t_THL

t_TLH

t_ISU

t_IH

V_{OL (MAX)}

t_WL

t_WH

t_ODLY

t_OH

OUTPUT

NOTES:

1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.

Figure 44. SD/SDIO Controller Timing (High Speed Mode)

Rev. C

|

Page 70 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

MXVR Timing

Table 52 and Table 53 describe the MXVR timing requirements.

Figure 5 illustrates the MOST connection.

Table 52. MXVR Timing—MXI Center Frequency Requirements

Parameter

Fs = 38 kHz

9.728

Fs = 44.1 kHz Fs = 48 kHz

Unit

MHz

f_{MXI_256}

f_{MXI_384}

f_{MXI_512}

f_{MXI_1024}

MXI Center Frequency (256 Fs)

MXI Center Frequency (384 Fs)

MXI Center Frequency (512 Fs)

MXI Center Frequency (1024 Fs)

11.2896

16.9344

22.5792

45.1584

12.288

18.432

24.576

49.152

14.592

19.456

38.912

Table 53. MXVR Timing— MXI Clock Requirements

Parameter

Min

Max

Unit

Timing Requirements

FS_MXI

FT_MXI

DC_MXI

MXI Clock Frequency Stability

MXI Frequency Tolerance Over Temperature

MXI Clock Duty Cycle

–50

+50

ppm

%

–300

+40

+300

+60

Rev. C

|

Page 71 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

HOSTDP A/C Timing-Host Read Cycle

Table 54 and Figure 45 describe the HOSTDP A/C host read

cycle timing requirements.

Table 54. Host Read Cycle Timing Requirements

Parameter

Min

Max

Units

Timing Requirements

t_SADRDL

HOST_ADDR and HOST_CE Setup Before HOST_RD Falling Edge

4

2.5

ns

t_HADRDHHOST_ADDR and HOST_CE Hold After HOST_RD Rising Edge

t_RDWL

t_RDWH

HOST_RD Pulse Width Low (ACK Mode)

HOST_RD Pulse Width Low (INT Mode)

HOST_RD Pulse Width High or Time Between HOST_RD Rising Edge and 2 × t_SCLK

HOST_WR Falling Edge

t_DRDYRDL+ t_RDYPRD+ t_DRDHRDY

1.5 × t_SCLK+ 8.7

t_DRDHRDYHOST_RD Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode) 0

ns

Switching Characteristics

t_SDATRDYHOST_D15–0 Valid Prior HOST_ACK Rising Edge (ACK Mode)

t_DRDYRDLHOST_ACK Falling Edge After HOST_CE (ACK Mode)

t_SCLK– 4.0

ns

11.25

NM¹

8.0

t_RDYPRD

t_DDARWHHOST_D15–0 Disable After HOST_RD

t_ACCHOST_D15–0 Valid After HOST_RD Falling Edge (INT Mode)

t_HDARWHHOST_D15–0 Hold After HOST_RD Rising Edge

HOST_ACK Low Pulse-Width for Read Access (ACK Mode)

1.5 × t_SCLK

1.0

¹NM (Not Measured) — This parameter is based on t_SCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host

DMA FIFO status. This is system design dependent.

HOST_ADDR

HOST_CE

t_SADRDL

t_HADRDH

t_RDWL

t_RDWH

HOST_RD

t_SDATRDY

t_ACC

t_DDARWH

t_HDARWH

HOST_DATA

t_DRDHRDY

t_DRDYRDL

t_RDYPRD

HOST_ACK

In Figure 45, HOST_DATA is HOST_D0–D15.

Figure 45. HOSTDP A/C—Host Read Cycle

Rev. C

|

Page 72 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

HOSTDP A/C Timing-Host Write Cycle

Table 55 and Figure 46 describe the HOSTDP A/C host write

cycle timing requirements.

Table 55. Host Write Cycle Timing Requirements

Parameter

Min

Max

Unit

Timing Requirements

t_SADWRL

t_HADWRH

t_WRWL

HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge

HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge

HOST_WR Pulse Width Low (ACK Mode)

4

ns

2.5

t_DRDYWRL+ t_RDYPRD+ t_DWRHRDY

1.5 × t_SCLK+ 8.7

HOST_WR Pulse Width Low (INT Mode)

t_WRWH

HOST_WR Pulse Width High or Time Between HOST_WR Rising Edge 2 × t_SCLK

and HOST_RD Falling Edge

t_DWRHRDY

t_HDATWH

t_SDATWH

HOST_WR Rising Edge Delay After HOST_ACK Rising Edge(ACKMode) 0

ns

HOST_D15–0 Hold After HOST_WR Rising Edge

HOST_D15–0 Setup Before HOST_WR Rising Edge

2.5

3.5

Switching Characteristics

t_DRDYWRLHOST_ACK Falling Edge After HOST_CE Asserted (ACK Mode)

t_RDYPWRHOST_ACK Low Pulse-Width for Write Access (ACK Mode)

11.25

NM¹

ns

¹NM (not measured)—This parameter is based on t_SCLK. It is not measured because the number of SCLK cycles for which HOST_ACK remains low depends on the Host DMA

FIFO status. This is system design dependent.

HOST_ADDR

HOST_CE

t_SADWRL

t_HADWRH

t_WRWH

t_WRWL

HOST_WR

HOST_DATA

HOST_ACK

t_SDATWH

t_HDATWH

t_RDYPWR

t_DRDYWRL

t_DWRHRDY

In Figure 46, HOST_DATA is HOST_D0–D15.

Figure 46. HOSTDP A/C- Host Write Cycle

Rev. C

|

Page 73 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ATA/ATAPI-6 Interface Timing

The following tables and figures specify ATAPI timing parame-

ters. For detailed parameter descriptions, refer to the ATAPI

specification (ANSI INCITS 361-2002). Table 58 to Table 61

include ATAPI timing parameter equations. System designers

should use these equations along with the parameters provided

in Table 56 and Table 57. ATAPI timing control registers

should be programmed such that ANSI INCITS 361-2002 speci-

fications are met for the desired transfer type and mode.

Table 56. ATA/ATAPI-6 Timing Parameters

Parameter

t_SK1

t_OD

Min

Max

6

Unit

ns

Difference in output delay after CLKOUT for ATAPI output pins¹

Output delay after CLKOUT for outputs¹

12

ns

t_SUD

t_SUI

ATAPI_D0-15 or ATAPI_D0-15A Setup Before CLKOUT

ATAPI_IORDY Setup Before CLKOUT

6

ns

6

ns

t_SUDU

ATAPI_D0-15 or ATAPI_D0-15A Setup Before ATAPI_IORDY (UDMA-in only)

2

ns

t_HDU

ATAPI_D0-15 or ATAPI_D0-15A Hold After ATAPI_IORDY (UDMA-in only)

2.6

ns

¹ATAPI output pins include ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_DIOR, ATAPI_DIOW, ATAPI_DMACK, ATAPI_D0-15, ATAPI_A0-2A, and ATAPI_D0-15A.

Table 57. ATA/ATAPI-6 System Timing Parameters

Parameter

t_SK2

t_BD

Source

System Design

Maximum difference in board propagation delay between any 2 ATAPI output pins¹

Maximum board propagation delay.

t_SK3

Maximum difference in board propagation delay during a read between ATAPI_IORDY and ATAPI_D0- System Design

15/ATAPI_D0-15A.

t_SK4

Maximum difference in ATAPI cable propagation delay between output pin group A and output pin ATAPI Cable Specification

group B²

t_CDD

t_CDC

ATAPI cable propagation delay for ATAPI_D0-15 and ATAPI_D0-15A signals.

ATAPI Cable Specification

ATAPI cable propagation delay for ATAPI_DIOR, ATAPI_DIOW, ATAPI_IORDY, and ATAPI_DMACK signals. ATAPI Cable Specification

¹ATAPI output pins include ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_DIOR, ATAPI_DIOW, ATAPI_DMACK, ATAPI_D0-15, ATAPI_A0-2A, and ATAPI_D0-15A.

²Output pin group A includes ATAPI_DIOR, ATAPI_DIOW, and ATAPI_DMACK. Output pin group B includes ATAPI_CS0, ATAPI_CS1, A1-3, ATAPI_D0-15,

ATAPI_A0-2A, and ATAPI_D0-15A.

Rev. C

|

Page 74 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Register and PIO

Table 58 and Figure 47 describe the ATAPI register and the PIO

data transfer timing.

Table 58. ATAPI Register and PIO Data Transfer Timing

ATAPI_REG/PIO_TIM_xTimingRegister

Setting¹

ATAPI Parameter/Description

Timing Equation

t₀

t₁

Cycle time

ATAPI_ADDR valid to

ATAPI_DIOR/ATAPI_DIOW setup

T2_PIO, TEOC_PIO

T1

(T2_PIO + TEOC_PIO) × t_SCLK

T1 × t_SCLK– (t_SK1+ t_SK2+ t_SK4)

t₂

t_2i

t₃

t₄

t₅

t₆

t₉

ATAPI_DIOR/ATAPI_DIOW pulse width

ATAPI_DIOR/ATAPI_DIOW recovery time TEOC_PIO

T2_PIO

T2_PIO × t_SCLK

TEOC_PIO × t_SCLK

T2_PIO × t_SCLK– (t_SK1+ t_SK2+ t_SK4

T4 × t_SCLK– (t_SK1+ t_SK2+ t_SK4

t_OD+ t_SUD+ 2 × t_BD+ t_CDD+ t_CDC

ATAPI_DIOW data setup

ATAPI_DIOW data hold

ATAPI_DIOR data setup

ATAPI_DIOR data hold

ATAPI_DIOR/ATAPI_DIOW to ATAPI_ADDR TEOC_PIO

valid hold

T2_PIO

T4

N/A

)

N/A

0

TEOC_PIO × t_SCLK– (t_SK1+ t_SK2+ t_SK4

)

t_A

ATAPI_IORDY setup time

T2_PIO

T2_PIO × t_SCLK– (t_OD+ t_SUI+ 2 × t_CDC+ 2 × t_BD)

¹ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for the ATA device mode of

operation.

Figure 47 displays the REG and PIO data transfer timing. Note

that ATAPI_ADDR pins include A1-3, ATAPI_CS0, and

ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins

include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0,

and ATAPI_CS1. Note that an alternate ATAPI_D0-15 port bus

is ATAPI_D0-15A

t₀

ATAPI

ADDR

t₉

t₁

t₂

t_2i

ATAPI_DIOR/

ATAPI_DIOW

ATAPI_D0–15

(WRITE)

t₃

t₄

ATAPI_D0–15

(READ)

t_A

t₅

t₆

ATAPI_IORDY

Figure 47. REG and PIO Data Transfer Timing¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 75 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ATAPI Multiword DMA Transfer Timing

Table 59 and Figure 48 through Figure 51 describe the ATAPI

multiword DMA transfer timing.

Table 59. ATAPI Multiword DMA Transfer Timing

ATAPI_MULTI_TIM_x Timing Register

ATAPI Parameter/Description

Setting¹

Timing Equation

(TD + TK) × t_SCLK

TD × t_SCLK

t₀

Cycle time

TD, TK

t_D

ATAPI_DIOR/ATAPI_DIOW asserted TD

Pulse Width

t_F

ATAPI_DIOR data hold

ATAPI_DIOW data setup

ATAPI_DIOR data setup

ATAPI_DIOW data hold

N/A

0

t_G(write)

t_G(read)

t_H

TD

TK

TD × t_SCLK– (t_SK1+ t_SK2+ t_SK4)

t_OD+ t_SUD+ 2 × t_BD+ t_CDD+ t_CDC

TK × t_SCLK– (t_SK1+ t_SK2+ t_SK4

TM × t_SCLK– (t_SK1+ t_SK2+ t_SK4

)

t_I

ATAPI_DMACK to

ATAPI_DIOR/ATAPI_DIOW setup

TM

)

t_J

ATAPI_DIOR/ATAPI_DIOW to

ATAPI_DMACK hold

TK, TEOC_MDMA

(TK + TEOC_MDMA) × t_SCLK– (t_SK1+ t_SK2+ t_SK4

)

t_KR

t_KW

t_LR

t_M

ATAPI_DIOR negated pulse width TKR

ATAPI_DIOW negated pulse width TKW

ATAPI_DIOR to ATAPI_DMARQ delay N/A

TKR × t_SCLK

TKW × t_SCLK

(TD + TK) × t_SCLK– (t_OD+ 2 × t_BD+ 2 × t_CDC

)

ATAPI_CS0-1 valid to

ATAPI_DIOR/ATAPI_DIOW

TM

TM × t_SCLK– (t_SK1+ t_SK2+ t_SK4

)

t_N

ATAPI_CS0-1 hold

TK, TEOC_MDMA

(TK + TEOC_MDMA) × t_SCLK– (t_SK1+ t_SK2+ t_SK4

¹ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for an ATA device mode of

operation.

Rev. C

|

Page 76 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 48 displays the initiation of a multiword DMA data

burst. Note that an alternate ATAPI_D0-15 port bus is

ATAPI_D0-15A.

ATAPI_CS0

ATAPI_CS1

t_M

ATAPI_DMARQ

t_I

ATAPI_DMACK

t_D

ATAPI_DIOR

ATAPI_DIOW

t_G

t_F

ATAPI_D0–15

(READ)

t_G

t_H

ATAPI_D0–15

(WRITE)

Figure 48. Initiating a Multiword DMA Data Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 49 displays a sustained multiword DMA data burst.

ATAPI_CS0

ATAPI_CS1

ATAPI_DMARQ

ATAPI_DMACK

t₀

ATAPI_DIOR

ATAPI_DIOW

t_D

t_K

ATAPI_D0–15

(READ)

t_G

t_F

t_G

t_F

ATAPI_D0–15

(WRITE)

t_G

t_H

t_G

t_H

Figure 49. Sustained Multiword DMA Data Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 77 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 50 displays a device terminating a multiword DMA data

burst.

ATAPI_CS0

ATAPI_CS1

t_N

ATAPI_DMARQ

t_LR

ATAPI_DMACK

t_KR

t_D

t_J

t_KW

ATAPI_DIOR

ATAPI_DIOW

t₀

ATAPI_D0–15

(READ)

t_G

t_F

ATAPI_D0–15

(WRITE)

t_G

Figure 50. Device Terminating a Multiword DMA Data Burst¹

t_H

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 51 displays a host terminating a multiword DMA data

burst.

ATAPI_CS0

ATAPI_CS1

t_N

ATAPI_DMARQ

ATAPI_DMACK

t_KR

t_D

t_J

t_KW

ATAPI_DIOR

ATAPI_DIOW

t₀

ATAPI_D0–15

(READ)

t_G

t_F

ATAPI_D0–15

(WRITE)

t_G

Figure 51. Host Terminating a Multiword DMA Data Burst¹

t_H

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 78 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ATAPI Ultra DMA Data-In Transfer Timing

Table 60 and Figure 52 through Figure 55 describe the ATAPI

ultra DMA data-in data transfer timing.

Table 60. ATAPI Ultra DMA Data-In Transfer Timing

ATAPI_ULTRA_TIM_x Timing

ATAPI Parameter

Register Setting¹

Timing Equation

T_SK3+ t_SUDU

t_DS

Data setup time at host

N/A

t_DH

t_CVS

t_CVH

t_LI

Data hold time at host

N/A

T_SK3+ t_HDU

CRC word valid setup time at host

CRC word valid hold time at host

Limited interlock time

TDVS

TACK

N/A

TDVS × t_SCLK– (t_SK1+ t_SK2)

TACK × t_SCLK– (t_SK1+ t_SK2

2 × t_BD+ 2 × t_SCLK+ t_OD

)

t_MLI

t_AZ

Interlock time with minimum

TZAH, TCVS

N/A

(TZAH + TCVS) × t_SCLK– (4 × t_BD+ 4 × t_SCLK+ 2 × t_OD)

0

Maximum time allowed for output drivers to

release

t_ZAH

Minimum delay time required for output

ATAPI_DMACK to ATAPI_DIOR/DIOW

Setup and hold times for ATAPI_DMACK

TZAH

TENV

TRP

2 × t_SCLK+ TZAH × t_SCLK+ t_SCLK

2

t_ENV

t_RP

(TENV × t_SCLK) +/- (t_SK1+ t_SK2

TRP × t_SCLK– (t_SK1+ t_SK2+ t_SK4

TACK × t_SCLK– (t_SK1+ t_SK2

)

t_ACK

TACK

)

¹ATAPI Timing Register Setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.

²This timing equation can be used to calculate both the minimum and maximum t_ENV

.

Rev. C

|

Page 79 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 52 displays the initiation of an ultra DMA data-in burst.

Note that an alternate ATAPI_D0-15 port bus is

ATAPI_D0-15A.

Also note that ATAPI_ADDR pins include A1-3, ATAPI_CS0,

and ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins

include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0,

and ATAPI_CS1.

ATAPI_DMARQ

ATAPI_DMACK

t_ACK

t_ENV

ATAPI_DIOW

t_ACK

t_ENV

ATAPI_DIOR

ATAPI_IORDY

t_AZ

ATAPI_D0–15

t_ACK

ATAPI ADDR

Figure 52. Initiating an Ultra DMA Data-In Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 53 displays a sustained ultra DMA data-in burst. Note

that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A.

ATAPI_IORDY

t_DS

t_DH

ATAPI_D0–15

Figure 53. Sustained Ultra DMA Data-In Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 80 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 54 displays a device terminating an ultra DMA data-in

burst.

ATAPI_DMARQ

ATAPI_DMACK

ATAPI_DIOW

ATAPI_DIOR

ATAPI_IORDY

ATAPI_D0–15

ATAPI ADDR

t_LI

t_MLI

t_ACK

t_LI

t_ACK

t_AZ

t_CVS

t_CVH

t_ZAH

t_ACK

Figure 54. Device Terminating an Ultra DMA Data-In Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 55 displays a host terminating an ultra DMA data-in

burst.

ATAPI_DMARQ

t_LI

t_MLI

ATAPI_DMACK

ATAPI_DIOW

ATAPI_DIOR

ATAPI_IORDY

ATAPI_D0–15

ATAPI ADDR

t_ACK

t_ZAH

t_RP

t_ACK

t_LI

t_CVS

t_CVH

t_ACK

Figure 55. Host Terminating an Ultra DMA Data-In Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 81 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ATAPI Ultra DMA Data-Out Transfer Timing

Table 61 and Figure 56 through Figure 59 describes the ATAPI

ultra DMA data-out transfer timing.

Table 61. ATAPI Ultra DMA Data-Out Transfer Timing

ATAPI_ULTRA_TIM_x Timing

ATAPI Parameter

Register Setting¹

TDVS, TCYC_TDVS

TDVS

Timing Equation

(TDVS + TCYC_TDVS) × t_SCLK

2 × (TDVS + TCYC_TDVS) × t_SCLK

TDVS × t_SCLK– (t_SK1+ t_SK2

TCYC_TDVS × t_SCLK– (t_SK1+ t_SK2

TDVS × t_SCLK– (t_SK1+ t_SK2

TACK × t_SCLK– (t_SK1+ t_SK2

TDVS × t_SCLK– (t_SK1+ t_SK2

2

t_CYC

t_2CYC

t_DVS

t_DVH

t_CVS

Cycle time

Two cycle time

Data valid setup time at sender

Data valid hold time at sender

CRC word valid setup time at host

CRC word valid hold time at host

)

TCYC_TDVS

TDVS

)

t_CVH

t_DZFS

TACK

)

Time from data output released-to-driving to first

strobe timing

TDVS

t_LI

Limited interlock time

N/A

2 × t_BD+ 2 × t_SCLK+ t_OD

t_MLI

Interlock time with minimum

ATAPI_DMACK to ATAPI_DIOR/DIOW

Ready to final strobe time

TMLI

TENV

N/A

TMLI × t_SCLK– (t_SK1+ t_SK2)

(TENV × t_SCLK) +/– (t_SK1+ t_SK2

2 × t_BD+ 2 × t_SCLK+ t_OD

3

t_ENV

)

t_RFS

t_ACK

t_SS

Setup and Hold time for ATAPI_DMACK

TACK

TACK × t_SCLK– (t_SK1+ t_SK2

)

Time from STROBE edge to assertion of ATAPI_DIOW TSS

TSS × t_SCLK– (t_SK1+ t_SK2

)

¹ATAPI Timing Register Setting should beprogrammed with a valuethatguarantees parameter compliance with the ATA ANSI specification for ATA device mode of operation.

²ATA/ATAPI-6 compliant functionality with limited speed.

³This timing equation can be used to calculate both the minimum and maximum t_ENV

.

Rev. C

|

Page 82 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 56 displays the initiation of an ultra DMA data-out burst.

Note that an alternate ATAPI_D0-15 port bus is ATAPI_D0-

15A.

ATAPI_DMARQ

ATAPI_DMACK

ATAPI_DIOW

t_ENV

t_LI

ATAPI_IORDY

t_ACK

ATAPI_DIOR

t_DZFS

t_DVS

t_DVH

ATAPI_D0–15

t_ACK

ATAPI ADDR

Figure 56. Initiating an Ultra DMA Data-Out Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 57 displays a sustained ultra DMA data-out burst. Note

that an alternate ATAPI_D0-15 port bus is ATAPI_D0-15A.

t_2CYC

t_CYC

t_2CYC

ATAPI_DIOR

ATAPI_D0–15

t_DVH

t_DVS

t_DVH

t_DVS

t_DVH

Figure 57. Sustained Ultra DMA Data-Out Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 83 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Figure 58 displays a host terminating an ultra DMA data-out

burst.

ATAPI_DMARQ

ATAPI_DMACK

t_LI

t_MLI

t_ACK

ATAPI_DIOW

t_SS

t_LI

ATAPI_IORDY

ATAPI_DIOR

ATAPI_D0–15

ATAPI ADDR

t_ACK

t_CVS

t_CVH

t_ACK

Figure 58. Host terminating an Ultra DMA Data-Out Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Figure 59 displays a device terminating an ultra DMA data-out

burst.

ATAPI_DMARQ

ATAPI_DMACK

t_LI

t_MLI

t_ACK

ATAPI_DIOW

ATAPI_IORDY

ATAPI_DIOR

ATAPI_D0–15

ATAPI ADDR

t_RFS

t_LI

t_MLI

t_ACK

t_CVS

t_CVH

t_ACK

Figure 59. Device Terminating an Ultra DMA Data-Out Burst¹

¹This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the

Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.

Rev. C

|

Page 84 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

USB On-The-Go-Dual-Role Device Controller Timing

Table 62 describes the USB On-The-Go Dual-Role Device Con-

troller timing requirements.

Table 62. USB On-The-Go Dual-Role Device Controller Timing Requirements

Parameter

Min

Max

Unit

Timing Requirements

f_USB

USB_XI frequency

9

33.3

+50

MHz

ppm

FS_USB

USB_XI Clock Frequency Stability

–50

JTAG Test And Emulation Port Timing

Table 63 and Figure 60 describe JTAG port operations.

Table 63. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Parameters

t_TCK

TCK Period

20

4

ns

t_TCK

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulse-Width²(measured in TCK cycles)

4

11

4

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

ns

0

16.5

¹System inputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, RESET, NMI, and

BMODE3–0.

²50 MHz Maximum

³System outputs = PA15–0, PB14–0, PC13–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ13–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,

DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, CLKOUT, A3–1, and MFS.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 60. JTAG Port Timing

Rev. C

|

Page 85 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

OUTPUT DRIVE CURRENTS

200

VOH

2.7V, +105°C

150

Figure 61 through Figure 70 show typical current-voltage char-

3.3V, +25°C

3.6V, –40°C

acteristics for the output drivers of the ADSP-BF54x Blackfin

100

processors. The curves represent the current drive capability of

50

the output drivers as a function of output voltage.

0

–50

–100

100

80

VOH

2.7V, +105°C

–150

–200

–250

2.25V, +105°C

60

40

VOL

2.5V, +25°C

3.3V, +25°C

2.0

3.6V, –40°C

2.5 3.0

2.75V, –40°C

20

0

0.5

1.0

1.5

3.5

4.0

SOURCE VOLTAGE (V)

0

–20

–40

–60

–80

–100

Figure 64. Drive Current B (High V_DDEXT)

VOL

60

40

2.25V, +105°C

2.5V, +25°C

VOH

2.75V, –40°C

2.25V, +105°C

2.5V, +25°C

2.75V, –40°C

2.0 2.5

SOURCE VOLTAGE (V)

0

0.5

1.0

1.5

3.0

20

0

Figure 61. Drive Current A (Low V_DDEXT

)

–20

–40

–60

–80

150

100

50

2.25V, +105°C

2.5V, +25°C

2.7V, +105°C

3.3V, +25°C

VOL

VOH

3.6V, –40°C

2.75V, –40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

0

Figure 65. Drive Current C (Low V_DDEXT

)

–50

–100

–150

2.7V, +105°C

3.3V, +25°C

VOL

80

60

2.7V, +105°C

3.3V, +25°C

VOH

3.6V, –40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

40

SOURCE VOLTAGE (V)

20

Figure 62. Drive Current A (High V_DDEXT

)

0

–20

–40

–60

–80

–100

150

100

50

2.25V, +105°C

2.5V, +25°C

VOH

2.7V, +105°C

VOL

2.75V, –40°C

3.3V, +25°C

3.6V, –40°C

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

OUTPUT VOLTAGE (V)

0

Figure 66. Drive Current C (High V_DDEXT

)

–50

–100

–150

2.25V, +105°C

2.5V, +25°C

VOL

2.75V, –40°C

2.0

0

0.5

1.0

1.5

2.5

3.0

SOURCE VOLTAGE (V)

Figure 63. Drive Current B (Low V_DDEXT

)

Rev. C

|

Page 86 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

50

40

10

VOH

2.7V, –40°C

2.5V, +105°C

2.6V, +25°C

0

–10

–20

–30

–40

–50

–60

30

20

10

0

–10

–20

–30

–40

–50

2.25V, +105°C

VOL

2.5V, +25°C

VOL

2.75V, –40°C

2.0

2.5V, –105°C

2.6V, +25°C

2.7V, –40°C

2.0

0

0.5

1.0

1.5

2.5

3.0

0

0.5

1.0

1.5

2.5

3.0

SOURCE VOLTAGE (V)

Figure 69. Drive Current E (Low V_DDEXT

)

Figure 67. Drive Current D (DDR SDRAM)

50

40

VOH

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

1.875V, +25°C

1.8V, +105°C

30

1.95V, –40°C

20

10

0

2.7V, +105°C

–10

–20

–30

–40

–50

3.3V, +25°C

VOL

1.8V, +105°C

3.6V, –40°C

VOL

1.875V, +25°C

0.5 0.75

SOURCE VOLTAGE (V)

1.95V, –40°C

1.25

0

0.25

1.0

1.5

1.75

2.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

Figure 70. Drive Current E (High V_DDEXT

)

Figure 68. Drive Current D (Mobile DDR SDRAM)

Rev. C

|

Page 87 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

TEST CONDITIONS

REFERENCE

SIGNAL

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 71

shows the measurement point for AC measurements (except

t_{DIS_MEASURED}

t_{ENA_MEASURED}

output enable/disable). The measurement point V_MEASis

t_DIS

t_ENA

V_DDEXT/2 or V_DDDDR/2, depending on the pin under test.

V

OH

V

(MEASURED)

OH

(MEASURED)

V

(MEASURED) ꢂ ꢃV

(MEASURED) + ꢃV

OH

V

(HIGH)

TRIP

V

(LOW)

V

TRIP

OL

INPUT

V

OL

(MEASURED)

OL

OR

OUTPUT

V

MEAS

(MEASURED)

MEAS

t_DECAY

t_TRIP

Figure 71. Voltage Reference Levels for AC Measurements

(Except Output Enable/Disable)

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Output Enable Time

Figure 72. Output Enable/Disable

Output pins are considered to be enabled when they have made

a transition from a high-impedance state to the point when they

start driving. The output enable time t_ENAis the interval from

the point when a reference signal reaches a high or low voltage

level to the point when the output starts driving as shown in the

output enable/disable diagram (Figure 72). The time,

t_{ENA_MEASURED}, is the interval from the point when the reference

signal switches to the point when the output voltage reaches

either 1.75 V (output high) or 1.25 V (output low). Time t_TRIPis

the interval from when the output starts driving to when the

output reaches the 1.25 V or 1.75 V trip voltage. Time t_ENAis

calculated as shown in the equation:

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-BF54x Blackfin proces-

sors’ output voltage and the input threshold for the device

requiring the hold time. A typical ∆V will be 0.4 V. C_Lis the total

bus capacitance (per data line), and I_Lis the total leakage or

three-state current (per data line). The hold time will be t_DECAY

plus the minimum disable time (for example, t_DDATfor an asyn-

chronous memory write cycle).

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all balls (see Figure 73).

t

= t

– t

ENA_MEASURED TRIP

ENA

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

TESTER PIN ELECTRONICS

50:

Output Disable Time

V

LOAD

T1

DUT

Output pins are considered to be disabled when they stop driv-

ing, go into a high-impedance state, and start to decay from

their output high or low voltage. The time for the voltage on the

bus to decay by ∆V is dependent on the capacitive load, C_Land

the load current, I_L. This decay time can be approximated by the

equation:

OUTPUT

45:

70:

ZO = 50:ꢀ(impedance)

TD = 4.04 r 1.18 ns

50:

0.5pF

4pF

2pF

400:

t

= (C ∆V) ⁄ I

DECAY

L

The output disable time t_DISis the difference between

NOTES:

THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

t

_{DIS_MEASURED}and t_DECAYas shown in Figure 72. The time

_{DIS_MEASURED}is the interval from when the reference signal

t

switches to when the output voltage decays ∆V from the mea-

sured output high or output low voltage. The time t_DECAYis

calculated with test loads C_Land I_L, and with ∆V equal to 0.25 V.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 73. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. C

|

Page 88 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

V_LOADis equal to V_DDEXT/2 or V_DDDDR/2, depending on the pin

12

under test. Figure 74 through Figure 85 on Page 91 show how

output rise time varies with capacitance. The delay and hold

specifications given should be derated by a factor derived from

these figures. The graphs in these figures may not be linear out-

side the ranges shown.

10

RISE TIME

8

6

4

2

0

FALL TIME

TYPICAL RISE AND FALL TIMES

14

12

RISE TIME

10

FALL TIME

0

50

100

150

200

250

8

LOAD CAPACITANCE (pF)

6

4

Figure 76. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver B at V_DDEXT= 2.25 V

2

0

10

0

50

100

150

200

250

9

8

LOAD CAPACITANCE (pF)

RISE TIME

Figure 74. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver A at V_DDEXT= 2.25 V

7

6

FALL TIME

5

12

4

3

2

1

0

10

RISE TIME

8

FALL TIME

6

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

4

2

0

Figure 77. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver B at V_DDEXT= 3.65 V

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 75. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver A at V_DDEXT= 3.65 V

Rev. C

|

Page 89 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

30

25

20

15

10

5

6

5

4

3

2

1

RISE TIME

RISE/FALL TIME

FALL TIME

0

50

100

150

200

250

0

10

20

30

40

50

60

70

LOAD CAPACITANCE (pF)

Figure 78. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver C at V_DDEXT= 2.25 V

Figure 81. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D DDR SDRAM at V_DDDDR= 2.7V

20

4

18

16

3.5

3

RISE TIME

RISE/FALL TIME

2.5

14

12

2

1.5

1

FALL TIME

10

8

6

4

2

0

.5

0

10

20

30

40

50

60

70

LOAD CAPACITANCE (pF)

Figure 82. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D Mobile DDR SDRAM at V_DDDDR= 1.8V

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 79. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver C at V_DDEXT= 3.65 V

4

3.5

3

6

5

RISE/FALL TIME

2.5

2

1.5

1

4

RISE/FALL TIME

3

2

.5

0

10

20

30

40

50

60

70

1

0

LOAD CAPACITANCE (pF)

Figure 83. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D Mobile DDR SDRAM at V_DDDDR= 1.95V

0

10

20

30

40

50

60

70

LOAD CAPACITANCE (pF)

Figure 80. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for

Driver D DDR SDRAM at V_DDDDR= 2.5V

Rev. C

|

Page 90 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

THERMAL CHARACTERISTICS

To determine the junction temperature on the application

printed circuit board use

132

128

T

= T

+ (Ψ × P )

JT

124

120

116

J

CASE

D

FALL TIME

where:

T_J=junction temperature (ꢄC)

_CASE= case temperature (ꢄC) measured by customer at top cen-

T

ter of package.

112

108

Ψ_JT= from Table 71

P_D= power dissipation. (See Table 18 on Page 38 for a method

to calculate P_D.)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Values of θ_JAare provided for package comparison and printed

circuit board design considerations. θ_JAcan be used for a first

order approximation of T_Jby the equation

Figure 84. Typical Fall Time (10% to 90%) vs. Load Capacitance for

Driver E at V_DDEXT= 2.7 V

124

120

T

= T + (θ × P )

JA

J

A

D

where:

T_A= ambient temperature (ꢄC)

116

FALL TIME

112

Table 64 lists values for θ_JCand θ_JBparameters. These values are

provided for package comparison and printed circuit board

design considerations. Airflow measurements in Table 64 com-

ply with JEDEC standards JESD51-2 and JESD51-6, and the

junction-to-board measurement complies with JESD51-8. The

junction-to-case measurement complies with MIL-STD-883

(Method 1012.1). All measurements use a 2S2P JEDEC

testboard.

108

104

100

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 85. Typical Fall Time (10% to 90%) vs. Load Capacitance for

Driver E at V_DDEXT= 3.65 V

Table 64. Thermal Characteristics, 400-Ball CSP_BGA

Parameter Condition

Typical Unit

θ_JA

0 linear m/s air flow

18.4

15.8

15.0

9.75

6.37

0.27

0.60

0.66

ꢄC/W

1 linear m/s air flow

2 linear m/s air flow

θ_JB

θ_JC

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Rev. C

|

Page 91 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

400-BALL CSP_BGA PACKAGE

Table 65 lists the CSP_BGA package by signal for the

ADSP-BF549. Table 66 on Page 95 lists the CSP_BGA package

by ball number.

Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)

Signal

A1

Ball No.

B2

Signal

DA4

Ball No.

G16

F19

D20

C20

F18

E19

B20

F17

D19

H17

H16

F16

E16

D16

C18

D18

B18

C19

B19

M20

N20

L18

M19

L19

L20

L17

K16

K20

K17

K19

J20

Signal

DQS1

DRAS

DWE

EMU

EXT_WAKE

GND

Ball No.

H18

E17

E18

R5

Signal

GND

GND_MP

MFS

Ball No.

L10

L11

L12

L13

L14

M6

A2

DA5

A3

B3

DA6

ABE0

ABE1

AMS0

AMS1

AMS2

AMS3

AOE

C17

C16

A10

D9

DA7

DA8

M18

A1

DA9

DA10

DA11

DA12

DBA0

DBA1

DCAS

DCLK0

DCLK1

DCLKE

DCS0

DCS1

DDR_VREF

DDR_VSSR

DQ0

A13

A20

B11

D1

M7

B10

D10

C10

B12

P19

D12

W1

M8

M9

M10

M11

M12

M13

M14

N6

ARE

D4

ATAPI_PDIAG

AWE

BMODE0

BMODE1

BMODE2

BMODE3

CLKBUF

CLKIN

CLKOUT

D0

E3

F3

F6

W2

F14

G9

W3

N7

W4

G10

G11

H7

N8

D11

A11

L16

D13

C13

B13

B15

A15

B16

A16

B17

C14

C15

A17

D14

D15

E15

E14

D17

G19

G17

E20

G18

N9

N10

N11

N12

N13

N14

P8

H8

H9

D1

H10

H11

H12

J7

D2

DQ1

D3

DQ2

D4

DQ3

P9

D5

DQ4

J8

P10

P11

P12

P13

R9

D6

DQ5

J9

D7

DQ6

J10

J11

J12

K7

D8

DQ7

D9

DQ8

D10

DQ9

R13

R14

R16

U8

D11

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM0

DQM1

DQS0

K18

H20

J19

K8

D12

K9

D13

K10

K11

K12

K13

L7

D14

J18

V6

D15

J17

Y1

DA0

J16

Y20

E7

DA1

G20

H19

F20

DA2

L8

E6

DA3

L9

MLF_M

F4

Rev. C

|

Page 92 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued)

Signal

MLF_P

MXI

Ball No.

E4

Signal

PC5

Ball No.

G1

Signal

PE15

PF0

Ball No.

W17

K3

Signal

PH7

PH8

PH9

PH10

PH11

PH12

PH13

PI0

Ball No.

H4

C2

PC6

J5

D5

MXO

NMI

PA0

C1

PC7

H3

PF1

J1

C4

C11

U12

V12

W12

Y12

W11

V11

Y11

U11

U10

Y10

Y9

PC8

Y14

V13

U13

W14

Y15

W15

P3

PF2

K2

C7

PC9

PF3

K1

C5

PA1

PC10

PC11

PC12

PC13

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PE0

PF4

L2

D7

PA2

PF5

L1

C6

PA3

PF6

L4

A3

PA4

PF7

K4

PI1

B4

PA5

PF8

L3

PI2

A4

PA6

P4

PF9

M1

M2

M3

M4

N4

PI3

B5

PA7

R1

PF10

PF11

PF12

PF13

PF14

PF15

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG8

PG9

PG10

PG11

PG12

PG13

PG14

PG15

PH0

PH1

PH2

PH3

PH4

PH5

PH6

PI4

A5

PA8

R2

PI5

B6

PA9

T1

PI6

A6

PA10

PA11

PA12

PA13

PA14

PA15

PB0

R3

PI7

B7

V10

Y8

T2

N1

PI8

A7

R4

N2

PI9

C8

W10

Y7

U1

J4

PI10

PI11

PI12

PI13

PI14

PI15

PJ0

B8

U2

K5

A8

W9

W5

Y2

T3

L5

A9

V1

N3

C9

PB1

T4

P1

D8

PB2

T6

V2

V15

Y17

W16

V16

Y19

Y18

U15

P16

R18

Y13

W13

W18

U14

V17

V18

U17

C3

B9

PB3

U6

U4

R20

N18

M16

T20

N17

U20

P18

N16

R19

P17

T19

M17

P20

N19

C12

A14

B14

PB4

Y4

U3

PJ1

PB5

Y3

V19

T17

U18

V14

Y16

W20

W19

R17

V20

U19

T18

P2

PJ2

PB6

W6

V7

PE1

PJ3

PB7

PE2

PJ4

PB8

W8

V8

PE3

PJ5

PB9

PE4

PJ6

PB10

PB11

PB12

PB13

PB14

PC0

U7

PE5

PJ7

W7

Y6

PE6

PJ8

PE7

PJ9

V9

PE8

PJ10

PJ11

PJ12

PJ13

RESET

RTXI

RTXO

Y5

PE9

H2

PE10

PE11

PE12

PE13

PE14

PC1

J3

PC2

J2

M5

P5

PC3

H1

PC4

G2

U16

D6

Rev. C

|

Page 93 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 65. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued)

Signal

TCK

Ball No.

V3

Signal

V_DDDDR

V_DDEXT

Ball No.

J14

J15

K14

K15

E5

Signal

V_DDEXT

V_DDINT

Ball No.

N5

Signal

V_DDINT

V_DDMP

V_DDRTC

V_DDUSB

V_DDVR

Ball No.

G13

J6

TDI

V5

N15

P15

R6

TDO

V4

J13

L6

TMS

U5

TRST

T5

R7

L15

P6

USB_DM

USB_DP

USB_ID

USB_RSET

USB_VBUS

USB_VREF

USB_XI

USB_XO

V_DDDDR

E2

E9

R8

E1

E10

E11

E12

F7

R15

T7

P7

G3

P14

R10

R11

R12

U9

D3

T8

D2

T9

B1

F8

T10

T11

T12

T13

T14

T15

T16

F9

F1

F13

G5

F2

E8

F10

F11

F12

G15

H13

H14

H15

G6

E13

F5

G7

G14

H5

G4

F15

A18

A19

A12

H6

VR_OUT0

VR_OUT1

XTAL

K6

G8

M15

G12

Rev. C

|

Page 94 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 66 lists the CSP_BGA package by ball number for the

ADSP-BF549. Table 65 on Page 92 lists the CSP_BGA package

by signal.

Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)

Ball No.

A1

Signal

GND

A2

Ball No.

C1

Signal

MXO

MXI

Ball No.

E1

Signal

USB_DP

USB_DM

GND

Ball No.

G1

Signal

PC5

A2

C2

E2

G2

PC4

A3

PI0

C3

PH5

E3

G3

USB_ID

V_DDUSB

V_DDEXT

V_DDINT

GND

A4

PI2

C4

PH9

E4

MLF_P

V_DDEXT

MFS

G4

A5

PI4

C5

PH11

PH13

PH10

PI9

E5

G5

A6

PI6

C6

E6

G6

A7

PI8

C7

E7

GND_MP

V_DDMP

V_DDEXT

V_DDRTC

D14

G7

A8

PI11

PI12

AMS0

CLKIN

XTAL

GND

RTXI

D4

C8

E8

G8

A9

C9

PI13

E9

G9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

D1

AOE

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

F1

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

H1

GND

NMI

GND

RESET

D1

V_DDINT

V_DDEXT

V_DDDDR

DA4

D8

D9

D13

D6

ABE1

ABE0

DCLK1

DCS0

DA7

DCLK0

DRAS

DWE

D10

VROUT₀

VROUT₁

GND

USB_VREF

A1

DA1

DA3

DA9

DA0

DA2

DQM0

PC3

GND

USB_VBUS

USB_RSET

GND

PH8

USB_XI

USB_XO

GND

B2

D2

F2

H2

PC0

B3

A3

D3

F3

H3

PC7

B4

PI1

D4

F4

MLF_M

V_DDUSB

GND

H4

PH7

B5

PI3

D5

F5

H5

V_DDEXT

GND

B6

PI5

D6

PH6

F6

H6

B7

PI7

D7

PH12

PI14

F7

V_DDEXT

V_DDINT

V_DDDDR

V_DDEXT

GND

H7

B8

PI10

PI15

AMS2

GND

ARE

D8

F8

H8

GND

B9

D9

AMS1

AMS3

CLKBUF

AWE

F9

H9

GND

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

GND

D2

D0

V_DDDDR

DBA1

DBA0

DQS1

DQM1

DQ11

RTXO

D3

D11

D12

V_DDVR

D5

DCLK0

D15

DCAS

DA11

DA8

D7

DCLKE

DCS1

DA10

DCLK1

DA12

DA6

DA5

DQS0

Rev. C

|

Page 95 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued)

Ball No.

J1

Signal

PF1

Ball No.

L1

Signal

PF5

Ball No.

N1

Signal

PF14

PF15

PG3

Ball No.

R1

Signal

PD2

J2

PC2

L2

PF4

N2

R2

PD3

J3

PC1

L3

PF8

N3

R3

PD5

J4

PG0

L4

PF6

N4

PF13

V_DDEXT

GND

V_DDEXT

PJ7

R4

PD7

J5

PC6

L5

PG2

N5

R5

EMU

V_DDEXT

GND

V_DDINT

GND

V_DDEXT

GND

PE7

J6

V_DDINT

GND

V_DDINT

V_DDDDR

DQ15

DQ14

DQ13

DQ12

DQ9

PF3

L6

V_DDINT

GND

V_DDINT

CLKOUT

DQ4

N6

R6

J7

L7

N7

R7

J8

L8

N8

R8

J9

L9

N9

R9

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

J20

K1

L10

L11

L12

L13

L14

L15

L16

L17

L18

L19

L20

M1

N10

N11

N12

N13

N14

N15

N16

N17

N18

N19

N20

P1

R10

R11

R12

R13

R14

R15

R16

R17

R18

R19

R20

T1

PJ4

DQ0

PJ1

PG13

PJ8

DQ2

PJ13

DQ3

DDR_VSSR

PG4

PJ0

PF9

PD4

K2

PF2

M2

PF10

PF11

PF12

PE12

GND

V_DDEXT

PJ2

P2

PE11

PD0

T2

PD6

K3

PF0

M3

P3

T3

PD10

PD12

TRST

PB2

K4

PF7

M4

P4

PD1

T4

K5

PG1

M5

P5

PE13

V_DDINT

GND

V_DDINT

V_DDEXT

PG12

PJ9

T5

K6

V_DDEXT

GND

V_DDDDR

DQ5

DQ7

DQ10

DQ8

DQ6

M6

P6

T6

K7

M7

P7

T7

V_DDEXT

PE1

K8

M8

P8

T8

K9

M9

P9

T9

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

M10

M11

M12

M13

M14

M15

M16

M17

M18

M19

M20

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

PJ11

EXT_WAKE

DQ1

PJ6

PE10

PJ10

ATAPI_PDIAG

PJ12

DDR_VREF

PJ3

Rev. C

|

Page 96 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

Table 66. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued)

Ball No.

U1

Signal

PD8

PD9

PD15

PD14

TMS

PB3

Ball No.

V1

Signal

PD11

PD13

TCK

Ball No.

W1

Signal

BMODE0

BMODE1

BMODE2

BMODE3

PB0

Ball No.

Y1

Signal

GND

PB1

U2

V2

W2

Y2

U3

V3

W3

Y3

PB5

U4

V4

TDO

TDI

W4

Y4

PB4

U5

V5

W5

Y5

PB14

PB12

PA14

PA12

PA10

PA9

U6

V6

GND

PB7

W6

PB6

Y6

U7

PB10

GND

V_DDINT

PA8

V7

W7

PB11

PB8

Y7

U8

V8

PB9

W8

Y8

U9

V9

PB13

PA11

PA5

W9

PA15

PA13

PA4

Y9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

PA7

PA6

PA0

PA1

PA2

PA3

PC10

PH1

PC9

PG15

PC11

PC13

PG7

PG14

PC8

PE3

PG11

PE14

PH4

PG5

PG8

PH2

PH3

PE0

PC12

PE4

PE15

PH0

PG6

PE2

PG10

PG9

PE9

PE6

PJ5

PE8

PE5

GND

Figure 86 lists the top view of the BGA ball configuration.

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

V

A

B

C

D

E

F

R

G

S

G

H

J

S

K

L

R

G

M

N

P

R

T

U

V

W

Y

KEY:

V

S

SUPPLIES: V

, V

,V

, V

,V

DDINT

DDDDR

DDMP DDUSB

DDRTC DDVR

V

R

REFERENCES: DDR_V

, USB_V

REF

DDEXT

REF

G

V

GROUNDS: GND , DDR_V

MP

GND

NC

SSR

VR

OUT

I/O SIGNALS

Figure 86. 400-Ball CSP_BGA Configuration (Top View)

Rev. C

|

Page 97 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

OUTLINE DIMENSIONS

Dimensions for the 17 mm × 17 mm CSP_BGA package in

Figure 87 are shown in millimeters.

15.20 BSC SQ

17.00 BSC SQ

A1 BALL INDICATOR

A1 BALL

0.80 BSC BALL PITCH

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

20 19 18 17 16 1514 13 12 11 10

9 8 7 6 5 4 3 2 1

BOTTOM VIEW

TOP VIEW

0.28 MIN

0.12 MAX

COPLANARITY

SIDE VIEW

1.70 MAX

0.50

0.45

0.40

SEATING PLANE

BALL DIAMETER

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,

WITH THE EXCEPTION OF BALL DIAMETER.

3. CENTER DIMENSIONS ARE NOMINAL.

Figure 87. 400-Ball, 17 mm × 17 mm CSP_BGA (Chip Scale Package Ball Grid Array) (BC-400-1)

SURFACE-MOUNT DESIGN

Table 67 is provided as an aid to PCB design. For industry-stan-

dard design recommendations, refer to IPC-7351, Generic

Requirements for Surface-Mount Design and Land Pattern

Standard.

Table 67. BGA Data for Use with Surface-Mount Design

Package

Ball Attach Type

400-Ball CSP_BGA (Chip Scale Package Ball Grid Array) BC-400-1 Solder Mask Defined

Package

Solder Mask Opening

0.40 mm Diameter

Package

Ball Pad Size

0.50 mm Diameter

Package

Rev. C

|

Page 98 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

AUTOMOTIVE PRODUCTS

Some ADSP-BF54x Blackfin processor models are available for

automotive applications with controlled manufacturing. Note

that these special models may have specifications that differ

from the general release models.

The automotive grade products shown in Table 68 are available

for use in automotive applications. Contact your local ADI

account representative or authorized ADI product distributor

for specific product ordering information. Note that all automo-

tive products are RoHS compliant.

Table 68. Automotive Products

Product Family¹

Temperature Range²

–40°C to +85°C

Speed Grade (Max)

400 MHz

Package Description

400-Ball CSP_BGA

Package Option

BC-400-1

ADBF542WBBCZ-4xx

ADBF542WBBCZ-5xx

ADBF544WBBCZ-5xx

ADBF549WBBCZ-5xx

ADBF549MWBBCZ-5xx

¹The use of xx designates silicon revision

533 MHz

BC-400-1

533 MHz

BC-400-1

533 MHz

BC-400-1

533 MHz

BC-400-1

²Referenced temperature is ambient temperature.

Rev. C

|

Page 99 of 100

|

February 2010

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549

ORDERING GUIDE

Model^{1, 2, 3}

Temperature Range⁴

–40°C to +85°C

0°C to +70°C

–40°C to +85°C

0°C to +70°C

Speed Grade (Max)

400 MHz

Package Description

400-Ball CSP_BGA

Package Option

BC-400-1

ADSP-BF542BBCZ-4A

ADSP-BF542BBCZ-5A

ADSP-BF542MBBCZ-5M

ADSP-BF542KBCZ-6A

ADSP-BF544BBCZ-4A

ADSP-BF544BBCZ-5A

ADSP-BF544MBBCZ-5M

ADSP-BF547BBCZ-5A

ADSP-BF547MBBCZ-5M

ADSP-BF547KBCZ-6A

ADSP-BF548MBBCZ-5M

ADSP-BF548BBCZ-5A

533 MHz

600 MHz

400 MHz

533 MHz

600 MHz

–40°C to +85°C

533 MHz

¹Each ADSP-BF54xM model contains a mobile DDR controller and does not support the use of standard DDR memory.

²Z = RoHS Compliant Part.

³The ADSP-BF549 is available for automotive use only. Please contact your local ADI product representative or authorized distributor for specific automotive product ordering

information.

⁴Referenced temperature is ambient temperature.

registered trademarks are the property of their respective owners.

D06512-0-2/10(C)

Rev. C

|

Page 100 of 100

|

February 2010


型号：	ADSP-BF542MBBCZ-5M
厂家：	ADI
描述：	Embedded Processor 嵌入式处理器
文件：	总100页 (文件大小：3415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF542MBBCZ-5M [ADI]

相关型号：

ADSP-BF542_07

ADSP-BF542_1

ADSP-BF542_15

ADSP-BF544

ADSP-BF544BBCZ-4A

ADSP-BF544BBCZ-5A

ADSP-BF544BBCZ-5X

ADSP-BF544MBBCZ-5M

ADSP-BF544_15

ADSP-BF547

ADSP-BF547BBCZ-5A

ADSP-BF547BBCZ-5X