ADSP-BF561SKBCZ5002_技术文档

Blackfin^®Embedded

Symmetric Multiprocessor

ADSP-BF561

Two internal memory-to-memory DMAs and one internal

memory DMA controller

12 general-purpose 32-bit timers/counters with PWM

capability

SPI-compatible port

UART with support for IrDA^®

Dual watchdog timers

Dual 32-bit core timers

48 programmable flags (GPIO)

On-chip phase-locked loop capable of 0.5× to 64× frequency

multiplication

Two parallel input/output peripheral interface units support-

ing ITU-R 656 video and glueless interface to analog front

end ADCs

Two dual channel, full duplex synchronous serial ports sup-

porting eight stereo I²S channels

FEATURES

Dual symmetric 600 MHz high performance Blackfin cores

328K bytes of on-chip memory

(see Memory Architecture on Page 4)

Each Blackfin core includes:

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler-friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.35 V core V_DDwith on-chip voltage regulator

2.5 V and 3.3 V compliant I/O

256-ball CSP_BGA (two sizes) and 297-ball PBGA

package options

PERIPHERALS

Dual 12-channel DMA controllers

(supporting 24 peripheral DMAs)

Four memory-to-memory DMAs

IRQ CONTROL/

WATCHDOG

TIMER

JTAG TEST

EMULATION

IRQ CONTROL/

WATCHDOG

TIMER

VOLTAGE

REGULATOR

UART

IrDA

B

SPI

L1

DATA

MEMORY

L1

DATA

MEMORY

L1

L2 SRAM

128K BYTES

INSTRUCTION

MEMORY

INSTRUCTION

MEMORY

SPORT0

SPORT1

GPIO

IMDMA

CONTROLLER

CORE SYSTEM/BUS INTERFACE

EAB

DMA

CONTROLLER1

32

TIMERS

DMA

CONTROLLER2

DEB

DAB

16

BOOT ROM

16

32

DAB

PAB

EXTERNAL PORT

FLASH/SDRAM CONTROL

PPI0

PPI1

Figure 1. Functional Block Diagram

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Rev. B

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

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Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADSP-BF561

TABLE OF CONTENTS

General Description ................................................. 3

Portable Low Power Architecture ............................. 3

Blackfin Processor Core .......................................... 3

Memory Architecture ............................................ 4

DMA Controllers .................................................. 8

Watchdog Timer .................................................. 8

Timers ............................................................... 9

Serial Ports (SPORTs) ............................................ 9

Serial Peripheral Interface (SPI) Port ......................... 9

UART Port .......................................................... 9

Programmable Flags (PFx) .................................... 10

Parallel Peripheral Interface ................................... 10

Dynamic Power Management ................................ 11

Voltage Regulation .............................................. 12

Voltage Regulator Layout Guidelines .................... 12

Clock Signals ..................................................... 13

Booting Modes ................................................... 14

Instruction Set Description ................................... 14

Development Tools ............................................. 15

Designing an Emulator-Compatible Processor Board .. 16

Related Documents ............................................. 16

Pin Descriptions .................................................... 17

Specifications ........................................................ 20

Operating Conditions .......................................... 20

Electrical Characteristics ....................................... 20

Absolute Maximum Ratings .................................. 21

Package Information ........................................... 21

ESD Sensitivity ................................................... 21

Timing Specifications .......................................... 22

Clock and Reset Timing .................................... 23

Asynchronous Memory Read Cycle Timing ........... 24

Asynchronous Memory Write Cycle Timing .......... 25

SDRAM Interface Timing .................................. 26

External Port Bus Request and Grant Cycle Timing .. 27

Parallel Peripheral Interface Timing ..................... 28

Serial Ports ..................................................... 32

Programmable Flags Cycle Timing ....................... 38

Timer Cycle Timing .......................................... 39

JTAG Test and Emulation Port Timing .................. 40

Output Drive Currents ......................................... 41

Power Dissipation ............................................... 42

Test Conditions .................................................. 42

Environmental Conditions .................................... 44

256-Ball CSP_BGA Ball Assignment ........................... 46

256-Ball CSP_BGA Ball Assignment ........................... 51

297-Ball PBGA ball assignment .................................. 56

Outline Dimensions ................................................ 61

Ordering Guide ..................................................... 64

REVISION HISTORY

4/07—Changes from Rev. A to Rev. B

Added Text to Serial Ports (SPORTs)............................. 9

Changed Font in Formula in Power Savings ...................12

Complete Rewrite of Operating Conditions ....................20

Complete Rewrite of Electrical Characteristics ................20

Edit to Figure Asynchronous Memory Read Cycle Timing .24

Edit to Figure Asynchronous Memory Write Cycle Timing 25

Deleted References to Temperature in Figures

in Output Drive Currents ..........................................41

Moved Data to Operating Conditions

and Rewrote Power Dissipation ..................................42

Deleted References to Temperature in Figures

in Test Conditions ...................................................42

Added figures for 256-Ball CSP_BGA Ball Configuration (Top

View) ....................................................................50

Added figure 256-Ball Chip Scale Package Ball Grid Array

(CSP_BGA) (BC-256-4).............................................61

Added Models to Ordering Guide ................................64

5/06—Changes from Rev. 0 to Rev. A

1/05—Initial version

Serial Peripheral Interface (SPI) Port—

Master Timing ............................................. 35

Serial Peripheral Interface (SPI) Port—

Slave Timing ............................................... 36

Universal Asynchronous Receiver Transmitter (UART)

Port—Receive and Transmit Timing ................. 37

Rev. B

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ADSP-BF561

GENERAL DESCRIPTION

The ADSP-BF561 processor is a high performance member of

the Blackfin family of products targeting a variety of multime-

dia, industrial, and telecommunications applications. At the

heart of this device are two independent Analog Devices Black-

fin processors. These Blackfin processors combine a dual-MAC

state-of-the-art signal processing engine, the advantage of a

clean, orthogonal RISC-like microprocessor instruction set, and

single instruction, multiple data (SIMD) multimedia capabilities

in a single instruction set architecture.

The powerful 40-bit shifter has extensive capabilities for per-

forming shifting, rotating, normalization, extraction, and

depositing of data. The data for the computational units is

found in a multiported register file of sixteen 16-bit entries or

eight 32-bit entries.

A powerful program sequencer controls the flow of instruction

execution, including instruction alignment and decoding. The

sequencer supports conditional jumps and subroutine calls, as

well as zero overhead looping. A loop buffer stores instructions

locally, eliminating instruction memory accesses for tight

looped code.

The ADSP-BF561 processor has 328K bytes of on-chip memory.

Each Blackfin core includes:

• 16K bytes of instruction SRAM/cache

• 16K bytes of instruction SRAM

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches from memory. The DAGs

share a register file containing four sets of 32-bit Index, Modify,

Length, and Base registers. Eight additional 32-bit registers

provide pointers for general indexing of variables and stack

locations.

• 32K bytes of data SRAM/cache

• 32K bytes of data SRAM

• 4K bytes of scratchpad SRAM

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. Level 2 (L2) memories are other

memories, on-chip or off-chip, that may take multiple processor

cycles to access. At the L1 level, the instruction memory holds

instructions only. The two data memories hold data, and a dedi-

cated scratchpad data memory stores stack and local variable

information. At the L2 level, there is a single unified memory

space, holding both instructions and data.

Additional on-chip memory peripherals include:

• 128K bytes of low latency on-chip L2 SRAM

• Four-channel internal memory DMA controller

• External memory controller with glueless support for

SDRAM, mobile SDRAM, SRAM, and flash.

PORTABLE LOW POWER ARCHITECTURE

Blackfin processors provide world-class power management

and performance. Blackfin processors are designed in a low

power and low voltage design methodology and feature

dynamic power management, the ability to vary both the voltage

and frequency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

substantial reduction in power consumption, compared with

just varying the frequency of operation. This translates into

longer battery life for portable appliances.

In addition, half of L1 instruction memory and half of L1 data

memory may be configured as either Static RAMs (SRAMs) or

caches. The Memory Management Unit (MMU) provides mem-

ory protection for individual tasks that may be operating on the

core and may protect system registers from unintended access.

The architecture provides three modes of operation: user mode,

supervisor mode, and emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while supervisor mode has

unrestricted access to the system and core resources.

BLACKFIN PROCESSOR CORE

As shown in Figure 2, each Blackfin core contains two multi-

plier/accumulators (MACs), two 40-bit ALUs, four video ALUs,

and a single shifter. The computational units process 8-bit,

16-bit, or 32-bit data from the register file.

The Blackfin instruction set has been optimized so that 16-bit

op-codes represent the most frequently used instructions,

resulting in excellent compiled code density. Complex DSP

instructions are encoded into 32-bit op-codes, representing fully

featured multifunction instructions. Blackfin processors sup-

port a limited multi-issue capability, where a 32-bit instruction

can be issued in parallel with two 16-bit instructions, allowing

the programmer to use many of the core resources in a single

instruction cycle.

Each MAC performs a 16-bit by 16-bit multiply in every cycle,

with accumulation to a 40-bit result, providing eight bits of

extended precision. The ALUs perform a standard set of arith-

metic and logical operations. With two ALUs capable of

operating on 16-bit or 32-bit data, the flexibility of the computa-

tion units covers the signal processing requirements of a varied

set of application needs.

The Blackfin assembly language uses an algebraic syntax for

ease of coding and readability. The architecture has been opti-

mized for use in conjunction with the VisualDSP C/C++

compiler, resulting in fast and efficient software

implementations.

Each of the two 32-bit input registers can be regarded as two

16-bit halves, so each ALU can accomplish very flexible single

16-bit arithmetic operations. By viewing the registers as pairs of

16-bit operands, dual 16-bit or single 32-bit operations can be

accomplished in a single cycle. By further taking advantage of

the second ALU, quad 16-bit operations can be accomplished

simply, accelerating the per cycle throughput.

Rev. B

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ADSP-BF561

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1

DA0

32

PREG

32

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.L

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

Internal (On-Chip) Memory

MEMORY ARCHITECTURE

The ADSP-BF561 has four blocks of on-chip memory providing

high bandwidth access to the core.

The ADSP-BF561 views memory as a single unified 4G byte

address space, using 32-bit addresses. All resources including

internal memory, external memory, and I/O control registers

occupy separate sections of this common address space. The

memory portions of this address space are arranged in a hierar-

chical structure to provide a good cost/performance balance of

some very fast, low latency memory as cache or SRAM very

close to the processor, and larger, lower cost and performance

memory systems farther away from the processor. The

ADSP-BF561 memory map is shown in Figure 3.

The first is the L1 instruction memory of each Blackfin core

consisting of 16K bytes of four-way set-associative cache mem-

ory and 16K bytes of SRAM. The cache memory may also be

configured as an SRAM. This memory is accessed at full proces-

sor speed. When configured as SRAM, each of the two 16K

banks of memory is broken into 4K sub-banks which can be

independently accessed by the processor and DMA.

The second on-chip memory block is the L1 data memory of

each Blackfin core which consists of four banks of 16K bytes

each. Two of the L1 data memory banks can be configured as

one way of a two-way set-associative cache or as an SRAM. The

other two banks are configured as SRAM. All banks are accessed

at full processor speed. When configured as SRAM, each of the

four 16K banks of memory is broken into 4K sub-banks which

can be independently accessed by the processor and DMA.

The L1 memory system in each core is the highest performance

memory available to each Blackfin core. The L2 memory pro-

vides additional capacity with lower performance. Lastly, the

off-chip memory system, accessed through the External Bus

Interface Unit (EBIU), provides expansion with SDRAM, flash

memory, and SRAM, optionally accessing more than

768M bytes of physical memory. The memory DMA controllers

provide high bandwidth data movement capability. They can

perform block transfers of code or data between the internal

L1/L2 memories and the external memory spaces.

The third memory block associated with each core is a 4K byte

scratchpad SRAM which runs at the same speed as the L1 mem-

ories, but is only accessible as data SRAM (it cannot be

configured as cache memory and is not accessible via DMA).

Rev. B

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ADSP-BF561

CORE A MEMORY MAP

CORE MMR REGISTERS

CORE B MEMORY MAP

0xFFFF FFFF

CORE MMR REGISTERS

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 4000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

SYSTEM MMR REGISTERS

RESERVED

L1 SCRATCHPAD SRAM (4K)

RESERVED

L1 INSTRUCTION SRAM/CACHE (16K)

RESERVED

L1 INSTRUCTION SRAM (16K)

RESERVED

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

RESERVED

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

0xFF80 0000

0xFF70 1000

RESERVED

INTERNAL MEMORY

L1 SCRATCHPAD SRAM (4K)

RESERVED

0xFF70 0000

0xFF61 4000

L1 INSTRUCTION SRAM/CACHE (16K)

RESERVED

0xFF61 0000

0xFF60 4000

L1 INSTRUCTION SRAM (16K)

RESERVED

0xFF60 0000

0xFF50 8000

L1 DATA BANK B SRAM/CACHE (16K)

L1 DATA BANK B SRAM (16K)

RESERVED

0xFF50 4000

0xFF50 0000

0xFF40 8000

0xFF40 4000

0xFF40 0000

L1 DATA BANK A SRAM/CACHE (16K)

L1 DATA BANK A SRAM (16K)

RESERVED

0xFEB2 0000

L2 SRAM (128K)

RESERVED

0xFEB0 0000

0xEF00 4000

0xEF00 0000

BOOT ROM

RESERVED

0x3000 0000

0x2C00 0000

ASYNC MEMORY BANK 3

ASYNC MEMORY BANK 2

ASYNC MEMORY BANK 1

ASYNC MEMORY BANK 0

0x2800 0000

0x2400 0000

0x2000 0000

RESERVED

SDRAM BANK 3

SDRAM BANK 2

EXTERNAL MEMORY

Top of last SDRAM page

SDRAM BANK 1

SDRAM BANK 0

0x0000 0000

Figure 3. Memory Map

The fourth on-chip memory system is the L2 SRAM memory

array which provides 128K bytes of high speed SRAM operating

at one half the frequency of the core, and slightly longer latency

than the L1 memory banks. The L2 memory is a unified instruc-

tion and data memory and can hold any mixture of code and

data required by the system design. The Blackfin cores share a

dedicated low latency 64-bit wide data path port into the L2

SRAM memory.

(SDRAM) as well as up to four banks of asynchronous memory

devices, including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The PC133-compliant SDRAM controller can be programmed

to interface to up to four banks of SDRAM, with each bank con-

taining between 16M bytes and 128M bytes providing access to

up to 512M bytes of SDRAM. Each bank is independently pro-

grammable and is contiguous with adjacent banks regardless of

the sizes of the different banks or their placement. This allows

flexible configuration and upgradability of system memory

while allowing the core to view all SDRAM as a single, contigu-

ous, physical address space.

Each Blackfin core processor has its own set of core Memory

Mapped Registers (MMRs) but share the same system MMR

registers and 128K bytes L2 SRAM memory.

External (Off-Chip) Memory

The asynchronous memory controller can also be programmed

to control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

The ADSP-BF561 external memory is accessed via the External

Bus Interface Unit (EBIU). This interface provides a glueless

connection to up to four banks of synchronous DRAM

Rev. B

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ADSP-BF561

64M byte segment regardless of the size of the devices used so

that these banks will only be contiguous if fully populated with

64M bytes of memory.

The ADSP-BF561 event controller consists of two stages: the

Core Event Controller (CEC) and the System Interrupt Control-

ler (SIC). The Core Event Controller works with the System

Interrupt Controller to prioritize and control all system events.

Conceptually, interrupts from the peripherals enter into the

SIC, and are then routed directly into the general-purpose

interrupts of the CEC.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The core MMRs are accessible only by the core and only in

supervisor mode and appear as reserved space by on-chip

peripherals. The system MMRs are accessible by the core in

supervisor mode and can be mapped as either visible or reserved

to other devices, depending on the system protection

model desired.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general-purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF561. Table 1 describes

the inputs to the CEC, identifies their names in the Event Vector

Table (EVT), and lists their priorities.

Table 1. Core Event Controller (CEC)

Priority

(0 is Highest)

Booting

Event Class

EVT Entry

EMU

The ADSP-BF561 contains a small boot kernel, which config-

ures the appropriate peripheral for booting. If the ADSP-BF561

is configured to boot from boot ROM memory space, the pro-

cessor starts executing from the on-chip boot ROM.

0

Emulation/Test Control

Reset

1

RST

2

Nonmaskable Interrupt

Exceptions

NMI

3

EVX

Event Handling

4

Global Enable

The event controller on the ADSP-BF561 handles all asynchro-

nous and synchronous events to the processor. The

5

Hardware Error

IVHW

IVTMR

IVG7

6

Core Timer

ADSP-BF561 provides event handling that supports both nest-

ing and prioritization. Nesting allows multiple event service

routines to be active simultaneously. Prioritization ensures that

servicing of a higher priority event takes precedence over servic-

ing of a lower priority event. The controller provides support for

five different types of events:

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

8

IVG8

9

IVG9

10

11

12

13

14

15

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

• Nonmaskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general-purpose interrupt inputs of the CEC.

Although the ADSP-BF561 provides a default mapping, the user

can alter the mappings and priorities of interrupt events by writ-

ing the appropriate values into the Interrupt Assignment

Registers (SIC_IAR7–0). Table 2 describes the inputs into the

SIC and the default mappings into the CEC.

• Exceptions – Events that occur synchronously to program

flow, i.e., the exception will be taken before the instruction

is allowed to complete. Conditions such as data alignment

violations or undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by timers, peripherals, input pins,

and an explicit software instruction.

Each event has an associated register to hold the return address

and an associated “return from event” instruction. When an

event is triggered, the state of the processor is saved on the

supervisor stack.

Rev. B

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ADSP-BF561

Table 2. System Interrupt Controller (SIC)

Table 2. System Interrupt Controller (SIC) (Continued)

Default

Peripheral Interrupt Event

PLL Wakeup

Mapping

Peripheral Interrupt Event

Mapping

IVG7

IVG8

IVG9

IVG10

Timer10 Interrupt

IVG10

IVG11

IVG8

DMA1 Error (Generic)

DMA2 Error (Generic)

IMDMA Error

Timer11 Interrupt

Programmable Flags 15–0 Interrupt A

Programmable Flags 15–0 Interrupt B

Programmable Flags 31–16 Interrupt A

Programmable Flags 31–16 Interrupt B

Programmable Flags 47–32 Interrupt A

Programmable Flags 47–32 Interrupt B

PPI0 Error

PPI1 Error

SPORT0 Error

SPORT1 Error

SPI Error

DMA1 Channel 12/13 Interrupt

(Memory DMA/Stream 0)

UART Error

DMA1 Channel 14/15 Interrupt

(Memory DMA/Stream 1)

IVG8

IVG9

Reserved

DMA1 Channel 0 Interrupt (PPI0)

DMA1 Channel 1 Interrupt (PPI1)

DMA1 Channel 2 Interrupt

DMA1 Channel 3 Interrupt

DMA1 Channel 4 Interrupt

DMA1 Channel 5 Interrupt

DMA1 Channel 6 Interrupt

DMA1 Channel 7 Interrupt

DMA1 Channel 8 Interrupt

DMA1 Channel 9 Interrupt

DMA1 Channel 10 Interrupt

DMA1 Channel 11 Interrupt

DMA2 Channel 0 Interrupt (SPORT0 Rx)

DMA2 Channel 1 Interrupt (SPORT0 Tx)

DMA2 Channel 2 Interrupt (SPORT1 Rx)

DMA2 Channel 3 Interrupt (SPORT1 Tx)

DMA2 Channel 4 Interrupt (SPI)

DMA2 Channel 5 Interrupt (UART Rx)

DMA2 Channel 6 Interrupt (UART Tx)

DMA2 Channel 7 Interrupt

DMA2 Channel 8 Interrupt

DMA2 Channel 9 Interrupt

DMA2 Channel 10 Interrupt

DMA2 Channel 11 Interrupt

Timer0 Interrupt

DMA2 Channel 12/13 Interrupt

(Memory DMA/Stream 0)

DMA2 Channel 14/15 Interrupt

(Memory DMA/Stream 1)

IMDMA Stream 0 Interrupt

IMDMA Stream 1 Interrupt

Watchdog Timer Interrupt

Reserved

IVG12

IVG13

IVG7

Reserved

IVG7

Supplemental Interrupt 0

Supplemental Interrupt 1

IVG7

Event Control

The ADSP-BF561 provides the user with a very flexible mecha-

nism to control the processing of events. In the CEC, three

registers are used to coordinate and control events. Each of the

registers is 16 bits wide, while each bit represents a particular

event class.

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

may also be written to clear (cancel) latched events. This

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

Timer1 Interrupt

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event,

thereby preventing the processor from servicing the event

even though the event may be latched in the ILAT register.

This register may be read from or written to while in

supervisor mode.

Timer2 Interrupt

Timer3 Interrupt

Timer4 Interrupt

Timer5 Interrupt

Timer6 Interrupt

Timer7 Interrupt

Timer8 Interrupt

Timer9 Interrupt

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ADSP-BF561

Note that general-purpose interrupts can be globally

enabled and disabled with the STI and CLI instructions,

respectively.

controller. DMA-capable peripherals include the SPORTs, SPI

port, UART, and PPIs. Each individual DMA-capable periph-

eral has at least one dedicated DMA channel.

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The ADSP-BF561 DMA controllers support both 1-dimen-

sional (1-D) and 2-dimensional (2-D) DMA transfers. DMA

transfer initialization can be implemented from registers or

from sets of parameters called descriptor blocks.

The 2-D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to ± 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

The SIC allows further control of event processing by providing

six 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 2.

• SIC Interrupt Mask Registers (SIC_IMASKx) – These reg-

isters control the masking and unmasking of each

peripheral interrupt event. When a bit is set in these regis-

ters, that peripheral event is unmasked and will be

processed by the system when asserted. A cleared bit in

these registers masks the peripheral event, thereby prevent-

ing the processor from servicing the event.

Examples of DMA types supported by the ADSP-BF561 DMA

controllers include:

• A single linear buffer that stops upon completion.

• A circular autorefreshing buffer that interrupts on each full

or fractionally full buffer.

• SIC Interrupt Status Registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt; a cleared bit indicates

the peripheral is not asserting the event.

• 1-D or 2-D DMA using a linked list of descriptors.

• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page.

In addition to the dedicated peripheral DMA channels, each

DMA Controller has four memory DMA channels provided for

transfers between the various memories of the ADSP-BF561

system. These enable transfers of blocks of data between any of

the memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

DMA transfers can be controlled by a very flexible descriptor-

based methodology or by a standard register-based autobuffer

mechanism.

• SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, each

peripheral can be configured to wake up the processor,

should the processor be in a powered-down mode when

the event is generated.

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

Further, the ADSP-BF561 has a four channel Internal Memory

DMA (IMDMA) Controller. The IMDMA Controller allows

data transfers between any of the internal L1 and L2 memories.

WATCHDOG TIMER

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the mode of the processor.

Each ADSP-BF561 core includes a 32-bit timer, which can be

used to implement a software watchdog function. A software

watchdog can improve system availability by forcing the proces-

sor to a known state, via generation of a hardware reset,

nonmaskable interrupt (NMI), or general-purpose interrupt, if

the timer expires before being reset by software. The program-

mer initializes the count value of the timer, enables the

appropriate interrupt, then enables the timer. Thereafter, the

software must reload the counter before it counts to zero from

the programmed value. This protects the system from remain-

ing in an unknown state where software, which would normally

reset the timer, has stopped running due to an external noise

condition or software error.

DMA CONTROLLERS

The ADSP-BF561 has two independent DMA controllers that

support automated data transfers with minimal overhead for

the DSP cores. DMA transfers can occur between the

ADSP-BF561 internal memories and any of its DMA-capable

peripherals. Additionally, DMA transfers can be accomplished

between any of the DMA-capable peripherals and external

devices connected to the external memory interfaces, including

the SDRAM controller and the asynchronous memory

After a reset, software can determine if the watchdog was the

source of the hardware reset by interrogating a status bit in the

timer control register, which is set only upon a watchdog gener-

ated reset.

Rev. B

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ADSP-BF561

The timer is clocked by the system clock (SCLK) at a maximum

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

frequency of f_SCLK

.

TIMERS

There are 14 programmable timer units in the ADSP-BF561.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1,024-channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

Each of the 12 general-purpose timer units can be indepen-

dently programmed as a Pulse Width Modulator (PWM),

internally or externally clocked timer, or pulse width counter.

The general-purpose timer units can be used in conjunction

with the UART to measure the width of the pulses in the data

stream to provide an autobaud detect function for a serial chan-

nel. The general-purpose timers can generate interrupts to the

processor core providing periodic events for synchronization,

either to the processor clock or to a count of external signals.

An additional 250 mV of SPORT input hysteresis can be

enabled by setting Bit 15 of the PLL_CTL register. When this bit

is set, all SPORT input pins have the increased hysteresis.

SERIAL PERIPHERAL INTERFACE (SPI) PORT

The ADSP-BF561 processor has an SPI-compatible port that

enables the processor to communicate with multiple SPI-com-

patible devices.

In addition to the 12 general-purpose programmable timers,

another timer is also provided for each core. These extra timers

are clocked by the internal processor clock (CCLK) and are typ-

ically used as a system tick clock for generation of operating

system periodic interrupts.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSI, and master input-slave

output, MISO) and a clock pin (serial clock, SCK). An SPI chip

select input pin (SPISS) lets other SPI devices select the proces-

sor, and seven SPI chip select output pins (SPISEL7–1) let the

processor select other SPI devices. The SPI select pins are recon-

figured programmable flag pins. Using these pins, the SPI port

provides a full-duplex, synchronous serial interface which sup-

ports both master/slave modes and multimaster environments.

SERIAL PORTS (SPORTs)

The ADSP-BF561 incorporates two dual-channel synchronous

serial ports (SPORT0 and SPORT1) for serial and multiproces-

sor communications. The SPORTs support the following

features:

The baud rate and clock phase/polarities for the SPI port are

programmable, and it has an integrated DMA controller, con-

figurable to support transmit or receive data streams. The SPI

DMA controller can only service unidirectional accesses at any

given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

The SPI port clock rate is calculated as:

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other DSP components and shift registers for shifting data

in and out of the data registers.

f_SCLK

2 × SPI_BAUD

-----------------------------------

SPI Clock Rate =

Where the 16-bit SPI_BAUD register contains a value of 2 to

65,535.

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

• Word length – Each SPORT supports serial data words

from 3 bits to 32 bits in length, transferred most significant

bit first or least significant bit first.

UART PORT

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulse widths and early or late

frame sync.

The ADSP-BF561 processor provides a full-duplex universal

asynchronous receiver/transmitter (UART) port, which is fully

compatible with PC-standard UARTs. The UART port provides

a simplified UART interface to other peripherals or hosts, sup-

porting full-duplex, DMA-supported, asynchronous transfers of

serial data. The UART port includes support for 5 data bits to

8 data bits, 1 stop bit or 2 stop bits, and none, even, or odd par-

ity. The UART port supports two modes of operation:

• Companding in hardware – Each SPORT can perform

A-law or μ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

• PIO (programmed I/O) – The processor sends or receives

data by writing or reading I/O-mapped UART registers.

The data is double-buffered on both transmit and receive.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The DSP can link or chain sequences of

DMA transfers between a SPORT and memory.

• DMA (direct memory access) – The DMA controller trans-

fers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

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ADSP-BF561

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

interrupt function. PFx pins defined as inputs can be con-

figured to generate hardware interrupts, while output PFx

pins can be configured to generate software interrupts.

The baud rate, serial data format, error code generation and

status, and interrupts for the UART port are programmable.

• Flag interrupt sensitivity registers – These registers specify

whether individual PFx pins are level- or edge-sensitive

and specify, if edge-sensitive, whether just the rising edge

or both the rising and falling edges of the signal are signifi-

cant. One register selects the type of sensitivity, and one

register selects which edges are significant for edge

sensitivity.

The UART programmable features include:

• Supporting bit rates ranging from (f_SCLK/1,048,576) bits per

second to (f_SCLK/16) bits per second.

• Supporting data formats from seven bits to 12 bits per

frame.

PARALLEL PERIPHERAL INTERFACE

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The ADSP-BF561 processor provides two parallel peripheral

interfaces (PPI0, PPI1) that can connect directly to parallel A/D

and D/A converters, video encoders and decoders, and other

general-purpose peripherals. The PPI consists of a dedicated

input clock pin, up to 3 frame synchronization pins, and up to

16 data pins. The input clock supports parallel data rates at up to

The UART port’s clock rate is calculated as:

f_SCLK

-----------------------------------------------

UART Clock Rate =

16 × UART_Divisor

Where the 16-bit UART_Divisor comes from the UART_DLH

register (most significant 8 bits) and UART_DLL register (least

significant 8 bits).

f

_SCLK/2 MHz, and the synchronization signals can be configured

as either inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656

modes of operation. In general-purpose mode, the PPI provides

half-duplex, bi-directional data transfer with up to 16 bits of

data. Up to 3 frame synchronization signals are also provided.

In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-

tional transfer of 8- or 10-bit video data. Additionally, on-chip

decode of embedded start-of-line (SOL) and start-of-field (SOF)

preamble packets is supported.

In conjunction with the general-purpose timer functions,

autobaud detection is supported.

The capabilities of the UART are further extended with support

for the Infrared Data Association (IrDA) serial infrared physical

layer link specification (SIR) protocol.

PROGRAMMABLE FLAGS (PFx)

The ADSP-BF561 has 48 bidirectional, general-purpose I/O,

programmable flag (PF47–0) pins. Some programmable flag

pins are used by peripherals (see Pin Descriptions on Page 17).

When not used as a peripheral pin, each programmable flag can

be individually controlled by manipulation of the flag control,

status, and interrupt registers as follows:

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input mode – frame syncs and data are inputs into the PPI.

• Flag direction control register – Specifies the direction of

each individual PFx pin as input or output.

• Frame capture mode – frame syncs are outputs from the

PPI, but data are inputs.

• Flag control and status registers – Rather than forcing the

software to use a read-modify-write process to control the

setting of individual flags, the ADSP-BF561 employs a

“write one to set” and “write one to clear” mechanism that

allows any combination of individual flags to be set or

cleared in a single instruction, without affecting the level of

any other flags. Two control registers are provided, one

register is written-to in order to set flag values, while

another register is written-to in order to clear flag values.

Reading the flag status register allows software to interro-

gate the sense of the flags.

• Output mode – frame syncs and data are outputs from the

PPI.

Input Mode

Input mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_COUNT register. The PPI supports 8-bit, and 10-bit

through 16-bit data, and are programmable in the

• Flag interrupt mask registers – These registers allow each

individual PFx pin to function as an interrupt to the pro-

cessor. Similar to the flag control registers that are used to

set and clear individual flag values, one flag interrupt mask

register sets bits to enable an interrupt function, and the

other flag interrupt mask register clears bits to disable an

PPI_CONTROL register.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave

(e.g., for frame capture). The ADSP-BF561 processors control

when to read from the video source(s). PPI_FS1 is an HSYNC

output and PPI_FS2 is a VSYNC output.

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ADSP-BF561

Table 3. Power Settings

Output Mode

Output mode is used for transmitting video or other data with

up to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

Core

Clock

System

Clock

PLL

Core

Mode/State PLL

Bypassed (CCLK) (SCLK) Power

Full-On

Active

Enabled No

Enabled Enabled On

Enabled/ Yes

Disabled

ITU-R 656 Mode Descriptions

Sleep

Enabled

–

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

Deep Sleep Disabled –

Hibernate Disabled –

• Active video only mode

• Vertical blanking only mode

• Entire field mode

Active Operating Mode—Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the

PLL is bypassed, the processor’s core clock (CCLK) and system

clock (SCLK) run at the input clock (CLKIN) frequency. In this

mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the full-on mode is

entered. DMA access is available to appropriately configured L1

and L2 memories.

Active Video Only Mode

Active video only mode is used when only the active video por-

tion of a field is of interest and not any of the blanking intervals.

The PPI does not read in any data between the end of active

video (EAV) and start of active video (SAV) preamble symbols,

or any data present during the vertical blanking intervals. In this

mode, the control byte sequences are not stored to memory;

they are filtered by the PPI. After synchronizing to the start of

Field 1, the PPI ignores incoming samples until it sees an SAV

code. The user specifies the number of active video lines per

frame (in the PPI_COUNT register).

In the active mode, it is possible to disable the PLL through the

PLL control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the full-on or sleep modes.

Sleep Operating Mode—High Dynamic Power Savings

The sleep mode reduces power dissipation by disabling the

clock to the processor core (CCLK). The PLL and system clock

(SCLK), however, continue to operate in this mode. Typically an

external event will wake up the processor. When in the sleep

mode, assertion of wakeup will cause the processor to sense the

value of the BYPASS bit in the PLL control register (PLL_CTL).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

Entire Field Mode

When in the sleep mode, system DMA access is only available to

external memory, not to L1 or on-chip L2 memory.

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1.

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

The deep sleep mode maximizes power savings by disabling the

clocks to the processor cores (CCLK) and to all synchronous

peripherals (SCLK). Asynchronous peripherals will not be able

to access internal resources or external memory. This powered-

down mode can only be exited by assertion of the reset interrupt

(RESET). If BYPASS is disabled, the processor will transition to

the full-on mode. If BYPASS is enabled, the processor will tran-

sition to the active mode.

DYNAMIC POWER MANAGEMENT

The ADSP-BF561 provides four power management modes and

one power management state, each with a different perfor-

mance/power profile. In addition, dynamic power management

provides the control functions to dynamically alter the proces-

sor core supply voltage, further reducing power dissipation.

Control of clocking to each of the ADSP-BF561 peripherals also

reduces power consumption. See Table 3 for a summary of the

power settings for each mode.

Hibernate State—Maximum Static Power Savings

The hibernate state maximizes static power savings by disabling

the voltage and clocks to the processor core (CCLK) and to all

the synchronous peripherals (SCLK). The internal voltage regu-

lator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the lowest static power dissipation.

Any critical information stored internally (memory contents,

register contents, etc.) must be written to a nonvolatile storage

device prior to removing power if the processor state is to be

Full-On Operating Mode—Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the default execution state in which maximum performance

can be achieved. The processor cores and all enabled peripherals

run at full speed.

Rev. B

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ADSP-BF561

preserved. Since V_DDEXTis still supplied in this mode, all of the

external pins three-state, unless otherwise specified. This allows

other devices that may be connected to the processor to have

power still applied without drawing unwanted current. The

internal supply regulator can be woken up by asserting the

RESET pin.

VOLTAGE REGULATION

The ADSP-BF561 processor provides an on-chip voltage regula-

tor that can generate processor core voltage levels 0.85 V to

1.30 V (within a specified tolerance, see Operating Conditions)

from an external 2.25 V to 3.6 V supply. Figure 4 shows the typ-

ical external components required to complete the power

management system. The regulator controls the internal logic

voltage levels and is programmable with the voltage regulator

control register (VR_CTL) in increments of 50 mV. To reduce

standby power consumption, the internal voltage regulator can

be programmed to remove power to the processor core while

keeping I/O power (V_DDEXT) supplied. While in the hibernate

state, V_DDEXTcan still be applied, thus eliminating the need for

external buffers. The voltage regulator can be activated from

this power-down state by asserting RESET, which will then ini-

tiate a boot sequence. The regulator can also be disabled and

bypassed at the user’s discretion.

Power Savings

As shown in Table 4, the ADSP-BF561 supports two different

power domains. The use of multiple power domains maximizes

flexibility, while maintaining compliance with industry stan-

dards and conventions. By isolating the internal logic of the

ADSP-BF561 into its own power domain, separate from the I/O,

the processor can take advantage of Dynamic Power Manage-

ment, without affecting the I/O devices. There are no

sequencing requirements for the various power domains.

Table 4. ADSP-BF561 Power Domains

The internal voltage regulation feature is not available on auto-

motive grade models. External voltage regulation is required to

ensure correct operation of these parts.

Power Domain

All internal logic

I/O

V_DDRange

V_DDINT

V_DDEXT

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

results in a 25% reduction in dynamic power dissipation, while

reducing the voltage by 25% reduces dynamic power dissipation

by more than 40%. Further, these power savings are additive, in

that if the clock frequency and supply voltage are both reduced,

the power savings can be dramatic.

SETOFDECOUPLING

CAPACITORS

2.25V TO 3.6V

INPUT VOLTAGE

RANGE

V_DDEXT

(LOW-INDUCTANCE)

V_DDEXT

+

100µF

10µH

100nF

V_DDINT

+

100µF

The dynamic power management feature of the ADSP-BF561

allows both the processor’s input voltage (V_DDINT) and clock fre-

quency (f_CCLK) to be dynamically controlled.

FDS9431A

100µF

10µF

LOW ESR

ZHCS1000

VR_OUT

The savings in power dissipation can be modeled using the

power savings factor and % power savings calculations.

SHORT AND LOW-

INDUCTANCE WIRE

The power savings factor is calculated as:

NOTE: DESIGNER SHOULD MINIMIZE

TRACE LENGTH TO FDS9431A.

power savings factor

GND

2

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

--------------------------

V_DDINTNOM

t_RED

----------

t_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

Figure 4. Voltage Regulator Circuit

where the variables in the equations are:

Voltage Regulator Layout Guidelines

f

_CCLKNOMis the nominal core clock frequency

_CCLKREDis the reduced core clock frequency

f

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1-0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the

ADSP-BF561 processors as possible.

V

_DDINTNOMis the nominal internal supply voltage

_DDINTREDis the reduced internal supply voltage

t

_NOMis the duration running at f_CCLKNOM

_REDis the duration running at f_CCLKRED

t

The percent power savings is calculated as:

% power savings = (1 – power savings factor) × 100%

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ADSP-BF561

For further details on the on-chip voltage regulator and related

board design guidelines, see the Switching Regulator Design

Considerations for ADSP-BF533 Blackfin Processors (EE-228)

applications note on the Analog Devices web site (www.ana-

log.com)—use site search on “EE-228”.

As shown in Figure 6, the core clock (CCLK) and system

peripheral clock (SCLK) are derived from the input clock

(CLKIN) signal. An on-chip PLL is capable of multiplying the

CLKIN signal by a user-programmable 0.5× to 64× multiplica-

tion factor. The default multiplier is 10×, but it can be modified

by a software instruction sequence. On the fly frequency

changes can be effected by simply writing to the PLL_DIV

register.

CLOCK SIGNALS

The ADSP-BF561 processor can be clocked by an external crys-

tal, a sine wave input, or a buffered, shaped clock derived from

an external clock oscillator.

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

÷ 1, 2, 4, 8

÷ 1 TO 15

CCLK

SCLK

PLL

0.5× TO 64×

CLKIN

VCO

Alternatively, because the ADSP-BF561 processor includes an

on-chip oscillator circuit, an external crystal may be used. For

fundamental frequency operation, use the circuit shown in

Figure 5. A parallel-resonant, fundamental frequency, micro-

processor-grade crystal is connected across the CLKIN and

XTAL pins. The on-chip resistance between CLKIN and the

XTAL pin is in the 500 kΩ range. Further parallel resistors are

typically not recommended. The two capacitors and the series

resistor shown in Figure 5 fine tune the phase and amplitude of

the sine frequency. The capacitor and resistor values shown in

Figure 5 are typical values only. The capacitor values are depen-

dent upon the crystal manufacturer’s load capacitance

recommendations and the physical PCB layout. The resistor

value depends on the drive level specified by the crystal manu-

facturer. System designs should verify the customized values

based on careful investigation on multiple devices over the

allowed temperature range.

SCLK ≤ CCLK

SCLK ≤ 133MHz

Figure 6. Frequency Modification Methods

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 5 illustrates typical system clock ratios.

Table 5. Example System Clock Ratios

Example Frequency

Ratios (MHz)

Signal Name

SSEL3–0

Divider Ratio

VCO/SCLK

A third-overtone crystal can be used at frequencies above

25 MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 5.

VCO

100

300

500

SCLK

0001

0110

1010

1:1

100

50

6:1

10:1

50

Blackfin

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f_SCLK. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

CLKOUT

TO PLL CIRCUITRY

EN

CLKIN

18pF*

XTAL

FOR OVERTONE

OPERATION ONLY:

18pF*

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED

DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE

ANALYZE CAREFULLY.

Figure 5. External Crystal Connections

Rev. B

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ADSP-BF561

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 6. This programmable core clock capability is useful for

fast core frequency modifications.

All configuration settings are set for the slowest device pos-

sible (3-cycle hold time; 15-cycle R/W access times; 4-cycle

setup).

• Boot from SPI host device – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the boot ROM

is busy, the Blackfin processor asserts a GPIO pin, called

host wait (HWAIT), to signal the host device not to send

any more bytes until the flag is deasserted. The flag is cho-

sen by the user and this information is transferred to the

Blackfin processor via bits 10:5 of the FLAG header.

Table 6. Core Clock Ratios

Example Frequency

Ratios (MHz)

Signal Name

CSEL1–0

Divider Ratio

VCO/CCLK

VCO

500

200

CCLK

00

01

10

11

1:1

2:1

4:1

8:1

500

250

50

• Boot from SPI serial EEPROM (16-, 24-bit addressable) –

The SPI uses the PF2 output pin to select a single SPI

EPROM device, submits a read command at address

0x0000, and begins clocking data into the beginning of L1

instruction memory. A 16-, 24-bit addressable SPI-compat-

ible EPROM must be used.

25

The maximum PLL clock time when a change is programmed

via the PLL_CTL register is 40 μs. The maximum time to change

the internal voltage via the internal voltage regulator is also

40 μs. The reset value for the PLL_LOCKCNT register is 0x200.

This value should be programmed to ensure a 40 μs wakeup

time when either the voltage is changed or a new MSEL value is

programmed. The value should be programmed to ensure an

80 μs wakeup time when both voltage and the MSEL value are

changed. The time base for the PLL_LOCKCNT register is the

period of CLKIN.

For each of the boot modes, a boot loading protocol is used to

transfer program and data blocks from an external memory

device to their specified memory locations. Multiple memory

blocks may be loaded by any boot sequence. Once all blocks are

loaded, Core A program execution commences from the start of

L1 instruction SRAM (0xFFA0 0000). Core B remains in a held-

off state until Bit 5 of SICA_SYSCR is cleared by Core A. After

that, Core B will start execution at address 0xFF60 0000.

In addition, Bit 4 of the reset configuration register can be set by

application code to bypass the normal boot sequence during a

software reset. For this case, the processor jumps directly to the

beginning of L1 instruction memory.

BOOTING MODES

The ADSP-BF561 has three mechanisms (listed in Table 7) for

automatically loading internal L1 instruction memory, L2, or

external memory after a reset. A fourth mode is provided to exe-

cute from external memory, bypassing the boot sequence.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set

employs an algebraic syntax that was designed for ease of coding

and readability. The instructions have been specifically tuned to

provide a flexible, densely encoded instruction set that compiles

to a very small final memory size. The instruction set also pro-

vides fully featured multifunction instructions that allow the

programmer to use many of the processor core resources in a

single instruction. Coupled with many features more often seen

on microcontrollers, this instruction set is very efficient when

compiling C and C++ source code. In addition, the architecture

supports both a user (algorithm/application code) and a super-

visor (O/S kernel, device drivers, debuggers, ISRs) mode of

operation—allowing multiple levels of access to core processor

resources.

Table 7. Booting Modes

BMODE1–0 Description

00

Execute from 16-bit external memory

(Bypass Boot ROM)

01

10

11

Boot from 8-bit/16-bit flash

Boot from SPI host slave mode

Boot from SPI serial EEPROM

(16-, 24-bit address range)

The BMODE pins of the reset configuration register, sampled

during power-on resets and software initiated resets, implement

the following modes:

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time,

15-cycle R/W access times, 4-cycle setup). Note that, in

bypass mode, only Core A can execute instructions from

external memory.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU plus

two load/store plus two pointer updates per cycle.

• Boot from 8-bit/16-bit external flash memory – The

8-bit/16-bit flash boot routine located in boot ROM mem-

ory space is set up using Asynchronous Memory Bank 0.

Rev. B

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June 2007

ADSP-BF561

• All registers, I/O, and memory are mapped into a unified

4G byte memory space providing a simplified program-

ming model.

• Set conditional breakpoints on registers, memory, and

stacks.

• Trace instruction execution.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data types; and separate user and ker-

nel stack pointers.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Code density enhancements, which include intermixing of

16-bit and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded as

16-bits.

• Create custom debugger windows.

The VisualDSP++ IDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all development tools,

including color syntax highlighting in the VisualDSP++ editor.

These capabilities permit programmers to:

DEVELOPMENT TOOLS

The ADSP-BF561 is supported with a complete set of

• Control how the development tools process inputs and

generate outputs.

CROSSCORE^®^†software and hardware development tools,

‡

including Analog Devices emulators and the VisualDSP++^®

development environment. The same emulator hardware that

supports other Analog Devices processors also fully emulates

the ADSP-BF561.

• Maintain a one-to-one correspondence with the tool’s

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of embedded, real-time

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler that is based on an algebraic

syntax, an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemati-

cal functions. A key point for these tools is C/C++ code

efficiency. The compiler has been developed for efficient trans-

lation of C/C++ code to Blackfin assembly. The Blackfin

processor has architectural features that improve the efficiency

of compiled C/C++ code.

programming. These capabilities enable engineers to develop

code more effectively, eliminating the need to start from the

very beginning when developing new application code. The

VDK features include threads, critical and unscheduled regions,

semaphores, events, and device flags. The VDK also supports

priority-based, pre-emptive, cooperative, and time-sliced

scheduling approaches. In addition, the VDK was designed to

be scalable. If the application does not use a specific feature, the

support code for that feature is excluded from the target system.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used with standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the

generation of various VDK-based objects, and visualizing the

system state when debugging an application that uses the VDK.

The Expert Linker can be used to visually manipulate the place-

ment of code and data in the embedded system. Memory

utilization can be viewed in a color-coded graphical form. Code

and data can be easily moved to different areas of the processor

or external memory with the drag of the mouse. Runtime stack

and heap usage can be examined. The Expert Linker is fully

compatible with existing Linker Definition File (LDF), allowing

the developer to move between the graphical and textual

environments.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

Analog Devices emulators use the IEEE 1149.1 JTAG test access

port of the ADSP-BF561 to monitor and control the target

board processor during emulation. The emulator provides full-

speed emulation, allowing inspection and modification of mem-

ory, registers, and processor stacks. Nonintrusive in-circuit

emulation is assured by the use of the processor’s JTAG inter-

face—the emulator does not affect the loading or timing of the

target system.

• View mixed C/C++ and assembly code (interleaved source

and object information).

• Insert breakpoints.

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. B

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June 2007

ADSP-BF561

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the Blackfin processor family. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

EZ-KIT Lite Evaluation Board

For evaluation of ADSP-BF561 processors, use the

ADSP-BF561 EZ-KIT Lite^®board available from Analog

Devices. Order part number ADDS-BF561-EZLITE. The board

comes with on-chip emulation capabilities and is equipped to

enable software development. Multiple daughter cards are

available.

DESIGNING AN EMULATOR-COMPATIBLE

PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on the ADSP-BF561. The emulator uses

the TAP to access the internal features of the processor, allow-

ing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor is

set running at full speed with no impact on system timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

For details on target board design issues, including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see Analog Devices JTAG Emulation Technical Reference

(EE-68) on the Analog Devices website (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.


型号：	ADSP-BF561SKBCZ5002
厂家：	ADI
描述：	Blackfin㈢ Embedded Symmetric Multiprocessor Blackfin㈢嵌入式对称多处理器
文件：	总64页 (文件大小：3260K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF561SKBCZ5002 [ADI]

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