ADSP-BF609BBCZ-5 [ADI]
Blackfin Dual Core Embedded Processor; Blackfin处理器双核嵌入式处理器型号: | ADSP-BF609BBCZ-5 |
厂家: | ADI |
描述: | Blackfin Dual Core Embedded Processor |
文件: | 总112页 (文件大小:3197K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Blackfin Dual Core
Embedded Processor
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
FEATURES
MEMORY
Dual-core symmetric high-performance Blackfin processor,
up to 500 MHz per core
Each core contains two 16-bit MACs, two 40-bit ALUs, and a
40-bit barrel shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Pipelined Vision Processor provides hardware to process sig-
nal and image algorithms used for pre- and co-processing
of video frames in ADAS or other video processing
applications
Each core contains 148K bytes of L1 SRAM memory (proces-
sor core-accessible) with multi-parity bit protection
Up to 256K bytes of L2 SRAM memory with ECC protection
Dynamic memory controller provides 16-bit interface to a
single bank of DDR2 or LPDDR DRAM devices
Static memory controller with asynchronous memory inter-
face that supports 8-bit and 16-bit memories
4 Memory-to-memory DMA streams, 2 of which feature CRC
protection
Flexible booting options from flash, SD EMMC and SPI mem-
ories and from SPI, link port and UART hosts
Accepts a range of supply voltages for I/O operation. See
Operating Conditions on Page 52
Memory management unit provides memory protection
Off-chip voltage regulator interface
349-ball BGA package (19 mm × 19 mm), RoHS compliant
SYSTEM CONTROL BLOCKS
PERIPHERALS
2× TWI
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
DUAL
CONTROL
WATCHDOG
8× TIMER
1× COUNTER
2× PWM
L2 MEMORY
CORE 0
CORE 1
32K BYTE
ROM
3× SPORT
1× ACM
B
B
256K BYTE
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
148K BYTE
PARITY BIT PROTECTED
L1 SRAM
ECC-
PROTECTED
SRAM
INSTRUCTION/DATA
INSTRUCTION/DATA
2× UART
112
GP
I/O
EMMC/RSI
1× CAN
DMA SYSTEM
2× EMAC
WITH
2× IEEE 1588
EXTERNAL
BUS
INTERFACES
2× SPI
4× LINK PORT
3× PPI
PIPELINED
VISION PROCESSOR
CRC
STATIC
MEMORY
CONTROLLER
DYNAMIC
MEMORY
CONTROLLER
VIDEO
SUBSYSTEM
HARDWARE
FUNCTIONS
PIXEL
COMPOSITOR
LPDDR
DDR2
16
USB 2.0 HS OTG
16
FLASH
SRAM
Figure 1. Processor Block Diagram
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
General Description ................................................. 3
Blackfin Processor Core .......................................... 3
Instruction Set Description ..................................... 4
Processor Infrastructure ......................................... 5
Memory Architecture ............................................ 6
Video Subsystem .................................................. 9
Processor Safety Features ...................................... 10
Additional Processor Peripherals ............................ 11
Power and Clock Management ............................... 14
System Debug .................................................... 17
Development Tools ............................................. 17
Additional Information......................................... 18
Related Signal Chains .......................................... 18
ADSP-BF60x Detailed Signal Descriptions ................... 19
349-Ball CSP_BGA Signal Descriptions ....................... 23
GP I/O Multiplexing for 349-Ball CSP_BGA ................. 33
ADSP-BF60x Designer Quick Reference ...................... 37
Specifications ........................................................ 52
Operating Conditions ........................................... 52
Electrical Characteristics ....................................... 54
Processor — Absolute Maximum Ratings .................. 58
ESD Sensitivity ................................................... 58
Processor — Package Information ........................... 58
Timing Specifications ........................................... 59
Output Drive Currents ......................................... 99
Environmental Conditions .................................. 101
ADSP-BF60x 349-Ball CSP_BGA Ball Assignments ...... 103
349-Ball CSP_BGA Ball Assignment (Numerical by Ball
Number) ...................................................... 103
349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin
Name) ......................................................... 105
349-Ball CSP_BGA Ball Configuration ................... 107
Outline Dimensions .............................................. 108
Surface-Mount Design ........................................ 108
Automotive Products ............................................ 109
Ordering Guide ................................................... 109
REVISION HISTORY
6/13—Revision 0:
Initial Version.
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GENERAL DESCRIPTION
The ADSP-BF60x processors are members of the Blackfin
family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
Table 1. Processor Comparison (Continued)
Processor Feature
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
64K
16K
32K
32K
4K
The processors offer performance up to 500 MHz, as well as low
static power consumption. Produced with a low-power and low-
voltage design methodology, they provide world-class power
management and performance.
L1 Data SRAM/Cache
L1 Scratchpad
By integrating a rich set of industry-leading system peripherals
and memory (shown in Table 1), Blackfin processors are the
platform of choice for next-generation applications that require
RISC-like programmability, multimedia support, and leading-
edge signal processing in one integrated package. These applica-
tions span a wide array of markets, from automotive systems to
embedded industrial, instrumentation and power/motor con-
trol applications.
L2 Data SRAM
128K
256K
L2 Boot ROM
32K
Maximum Speed Grade (MHz)2 400
Maximum SYSCLK (MHz)
500
250
Package Options
349-Ball CSP_BGA
1 VGA is 640 × 480 pixels per frame. HD is 1280 × 960 pixels per frame.
2 Maximum speed grade is not available with every possible SYSCLK selection.
Table 1. Processor Comparison
BLACKFIN PROCESSOR CORE
As shown in Figure 1, the processor integrates two Blackfin pro-
cessor cores. Each core, shown in Figure 2, contains two 16-bit
multipliers, two 40-bit accumulators, two 40-bit ALUs, four
video ALUs, and a 40-bit shifter. The computation units process
8-, 16-, or 32-bit data from the register file.
Processor Feature
Up/Down/Rotary Counters
Timer/Counters with PWM
3-Phase PWM Units (4-pair)
SPORTs
1
8
2
3
2
1
3
1
1
2
2
1
4
2
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
SPIs
USB OTG
Parallel Peripheral Interface
Removable Storage Interface
CAN
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
TWI
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
UART
ADC Control Module (ACM)
Link Ports
Ethernet MAC (IEEE 1588)
Pixel Compositor (PIXC)
No
1
1
Pipelined Vision Processor
(PVP) Video Resolution1
No
VGA
640
HD
Maximum PVP Line Buffer Size
GPIOs
N/A
1280
112
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADDRESS ARITHMETIC UNIT
SP
FP
P5
P4
P3
P2
P1
P0
I3
I2
I1
I0
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
DA1
DA0
32
32
32
PREG
32
RAB
SD
LD1
LD0
32
32
32
ASTAT
32
32
SEQUENCER
ALIGN
R7.H
R7.L
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
LOOP BUFFER
40
40
40 40
A0
A1
CONTROL
UNIT
32
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware supports zero-overhead looping.
The architecture is fully interlocked, meaning that the program-
mer need not manage the pipeline when executing instructions
with data dependencies.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
INSTRUCTION SET DESCRIPTION
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The data memory holds data,
and a dedicated scratchpad data memory stores stack and local
variable information.
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
a very small final memory size. The instruction set also provides
sequence. Descriptor-based DMA transfers allow multiple
DMA sequences to be chained together and a DMA channel can
be programmed to automatically set up and start another DMA
transfer after the current sequence completes.
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core
The DMA controller supports the following DMA operations.
• A single linear buffer that stops on completion.
• A linear buffer with negative, positive or zero stride length.
• A circular, auto-refreshing buffer that interrupts when each
buffer becomes full.
processor resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
• A similar buffer that interrupts on fractional buffers (for
example, 1/2, 1/4).
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• 1D DMA – uses a set of identical ping-pong buffers defined
by a linked ring of two-word descriptor sets, each contain-
ing a link pointer and an address.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
• 1D DMA – uses a linked list of 4 word descriptor sets con-
taining a link pointer, an address, a length, and a
configuration.
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified program-
ming model.
• 2D DMA – uses an array of one-word descriptor sets, spec-
ifying only the base DMA address.
• Control of all asynchronous and synchronous events to the
processor is handled by two subsystems: the Core Event
Controller (CEC) and the System Event Controller (SEC).
• 2D DMA – uses a linked list of multi-word descriptor sets,
specifying everything.
CRC Protection
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
The two CRC protection modules allow system software to peri-
odically calculate the signature of code and/or data in memory,
the content of memory-mapped registers, or communication
message objects. Dedicated hardware circuitry compares the
signature with pre calculated values and triggers appropriate
fault events.
• Code density enhancements, which include intermixing of
16-bit and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded
in 16 bits.
For example, every 100 ms the system software might initiate
the signature calculation of the entire memory contents and
compare these contents with expected, pre calculated values. If a
mismatch occurs, a fault condition can be generated (via the
processor core or the trigger routing unit).
PROCESSOR INFRASTRUCTURE
The following sections provide information on the primary
infrastructure components of the ADSP-BF609 processor.
The CRC is a hardware module based on a CRC32 engine that
computes the CRC value of the 32-bit data words presented to
it. Data is provided by the source channel of the memory-to-
memory DMA (in memory scan mode) and is optionally for-
warded to the destination channel (memory transfer mode).
The main features of the CRC peripheral are:
DMA Controllers
The processor uses Direct Memory Access (DMA) to transfer
data within memory spaces or between a memory space and a
peripheral. The processor can specify data transfer operations
and return to normal processing while the fully integrated DMA
controller carries out the data transfers independent of proces-
sor activity.
• Memory scan mode
• Memory transfer mode
DMA transfers can occur between memory and a peripheral or
between one memory and another memory. Each Memory-to-
memory DMA stream uses two channels, where one channel is
the source channel, and the second is the destination channel.
• Data verify mode
• Data fill mode
• User-programmable CRC32 polynomial
• Bit/byte mirroring option (endianness)
• Fault/error interrupt mechanisms
• 1D and 2D fill block to initialize array with constants.
All DMAs can transport data to and from all on-chip and off-
chip memories. Programs can use two types of DMA transfers,
descriptor-based or register-based. Register-based DMA allows
the processor to directly program DMA control registers to ini-
tiate a DMA transfer. On completion, the control registers may
be automatically updated with their original setup values for
continuous transfer. Descriptor-based DMA transfers require a
set of parameters stored within memory to initiate a DMA
• 32-bit CRC signature of a block of a memory or MMR
block.
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operation. Six system-level interrupt channels (PINT0–5) are
Event Handling
reserved for this purpose. Each of these interrupt channels can
manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed on a pin-by-pin basis. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
The processor provides event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher-priority event takes precedence over ser-
vicing of a lower-priority event. The processor provides support
for five different types of events:
Every pin interrupt channel features a special set of 32-bit mem-
ory-mapped registers that enable half-port assignment and
interrupt management. This includes masking, identification,
and clearing of requests. These registers also enable access to the
respective pin states and use of the interrupt latches, regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated either by the software watchdog timer, by the
NMI input signal to the processor, or by software. The
NMI event is frequently used as a power-down indicator to
initiate an orderly shutdown of the system.
General-Purpose I/O (GPIO)
Each general-purpose port pin can be individually controlled by
manipulation of the port control, status, and interrupt registers:
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – A “write one to mod-
ify” mechanism allows any combination of individual
GPIO pins to be modified in a single instruction, without
affecting the level of any other GPIO pins.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input signals, timers, and other
peripherals, as well as by an explicit software instruction.
• GPIO interrupt mask registers – Allow each individual
GPIO pin to function as an interrupt to the processor.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers. For more information, see the
ADSP-BF60x Processor Programmer’s Reference.
• GPIO interrupt sensitivity registers – Specify whether indi-
vidual pins are level- or edge-sensitive and specify—if
edge-sensitive—whether just the rising edge or both the ris-
ing and falling edges of the signal are significant.
System Event Controller (SEC)
Pin Multiplexing
The SEC manages the enabling, prioritization, and routing of
events from each system interrupt or fault source. Additionally,
it provides notification and identification of the highest priority
active system interrupt request to each core and routes system
fault sources to its integrated fault management unit.
The processor supports a flexible multiplexing scheme that mul-
tiplexes the GPIO pins with various peripherals. A maximum of
4 peripherals plus GPIO functionality is shared by each GPIO
pin. All GPIO pins have a bypass path feature – that is, when the
output enable and the input enable of a GPIO pin are both
active, the data signal before the pad driver is looped back to the
receive path for the same GPIO pin. For more information, see
GP I/O Multiplexing for 349-Ball CSP_BGA on Page 33.
Trigger Routing Unit (TRU)
The TRU provides system-level sequence control without core
intervention. The TRU maps trigger masters (generators of trig-
gers) to trigger slaves (receivers of triggers). Slave endpoints can
be configured to respond to triggers in various ways. Common
applications enabled by the TRU include:
MEMORY ARCHITECTURE
The processor views memory as a single unified 4G byte address
space, using 32-bit addresses. All resources, including internal
memory, external memory, and I/O control registers, occupy
separate sections of this common address space. The memory
portions of this address space are arranged in a hierarchical
structure to provide a good cost/performance balance of some
very fast, low-latency core-accessible memory as cache or
SRAM, and larger, lower-cost and performance interface-acces-
sible memory systems. See Figure 3 and Figure 4.
• Automatically triggering the start of a DMA sequence after
a sequence from another DMA channel completes
• Software triggering
• Synchronization of concurrent activities
Pin Interrupts
Every port pin on the processor can request interrupts in either
an edge-sensitive or a level-sensitive manner with programma-
ble polarity. Interrupt functionality is decoupled from GPIO
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Figure 3. ADSP-BF606 Internal/External Memory Map
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Figure 4. ADSP-BF607/ADSP-BF608/ADSP-BF609 Internal/External Memory Map
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Internal (Core-Accessible) Memory
Booting
The L1 memory system is the highest-performance memory
available to the Blackfin processor cores.
The processor has several mechanisms for automatically loading
internal and external memory after a reset. The boot mode is
defined by the SYS_BMODE input pins dedicated for this pur-
pose. There are two categories of boot modes. In master boot
modes, the processor actively loads data from parallel or serial
memories. In slave boot modes, the processor receives data
from external host devices.
Each core has its own private L1 memory. The modified Har-
vard architecture supports two concurrent 32-bit data accesses
along with an instruction fetch at full processor speed which
provides high bandwidth processor performance. In each core a
64K-byte block of data memory partners with an 80K-byte
memory block for instruction storage. Each data block is multi-
banked for efficient data exchange through DMA and can be
configured as SRAM. Alternatively, 16K bytes of each block can
be configured in L1 cache mode. The four-way set-associative
instruction cache and the 2 two-way set-associative data caches
greatly accelerate memory access performance, especially when
accessing external memories.
The boot modes are shown in Table 2. These modes are imple-
mented by the SYS_BMODE bits of the reset configuration
register and are sampled during power-on resets and software-
initiated resets.
Table 2. Boot Modes
SYS_BMODE Setting Boot Mode
The L1 memory domain also features a 4K-byte scratchpad
SRAM block which is ideal for storing local variables and the
software stack. All L1 memory is protected by a multi-parity bit
concept, regardless of whether the memory is operating in
SRAM or cache mode.
000
001
010
011
100
101
110
111
No boot/Idle
Memory
RSI0 Master
SPI0 Master
SPI0 Slave
Reserved
Outside of the L1 domain, L2 and L3 memories are arranged
using a Von Neumann topology. The L2 memory domain is a
unified instruction and data memory and can hold any mixture
of code and data required by the system design. The L2 memory
domain is accessible by both Blackfin cores through a dedicated
64-bit interface. It operates at SYSCLK frequency.
LP0 Slave
UART0 Slave
VIDEO SUBSYSTEM
The processor features up to 256K bytes of L2 SRAM which is
ECC-protected and organized in eight banks. Individual banks
can be made private to any of the cores or the DMA subsystem.
There is also a 32K-byte single-bank ROM in the L2 domain. It
contains boot code and safety functions.
The following sections describe the components of the proces-
sor’s video subsystem. These blocks are shown with blue
shading in Figure 1 on Page 1.
Video Interconnect (VID)
Static Memory Controller (SMC)
The Video Interconnect provides a connectivity matrix that
interconnects the Video Subsystem: three PPIs, the PIXC, and
the PVP. The interconnect uses a protocol to manage data
transfer among these video peripherals.
The SMC can be programmed to control up to four banks of
external memories or memory-mapped devices, with very flexi-
ble timing parameters. Each bank occupies a 64M byte segment
regardless of the size of the device used, so that these banks are
only contiguous if each is fully populated with 64M bytes of
memory.
Pipelined Vision Processor (PVP)
The PVP engine provides hardware implementation of signal
and image processing algorithms that are required for
co-processing and pre-processing of monochrome video frames
in ADAS applications, robotic systems, and other machine
applications.
Dynamic Memory Controller (DMC)
The DMC includes a controller that supports JESD79-2E com-
patible double data rate (DDR2) SDRAM and JESD209A low
power DDR (LPDDR) SDRAM devices.
The PVP works in conjunction with the Blackfin cores. It is
optimized for convolution and wavelet based object detection
and classification, and tracking and verification algorithms. The
PVP has the following processing blocks.
I/O Memory Space
The processor does not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.
• Four 5 × 5 16-bit convolution blocks optionally followed by
down scaling
• A 16-bit cartesian-to-polar coordinate conversion block
• A pixel edge classifier that supports 1st and 2nd derivative
modes
• An arithmetic unit with 32-bit addition, multiply and
divide
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• A 32-bit threshold block with 16 thresholds, a histogram,
and run-length encoding
• ITU-656 status word error detection and correction for
ITU-656 receive modes and ITU-656 preamble and status
word decode.
• Two 32-bit integral blocks that support regular and diago-
nal integrals
• Optional packing and unpacking of data to/from 32 bits
from/to 8 bits, 16 bits and 24 bits. If packing/unpacking is
enabled, endianness can be configured to change the order
of packing/unpacking of bytes/words.
• An up- and down-scaling unit with independent scaling
ratios for horizontal and vertical components
• Input and output formatters for compatibility with many
data formats, including Bayer input format
• RGB888 can be converted to RGB666 or RGB565 for trans-
mit modes.
The PVP can form a pipe of all the constituent algorithmic
modules and is dynamically reconfigurable to form different
pipeline structures.
• Various de-interleaving/interleaving modes for receiv-
ing/transmitting 4:2:2 YCrCb data.
• Configurable LCD data enable (DEN) output available on
Frame Sync 3.
The PVP supports the simultaneous processing of up to four
data streams. The memory pipe stream operates on data
received by DMA from any L1, L2, or L3 memory. The three
camera pipe streams operate on a common input received
directly from any of the three PPI inputs. Optionally, the PIXC
can convert color data received by the PPI and forward luma
values to the PVP’s monochrome engine. Each stream has a
dedicated DMA output. This preprocessing concept ensures
careful use of available power and bandwidth budgets and frees
up the processor cores for other tasks.
PROCESSOR SAFETY FEATURES
The ADSP-BF60x processor has been designed for functional
safety applications. While the level of safety is mainly domi-
nated by the system concept, the following primitives are
provided by the devices to build a robust safety concept.
Dual Core Supervision
The processor has been implemented as dual-core devices to
separate critical tasks to large independency. Software models
support mutual supervision of the cores in symmetrical fashion.
The PVP provides for direct core MMR access to all control/sta-
tus registers. Two hardware interrupts interface to the system
event controller. For optimal performance, the PVP allows reg-
ister programming through its control DMA interface, as well as
outputting selected status registers through the status DMA
interface. This mechanism enables the PVP to automatically
process job lists completely independent of the Blackfin cores.
Multi-Parity-Bit-Protected L1 Memories
In the processor’s L1 memory space, whether SRAM or cache,
each word is protected by multiple parity bits to detect the single
event upsets that occur in all RAMs. This applies both to L1
instruction and data memory spaces.
Pixel Compositor (PIXC)
The pixel compositor (PIXC) provides image overlays with
transparent-color support, alpha blending, and color space con-
version capabilities for output to TFT LCDs and NTSC/PAL
video encoders. It provides all of the control to allow two data
streams from two separate data buffers to be combined,
blended, and converted into appropriate forms for both LCD
panels and digital video outputs. The main image buffer pro-
vides the basic background image, which is presented in the
data stream. The overlay image buffer allows the user to add
multiple foreground text, graphics, or video objects on top of
the main image or video data stream.
ECC-Protected L2 Memories
Error correcting codes (ECC) are used to correct single event
upsets. The L2 memory is protected with a Single Error Correct-
Double Error Detect (SEC-DED) code. By default ECC is
enabled, but it can be disabled on a per-bank basis. Single-bit
errors are transparently corrected. Dual-bit errors can issue a
system event or fault if enabled. ECC protection is fully trans-
parent to the user, even if L2 memory is read or written by 8-bit
or 16-bit entities.
CRC-Protected Memories
Parallel Peripheral Interface (PPI)
While parity bit and ECC protection mainly protect against ran-
dom soft errors in L1 and L2 memory cells, the CRC engines can
be used to protect against systematic errors (pointer errors) and
static content (instruction code) of L1, L2 and even L3 memo-
ries (DDR2, LPDDR). The processors feature two CRC engines
which are embedded in the memory-to-memory DMA control-
lers. CRC check sums can be calculated or compared on the fly
during memory transfers, or one or multiple memory regions
can be continuously scrubbed by single DMA work unit as per
DMA descriptor chain instructions. The CRC engine also pro-
tects data loaded during the boot process.
The processor provides up to three parallel peripheral interfaces
(PPIs), supporting data widths up to 24 bits. The PPI supports
direct connection to TFT LCD panels, parallel analog-to-digital
and digital-to-analog converters, video encoders and decoders,
image sensor modules and other general-purpose peripherals.
The following features are supported in the PPI module:
• Programmable data length: 8 bits, 10 bits, 12 bits, 14 bits,
16 bits, 18 bits, and 24 bits per clock.
• Various framed, non-framed, and general-purpose operat-
ing modes. Frame syncs can be generated internally or can
be supplied by an external device.
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a “fault”. Additionally, the system events can be defined as an
interrupt to the cores. If defined as such, the SEC forwards the
Memory Protection
The Blackfin cores feature a memory protection concept, which
grants data and/or instruction accesses from enabled memory
regions only. A supervisor mode vs. user mode programming
model supports dynamically varying access rights. Increased
flexibility in memory page size options supports a simple
method of static memory partitioning.
event to the fault management unit which may automatically
reset the entire device for reboot, or simply toggle the SYS_
FAULT output pins to signal off-chip hardware. Optionally, the
fault management unit can delay the action taken via a keyed
sequence, to provide a final chance for the Blackfin cores to
resolve the crisis and to prevent the fault action from being
taken.
System Protection
All system resources and L2 memory banks can be controlled by
either the processor cores, memory-to-memory DMA, or the
system debug unit (SDU). A system protection unit (SPU)
enables write accesses to specific resources that are locked to
any of four masters: Core 0, Core 1, Memory DMA, and the Sys-
tem Debug Unit. System protection is enabled in greater
granularity for some modules (L2, SEC and GPIO controllers)
through a global lock concept.
ADDITIONAL PROCESSOR PERIPHERALS
The processor contains a rich set of peripherals connected to the
core via several high-bandwidth buses, providing flexibility in
system configuration as well as excellent overall system perfor-
mance (see the block diagram on Page 1). The processors
contain high-speed serial and parallel ports, an interrupt con-
troller for flexible management of interrupts from the on-chip
peripherals or external sources, and power management control
functions to tailor the performance and power characteristics of
the processor and system to many application scenarios.
Watchpoint Protection
The primary purpose of watchpoints and hardware breakpoints
is to serve emulator needs. When enabled, they signal an emula-
tor event whenever user-defined system resources are accessed
or a core executes from user-defined addresses. Watchdog
events can be configured such that they signal the events to the
other Blackfin core or to the fault management unit.
The following sections describe additional peripherals that were
not described in the previous sections.
Timers
The processor includes several timers which are described in the
following sections.
Dual Watchdog
General-Purpose Timers
The two on-chip watchdog timers each may supervise one
Blackfin core.
There is one GP timer unit and it provides eight general-pur-
pose programmable timers. Each timer has an external pin that
can be configured either as a pulse width modulator (PWM) or
timer output, as an input to clock the timer, or as a mechanism
for measuring pulse widths and periods of external events.
These timers can be synchronized to an external clock input on
the TMRx pins, an external clock TMRCLK input pin, or to the
internal SCLK0.
Bandwidth Monitor
All DMA channels that operate in memory-to-memory mode
(Memory DMA, PVP Memory Pipe DMA, PIXC DMA) are
equipped with a bandwidth monitor mechanism. They can sig-
nal a system event or fault when transactions tend to starve
because system buses are fully loaded with higher-priority
traffic.
The timer units can be used in conjunction with the UARTs and
the CAN controller to measure the width of the pulses in the
data stream to provide a software auto-baud detect function for
the respective serial channels.
Signal Watchdogs
The eight general-purpose timers feature two new modes to
monitor off-chip signals. The Watchdog Period mode monitors
whether external signals toggle with a period within an expected
range. The Watchdog Width mode monitors whether the pulse
widths of external signals are in an expected range. Both modes
help to detect incorrect undesired toggling (or lack thereof) of
system-level signals.
The timers can generate interrupts to the processor core, pro-
viding periodic events for synchronization to either the system
clock or to external signals. Timer events can also trigger other
peripherals via the TRU (for instance, to signal a fault).
Core Timers
Each processor core also has its own dedicated timer. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generating periodic operating
system interrupts.
Up/Down Count Mismatch Detection
The up/down counter can monitor external signal pairs, such as
request/grant strobes. If the edge count mismatch exceeds the
expected range, the up/down counter can flag this to the proces-
sor or to the fault management unit.
Watchdog Timers
Each core includes a 32-bit timer, which may be used to imple-
ment a software watchdog function. A software watchdog can
improve system availability by forcing the processor to a known
state, via generation of a hardware reset, nonmaskable interrupt
(NMI), or general-purpose interrupt, if the timer expires before
Fault Management
The fault management unit is part of the system event controller
(SEC). Any system event, whether a dual-bit uncorrectable ECC
error, or any peripheral status interrupt, can be defined as being
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being reset by software. The programmer initializes the count
value of the timer, enables the appropriate interrupt, then
enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown state
where software, which would normally reset the timer, has
stopped running due to an external noise condition or software
error.
Serial ports operate in five modes:
• Standard DSP serial mode
• Multichannel (TDM) mode
• I2S mode
• Packed I2S mode
• Left-justified mode
After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
timer control register, which is set only upon a watchdog gener-
ated reset.
ACM Interface
The ADC control module (ACM) provides an interface that
synchronizes the controls between the processor and an analog-
to-digital converter (ADC). The analog-to-digital conversions
are initiated by the processor, based on external or internal
events.
3-Phase PWM Units
The Pulse Width Modulator (PWM) module is a flexible and
programmable waveform generator. With minimal CPU inter-
vention the PWM peripheral is capable of generating complex
waveforms for motor control, Pulse Coded Modulation (PCM),
Digital to Analog Conversion (DAC), power switching and
power conversion. The PWM module has 4 PWM pairs capable
of 3-phase PWM generation for source inverters for AC induc-
tion and DC brush less motors.
The ACM allows for flexible scheduling of sampling instants
and provides precise sampling signals to the ADC.
Figure 5 shows how to connect an external ADC to the ACM
and one of the SPORTs.
The two 3-phase PWM generation units each feature:
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
SPT_AD1
SPT_AD0
SPORTx
SPT_CLK
SPT_FS
• Single update mode with option for asymmetric duty
• Programmable dead time and switching frequency
ADSP-BF60x
SPORT
SELECT
MUX
ACM_CLK
ACM_FS
• Twos-complement implementation which permits smooth
transition to full ON and full OFF states
ACM
ACM_A[2:0]
ACM_A3
ACM_A4
• Dedicated asynchronous PWM shutdown signal
Link Ports
RANGE
SGL/DIFF
A[2:0]
Four DMA-enabled, 8-bit-wide link ports can connect to the
link ports of other DSPs or processors. Link ports are bidirec-
tional ports having eight data lines, an acknowledge line and a
clock line.
ADC
CS
ADSCLK
D
D
A
B
OUT
OUT
Serial Ports (SPORTs)
Three synchronous serial ports that provide an inexpensive
interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices’ AD183x family of audio codecs,
ADCs, and DACs. The serial ports are made up of two data
lines, a clock, and frame sync. The data lines can be pro-
grammed to either transmit or receive and each data line has a
dedicated DMA channel.
Figure 5. ADC, ACM, and SPORT Connections
The ACM synchronizes the ADC conversion process, generat-
ing the ADC controls, the ADC conversion start signal, and
other signals. The actual data acquisition from the ADC is done
by a peripheral such as a SPORT or a SPI.
The processor interfaces directly to many ADCs without any
glue logic required.
Serial port data can be automatically transferred to and from
on-chip memory/external memory via dedicated DMA chan-
nels. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. In this configura-
tion, one SPORT provides two transmit signals while the other
SPORT provides the two receive signals. The frame sync and
clock are shared.
General-Purpose Counters
A 32-bit counter is provided that can operate in general-pur-
pose up/down count modes and can sense 2-bit quadrature or
binary codes as typically emitted by industrial drives or manual
thumbwheels. Count direction is either controlled by a level-
sensitive input pin or by two edge detectors.
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A third counter input can provide flexible zero marker support
To help support the Local Interconnect Network (LIN) proto-
cols, a special command causes the transmitter to queue a break
command of programmable bit length into the transmit buffer.
Similarly, the number of stop bits can be extended by a pro-
grammable inter-frame space.
and can alternatively be used to input the push-button signal of
thumb wheels. All three pins have a programmable debouncing
circuit.
Internal signals forwarded to each general-purpose timer enable
these timers to measure the intervals between count events.
Boundary registers enable auto-zero operation or simple system
warning by interrupts when programmable count values are
exceeded.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
TWI Controller Interface
Serial Peripheral Interface (SPI) Ports
The processors include a 2-wire interface (TWI) module for
providing a simple exchange method of control data between
multiple devices. The TWI module is compatible with the
widely used I2C bus standard. The TWI module offers the
capabilities of simultaneous master and slave operation and
support for both 7-bit addressing and multimedia data arbitra-
tion. The TWI interface utilizes two pins for transferring clock
(TWI_SCL) and data (TWI_SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compati-
ble with 5 V logic levels.
The processors have two SPI-compatible ports that allow the
processor to communicate with multiple SPI-compatible
devices.
In its simplest mode, the SPI interface uses three pins for trans-
ferring data: two data pins (Master Output-Slave Input, MOSI,
and Master Input-Slave Output, MISO) and a clock pin (serial
clock, SPI_CLK). A SPI chip select input pin (SPI_SS) lets other
SPI devices select the processor, and seven SPI chip select out-
put pins (SPI_SEL7–1) let the processor select other SPI devices.
The SPI select pins are reconfigured general-purpose I/O pins.
Using these pins, the SPI port provides a full-duplex, synchro-
nous serial interface, which supports both master/slave modes
and multimaster environments.
Additionally, the TWI module is fully compatible with serial
camera control bus (SCCB) functionality for easier control of
various CMOS camera sensor devices.
Removable Storage Interface (RSI)
In a multi-master or multi-slave SPI system, the MOSI and
MISO data output pins can be configured to behave as open
drain outputs (using the ODM bit) to prevent contention and
possible damage to pin drivers. An external pull-up resistor is
required on both the MOSI and MISO pins when this option is
selected.
The removable storage interface (RSI) controller acts as the host
interface for multimedia cards (MMC), secure digital memory
cards (SD), secure digital input/output cards (SDIO). The fol-
lowing list describes the main features of the RSI controller.
• Support for a single MMC, SD memory, SDIO card
• Support for 1-bit and 4-bit SD modes
When ODM is set and the SPI is configured as a master, the
MOSI pin is three-stated when the data driven out on MOSI is a
logic-high. The MOSI pin is not three-stated when the driven
data is a logic-low. Similarly, when ODM is set and the SPI is
configured as a slave, the MISO pin is three-stated if the data
driven out on MISO is a logic-high.
• Support for 1-bit, 4-bit, and 8-bit MMC modes
• Support for eMMC 4.3 embedded NAND flash devices
• A ten-signal external interface with clock, command, and
up to eight data lines
The SPI port’s baud rate and clock phase/polarities are pro-
grammable, and it has integrated DMA channels for both
transmit and receive data streams.
• Card interface clock generation from SCLK0
• SDIO interrupt and read wait features
Controller Area Network (CAN)
UART Ports
A CAN controller implements the CAN 2.0B (active) protocol.
This protocol is an asynchronous communications protocol
used in both industrial and automotive control systems. The
CAN protocol is well suited for control applications due to its
capability to communicate reliably over a network. This is
because the protocol incorporates CRC checking, message error
tracking, and fault node confinement.
The processors provide two full-duplex universal asynchronous
receiver/transmitter (UART) ports, which are fully compatible
with PC-standard UARTs. Each UART port provides a simpli-
fied UART interface to other peripherals or hosts, supporting
full-duplex, DMA-supported, asynchronous transfers of serial
data. A UART port includes support for five to eight data bits,
and none, even, or odd parity. Optionally, an additional address
bit can be transferred to interrupt only addressed nodes in
multi-drop bus (MDB) systems. A frame is terminates by one,
one and a half, two or two and a half stop bits.
The CAN controller offers the following features:
• 32 mailboxes (8 receive only, 8 transmit only, 16 configu-
rable for receive or transmit).
The UART ports support automatic hardware flow control
through the Clear To Send (CTS) input and Request To Send
(RTS) output with programmable assertion FIFO levels.
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29-
bit) identifier (ID) message formats.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
• Support for remote frames.
(PTP_TSYNC). This engine provides hardware assisted time
stamping to improve the accuracy of clock synchronization
between PTP nodes. The main features of the engine are:
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
consumption mode).
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Interrupts, including: TX complete, RX complete, error
and global.
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
An additional crystal is not required to supply the CAN clock, as
the CAN clock is derived from a system clock through a pro-
grammable divider.
• Lock adjustment
• Automatic detection of IPv4 and IPv6 packets, as well as
PTP messages
10/100 Ethernet MAC
• Multiple input clock sources (SCLK0, RMII clock, external
clock)
The processor can directly connect to a network by way of an
embedded fast Ethernet media access controller (MAC) that
supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M
bits/sec) operation. The 10/100 Ethernet MAC peripheral on the
processor is fully compliant to the IEEE 802.3-2002 standard
and it provides programmable features designed to minimize
supervision, bus use, or message processing by the rest of the
processor system.
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
USB 2.0 On-the-Go Dual-Role Device Controller
The USB 2.0 OTG dual-role device controller provides a low-
cost connectivity solution for the growing adoption of this bus
standard in industrial applications, as well as consumer mobile
devices such as cell phones, digital still cameras, and MP3 play-
ers. The USB 2.0 controller allows these devices to transfer data
using a point-to-point USB connection without the need for a
PC host. The module can operate in a traditional USB periph-
eral-only mode as well as the host mode presented in the On-
the-Go (OTG) supplement to the USB 2.0 specification.
Some standard features are:
• Support and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Media access management (in half-duplex operation)
• Flow control
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
The USB clock (USB_CLKIN) is provided through a dedicated
external crystal or crystal oscillator.
Some advanced features are:
The USB On-the-Go dual-role device controller includes a
Phase Locked Loop with programmable multipliers to generate
the necessary internal clocking frequency for USB.
• Automatic checksum computation of IP header and IP
payload fields of RX frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
POWER AND CLOCK MANAGEMENT
The processor provides four operating modes, each with a dif-
ferent performance/power profile. When configured for a 0 V
internal supply voltage (VDD_INT), the processor enters the hiber-
nate state. Control of clocking to each of the processor
peripherals also reduces power consumption. See Table 5 for a
summary of the power settings for each mode.
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• TX DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
• Convenient frame alignment modes
Crystal Oscillator (SYS_XTAL)
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
The processor can be clocked by an external crystal, (Figure 6) a
sine wave input, or a buffered, shaped clock derived from an
external clock oscillator. If an external clock is used, it should be
a TTL compatible signal and must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s SYS_CLKIN
pin. When an external clock is used, the SYS_XTAL pin must be
left unconnected. Alternatively, because the processor includes
an on-chip oscillator circuit, an external crystal may be used.
• Advanced power management
• Magic packet detection and wakeup frame filtering
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
IEEE 1588 Support
For fundamental frequency operation, use the circuit shown in
Figure 6. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected across the SYS_CLKIN and
XTAL pins. The on-chip resistance between SYS_CLKIN and
the XTAL pin is in the 500 kΩ range. Further parallel resistors
are typically not recommended.
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
processor includes hardware support for IEEE 1588 with an
integrated precision time protocol synchronization engine
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
BLACKFIN
BLACKFIN
TO PLL
CIRCUITRY
TO USB PLL
ꢅꢁꢀȍ2
ꢄꢅꢁȍ
5-12 pf1, 2
SYS_CLKIN
18 pF*
SYS_XTAL
ꢃꢃꢁȍ
*
FOR OVERTONE
OPERATION ONLY:
NOTES:
1. CAPACITANCE VALUE SHOWN INCLUDES BOARD PARASITICS
2. VALUES ARE A PRELIMINARY ESTIMATE.
18 pF *
Figure 7. External USB Crystal Connection
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING
ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR
FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE
OF 18pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED
5(6,6725ꢀ9$/8(ꢀ6+28/'ꢀ%(ꢀ5('8&('ꢀ72ꢀꢁꢀȍꢂ
The crystal should be chosen so that its rated load capacitance
matches the nominal total capacitance on this node. A series
resistor may be added between the USB_XTAL pin and the par-
allel crystal and capacitor combination, in order to further
reduce the drive level of the crystal.
Figure 6. External Crystal Connection
The parallel capacitor and the series resistor shown in Figure 7
fine tune phase and amplitude of the sine frequency. The capac-
itor and resistor values shown in Figure 7 are typical values
only. The capacitor values are dependent upon the crystal man-
ufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations on multiple
devices over temperature range.
The two capacitors and the series resistor shown in Figure 6 fine
tune phase and amplitude of the sine frequency. The capacitor
and resistor values shown in Figure 6 are typical values only.
The capacitor values are dependent upon the crystal manufac-
turers’ load capacitance recommendations and the PCB physical
layout. The resistor value depends on the drive level specified by
the crystal manufacturer. The user should verify the customized
values based on careful investigations on multiple devices over
temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone oper-
ation is discussed in detail in application note (EE-168) Using
Third Overtone Crystals with the ADSP-218x DSP on the Ana-
log Devices website (www.analog.com)—use site search on
“EE-168.”
Clock Generation
The clock generation unit (CGU) generates all on-chip clocks
and synchronization signals. Multiplication factors are pro-
grammed to the PLL to define the PLLCLK frequency.
Programmable values divide the PLLCLK frequency to generate
the core clock (CCLK), the system clocks (SYSCLK, SCLK0 and
SCLK1), the LPDDR or DDR2 clock (DCLK) and the output
clock (OCLK). This is illustrated in Figure 8 on Page 53.
USB Crystal Oscillator
Writing to the CGU control registers does not affect the behav-
ior of the PLL immediately. Registers are first programmed with
a new value, and the PLL logic executes the changes so that it
transitions smoothly from the current conditions to the new
ones.
The USB can be clocked by an external crystal, a sine wave
input, or a buffered, shaped clock derived from an external
clock oscillator. If an external clock is used, it should be a TTL
compatible signal and must not be halted, changed, or operated
below the specified frequency during normal operation. This
signal is connected to the processor’s USB_XTAL pin. Alterna-
tively, because the processor includes an on-chip oscillator
circuit, an external crystal may be used.
SYS_CLKIN oscillations start when power is applied to the VDD_
EXT pins. The rising edge of SYS_HWRST can be applied after all
voltage supplies are within specifications (see Operating Condi-
tions on Page 52), and SYS_CLKIN oscillations are stable.
For fundamental frequency operation, use the circuit shown in
Figure 7. A parallel-resonant, fundamental frequency, micro-
processor grade crystal is connected between the USB_XTAL
pin and ground. A load capacitor is placed in parallel with the
crystal. The combined capacitive value of the board trace para-
sitic, the case capacitance of the crystal (from crystal
manufacturer) and the parallel capacitor in the diagram should
be in the range of 8 pF to 15 pF.
Clock Out/External Clock
The SYS_CLKOUT output pin has programmable options to
output divided-down versions of the on-chip clocks. By default,
the SYS_CLKOUT pin drives a buffered version of the SYS_
CLKIN input. Clock generation faults (for example PLL unlock)
may trigger a reset by hardware. The clocks shown in Table 3
can be outputs from SYS_CLKOUT.
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Table 3. Clock Dividers
See Table 5 for a summary of the power settings for each mode.
Clock Source
Divider
By 4
Table 5. Power Settings
CCLK (core clock)
SYSCLK (System clock)
fSYSCLK,
fDCLK,
By 2
SCLK0 (system clock for PVP, all None
peripherals not covered by
SCLK1)
PLL
Bypassed fCCLK
f
SCLK0,
Core
Power
Mode/State PLL
fSCLK1
Full On
Active
Enabled No
Enabled Enabled
Enabled Enabled
On
On
SCLK1 (system clock for SPORTS, None
SPI, ACM)
Enabled/ Yes
Disabled
DCLK (LPDDR/DDR2 clock)
OCLK (output clock)
CLKBUF
By 2
Deep Sleep Disabled —
Hibernate Disabled —
Disabled Disabled On
Disabled Disabled Off
Programmable
None, direct from SYS_CLKIN
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
Power Management
As shown in Table 4, the processor supports five different power
domains, which maximizes flexibility while maintaining com-
pliance with industry standards and conventions. There are no
sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate Specifi-
cations table for processor operating conditions; even if the
feature/peripheral is not used.
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core and to all synchronous
peripherals. Asynchronous peripherals may still be running but
cannot access internal resources or external memory.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor cores and to all of the
peripherals. This setting signals the external voltage regulator
supplying the VDD_INT pins to shut off using the SYS_
EXTWAKE signal, which provides the lowest static power dissi-
pation. Any critical information stored internally (for example,
memory contents, register contents, and other information)
must be written to a non-volatile storage device prior to remov-
ing power if the processor state is to be preserved.
Table 4. Power Domains
Power Domain
All internal logic
DDR2/LPDDR
USB
VDD Range
VDD_INT
VDD_DMC
VDD_USB
Thermal diode
VDD_TD
Since the VDD_EXT pins can still be supplied in this mode, all of
the external pins three-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
still have power applied without drawing unwanted current.
All other I/O (includes SYS, JTAG, and Ports pins) VDD_EXT
The dynamic power management feature of the processor
allows the processor’s core clock frequency (fCCLK) to be dynam-
ically controlled.
Reset Control Unit
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in dynamic power dissipation.
Reset is the initial state of the whole processor or one of the
cores and is the result of a hardware or software triggered event.
In this state, all control registers are set to their default values
and functional units are idle. Exiting a full system reset starts
with Core-0 only being ready to boot. Exiting a Core-n only
reset starts with this Core-n being ready to boot.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor cores and all enabled
peripherals run at full speed.
The Reset Control Unit (RCU) controls how all the functional
units enter and exit reset. Differences in functional require-
ments and clocking constraints define how reset signals are
generated. Programs must guarantee that none of the reset
functions puts the system into an undefined state or causes
resources to stall. This is particularly important when only one
of the cores is reset (programs must ensure that there is no
pending system activity involving the core that is being reset).
Active Operating Mode—Moderate Dynamic Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clocks and system clocks
run at the input clock (SYS_CLKIN) frequency. DMA access is
available to appropriately configured L1 memories.
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF60x Blackfin Pro-
cessor Hardware Reference.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
From a system perspective reset is defined by both the reset tar-
get and the reset source as described below.
System Debug Unit
The System Debug Unit (SDU) provides IEEE-1149.1 support
through its JTAG interface. In addition to traditional JTAG fea-
tures, present in legacy Blackfin products, the SDU adds more
features for debugging the chip without halting the core
processors.
Target defined:
• Hardware Reset – All functional units are set to their
default states without exception. History is lost.
• System Reset – All functional units except the RCU are set
to their default states.
DEVELOPMENT TOOLS
• Core-n only Reset – Affects Core-n only. The system soft-
ware should guarantee that the core in reset state is not
accessed by any bus master.
Analog Devices supports its processors with a complete line of
software and hardware development tools, including integrated
development environments (which include CrossCore® Embed-
ded Studio and/or VisualDSP++®), evaluation products,
emulators, and a wide variety of software add-ins.
Source defined:
• Hardware Reset – The SYS_HWRST input signal is
asserted active (pulled down).
Integrated Development Environments (IDEs)
• System Reset – May be triggered by software (writing to the
RCU_CTL register) or by another functional unit such as
the dynamic power management (DPM) unit (Hibernate)
or any of the system event controller (SEC), trigger routing
unit (TRU), or emulator inputs.
For C/C++ software writing and editing, code generation, and
debug support, Analog Devices offers two IDEs.
The newest IDE, CrossCore Embedded Studio, is based on the
TM
Eclipse framework. Supporting most Analog Devices proces-
sor families, it is the IDE of choice for future processors,
including multicore devices. CrossCore Embedded Studio
seamlessly integrates available software add-ins to support real
time operating systems, file systems, TCP/IP stacks, USB stacks,
algorithmic software modules, and evaluation hardware board
support packages. For more information visit
• Core-n-only reset – Triggered by software.
• Trigger request (peripheral).
Voltage Regulation
The processor requires an external voltage regulator to power
the VDD_INT pins. To reduce standby power consumption, the
external voltage regulator can be signaled through SYS_
EXTWAKE to remove power from the processor core. This sig-
nal is high-true for power-up and may be connected directly to
the low-true shut-down input of many common regulators.
www.analog.com/cces.
The other Analog Devices IDE, VisualDSP++, supports proces-
sor families introduced prior to the release of CrossCore
Embedded Studio. This IDE includes the Analog Devices VDK
real time operating system and an open source TCP/IP stack.
For more information visit www.analog.com/visualdsp. Note
that VisualDSP++ will not support future Analog Devices
processors.
While in the hibernate state, all external supply pins (VDD_EXT
,
VDD_USB, VDD_DMC) can still be powered, eliminating the need for
external buffers. The external voltage regulator can be activated
from this power down state by asserting the SYS_HWRST pin,
which then initiates a boot sequence. SYS_EXTWAKE indicates
a wakeup to the external voltage regulator.
EZ-KIT Lite Evaluation Board
For processor evaluation, Analog Devices provides wide range
of EZ-KIT Lite® evaluation boards. Including the processor and
key peripherals, the evaluation board also supports on-chip
emulation capabilities and other evaluation and development
features. Also available are various EZ-Extenders®, which are
daughter cards delivering additional specialized functionality,
including audio and video processing. For more information
visit www.analog.com and search on “ezkit” or “ezextender”.
SYSTEM DEBUG
The processor includes various features that allow for easy sys-
tem debug. These are described in the following sections.
System Watchpoint Unit
The System Watchpoint Unit (SWU) is a single module which
connects to a single system bus and provides for transaction
monitoring. One SWU is attached to the bus going to each sys-
tem slave. The SWU provides ports for all system bus address
channel signals. Each SWU contains four match groups of regis-
ters with associated hardware. These four SWU match groups
operate independently, but share common event (interrupt,
trigger and others) outputs.
EZ-KIT Lite Evaluation Kits
For a cost-effective way to learn more about developing with
Analog Devices processors, Analog Devices offer a range of EZ-
KIT Lite evaluation kits. Each evaluation kit includes an EZ-KIT
Lite evaluation board, directions for downloading an evaluation
version of the available IDE(s), a USB cable, and a power supply.
The USB controller on the EZ-KIT Lite board connects to the
USB port of the user’s PC, enabling the chosen IDE evaluation
suite to emulate the on-board processor in-circuit. This permits
the customer to download, execute, and debug programs for the
EZ-KIT Lite system. It also supports in-circuit programming of
the on-board Flash device to store user-specific boot code,
enabling standalone operation. With the full version of
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
CrossCore Embedded Studio or VisualDSP++ installed (sold
separately), engineers can develop software for supported EZ-
KITs or any custom system utilizing supported Analog Devices
processors.
For details on target board design issues including mechanical
layout, single processor connections, signal buffering, signal ter-
mination, and emulator pod logic, see the EE-68: Analog Devices
JTAG Emulation Technical Reference on the Analog Devices
website (www.analog.com)—use site search on “EE-68.” This
document is updated regularly to keep pace with improvements
to emulator support.
Software Add-Ins for CrossCore Embedded Studio
Analog Devices offers software add-ins which seamlessly inte-
grate with CrossCore Embedded Studio to extend its capabilities
and reduce development time. Add-ins include board support
packages for evaluation hardware, various middleware pack-
ages, and algorithmic modules. Documentation, help,
configuration dialogs, and coding examples present in these
add-ins are viewable through the CrossCore Embedded Studio
IDE once the add-in is installed.
ADDITIONAL INFORMATION
The following publications that describe the ADSP-BF606/
ADSP-BF607/ADSP-BF608/ADSP-BF609 processors (and
related processors) can be ordered from any Analog Devices
sales office or accessed electronically on our website:
• Getting Started With Blackfin Processors
Board Support Packages for Evaluation Hardware
• ADSP-BF60x Blackfin Processor Hardware Reference
• Blackfin Processor Programming Reference
• ADSP-BF60x Blackfin Processor Anomaly List
Software support for the EZ-KIT Lite evaluation boards and EZ-
Extender daughter cards is provided by software add-ins called
Board Support Packages (BSPs). The BSPs contain the required
drivers, pertinent release notes, and select example code for the
given evaluation hardware. A download link for a specific BSP is
located on the web page for the associated EZ-KIT or EZ-
Extender product. The link is found in the Product Download
area of the product web page.
RELATED SIGNAL CHAINS
A signal chain is a series of signal-conditioning electronic com-
ponents that receive input (data acquired from sampling either
real-time phenomena or from stored data) in tandem, with the
output of one portion of the chain supplying input to the next.
Signal chains are often used in signal processing applications to
gather and process data or to apply system controls based on
analysis of real-time phenomena. For more information about
this term and related topics, see the “signal chain” entry in the
Glossary of EE Terms on the Analog Devices website.
Middleware Packages
Analog Devices separately offers middleware add-ins such as
real time operating systems, file systems, USB stacks, and
TCP/IP stacks. For more information see the following web
pages:
Analog Devices eases signal processing system development by
providing signal processing components that are designed to
work together well. A tool for viewing relationships between
specific applications and related components is available on the
www.analog.com website.
• www.analog.com/ucos3
• www.analog.com/ucfs
• www.analog.com/ucusbd
• www.analog.com/lwip
The Application Signal Chains page in the Circuits from the
TM
Algorithmic Modules
Lab site (http:\\www.analog.com\circuits) provides:
To speed development, Analog Devices offers add-ins that per-
form popular audio and video processing algorithms. These are
available for use with both CrossCore Embedded Studio and
VisualDSP++. For more information visit www.analog.com and
search on “Blackfin software modules”.
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
• Drill down links for components in each chain to selection
guides and application information
• Reference designs applying best practice design techniques
Designing an Emulator-Compatible DSP Board (Target)
For embedded system test and debug, Analog Devices provides
a family of emulators. On each JTAG DSP, Analog Devices sup-
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit
emulation is facilitated by use of this JTAG interface. The emu-
lator accesses the processor’s internal features via the
processor’s TAP, allowing the developer to load code, set break-
points, and view variables, memory, and registers. The
processor must be halted to send data and commands, but once
an operation is completed by the emulator, the DSP system is set
to run at full speed with no impact on system timing. The emu-
lators require the target board to include a header that supports
connection of the DSP’s JTAG port to the emulator.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DETAILED SIGNAL DESCRIPTIONS
Table 6 provides a detailed description of each signal.
Table 6. Detailed Signal Descriptions
Signal Name
ACM_An
ACM_CLK
ACM_FS
Direction
Output
Output
Output
Input
Description
ADC Control Signals Function varies by mode.
Clock SCLK derived clock for connecting to an ADC.
Frame Sync Typically used as an ADC chip select.
External Trigger n Input for external trigger events.
Receive Typically an external CAN transceiver's RX output.
Transmit Typically an external CAN transceiver's TX input.
ACM_Tn
CAN_RX
Input
CAN_TX
Output
Input
CNT_DG
Count Down and Gate Depending on the mode of operation this input acts either as a count down
signal or a gate signal.
Count Down: This input causes the GP counter to decrement.
Gate: Stops the GP counter from incrementing or decrementing.
CNT_UD
Input
Count Up and Direction Depending on the mode of operation this input acts either as a count up signal
or a direction signal.
Count Up: This input causes the GP counter to increment.
Direction: Selects whether the GP counter is incrementing or decrementing.
CNT_ZM
Input
Count Zero Marker Input that connects to the zero marker output of a rotary device or detects the
pressing of a push button.
DMC_Ann
DMC_BAn
Output
Output
Address n Address bus.
BankAddressInputn DefineswhichinternalbankanACTIVATE,READ, WRITE,orPRECHARGEcommand
is being applied to on the dynamic memory. Also defines which mode registers (MR, EMR, EMR2, and/or
EMR3) are loaded during the LOAD MODE REGISTER command.
DMC_CAS
Output
Column Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the CAS input of dynamic memory.
DMC_CK
Output
Output
Output
Output
I/O
Clock (complement) Complement of DMC_CK.
DMC_CK
Clock Outputs DCLK to external dynamic memory.
DMC_CKE
DMC_CSn
DMC_DQnn
DMC_LDM
Clock enable Active high clock enables. Connects to the dynamic memory’s CKE input.
Chip Select n Commands are recognized by the memory only when this signal is asserted.
Data n Bidirectional data bus.
Output
Data Mask for Lower Byte Mask for DMC_DQ07:DMC_DQ00 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
DMC_LDQS
DMC_LDQS
I/O
I/O
Data Strobe for Lower Byte (complement) Complement of LDQS. Not used in single-ended mode.
Data Strobe for Lower Byte DMC_DQ07:DMC_DQ00 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_ODT
DMC_RAS
DMC_UDM
Output
Output
Output
On-die Termination Enables dynamic memory termination resistances when driven high (assuming
the memory is properly configured). ODT is enabled/disabled regardless of read or write commands.
Row Address Strobe Defines the operation for external dynamic memory to perform in conjunction
with other DMC command signals. Connect to the RAS input of dynamic memory.
Data Mask for Upper Byte Mask for DMC_DQ15:DMC_DQ08 write data when driven high. Sampled on
both edges of the data strobe by the dynamic memory.
DMC_UDQS
DMC_UDQS
I/O
I/O
Data Strobe for Upper Byte (complement) Complement of UDQS. Not used in single-ended mode.
Data Strobe for Upper Byte DMC_DQ15:DMC_DQ08 data strobe. Output with Write Data. Input with
Read Data. May be single-ended or differential depending on register settings.
DMC_WE
Output
Write Enable Defines the operation for external dynamic memory to perform in conjunction with other
DMC command signals. Connect to the WE input of dynamic memory.
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Table 6. Detailed Signal Descriptions (Continued)
Signal Name
Direction
Description
ETH_CRS
Input
Carrier Sense/RMII Receive Data Valid Multiplexed on alternate clock cycles.
CRS: Asserted by the PHY when either the transmit or receive medium is not idle. De-asserted when both
are idle.
RXDV: Asserted by the PHY when the data on RXDn is valid.
ETH_MDC
Output
I/O
Management Channel Clock Clocks the MDC input of the PHY.
ETH_MDIO
Management Channel Serial Data Bidirectional data bus for PHY control.
ETH_PTPAUXIN
Input
PTP Auxiliary Trigger Input Assert this signal to take an auxiliary snapshot of the time and store it in
the auxiliary time stamp FIFO.
ETH_PTPCLKIN
ETH_PTPPPS
Input
PTP Clock Input Optional external PTP clock input.
Output
PTP Pulse-Per-Second Output When the Advanced Time Stamp feature is enabled, this signal is
asserted based on the PPS mode selected. Otherwise, PTPPPS is asserted every time the seconds counter
is incremented.
ETH_REFCLK
ETH_RXDn
ETH_TXDn
ETH_TXEN
JTG_EMU
JTG_TCK
Input
Input
Output
I/O
Reference Clock Externally supplied Ethernet clock.
Receive Data n Receive data bus.
Transmit Data n Transmit data bus.
Transmit Enable When asserted indicates that the data on TXDn is valid.
Emulation Output JTAG emulation flag.
Output
Input
Input
Output
Input
Input
I/O
Clock JTAG test access port clock.
JTG_TDI
Serial Data In JTAG test access port data input.
Serial Data Out JTAG test access port data output.
Mode Select JTAG test access port mode select.
Reset JTAG test access port reset.
JTG_TDO
JTG_TMS
JTG_TRST
LP_ACK
Acknowledge Provides handshaking. When the link port is configured as a receiver, ACK is an output.
When the link port is configured as a transmitter, ACK is an input.
LP_CLK
I/O
Clock When the link port is configured as a receiver, CLK is an input. When the link port is configured as
a transmitter, CLK is an output.
LP_Dn
I/O
I/O
I/O
I/O
Data n Data bus. Input when receiving, output when transmitting.
Clock Input in external clock mode, output in internal clock mode.
Data n Bidirectional data bus.
PPI_CLK
PPI_Dnn
PPI_FS1
Frame Sync 1 (HSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
PPI_FS2
PPI_FS3
I/O
I/O
Frame Sync 2 (VSYNC) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
Frame Sync 3 (FIELD) Behavior depends on PPI mode. See the PPI chapter in the processor hardware
reference for more details.
PWM_AH
PWM_AL
PWM_BH
PWM_BL
PWM_CH
PWM_CL
PWM_DH
PWM_DL
PWM_SYNC
Output
Output
Output
Output
Output
Output
Output
Output
Input
Channel A High Side High side drive signal.
Channel A Low Side Low side drive signal.
Channel B High Side High side drive signal.
Channel B Low Side Low side drive signal.
Channel C High Side High side drive signal.
Channel C Low Side Low side drive signal.
Channel D High Side High side drive signal.
Channel D Low Side Low side drive signal.
PWM External Sync This input is for an externally generated sync signal. If the sync signal is internally
generated no connection is necessary.
PWM_TRIPn
Px_nn
Input
I/O
Shutdown Input n When asserted the selected PWM channel outputs are shut down immediately.
Position n General purpose input/output. See the GP Ports chapter in the processor hardware reference
for programming information.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 6. Detailed Signal Descriptions (Continued)
Signal Name
RSI_CLK
Direction
Output
I/O
Description
Clock The clock signal applied to the connected device from the RSI.
Command Used to send commands to and receive responses from the connected device.
Data n Bidirectional data bus.
RSI_CMD
RSI_Dn
I/O
SMC_ABEn
Output
Byte Enable n Indicate whether the lower or upper byte of a memory is being accessed. When an
asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 =0 and SMC_ABE0 =1.
When an asynchronous write is made to the lower byte of a 16-bit memory, SMC_ABE1 =1 and
SMC_ABE0 =0.
SMC_AMSn
SMC_Ann
SMC_AOE
SMC_ARDY
Output
Output
Output
Input
Memory Select n Typically connects to the chip select of a memory device.
Address n Address bus.
Output Enable Asserts at the beginning of the setup period of a read access.
Asynchronous Ready Flow control signal used by memory devices to indicate to the SMC when further
transactions may proceed.
SMC_ARE
SMC_AWE
SMC_BG
Output
Output
Output
Read Enable Asserts at the beginning of a read access.
Write Enable Asserts for the duration of a write access period.
Bus Grant Output used to indicate to an external device that it has been granted control of the SMC
buses.
SMC_BGH
Output
Bus Grant Hang Output used to indicate that the SMC has a pending transaction which requires control
of the bus to be restored before it can be completed.
SMC_BR
Input
I/O
Bus Request Input used by an external device to indicate that it is requesting control of the SMC buses.
Data n Bidirectional data bus.
SMC_Dnn
SMC_NORCLK
SMC_NORDV
SMC_NORWT
Output
Output
Input
NOR Clock Clock for synchronous burst mode.
NOR Data Valid Asserts for the duration of a synchronous burst mode read setup period.
NOR Wait Flow control signal used by memory devices in synchronous burst mode to indicate to the
SMC when further transactions may proceed.
SPI_CLK
SPI_D2
I/O
I/O
I/O
I/O
Clock Input in slave mode, output in master mode.
Data 2 Used to transfer serial data in quad mode. Open drain in ODM mode.
Data 3 Used to transfer serial data in quad mode. Open drain in ODM mode.
SPI_D3
SPI_MISO
Master In, Slave Out Used to transfer serial data. Operates in the same direction as SPI_MOSI in dual
and quad modes. Open drain in ODM mode.
SPI_MOSI
I/O
Master Out, Slave In Used to transfer serial data. Operates in the same direction as SPI_MISO in dual
and quad modes. Open drain in ODM mode.
SPI_RDY
SPI_SELn
SPI_SS
I/O
Ready Optional flow signal. Output in slave mode, input in master mode.
Slave Select Output n Used in master mode to enable the desired slave.
Output
Input
Slave Select Input Slave mode: acts as the slave select input. Master mode: optionally serves as an error
detection input for the SPI when there are multiple masters.
SPT_ACLK
SPT_AD0
SPT_AD1
SPT_AFS
SPT_ATDV
SPT_BCLK
SPT_BD0
I/O
Channel A Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be
either internally or externally generated.
I/O
Channel A Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit
serial data, or as an input to receive serial data.
I/O
Channel A Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
I/O
Channel A Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
Output
I/O
Channel A Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
Channel B Clock Data and frame sync are driven/sampled with respect to this clock. This signal can be
either internally or externally generated.
I/O
Channel B Data 0 Primary bidirectional data I/O. This signal can be configured as an output to transmit
serial data, or as an input to receive serial data.
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Table 6. Detailed Signal Descriptions (Continued)
Signal Name
Direction
Description
SPT_BD1
I/O
Channel B Data 1 Secondary bidirectional data I/O. This signal can be configured as an output to
transmit serial data, or as an input to receive serial data.
SPT_BFS
I/O
Channel B Frame Sync The frame sync pulse initiates shifting of serial data. This signal is either
generated internally or externally.
SPT_BTDV
Output
Channel B Transmit Data Valid This signal is optional and only active when SPORT is configured in
multi-channel transmit mode. It is asserted during enabled slots.
SYS_BMODEn
SYS_CLKIN
Input
Boot Mode Control n Selects the boot mode of the processor.
Clock/Crystal Input Connect to an external clock source or crystal.
Input
SYS_CLKOUT
Output
Processor Clock Output Outputs internal clocks. Clocks may be divided down. See the CGU chapter in
the processor hardware reference for more details.
SYS_EXTWAKE
Output
External Wake Control Drives low during hibernate and high all other times. Typically connected to the
enable input of the voltage regulator controlling the VDD_INT supply.
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_IDLEn
SYS_NMI
I/O
Complementary Fault Complement of SYS_FAULT.
I/O
Fault Indicates internal faults or senses external faults depending on the operating mode.
Processor Hardware Reset Control Resets the device when asserted.
Core n Idle Indicator When low indicates that core n is in idle mode or being held in reset.
Input
Output
Input
Non-maskable Interrupt Priority depends on the core that receives the interrupt. See the processor
hardware and programming references for more details.
SYS_PWRGD
Input
Power Good Indicator When high it indicates to the processor that the VDD_INT level is within specifica-
tions such that it is safe to begin booting upon return from hibernate.
SYS_RESOUT
SYS_SLEEP
Output
Output
Reset Output Indicates that the device is in the reset state.
Processor Sleep Indicator When low indicates that the processor is in the deep sleep power saving
mode.
SYS_TDA
SYS_TDK
Input
Input
Thermal Diode Anode May be used by an external temperature sensor to measure the die temperature.
Thermal Diode Cathode May be used by an external temperature sensor to measure the die
temperature.
SYS_XTAL
TMR_ACIn
TMR_ACLKn
TMR_CLK
TMR_TMRn
TWI_SCL
Output
Input
Input
Input
I/O
Crystal Output Drives an external crystal. Must be left unconnected if an external clock is driving CLKIN.
Alternate Capture Input n Provides an additional input for WIDCAP, WATCHDOG, and PININT modes.
Alternate Clock n Provides an additional time base for use by an individual timer.
Clock Provides an additional global time base for use by all the GP timers.
Timer n The main input/output signal for each timer.
I/O
Serial Clock Clock output when master, clock input when slave.
Serial Data Receives or transmits data.
TWI_SDA
UART_CTS
UART_RTS
UART_RX
I/O
Input
Output
Input
Clear to Send Flow control signal.
Request to Send Flow control signal.
Receive Receive input. Typically connects to a transceiver that meets the electrical requirements of the
device being communicated with.
UART_TX
Output
Input
Transmit Transmit output. Typically connects to a transceiver that meets the electrical requirements of
the device being communicated with.
USB_CLKIN
Clock/Crystal Input This clock input is multiplied by a PLL to form the USB clock. See Universal Serial
Bus (USB) On-The-Go—Receive and Transmit Timing for frequency/tolerance information.
USB_DM
USB_DP
USB_ID
I/O
Data – Bidirectional differential data line.
Data + Bidirectional differential data line.
I/O
Input
OTG ID Senses whether the controller is a host or device. This signal is pulled low when an A-type plug
is sensed (signifying that the USB controller is the A device), but the input is high when a B-type plug is
sensed (signifying that the USB controller is the B device).
USB_VBC
Output
I/O
VBUS Control Controls an external voltage source to supply VBUS when in host mode. May be
configured as open drain. Polarity is configurable as well.
USB_VBUS
Bus Voltage Connects to bus voltage in host and device modes.
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ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA SIGNAL DESCRIPTIONS
The processors' pin definitions are shown in the table. The col-
umns in this table provide the following information:
• Port: The General-Purpose I/O Port column in the table
shows whether or not the signal is multiplexed with other
signals on a general-purpose I/O port pin.
• Signal Name: The Signal Name column in the table
includes the Signal Name for every pin.
• Pin Name: The Pin Name column in the table identifies the
name of the package pin (at power-on reset) on which the
signal is located (if a single function pin) or is multiplexed
(if a general-purpose I/O pin).
• Description: The Description column in the table provides
a verbose (descriptive) name for the signal.
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions
Signal Name
ACM0_A0
ACM0_A1
ACM0_A2
ACM0_A3
ACM0_A4
ACM0_CLK
ACM0_FS
Description
Port
Pin Name
PF_14
ACM0 Address 0
F
ACM0 Address 1
F
PF_15
ACM0 Address 2
F
PF_12
ACM0 Address 3
F
PF_13
ACM0 Address 4
F
PF_10
ACM0 Clock
E
PE_04
ACM0 Frame Sync
ACM0 External Trigger 0
ACM0 External Trigger 1
CAN0 Receive
E
PE_03
ACM0_T0
E
PE_08
ACM0_T1
G
PG_05
CAN0_RX
G
PG_04
CAN0_TX
CAN0 Transmit
G
PG_01
CNT0_DG
CNT0_UD
CNT0_ZM
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
CNT0 Count Down and Gate
CNT0 Count Up and Direction
CNT0 Count Zero Marker
DMC Address 0
G
PG_12
G
PG_11
G
PG_07
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
DMC0_CKE
DMC0_CK
DMC0_CS0
DMC Address 1
DMC Address 2
DMC Address 3
DMC Address 4
DMC Address 5
DMC Address 6
DMC Address 7
DMC Address 8
DMC Address 9
DMC Address 10
DMC Address 11
DMC Address 12
DMC Address 13
DMC Bank Address Input 0
DMC Bank Address Input 1
DMC Bank Address Input 2
DMC Column Address Strobe
DMC Clock
DMC Clock Enable
DMC Clock (complement)
DMC Chip Select 0
Rev. 0
| Page 23 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
Description
Port
Pin Name
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
PC_05
DMC Data 0
Not Muxed
DMC Data 1
Not Muxed
DMC Data 2
Not Muxed
DMC Data 3
Not Muxed
DMC Data 4
Not Muxed
DMC Data 5
Not Muxed
DMC Data 6
Not Muxed
DMC Data 7
Not Muxed
DMC Data 8
Not Muxed
DMC Data 9
Not Muxed
DMC Data 10
Not Muxed
DMC Data 11
Not Muxed
DMC Data 12
Not Muxed
DMC Data 13
Not Muxed
DMC Data 14
Not Muxed
DMC Data 15
Not Muxed
DMC Data Mask for Lower Byte
DMC Data Strobe for Lower Byte
DMC Data Strobe for Lower Byte (complement)
DMC On-die Termination
DMC Row Address Strobe
DMC Data Mask for Upper Byte
DMC Data Strobe for Upper Byte
DMC Data Strobe for Upper Byte (complement)
DMC Write Enable
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
DMC0_WE
Not Muxed
Not Muxed
Not Muxed
Not Muxed
ETH0_CRS
EMAC0 Carrier Sense/RMII Receive Data Valid
EMAC0 Management Channel Clock
EMAC0 Management Channel Serial Data
EMAC0 PTP Pulse-Per-Second Output
EMAC0 Reference Clock
EMAC0 Receive Data 0
EMAC0 Receive Data 1
EMAC0 Transmit Data 0
EMAC0 Transmit Data 1
EMAC0 Transmit Enable
EMAC1 Carrier Sense/RMII Receive Data Valid
EMAC1 Management Channel Clock
EMAC1 Management Channel Serial Data
EMAC1 PTP Pulse-Per-Second Output
EMAC1 Reference Clock
EMAC1 Receive Data 0
EMAC1 Receive Data 1
EMAC1 Transmit Data 0
EMAC1 Transmit Data 1
EMAC1 Transmit Enable
EMAC0/EMAC1 PTP Auxiliary Trigger Input
C
C
C
B
B
C
C
C
C
B
E
ETH0_MDC
PC_06
ETH0_MDIO
ETH0_PTPPPS
ETH0_REFCLK
ETH0_RXD0
ETH0_RXD1
ETH0_TXD0
ETH0_TXD1
ETH0_TXEN
ETH1_CRS
PC_07
PB_15
PB_14
PC_00
PC_01
PC_02
PC_03
PB_13
PE_13
ETH1_MDC
E
PE_10
ETH1_MDIO
ETH1_PTPPPS
ETH1_REFCLK
ETH1_RXD0
ETH1_RXD1
ETH1_TXD0
ETH1_TXD1
ETH1_TXEN
ETH_PTPAUXIN
E
PE_11
C
G
G
E
PC_09
PG_06
PG_00
PE_15
G
G
G
C
PG_03
PG_02
PG_05
PC_11
Rev. 0
| Page 24 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
ETH_PTPCLKIN
GND
Description
EMAC0/EMAC1 PTP Clock Input
Ground
Port
Pin Name
PC_13
GND
C
Not Muxed
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
LP0_ACK
LP0_CLK
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_ACK
LP1_CLK
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
LP2_ACK
LP2_CLK
LP2_D0
LP2_D1
LP2_D2
LP2_D3
LP2_D4
LP2_D5
LP2_D6
LP2_D7
LP3_ACK
LP3_CLK
LP3_D0
LP3_D1
LP3_D2
LP3_D3
LP3_D4
LP3_D5
Emulation Output
JTAG Clock
Not Muxed
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PB_01
PB_00
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PB_02
PB_03
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PE_08
PE_09
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PE_07
PE_06
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
Not Muxed
JTAG Serial Data Input
JTAG Serial Data Output
JTAG Mode Select
JTAG Reset
Not Muxed
Not Muxed
Not Muxed
Not Muxed
LP0 Acknowledge
LP0 Clock
B
B
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
E
LP0 Data 0
LP0 Data 1
LP0 Data 2
LP0 Data 3
LP0 Data 4
LP0 Data 5
LP0 Data 6
LP0 Data 7
LP1 Acknowledge
LP1 Clock
LP1 Data 0
LP1 Data 1
LP1 Data 2
LP1 Data 3
LP1 Data 4
LP1 Data 5
LP1 Data 6
LP1 Data 7
LP2 Acknowledge
LP2 Clock
E
LP2 Data 0
F
LP2 Data 1
F
LP2 Data 2
F
LP2 Data 3
F
LP2 Data 4
F
LP2 Data 5
F
LP2 Data 6
F
LP2 Data 7
F
LP3 Acknowledge
LP3 Clock
E
E
LP3 Data 0
F
LP3 Data 1
F
LP3 Data 2
F
LP3 Data 3
F
LP3 Data 4
F
LP3 Data 5
F
Rev. 0
| Page 25 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
LP3_D6
Description
Port
F
Pin Name
PF_14
LP3 Data 6
LP3_D7
LP3 Data 7
F
PF_15
PA_00 – PA_15
PB_00 – PB_15
PC_00 – PC_15
PD_00 – PD_15
PE_00 – PE_15
PF_00 – PF_15
PG_00 – PG_15
PPI0_CLK
PORTA Position 00 through PORTA Position 15
PORTB Position 00 through PORTB Position 15
PORTC Position 00 through PORTC Position 15
PORTD Position 00 through PORTD Position 15
PORTE Position 00 through PORTE Position 15
PORTF Position 00 through PORTF Position 15
PORTG Position 00 through PORTG Position 15
EPPI0 Clock
A
B
C
D
E
PA_00 – PA_15
PB_00 – PB_15
PC_00 – PC_15
PD_00 – PD_15
PE_00 – PE_15
PF_00 – PF_15
PG_00 – PG_15
PE_09
F
G
E
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
PPI0_D16
PPI0_D17
PPI0_D18
PPI0_D19
PPI0_D20
PPI0_D21
PPI0_D22
PPI0_D23
PPI0_FS1
EPPI0 Data 0
F
PF_00
EPPI0 Data 1
F
PF_01
EPPI0 Data 2
F
PF_02
EPPI0 Data 3
F
PF_03
EPPI0 Data 4
F
PF_04
EPPI0 Data 5
F
PF_05
EPPI0 Data 6
F
PF_06
EPPI0 Data 7
F
PF_07
EPPI0 Data 8
F
PF_08
EPPI0 Data 9
F
PF_09
EPPI0 Data 10
F
PF_10
EPPI0 Data 11
F
PF_11
EPPI0 Data 12
F
PF_12
EPPI0 Data 13
F
PF_13
EPPI0 Data 14
F
PF_14
EPPI0 Data 15
F
PF_15
EPPI0 Data 16
E
PE_03
EPPI0 Data 17
E
PE_04
EPPI0 Data 18
E
PE_00
EPPI0 Data 19
E
PE_01
EPPI0 Data 20
D
D
E
PD_12
EPPI0 Data 21
PD_15
EPPI0 Data 22
PE_02
EPPI0 Data 23
E
PE_05
EPPI0 Frame Sync 1 (HSYNC)
EPPI0 Frame Sync 2 (VSYNC)
EPPI0 Frame Sync 3 (FIELD)
EPPI1 Clock
E
PE_08
PPI0_FS2
E
PE_07
PPI0_FS3
E
PE_06
PPI1_CLK
B
C
C
C
C
C
C
C
C
PB_14
PPI1_D00
PPI1_D01
PPI1_D02
PPI1_D03
PPI1_D04
PPI1_D05
PPI1_D06
PPI1_D07
EPPI1 Data 0
PC_00
EPPI1 Data 1
PC_01
EPPI1 Data 2
PC_02
EPPI1 Data 3
PC_03
EPPI1 Data 4
PC_04
EPPI1 Data 5
PC_05
EPPI1 Data 6
PC_06
EPPI1 Data 7
PC_07
Rev. 0
| Page 26 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PPI1_D08
PPI1_D09
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
PPI1_D16
PPI1_D17
PPI1_FS1
PPI1_FS2
PPI1_FS3
PPI2_CLK
PPI2_D00
PPI2_D01
PPI2_D02
PPI2_D03
PPI2_D04
PPI2_D05
PPI2_D06
PPI2_D07
PPI2_D08
PPI2_D09
PPI2_D10
PPI2_D11
PPI2_D12
PPI2_D13
PPI2_D14
PPI2_D15
PPI2_D16
PPI2_D17
PPI2_FS1
PPI2_FS2
PPI2_FS3
PWM0_AH
PWM0_AL
PWM0_BH
PWM0_BL
PWM0_CH
PWM0_CL
PWM0_DH
PWM0_DL
PWM0_SYNC
PWM0_TRIP0
PWM0_TRIP1
Description
Port
C
C
C
C
C
C
C
C
D
D
B
Pin Name
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PB_13
PD_06
PB_15
PB_00
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_07
PB_08
PB_01
PB_02
PB_03
PF_01
PF_00
PF_03
PF_02
PF_05
PF_04
PF_07
PF_06
PE_08
PE_09
PF_11
EPPI1 Data 8
EPPI1 Data 9
EPPI1 Data 10
EPPI1 Data 11
EPPI1 Data 12
EPPI1 Data 13
EPPI1 Data 14
EPPI1 Data 15
EPPI1 Data 16
EPPI1 Data 17
EPPI1 Frame Sync 1 (HSYNC)
EPPI1 Frame Sync 2 (VSYNC)
EPPI1 Frame Sync 3 (FIELD)
EPPI2 Clock
D
B
B
EPPI2 Data 0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
EPPI2 Data 1
EPPI2 Data 2
EPPI2 Data 3
EPPI2 Data 4
EPPI2 Data 5
EPPI2 Data 6
EPPI2 Data 7
EPPI2 Data 8
EPPI2 Data 9
EPPI2 Data 10
EPPI2 Data 11
EPPI2 Data 12
EPPI2 Data 13
EPPI2 Data 14
EPPI2 Data 15
EPPI2 Data 16
EPPI2 Data 17
B
EPPI2 Frame Sync 1 (HSYNC)
EPPI2 Frame Sync 2 (VSYNC)
EPPI2 Frame Sync 3 (FIELD)
PWM0 Channel A High Side
PWM0 Channel A Low Side
PWM0 Channel B High Side
PWM0 Channel B Low Side
PWM0 Channel C High Side
PWM0 Channel C Low Side
PWM0 Channel D High Side
PWM0 Channel D Low Side
PWM0 Sync
B
B
B
F
F
F
F
F
F
F
F
E
PWM0 Shutdown Input 0
PWM0 Shutdown Input 1
E
F
Rev. 0
| Page 27 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
PWM1_AH
PWM1_AL
PWM1_BH
PWM1_BL
PWM1_CH
PWM1_CL
PWM1_DH
PWM1_DL
PWM1_SYNC
PWM1_TRIP0
PWM1_TRIP1
RSI0_CLK
Description
Port
Pin Name
PG_03
PG_02
PG_00
PE_15
PE_13
PE_12
PE_11
PE_10
PG_05
PG_06
PG_08
PG_06
PG_05
PG_03
PG_02
PG_00
PE_15
PE_13
PE_12
PE_10
PE_11
SMC0_A01
SMC0_A02
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PB_02
PA_10
PA_11
PB_03
PA_12
PA_13
PA_14
PA_15
PB_06
PB_07
PB_08
PB_10
PB_11
PWM1 Channel A High Side
PWM1 Channel A Low Side
PWM1 Channel B High Side
PWM1 Channel B Low Side
PWM1 Channel C High Side
PWM1 Channel C Low Side
PWM1 Channel D High Side
PWM1 Channel D Low Side
PWM1 Sync
G
G
G
E
E
E
E
E
G
PWM1 Shutdown Input 0
PWM1 Shutdown Input 1
RSI0 Clock
G
G
G
RSI0_CMD
RSI0_D0
RSI0 Command
G
RSI0 Data 0
G
RSI0_D1
RSI0 Data 1
G
RSI0_D2
RSI0 Data 2
G
RSI0_D3
RSI0 Data 3
E
RSI0_D4
RSI0 Data 4
E
RSI0_D5
RSI0 Data 5
E
RSI0_D6
RSI0 Data 6
E
RSI0_D7
RSI0 Data 7
E
SMC0_A01
SMC0_A02
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A13
SMC0_A14
SMC0_A15
SMC0_A16
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_A24
SMC0_A25
SMC0 Address 1
SMC0 Address 2
SMC0 Address 3
SMC0 Address 4
SMC0 Address 5
SMC0 Address 6
SMC0 Address 7
SMC0 Address 8
SMC0 Address 9
SMC0 Address 10
SMC0 Address 11
SMC0 Address 12
SMC0 Address 13
SMC0 Address 14
SMC0 Address 15
SMC0 Address 16
SMC0 Address 17
SMC0 Address 18
SMC0 Address 19
SMC0 Address 20
SMC0 Address 21
SMC0 Address 22
SMC0 Address 23
SMC0 Address 24
SMC0 Address 25
Not Muxed
Not Muxed
A
A
A
A
A
A
A
A
A
A
B
A
A
B
A
A
A
A
B
B
B
B
B
Rev. 0
| Page 28 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SMC0_ABE0
SMC0_ABE1
SMC0_AMS0
SMC0_AMS1
SMC0_AMS2
SMC0_AMS3
SMC0_AOE
SMC0_ARDY
SMC0_ARE
SMC0_AWE
SMC0_BGH
SMC0_BG
Description
Port
Pin Name
PB_04
SMC0 Byte Enable 0
SMC0 Byte Enable 1
SMC0 Memory Select 0
SMC0 Memory Select 1
SMC0 Memory Select 2
SMC0 Memory Select 3
SMC0 Output Enable
SMC0 Asynchronous Ready
SMC0 Read Enable
SMC0 Write Enable
SMC0 Bus Grant Hang
SMC0 Bus Grant
B
B
PB_05
Not Muxed
SMC0_AMS0
PB_01
B
B
PB_04
B
PB_05
Not Muxed
SMC0_AOE_NORDV
SMC0_ARDY_NORWT
SMC0_ARE
SMC0_AWE
PB_09
Not Muxed
Not Muxed
Not Muxed
B
B
PB_12
SMC0_BR
SMC0 Bus Request
SMC0 Data 0
Not Muxed
SMC0_BR
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
PB_00
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SMC0_NORCLK
SMC0_NORDV
SMC0_NORWT
SPI0_CLK
Not Muxed
SMC0 Data 1
Not Muxed
SMC0 Data 2
Not Muxed
SMC0 Data 3
Not Muxed
SMC0 Data 4
Not Muxed
SMC0 Data 5
Not Muxed
SMC0 Data 6
Not Muxed
SMC0 Data 7
Not Muxed
SMC0 Data 8
Not Muxed
SMC0 Data 9
Not Muxed
SMC0 Data 10
Not Muxed
SMC0 Data 11
Not Muxed
SMC0 Data 12
Not Muxed
SMC0 Data 13
Not Muxed
SMC0 Data 14
Not Muxed
SMC0 Data 15
Not Muxed
SMC0 NOR Clock
SMC0 NOR Data Valid
SMC0 NOR Wait
B
Not Muxed
SMC0_AOE_NORDV
SMC0_ARDY_NORWT
PD_04
Not Muxed
SPI0 Clock
D
D
D
D
D
D
D
D
D
C
SPI0_D2
SPI0 Data 2
PD_00
SPI0_D3
SPI0 Data 3
PD_01
SPI0_MISO
SPI0_MOSI
SPI0_RDY
SPI0 Master In, Slave Out
SPI0 Master Out, Slave In
SPI0 Ready
PD_02
PD_03
PD_10
SPI0_SEL1
SPI0_SEL2
SPI0_SEL3
SPI0_SEL4
SPI0_SEL5
SPI0_SEL6
SPI0_SEL7
SPI0_SS
SPI0 Slave Select Output 1
SPI0 Slave Select Output 2
SPI0 Slave Select Output 3
SPI0 Slave Select Output 4
SPI0 Slave Select Output 5
SPI0 Slave Select Output 6
SPI0 Slave Select Output 7
SPI0 Slave Select Input
PD_11
PD_01
PD_00
PC_15
D
C
PD_09
PC_13
C
PC_12
D
PD_11
Rev. 0
| Page 29 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SPI1_CLK
Description
Port
Pin Name
PD_05
PE_01
PE_00
PD_14
PD_13
PE_02
PD_12
PD_15
PD_10
PD_09
PF_08
SPI1 Clock
D
SPI1_D2
SPI1 Data 2
E
SPI1_D3
SPI1 Data 3
E
SPI1_MISO
SPI1_MOSI
SPI1_RDY
SPI1 Master In, Slave Out
SPI1 Master Out, Slave In
SPI1 Ready
D
D
E
SPI1_SEL1
SPI1_SEL2
SPI1_SEL3
SPI1_SEL4
SPI1_SEL5
SPI1_SEL6
SPI1_SEL7
SPI1_SS
SPI1 Slave Select Output 1
SPI1 Slave Select Output 2
SPI1 Slave Select Output 3
SPI1 Slave Select Output 4
SPI1 Slave Select Output 5
SPI1 Slave Select Output 6
SPI1 Slave Select Output 7
SPI1 Slave Select Input
D
D
D
D
F
F
PF_09
C
PC_14
PD_12
PB_05
PB_09
PB_12
PB_04
PB_06
PB_08
PB_11
PB_10
PB_07
PB_12
PE_02
PD_15
PD_12
PE_05
PE_06
PE_04
PE_01
PE_00
PE_03
PE_07
PG_04
PG_09
PG_08
PG_01
PE_14
PG_10
PG_12
PG_11
PG_07
PG_06
SYS_BMODE0
SYS_BMODE1
D
SPT0_ACLK
SPT0_AD0
SPT0_AD1
SPT0_AFS
SPT0_ATDV
SPT0_BCLK
SPT0_BD0
SPT0_BD1
SPT0_BFS
SPT0_BTDV
SPT1_ACLK
SPT1_AD0
SPT1_AD1
SPT1_AFS
SPT1_ATDV
SPT1_BCLK
SPT1_BD0
SPT1_BD1
SPT1_BFS
SPT1_BTDV
SPT2_ACLK
SPT2_AD0
SPT2_AD1
SPT2_AFS
SPT2_ATDV
SPT2_BCLK
SPT2_BD0
SPT2_BD1
SPT2_BFS
SPT2_BTDV
SYS_BMODE0
SYS_BMODE1
SPORT0 Channel A Clock
SPORT0 Channel A Data 0
SPORT0 Channel A Data 1
SPORT0 Channel A Frame Sync
SPORT0 Channel A Transmit Data Valid
SPORT0 Channel B Clock
SPORT0 Channel B Data 0
SPORT0 Channel B Data 1
SPORT0 Channel B Frame Sync
SPORT0 Channel B Transmit Data Valid
SPORT1 Channel A Clock
SPORT1 Channel A Data 0
SPORT1 Channel A Data 1
SPORT1 Channel A Frame Sync
SPORT1 Channel A Transmit Data Valid
SPORT1 Channel B Clock
SPORT1 Channel B Data 0
SPORT1 Channel B Data 1
SPORT1 Channel B Frame Sync
SPORT1 Channel B Transmit Data Valid
SPORT2 Channel A Clock
SPORT2 Channel A Data 0
SPORT2 Channel A Data 1
SPORT2 Channel A Frame Sync
SPORT2 Channel A Transmit Data Valid
SPORT2 Channel B Clock
SPORT2 Channel B Data 0
SPORT2 Channel B Data 1
SPORT2 Channel B Frame Sync
SPORT2 Channel B Transmit Data Valid
Boot Mode Control 0
B
B
B
B
B
B
B
B
B
B
E
D
D
E
E
E
E
E
E
E
G
G
G
G
E
G
G
G
G
G
Not Muxed
Not Muxed
Boot Mode Control 1
Rev. 0
| Page 30 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_HWRST
SYS_IDLE0
SYS_IDLE1
SYS_NMI
Description
Port
Pin Name
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_HWRST
PG_15
Boot Mode Control 2
Clock/Crystal Input
Not Muxed
Not Muxed
Processor Clock Output
External Wake Control
Fault Output
Not Muxed
Not Muxed
Not Muxed
Complementary Fault Output
Processor Hardware Reset Control
Core 0 Idle Indicator
Not Muxed
Not Muxed
G
Core 1 Idle Indicator
G
PG_14
Non-maskable Interrupt
Power Good Indicator
Reset Output
Not Muxed
SYS_NMI_RESOUT
SYS_PWRGD
SYS_NMI_RESOUT
PG_15
SYS_PWRGD
SYS_RESOUT
SYS_SLEEP
SYS_TDA
Not Muxed
Not Muxed
Processor Sleep Indicator
Thermal Diode Anode
Thermal Diode Cathode
Crystal Output
G
Not Muxed
SYS_TDA
SYS_TDK
SYS_XTAL
PD_08
SYS_TDK
Not Muxed
SYS_XTAL
Not Muxed
TM0_ACI0
TM0_ACI1
TM0_ACI2
TM0_ACI3
TM0_ACI4
TM0_ACI5
TM0_ACI6
TM0_ACLK0
TM0_ACLK1
TM0_ACLK2
TM0_ACLK3
TM0_ACLK4
TM0_ACLK5
TM0_ACLK6
TM0_ACLK7
TM0_CLK
TIMER0 Alternate Capture Input 0
TIMER0 Alternate Capture Input 1
TIMER0 Alternate Capture Input 2
TIMER0 Alternate Capture Input 3
TIMER0 Alternate Capture Input 4
TIMER0 Alternate Capture Input 5
TIMER0 Alternate Capture Input 6
TIMER0 Alternate Clock 0
TIMER0 Alternate Clock 1
TIMER0 Alternate Clock 2
TIMER0 Alternate Clock 3
TIMER0 Alternate Clock 4
TIMER0 Alternate Clock 5
TIMER0 Alternate Clock 6
TIMER0 Alternate Clock 7
TIMER0 Clock
D
G
PG_14
G
PG_04
D
PD_07
G
PG_15
D
PD_06
B
PB_13
B
PB_10
B
PB_12
B
PB_09
B
PB_11
B
PB_06
D
PD_13
D
PD_14
D
PD_05
G
PG_13
TM0_TMR0
TM0_TMR1
TM0_TMR2
TM0_TMR3
TM0_TMR4
TM0_TMR5
TM0_TMR6
TM0_TMR7
TWI0_SCL
TIMER0 Timer 0
E
PE_14
TIMER0 Timer 1
G
PG_04
TIMER0 Timer 2
G
PG_01
TIMER0 Timer 3
G
PG_08
TIMER0 Timer 4
G
PG_09
TIMER0 Timer 5
G
PG_07
TIMER0 Timer 6
G
PG_11
TIMER0 Timer 7
G
PG_12
TWI0 Serial Clock
Not Muxed
Not Muxed
Not Muxed
Not Muxed
D
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
PD_10
TWI0_SDA
TWI1_SCL
TWI0 Serial Data
TWI1 Serial Clock
TWI1_SDA
UART0_CTS
UART0_RTS
TWI1 Serial Data
UART0 Clear to Send
UART0 Request to Send
D
PD_09
Rev. 0
| Page 31 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 7. ADSP-BF60x 349-Ball CSP_BGA Signal Descriptions (Continued)
Signal Name
UART0_RX
UART0_TX
UART1_CTS
UART1_RTS
UART1_RX
UART1_TX
USB0_CLKIN
USB0_DM
USB0_DP
Description
Port
Pin Name
PD_08
UART0 Receive
UART0 Transmit
UART1 Clear to Send
UART1 Request to Send
UART1 Receive
UART1 Transmit
USB0 Clock/Crystal Input
USB0 Data –
D
D
PD_07
G
PG_13
G
PG_10
G
PG_14
G
PG_15
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
Not Muxed
USB0_CLKIN
USB0_DM
USB0_DP
USB0_ID
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_EXT
VDD_INT
VDD_TD
VDD_USB
VREF_DMC
USB0 Data +
USB0_ID
USB0 OTG ID
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_EXT
USB0 VBUS Control
USB0 Bus Voltage
VDD for DMC
External VDD
VDD_INT
Internal VDD
VDD_TD
VDD for Thermal Diode
VDD for USB
VDD_USB
VREF_DMC
VREF for DMC
Rev. 0
| Page 32 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
GP I/O MULTIPLEXING FOR 349-BALL CSP_BGA
Table 8 through Table 14 identifies the pin functions that are
multiplexed on the general-purpose I/O pins of the 349-ball
CSP_BGA package.
Table 8. Signal Multiplexing for Port A
Multiplexed Function
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
Signal Name
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
SMC0_A03
SMC0_A04
SMC0_A05
SMC0_A06
SMC0_A07
SMC0_A08
SMC0_A09
SMC0_A10
SMC0_A11
SMC0_A12
SMC0_A14
SMC0_A15
SMC0_A17
SMC0_A18
SMC0_A19
SMC0_A20
PPI2_D00
PPI2_D01
PPI2_D02
PPI2_D03
PPI2_D04
PPI2_D05
PPI2_D06
PPI2_D07
PPI2_D08
PPI2_D09
PPI2_D10
PPI2_D11
PPI2_D12
PPI2_D13
PPI2_D14
PPI2_D15
LP0_D0
LP0_D1
LP0_D2
LP0_D3
LP0_D4
LP0_D5
LP0_D6
LP0_D7
LP1_D0
LP1_D1
LP1_D2
LP1_D3
LP1_D4
LP1_D5
LP1_D6
LP1_D7
Table 9. Signal Multiplexing for Port B
Multiplexed Function
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
Signal Name
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
SMC0_NORCLK
SMC0_AMS1
SMC0_A13
SMC0_A16
SMC0_AMS2
SMC0_AMS3
SMC0_A21
SMC0_A22
SMC0_A23
SMC0_BGH
SMC0_A24
SMC0_A25
SMC0_BG
PPI2_CLK
PPI2_FS1
LP0_CLK
LP0_ACK
LP1_ACK
LP1_CLK
SPT0_AFS
SPT0_ACLK
PPI2_FS2
PPI2_FS3
SMC0_ABE0
SMC0_ABE1
SPT0_ATDV
PPI2_D16
PPI2_D17
TM0_ACLK4
SPT0_BFS
SPT0_BCLK
SPT0_AD0
SPT0_BD1
SPT0_BD0
SPT0_AD1
TM0_ACLK2
TM0_ACLK0
TM0_ACLK3
TM0_ACLK1
TM0_ACI6
SPT0_BTDV
PPI1_FS1
PPI1_CLK
PPI1_FS3
ETH0_TXEN
ETH0_REFCLK
ETH0_PTPPPS
Rev. 0
| Page 33 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 10. Signal Multiplexing for Port C
Multiplexed Function
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
Signal Name
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
ETH0_RXD0
ETH0_RXD1
ETH0_TXD0
ETH0_TXD1
PPI1_D00
PPI1_D01
PPI1_D02
PPI1_D03
PPI1_D04
PPI1_D05
PPI1_D06
PPI1_D07
PPI1_D08
PPI1_D09
PPI1_D10
PPI1_D11
PPI1_D12
PPI1_D13
PPI1_D14
PPI1_D15
ETH0_CRS
ETH0_MDC
ETH0_MDIO
ETH1_PTPPPS
ETH_PTPAUXIN
ETH_PTPCLKIN
SPI0_SEL7
SPI0_SEL6
SPI1_SEL7
SPI0_SEL4
Table 11. Signal Multiplexing for Port D
Multiplexed Function
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
Signal Name
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
SPI0_D2
PPI1_D16
PPI1_D17
SPI0_SEL3
SPI0_SEL2
SPI0_D3
SPI0_MISO
SPI0_MOSI
SPI0_CLK
SPI1_CLK
TM0_ACLK7
TM0_ACI5
TM0_ACI3
TM0_ACI0
PPI1_FS2
UART0_TX
UART0_RX
UART0_RTS
UART0_CTS
SPI0_SEL5
SPI0_RDY
SPI0_SEL1
SPI1_SEL1
SPI1_MOSI
SPI1_MISO
SPI1_SEL2
SPI1_SEL4
SPI1_SEL3
SPI0_SS
PPI0_D20
PPI0_D21
SPT1_AD1
SPT1_AD0
SPI1_SS
TM0_ACLK5
TM0_ACLK6
Rev. 0
| Page 34 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 12. Signal Multiplexing for Port E
Multiplexed Function
Signal Name
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2
Input Tap
PE_00
PE_01
PE_02
PE_03
PE_04
PE_05
PE_06
PE_07
PE_08
PE_09
PE_10
PE_11
PE_12
PE_13
PE_14
PE_15
SPI1_D3
SPI1_D2
SPI1_RDY
PPI0_D18
PPI0_D19
PPI0_D22
PPI0_D16
PPI0_D17
PPI0_D23
PPI0_FS3
PPI0_FS2
PPI0_FS1
PPI0_CLK
PWM1_DL
PWM1_DH
PWM1_CL
PWM1_CH
SPT2_ATDV
PWM1_BL
SPT1_BD1
SPT1_BD0
SPT1_ACLK
ACM0_FS/SPT1_BFS
ACM0_CLK/SPT1_BCLK
SPT1_AFS
LP3_CLK
SPT1_ATDV
SPT1_BTDV
PWM0_SYNC
LP3_ACK
LP2_ACK
ACM0_T0
LP2_CLK
PWM0_TRIP0
ETH1_MDC
ETH1_MDIO
RSI0_D6
RSI0_D7
RSI0_D5
ETH1_CRS
RSI0_D4
TM0_TMR0
RSI0_D3
ETH1_RXD1
Table 13. Signal Multiplexing for Port F
Multiplexed Function
Signal Name
PF_00
PF_01
PF_02
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
PWM0_AL
PWM0_AH
PWM0_BL
PWM0_BH
PWM0_CL
PWM0_CH
PWM0_DL
PWM0_DH
SPI1_SEL5
SPI1_SEL6
ACM0_A4
PPI0_D00
PPI0_D01
PPI0_D02
PPI0_D03
PPI0_D04
PPI0_D05
PPI0_D06
PPI0_D07
PPI0_D08
PPI0_D09
PPI0_D10
PPI0_D11
PPI0_D12
PPI0_D13
PPI0_D14
PPI0_D15
LP2_D0
LP2_D1
LP2_D2
LP2_D3
LP2_D4
LP2_D5
LP2_D6
LP2_D7
LP3_D0
LP3_D1
LP3_D2
LP3_D3
LP3_D4
LP3_D5
LP3_D6
LP3_D7
PWM0_TRIP1
ACM0_A2
ACM0_A3
ACM0_A0
ACM0_A1
Rev. 0
| Page 35 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 14. Signal Multiplexing for Port G
Multiplexed Function
Signal Name
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
PG_06
PG_07
PG_08
PG_09
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Input Tap
ETH1_RXD0
SPT2_AFS
PWM1_BH
TM0_TMR2
PWM1_AL
PWM1_AH
TM0_TMR1
RSI0_CMD
RSI0_CLK
RSI0_D2
CAN0_TX
RSI0_D1
ETH1_TXD1
ETH1_TXD0
SPT2_ACLK
ETH1_TXEN
ETH1_REFCLK
SPT2_BFS
RSI0_D0
CAN0_RX
PWM1_SYNC
SPT2_BTDV
TM0_ACI2
ACM0_T1
PWM1_TRIP0
CNT0_ZM
TM0_TMR5
TM0_TMR3
TM0_TMR4
SPT2_BCLK
TM0_TMR6
TM0_TMR7
SPT2_AD1
SPT2_AD0
UART1_RTS
SPT2_BD1
SPT2_BD0
UART1_CTS
UART1_RX
UART1_TX
PWM1_TRIP1
CNT0_UD
CNT0_DG
TM0_CLK
TM0_ACI1
TM0_ACI4
SYS_IDLE1
SYS_IDLE0
SYS_SLEEP
Rev. 0
| Page 36 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x DESIGNER QUICK REFERENCE
The table provides a quick reference summary of pin related
information for circuit board design. The columns in this table
provide the following information:
• Reset Drive: The Reset Drive column in the table specifies
the active drive on the signal when the processor is in the
reset state.
• Signal Name: The Signal Name column in the table
includes the Signal Name for every pin.
• Hiber Term: The Hibernate Termination column in the
table specifies the termination present when the processor
is in the hibernate state. The abbreviations used in this col-
umn are wk (Weak Keeper, weakly retains previous value
driven on the pin), pu (Pull-up resistor), or pd (Pull-down
resistor).
• Type: The Pin Type column in the table identifies the I/O
type or supply type of the pin. The abbreviations used in
this column are na (None), I/O (Digital input and/or out-
put), a (Analog), s (Supply), and g (Ground).
• Hiber Drive: The Hibernate Drive column in the table
specifies the active drive on the signal when the processor is
in the hibernate state.
• Driver Type: The Driver Type column in the table identi-
fies the driver type used by the pin. The driver types are
defined in Output Drive Currents on Page 99.
• Power Domain: The Power Domain column in the table
specifies the power supply domain in which the signal
resides.
• Int Term: The Internal Termination column in the table
specifies the termination present when the processor is not
in the reset or hibernate state. The abbreviations used in
this column are wk (Weak Keeper, weakly retains previous
value driven on the pin), pu (Pull-up resistor), or pd (Pull-
down resistor).
• Description and Notes: The Description and Notes column
in the table identifies any special requirements or charac-
teristics for the signal. If no special requirements are listed
the signal may be left unconnected if it is not used. Also, for
multiplexed general-purpose I/O pins, this column identi-
fies the functions available on the pin.
• Reset Term: The Reset Termination column in the table
specifies the termination present when the processor is in
the reset state. The abbreviations used in this column are
wk (Weak Keeper, weakly retains previous value driven on
the pin), pu (Pull-up resistor), or pd (Pull-down resistor).
Table 15. ADSP-BF60x Designer Quick Reference
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Address 0.
Notes: No notes.
B
B
B
B
B
B
B
B
B
B
none
none
none
none
none
none
none
none
none
none
Desc: DMC0 Address 1.
Notes: No notes.
Desc: DMC0 Address 2.
Notes: No notes.
Desc: DMC0 Address 3.
Notes: No notes.
Desc: DMC0 Address 4.
Notes: No notes.
Desc: DMC0 Address 5.
Notes: No notes.
Desc: DMC0 Address 6.
Notes: No notes.
Desc: DMC0 Address 7.
Notes: No notes.
Desc: DMC0 Address 8.
Notes: No notes.
Desc: DMC0 Address 9.
Notes: No notes.
Desc: DMC0 Address 10.
Notes: No notes.
Rev. 0
|
Page 37 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
L
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
L
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Address 11.
Notes: No notes.
B
B
B
B
B
B
C
C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
Desc: DMC0 Address 12.
Notes: No notes.
Desc: DMC0 Address 13.
Notes: No notes.
Desc: DMC0 Bank Address Input 0.
Notes: No notes.
Desc: DMC0 Bank Address Input 1.
Notes: No notes.
Desc: DMC0 Bank Address Input 2.
Notes: For LPDDR, leave unconnected.
Desc: DMC0 Column Address Strobe.
Notes: No notes.
Desc: DMC0 Clock.
Notes: No notes.
DMC0_CK
L
L
Desc: DMC0 Clock (complement).
Notes: No notes.
DMC0_CKE
DMC0_CS0
L
L
Desc: DMC0 Clock enable.
Notes: No notes.
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
Desc: DMC0 Chip Select 0.
Notes: No notes.
DMC0_DQ00 I/O
DMC0_DQ01 I/O
DMC0_DQ02 I/O
DMC0_DQ03 I/O
DMC0_DQ04 I/O
DMC0_DQ05 I/O
DMC0_DQ06 I/O
DMC0_DQ07 I/O
DMC0_DQ08 I/O
DMC0_DQ09 I/O
DMC0_DQ10 I/O
DMC0_DQ11 I/O
DMC0_DQ12 I/O
Desc: DMC0 Data 0.
Notes: No notes.
Desc: DMC0 Data 1.
Notes: No notes.
Desc: DMC0 Data 2.
Notes: No notes.
Desc: DMC0 Data 3.
Notes: No notes.
Desc: DMC0 Data 4.
Notes: No notes.
Desc: DMC0 Data 5.
Notes: No notes.
Desc: DMC0 Data 6.
Notes: No notes.
Desc: DMC0 Data 7.
Notes: No notes.
Desc: DMC0 Data 8.
Notes: No notes.
Desc: DMC0 Data 9.
Notes: No notes.
Desc: DMC0 Data 10.
Notes: No notes.
Desc: DMC0 Data 11.
Notes: No notes.
Desc: DMC0 Data 12.
Notes: No notes.
Rev. 0
|
Page 38 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
DMC0_DQ13 I/O
B
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 Data 13.
Notes: No notes.
DMC0_DQ14 I/O
DMC0_DQ15 I/O
B
B
B
C
none
none
none
none
Desc: DMC0 Data 14.
Notes: No notes.
Desc: DMC0 Data 15.
Notes: No notes.
DMC0_LDM
I/O
Desc: DMC0 Data Mask for Lower Byte.
Notes: No notes.
DMC0_LDQS I/O
DMC0_LDQS I/O
Desc: DMC0 Data Strobe for Lower Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Lower Byte
(complement).
Notes:ForsingleendedDDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_ODT
DMC0_RAS
DMC0_UDM
I/O
I/O
I/O
B
B
B
C
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
Desc: DMC0 On-die termination.
Notes: For LPDDR, leave unconnected.
Desc: DMC0 Row Address Strobe.
Notes: No notes.
Desc: DMC0 Data Mask for Upper Byte.
Notes: No notes.
DMC0_UDQS I/O
DMC0_UDQS I/O
Desc: DMC0 Data Strobe for Upper Byte.
Notes: For LPDDR, a 100k ohm pull-down
resistor is required.
C
none
none
none
none
none
VDD_DMC
Desc: DMC0 Data Strobe for Upper Byte
(complement).
Notes:ForsingleendedDDR2, connect to
VREF_DMC. For LPDDR, leave
unconnected.
DMC0_WE
GND
I/O
g
B
none
none
none
pd
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_DMC
na
Desc: DMC0 Write Enable.
Notes: No notes.
na
A
Desc: Ground.
Notes: No notes.
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
I/O
I/O
I/O
I/O
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: Emulation Output.
Notes: No notes.
na
na
A
Desc: JTG Clock.
Notes: Functional during reset.
Desc: JTG Serial Data Input.
Notes: Functional during reset.
pu
none
Desc: JTG Serial Data Output.
Notes: Functional during reset, three-
state when JTG_TRST is asserted.
JTG_TMS
JTG_TRST
I/O
I/O
na
na
pu
pd
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
Desc: JTG Mode Select.
Notes: Functional during reset.
Desc: JTG Reset.
Notes: Functional during reset.
Rev. 0
|
Page 39 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PA Position 0 | SMC0 Address 3 |
EPPI2 Data 0 | LP0 Data 0.
Notes: No notes.
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
Desc: PA Position 1 | SMC0 Address 4 |
EPPI2 Data 1 | LP0 Data 1.
Notes: No notes.
Desc: PA Position 2 | SMC0 Address 5 |
EPPI2 Data 2 | LP0 Data 2.
Notes: No notes.
Desc: PA Position 3 | SMC0 Address 6 |
EPPI2 Data 3 | LP0 Data 3.
Notes: No notes.
Desc: PA Position 4 | SMC0 Address 7 |
EPPI2 Data 4 | LP0 Data 4.
Notes: No notes.
Desc: PA Position 5 | SMC0 Address 8 |
EPPI2 Data 5 | LP0 Data 5.
Notes: No notes.
Desc: PA Position 6 | SMC0 Address 9 |
EPPI2 Data 6 | LP0 Data 6.
Notes: No notes.
Desc: PA Position 7 | SMC0 Address 10 |
EPPI2 Data 7 | LP0 Data 7.
Notes: No notes.
Desc: PA Position 8 | SMC0 Address 11 |
EPPI2 Data 8 | LP1 Data 0.
Notes: No notes.
Desc: PA Position 9 | SMC0 Address 12 |
EPPI2 Data 9 | LP1 Data 1.
Notes: No notes.
Desc: PA Position 10 | SMC0 Address 14 |
EPPI2 Data 10 | LP1 Data 2.
Notes: No notes.
Desc: PA Position 11 | SMC0 Address 15 |
EPPI2 Data 11 | LP1 Data 3.
Notes: No notes.
Desc: PA Position 12 | SMC0 Address 17 |
EPPI2 Data 12 | LP1 Data 4.
Notes: No notes.
Desc: PA Position 13 | SMC0 Address 18 |
EPPI2 Data 13 | LP1 Data 5.
Notes: No notes.
Desc: PA Position 14 | SMC0 Address 19 |
EPPI2 Data 14 | LP1 Data 6.
Notes: No notes.
Desc: PA Position 15 | SMC0 Address 20 |
EPPI2 Data 15 | LP1 Data 7.
Notes:Maybeusedtowaketheprocessor
from hibernate or deep sleep mode.
Rev. 0
|
Page 40 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PB_00
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PB Position 0 | SMC0 NOR Clock |
EPPI2 Clock | LP0 Clock.
Notes: No notes.
PB_01
I/O
A
A
wk
wk
wk
none
wk
none
VDD_EXT
Desc: PB Position 1| SMC0Memory Select
1 | EPPI2 Frame Sync 1 (HSYNC) | LP0
Acknowledge.
Notes: No notes.
PB_02
I/O
wk
none
wk
none
VDD_EXT
Desc: PB Position 2 | SMC0 Address 13 |
EPPI2 Frame Sync 2 (VSYNC) | LP1
Acknowledge.
Notes: No notes.
PB_03
PB_04
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PB Position 3 | SMC0 Address 16 |
EPPI2 Frame Sync 3 (FIELD) | LP1 Clock.
Notes: No notes.
Desc: PB Position 4| SMC0Memory Select
2 | SMC0 Byte Enable 0 | SPORT0 Channel
A Frame Sync.
Notes: No notes.
PB_05
PB_06
PB_07
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PB Position 5| SMC0Memory Select
3 | SMC0 Byte Enable 1 | SPORT0 Channel
A Clock.
Notes: No notes.
Desc: PB Position 6 | SMC0 Address 21 |
SPORT0 Channel A Transmit Data Valid |
TIMER0 Alternate Clock 4.
Notes: No notes.
Desc: PB Position 7 | SMC0 Address 22 |
EPPI2 Data 16 | SPORT0 Channel B Frame
Sync.
Notes: No notes.
PB_08
PB_09
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PB Position 8 | SMC0 Address 23 |
EPPI2 Data 17 | SPORT0 Channel B Clock.
Notes: No notes.
Desc:PBPosition9|SMC0BusGrantHang
| SPORT0 Channel A Data 0 | TIMER0
Alternate Clock 2.
Notes: No notes.
PB_10
PB_11
PB_12
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PB Position 10 | SMC0 Address 24 |
SPORT0 Channel B Data 1 | TIMER0
Alternate Clock 0.
Notes: No notes.
Desc: PB Position 11 | SMC0 Address 25 |
SPORT0 Channel B Data 0 | TIMER0
Alternate Clock 3.
Notes: No notes.
Desc: PB Position 12 | SMC0 Bus Grant |
SPORT0 Channel B Transmit Data Valid |
SPORT0 Channel A Data 1 | TIMER0
Alternate Clock 1.
Notes: No notes.
Rev. 0
|
Page 41 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PB_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PB Position 13 | EPPI1 Frame Sync 1
(HSYNC) | ETH0 Transmit Enable | TIMER0
Alternate Capture Input 6.
Notes: No notes.
PB_14
PB_15
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PB Position 14 | EPPI1 Clock | ETH0
Reference Clock.
Notes: No notes.
Desc: PB Position 15 | EPPI1 Frame Sync 3
(FIELD) | ETH0 PTP Pulse-Per-Second
Output.
Notes:Maybeusedtowaketheprocessor
from hibernate or deep sleep mode.
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
A
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PC Position 0 | EPPI1 Data 0 | ETH0
Receive Data 0.
Notes: No notes.
Desc: PC Position 1 | EPPI1 Data 1 | ETH0
Receive Data 1.
Notes: No notes.
Desc: PC Position 2 | EPPI1 Data 2 | ETH0
Transmit Data 0.
Notes: No notes.
Desc: PC Position 3 | EPPI1 Data 3 | ETH0
Transmit Data 1.
Notes: No notes.
Desc: PC Position 4 | EPPI1 Data 4 | ETH0
Receive Error.
Notes: No notes.
Desc: PC Position 5 | EPPI1 Data 5 | ETH0
Carrier Sense/RMII Receive Data Valid.
Notes: No notes.
Desc: PC Position 6 | EPPI1 Data 6 | ETH0
Management Channel Clock.
Notes: No notes.
Desc: PC Position 7 | EPPI1 Data 7 | ETH0
Management Channel Serial Data.
Notes: No notes.
PC_08
PC_09
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PC Position 8 | EPPI1 Data 8.
Notes: No notes.
Desc: PC Position 9 | EPPI1 Data 9 | ETH1
PTP Pulse-Per-Second Output.
Notes: No notes.
PC_10
PC_11
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PC Position 10 | EPPI1 Data 10.
Notes: No notes.
Desc: PC Position 11 | EPPI1 Data 11 | ETH
PTP Auxiliary Trigger Input.
Notes: No notes.
PC_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PC Position 12 | SPI0 Slave Select
Output b | EPPI1 Data 12.
Notes: No notes.
Rev. 0
|
Page 42 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PC_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PC Position 13 | SPI0 Slave Select
Output b | EPPI1 Data 13 | ETH PTP Clock
Input.
Notes: No notes.
PC_14
PC_15
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PC Position 14 | SPI1 Slave Select
Output b | EPPI1 Data 14.
Notes: No notes.
Desc: PC Position 15 | SPI0 Slave Select
Output b | EPPI1 Data 15.
Notes:Maybeusedtowaketheprocessor
from hibernate or deep sleep mode.
PD_00
PD_01
PD_02
PD_03
I/O
I/O
I/O
I/O
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
wk
wk
wk
wk
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PD Position 0 | SPI0 Data 2 | EPPI1
Data 16 | SPI0 Slave Select Output b.
Notes: No notes.
Desc: PD Position 1 | SPI0 Data 3 | EPPI1
Data 17 | SPI0 Slave Select Output b.
Notes: No notes.
Desc: PD Position 2 | SPI0 Master In, Slave
Out.
Notes: No notes.
Desc: PD Position 3 | SPI0 Master Out,
Slave In.
Notes: No notes.
PD_04
PD_05
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PD Position 4 | SPI0 Clock.
Notes: No notes.
Desc: PD Position 5 | SPI1 Clock | TIMER0
Alternate Clock 7.
Notes: No notes.
PD_06
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PD Position 6 | EPPI1 Frame Sync 2
(VSYNC) | ETH0 RMII Management Data
Interrupt | TIMER0 Alternate Capture
Input 5.
Notes:Maybeusedtowaketheprocessor
from hibernate or deep sleep mode.
PD_07
PD_08
PD_09
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PD Position 7 | UART0 Transmit |
TIMER0 Alternate Capture Input 3.
Notes: No notes.
Desc: PD Position 8 | UART0 Receive |
TIMER0 Alternate Capture Input 0.
Notes: No notes.
Desc: PD Position 9 | SPI1 Slave Select
Output b | UART0 Request to Send | SPI0
Slave Select Output b.
Notes: No notes.
PD_10
PD_11
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PD Position 10 | SPI0 Ready | UART0
Clear to Send | SPI1 Slave Select Output b.
Notes: No notes.
Desc: PD Position 11 | SPI0 Slave Select
Output b | SPI0 Slave Select Input.
Notes: No notes.
Rev. 0
|
Page 43 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PD_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PD Position 12 | SPI1 Slave Select
Output b | EPPI0 Data 20 | SPORT1
Channel A Data 1 | SPI1 Slave Select Input.
Notes: No notes.
PD_13
PD_14
PD_15
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PD Position 13 | SPI1 Master Out,
Slave In | TIMER0 Alternate Clock 5.
Notes: No notes.
Desc:PDPosition14|SPI1MasterIn,Slave
Out | TIMER0 Alternate Clock 6.
Notes: No notes.
Desc: PD Position 15 | SPI1 Slave Select
Output b | EPPI0 Data 21 | SPORT1
Channel A Data 0.
Notes: No notes.
PE_00
PE_01
PE_02
PE_03
I/O
I/O
I/O
I/O
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
wk
wk
wk
wk
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PE Position 0 | SPI1 Data 3 | EPPI0
Data 18 | SPORT1 Channel B Data 1.
Notes: No notes.
Desc: PE Position 1 | SPI1 Data 2 | EPPI0
Data 19 | SPORT1 Channel B Data 0.
Notes: No notes.
Desc: PE Position 2 | SPI1 Ready | EPPI0
Data 22 | SPORT1 Channel A Clock.
Notes: No notes.
Desc: PE Position 3 | EPPI0 Data 16 |
SPORT1 Channel B Frame Sync | ACM0
Frame Sync.
Notes: No notes.
PE_04
PE_05
PE_06
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PE Position 4 | EPPI0 Data 17 |
SPORT1 Channel B Clock | ACM0 Clock.
Notes: No notes.
Desc: PE Position 5 | EPPI0 Data 23 |
SPORT1 Channel A Frame Sync.
Notes: No notes.
Desc: PE Position 6 | SPORT1 Channel A
Transmit Data Valid | EPPI0 Frame Sync 3
(FIELD) | LP3 Clock.
Notes: No notes.
PE_07
PE_08
PE_09
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PE Position 7 | SPORT1 Channel B
Transmit Data Valid | EPPI0 Frame Sync 2
(VSYNC) | LP3 Acknowledge.
Notes: No notes.
Desc: PE Position 8 | PWM0 Sync | EPPI0
FrameSync1(HSYNC)|LP2Acknowledge
| ACM0 External Trigger 0.
Notes: No notes.
Desc: PE Position 9 | EPPI0 Clock | LP2
Clock | PWM0 Shutdown Input.
Notes: No notes.
Rev. 0
|
Page 44 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PE_10
PE_11
PE_12
I/O
I/O
I/O
A
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PE Position 10 | PWM1 Channel D
Low Side | RSI0 Data 6 | ETH1
Management Channel Clock.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
A
A
wk
wk
Desc: PE Position 11 | PWM1 Channel D
High Side | ETH1 Management Channel
Serial Data | RSI0 Data 7.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
Desc: PE Position 12 | PWM1 Channel C
Low Side | RSI0 Data 5 | ETH1 RMII
Management Data Interrupt.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
referenceformoredetails. Maybeusedto
wake the processor from hibernate or
deep sleep mode.
PE_13
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PE Position 13 | PWM1 Channel C
High Side | RSI0 Data 4 | ETH1 Carrier
Sense/RMII Receive Data Valid.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PE_14
PE_15
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PE Position 14 | SPORT2 Channel A
Transmit Data Valid | TIMER0 Timer 0 |
ETH1 Receive Error.
Notes: No notes.
Desc: PE Position 15 | PWM1 Channel B
Low Side | RSI0 Data 3 | ETH1 Receive
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PF_00
PF_01
PF_02
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc:PFPosition0|PWM0ChannelALow
Side | EPPI0 Data 0 | LP2 Data 0.
Notes: No notes.
Desc: PF Position 1 | PWM0 Channel A
High Side | EPPI0 Data 1 | LP2 Data 1.
Notes: No notes.
Desc:PFPosition2|PWM0ChannelBLow
Side | EPPI0 Data 2 | LP2 Data 2.
Notes: No notes.
Rev. 0
|
Page 45 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PF_03
PF_04
PF_05
PF_06
PF_07
PF_08
PF_09
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PG_00
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PF Position 3 | PWM0 Channel B
High Side | EPPI0 Data 3 | LP2 Data 3.
Notes: No notes.
A
A
A
A
A
A
A
A
A
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
Desc:PFPosition4|PWM0ChannelCLow
Side | EPPI0 Data 4 | LP2 Data 4.
Notes: No notes.
Desc: PF Position 5 | PWM0 Channel C
High Side | EPPI0 Data 5 | LP2 Data 5.
Notes: No notes.
Desc: PF Position 6 | PWM0 Channel D
Low Side | EPPI0 Data 6 | LP2 Data 6.
Notes: No notes.
Desc: PF Position 7 | PWM0 Channel D
High Side | EPPI0 Data 7 | LP2 Data 7.
Notes: No notes.
Desc: PF Position 8 | SPI1 Slave Select
Output b | EPPI0 Data 8 | LP3 Data 0.
Notes: No notes.
Desc: PF Position 9 | SPI1 Slave Select
Output b | EPPI0 Data 9 | LP3 Data 1.
Notes: No notes.
Desc: PF Position 10 | ACM0 Address 4 |
EPPI0 Data 10 | LP3 Data 2.
Notes: No notes.
Desc: PF Position 11 | EPPI0 Data 11 | LP3
Data 3 | PWM0 Shutdown Input.
Notes: No notes.
Desc: PF Position 12 | ACM0 Address 2 |
EPPI0 Data 12 | LP3 Data 4.
Notes: No notes.
Desc: PF Position 13 | ACM0 Address 3 |
EPPI0 Data 13 | LP3 Data 5.
Notes: No notes.
Desc: PF Position 14 | EPPI0 Data 14 |
ACM0 Address 0 | LP3 Data 6.
Notes: No notes.
Desc: PF Position 15 | ACM0 Address 1 |
EPPI0 Data 15 | LP3 Data 7.
Notes: No notes.
Desc: PG Position 0 | PWM1 Channel B
High Side | RSI0 Data 2 | ETH1 Receive
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_01
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PG Position 1 | SPORT2 Channel A
Frame Sync | TIMER0 Timer 2 | CAN0
Transmit.
Notes: No notes.
Rev. 0
|
Page 46 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PG_02
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PG Position 2 | PWM1 Channel A
Low Side | RSI0 Data 1 | ETH1 Transmit
Data 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_03
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PG Position 3 | PWM1 Channel A
High Side | RSI0 Data 0 | ETH1 Transmit
Data 0.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_04
PG_05
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PG Position 4 | SPORT2 Channel A
Clock | TIMER0 Timer 1 | CAN0 Receive |
TIMER0 Alternate Capture Input 2.
Notes:Maybeusedtowaketheprocessor
from hibernate or deep sleep mode.
Desc: PG Position 5 | RSI0 Command |
ETH1 Transmit Enable | PWM1 Sync |
ACM0 External Trigger 1.
Notes: Has an optional internal pull-up
resistor for use with RSI. See the RSI
chapter in the processor hardware
reference for more details.
PG_06
PG_07
PG_08
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PG Position 6 | RSI0 Clock | SPORT2
Channel B Transmit Data Valid | ETH1
Reference Clock | PWM1 Shutdown Input.
Notes: No notes.
Desc: PG Position 7 | SPORT2 Channel B
FrameSync|TIMER0Timer5|CNT0Count
Zero Marker.
Notes: No notes.
Desc: PG Position 8 | SPORT2 Channel A
Data 1 | TIMER0 Timer 3 | PWM1
Shutdown Input.
Notes: No notes.
PG_09
PG_10
PG_11
I/O
I/O
I/O
A
A
A
wk
wk
wk
wk
wk
wk
none
none
none
wk
wk
wk
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: PG Position 9 | SPORT2 Channel A
Data 0 | TIMER0 Timer 4.
Notes: No notes.
Desc: PG Position 10 | UART1 Request to
Send | SPORT2 Channel B Clock.
Notes: No notes.
Desc: PG Position 11 | SPORT2 Channel B
Data 1 | TIMER0 Timer 6 | CNT0 Count Up
and Direction.
Notes: No notes.
Rev. 0
|
Page 47 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
PG_12
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PG Position 12 | SPORT2 Channel B
Data 0 | TIMER0 Timer 7 | CNT0 Count
Down and Gate.
Notes: No notes.
PG_13
PG_14
I/O
I/O
A
A
wk
wk
wk
wk
none
none
wk
wk
none
none
VDD_EXT
VDD_EXT
Desc: PG Position 13 | UART1 Clear to
Send | TIMER0 Clock.
Notes: No notes.
Desc:PGPosition14|UART1Receive| SYS
Core 1 Idle Indicator | TIMER0 Alternate
Capture Input 1.
Notes: No notes.
PG_15
I/O
A
wk
wk
none
wk
none
VDD_EXT
Desc: PG Position 15 | UART1 Transmit |
SYS Core 0 Idle Indicator | SYS Processor
Sleep Indicator | TIMER0 Alternate
Capture Input 4.
Notes: No notes.
SMC0_A01
SMC0_A02
I/O
I/O
A
A
A
A
wk
wk
pu
wk
wk
wk
pu
wk
none
none
none
none
wk
wk
pu
wk
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: SMC0 Address 1.
Notes: No notes.
Desc: SMC0 Address 2.
Notes: No notes.
SMC0_AMS0 I/O
Desc: SMC0 Memory Select 0.
Notes: No notes.
SMC0_AOE_ I/O
NORDV
Desc: SMC0 NOR Data Valid | SMC0
Output Enable.
Notes: No notes.
SMC0_ARDY_ I/O
NORWT
na
none
none
none
none
none
VDD_EXT
Desc: SMC0 NOR Wait | SMC0
Asynchronous Ready.
Notes: Requires an external pull-up
resistor.
SMC0_ARE
SMC0_AWE
SMC0_BR
I/O
I/O
I/O
A
pu
pu
none
none
none
pu
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
Desc: SMC0 Read Enable.
Notes: No notes.
A
pu
pu
pu
Desc: SMC0 Write Enable.
Notes: No notes.
na
none
none
none
Desc: SMC0 Bus Request.
Notes: Requires an external pull-up
resistor.
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
I/O
I/O
I/O
I/O
I/O
I/O
A
A
A
A
A
A
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
wk
wk
wk
wk
wk
wk
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: SMC0 Data 0.
Notes: No notes.
Desc: SMC0 Data 1.
Notes: No notes.
Desc: SMC0 Data 2.
Notes: No notes.
Desc: SMC0 Data 3.
Notes: No notes.
Desc: SMC0 Data 4.
Notes: No notes.
Desc: SMC0 Data 5.
Notes: No notes.
Rev. 0
|
Page 48 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A
wk
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
L
wk
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
L
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: SMC0 Data 6.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 7.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 8.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 9.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 10.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 11.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 12.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 13.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 14.
Notes: No notes.
A
wk
wk
wk
Desc: SMC0 Data 15.
Notes: No notes.
SYS_BMODE0 I/O
SYS_BMODE1 I/O
SYS_BMODE2 I/O
na
na
na
na
A
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
Desc: SYS Boot Mode Control 0.
Notes: No notes.
Desc: SYS Boot Mode Control 1.
Notes: No notes.
Desc: SYS Boot Mode Control 2.
Notes: No notes.
SYS_CLKIN
a
Desc: SYS Clock Input/Crystal Input.
Notes: Active during reset.
Desc: SYS Processor Clock Output.
Notes: No notes.
SYS_CLKOUT I/O
SYS_EXTWAKE I/O
A
H
Desc: SYS External Wake Control.
Notes: Drives low during hibernate and
high all other times.
SYS_FAULT
SYS_FAULT
SYS_HWRST
I/O
I/O
I/O
I/O
A
none
none
none
none
none
none
none
none
none
none
none
L
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: SYS Fault.
Notes: Open source, requires an external
pull-down resistor.
A
Desc: SYS Complementary Fault.
Notes: Open drain, requires an external
pull-up resistor.
na
A
Desc: SYS Processor Hardware Reset
Control.
Notes: Active during reset.
SYS_NMI_
RESOUT
Desc: SYS Reset Output | SYS Non-
maskable Interrupt.
Notes: Requires an external pull-up
resistor.
Rev. 0
|
Page 49 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
SYS_PWRGD
SYS_TDA
I/O
a
na
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_EXT
VDD_TD
VDD_TD
VDD_EXT
Desc: SYS Power Good Indicator.
Notes: If hibernate is not used or the
internal Power Good Counter is used,
connect to VDD_EXT.
na
na
na
none
none
none
Desc: SYS Thermal Diode Anode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
SYS_TDK
a
Desc: SYS Thermal Diode Cathode.
Notes: Active during reset and hibernate.
If the thermal diode is not used, connect
to ground.
SYS_XTAL
a
Desc: SYS Crystal Output.
Notes: Leave unconnected if an oscillator
is used to provide SYS_CLKIN. Active
during reset. State during hibernate is
controlled by DPM_HIB_DIS.
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
I/O
I/O
I/O
I/O
D
D
D
D
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
Desc: TWI0 Serial Clock.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specificationfortheproperresistorvalue.
If TWI is not used, connect to ground.
Desc: TWI0 Serial Data.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specificationfortheproperresistorvalue.
If TWI is not used, connect to ground.
Desc: TWI1 Serial Clock.
Notes: Open drain, requires external pull-
up resistor. Consult Version 2.1 of the I2C
specificationfortheproperresistorvalue.
If TWI is not used, connect to ground.
Desc: TWI1 Serial Data.
Notes: Open drain, requires external pull-
up resistor. See the I2C-Bus Specification,
Version 2.1, January 2000 for the proper
resistor value. If TWI is not used, connect
to ground.
USB0_CLKIN
USB0_DM
a
na
F
none
none
none
none
none
none
none
none
none
none
VDD_USB
VDD_USB
Desc: USB0 Clock/Crystal Input.
Notes: If USB is not used, connect to
ground. Active during reset.
I/O
Desc: USB0 Data –.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
Rev. 0
|
Page 50 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 15. ADSP-BF60x Designer Quick Reference (Continued)
Driver Int
Reset
Term
Reset
Drive
Hiber
Term
Hiber
Drive
Power
Domain
Description
and Notes
Type
Signal Name Type
Term
USB0_DP
I/O
F
none
none
none
none
none
VDD_USB
Desc: USB0 Data +.
Notes: Pull low if not using USB. For
complete documentation of hibernate
behavior when USB is used, see the USB
chapter in the processor hardware
reference.
USB0_ID
I/O
na
none
none
none
pu
none
VDD_USB
Desc: USB0 OTG ID.
Notes: If USB is not used, connect to
ground. When USB is being used, the
internal pull-up resistor that is present
during hibernate is programmable. See
the USB chapter in the processor
hardware reference. Active during reset.
USB0_VBC
I/O
I/O
E
none
none
none
none
none
none
none
none
none
none
VDD_USB
VDD_USB
Desc: USB0 VBUS Control.
Notes: If USB is not used, pull low.
USB0_VBUS
G
Desc: USB0 Bus Voltage.
Notes: If USB is not used, connect to
ground.
VDD_DMC
s
na
none
none
none
none
none
na
Desc: VDD for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
VDD_EXT
VDD_INT
VDD_TD
s
s
s
na
na
na
none
none
none
none
none
none
none
none
none
none
none
none
none
none
none
na
na
na
Desc: External VDD.
Notes: Must be powered.
Desc: Internal VDD.
Notes: Must be powered.
Desc: VDD for Thermal Diode.
Notes: If the thermal diode is not used,
connect to ground.
VDD_USB
s
s
na
na
none
none
none
none
none
none
none
none
none
none
na
na
Desc: VDD for USB.
Notes: If USB is not used, connect to VDD_
EXT.
VREF_DMC
Desc: VREF for DMC.
Notes: If the DMC is not used, connect to
VDD_INT.
Rev. 0
|
Page 51 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPECIFICATIONS
For information about product specifications please contact
your ADI representative.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
1.25
1.8
Max
1.32
1.9
Unit
V
VDD_INT
Internal Supply Voltage
External Supply Voltage
External Supply Voltage
DDR2/LPDDR Supply Voltage
USB Supply Voltage
CCLK ≤ 500 MHz
1.19
1
VDD_EXT
1.7
V
1
VDD_EXT
3.13
3.3
3.47
1.9
V
VDD_DMC
1.7
1.8
V
2
VDD_USB
3.13
3.3
3.47
3.47
V
VDD_TD
Thermal Diode Supply Voltage
High Level Input Voltage
High Level Input Voltage
High Level Input Voltage
3.13
3.3
V
3
VIH
VDD_EXT = 3.47 V
2.1
V
3
VIH
VDD_EXT = 1.9 V
0.7 × VDD_EXT
0.7 × VVBUSTWI
VDDR_REF + 0.25
0.8 × VDD_DMC
0.50
V
4, 5
VIHTWI
VDD_EXT = Maximum
VDD_DMC = 1.9 V
VDD_DMC = 1.9 V
VIX = 1.075 V
VVBUSTWI
V
6, 7
VIH_DDR2
V
8
VIH_LPDDR
V
9
VID_DDR2
Differential Input Voltage
Differential Input Voltage
Low Level Input Voltage
Low Level Input Voltage
Low Level Input Voltage
V
9
VID_DDR2
VIX = 0.725 V
0.55
V
3
VIL
VDD_EXT = 3.13 V
0.8
V
3
VIL
VDD_EXT = 1.7 V
0.3 × VDD_EXT
0.3 × VVBUSTWI
VDDR_REF – 0.25
0.2 × VDD_DMC
+105
V
4, 5
VILTWI
VDD_EXT = Minimum
VDD_DMC = 1.7 V
VDD_DMC = 1.7 V
TAMBIENT = –40°C to +85°C
TAMBIENT = –40°C to +105°C
V
6, 7
VIL_DDR2
V
8
VIL_LPDDR
V
TJ
TJ
Junction Temperature
Junction Temperature
–40
–40
°C
°C
+125
1 Must remain powered (even if the associated function is not used).
2 If not used, connect to 1.8 V or 3.3 V.
3 Parameter value applies to all input and bidirectional signals except TWI signals, DMC0 signals and USB0 signals.
4 Parameter applies to TWI signals.
5 TWI signals are pulled up to VBUSTWI. See Table 16.
6 Parameter applies to DMC0 signals in DDR2 mode.
7 VDDR_REF is the voltage applied to pin VREF_DMC, nominally VDD_DMC/2.
8 Parameter applies to DMC0 signals in LPDDR mode.
9 Parameter applies to signals DMC0_CK, DMC0_CK, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS when used in DDR2 differential input mode.
Table 16. TWI_VSEL Selections and VDD_EXT/VBUSTWI
VDD_EXT Nominal
3.300
VBUSTWI Min
3.135
VBUSTWI Nom
3.300
VBUSTWI Max
3.465
Unit
TWI0001
TWI001
TWI011
TWI100
V
V
V
V
1.800
1.700
1.800
1.900
1.800
3.135
3.300
3.465
3.300
4.750
5.000
5.250
1 Designs must comply with the VDD_EXT and VBUSTWI voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
Rev. 0
| Page 52 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Clock Related Operating Conditions
Table 17 describes the core clock timing requirements. The data
presented in the tables applies to all speed grades (found in
Automotive Products on Page 109) except where expressly
noted. Figure 8 provides a graphical representation of the vari-
ous clocks and their available divider values.
Table 17. Clock Operating Conditions
Parameter
Min
Max
500
250
125
125
250
125
83.3
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fCCLK
Core Clock Frequency (CCLK ≥ SYSCLK)
SYSCLK Frequency
fSYSCLK
1
fSCLK0
SCLK0 Frequency (SYSCLK ≥ SCLK0)
SCLK1 Frequency (SYSCLK ≥ SCLK1)
DDR2/LPDDR Clock Frequency (SYSCLK ≥ DCLK)
Output Clock Frequency
30
fSCLK1
fDCLK
fOCLK
fPVPCLK
PVP Clock Frequency
1 The minimum frequency for SCLK0 applies only when the USB is used.
Table 18. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fPLLCLK
PLL Clock Frequency
250
1000
MHz
CSEL
(1 32)
CCLK
-
SCLK0
(PVP, ALL OTHER
PERIPHERALS)
S0SEL
(1 4)
-
SYSCLK
SYSSEL
(1 32)
-
SYS_CLKIN
PLL
PLLCLK
SCLK1
(SPORTS, SPI, ACM)
S1SEL
(1 4)
-
DSEL
(1 32)
DCLK
OCLK
-
OSEL
(1 128)
-
Figure 8. Clock Relationships and Divider Values
Rev. 0
| Page 53 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Min
Typical
Max
Unit
V
1
VOH
High Level Output Voltage
High Level Output Voltage
VDD_EXT = 1 . 7 V, IOH = –0.5 mA
VDD_EXT = 3 . 13 V, IOH = –0.5 mA
VDD_EXT – 0.40
VDD_EXT – 0.40
1.388
1
VOH
V
2
VOH_DDR2
High Level Output Voltage, ds = 00 VDD_DMC = 1.70 V, IOH = –13.4 mA
High Level Output Voltage, ds = 10 VDD_DMC = 1.70 V, IOH = –6.70 mA
High Level Output Voltage, ds = 00 VDD_DMC = 1.70 V, IOH = –11.2 mA
High Level Output Voltage, ds = 01 VDD_DMC = 1.70 V, IOH = –7.85 mA
High Level Output Voltage, ds = 10 VDD_DMC = 1.70 V, IOH = –5.10 mA
High Level Output Voltage, ds = 11 VDD_DMC = 1.70 V, IOH = –2.55 mA
V
3
VOH_DDR2
1.311
V
4
VOH_LPDDR
1.300
V
5
VOH_LPDDR
1.300
V
6
VOH_LPDDR
1.300
V
7
VOH_LPDDR
1.300
V
8
VOL
Low Level Output Voltage
Low Level Output Voltage
VDD_EXT = 1 . 7 V, IOL = 2.0 mA
VDD_EXT = 3.13 V, IOL = 2.0 mA
0.400
0.400
0.312
0.390
0.400
0.400
0.400
0.400
10
V
8
VOL
V
2
VOL_DDR2
Low Level Output Voltage, ds = 00 VDD_DMC = 1.70 V, IOL13.4 mA
Low Level Output Voltage, ds = 10 VDD_DMC = 1.70 V, IOL = 6.70 mA
Low Level Output Voltage, ds = 00 VDD_DMC = 1.70 V, IOL = 11.2 mA
Low Level Output Voltage, ds = 01 VDD_DMC = 1.70 V, IOL = 7.85 mA
Low Level Output Voltage, ds = 10 VDD_DMC = 1.70 V, IOL = 5.10 mA
Low Level Output Voltage, ds = 11 VDD_DMC = 1.70 V, IOL = 2.55 mA
V
3
VOL_DDR2
V
4
VOL_LPDDR
V
5
VOL_LPDDR
V
6
VOL_LPDDR
V
7
VOL_LPDDR
V
9
IIH
High Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 3.47 V
μA
10
IIH_PD
High Level Input Current with Pull- VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
110
10
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
down Resistor
USB = 3.47 V, VIN = 3.47 V
11
IIL
Low Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 0 V
12
IIL_PU
Low Level Input Current with Pull-up VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
100
240
100
10
Resistor
USB = 3.47 V, VIN = 0 V
13
IIH_USB0
High Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 3.47 V
13
IIL_USB0
Low Level Input Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 0 V
14
IOZH
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 3.47 V
15
IOZH
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 1.9 V
10
16
IOZL
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 0 V
10
17
IOZL_PU
Three-State Leakage Current with VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
100
10
Pull-up Resistor
USB = 3.47 V, VIN = 0 V
18
IOZH_TWI
Three-State Leakage Current
VDD_EXT = 3.47 V, VDD_DMC = 1.9 V, VDD_
USB = 3.47 V, VIN = 5.5 V
19, 20
CIN
Input Capacitance
Input Capacitance
Input Capacitance
VDD_TD Current
TAMBIENT = 25°C
TAMBIENT = 25°C
TAMBIENT = 25°C
VDD_TD = 3.3 V
4.9
8.9
5.8
6.7
9.9
6.6
1
pF
pF
pF
μA
mA
18, 20
CIN_TWI
20, 21
CIN_DDR
IDD_TD
22, 23
IDD_DEEPSLEEP
VDD_INT Current in Deep Sleep Mode fCCLK = 0 MHz
SCLK0/1 = 0 MHz
Table 21 on
Page 57
f
Rev. 0
| Page 54 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Parameter
Test Conditions
fCCLK = 500 MHz
Min
Typical
Max
Unit
23
IDD_IDLE
VDD_INT Current in Idle
137
mA
ASFC0 = 0.14 (Idle)
ASFC1 = 0 (Disabled)
f
SYSCLK = 250 MHz, fSCLK0/1 = 125 MHz
fDCLK = 0 MHz (DDR Disabled)
USBCLK = 0 MHz (USB Disabled)
f
No PVP or DMA activity
TJ = 25°C
23
IDD_TYP
VDD_INT Current
fCCLK = 500 MHz
357
mA
ASFC0 = 1.0 (Full-on Typical)
ASFC1 = 0.86 (App)
f
f
f
SYSCLK = 250 MHz, fSCLK0/1 = 125 MHz
DCLK = 250 MHz
USBCLK = 0 MHz (USB Disabled)
DMA Data Rate = 124 MB/s
Medium PVP Activity
TJ = 25°C
22, 24
IDD_HIBERNATE
Hibernate State Current
VDD_INT = 0 V,
40
10
A
A
V
V
DD_EXT = VDD_TD = VDD_USB = 3.3 V,
DD_DMC = 1.8 V, VREF_DMC = 0.9 V,
TJ = 25°C, fCLKIN = 0 MHz
VDD_INT = 0 V,
V
22, 24
IDD_HIBERNATE
Hibernate State Current
Without USB
DD_EXT = VDD_TD = VDD_USB = 3.3 V,
VDD_DMC = 1.8 V, VREF_DMC = 0.9 V,
TJ = 25°C,
f
CLKIN = 0 MHz, USB protection
disabled (USB0_PHY_CTL.DIS=1)
23
IDD_INT
VDD_INT Current
fCCLK > 0 MHz
See IDDINT_TOT mA
equation
f
SCLK0/1 ≥ 0 MHz
on Page 56
1 Applies to all output and bidirectional signals except DMC0 signals, TWI signals and USB0 signals.
2 Applies to all DMC0 output and bidirectional signals in DDR2 full drive strength mode.
3 Applies to all DMC0 output and bidirectional signals in DDR2 half drive strength mode.
4 Applies to all DMC0 output and bidirectional signals in LPDDR full drive strength mode.
5 Applies to all DMC0 output and bidirectional signals in LPDDR three-quarter drive strength mode.
6 Applies to all DMC0 output and bidirectional signals in LPDDR half drive strength mode.
7 Applies to all DMC0 output and bidirectional signals in LPDDR one-quarter drive strength mode.
8 Applies to all output and bidirectional signals except DMC0 signals and USB0 signals.
9 Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TDI, and JTG_TMS.
10Applies to signals JTG_TCK and JTG_TRST.
11Applies to signals SMC0_ARDY, SMC0_BR, SYS_BMODE0–2, SYS_CLKIN, SYS_HWRST, SYS_PWRGD, JTG_TCK, and JTG_TRST.
12Applies to signals JTG_TDI, JTG_TMS.
13Applies to signal USB0_CLKIN.
14Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_AMS0, SMC0_ARE, SMC0_AWE, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_
FAULT, SYS_FAULT, JTG_EMU, JTG_TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS.
15 Applies to DMC0_A[00:13], DMC0_BA[0:2], DMC0_CAS, DMC0_CS0, DMC0_DQ[00:15], DMC0_LQDS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM,
DMC0_UDM, DMC0_ODT, DMC0_RAS, and DMC0_WE.
16Applies to signals PA0–15, PB0–15, PC0–15, PD0–15, PE0–15, PF0–15, PG0–15, SMC0_A0E, SMC0_A01–02, SMC0_D00–15, SYS_FAULT, SYS_FAULT, JTG_EMU, JTG_
TDO, USB0_DM, USB0_DP, USB0_ID, USB0_VBC, USB0_VBUS, DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CS0, DMC0_DQ00–15, DMC0_LQDS, DMC0_
LDQS, DMC0_UDQS, DMC0_UDQS, DMC0_LDM, DMC0_UDM, DMC0_ODT, DMC0_RAS, DMC0_WE, and TWI signals.
17Applies to signals SMC0_AMS0, SMC0_ARE, SMC0_AWE, and when RSI pull-up resistors are enabled, PE10–13, 15 and PG00, 02, 03, 05.
18Applies to all TWI signals.
19Applies to all signals, except DMC0 and TWI signals.
20Guaranteed, but not tested.
21Applies to all DMC0 signals
22See the ADSP-BF60x Blackfin Processor Hardware Reference Manual for definition of deep sleep and hibernate operating modes.
23Additional information can be found at Total Internal Power Dissipation on Page 56.
24Applies to VDD_EXT, VDD_DMC, VDD_USB and VDD_TD supply signals only. Clock inputs are tied high or low.
Rev. 0
| Page 55 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
I
DDINT_CCLK_DYN (mA) = Table 19 × (ASFC0 + ASFC1)
Total Internal Power Dissipation
The dynamic current of the PVP is determined by selecting the
appropriate use case from Table 22.
Total power dissipation has two components:
1. Static, including leakage current (deep sleep)
I
DDINT_PVP_DYN (mA) = Table 22
2. Dynamic, due to transistor switching characteristics for
each clock domain
Clock Current
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. The following equation describes the internal
current consumption.
The dynamic clock currents provide the total power dissipated
by all transistors switching in the clock paths. The power dissi-
pated by each clock domain is dependent on voltage (VDD_INT),
operating frequency and a unique scaling factor.
I
DDINT_TOT = IDDINT_CCLK_DYN + IDDINT_SYSCLK_DYN +
IDDINT_SYSCLK_DYN (mA) = 0.187 × fSYSCLK (MHz) × VDD_INT (V)
IDDINT_SCLK0_DYN + IDDINT_SCLK1_DYN + IDDINT_DCLK_DYN +
I
I
I
DDINT_SCLK0_DYN (mA) = 0.217 × fSCLK0 (MHz) × VDD_INT (V)
DDINT_SCLK1_DYN (mA) = 0.042 × fSCLK1 (MHz) × VDD_INT (V)
DDINT_DCLK_DYN (mA) = 0.024 × fDCLK (MHz) × VDD_INT (V)
I
I
DDINT_USBCLK_DYN + IDDINT_DMA_DR_DYN +
DDINT_DEEPSLEEP + IDDINT_PVP_DYN
I
DDINT_DEEPSLEEP is the only item present that is part of the static
power dissipation component. IDDINT_DEEPSLEEP is specified as a
function of voltage (VDD_INT) and temperature (see Table 21).
The dynamic component of the USB clock is a unique case. The
USB clock contributes a near constant current value when used.
There are eight different items that contribute to the dynamic
power dissipation. These components fall into three broad cate-
gories: application-dependent currents, clock currents and data
transmission currents.
I
DDINT_USBCLK_DYN (mA) = 5 mA (if USB enabled)
Data Transmission Current
The data transmission current represents the power dissipated
when transmitting data. This current is expressed in terms of
data rate. The calculation is performed by adding the data rate
(MB/s) of each DMA and core driven access to peripherals and
L2/external memory. This number is then multiplied by a coeffi-
cient and VDD_INT. The following equation provides an estimate
of all data transmission current.
Application-Dependent Current
The application-dependent currents include the dynamic cur-
rent in the core clock domain and the dynamic current of the
PVP.
Core clock (CCLK) use is subject to an activity scaling factor
(ASF) that represents application code running on the processor
cores and L1/L2 memories (Table 20). The ASF is combined
with the CCLK frequency and VDD_INT dependent data in
Table 19 to calculate this portion.
I
DDINT_DMA_DR_DYN(mA) = 0.0578 × data rate (MB/s) × VDD_INT (V)
For details on using this equation see the related Engineer Zone
material.
Table 19. CCLK Dynamic Current per core (mA, with ASF = 1)
Voltage (VDD_INT
)
fCCLK (MHz)
500
1.175 1.200 1.225 1.250 1.275 1.300 1.320
96.3
87.2
78.0
68.7
59.7
50.3
41.3
32.0
22.7
98.8
89.5
80.1
70.7
61.2
51.8
42.4
32.9
23.5
101.5
91.9
82.2
72.5
63.0
53.2
43.6
34.0
24.2
103.9
94.1
84.3
74.4
64.6
54.7
44.8
34.8
25.0
106.7
96.7
86.5
76.3
66.3
56.3
46.0
35.9
25.7
109.3
98.9
88.6
78.3
68.0
57.6
47.2
37.0
26.5
110.8
100.6
90.1
79.4
69.1
58.5
48.2
37.4
26.9
450
400
350
300
250
200
150
100
Rev. 0
| Page 56 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 20. Activity Scaling Factors (ASF)
IDDINT Power Vector
IDD-PEAK
ASF
1.34
1.25
1.00
0.86
0.72
0.14
IDD-HIGH
IDD-FULL-ON-TYP
IDD-APP
IDD-NOP
IDD-IDLE
Table 21. Static Current—IDD_DEEPSLEEP (mA)
Voltage (VDD_INT
)
TJ (°C)
–40
–20
0
1.175 1.200 1.225 1.250 1.275 1.300 1.320
1.7
1.8
2.2
2.5
2.7
3.1
3.4
4.0
4.2
4.6
5.1
5.6
6.2
6.8
8.2
9.0
9.6
10.6
23.2
36.8
56.4
80.6
113.0
163.4
183.4
229.5
277.3
11.5
25.3
40.0
60.6
86.2
120.7
173.9
195.2
243.9
294.0
12.5
27.2
42.8
65.0
92.4
128.9
185.1
207.5
258.6
311.9
13.4
29.0
45.4
68.1
97.9
136.4
194.1
217.5
271.1
326.4
25
18.3
29.6
45.4
65.8
92.8
135.5
152.7
191.9
232.8
19.8
31.7
48.9
70.4
99.3
144.2
162.4
203.7
247.2
21.5
34.4
52.4
75.5
105.9
153.6
172.5
216.2
261.8
40
55
70
85
100
105
115
125
Table 22. IDDINT_PVP_DYN (mA)
PVP Activity Level
PVPSF (PVP Scaling Factor)
High
42.4
20
0
Medium
Low
Rev. 0
| Page 57 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
PROCESSOR — ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Stresses greater than those listed in Table 23 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 23. Absolute Maximum Ratings
Parameter
Rating
PROCESSOR — PACKAGE INFORMATION
Internal Supply Voltage (VDD_INT
)
–0.33 V to 1.32 V
The information presented in Figure 9 and Table 25 provides
details about package branding. For a complete listing of prod-
uct availability, see Automotive Products on Page 109.
External (I/O) Supply Voltage (VDD_EXT) –0.33 V to 3.63 V
Thermal Diode Supply Voltage
(VDD_TD
DDR2 Controller Supply Voltage
(VDD_DMC
–0.33 V to 3.63 V
)
–0.33 V to 1.90 V
)
USB PHY Supply Voltage (VDD_USB
Input Voltage1, 2, 3
)
–0.33 V to 3.63 V
–0.33 V to 3.63 V
–0.33 V to 5.50 V
–0.33 V to 5.25 V
–0.33 V to 6.00 V
–0.33 V to 1.90 V
–0.33 V to VDD_EXT + 0.5 V
12.5 mA (max)
a
ADSP-BF609
tppZccc
TWI Input Voltage2, 4
USB0_Dx Input Voltage5
USB0_VBUS Input Voltage5
DDR2 Input Voltage6
vvvvvv.x n.n
#yyww country_of_origin
B
Output Voltage Swing
I
OH/IOL Current per Signal1
Figure 9. Product Information on Package
Storage Temperature Range
–65°C to +150°C
+125°C
Junction Temperature Under Bias
Table 25. Package Brand Information
1 Applies to 100% transient duty cycle.
2 Applies only when VDD_EXT is within specifications. When VDD_EXT is outside
specifications, the range is VDD_EXT 0.2 V.
Brand Key
Field Description
Product Model
ADSP-BF609
3 For other duty cycles see Table 24.
4 Applies to balls TWI_SCL and TWI_SDA.
t
Temperature Range
Package Type
5 If the USB is not used, connect USB0_Dx and USB0_VBUS according to Table 15
on Page 37.
pp
6 Applies only when VDD_DMC is within specifications. When VDD_DMC is outside
specifications, the range is VDD_DMC 0.2 V.
Z
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
ccc
vvvvvv.x
n.n
Table 24. Maximum Duty Cycle for Input Transient Volt-
age1, 2
yyww
Date Code
Maximum Duty Cycle (%)2
VIN Min (V)3
–0.33
VIN Max (V)3
3.63
100
50
40
25
20
15
10
–0.50
3.80
–0.56
3.86
–0.67
3.97
–0.73
4.03
–0.80
4.10
–0.90
4.20
1 Applies to all signal balls with the exception of SYS_CLKIN, SYS_XTAL,
SYS_EXT_WAKE, USB0_DP, USB0_DM, USB0_VBUS, TWI signals, and
DMC0 signals.
2 Applies onlywhenVDD_EXT is withinspecifications. WhenVDD_EXT is outside speci-
fications, the range is VDD_EXT 0.2 V.
3 The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of
the specified voltages, and the total duration of the overshoot or undershoot
(exceeding the 100% case) must be less than or equal to the corresponding duty
cycle.
Rev. 0
| Page 58 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Clock and Reset Timing
Table 26 and Figure 10 describe clock and reset operations. Per
the CCLK, SYSCLK, SCLK0, SCLK1, DCLK, and OCLK timing
specifications in Table 17 on Page 53, combinations of
SYS_CLKIN and clock multipliers must not select clock rates in
excess of the processor’s maximum instruction rate.
Table 26. Clock and Reset Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
fCKIN
SYS_CLKIN Frequency (using a crystal)1, 2, 3
SYS_CLKIN Frequency (using a crystal oscillator)1, 2, 3 20
SYS_CLKIN Low Pulse1
SYS_CLKIN High Pulse1
20
50
60
MHz
MHz
ns
fCKIN
tCKINL
tCKINH
tWRST
6.67
6.67
ns
SYS_HWRST Asserted Pulse Width Low4
11 × tCKIN
ns
1 Applies to PLL bypass mode and PLL non bypass mode.
2 The tCKIN period (see Figure 10) equals 1/fCKIN
.
3 If the CGU_CTL.DF bit is set, the minimum fCKIN specification is 40 MHz.
4 Applies after power-up sequence is complete. See Table 27 and Figure 11 for power-up reset timing.
tCKIN
SYS_CLKIN
tCKINL
tCKINH
tWRST
SYS_HWRST
Figure 10. Clock and Reset Timing
Rev. 0
| Page 59 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Power-Up Reset Timing
In Figure 11, VDD_SUPPLIES are VDD_INT, VDD_EXT, VDD_DMC, VDD_USB
,
and VDD_TD
.
Table 27. Power-Up Reset Timing
Parameter
Min
Max
Unit
Timing Requirement
tRST_IN_PWR SYS_HWRST Deasserted after VDD_INT, VDD_EXT, VDD_DMC, VDD_USB, VDD_TD, and SYS_ 11 × tCKIN
CLKIN are Stable and Within Specification
ns
RESET
tRST_IN_PWR
CLKIN
V
DD_SUPPLIES
Figure 11. Power-Up Reset Timing
Rev. 0
| Page 60 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Read
Table 28. Asynchronous Memory Read (BxMODE = b#00)
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSDATARE
tHDATARE
tDARDYARE
DATA in Setup Before SMC0_ARE High
DATA in Hold After SMC0_ARE High
SMC0_ARDY Valid After SMC0_ARE Low1, 2
8.2
0
ns
ns
ns
(RAT – 2.5) × tSCLK0 – 17.5
Switching Characteristics
tADDRARE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_ (PREST + RST + PREAT) × tSCLK0 – 2
ARE Low3
ns
tAOEARE
tHARE
SMC0_AOE Assertion Before SMC0_ARE Low
Output4 Hold After SMC0_ARE High5
SMC0_ARE Active Low Width6
(RST + PREAT) × tSCLK0 – 2
RHT × tSCLK0 –2
ns
ns
ns
ns
tWARE
RAT × tSCLK0 – 2
2.5 × tSCLK0
tDAREARDY
SMC0_ARE High Delay After SMC0_ARDY
Assertion1
3.5 × tSCLK0 + 17.5
1 SMC0_BxCTL.ARDYEN bit = 1.
2 RAT value set using the SMC_BxTIM.RAT bits.
3 PREST, RST, and PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, and the SMC_BxETIM.PREAT bits.
4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE, SMC0_ABEx.
5 RHT value set using the SMC_BxTIM.RHT bits.
6 SMC0_BxCTL.ARDYEN bit = 0.
SMC0_ARE
tWARE
tHARE
tADDRARE
SMC0_AMSx
SMC0_Ax
tAOEARE
SMC0_AOE
tDARDYARE
tDAREARDY
SMC0_ARDY
tSDATARE
tHDATARE
SMC0_Dx (DATA)
Figure 12. Asynchronous Read
Rev. 0
| Page 61 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Flash Read
Table 29. Asynchronous Flash Read
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
PREST × tSCLK0 – 2
Max
Unit
Switching Characteristics
tAMSADV
SMC0_Ax (Address)/SMC0_AMSx Assertion Before SMC0_NORDV
ns
Low1
tWADV
SMC0_NORDV Active Low Width2
SMC0_ARE Low Delay From SMC0_NORDV High3
Output4 Hold After SMC0_ARE High5
SMC0_ARE Active Low Width7
RST × tSCLK0 – 2
PREAT × tSCLK0 – 2
RHT × tSCLK0 – 2
RAT × tSCLK0 – 2
ns
ns
ns
ns
tDADVARE
tHARE
6
tWARE
1 PREST value set using the SMC_BxETIM.PREST bits.
2 RST value set using the SMC_BxTIM.RST bits.
3 PREAT value set using the SMC_BxETIM.PREAT bits.
4 Output signals are SMC0_Ax, SMC0_AMS, SMC0_AOE.
5 RHT value set using the SMC_BxTIM.RHT bits.
6 SMC0_BxCTL.ARDYEN bit = 0.
7 RAT value set using the SMC_BxTIM.RAT bits.
SMC0_Ax
SMC0_AMSx
(NOR_CE)
tAMSADV
tWADV
SMC0_NORDV
tWARE
tHARE
tDADVARE
SMC0_ARE
(NOR_OE)
SMC0_Dx
(DATA)
READ LATCHED
DATA
Figure 13. Asynchronous Flash Read
Rev. 0
| Page 62 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Page Mode Read
Table 30. Asynchronous Page Mode Read
VDD_EXT
1.8V /3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tAV
SMC0_Ax (Address) Valid for First Address Min Width1 (PREST + RST + PREAT + RAT) × tSCLK0 – 2
ns
ns
tAV1
SMC0_Ax (Address) Valid for Subsequent SMC0_Ax
(Address) Min Width
PGWS × tSCLK0 – 2
tWADV
tHARE
SMC0_NORDV Active Low Width2
Output3 Hold After SMC0_ARE High4
SMC0_ARE Active Low Width6
RST × tSCLK0 – 2
RHT × tSCLK0 – 2
RAT × tSCLK0 – 2
ns
ns
ns
5
tWARE
1 PREST, RST, PREAT and RAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.RST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
2 RST value set using the SMC_BxTIM.RST bits.
3 Output signals are SMC0_Ax, SMC0_AMSx, SMC0_AOE.
4 RHT value set using the SMC_BxTIM.RHT bits.
5 SMC_BxCTL.ARDYEN bit = 0.
6 RAT value set using the SMC_BxTIM.RAT bits.
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
READ
LATCHED
DATA
tAV
A0
tAV1
tAV1
tAV1
SMC0_Ax
(ADDRESS)
A0 + 1
A0 + 2
A0 + 3
SMC0_AMSx
(NOR_CE)
SMC0_AOE
NOR_ADV
tWADV
SMC0_ARE
(NOR_OE)
tWARE
tHARE
SMC0_Dx
(DATA)
D0
D1
D2
D3
Figure 14. Asynchronous Page Mode Read
Rev. 0
| Page 63 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Synchronous Burst Flash Read
Table 31. Synchronous Burst AC Timing (BxMODE = b#11)
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tNDS
tNDH
tNWS
tNWH
DATA-In Setup Before SMC0_NORCLK High
DATA-In Hold After SMC0_NORCLK High
WAIT-In Setup Before SMC0_NORCLK High
WAIT-In Hold After SMC0_NORCLK High
3
ns
ns
ns
ns
1.5
3
1.5
Switching Characteristics
tNRCLS
NOR_CLK Low Period1, 2
NOR_CLK High Period1, 2
NOR_CLK Period1, 2
Output Delay After SMC0_NORCLK High3
Output Hold After SMC0_NORCLK High3
[0.5 × BCLK × tSCLK0 – 1] or [7]
[0.5 × BCLK × tSCLK0 – 1] or [7]
[BCLK × tSCLK0 – 1] or [15]
ns
ns
ns
ns
ns
tNRCHS
tNRCLK
tNDO
6
tNHO
0.8
1 Whichever is greater.
2 BCLKDIV value set using the SMC_BxCTL.BCLK bits. BCLKDIV = (SMC_BxCTL.BCLK + 1).
3 Output = SMC0_Ax (address), SMC0_NORDV, SMC0_ARE, SMC0_AMSx (N0R_CE).
SMC0_NORCLK
tNRCLS
tNRCLK
tNRCHS
tNDO
tNDO
tNDO
tNDO
SMC0_AMSx
tNHO
SMC0_ABE1-0
tNHO
SMC0_Ax
(ADDRESS)
tNDH
t
NDH
t
NDS
tNDS
SMC0_Dx
(DATA)
Dn
Dn+1 Dn+2 Dn+3
tNDO
tNDO
SMC0_NORDV
SMC0_AOE
tNWH
tNWS
SMC0_NORWT
tNDO
tNDO
SMC0_ARE
NOR_OE
NOTE: SMC0_NORCLK dotted line represents a free running version
of SMC0_NORCLK that is not visible on the SMC0_NORCLK pin.
Figure 15. Synchronous Burst AC Interface Timing
Rev. 0
| Page 64 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Write
Table 32. Asynchronous Memory Write (BxMODE = b#00)
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirement
1
tDARDYAWE
SMC0_ARDY Valid After SMC0_AWE Low2
(WAT – 2.5) ×
tSCLK0 – 17.5
ns
Switching Characteristics
tENDAT DATA Enable After SMC0_AMSx Assertion
tDDAT DATA Disable After SMC0_AMSx Deassertion
–3
ns
ns
ns
3
tAMSAWE
SMC0_Ax/SMC0_AMSx Assertion Before SMC0_AWE (PREST + WST + PREAT) × tSCLK0 – 2
Low3
tHAWE
Output4 Hold After SMC0_AWE High5
SMC0_AWE Active Low Width2
WHT × tSCLK0 – 2
WAT × tSCLK0 – 2
ns
ns
6
tWAWE
1
tDAWEARDY
SMC0_AWE High Delay After SMC0_ARDY Assertion 2.5 × tSCLK0
3.5 × tSCLK0 + 17.5 ns
1 SMC_BxCTL.ARDYEN bit = 1.
2 WAT value set using the SMC_BxTIM.WAT bits.
3 PREST, WST, PREAT values set using the SMC_BxETIM.PREST bits, SMC_BxTIM.WST bits, SMC_BxETIM.PREAT bits, and the SMC_BxTIM.RAT bits.
4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5 WHT value set using the SMC_BxTIM.WHT bits.
6 SMC_BxCTL.ARDYEN bit = 0.
SMC0_AWE
SMC0_ABEx
SMC0_Ax
tAMSAWE
tWAWE
tHAWE
SMC0_ARDY
tDARDYAWE
tDAWEARDY
SMC0_AMSx
SMC0_Dx (DATA)
tDDAT
tENDAT
Figure 16. Asynchronous Write
Rev. 0
| Page 65 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Asynchronous Flash Write
Table 33. Asynchronous Flash Write
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tAMSADV
tDADVAWE
tWADV
SMC0_Ax/SMC0_AMSx Assertion Before ADV Low1
SMC0_AWE Low Delay From ADV High2
NR_ADV Active Low Width3
Output4 Hold After SMC0_AWE High5
SMC0_AWE Active Low Width7
PREST × tSCLK0 – 2
ns
ns
ns
ns
ns
PREAT × tSCLK0 – 2
WST × tSCLK0 – 2
WHT × tSCLK0 – 2
WAT × tSCLK0 – 2
tHAWE
6
tWAWE
1 PREST value set using the SMC_BxETIM.PREST bits.
2 PREAT value set using the SMC_BxETIM.PREAT bits.
3 WST value set using the SMC_BxTIM.WST bits.
4 Output signals are DATA, SMC0_Ax, SMC0_AMSx, SMC0_ABEx.
5 WHT value set using the SMC_BxTIM.WHT bits.
6 SMC_BxCTL.ARDYEN bit = 0.
7 WAT value set using the SMC_BxTIM.WAT bits.
NOR_A 25-1
(SMC0_Ax)
NR_CE
(SMC0_AMSx)
tAMSADV
tWADV
NR_ADV
(SMC0_AOE)
tWAWE
tHAWE
tDADVAWE
NR_WE
(SMC0_AWE)
NR_DQ 15
-0
(SMC0_Dx)
Figure 17. Asynchronous Flash Write
All Accesses
Table 34. All Accesses
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristic
tTURN
SMC0_AMSx Inactive Width
(IT + TT) × tSCLK0 – 2
ns
Rev. 0
| Page 66 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Bus Request/Bus Grant
Table 35. Bus Request/Bus Grant
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tDBGBR
SMC0_BG Delay After SMC0_BR
2.5 × tSCLK0
–3
3.5 × tSCLK0 + 17.5
3
ns
ns
ns
tENGDAT
tDBGDAT
DATA Enable After SMC0_BG Deassertion
DATA Disable After SMC0_BG Assertion
SMC0_BR
SMC0_BG
tDBGBR
tDNGDAT
tENGDAT
SMC0 DATA/ADDRESS
CONTROL
Figure 18. Bus Request/Bus Grant
DDR2 SDRAM Clock and Control Cycle Timing
Table 36. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
250 MHz
Max
Parameter
Min
Unit
Switching Characteristics
tCK
tCH
tCL
tIS
Clock Cycle Time (CL = 2 Not Supported)
Minimum Clock Pulse Width
4
ns
tCK
tCK
ps
ps
0.45
0.45
350
475
0.55
0.55
Maximum Clock Pulse Width
Control/Address Setup Relative to DMC0_CK Rise
Control/Address Hold Relative to DMC0_CK Rise
tIH
tCK
tCH
tCL
DMC0_CK
DMC0_CK
tIS
tIH
ADDRESS
CONTROL
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00 13, AND DMC0_BA0 1.
-
-
Figure 19. DDR2 SDRAM Clock and Control Cycle Timing
Rev. 0
| Page 67 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Read Cycle Timing
Table 37. DDR2 SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
250 MHz1
Max
Parameter
Min
Unit
Timing Requirements
tDV
Data Valid Window
1
ns
ns
tDQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated DMC0_
DQ Signals
0.35
tQH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
1.6
0.9
0.4
ns
tCK
tCK
tRPRE
tRPST
Read Preamble
Read Postamble
1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
tCK
tCH
tCL
DDR2_CLKx
DDR2_CLKx
tAS
tAH
DDR2_ADDR
DDR2_CTL
tAC
tDQSCK
tRPRE
DDR2_DQSn
DDR2_DQSn
tDQSQ
tRPST
tQH
tDQSQ
tQH
DDR2_DATA
Figure 20. DDR2 SDRAM Controller Input AC Timing
Rev. 0
| Page 68 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DDR2 SDRAM Write Cycle Timing
Table 38. DDR2 SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V
250 MHz1
Max
Parameter
Min
Unit
Switching Characteristics
2
tDQSS
tDS
DMC0_DQS Latching Rising Transitions to Associated Clock Edges
Last Data Valid to DMC0_DQS Delay
DMC0_DQS to First Data Invalid Delay
DMC0_DQS Falling Edge to Clock Setup Time
DMC0_DQS Falling Edge Hold Time From DMC0_CK
DMC0_DQS Input High Pulse Width
DMC0_DQS Input Low Pulse Width
–0.15
0.15
0.3
0.15
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tDH
tDSS
0.25
0.25
0.35
0.35
0.35
0.4
tDSH
tDQSH
tDQSL
tWPRE
tWPST
tIPW
Write Preamble
Write Postamble
Address and Control Output Pulse Width
0.6
tDIPW
DMC0_DQ and DMC0_DM Output Pulse Width
0.35
1 In order to ensure proper operation of the DDR2, all the DDR2 guidelines have to be strictly followed.
2 Write command to first DMC0_DQS delay = WL × tCK + tDQSS
.
DMC0_CK
tIPW
DMC0_A00
tDSH
tDSS
tDQSS
DMC0_LDQS
DMC0_UDQS
tWPRE
tDQSL
tDQSH
tWPST
tDS
tDH
tDIPW
DMC0_LDM
DMC0_UDM
Figure 21. DDR2 SDRAM Controller Output AC Timing
Rev. 0
| Page 69 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Clock and Control Cycle Timing
Table 39. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
200 MHz
Max
Parameter
Min
Unit
Switching Characteristics
tCK
tCH
tCL
tIS
Clock Cycle Time (CL = 2 Not Supported)
5
ns
tCK
tCK
ns
ns
Minimum Clock Pulse Width
0.45
0.45
1
0.55
0.55
Maximum Clock Pulse Width
Control/Address Setup Relative to DMC0_CK Rise
Control/Address Hold Relative to DMC0_CK Rise
tIH
1
tCK
tCH
tCL
DMC0_CK
DMC0_CK
tIS
tIH
ADDRESS
CONTROL
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00 13, AND DMC0_BA0 1.
-
-
Figure 22. Mobile DDR SDRAM Clock and Control Cycle Timing
Mobile DDR SDRAM Read Cycle Timing
Table 40. Mobile DDR SDRAM Read Cycle Timing, VDD_DMC Nominal 1.8 V
200 MHz
Max
Parameter
Min
Unit
Timing Requirements
tQH
DMC0_DQ, DMC0_DQS Output Hold Time From DMC0_DQS
1.75
ns
ns
tDQSQ
DMC0_DQS-DMC0_DQ Skew for DMC0_DQS and Associated
DMC0_DQ Signals
0.4
tRPRE
tRPST
Read Preamble
Read Postamble
0.9
0.4
1.1
0.6
tCK
tCK
DMC0_CK
t
t
RPST
RPRE
DMC0_DQS
t
QH
DMC0_DQS
(DATA)
Dn
Dn+1
Dn+2
Dn+3
t
DQSQ
Figure 23. Mobile DDR SDRAM Controller Input AC Timing
Rev. 0
| Page 70 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Mobile DDR SDRAM Write Cycle Timing
Table 41. Mobile DDR SDRAM Write Cycle Timing, VDD_DMC Nominal 1.8 V
200 MHz
Max
Parameter
Min
Unit
Switching Characteristics
1
tDQSS
tDS
DMC0_DQS Latching Rising Transitions to Associated Clock Edges
Last Data Valid to DMC0_DQS Delay (Slew > 1 V/ns)
DMC0_DQS to First Data Invalid Delay (Slew > 1 V/ns)
DMC0_DQS Falling Edge to Clock Setup Time
DMC0_DQS Falling Edge Hold Time From DMC0_CK
DMC0_DQS Input High Pulse Width
0.75
0.48
0.48
0.2
1.25
tCK
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
tDH
tDSS
tDSH
tDQSH
tDQSL
tWPRE
tWPST
tIPW
0.2
0.4
DMC0_DQS Input Low Pulse Width
0.4
Write Preamble
0.25
0.4
Write Postamble
Address and Control Output Pulse Width
2.3
tDIPW
DMC0_DQ and DMC0_DM Output Pulse Width
1.8
1 Write command to first DMC0_DQS delay = WL × tCK + tDQSS
.
DMC0_CK
t
t
DSS
DSH
t
DQSS
DMC0_DQS0-1
t
WPRE
t
t
t
WPST
DQSL
DQSH
t
t
DH
DS
t
DIPW
DMC0_DQ0
-
15/
Dn
Dn+1
Dn+2
Dn+3
DMC0_DQM0
-
1
t
DIPW
Write CMD
CONTROL
NOTE: CONTROL = DMC0_CS0, DMC0_CKE, DMC0_RAS, DMC0_CAS, AND DMC0_WE.
ADDRESS = DMC0_A00 13, AND DMC0_BA0 1.
-
-
t
IPW
Figure 24. Mobile DDR SDRAM Controller Output AC Timing
Rev. 0
| Page 71 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Enhanced Parallel Peripheral Interface Timing
Table 42 and Figure 25 on Page 72, Figure 27 on Page 74,
Figure 26 on Page 73, and Figure 28 on Page 74 describe
enhanced parallel peripheral interface timing operations.
Table 42. Enhanced Parallel Peripheral Interface—Internal Clock
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSPI
External Frame Sync Setup Before EPPI_ 7.9
CLK
External Frame Sync Hold After EPPI_CLK 0
6.5
ns
tHFSPI
tSDRPI
tHDRPI
0
ns
ns
ns
Receive Data Setup Before EPPI_CLK
Receive Data Hold After EPPI_CLK
7.9
6.5
0
0
Switching Characteristics
tPCLKW
EPPI_CLK Width for Data Transmit, FS
[0.5 × tSCLK0 – 1.5] or [4.5]
[0.5 × tSCLK0 – 1.5] or [6.5]
[tSCLK0 – 1.5] or [12]
[0.5 × tSCLK0 – 1.5] or [4.5]
[0.5 × tSCLK0 – 1.5] or [6.5]
[tSCLK0 – 1.5] or [12]
ns
ns
ns
ns
External Data/FS Transmit1
EPPI_CLK Width for Data Transmit, FS
Internal Data/FS Receive1
tPCLK
EPPI_CLK Period for Data Receive, FS
External Data/FS Transmit1
EPPI_CLK Period for Data Receive, FS
Internal Data/FS Receive1
[tSCLK0 – 1.5] or [16]
[tSCLK0 – 1.5] or [16]
tDFSPI
Internal Frame Sync Delay After EPPI_CLK
3.5
3.5
3.5
3.5
ns
ns
ns
ns
ns
tHOFSPI
tDDTPI
tHDTPI
tSFS3GE
Internal Frame Sync Hold After EPPI_CLK –0.5
Transmit Data Delay After EPPI_CLK
–0.5
Transmit Data Hold After EPPI_CLK
–0.5
–0.5
14
External FS3 Input Setup Before EPPI_CLK 15.4
Fall Edge in Clock Gating Mode
1 Whichever is greater.
FRAME SYNC
DRIVEN
DATA
SAMPLED
EPPI_CLK
tDFSPI
tPCLKW
tHOFSPI
tPCLK
EPPI_FS1/2
tSDRPI
tHDRPI
EPPI_D00-23
Figure 25. PPI GP Receive Mode with Internal Frame Sync Timing
Rev. 0
| Page 72 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
FRAME SYNC
DRIVEN
DATA
DRIVEN
tPCLK
DATA
DRIVEN
EPPI_CLK
tDFSPI
tPCLKW
tHOFSPI
EPPI_FS1/2
tDDTPI
tHDTPI
EPPI_D00-23
Figure 26. PPI GP Transmit Mode with Internal Frame Sync Timing
Rev. 0
| Page 73 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 43. Enhanced Parallel Peripheral Interface—External Clock
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tPCLKW
EPPI_CLKWidthforDataTransmit, FSExternal [0.5 × tSCLK0 – 0.5] or [5.5]
Data/FS Receive1
[0.5 × tSCLK0 – 0.5] or [5.5]
[0.5 × tSCLK0 – 1] or [7.5]
[tSCLK0 – 1] or [12]
ns
ns
ns
ns
EPPI_CLK Width for Data Transmit, FS Internal [0.5 × tSCLK0 – 1] or [7.5]
Data/FS Transmit1
tPCLK
EPPI_CLK Period for Data Receive, FS External [tSCLK0 – 1] or [12]
Data/FS Receive1
EPPI_CLK Period for Data Receive, FS Internal [tSCLK0 – 1] or [17]
Data/FS Transmit1
[tSCLK0 – 1] or [17]
tSFSPE
tHFSPE
tSDRPE
tHDRPE
External Frame Sync Setup Before EPPI_CLK
External Frame Sync Hold After EPPI_CLK
Receive Data Setup Before EPPI_CLK
Receive Data Hold After EPPI_CLK
2
2
ns
ns
ns
ns
3.7
2
3.7
2
3.7
3.7
Switching Characteristics
tDFSPE
tHOFSPE
tDDTPE
tHDTPE
Internal Frame Sync Delay After EPPI_CLK
20.1
20.1
15.3
15.3
ns
ns
ns
ns
Internal Frame Sync Hold After EPPI_CLK
Transmit Data Delay After EPPI_CLK
Transmit Data Hold After EPPI_CLK
2.4
2.4
2.4
2.4
1 Whichever is greater.
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
EPPI_CLK
tPCLKW
tSFSPE
tHFSPE
tPCLK
EPPI_FS1/2
tSDRPE
tHDRPE
EPPI_D00-23
Figure 27. PPI GP Receive Mode with External Frame Sync Timing
DATA DRIVEN /
FRAME SYNC SAMPLED
EPPI_CLK
tSFSPE
tHFSPE
tPCLKW
tPCLK
EPPI_FS1/2
tDDTPE
tHDTPE
EPPI_D00-23
Figure 28. PPI GP Transmit Mode with External Frame Sync Timing
Rev. 0
| Page 74 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path length differ-
ence between LP_Dx (data) and LP_CLK. Setup skew is the
maximum delay that can be introduced in LP_Dx relative to
LP_CLK:
(setup skew = tLCLKTWH min – tDLDCH – tSLDCL). Hold skew is the
maximum delay that can be introduced in LP_CLK relative to
LP_Dx: (hold skew = tLCLKTWL min – tHLDCH – tHLDCL).
Table 44. Link Ports—Receive
VDD_EXT
1.8V Nominal/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSLDCL
Data Setup Before LP_CLK Low
Data Hold After LP_CLK Low
LP_CLK Period1
LP_CLK Width Low1
LP_CLK Width High1
2
ns
ns
ns
ns
ns
tHLDCL
3
tLCLKIW
tLCLKRWL
tLCLKRWH
[tSCLK0 – 1] or [12]
[0.5 × tSCLK0 – 0.5] or [5.5]
[0.5 × tSCLK0 – 0.5] or [5.5]
Switching Characteristic
tDLALC
LP_ACK Low Delay After LP_CLK Low2
1.5 × tSCLK0 + 4
2.5 × tSCLK0 + 12
ns
1 Whichever is greater.
2 LP_ACK goes low with tDLALC relative to rise of LP_CLK after first byte, but does not go low if the receiver's link buffer is not about to fill.
tLCLKIW
tLCLKRWH
tLCLKRWL
LP_CLK
LP_D7–0
tHLDCL
tSLDCL
IN
tDLALC
LP_ACK (OUT)
Figure 29. Link Ports—Receive
Rev. 0
| Page 75 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 45. Link Ports—Transmit
VDD_EXT
1.8V Nominal/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSLACH
LP_ACK Setup Before LP_CLK Low
LP_ACK Hold After LP_CLK Low
2 × tSCLK0 + 10
0
ns
ns
tHLACH
Switching Characteristics
tDLDCH
Data Delay After LP_CLK High
Data Hold After LP_CLK High
LP_CLK Width Low
2.5
ns
ns
ns
ns
ns
tHLDCH
–1
tLCLKTWL
tLCLKTWH
tDLACLK
0.4 × tLCLK
0.4 × tLCLK
tSCLK0 + 4
0.6 × tLCLK
LP_CLK Width High
0.6 × tLCLK
LP_CLK Low Delay After LP_ACK High
(2 × tSCLK0) + tLCLK + 10
LAST BYTE
TRANSMITTED
FIRST BYTE
1
tLCLKTWH tLCLKTWL
TRANSMITTED
LP_CLK
tDLDCH
tHLDCH
LP_Dx
OUT
(DATA)
tSLACH
tHLACH
tDLACLK
LP_ACK (IN)
NOTES
The tSLACH and t
specifications apply only to the LP_ACK falling edge. If these specifications are met,
LP_CLK wouldHeLAxCtHend and the dotted LP_CLK falling edge would not occur as shown. The position of the
dotted falling edge can be calculated using the tLCLKTWH specification. tLCLKTWH Min should be used for t SLACH
and tLCLKTWH Max for tHLACH
.
Figure 30. Link Ports—Transmit
Rev. 0
| Page 76 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) serial clock
(SPT_CLK) width. In Figure 31 either the rising edge or the fall-
ing edge of SPT_CLK (external or internal) can be used as the
active sampling edge.
Table 46. Serial Ports—External Clock
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSE
Frame Sync Setup Before SPT_CLK
2
2
ns
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
tHFSE
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
2.7
2.7
ns
tSDRE
Receive Data Setup Before Receive SPT_CLK1
Receive Data Hold After SPT_CLK1
2
2
ns
ns
ns
tHDRE
tSCLKW
2.7
2.7
SPT_CLK Width for External SPT_CLK Data/FS [0.5 × tSCLK1 – 0.5] or [5.5]
Receive2
[0.5 × tSCLK1 – 0.5] or [5.5]
[0.5 × tSCLK1 – 0.5] or [8]
[tSCLK1 – 1] or [12]
SPT_CLK Width for External SPT_CLK Data/FS [0.5 × tSCLK1 – 0.5] or [8]
Transmit2
ns
ns
ns
tSPTCLK
SPT_CLK Period for External SPT_CLK Data/FS [tSCLK1 – 1] or [12]
Receive2
SPT_CLK Period for External SPT_CLK Data/FS [tSCLK1 – 1] or [17]
Transmit2
[tSCLK1 – 1] or [17]
Switching Characteristics
tDFSE
Frame Sync Delay After SPT_CLK
19.3
18.8
14.5
ns
ns
(Internally Generated Frame Sync in either
Transmit or Receive Mode)3
tHOFSE
Frame Sync Hold After SPT_CLK
(Internally Generated Frame Sync in either
Transmit or Receive Mode)3
Transmit Data Delay After Transmit SPT_CLK3
Transmit Data Hold After Transmit SPT_CLK3
2
2
2
2
tDDTE
tHDTE
14
ns
ns
1 Referenced to sample edge.
2 Whichever is greater.
3 Referenced to drive edge.
Rev. 0
| Page 77 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 47. Serial Ports—Internal Clock
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tSFSI
Frame Sync Setup Before SPT_CLK
16.8
12
(Externally Generated Frame Sync in either
ns
Transmit or Receive Mode)1
tHFSI
Frame Sync Hold After SPT_CLK
(Externally Generated Frame Sync in either
Transmit or Receive Mode)1
0
–0.5
ns
tSDRI
tHDRI
Receive Data Setup Before SPT_CLK1
Receive Data Hold After SPT_CLK1
4.8
1.5
3.4
1.5
ns
ns
Switching Characteristics
tDFSI
FrameSyncDelayAfterSPT_CLK(Internally
3.5
3.5
3.5
3.5
ns
ns
Generated Frame Sync in Transmit or
Receive Mode)2
tHOFSI
Frame Sync Hold After SPT_CLK (Internally –1.0
Generated Frame Sync in Transmit or
Receive Mode)2
Transmit Data Delay After SPT_CLK2
–1.0
tDDTI
ns
ns
ns
tHDTI
Transmit Data Hold After SPT_CLK2
–1.25
–1.25
tSCLKIW
SPT_CLK Width for Internal SPT_CLK
Data/FS Transmit3
[0.5 × tSCLK1 – 1.5] or [4.5]
[0.5 × tSCLK1 – 1.5] or [4.5]
SPT_CLK Width for Internal SPT_CLK
Data/FS Receive
[0.5 × tSCLK1 – 1.5] or [6.5]
[tSCLK1 – 1.5] or [12]
[tSCLK1 – 1.5] or [16]
[0.5 × tSCLK1 – 1.5] or [6.5]
[tSCLK1 – 1.5] or [12]
ns
ns
ns
tSPTCLK
tSPTCLK
SPT_CLK Period for Internal SPT_CLK
Data/FS Transmit3
SPT_CLK Period for Internal SPT_CLK
Data/FS Receive3
[tSCLK1 – 1.5] or [16]
1 Referenced to the sample edge.
2 Referenced to drive edge.
3 Whichever is greater.
Rev. 0
| Page 78 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPT_A/BFS
(FRAME SYNC)
SPT_A/BFS
(FRAME SYNC)
tSDRI
tHDRI
tSDRE
tHDRE
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BDx
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
SPT_A/BCLK
(SPORT CLOCK)
SPT_A/BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tSFSI
tHFSI
tHOFSE
tSFSE
tHFSE
SPT_A/BFS
(FRAME SYNC)
SPT_A/BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
tHDTE
SPT_A/BDx
(DATA CHANNEL A/B)
SPT_A/BDx
(DATA CHANNEL A/B)
Figure 31. Serial Ports
Rev. 0
| Page 79 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 48. Serial Ports—Enable and Three-State
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
1
Max
Min
1
Max
Unit
Switching Characteristics
tDDTEN
tDDTTE
tDDTIN
tDDTTI
Data Enable from External Transmit SPT_CLK1
ns
ns
ns
ns
Data Disable from External Transmit SPT_CLK1
Data Enable from Internal Transmit SPT_CLK1
Data Disable from Internal Transmit SPT_CLK1
18.8
2.8
14
–1
–1
2.8
1 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
tDDTEN
tDDTTE
SPT_A/BDx
(DATA
CHANNEL A/B)
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
tDDTIN
tDDTTI
SPT_A/BDx
(DATA
CHANNEL A/B)
Figure 32. Serial Ports—Enable and Three-State
Rev. 0
| Page 80 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
The SPT_TDV output signal becomes active in SPORT multi-
channel mode. During transmit slots (enabled with active
channel selection registers) the SPT_TDV is asserted for com-
munication with external devices.
Table 49. Serial Ports—TDV (Transmit Data Valid)
VDD_EXT
1.8V Nominal
Max
VDD_EXT
3.3V Nominal
Parameter
Min
Min
2
Max
Unit
Switching Characteristics
tDRDVEN
tDFDVEN
tDRDVIN
tDFDVIN
Data-Valid Enable Delay from Drive Edge of External Clock1
Data-Valid Disable Delay from Drive Edge of External Clock1
2
ns
ns
ns
ns
18.8
3.5
14
Data-Valid Enable Delay from Drive Edge of Internal Clock1 –1
Data-Valid Disable Delay from Drive Edge of Internal Clock1
–1
3.5
1 Referenced to drive edge.
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
EXTERNAL)
tDRDVEN
tDFDVEN
SPT_A/BTDV
DRIVE EDGE
DRIVE EDGE
SPT_CLK
(SPORT CLOCK
INTERNAL)
tDRDVIN
tDFDVIN
SPT_A/BTDV
Figure 33. Serial Ports—Transmit Data Valid Internal and External Clock
Rev. 0
| Page 81 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 50. Serial Ports—External Late Frame Sync
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Max
Parameter
Min
Min
Max
Unit
Switching Characteristics
tDDTLFSE
Data Delay from Late External Transmit Frame Sync or External
18.8
14
ns
Receive Frame Sync with MCE = 1, MFD = 01
Data Enable for MCE = 1, MFD = 01
tDDTENFS
0.5
0.5
ns
1 The tDDTLFSE and tDDTENFS parameters apply to left-justified as well as standard serial mode, and MCE = 1, MFD = 0.
DRIVE
SAMPLE
DRIVE
SPT_A/BCLK
(SPORT CLOCK)
tHFSE/I
tSFSE/I
SPT_A/BFS
(FRAME SYNC)
tDDTE/I
tDDTENFS
tHDTE/I
SPT_A/BDx
(DATA CHANNEL A/B)
1ST BIT
2ND BIT
tDDTLFSE
Figure 34. External Late Frame Sync
Rev. 0
| Page 82 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Master Timing
Table 51 and Figure 35 describe SPI port master operations.
Note that:
• In dual mode data receive the SPI_MOSI signal is also an
input.
• In dual mode data transmit the SPI_MISO signal is also an
output.
• In quad mode data receive the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also inputs.
• In quad mode data transmit the SPI_MISO, SPI_D2, and
SPI_D3 signals are also outputs.
Table 51. Serial Peripheral Interface (SPI) Port—Master Timing
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSSPIDM
tHSPIDM
Switching Characteristics
tSDSCIM
SPI_SEL low to First SPI_CLK Edge1
tSPICHM
Data Input Valid to SPI_CLK Edge (Data Input Setup) 3.2
ns
ns
SPI_CLK Sampling Edge to Data Input Invalid
1.2
[0.5 × tSCLK1 – 2] or [5]
[0.5 × tSCLK1 – 1] or [5]
[0.5 × tSCLK1 – 1] or [5]
[0.5 × tSCLK1 – 1] or [5]
[0.5 × tSCLK1 – 1] or [5]
[tSCLK1 – 1] or [12]
ns
ns
ns
ns
ns
ns
ns
n s
ns
ns
ns
SPI_CLK High Period for Data Transmit1
SPI_CLK High Period for Data Receive1
SPI_CLK Low Period for Data Transmit1
SPI_CLK Low Period for Data Receive1
SPI_CLK Period for Data Transmit1
tSPICLM
tSPICLK
SPI_CLK Period for Data Receive1
[tSCLK1 – 1] or [13.33]
2 × tSCLK1 – 1
tHDSM
Last SPI_CLK Edge to SPI_SEL High
Sequential Transfer Delay1
tSPITDM
[0.5 × tSCLK1 – 1] or [5]
tDDSPIDM
SPI_CLK Edge to Data Out Valid (Data Out Delay)
SPI_CLK Edge to Data Out Invalid (Data Out Hold)
2.6
tHDSPIDM
–1
1 Whichever is greater.
Rev. 0
| Page 83 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPI_SEL
(OUTPUT)
tSDSCIM
tSPICLM
tSPICHM
tSPICLK
tHDSM
tSPITDM
SPI_CLK
(OUTPUT)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPI_MOSI)
tSSPIDM
CPHA = 1
tHSPIDM
DATA INPUTS
(SPI_MISO)
tHDSPIDM
tDDSPIDM
DATA OUTPUTS
(SPI_MOSI)
tSSPIDM
tHSPIDM
CPHA = 0
DATA INPUTS
(SPI_MISO)
Figure 35. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. 0
| Page 84 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 52 and Figure 36 describe SPI port slave operations. Note
that:
• In dual mode data receive the SPI_MISO signal is also an
input.
• In dual mode data transmit the SPI_MOSI signal is also an
output.
• In quad mode data receive the SPI_MISO, SPI_D2, and
SPI_D3 signals are also inputs.
• In quad mode data transmit the SPI_MOSI, SPI_D2, and
SPI_D3 signals are also outputs.
Table 52. Serial Peripheral Interface (SPI) Port—Slave Timing
VDD_EXT
1.8V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSPICHS
tSPICLS
tSPICLK
SPI_CLK High Period for Data Transmit1
SPI_CLK High Period for Data Receive1
SPI_CLK Low Period for Data Transmit1
SPI_CLK Low Period for Data Receive1
SPI_CLK Period for Data Transmit1
[0.5 × tSCLK1 – 1.5] or [7.0]
[0.5 × tSCLK1 – 1.5] or [4.5]
[0.5 × tSCLK1 – 1.5] or [7.0]
[0.5 × tSCLK1 – 1.5] or [4.5]
[tSCLK1 – 1.5] or [17]
[tSCLK1 – 1.5] or [12]
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI_CLK Period for Data Receive1
tHDS
Last SPI_CLK Edge to SPI_SS Not Asserted
Sequential Transfer Delay
tSPITDS
tSDSCI
tSSPID
tHSPID
0.5 × tSPICLK – 1.5
10.5
SPI_SS Assertion to First SPI_CLK Edge
Data Input Valid to SPI_CLK Edge (Data Input Setup)
SPI_CLK Sampling Edge to Data Input Invalid
2.0
1.6
Switching Characteristics
tDSOE
SPI_SS Assertion to Data Out Active
0
0
14
ns
ns
ns
ns
tDSDHI
tDDSPID
tHDSPID
SPI_SS Deassertion to Data High Impedance
SPI_CLK Edge to Data Out Valid (Data Out Delay)
SPI_CLK Edge to Data Out Invalid (Data Out Hold)
12.5
14
0
1 Whichever is greater.
Rev. 0
| Page 85 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
SPI_SS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPI_CLK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPI_MISO)
CPHA = 1
tSSPID
tHSPID
DATA INPUTS
(SPI_MOSI)
tDSOE
tHDSPID
tDDSPID
tDSDHI
DATA OUTPUTS
(SPI_MISO)
tHSPID
CPHA = 0
tSSPID
DATA INPUTS
(SPI_MOSI)
Figure 36. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. 0
| Page 86 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—SPI_RDY Slave
Timing
Table 53. SPI Port—SPI_RDY Slave Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tDSPISCKRDYSR
tDSPISCKRDYST
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive 2.5 × tSCLK1
SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit 3.5 × tSCLK1
3.5 × tSCLK1 + 17.5 ns
4.5 × tSCLK1 + 17.5 ns
tDSPISCKRDYSR
SPI_CLK
(CPOL = 0)
CPHA = 0
SPI_CLK
(CPOL = 1)
SPI_CLK
(CPOL = 0)
CPHA = 1
SPI_CLK
(CPOL = 1)
SPI_RDY (O)
Figure 37. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Receive (FCCH = 0)
tDSPISCKRDYST
SPI_CLK
(CPOL = 1)
CPHA = 0
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
CPHA = 1
SPI_CLK
(CPOL = 0)
SPI_RDY (O)
Figure 38. SPI_RDY De-assertion from Valid Input SPI_CLK Edge in Slave Mode Transmit (FCCH = 1)
Rev. 0
| Page 87 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—Open Drain Mode
Timing
In Figure 39 and Figure 40, the outputs can be SPI_MOSI SPI_
MISO, SPI_D2, and/or SPI_D3 depending on the mode of
operation.
Table 54. SPI Port ODM Master Mode Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Switching Characteristics
tHDSPIODMM
tDDSPIODMM
SPI_CLK Edge to High Impedance from Data Out Valid
–1
0
ns
ns
SPI_CLK Edge to Data Out Valid from High Impedance
6
tHDSPIODMM
tHDSPIODMM
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMM
tDDSPIODMM
Figure 39. ODM Master
Table 55. SPI Port—ODM Slave Mode
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tHDSPIODMS
tDDSPIODMS
SPI_CLK Edge to High Impedance from Data Out Valid
SPI_CLK Edge to Data Out Valid from High Impedance
0
ns
ns
11.5
tHDSPIODMS
tHDSPIODMS
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
OUTPUT
(CPHA = 1)
OUTPUT
(CPHA = 0)
tDDSPIODMS
tDDSPIODMS
Figure 40. ODM Slave
Rev. 0
| Page 88 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Serial Peripheral Interface (SPI) Port—SPI_RDY Timing
Table 56. SPI Port—SPI_RDY Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSRDYSCKM0 Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 0
(2.5 + 1.5 × BAUD1) × tSCLK1
17.5
+
ns
tSRDYSCKM1 Minimum Setup Time for SPI_RDY De-assertion in Master
Mode Before Last SPI_CLK Edge of Valid Data Transfer to
Block Subsequent Transfer with CPHA = 1
(1.5 × BAUD1) × tSCLK1 + 17.5
ns
ns
Switching Characteristic
tSRDYSCKM Time Between Assertion of SPI_RDY by Slave and First Edge 3 × tSCLK1
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD = 0
(STOP, LEAD, LAG = 0)
4 × tSCLK1 + 17.5
Time Between Assertion of SPI_RDY by Slave and First Edge (4 + 1.5 × BAUD1) × tSCLK1
of SPI_CLK for New SPI Transfer with CPHA = 0 and BAUD ≥ 1
(STOP, LEAD, LAG = 0)
Time Between Assertion of SPI_RDY by Slave and First Edge (3 + 0.5 × BAUD1) × tSCLK1
of SPI_CLK for New SPI Transfer with CPHA = 1 (STOP, LEAD,
LAG = 0)
(5 + 1.5 × BAUD1) × tSCLK1 + ns
17.5
(4 + 0.5 × BAUD1) × tSCLK1 + ns
17.5
1 BAUD value set using the SPI_CLK.BAUD bits.
tSRDYSCKM0
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 41. SPI_RDY Setup Before SPI_CLK with CPHA = 0
tSRDYSCKM1
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 42. SPI_RDY Setup Before SPI_CLK with CPHA = 1
Rev. 0
| Page 89 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
tSRDYSCKM
SPI_RDY
SPI_CLK
(CPOL = 0)
SPI_CLK
(CPOL = 1)
Figure 43. SPI_CLK Switching Diagram after SPI_RDY Assertion, CPHA = x
Rev. 0
| Page 90 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
General-Purpose Port Timing
Table 57 and Figure 44 describe general-purpose
port operations.
Table 57. General-Purpose Port Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
2 × tSCLK0
ns
tWFI
GPIO INPUT
Figure 44. General-Purpose Port Timing
Timer Cycle Timing
Table 58 and Figure 45 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (fSCLK0/4) MHz. The Period Value value is the timer
period assigned in the TMx_TMRn_PER register and can range
from 2 to 232 – 1.
Table 58. Timer Cycle Timing
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tWL
Timer Pulse Width Input Low (Measured In 2 × tSCLK0
SCLK0 Cycles)1
2 × tSCLK0
2 × tSCLK0
ns
ns
tWH
Timer Pulse Width Input High (Measured In 2 × tSCLK0
SCLK0 Cycles)1
Switching Characteristics
tHTO Timer Pulse Width Output (Measured In
SCLK0 Cycles)
tSCLK0 × Period
Value
tSCLK0 × Period
Value
tSCLK0 × Period
Value
tSCLK0 × Period
Value
ns
1 The minimum pulse widths apply for TMx signals in width capture and external clock modes.
TMR OUTPUT
tHTO
TMR INPUT
tWH, tWL
Figure 45. Timer Cycle Timing
Rev. 0
| Page 91 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Up/Down Counter/Rotary Encoder Timing
Table 59. Up/Down Counter/Rotary Encoder Timing
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirement
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width 2 × tSCLK0
2 × tSCLK0
ns
CNT_UD
CNT_DG
CNT_ZM
tWCOUNT
Figure 46. Up/Down Counter/Rotary Encoder Timing
Pulse Width Modulator (PWM) Timing
Table 60 and Figure 47 describe PWM operations.
Table 60. PWM Timing
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirement
tES
Switching Characteristics
tDODIS
Output Inactive (OFF) After Trip Input1
tDOE
Output Delay After External Sync1, 2
External Sync Pulse Width
2 × tSCLK0
ns
15
ns
ns
2 × tSCLK0 + 5.5
5 × tSCLK0 + 14
1 PWM outputs are: PWMx_AH, PWMx_AL, PWMx_BH, PWMx_BL, PWMx_CH, and PWMx_CL.
2 When the external sync signal is synchronous to the peripheral clock, it takes fewer clock cycles for the output to appear compared to when the external sync signal is
asynchronous to the peripheral clock. For more information, see the ADSP-BF60x Blackfin Processor Hardware Reference.
PWM_SYNC
(AS INPUT)
tES
tDOE
OUTPUT
tDODIS
PWM_TRIP
Figure 47. PWM Timing
Rev. 0
| Page 92 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADC Controller Module (ACM) Timing
Table 61 and Figure 48 describe ACM operations.
f
SCLK1
f
= --------------------------
Note that the ACM clock (ACMx_CLK) frequency in MHz is
set by the following equation where CKDIV is a field in the
ACM_TC0 register and ranges from 1 to 255. Setup cycles (SC)
in Table 61 is also a field in the ACM_TC0 register and ranges
from 0 to 4095. Hold Cycles (HC) is a field in the ACM_TC1
register that ranges from 0 to 15.
ACLK
CKDIV + 1
1
t
= -----------------
ACLK
f
ACLK
Table 61. ACM Timing
VDD_EXT
1.8 V/3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
tSDR
tHDR
SPORT DRxPRI/DRxSEC Setup Before ACMx_CLK
SPORT DRxPRI/DRxSEC Hold After ACMx_CLK
3
ns
ns
1.5
Switching Characteristics
tSCTLCS
tHCTLCS
tACLKW
tACLK
ACM Controls (ACMx_A[4:0]) Setup Before Assertion of CS
(SC + 1) × tSCLK1 – 3
HC × tACLK + 0.1
ns
ns
ns
ns
ns
ns
ACM Control (ACMx_A[4:0]) Hold After De-assertion of CS
ACM Clock Pulse Width
ACM Clock Period1
(tSCLK1/2) × (CLKDIV + 1) – 1.5
[tSCLK1 × (CKDIV + 1)] or [16]
–0.1
tHCSACLK
tSCSACLK
CS Hold to ACMx_CLK Edge
CS Setup to ACMx_CLK Edge
tACLK – 3.5
1 Whichever is greater.
CS
CSPOL = 1/0
tSCSACLK
ACM_CLK
CLKPOL = 1/0
tACLK
tHCSACLK
ACM
CONTROLS
tSDR
tHDR
tHCTLCS
tSCTLCS
DRxPRI/
DRxSEC
Figure 48. ACM Timing
Rev. 0
| Page 93 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
The UART ports receive and transmit operations are described
in the ADSP-BF60x Hardware Reference Manual.
CAN Interface
The CAN interface timing is described in the ADSP-BF60x
Hardware Reference Manual.
Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing
Table 62 describes the USB On-The-Go receive and transmit
operations.
Table 62. USB On-The-Go—Receive and Transmit Timing
VDD_USB
3.3V Nominal
Parameter
Min
Max
Unit
Timing Requirements
fUSBS
fsUSB
USB_XI Frequency
48
48
MHz
ppm
USB_XI Clock Frequency Stability
–50
+50
Rev. 0
| Page 94 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
RSI Controller Timing
Table 63 and Figure 49 describe RSI controller timing.
Table 63. RSI Controller Timing
VDD_EXT
1.8V Nominal
Max
VDD_EXT
3.3V Nominal
Parameter
Min
Min
Max
Unit
Timing Requirements
tISU
tIH
Input Setup Time
Input Hold Time
11
2
9.6
2
ns
ns
Switching Characteristics
fPP
Clock Frequency Data Transfer Mode1
41.67
41.67
MHz
ns
tWL
Clock Low Time
8
8
8
8
tWH
Clock High Time
ns
tTLH
Clock Rise Time
3
3
ns
tTHL
Clock Fall Time
3
3
ns
tODLY
Output Delay Time During Data Transfer Mode
Output Hold Time
2.5
2.5
ns
tOH
–1
–1
ns
1 tPP = 1/fPP
VOH (MIN)
tPP
RSI_CLK
tTHL
tTLH
tISU
tIH
VOL (MAX)
tWL
tWH
INPUT
tODLY
tOH
OUTPUT
NOTES:
1 INPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
2 OUTPUT INCLUDES RSI_Dx AND RSI_CMD SIGNALS.
Figure 49. RSI Controller Timing
Rev. 0
| Page 95 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
10/100 Ethernet MAC Controller Timing
Table 64 through Table 66 and Figure 50 through Figure 52
describe the 10/100 Ethernet MAC Controller operations.
Table 64. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
VDD_EXT
1.8V/3.3V Nominal
Parameter1
Min
Max
Unit
Timing Requirements
tREFCLKF
tREFCLKW
tREFCLKIS
tREFCLKIH
ETHx_REFCLK Frequency (fSCLK0 = SCLK0 Frequency)
None
50 + 1%
MHz
ns
ETHx_REFCLK Width (tREFCLK = ETHx_REFCLK Period)
tREFCLK × 35%
tREFCLK × 65%
Rx Input Valid to RMII ETHx_REFCLK Rising Edge (Data In Setup)
RMII ETHx_REFCLK Rising Edge to Rx Input Invalid (Data In Hold)
4
ns
2.2
ns
1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
tREFCLK
RMII_REF_CLK
tREFCLKW
ETHx_RXD1–0
ETHx_CRS
ETHx_RXERR
tREFCLKIS tREFCLKIH
Figure 50. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 65. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
VDD_EXT
1.8V/3.3V Nominal
Parameter1
Min
Max
Unit
Switching Characteristics
tREFCLKOV
tREFCLKOH
RMII ETHx_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)
RMII ETHx_REFCLK Rising Edge to Transmit Output Invalid (Data Out Hold)
14
ns
ns
2
1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
tREFCLK
RMII_REF_CLK
tREFCLKOH
ETHx_TXD1–0
ETHx_TXEN
tREFCLKOV
Figure 51. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Rev. 0
| Page 96 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Table 66. 10/100 Ethernet MAC Controller Timing: RMII Station Management
VDD_EXT
1.8V/3.3V Nominal
Parameter1
Min
Max
Unit
Timing Requirements
tMDIOS
tMDCIH
Switching Characteristics
tMDCOV ETHx_MDC Falling Edge to ETHx_MDIO Output Valid
tMDCOH ETHx_MDC Falling Edge to ETHx_MDIO Output Invalid (Hold)
ETHx_MDIO Input Valid to ETHx_MDC Rising Edge (Setup)
14
0
ns
ns
ETHx_MDC Rising Edge to ETHx_MDIO Input Invalid (Hold)
tSCLK0 + 5
ns
ns
tSCLK0 –1
1 ETHx_MDC/ETHx_MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. ETHx_MDC is an output clock whose minimum period is
programmable as a multiple of the system clock SCLK0. ETHx_MDIO is a bidirectional data line.
ETHx_MDC
(OUTPUT)
tMDCOH
ETHx_MDIO
(OUTPUT)
tMDCOV
ETHx_MDIO
(INPUT)
tMDIOS
tMDCIH
Figure 52. 10/100 Ethernet MAC Controller Timing: RMII Station Management
Rev. 0
| Page 97 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
JTAG Test And Emulation Port Timing
Table 67 and Figure 53 describe JTAG port operations.
Table 67. JTAG Port Timing
VDD_EXT
VDD_EXT
3.3V Nominal
1.8V Nominal
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
tTCK
JTG_TCK Period
20
4
20
4
ns
tSTAP
tHTAP
tSSYS
tHSYS
tTRSTW
JTG_TDI, JTG_TMS Setup Before JTG_TCK High
JTG_TDI, JTG_TMS Hold After JTG_TCK High
System Inputs Setup Before JTG_TCK High1
System Inputs Hold After JTG_TCK High1
ns
4
4
ns
12
5
12
5
ns
ns
JTG_TRST Pulse Width (measured in JTG_TCK cycles)2
4
4
TCK
Switching Characteristics
tDTDO JTG_TDO Delay from JTG_TCK Low
tDSYS
System Outputs Delay After JTG_TCK Low3
18
22
13.5
17
ns
ns
1 System Inputs = DMC0_DQ00–15, DMC0_LDQS, DMC0_LDQS, DMC0_UDQS, DMC0_UDQS, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_15–0, PG_15–0,
SMC0_ARDY_NORWT, SMC0_BR, SMC0_D15–0, SYS_BMODE0–2, SYS_HWRST, SYS_FAULT, SYS_FAULT, SYS_NMI_RESOUT, SYS_PWRGD, TWI0_SCL, TWI0_
SDA, TWI1_SCL, TWI1_SDA.
2 50 MHz Maximum.
3 System Outputs = DMC0_A00–13, DMC0_BA0–2, DMC0_CAS, DMC0_CK, DMC0_CK, DMC0_CKE, DMC0_CS0, DMC0_DQ00–15, DMC0_LDM, DMC0_LDQS,
DMC0_LDQS, DMC0_ODT, DMC0_RAS, DMC0_UDM, DMC0_UDQS, DMC0_UDQS, DMC0_WE, JTG_EMU, PA_15–0, PB_15–0, PC_15–0, PD_15–0, PE_15–0, PF_
15–0, PG_15–0, SMC0_AMS0, SMC0_AOE_NORDV, SMC0_ARE, SMC0_AWE, SMC0_A01, SMC0_A02, SMC0_D15–0, SYS_CLKOUT, SYS_FAULT, SYS_FAULT,
SYS_NMI_RESOUT, TWI0_SCL, TWI0_SDA, TWI1_SCL, TWI1_SDA.
tTCK
JTG_TCK
tSTAP
tHTAP
JTG_TMS
JTG_TDI
tDTDO
JTG_TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 53. JTAG Port Timing
Rev. 0
| Page 98 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
OUTPUT DRIVE CURRENTS
Figure 54 through Figure 59 show typical current-voltage char-
acteristics for the output drivers of the ADSP-BF60x Blackfin
processors. The curves represent the current drive capability of
the output drivers as a function of output voltage.
100
80
40
VDD_EXT = 1.9V @ – 40
VDD_EXT = 1.8V @ 25
DD_EXT = 1.7V @ 125°C
°C
VDD_DMC = 1.9V @ – 40
VDD_DMC = 1.8V @ 25
DD_DMC = 1.7V @ 125°C
°C
°
C
°
C
V
V
60
20
0
40
V
OH
V
OH
20
0
– 20
– 40
– 60
– 80
V
OL
V
OL
– 20
– 40
0
0.5
1.0
1.5
2.0
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 54. Driver Type A Current (1.8 V VDD_EXT
)
Figure 56. Driver Type B Current (1.8 V VDD_DMC
)
80
60
100
80
VDD_EXT = 3.465V @ – 40
VDD_EXT = 3.30V @ 25
DD_EXT = 3.135V @ 105°C
°C
VDD_DMC = 1.9V @ – 40
°C
°C
VDD_DMC = 1.8V @ 25
°C
V
60
VDD_DMC = 1.7V @ 125°C
40
V
40
OH
V
20
OH
20
0
0
– 20
– 40
– 60
– 80
– 20
– 40
– 60
– 80
V
OL
V
OL
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
SOURCE VOLTAGE (V)
Figure 55. Driver Type A Current (3.3 V VDD_EXT
)
Figure 57. Driver Type C Current (1.8 V VDD_DMC
)
Rev. 0
|
Page 99 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Capacitive Loading
0
VDD_EXT = 1.9V @ – 40
VDD_EXT = 1.8V @ 25
DD_EXT = 1.7V @ 125°C
°C
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all pins (see Figure 60). VLOAD is equal
to (VDD_EXT)/2.
°
C
V
– 5
TESTER PIN ELECTRONICS
– 10
50:
V
LOAD
T1
DUT
OUTPUT
V
OL
45:
70:
– 15
– 20
ZO = 50:ꢀ(impedance)
TD = 4.04 ꢀ 1.18 ns
50:
0.5pF
4pF
2pF
0
0.5
1.0
1.5
2.0
SOURCE VOLTAGE (V)
400:
Figure 58. Driver Type D Current (1.8 V VDD_EXT
)
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED.THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
0
– 20
– 40
– 60
VDD_EXT = 3.465V @ – 40
VDD_EXT = 3.30V @ 25
DD_EXT = 3.135V @ 125°C
°C
°
C
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
Figure 60. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
The graphs of Figure 61 through Figure 63 show how output
rise and fall times vary with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out-
side the ranges shown.
V
OL
0
1.0
2.0
3.0
4.0
SOURCE VOLTAGE (V)
16
tRISE
Figure 59. Driver Type D Current (3.3 V VDD_EXT
)
14
tFALL
12
10
8
6
4
2
tFALL = 1.8V @ 25
°C
tRISE = 1.8V @ 25
200
°C
0
0
50
150
250
100
LOAD CAPACITANCE (pF)
Figure 61. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_EXT = 1.8 V)
Rev. 0
| Page 100 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ENVIRONMENTAL CONDITIONS
16
14
To determine the junction temperature on the application
printed circuit board use:
tRISE
12
10
8
tFALL
TJ = TCASE + JT PD
where:
TJ = Junction temperature (°C)
6
4
T
CASE = Case temperature (°C) measured by customer at top
center of package.
JT = From Table 68
2
0
tFALL = 3.3V @ 25
°
C
PD = Power dissipation (see Total Internal Power Dissipation on
Page 56 for the method to calculate PD)
tRISE = 3.3V @ 25
200
°
C
0
50
150
250
100
LOAD CAPACITANCE (pF)
Table 68. Thermal Characteristics
Figure 62. Driver Type A Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_EXT = 3.3 V)
Parameter Condition
Typical Unit
JA
0 linear m/s air flow
16.7
14.6
13.9
4.41
0.11
0.24
0.25
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1.4
JMA
JMA
JC
JT
JT
JT
1 linear m/s air flow
2 linear m/s air flow
tRISE DS = 10
1.2
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
1.0
tFALL DS = 10
0.8
tRISE DS = 00
0.6
Values of JA are provided for package comparison and printed
circuit board design considerations. JA can be used for a first
order approximation of TJ by the equation:
tFALL DS = 00
0.4
0.2
TJ = TA + JA PD
tFALL = 1.8V @ 25
tRISE = 1.8V @ 25
25 30
LOAD CAPACITANCE (pF)
°
C
°C
0
0
5
10
15
20
35
where:
TA = Ambient temperature (°C)
Figure 63. Driver Type B & C Typical Rise and Fall Times (10%-90%) vs. Load
Capacitance (VDD_DMC = 1.8 V)
Values of JC are provided for package comparison and printed
circuit board design considerations when an external heat sink
is required.
In Table 68, airflow measurements comply with JEDEC stan-
dards JESD51-2 and JESD51-6. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Rev. 0
| Page 101 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Thermal Diode
The processor incorporates a thermal diode to monitor the die
temperature. The thermal diode is a grounded collector, PNP
Bipolar Junction Transistor (BJT). The SYS_TDA ball is con-
nected to the emitter and the SYS_TDK ball is connected to the
base of the transistor. These balls can be used by an external
temperature sensor (such as the ADM 1021A or the LM86 or
others) to read the die temperature of the chip.
where:
nQ = multiplication factor close to 1, depending on process
variations
k = Boltzmann’s constant
T = temperature (°Kelvin)
q = charge of the electron
N = ratio of the two currents
The technique used by the external temperature sensor is to
measure the change in VBE when the thermal diode is operated
at two different currents. This is shown in the following
equation:
The two currents are usually in the range of 10 micro Amperes
to 300 micro Amperes for the common temperature sensor
chips available.
kT
q
VBE= n
In(N)
-----
Q
Table 69 contains the thermal diode specifications using the
transistor model. Note that Measured Ideality Factor already
takes into effect variations in beta (Β).
Table 69. Thermal Diode Parameters—Transistor Model
Symbol
Parameter
Min
10
Typ
Max
300
300
Unit
A
A
1
IFW
Forward Bias Current
Emitter Current
Transistor Ideality
Series Resistance
IE
10
2, 3
nQ
1.006
2.8
2, 4
RT
1 Analog Devices does not recommend operation of the thermal diode under reverse bias.
2 Not 100% tested. Specified by design characterization.
3 The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified by the diode equation: IC = IS × (exp(qVBE/nQkT– 1), where IS = saturation current,
q = electrical charge, VBE = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4 The series resistance (RT) can be used for more accurate readings as needed.
Rev. 0
| Page 102 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
ADSP-BF60x 349-BALL CSP_BGA BALL ASSIGNMENTS
The 349-Ball CSP_BGA Ball Assignment (Numerical by Ball
Number) table lists the CSP_BGA package by ball number for
the ADSP-BF609.
The 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin
Name) table lists the CSP_BGA package by signal.
349-BALL CSP_BGA BALL ASSIGNMENT (NUMERICAL BY BALL NUMBER)
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
GND
B19
B20
B21
B22
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D01
D02
D03
D11
D12
D20
D21
D22
E01
E02
E03
E05
E20
E21
SMC0_D13
SMC0_D05
GND
E22
F01
F02
F03
F06
F07
F08
F09
F10
F11
F12
F13
F14
F15
F16
F17
F20
F21
F22
G01
G02
G03
G06
G07
G08
G09
G10
G11
G12
G13
G14
DMC0_DQ13
SYS_FAULT
SYS_FAULT
SYS_NMI_RESOUT
VDD_EXT
H06
H07
H16
H17
H20
H21
H22
J01
J02
J03
J06
J09
J10
J11
J12
J13
J14
J17
J20
J21
J22
K01
K02
K03
K06
K08
K09
K10
K11
K12
K13
K14
K15
K17
K20
K21
K22
L01
L02
L03
VDD_EXT
USB0_DM
USB0_DP
PB_10
VDD_EXT
VDD_DMC
VDD_DMC
DMC0_RAS
DMC0_DQ09
DMC0_DQ14
GND
SMC0_AOE_NORDV
USB0_CLKIN
USB0_VBC
GND
PB_07
PA_14
VDD_INT
PA_12
VDD_INT
PA_10
PB_12
VDD_INT
PA_08
PB_09
VDD_INT
SYS_PWRGD
SYS_BMODE0
VDD_EXT
PA_06
PB_06
VDD_EXT
PA_04
PB_05
VDD_EXT
PA_02
PB_04
VDD_INT
GND
PA_00
PB_03
VDD_INT
GND
SMC0_A01
SMC0_D00
SMC0_AMS0
SMC0_D03
SMC0_D04
SMC0_D07
SMC0_D10
SMC0_AWE
GND
PB_02
VDD_INT
GND
PB_01
VDD_INT
GND
PB_00
VDD_DMC
GND
SMC0_BR
SMC0_D06
SMC0_D12
SMC0_ARE
SMC0_D08
SMC0_D11
SMC0_D14
GND
DMC0_CS0
DMC0_DQ15
DMC0_DQ08
GND
GND
VDD_DMC
DMC0_ODT
DMC0_DQ12
DMC0_DQ11
PC_00
SYS_HWRST
SYS_BMODE2
VDD_EXT
USB0_VBUS
GND
SYS_EXTWAKE
PB_13
VDD_EXT
USB0_ID
PB_11
TWI1_SCL
TWI0_SCL
JTG_TDI
JTG_TDO
JTG_TCK
VDD_EXT
VDD_INT
VDD_EXT
VDD_INT
GND
PB_08
VDD_EXT
GND
PA_15
VDD_EXT
GND
PA_13
VDD_EXT
GND
PA_11
VDD_EXT
GND
PA_09
GND
VDD_INT
GND
PA_07
SMC0_ARDY_NORWT G15
VDD_INT
GND
PA_05
TWI1_SDA
TWI0_SDA
JTG_TRST
JTG_EMU
JTG_TMS
G16
G17
G20
G21
G22
H01
H02
H03
VDD_DMC
GND
PA_03
VDD_DMC
VDD_DMC
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
PC_02
PA_01
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
SYS_CLKIN
SYS_XTAL
SYS_BMODE1
SMC0_A02
SMC0_D01
SMC0_D15
SMC0_D09
SMC0_D02
VDD_USB
DMC0_CAS
DMC0_DQ10
PC_01
PB_14
Rev. 0
|
Page 103 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
L04
VDD_EXT
VDD_EXT
GND
N22
P01
P02
P03
P06
P09
P10
P11
P12
P13
P14
P17
P20
P21
P22
R01
R02
R03
R06
R07
R16
R17
R20
R21
R22
T01
T02
T03
T06
T07
T08
T09
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
U01
U02
U03
U06
U07
DMC0_DQ03
PC_08
U08
U09
U10
U11
U12
U13
U14
U15
U16
U17
U20
U21
U22
V01
V02
V03
V20
V21
V22
W01
W02
W03
W11
W12
W20
W21
W22
Y01
Y02
Y03
Y04
Y05
Y06
Y07
Y08
Y09
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
VDD_INT
Y22
DMC0_A02
PD_11
GND
L06
VDD_INT
AA01
AA02
AA03
AA04
AA05
AA06
AA07
AA08
AA09
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB01
AB02
AB03
AB04
AB05
AB06
AB07
AB08
AB09
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
L08
PC_07
VDD_INT
L09
GND
PD_06
VDD_EXT
PD_13
PE_00
PE_03
PF_14
PF_12
PF_10
PF_08
PF_06
PF_04
PF_02
PF_00
PG_00
PE_15
PE_14
PG_05
PG_08
PG_07
PG_13
GND
L10
GND
VDD_EXT
VDD_EXT
L11
GND
GND
VDD_INT
L12
GND
GND
VDD_INT
L13
GND
GND
VDD_INT
L14
GND
GND
VDD_INT
L15
GND
GND
VDD_DMC
DMC0_A09
DMC0_A05
DMC0_A01
PD_00
L17
VDD_DMC
VREF_DMC
DMC0_CK
DMC0_DQ06
DMC0_DQ07
PC_04
PC_03
PB_15
GND
GND
L19
VDD_DMC
DMC0_CKE
DMC0_DQ02
DMC0_DQ05
PC_10
L20
L21
L22
PC_15
M01
M02
M03
M04
M06
M08
M09
M10
M11
M12
M13
M14
M15
M17
M19
M20
M21
M22
N01
N02
N03
N06
N08
N09
N10
N11
N12
N13
N14
N15
N17
N20
N21
PD_10
PC_09
DMC0_BA1
DMC0_A13
DMC0_A11
PD_04
PD_07
VDD_EXT
VDD_EXT
GND
VDD_EXT
VDD_DMC
VDD_DMC
DMC0_BA2
DMC0_BA0
DMC0_A10
PC_12
PD_01
GND
PD_12
GND
GND
GND
GND
VDD_TD
GND
GND
DMC0_A04
DMC0_A06
DMC0_A08
PD_03
PD_05
PD_14
PE_01
PE_04
PF_15
PF_13
PF_11
PF_09
PF_07
PF_05
PF_03
PF_01
PE_13
PG_03
PG_06
PG_02
PG_12
PG_14
PG_15
PG_10
GND
GND
GND
PC_11
GND
PD_08
VDD_DMC
GND
VDD_EXT
PD_02
VDD_EXT
GND
DMC0_CK
DMC0_DQ00
DMC0_DQ01
PC_06
PC_05
SYS_CLKOUT
VDD_EXT
GND
VDD_INT
PD_15
VDD_INT
PE_02
VDD_EXT
PE_05
VDD_EXT
PE_06
VDD_EXT
PE_07
VDD_EXT
PE_08
VDD_INT
PE_09
VDD_INT
SYS_TDK
SYS_TDA
PE_12
GND
VDD_DMC
VDD_DMC
DMC0_A03
DMC0_A07
DMC0_A12
PC_14
GND
GND
PE_10
GND
PE_11
GND
PG_09
GND
PG_01
GND
PC_13
PG_04
VDD_DMC
DMC0_WE
DMC0_DQ04
PD_09
PG_11
VDD_EXT
GND
VDD_INT
DMC0_A00
Rev. 0
|
Page 104 of 112
|
June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA BALL ASSIGNMENT (ALPHABETICAL BY PIN NAME)
The 349-Ball CSP_BGA Ball Assignment (Numerical by Ball
Number) table lists the CSP_BGA package by ball number for
the ADSP-BF609.
The 349-Ball CSP_BGA Ball Assignment (Alphabetical by Pin
Name) table lists the CSP_BGA package by signal.
Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No.
C06
A05
B05
DMC0_A00
DMC0_A01
DMC0_A02
DMC0_A03
DMC0_A04
DMC0_A05
DMC0_A06
DMC0_A07
DMC0_A08
DMC0_A09
DMC0_A10
DMC0_A11
DMC0_A12
DMC0_A13
DMC0_BA0
DMC0_BA1
DMC0_BA2
DMC0_CAS
DMC0_CK
Y21
U22
Y22
T20
W20
U21
W21
T21
W22
U20
R22
V22
T22
V21
R21
V20
R20
E20
M20
P20
L20
F20
M21
M22
P21
N22
N21
P22
L21
L22
F22
H21
E21
J22
DMC0_WE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N20
A01
A22
AA02
AA21
AA22
AB01
AB22
B21
C20
D12
G01
J01
GND
N09
N10
N11
N12
N13
N14
N15
P09
P10
P11
P12
P13
P14
W11
Y03
Y20
C03
B02
E02
D03
D01
D02
E03
E01
A13
B13
A12
B12
A11
B11
A10
B10
A09
B09
A08
B08
A07
B07
A06
B06
C12
C11
C10
C09
C08
C07
PB_06
PB_07
PB_08
PB_09
PB_10
PB_11
PB_12
PB_13
PB_14
PB_15
PC_00
PC_01
PC_02
PC_03
PC_04
PC_05
PC_06
PC_07
PC_08
PC_09
PC_10
PC_11
PC_12
PC_13
PC_14
PC_15
PD_00
PD_01
PD_02
PD_03
PD_04
PD_05
PD_06
PD_07
PD_08
PD_09
PD_10
PD_11
PD_12
PD_13
PD_14
PD_15
PE_00
PE_01
PE_02
PE_03
GND
GND
GND
C05
A04
B04
GND
GND
GND
C04
K03
GND
GND
L03
GND
M03
K01
GND
GND
L02
GND
L01
J09
GND
M02
M01
N02
N01
P02
J10
GND
J11
GND
J12
GND
J13
GND
J14
JTG_EMU
JTG_TCK
JTG_TDI
JTG_TDO
JTG_TMS
JTG_TRST
PA_00
PA_01
PA_02
PA_03
PA_04
PA_05
PA_06
PA_07
PA_08
PA_09
PA_10
PA_11
PA_12
PA_13
PA_14
PA_15
PB_00
PB_01
PB_02
PB_03
PB_04
PB_05
P01
DMC0_CKE
DMC0_CK
K08
K09
K10
K11
K12
K13
K14
K15
L08
R02
R01
DMC0_CS0
DMC0_DQ00
DMC0_DQ01
DMC0_DQ02
DMC0_DQ03
DMC0_DQ04
DMC0_DQ05
DMC0_DQ06
DMC0_DQ07
DMC0_DQ08
DMC0_DQ09
DMC0_DQ10
DMC0_DQ11
DMC0_DQ12
DMC0_DQ13
DMC0_DQ14
DMC0_DQ15
DMC0_LDM
DMC0_LDQS
DMC0_LDQS
DMC0_ODT
DMC0_RAS
DMC0_UDM
DMC0_UDQS
DMC0_UDQS
T02
T01
U02
U01
V02
V01
W02
Y02
L09
L10
Y01
L11
W01
AB02
P03
L12
L13
L14
R03
J21
L15
T03
E22
H22
F21
K20
K22
K21
J20
M04
M08
M09
M10
M11
M12
M13
M14
M15
M19
N08
U03
V03
AA01
W03
AA03
AB03
Y04
H20
G20
G21
G22
AA04
AB04
Y05
AA05
Rev. 0
| Page 105 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
Pin Name
PE_04
Ball No. Pin Name
Ball No. Pin Name
Ball No. Pin Name
Ball No.
T08
AB05
Y06
SMC0_AWE
SMC0_BR
A21
C13
A15
B15
B18
A17
A18
B20
C14
A19
C17
B17
A20
C18
C15
B19
C19
B16
J03
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_DMC
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_EXT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
M17
N17
P17
R16
R17
T16
T17
U17
D11
F06
F11
F12
G06
G07
G10
G11
G12
G13
H06
H07
J06
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_INT
VDD_TD
PE_05
T09
PE_06
Y07
SMC0_D00
SMC0_D01
SMC0_D02
SMC0_D03
SMC0_D04
SMC0_D05
SMC0_D06
SMC0_D07
SMC0_D08
SMC0_D09
SMC0_D10
SMC0_D11
SMC0_D12
SMC0_D13
SMC0_D14
SMC0_D15
SYS_BMODE0
SYS_BMODE1
SYS_BMODE2
SYS_CLKIN
SYS_CLKOUT
SYS_EXTWAKE
SYS_FAULT
SYS_FAULT
SYS_NMI_RESOUT
SYS_PWRGD
SYS_HWRST
SYS_TDA
T14
PE_07
Y08
T15
PE_08
Y09
U07
U08
U09
U10
U13
U14
U15
U16
W12
E05
PE_09
Y10
PE_10
Y14
PE_11
Y15
PE_12
Y13
PE_13
AB14
AA16
AA15
AA13
AB13
AA12
AB12
AA11
AB11
AA10
AB10
AA09
AB09
AA08
AB08
AA07
AB07
AA06
AB06
AA14
Y17
PE_14
PE_15
PF_00
PF_01
VDD_USB
VREF_DMC
PF_02
L19
PF_03
PF_04
PF_05
PF_06
PF_07
H03
G03
H01
N03
K02
F02
F01
F03
J02
PF_08
PF_09
K06
L04
L06
M06
N06
P06
R06
R07
T06
T07
T10
T11
T12
T13
U06
U11
U12
F07
F08
F09
F10
F13
F14
F15
F16
G08
G09
G14
G15
PF_10
PF_11
PF_12
PF_13
PF_14
PF_15
PG_00
PG_01
PG_02
PG_03
PG_04
PG_05
PG_06
PG_07
PG_08
PG_09
PG_10
PG_11
PG_12
PG_13
PG_14
PG_15
SMC0_A01
SMC0_A02
SMC0_AMS0
SMC0_AOE_NORDV
G02
Y12
Y11
H02
C22
D22
C21
D21
C01
A02
A03
B03
C02
B01
F17
G16
G17
H16
H17
J17
AB17
AB15
Y18
SYS_TDK
SYS_XTAL
TWI0_SCL
TWI0_SDA
TWI1_SCL
TWI1_SDA
USB0_CLKIN
USB0_DM
USB0_DP
AA17
AB16
AA19
AA18
Y16
AB21
Y19
USB0_ID
AB18
AA20
AB19
AB20
A14
USB0_VBC
USB0_VBUS
VDD_DMC
VDD_DMC
VDD_DMC
B14
VDD_DMC
A16
VDD_DMC
B22
VDD_DMC
SMC0_ARDY_NORWT D20
SMC0_ARE C16
VDD_DMC
K17
L17
VDD_DMC
Rev. 0
| Page 106 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
349-BALL CSP_BGA BALL CONFIGURATION
Figure 64 shows an overview of signal placement on the 349-ball
CSP_BGA package.
TOP VIEW
2
4
6
8
10 12 14 16 18 20 22
9 11 13 15 17 19 21
A1 BALL
PAD CORNER
1
3
5
7
A
C
E
G
J
B
D
F
U
D
D
D
D
D
D
D
D
D
D
D
D
D
D
H
K
M
P
T
L
GND
N
R
U
W
I/O SIGNALS
V
D
D
DD_EXT
V
DD_INT
V
Y
T
D
V
DD_DMC
T
AA
AB
V
DD_TD
U
V
DD_USB
BOTTOM VIEW
A1 BALL
PAD CORNER
22 20 18 16 14 12 10
21 19 17 15 13 11
8
6
4
2
9
7
5
3
1
A
C
B
D
F
U
E
D
D
D
D
D
D
D
D
D
D
D
D
D
D
G
J
H
K
M
P
T
L
N
D
D
R
U
V
Y
T
W
AA
AB
Figure 64. 349-Ball CSP_BGA Ball Configuration
Rev. 0
| Page 107 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
OUTLINE DIMENSIONS
Dimensions for the 19 mm 19 mm CSP_BGA package in
Figure 65 are shown in millimeters.
19.10
19.00 SQ
18.90
A1 BALL
CORNER
22 20 18 16 14 12 10
8
6
4
2
A1 BALL
CORNER
21 19 17 15 13 11
9
7
5
3
1
A
C
E
G
J
B
D
F
16.80
H
K
M
P
T
BSC SQ
L
N
R
U
W
0.80
BSC
V
Y
AB
AA
TOP VIEW
DETAIL A
BOTTOM VIEW
DETAIL A
1.10 REF
1.50
1.36
1.21
1.11
1.01
0.91
0.35 NOM
0.30 MIN
0.50
0.45
0.40
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.
Figure 65. 349-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-349-1)
Dimensions shown in millimeters
SURFACE-MOUNT DESIGN
Table 70 is provided as an aid to PCB design. For industry-stan-
dard design recommendations, refer to IPC-7351, Generic
Requirements for Surface-Mount Design and Land Pattern
Standard.
Table 70. BGA Data for Use with Surface-Mount Design
Package
Package
Package
Package
Ball Attach Type
Solder Mask Opening
Ball Pad Size
BC-349-1
Solder Mask Defined
0.4 mm Diameter
0.5 mm Diameter
Rev. 0
| Page 108 of 112 | June 2013
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609
AUTOMOTIVE PRODUCTS
Some models are available with controlled manufacturing to
support the quality and reliability requirements of automotive
applications. Note that these automotive models may have spec-
ifications that differ from the commercial models and designers
should review the product specifications section of this data
sheet carefully. Contact your local ADI account representative
for specific product ordering information and to obtain the spe-
cific Automotive Reliability reports for these models.
ORDERING GUIDE
Temperature
Package
Option
Model
Max. Core Clock Range1
Package Description
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
349-Ball CSP_BGA
ADSP-BF606KBCZ-4
ADSP-BF606BBCZ-4
ADSP-BF607KBCZ-5
ADSP-BF607BBCZ-5
ADSP-BF608KBCZ-5
ADSP-BF608BBCZ-5
ADSP-BF609KBCZ-5
ADSP-BF609BBCZ-5
400 MHz
400 MHz
500 MHz
500 MHz
500 MHz
500 MHz
500 MHz
500 MHz
0°C to +70°C
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
BC-349-1
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see Operating Conditions on Page 52 for the junction temperature
(TJ) specification which is the only temperature specification.
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