ADT7316ARQZ-REEL7 [ADI]
Accurate Digital Temperature Sensor; 准确的数字温度传感器
| 型号： | ADT7316ARQZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Accurate Digital Temperature Sensor |
| 文件： | 总44页 (文件大小：3873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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rꢄdCQcrdCVsꢁaritCOcamcaC12-/1±-/8-BDaCꢀ °n
CC
ꢀꢂ7316/ ꢀꢂ7317/ ꢀꢂ7318
FEATURES
PIN CONFIGURATION
ADT7316—four 12-bit DACs
ADT7317—four 10-bit DACs
ADT7318—four 8-bit DACs
Buffered voltage output
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
Temperature range: −40°C to +120°C
Temperature sensor accuracy of 0.ꢀ°C
Supply range: 2.7 V to ꢀ.ꢀ V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
-B
-A
V
-C
-D
OUT
OUT
V
V
OUT
OUT
V
-AB
CS
ADT7316/
ADT7317/
ADT7318
-CD
REF
REF
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
GND
TOP VIEW
(Not to Scale)
V
DD
D+
D–
LDAC
DAC output range: 0 V to 2 VREF
Power-down current : <10 μA
Internal 2.28 VREF option
Figure 1.
Double-buffered input logic
Buffered/unbuffered reference input option
Power-on reset to 0 V
LDAC
Simultaneous update of outputs (
function)
On-chip rail-to-rail output buffer amplifier
I2C®-, SMBus-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-
compatible 4-wire serial interface
SMBus packet error checking (PEC) compatible
16-lead QSOP
APPLICATIONS
Portable battery-powered instruments
Personal computers
Telecommunications systems
Electronic test equipment
Domestic appliances
Process control
GENERAL DESCRIPTION
The ADT7316/ADT7317/ADT73181combine a 10-bit
temperature-to-digital converter and a quad 12-/10-/8-bit
DAC, respectively, in a 16-lead QSOP. This includes a band
gap temperature sensor and a 10-bit ADC to monitor and
digitize the temperature reading to a resolution of 0.25°C. The
ADT7316/ ADT7317/ADT7318 operate from a single 2.7 V to
5.5 V supply. The output voltage of the DAC ranges from 0 V
to 2 VREF, with an output voltage settling time of 7 μs typically.
The ADT7316/ ADT7317/ADT7318 provide two serial inter-
face options, a 4-wire serial interface that is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards, and a
2-wire SMBus/I2C interface. They feature a standby mode that
is controlled via the serial interface.
The reference for the four DACs is derived either internally
or from two reference pins (one per DAC pair). The outputs
of all DACs may be updated simultaneously using the software
LDAC
LDAC function or external
pin. The ADT7316/ADT7317/
ADT7318 incorporate a power-on-reset circuit that ensures the
DAC output powers up to 0 V and remains there until a valid
write takes place.
The ADT7316/ADT7317/ADT7318 wide supply voltage range,
low supply current, and SPI-/I2C-compatible interface make
them ideal for a variety of applications, including personal
computers, office equipment, and domestic appliances.
1 Protected by the following U.S. patent numbers: 5,764,174; 5,867,012;
6,097,239; 6,169,442.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
ADT7316/ADT7317/ADT7318
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Amplifier........................................................................ 21
Thermal Voltage Output ........................................................... 21
Functional Description—Measurement...................................... 23
Temperature Sensor ................................................................... 23
VDD Monitoring .......................................................................... 23
On-Chip Reference .................................................................... 24
Round Robin Measurement...................................................... 24
Single-Channel Measurement .................................................. 24
Temperature Measurement Method........................................ 24
Temperature Value Format ....................................................... 25
Interrupts..................................................................................... 26
Registers........................................................................................... 27
Register Descriptions................................................................. 28
Serial Interface ................................................................................ 36
Serial Interface Selection........................................................... 36
I2C Serial Interface ..................................................................... 36
SPI Serial Interface..................................................................... 37
Layout Considerations................................................................... 41
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
Applications....................................................................................... 1
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Functional Block Diagram .............................................................. 8
DAC AC Characteristics.................................................................. 9
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 19
Power-Up Calibration................................................................ 19
Conversion Speed....................................................................... 19
Functional Description—Voltage Output................................... 20
Digital-to-Analog Converters................................................... 20
Digital-to-Analog Section ......................................................... 20
Resistor String............................................................................. 20
DAC External Reference Inputs ............................................... 20
REVISION HISTORY
6/04—Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Internal VREF Value Change................................................... Universal
Change to Equation in Thermal Voltage Output Section..............21
Changes to Outline Dimensions .......................................................40
1/07—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Table 3.......................................................................... 10
Changes to Internal THIGH Limit Register (Read/Write)
[Address 0x25] Section .................................................................. 33
Changes to Internal TLOW Limit Register (Read/Write)
[Address 0x26] Section .................................................................. 33
Changes to External THIGH Limit Register (Read/Write)
[Address 0x27] Section .................................................................. 33
External TLOW Limit Register (Read/Write) [Address 0x28]
Section.............................................................................................. 37
Changes to SPI Interface Section.................................................. 38
Updated Outline Dimensions....................................................... 42
Changes to Ordering Guide .......................................................... 42
8/03—Revision 0: Initial Version
Rev. B | Page 2 of 44
ADT7316/ADT7317/ADT7318
SPECIFICATIONS
Temperature ranges for A version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.
Table 1.
Parameter1
DAC DC PERFORMANCE2, 3
Min
Typ
Max
Unit
Conditions/Comments
ADT7318
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
ADT7317
0.15
0.02
1
0.25
Guaranteed monotonic over all codes.
Guaranteed monotonic over all codes.
Guaranteed monotonic over all codes.
Resolution
10
0.5
0.05
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
ADT7316
4
0.5
Resolution
12
2
0.02
0.4
0.4
Bits
LSB
LSB
% of FSR
% of FSR
mV
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Dead Band
16
0.9
2
2
65
20
Lower dead band exists only if offset error is
negative. See Figure 2.
Upper Dead Band
60
100
mV
Upper dead band exists if VREF = VDD and offset
plus gain error is positive. See Figure 3.
Offset Error Drift
ppm of FSR/°C
−12
−5
Gain Error Drift
ppm of FSR/°C
DC Power Supply Rejection Ratio
DC Crosstalk
dB
μV
−60
200
∆VDD = 10%.
See Figure 6.
THERMAL CHARACTERISTICS
Internal reference used. Averaging on.
INTERNAL TEMPERATURE SENSOR
Accuracy at VDD = 3.3 V 10%
1.5
3
5
°C
°C
°C
°C
°C
Bits
°C
TA = 85°C.
TA = 0°C to +85°C.
0.5
2
TA = −40°C to +120°C.
TA = 0°C to +85°C.
Accuracy at VDD = 5 V 5%
2
3
3
5
TA = −40°C to +120°C.
Equivalent to 0.25°C.
Drift over 10 years if part is operated at 55°C.
External transistor = 2N3906.
TA = +85°C.
Resolution
Long-Term Drift
10
0.25
EXTERNAL TEMPERATURE SENSOR
Accuracy at VDD = 3.3 V 10%
1.5
3
°C
°C
TA = 0°C to +85°C.
5
°C
TA = −40°C to +120°C.
TA = 0°C to +85°C.
Accuracy at VDD = 5 V 5%
2
3
3
°C
5
°C
TA = −40°C to +120°C.
Equivalent to +0.25°C.
High level.
Resolution
10
Bits
μA
μA
Output Source Current
180
11
Low level.
Thermal Voltage Output
8-Bit DAC Output
Resolution
1
°C
Scale Factor
8.79
mV/°C
mV/°C
0 V to VREF output. TA = −40°C to +120°C.
0 V to 2 VREF output. TA = −40°C to +120°C.
17.58
10-Bit DAC Output
Resolution
0.25
°C
Scale Factor
2.2
mV/°C
mV/°C
0 V to VREF output. TA = −40°C to +120°C.
0 V to 2 VREF output. TA= −40°C to +120°C.
4.39
Rev. B | Page 3 of 44
ADT7316/ADT7317/ADT7318
Parameter1
CONVERSION TIMES
Slow ADC
Min
Typ
Max
Unit
Conditions/Comments
Single channel mode.
VDD
11.4
712
ms
μs
Averaging (16 samples) on.
Averaging off.
Internal Temperature
External Temperature
11.4
712
24.22
1.51
ms
μs
ms
ms
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on
Averaging off.
Fast ADC
VDD
712
μs
μs
ms
μs
ms
μs
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
44.5
2.14
134
14.25
890
Internal Temperature
External Temperature
ROUND ROBIN UPDATE RATE4
Slow ADC at 25°C
Time to complete one measurement cycle
through all channels.
59.95
6.52
ms
ms
Averaging on.
Averaging off.
Fast ADC at 25°C
19.59
2.89
ms
ms
Averaging on.
Averaging off.
DAC EXTERNAL REFERENCE INPUT5
VREF Input Range
VREF Input Range
VREF Input Impedance
1
0.25
37
VDD
VDD
V
V
kΩ
Buffered reference mode.
Unbuffered reference mode.
Unbuffered reference mode.
0 V to 2 VREF output range.
Unbuffered reference mode.
0 V to VREF output range.
45
74
90
kΩ
>10
MΩ
Buffered reference mode and power-down
mode.
Reference Feedthrough
Channel-to-Channel Isolation
ON-CHIP REFERENCE
dB
dB
Frequency = 10 kHz.
Frequency = 10 kHz.
−90
−75
Reference Voltage5
2.2662
0.001
2.28
80
2.2938
V
Temperature Coefficient5
OUTPUT CHARACTERISTICS5
Output Voltage6
ppm/°C
VDD to 0.001
V
This is a measure of the minimum and maximum
drive capability of the output amplifier.
DC Output Impedance
Short-Circuit Current
0.5
25
16
2.5
5
Ω
mA
mA
μs
VDD = 5 V.
VDD = 3 V.
Power-Up Time
Coming out of power-down mode. VDD = 5 V.
Coming out of power-down mode. VDD = 3.3 V.
μs
DIGITAL INPUTS5
Input Current
1
0.8
μA
V
V
pF
ns
VIN = 0 V to VDD.
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
1.89
20
3
10
50
All digital inputs.
Input filtering suppresses noise spikes of less than
50 ns.
SCL, SDA Glitch Rejection
LDAC
ns
Edge triggered input.
Pulse Width
Rev. B | Page 4 of 44
ADT7316/ADT7317/ADT7318
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
DIGITAL OUTPUT
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
2.4
V
V
mA
pF
V
ISOURCE = ISINK = 200 μA.
IOL = 3 mA.
VOH = 5 V.
0.4
1
50
0.8
INT
INT/
IOUT = 4 mA.
Output Saturation Voltage
I2C TIMING CHARACTERISTICS7, 8
Serial Clock Period, t1
Fast-mode I2C. See Figure 4.
2.5
50
0
μs
ns
ns
ns
Data In Setup Time to SCL High, t2
Data Out Stable After SCL Low, t3
See Figure 4.
See Figure 4.
SDA Low Setup Time to SCL Low
(Start Condition), t4
50
SDA High Hold Time After SCL High 50
(Stop Condition), t5
ns
See Figure 4.
SDA and SCL Fall Time, t6
300
3009
ns
ns
See Figure 4.
See Figure 4.
SDA and SCL Rise Time, t6
SPI TIMING CHARACTERISTICS10, 11
CS
0
ns
ns
ns
ns
to SCLK Setup Time, t1
See Figure 7.
See Figure 7.
See Figure 7.
See Figure 7.
SCLK High Pulse Width, t2
50
50
SCLK Low Pulse Width, t3
Data Access Time After SCLK Falling
Edge, t4
Data Setup Time Prior to SCLK
Rising Edge, t5
Data Hold Time after SCLK Rising
Edge, t6
35
40
12
20
0
ns
ns
See Figure 7.
See Figure 7.
CS
CS
0
ns
ns
to SCLK Hold Time, t7
See Figure 7.
See Figure 7.
to DOUT High Impedance, t8
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode)13
2.7
5.5
50
3
V
ms
mA
mA
μA
μA
mW
μW
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD , and VIL = GND.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD, and VIL = GND.
VDD = 3.3 V, using normal mode.
2.2
3
IDD (Power-Down Mode)
Power Dissipation
10
10
10
33
VDD = 3.3 V, using shutdown mode.
1 See the Terminology section.
2 DC specifications tested with the outputs unloaded.
3 Linearity is tested using a reduced code range: ADT7316 (Code 115 to 4095); ADT7317 (Code 28 to 1023); ADT7318 (Code 8 to 255).
4 A round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature.
5 Guaranteed by design and characterization, but not production tested.
6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD, offset plus
gain error must be positive.
7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate,
but has a negative effect on the EMC behavior of the part.
8 Guaranteed by design. Not tested in production.
9 The interface is also capable of handling the I2C standard mode rise time specification of 1000 ns.
10 Guaranteed by design and characterization, but not production tested.
11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
12 Measured with the load circuit of Figure 5.
13
I
specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
DD
Rev. B | Page 5 of 44
ADT7316/ADT7317/ADT7318
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
ACTUAL
IDEAL
LOWER
DEAD BAND
CODES
AMPLIFIER
FOOTROOM
NEGATIVE
OFFSET
ERROR
Figure 2. DAC Transfer Function with Negative Offset
GAIN ERROR
+
OFFSET ERROR
UPPER
DEAD BAND
CODES
OUTPUT
VOLTAGE
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
DAC CODE
FULL SCALE
Figure 3. DAC Transfer Function with Positive Offset (VREF = VDD
)
t1
SCL
t5
t2
t4
SDA
DATA IN
t3
SDA
DATA OUT
t6
Figure 4. I2C Bus Timing Diagram
Rev. B | Page 6 of 44
ADT7316/ADT7317/ADT7318
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for Access Time and Bus Relinquish Time
V
DD
4.7kΩ
TO DAC
OUTPUT
4.7kΩ
200pF
Figure 6. Load Circuit for DAC Outputs
CS
t1
t2
t7
SCLK
DIN
t6
t3
t5
t8
D7
X
D6
X
D5
D4
D3
X
D2
D1
D0
X
X
X
X
X
X
X
X
X
t4
DOUT
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7. SPI Bus Timing Diagram
Rev. B | Page 7 of 44
ADT7316/ADT7317/ADT7318
FUNCTIONAL BLOCK DIAGRAM
ADDRESS POINTER
REGISTER
ON-CHIP
TEMPERATURE
SENSOR
INTERNAL TEMPERATURE
VALUE REGISTER
DAC A
REGISTERS
STRING
DAC A
V
-A
2
OUT
T
LIMIT
HIGH
REGISTERS
T
LIMIT
LOW
REGISTERS
D+
D–
7
8
V
DD
A-TO-D
CONVERTER
ANALOG
MUX
LIMIT
COMPARATOR
DAC B
STRING
DAC B
VALUE
REGISTER
V
V
-B
-C
1
OUT
OUT
REGISTERS
V
LIMIT
DD
REGISTERS
CONTROL CONFIG. 1
REGISTER
DAC C
REGISTERS
V
STRING
DAC C
DD
EXTERNAL TEMPERATURE
VALUE REGISTER
16
SENSOR
CONTROL CONFIG. 2
REGISTER
DAC D
REGISTERS
STRING
DAC D
V
-D
15
10
CONTROL CONFIG. 3
REGISTER
OUT
ADT7316/
ADT7317/
ADT7318
DAC CONFIGURATION
REGISTER
GAIN
SELECT
LOGIC
POWER-
DOWN
LOGIC
LDAC CONFIGURATION
REGISTER
STATUS
REGISTERS
INTERRUPT MASK
REGISTERS
INT/INT
SMBus/SPI INTERFACE
INTERNAL
REFERENCE
6
5
4
13
12
11
9
3
14
-CD
V
GND
CS SCL/SCLK SDA/DIN DOUT/ADD
LDAC
V
-AB
V
DD
REF
REF
Figure 8.
Rev. B | Page 8 of 44
ADT7316/ADT7317/ADT7318
DAC AC CHARACTERISTICS
Guaranteed by design and characterization, but not production tested. VDD = 2.7 V to 5.5 V; RL = 4.7 kΩ to GND;
CL = 200 pF to GND; 4.7 kΩ to VDD. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Min
Typ (@ 25°C)
Max
Unit
Conditions and Comments
Output Voltage Settling Time
ADT7318
ADT7317
VREF = VDD = +5 V.
6
7
8
8
9
10
μs
μs
μs
1/4 scale to 3/4 scale change (0x40 to 0xC0).
1/4 scale to 3/4 scale change (0x100 to 0x300).
1/4 scale to 3/4 scale change (0x400 to 0xC00).
ADT7316
Slew Rate
0.7
12
0.5
1
0.5
3
V/μs
nV-s
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
1 LSB change around major carry.
nV-s
nV-s
nV-s
kHz
dB
200
−70
VREF = 2 V 0.1 V p-p.
VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz.
1 See Terminology section.
Rev. B | Page 9 of 44
ADT7316/ADT7317/ADT7318
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead QSOP
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +120°C
−65°C to +150°C
Table 4. I2C Address Selection
150°C
(TJ max − TA)/θJA
ADD Pin
I2C Address
1001 000
1001 010
1001 011
Power Dissipation1
Low
Float
High
Thermal Impedance2
θJA Junction-to-Ambient
θJC Junction-to-Case
IR Reflow Soldering
105.44°C/W
38.8°C/W
Peak Temperature
Time at Peak Temperature
Ramp-Up Rate
220°C (0/5°C)
10 sec to 20 sec
2°C/sec to 3°C/sec
−6°C/sec
ESD CAUTION
Ramp-Down Rate
IR Reflow Soldering (Pb-Free Package)
Peak Temperature
260°C (+ 0°C)
Time at Peak Temperature
Ramp-Up Rate
Ramp-Down Rate
20 sec to 40 sec
3°C/sec maximum
–6°C/sec maximum
8 minutes maximum
Time 25°C to Peak Temperature
1 Values relate to package being used on a 4-layer board.
2 Junction-to-case resistance is applicable to components featuring a
preferential flow direction, for example, components mounted on a heat
sink. Junction-to-ambient resistance is more useful for air-cooled, PCB-
mounted components.
Rev. B | Page 10 of 44
ADT7316/ADT7317/ADT7318
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
-B
-A
V
-C
-D
OUT
OUT
V
V
OUT
OUT
V
-AB
CS
ADT7316/
ADT7317/
ADT7318
-CD
REF
REF
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
GND
TOP VIEW
(Not to Scale)
V
DD
D+
D–
LDAC
Figure 9. Pin Configuration QSOP
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
VOUT-B
VOUT-A
VREF-AB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A and DAC B. It may be configured as a buffered or unbuffered input to both DAC A
and DAC B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
DAC A and DAC B default on power-up to this pin.
4
CS
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it
enables the input register, and data is transferred in on the rising edges and out on the falling edges of the
subsequent serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface
in I2C mode.
5
6
7
8
9
GND
VDD
D+
D−
LDAC
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
Positive connection to external temperature sensor.
Negative connection to external temperature sensor.
Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling
edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows
simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin.
Default is with the LDAC pin controlling the loading of DAC registers.
10
11
INT/INT
Over-Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature or VDD limits are exceeded. Default is active low. Open-drain output—needs a pull-up resistor.
DOUT/ADD DOUT: SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on
the falling edge of SCLK. Open-drain output—needs a pull-up resistor.
ADD: I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it
floating gives the address 1001 010, and setting it high gives the address 1001 011. The I2C address set up by the
ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the
second valid communication, the serial bus address is latched in. Any subsequent changes on this pin have no
affect on the I2C serial bus address.
12
SDA/DIN
SDA: I2C Serial Data Input. I2C serial data that is loaded into the device registers is provided on this input. Open-
drain configuration—needs a pull-up resistor.
DIN: SPI Serial Data Input. Serial data to be loaded into the device registers is provided on this input. Data is
clocked into a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.
13
14
SCL/SCLK
VREF-CD
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register
of the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain
configuration; needs a pull-up resistor.
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to both DAC C
and DAC D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode.
DAC C and DAC D default, on power-up, to this pin.
15
16
VOUT-D
VOUT-C
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Rev. B | Page 11 of 44
ADT7316/ADT7317/ADT7318
TERMINOLOGY
DC Crosstalk
Relative Accuracy
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in microvolts.
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. Typical
INL vs. code plots can be seen in Figure 10, Figure 11, and
Figure 12.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 0.9 LSB maximum
ensures monotonicity. Typical DAC DNL vs. code plots can be
seen in Figure 13, Figure 14, and Figure 15.
LDAC
(that is,
is high). It is expressed in decibels.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in decibels.
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier (see Figure 2 and Figure 3). It can be negative or
positive. It is expressed as a percentage of the full-scale range.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB
at the major carry transition (011…11 to 100…00 or 100...00 to
011…11).
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from
the ideal. It is expressed as a percentage of the full-scale range.
Digital Feedthrough
Offset Error Drift
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, that is, from all 0s to all 1s or vice versa.
This is a measure of the change in offset error with changes
in temperature. It is expressed in ppm of full-scale range/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm of full-scale range/°C.
Digital Crosstalk
Long Term Temperature Drift
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
This is a measure of the change in temperature error with the
passage of time. It is expressed in degrees Celsius. The concept
of long term stability has been used for many years to describe
by what amount an IC’s parameter would shift during its lifetime.
This is a concept that has been typically applied to both voltage
references and monolithic temperature sensors. Unfortunately,
integrated circuits cannot be evaluated at room temperature
(25°C) for 10 years or so to determine this shift. As a result,
manufacturers very typically perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated tem-
peratures (between 125°C and 150°C) over a shorter period of
time (typically between 500 and 1000 hours). As a result of this
operation, the lifetime of an integrated circuit is significantly
accelerated due to the increase in rates of reaction within the
semiconductor material.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
LDAC
(all 0s to all 1s and vice versa) while keeping
high. Pulse
LDAC
low and monitor the output of the DAC whose digital
code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in decibels. VREF is held at 2 V and VDD is varied 10ꢀ.
LDAC
code change (all 0s to all 1s and vice versa) with
low
and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.
Rev. B | Page 12 of 44
ADT7316/ADT7317/ADT7318
Multiplying Bandwidth
Round Robin
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on
the reference (with full-scale code loaded to the DAC) appears
on the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
This term is used to describe the ADT7316/ADT7317/
ADT7318 cycling through the available measurement
channels in sequence, taking a measurement on each
channel.
DAC Output Settling Time
Total Harmonic Distortion
This is the time required, following a prescribed data change,
for the output of a DAC to reach and remain within 0.5 LSB
of the final value. A typical prescribed change is from 1/4 scale
to 3/4 scale.
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure
of the harmonics present on the DAC output. It is measured
in decibels.
Rev. B | Page 13 of 44
ADT7316/ADT7317/ADT7318
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.10
0.08
0.06
0.04
0.02
0
0.15
0.10
0.05
0
–0.02
–0.04
–0.06
–0.08
–0.05
–0.10
–0.15
–0.20
–0.10
0
50
100
150
DAC CODE
200
250
0
50
100
150
200
250
DAC CODE
Figure 10. ADT7318 Typical INL Plot
Figure 13. ADT7318 Typical DNL Plot
0.6
0.3
0.2
0.4
0.2
0
0.1
0
–0.1
–0.2
–0.2
–0.3
–0.4
–0.6
0
200
400
600
800
1000
0
200
400
600
800
1000
DAC CODE
DAC CODE
Figure 14. ADT7317 Typical DNL Plot
Figure 11. ADT7317 Typical INL Plot
1.0
0.8
0.6
0.4
0.2
0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–0.2
–0.4
–0.6
–1.0
–1.5
–2.0
–2.5
–0.8
–1.0
0
500
1000 1500 2000
2500 3000 3500 4000
0
500
1000
1500 2000
2500 3000
3500 4000
DAC CODE
DAC CODE
Figure 15. ADT7316 Typical DNL Plot
Figure 12. ADT7316 Typical INL Plot
Rev. B | Page 14 of 44
ADT7316/ADT7317/ADT7318
0.30
10
0.25
0.20
OFFSET ERROR
INL WCP
5
0
0.15
V
= 2.25V
REF
0.10
0.05
–5
DNL WCP
–10
0
DNL WCN
INL WCN
GAIN ERROR
–15
–20
–0.05
–0.10
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.7
3.3
3.6
4.0
(V)
4.5
5.0
5.5
V
(V)
V
REF
DD
Figure 16. ADT7318 INL Error and DNL Error vs. VREF
Figure 19. Offset Error and Gain Error vs. VDD
2.505
0.14
0.12
INL WCP
INL WCN
DNL WCP
2.500
2.495
SOURCE CURRENT
0.10
0.08
0.06
0.04
0.02
0
2.490
2.485
SINK CURRENT
2.480
2.475
2.470
V
V
= 5V
–0.02
DD
DNL WCN
= 5V
REF
DAC OUTPUT
LOADED TO MIDSCALE
–0.04
–0.06
2.465
–40
–10
20
50
80
110
0
1
2
3
4
5
6
TEMPERATURE (°C)
CURRENT (mA)
Figure 17. ADT7318 INL Error and DNL Error vs. Temperature
Figure 20. VOUT Source and Sink Current Capability
1.98
1.96
1.94
1.92
1.90
1.88
1.86
0
DAC OUTPUT UNLOADED
–0.2
OFFSET ERROR
–0.4
–0.6
–0.8
–1.0
–1.2
DAC OUTPUT LOADED
–1.4
GAIN ERROR
–1.6
–1.8
0
500
1000 1500 2000
2500 3000
3500 4000
–40
–20
0
20
40
60
80
100
120
DAC CODE
TEMPERATURE (°C)
Figure 21. Supply Current vs. DAC Code
Figure 18. Offset Error and Gain Error vs. Temperature
Rev. B | Page 15 of 44
ADT7316/ADT7317/ADT7318
2.00
1.8
1.6
ADC OFF,
DAC OUTPUTS AT 0V
1.95
1.90
1.4
1.2
1.0
0.8
0.6
1.85
1.80
0.4
0.2
0
1.75
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
0
2
4
6
8
10
V
TIME (µs)
CC
Figure 25. Exiting Power-Down to Midscale
Figure 22. Supply Current vs. Supply Voltage @25°C
7
6
5
4
3
2
1
0
0.4700
0.4695
0.4690
0.4685
0.4680
0.4675
0.4670
0.4665
0.4660
0.4655
0.4650
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
0
2
4
6
8
10
V
TIME (µs)
CC
Figure 23. Power-Down Current vs. Supply Voltage @ 25°C
Figure 26. ADT7316 Major-Code Transition Glitch Energy
(0….11 to 100…00)
4.0
0.4730
0.4725
0.4720
0.4715
0.4710
0.4705
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.4700
0.4695
0.4690
0.4685
0
0
2
4
6
8
10
0
2
4
6
8
10
TIME (µs)
TIME (µs)
Figure 24. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 27. ADT7316 Major-Code Transition Glitch Energy
(100…00 to 011…11)
Rev. B | Page 16 of 44
ADT7316/ADT7317/ADT7318
0
1.5
1.0
0.5
V
= 5V
DD
= 25°C
EXTERNAL TEMPERATURE @ 5V
INTERNAL TEMPERATURE @ 3.3V
T
A
–2
–4
–6
0
–0.5
–1.0
–8
–10
EXTERNAL TEMPERATURE @ 3.3V
INTERNAL TEMPERATURE @ 5V
–12
–30
0
85
120
1
2
3
4
5
40
V
(V)
TEMPERATURE (°C)
REF
Figure 28. Full-Scale Error vs. VREF
Figure 31. Temperature Error @ 3.3 V and 5 V
2.329
2.328
2.327
15
10
5
V
V
= 5V
V
= 3.3V
DD
DD
= 5V
TEMPERATURE = 25°C
REF
DAC OUTPUT LOADED
TO MIDSCALE
D+ TO GND
0
2.326
2.325
2.324
2.323
2.322
–5
D+ TO V
CC
–10
–15
–20
–25
0
0
1
2
3
4
5
10
20
30
40
50
60
70
80
90
100
TIME (µs)
PCB TRACK RESISTANCE (MΩ)
Figure 29. DAC-to-DAC Crosstalk
Figure 32. External Temperature Error vs. PCB Track Resistance
0
0
–10
–20
±100mV RIPPLE ON V
CC
V
= 3.3V
V
V
= 2.25V
DD
REF
= 3.3V
DD
–10
–20
TEMPERATURE = 25°C
–30
–40
–50
–30
–40
–50
–60
1
–60
10
FREQUENCY (kHz)
100
0
5
10
15
20
25
30
35
40
45
50
CAPACITANCE (nF)
Figure 30. PSRR vs. Supply Ripple Frequency
Figure 33. External Temperature Error vs. Capacitance Between D+ and D−
Rev. B | Page 17 of 44
ADT7316/ADT7317/ADT7318
10
140
120
100
80
V
= 3.3V
DD
EXTERNAL TEMPERATURE
COMMON-MODE
VOLTAGE = 100mV
8
6
4
INTERNAL TEMPERATURE
2
60
0
40
–2
TEMPERATURE OF
ENVIRONMENT
20
–4
–6
CHANGED HERE
0
1
100
200
300
400
500
600
0
10
20
30
40
50
60
NOISE FREQUENCY (Hz)
TIME (s)
Figure 37. Temperature Sensor Response to Thermal Shock
Figure 34. External Temperature Error vs. Common-Mode Noise Frequency
0
70
V
= 3.3V
DD
DIFFERENTIAL-MODE
VOLTAGE = 100mV
60
–5
50
40
30
20
10
–10
–15
–20
–25
0
–10
10
100
1k
10k
100k
1M
10M
1
1
100
200
300
400
500
600
FREQUENCY (Hz)
NOISE FREQUENCY (MHz)
Figure 38. Multiplying Bandwidth (Small-Signal Frequency Response)
Figure 35. External Temperature Error vs. Differential-Mode Noise Frequency
0.6
V
= 3.3V
DD
0.4
0.2
0
–0.2
–0.4
–0.6
±250mV
1
100
200
300
400
500
600
NOISE FREQUENCY (Hz)
Figure 36. Internal Temperature Error vs. Power Supply Noise Frequency
Rev. B | Page 18 of 44
ADT7316/ADT7317/ADT7318
THEORY OF OPERATION
Directly after the power-up calibration routine, the ADT7316/
ADT7317/ADT7318 go into idle mode. In this mode, the device
is not performing any measurements and is fully powered up.
All four DAC outputs are at 0 V.
only be switched back to be I2C when the device is powered
2
CS
off and on. When using I C, the
VDD or GND.
pin should be tied to either
There are a number of different operating modes on the
ADT7316/ADT7317/ADT7318 devices, and all of them can
be controlled by the configuration registers. These features
consist of enabling and disabling interrupts, polarity of the
To begin monitoring, write to the Control Configuration 1
register (Address 0x18), and set Bit C0 = 1. The ADT7316/
ADT7317/ADT7318 go into their power-up default measure-
ment mode, which is round robin. The device proceeds to take
measurements on the VDD channel, the internal temperature
sensor channel, and the external temperature sensor channel.
Once it finishes taking measurements on the external tempera-
ture sensor channel, the device immediately loops back to start
taking measurements on the VDD channel and repeats the same
cycle as before. This loop continues until the monitoring is
stopped by resetting Bit C0 of the Control Configuration 1
register to 0.
INT
INT/
pin, enabling and disabling the averaging on the
measurement channels, SMBus timeout, and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part is initiated
until approximately 5 ms after VDD has settled to within 10ꢀ of
its final value. It is generally accepted that most systems take a
maximum of 50 ms to power-up. Power-up time is directly
related to the amount of decoupling on the voltage supply line.
During the 5 ms after VDD has settled, the part performs a cali-
bration routine; any communication to the device interrupts
this routine and can cause erroneous temperature measurements.
If it is not possible to have VDD at its nominal value by the time
50 ms has elapsed, or that communication to the device has
started prior to VDD settling, then it is recommended that a
measurement be taken on the VDD channel before a tempera
ture measurement is taken. The VDD measurement is used to
calibrate out any temperature measurement error due to
different supply voltage values.
It is also possible to continue monitoring as well as switching to
single-channel mode by writing to the Control Configuration 2
register (Address 0x19) and setting Bit C4 = 1. Further explana-
tion of the single-channel and round robin measurement modes
is given in later sections. All measurement channels have averaging
enabled on power-up. Averaging forces the device to take an
average of 16 readings before giving a final measured result. To
disable averaging and consequently decrease the conversion
time by a factor of 16, set C5 = 1 in the Control Configuration
2 register.
CONVERSION SPEED
Controlling the DAC outputs can be done by writing to the DAC
MSB and LSB registers (Address 0x10 to Address 0x17). The
power-up default setting is to have a low going pulse on the
The internal oscillator circuit used by the ADC has the capa-
bility to output two different clock frequencies. This means
that the ADC is capable of running at two different speeds
when performing a conversion on a measurement channel.
Thus, the time taken to perform a conversion on a channel
can be reduced by setting C0 of Control Configuration 3
register (Address 0x1A). This increases the ADC clock speed
from 1.4 kHz to 22 kHz. At the higher clock speed, the analog
filters on the D+ and D− input pins (external temperature
sensor) are switched off. This is why the power-up default
setting is to have the ADC working at the slow speed. The
typical times for fast and slow ADC speeds are given in the
Specifications section.
LDAC
pin controlling the updating of the DAC outputs from
the DAC registers. Alternatively, users can configure the updating
of the DAC outputs to be controlled by means other than the
LDAC
pin by setting C3 = 1 of the Control Configuration 3
register (Address 0x1A). The DAC Configuration register
(Address 0x1B), and the LDAC Configuration register (Address
0x1C) can then be used to control the DAC updating. These
two registers also control the output range of the DACs, enabling
or disabling the external reference buffer, and selecting between
the internal or external reference. DAC A and DAC B outputs
can be configured to give a voltage output proportional to the
temperature of the internal and external temperature sensors,
respectively.
The dual serial interface defaults to the I2C protocol on power-
up. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I2C protocol cannot be locked in, while the SPI protocol,
when selected, is automatically locked in. The interface can
The ADT7316/ADT7317/ADT7318 power up with averaging
on. This means every channel is measured 16 times and inter-
nally averaged to reduce noise. The conversion time can also
be sped up by turning the averaging off; to do so, set Bit C5 of
the Control Configuration 2 register (Address 0x19) to 1.
Rev. B | Page 19 of 44
ADT7316/ADT7317/ADT7318
FUNCTIONAL DESCRIPTION—VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTERS
DIGITAL-TO-ANALOG SECTION
The architecture of a DAC channel consists of a resistor string DAC
followed by an output buffer amplifier. The voltage at the VREF
pin or the on-chip reference of 2.28 V provides the reference
voltage for the corresponding DAC. Figure 39 shows a block
diagram of the DAC architecture. Because the input coding to
the DAC is straight binary, the ideal output voltage is given by
The ADT7316/ADT7317/ADT7318 have four resistor-string
DACs fabricated on a CMOS process, with resolutions of 12,
10, and 8 bits, respectively. They contain four output buffer
amplifiers and are written to via an I2C serial interface or an
SPI serial interface. See the Serial Interface Selection section
for more information.
VREF × D
The ADT7316/ADT7317/ADT7318 operate from a single supply
of 2.7 V to 5.5 V, and the output buffer amplifiers provide rail-
VOUT
=
2N
to-rail output swing with a slew rate of 0.7 V/μs. DAC A and
DAC B share a common external reference input, namely V
REF-AB. DAC C and DAC D share a common external reference
input, namely VREF-CD. Each reference input may be buffered
to draw virtually no current from the reference source or
unbuffered to give a reference input range from GND to VDD.
The devices have a power-down mode in which all DACs may
be turned off completely with a high impedance output.
where:
D = the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 255 for ADT7318 (8 bits).
0 to 1023 for ADT7317 (10 bits).
0 to 4095 for ADT7316 (12 bits).
N = the DAC resolution.
RESISTOR STRING
Each DAC output is not updated until it receives the LDAC
command. Therefore, while a new value is written to the DAC
registers, this value is not represented by a voltage output until
the DACs receive the LDAC command. Reading back from
any DAC register prior to issuing an LDAC command results in
the digital value that corresponds to the DAC output voltage.
Therefore, the digital value written to the DAC register cannot
be read back until after the LDAC command has been initiated.
The resistor string section is shown in Figure 40. It is a string of
resistors, each approximately 603 Ω. The digital code loaded to
the DAC register determines the node on the string where the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
LDAC
This LDAC command can be given by either pulling the
pin low (falling edge loads DACs), setting up Bit D4 and Bit D5
of the DAC Configuration register (Address 0x1B), or using the
LDAC Configuration register (Address 0x1C).
R
TO OUTPUT
AMPLIFIER
R
LDAC
When using the
pin to control DAC register loading, the
LDAC
low going pulse width should be 20 ns minimum. The
pin has to go high and low again before the DAC registers can
be reloaded.
R
R
V
-AB
REF
BUFFER
SELECT
SIGNAL
Figure 40. Resistor String
REFERENCE
BUFFER
DAC EXTERNAL REFERENCE INPUTS
There is a reference pin for each pair of DACs. The reference inputs
are buffered, but can also be individually configured as unbuffered.
The advantage with the buffered input is the high impedance it
presents to the voltage source driving it. However, if the unbuffered
mode is used, the user can have a reference voltage as low as
0.25 V and as high as VDD, because there is no restriction due
to headroom and footroom of the reference amplifier. If there
is a buffered reference in the circuit, there is no need to use the
on-chip buffers. In unbuffered mode, the input impedance is
still large at typically 90 kΩ per reference input for 0 V to VREF
output mode and 45 kΩ for 0 V to 2 VREF output mode.
GAIN MODE
(GAIN = 1 OR 2)
INT V
DAC
REF
INPUT
REGISTER
RESISTOR
STRING
V
-A
OUT
REGISTER
OUTPUT BUFFER
AMPLIFIER
Figure 39. Single DAC Channel Architecture
Rev. B | Page 20 of 44
ADT7316/ADT7317/ADT7318
V
DD
I
N × I
I
BIAS
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
V
OUT+
D+
REMOTE
C1
TO ADC
SENSING
TRANSISTOR
(2N3906)
D–
BIAS
DIODE
V
OUT–
LOW-PASS
FILTER
fC = 65kHz
Figure 41. Signal Conditioning for External Diode Temperature Sensors
proportional to output voltage. Each time a temperature
measurement is taken, the DAC output is updated. The out-
put resolution for the ADT7318 is 8 bits with the 1°C change
corresponding to the 1 LSB change. The output resolution for
the ADT7316 and ADT7317 is capable of 10 bits with a 0.25°C
change corresponding to the 1 LSB change.
The buffered/unbuffered option is controlled by the DAC
Configuration register (Address 0x1B; see the Registers
section). The LDAC Configuration register controls the
selection between internal and external voltage references.
The default setting is for external reference to be selected.
V
-AB
REF
The default output resolution for the ADT7316 and ADT7317
is 8 bits. To increase this to 10 bits, set C1 = 1 of the Control
Configuration 3 register (Address 0x1A). The default output
range is 0 V to VREF-AB, and this can be increased to 0 V to
2 VREF-AB. The user can select the internal VREF (VREF = 2.28 V)
by setting D4 = 1 in the LDAC Configuration register (Address
0x1C). Increasing the output voltage span to 2 VREF can be done
by setting D0 = 1 for DAC A (internal temperature sensor), and
D1 = 1 for DAC B (external temperature sensor) in the DAC
Configuration register (Address 0x1B).
2.25V INTERNAL
V
REF
STRING
DAC A
STRING
DAC B
Figure 42. DAC Reference Buffer Circuit
The output voltage is capable of tracking a maximum tem-
perature range of −128°C to +127°C, but the default setting is
−40°C to +127°C. If the output voltage range is 0 V to VREF-AB
(VREF-AB = 2.25 V), then this corresponds to 0 V representing
−40°C, and 1.48 V representing +127°C. This gives an upper
dead band between 1.48 V and VREF-AB.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of VREF, gain, and offset error.
If a gain of 1 is selected (Bit 0 to Bit 3 = 0, DAC Configuration
register, Address 0x1B), the output range is 0.001 V to VREF
If a gain of 2 is selected (Bit 0 to Bit 3 = 1, DAC Configuration
register, Address 0x1B), the output range is 0.001 V to 2 VREF
Because of clamping, however, the maximum output is limited
to VDD – 0.001 V.
.
The internal and external analog temperature offset registers
can be used to vary this upper dead band, and consequently,
the temperature that 0 V corresponds to. Table 6 and Table 7
give examples of how this is done using a DAC output voltage
span of VREF and 2 VREF, respectively. Write in the temperature
value, in twos complement format, at which 0 V is to start. For
example, if using the DAC A output with 0 V to start at −40°C,
program 0xD8 into the internal analog temperature offset regis-
ter (Address 0x21). This is an 8-bit register, and thus, only has a
temperature offset resolution of 1°C for all device models. Use
the following formulas to determine the value to program into
the offset registers.
.
The output amplifier is capable of driving a load of 4.7 kΩ to
VDD or 4.7 kΩ to GND in parallel with 200 pF to GND (see
Figure 6). The source and sink capabilities of the output
amplifier can be seen in Figure 20.
The slew rate is 0.7 V/μs with a half-scale settling time to
0.5 LSB (at 8 bits) of 6 μs.
THERMAL VOLTAGE OUTPUT
The ADT7316/ADT7317/ADT7318 are capable of outputting
voltages that are proportional to temperature. The DAC A
output can be configured to represent the temperature of the
internal sensor while DAC B output can be configured to
represent the external temperature sensor. Bit C5 and Bit C6
of the Control Configuration 3 register select the temperature
Rev. B | Page 21 of 44
ADT7316/ADT7317/ADT7318
Negative Temperatures
Table 7. Thermal Voltage Output (0 V to 2 VREF-AB)
Offset Register Code (dec) = (0 V Temp) + 128
Output Voltage (V)
Default (°C) Max (°C) Sample (°C)
0
−40
−26
+12
+3
+17
+23
+43
+45
−128
−114
−100
−85
−71
−65
−45
−43
−15
0
+14
+28
+42
+56
+70
+85
+99
+113
+127
0
+14
+28
+43
+57
+63
+83
+85
+113
+127
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
where D7 of Offset Register Code is set to 1 for negative
temperatures.
0.25
0.5
0.75
1
1.12
1.47
1.5
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4
Example:
Offset Register Code (dec) = −40 + 128 = 88d = 0x58
( )
Because a negative temperature is input into the equation, DB7
(MSB) of the Offset Register Code is set to 1. Therefore, 0x58
becomes 0xD8:
+73
+88
0x58 + DB7 1 = 0xD8
( )
+102
+116
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
UDB1
Positive Temperatures
Offset Register Code
Example:
Offset Register Code
(
dec
)
)
= 0 V Temp
= 10d =0x0A
(dec
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output:
4.25
4.5
8-Bit Temp = (DAC O/P ÷ 1 LSB) + (0 V Temp)
1Upper dead band has been reached. DAC output is not capable of increasing
(see Figure 3).
For example, if the output is 1.5 V, VREF-AB = 2.25 V, 8-bit DAC
has an LSB size = 2.25 V/256 = 8.79 × 10–3, and 0 V temp is at
−128°C, then the resultant temperature is
Figure 43 shows the DAC output vs. temperature for a
V
REF-AB = 2.25 V.
+ −128
( )
= + 43o C
−3
1.5 ÷ 8.79 ×10
2.25
2.10
1.95
1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output
0V = –128°C
10-Bit Temp = ((DAC O/P ÷ 1 LSB) × 0.25) + (0 V Temp)
For example, if the output is 0.4991 V, VREF-AB = 2.25 V, 10-bit
DAC has an LSB size = 2.25 V/1024 = 2.197 × 10-3, and 0 V temp
is at −40°C, then the resulting temperature is
0V = –40°C
0.4991 ÷ 2.197 ×10−3
× 0.25
+
(
− 40
)
= 16.75o C
0V = 0°C
Table 6. Thermal Voltage Output (0 V to VREF-AB)
Output Voltage (V)
Default (°C)
Max (°C)
−128
−71
−15
−1
+39
+42
+99
+127
Sample (°C)
0
+56
+113
+127
UDB1
UDB1
UDB1
UDB1
0
0.5
1
1.12
1.47
1.5
2
−40
+17
+73
+87
+127
UDB1
UDB1
UDB1
–128–110 –90 –70 –50 –30 –10 10 30 50 70 90 110 127
TEMPERATURE (°C)
Figure 43. 10-Bit DAC Output vs. Temperature, VREF-AB = 2.25 V
2.25
1Upper dead band has been reached. DAC output is not capable of increasing
(see Figure 3).
Rev. B | Page 22 of 44
ADT7316/ADT7317/ADT7318
FUNCTIONAL DESCRIPTION—MEASUREMENT
The third temperature measurement method is initiated after
every read or write to the part when the part is in either single-
channel measurement mode or round robin measurement mode.
Once serial communication has started, any conversion in pro-
gress is stopped and the ADC reset. Conversion starts again
immediately after the serial communication has finished. The
temperature measurement proceeds normally as described earlier.
TEMPERATURE SENSOR
The ADT7316/ADT7317/ADT7318 contain an ADC with spe-
cial input signal conditioning to enable operation with external
and on-chip diode temperature sensors. When the ADT7316/
ADT7317/ADT7318 are operating in single-channel mode, the
ADC continually processes the measurement taken on one
channel only. This channel is preselected by Bit C0 and Bit C1
in the Control Configuration 2 register (Address 0x19). When
in round robin mode, the analog input multiplexer sequentially
selects the VDD input channel, the on-chip temperature sensor
to measure its internal temperature, and the external tempera-
ture sensor. These signals are digitized by the ADC and the
results stored in the various value registers.
VDD MONITORING
The ADT7316/ADT7317/ADT7318 can monitor their own power
supplies. The parts measure the voltage on their VDD pin to a
resolution of 10 bits. The resulting value is stored in two 8-bit
registers: the 2 LSBs are stored in the Internal Temperature
Value/VDD Value register (Address 0x03) and the 8 MSBs are
stored in the VDD Value Register MSBs register (Address 0x06).
This allows the user to perform a 1-byte read if 10-bit resolution
is not important. The measured result is compared with VHIGH
and VLOW limits. If the VDD interrupt is not masked out, any out-
of-limit comparison generates a flag in the Interrupt Status 2
register (Address 0x10), and one or more out-of-limit results
The measured results are compared with the internal and
external, THIGH and TLOW, limits. These temperature limits are
stored in on-chip registers. If the temperature limits are not
masked out, any out-of-limit comparisons generate flags that
are stored in the Interrupt Status 1 register (Address 0x00). One
INT
or more out-of-limit results cause the INT/
output to pull
INT
cause the INT/
output to pull either high or low depending
either high or low depending on the output polarity setting.
on the output polarity setting.
Theoretically, the temperature measuring circuit can measure
temperatures from −128°C to +127°C with a resolution of 0.25°C.
Temperatures outside TA, however, are outside the guaranteed
operating temperature range of the device. Temperature meas-
urement from −128°C to +127°C is possible using an external
sensor.
Measuring the voltage on the VDD pin is regarded as monitoring
a channel. Therefore, along with the internal and external tem-
perature sensors, the VDD voltage makes up the third and final
monitoring channel. The user can select the VDD channel for
single-channel measurement by setting Bit C4 = 1 and setting
Bit C0 to Bit C2 to all 0s in the Control Configuration 2 register
(Address 0x19).
Temperature measurement is initiated by three methods. The first
method is applicable when the part is in single-channel meas-
urement mode. The temperature is measured 16 times and
internally averaged to reduce noise. In single-channel mode,
the part continuously monitors the selected channel, that is, as
soon as one measurement is taken, then another one is started
on the same channel. The total time to measure a temperature
channel with the ADC operating at slow speed is typically
11.4 ms (712 μs × 16) for the internal temperature sensor, and
24.22 ms (1.51 ms × 16) for the external temperature sensor.
The new temperature value is stored in two 8-bit registers and
ready for reading by the I2C or SPI interface. The user can
disable the averaging by setting Bit 5 = 1 in the Control Con-
figuration 2 register (Address 0x19). The ADT7316/ADT7317/
ADT7318 default on power-up, with the averaging enabled.
When measuring the VDD value, the reference for the ADC
is sourced from the internal reference. Table 8 shows the data
format. As the maximum VDD voltage measurable is 7 V,
internal scaling is performed on the VDD voltage to match the
2.28 V internal reference value. An example of how the transfer
function works follows.
V
DD = 5 V
ADC Reference = 2.28 V
1 LSB = ADC Reference/210 = 2.28/1024 = 2.226 mV
Scale Factor = Full-Scale VCC/ADC Reference = 7/2.28 = 3.07
Conversion Result = VDD/(Scale Factor × LSB Size)
= 5/(3.07 × 2.226 mV)
The second temperature measurement method is applicable
when the part is in round robin measurement mode. The part
measures both the internal and external temperature sensors
as it cycles through all possible measurement channels. The
two temperature channels are measured each time the part
runs a round robin sequence. In round-robin mode, the part
continuously measures all channels.
= 0x2DB
Rev. B | Page 23 of 44
ADT7316/ADT7317/ADT7318
V
DD
Table 8. VDD Data Format, VREF = 2.28 V
I
N × I
I
BIAS
Digital Output
VDD Value (V)
Binary
Hex
16E
1B7
200
249
292
2DC
325
36E
3B7
3FF
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
01 0110 1110
01 1011 0111
10 0000 0000
10 0100 1001
10 1001 0010
10 1101 1100
11 0010 0101
11 0110 1110
11 1011 0111
11 1111 1111
V
OUT+
TO ADC
INTERNAL
SENSE
TRANSISTOR
BIAS
DIODE
V
OUT–
Figure 44. Top Level Structure of Internal Temperature Sensors
SINGLE-CHANNEL MEASUREMENT
Setting C4 of the Control Configuration 2 register (Address
0x19) enables the single-channel mode and allows the ADT7316/
ADT7317/ ADT7318 to focus on one channel only. A channel
is selected by writing to Bit C0 and Bit C1 in the Control Con-
figuration 2 register. For example, to select the VDD channel for
monitoring, write to the Control Configuration 2 register and
set C4 = 1 (if this has not been done), then write all 0s to Bit C0
to Bit C1. All subsequent conversions are done on the VDD channel
only. To change the channel selection to the internal tempera-
ture channel, write to the Control Configuration 2 register and
set C0 = 1. When measuring in single-channel mode, conversions
on the channel selected occur directly after each other. Any
communication to the ADT7316/ADT7317/ ADT7318 stops
the conversions, but they are restarted once the read or write
operation is completed.
ON-CHIP REFERENCE
The ADT7316/ADT7317/ADT7318 have an on-chip 1.2 V band
gap reference that is gained up by a switched capacitor amplifier
to give an output of 2.28 V. The amplifier is powered up for the
duration of the device monitoring phase and is powered down
once monitoring is disabled. This saves on current consump-
tion. The internal reference is used as the reference for the
ADC. The ADC is used for measuring VDD and the internal
and external temperature sensors. The internal reference is
always used when measuring VDD, and the internal and exter-
nal temperature sensors. The external reference is the default
power-up reference for the DACs.
ROUND ROBIN MEASUREMENT
On power-up, the ADT7316/ADT7317/ADT7318 go into round
robin mode, but monitoring is disabled. Setting Bit C0 of the
Configuration 1 Register (Address 0x18) to 1 enables conversions.
It sequences through the three channels of VDD, the internal
temperature sensor, and the external temperature sensor and
takes a measurement from each. Once the conversion is completed
on the external temperature sensor, the device loops around for
another measurement cycle on all three channels. (This method
of taking a measurement on all three channels in one cycle is
called round robin.) Setting Bit 4 of the Control Configura-
tion 2 register (Address 0x19) disables the round-robin mode
and in turn sets up the single-channel mode. The single-channel
mode is where only one channel (for example, the internal tem-
perature sensor) is measured in each conversion cycle.
TEMPERATURE MEASUREMENT METHOD
Internal Temperature Measurement
The ADT7316/ADT7317/ADT7318 contain an on-chip, band
gap temperature sensor whose output is digitized by the on-chip
ADC. The temperature data is stored in the internal temperature
value register. As both positive and negative temperatures can
be measured, the temperature data is stored in twos comple-
ment format, as shown in Table 9. The thermal characteristics
of the measurement sensor can change, and therefore an offset
is added to the measured value to enable the transfer function
to match the thermal characteristics. This offset is added before
the temperature data is stored. The offset value used is stored in
the internal temperature offset register.
External Temperature Measurement
The time taken to monitor all channels is typically not of
interest, because the most recently measured value can be
read at any time.
The ADT7316/ADT7317/ADT7318 can measure the tempera-
ture of one external diode sensor or diode-connected transistor.
For applications where the round-robin time is important,
typical times at 25°C are given in the Specifications section.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, the absolute value
of VBE varies from device to device, and individual calibration is
required to null this out, so the technique is unsuitable for mass
production.
Rev. B | Page 24 of 44
ADT7316/ADT7317/ADT7318
The technique used in the ADT7316/ADT7317/ADT7318 is to
measure the change in VBE when the device is operated at two
different currents. This is given by
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25°C. The ADC can theo-
retically measure a temperature span of 255°C. The internal
temperature sensor is guaranteed to a low value limit of −40°C.
It is possible to measure the full temperature span using the
external temperature sensor. The temperature data format is
shown in Table 9. The result of the internal or external tempera-
ture measurements is stored in the temperature value registers
and is compared with limits programmed into the internal or
external high and low registers.
ΔVBE = KT/q × ln (N)
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
Figure 41 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a discrete substrate transistor. If a PNP
transistor is used, the base is connected to the D− input and the
emitter to the D+ input. If an NPN transistor is used, the emitter is
connected to the D− input and the base to the D+ input.
Table 9. Temperature Data Format (Internal and External
Temperature)
Digital Output
Temperature
−40°C
−25°C
−10°C
−0.25°C
0°C
0.25°C
10°C
25°C
50°C
75°C
100°C
105°C
125°C
DB9..........DB0
11 0110 0000
11 1001 1100
11 1101 1000
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
01 1010 0100
01 1111 0100
A 2N3906 is recommended to be used as the external transistor.
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground,
but is biased above ground by an internal diode at the D− input.
As the sensor is operating in a noisy environment, C1 is pro-
vided as a noise filter. See the Layout Considerations section on
for more information on C1.
To measure ꢁVBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a low-pass filter to remove noise, then to a chopper
stabilized amplifier that performs the functions of amplification
and rectification of the waveform to produce a dc voltage pro-
portional to ꢁVBE. This voltage is measured by the ADC to give
a temperature output in 10-bit twos complement format. To
further reduce the effects of noise, digital filtering is performed
by averaging the results of 16 measurement cycles.
Temperature Conversion Formula
Positive Temperature = ADC Code/4
Negative Temperature = (ADC Code − 512)/4
where DB9 is removed from the ADC code in the Negative
Temperature equation.
Rev. B | Page 25 of 44
ADT7316/ADT7317/ADT7318
(Address 0x00) and the Interrupt Status 2 register (Address
INT
to pull either high or low depending on the output polarity
setting. It is good design practice to mask out interrupts for
channels that are of no concern to the application.
INTERRUPTS
0x01). One or more out-of-limit results cause the INT/
output
The measured results from the internal temperature sensor,
external temperature sensor, and the VDD pin are compared with
the THIGH/VHIGH (greater than comparison) and TLOW/VLOW (less
than or equal to comparison) limits. An interrupt occurs if the
measurement exceeds or equals the limit registers. These limits
are stored in on-chip registers. Note that the limit registers are
8 bits long, while the conversion results are 10 bits long. If the
limits are not masked out, then any out-of-limit comparisons
generate flags that are stored in the Interrupt Status 1 register
Figure 45 shows the interrupt structure for the ADT7316/
ADT7317/ADT7318. It shows a block diagram of how the
INT
various measurement channels affect the INT/
pin.
S/W RESET
INTERNAL
TEMP
INTERRUPT
STATUS
REGISTER 1
(TEMP AND EXT.
DIODE CHECK)
EXTERNAL
TEMP
V
INTERRUPT
WATCHDOG
LIMIT
COMPARISONS
DD
INT/INT
(LATCHED OUTPUT)
MASK
REGISTERS
INTERRUPT
STATUS
REGISTER 2
DIODE
FAULT
(VDD
)
INT/INT
ENABLE BIT
READ RESET
CONTROL
CONFIGURATION
REGISTER 1
Figure 45. ADT7316/ADT7317/ADT7318 Interrupt Structure
Rev. B | Page 26 of 44
ADT7316/ADT7317/ADT7318
REGISTERS
The ADT7316/ADT7317/ADT7318 contain registers that are
used to store the results of external and internal temperature
measurements, VDD value measurements, high and low tem-
perature and supply voltage limits. They also set output DAC
voltage levels, configure multipurpose pins, and generally
control the device. A description of these registers follows.
Table 10. List of ADT7316/ADT7317/ADT7318 Registers
RD/WR
Address
Power-On
Default
Name
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Interrupt Status 1
Interrupt Status 2
Reserved
Internal Temp and VDD LSBs
External Temp LSBs
Reserved
0x00
0x00
0x00
0x00
0x00
0x00
0xxx
0x00
0x00
0x00
0x00
The register map is divided into registers of 8 bits. Each register
has its own individual address, but some consist of data that is
linked with other registers. These registers hold the 10-bit con-
version results of measurements taken on the temperature and
V
DD MSBs
VDD channels. For example, the 8 MSBs of the VDD measurement
Internal Temp MSBs
External Temp MSBs
are stored in VDD Value Register MSBs Register (Address 0x06),
while the 2 LSBs are stored in Internal Temperature Value/VDD
Value LSBs Register Address 0x03. These types of registers are
linked in that when the LSB register is read first, the MSB regis-
ters associated with that LSB register are locked out to prevent
any updates. To unlock these MSB registers, the user has only to
read any one of them, which effectively unlocks all previously
locked-out MSB registers. Therefore, for the example given
earlier, if Register 0x03 is read first, MSB Register 0x06 and
Register 0x07 are locked out to prevent any updates to them.
If Register 0x06 is read, then this register and Register 0x07
would be subsequently unlocked.
0x09 to 0x0F Reserved
0x10
DAC A LSBs
(ADT7316/ADT7317 only)
0x11
0x12
DAC A MSBs
DAC B LSBs
0x00
0x00
(ADT7316/ADT7317 only)
0x13
0x14
DAC B MSBs
DAC C LSBs
0x00
0x00
(ADT7316/ADT7317 only)
0x15
0x16
DAC C MSBs
DAC D LSBs
0x00
0x00
(ADT7316/ADT7317 only)
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
DAC D MSBs
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xD8
FIRST READ
COMMAND
LSB
OUTPUT
DATA
REGISTER
Control Configuration 1
Control Configuration 2
Control Configuration 3
DAC Configuration
LDAC Configuration
Interrupt Mask 1
LOCK ASSOCIATED
MSB REGISTERS
Figure 46. Phase 1 of 10-Bit Read
Interrupt Mask 2
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
Internal Temp Offset
External Temp Offset
Internal Analog Temp Offset
UNLOCK ASSOCIATED
MSB REGISTERS
External Analog Temp Offset 0xD8
V
V
DD VHIGH Limit
DD VLOW Limit
0xC7
0x62
0x64
0xC9
0xFF
0x00
Figure 47. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is
not locked out, allowing the user to read back only 8 bits (MSB)
of a 10-bit conversion result. Reading an MSB register first does
not lock out other MSB registers, and likewise, reading an LSB
register first does not lock out other LSB registers.
Internal THIGH Limit
Internal TLOW Limit
External THIGH Limit
External TLOW Limit
0x29 to 0x4C Reserved
0x4D
0x4E
0x4F
Device ID
Manufacturer’s ID
Silicon Revision
0x01/0x09/0x05
0x41
0xXx
0x50 to 0x7E Reserved
0x00
0x7F
SPI Lock Status
0x00
0x80 to 0xFF Reserved
0x00
Rev. B | Page 27 of 44
ADT7316/ADT7317/ADT7318
Table 15. Internal Temperature/VDD LSBs
REGISTER DESCRIPTIONS
D7
D6
D5
D4
D3
V1
01
D2
LSB
01
D1
T1
01
D0
LSB
01
The bit maps in this section show the register default settings at
power-up, unless otherwise noted.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Interrupt Status 1 Register (Read-Only) [Address 0x00]
This 8-bit, read-only register reflects the status of some of the
1 Default settings at power-up.
INT
interrupts that can cause the INT/
pin to go active. This
Table 16. Internal Temperature/VDD LSBs Bit Descriptions
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
Bit
D0
D1
D2
D3
Function
LSB of internal temperature value.
B1 of internal temperature value.
LSB of VDD value.
Table 11. Interrupt Status 1 Register
D7
D6
D5
D4
01
D3
01
D2
01
D1
01
D0
01
B1 of VDD value.
N/A
N/A
N/A
1 Default settings at power-up.
External Temperature Value Register LSBs (Read-Only)
[Address 0x04]
This 8-bit, read-only register stores the 2 LSBs of the 10-bit
Table 12. Interrupt Status 1 Register
Bit Function
temperature reading from the external temperature sensor.
D0 1 when internal temperature value exceeds THIGH limit. Any
internal temperature reading greater than the limit set
causes an out-of-limit event.
D1 1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the
limit set causes an out-of-limit event.
D2 1 when external temperature value exceeds THIGH limit. The
default value for this limit register is –1°C, so any external
temperature reading greater than the limit set causes an
out-of-limit event.
D3 1 when external temperature value exceeds TLOW limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the limit set
causes an out-of-limit event.
Table 17. External Temperature LSBs
D7
D6
D5
D4
D3
D2
D1
T1
01
D0
LSB
01
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Table 18. External Temperature LSBs Bit Descriptions
Bit
D0
D1
Function
LSB of external temperature value.
B1 of external temperature value.
VDD Value Register MSBs (Read-Only) [Address 0x06]
This 8-bit, read-only register stores the supply voltage value.
The 8 MSBs of the 10-bit value are stored in this register.
D4 1 indicates a fault (open or short) for the external
temperature sensor.
Interrupt Status 2 Register (Read-Only) [Address 0x01]
This 8-bit, read-only register reflects the status of the VDD
Table 19. VDD Value MSBs
D7
V9
X1
D6
V8
X1
D5
V7
X1
D4
V6
X1
D3
V5
X1
D2
V4
X1
D1
V3
X1
D0
V2
X1
INT
interrupt that can cause the INT/
pin to go active. This
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
1 Loaded with VDD value after power-up.
Table 13. Interrupt Status 2 Register
Internal Temperature Value Register MSBs (Read-Only)
[Address 0x07]
This 8-bit, read-only register stores the internal temperature
value from the internal temperature sensor in twos complement
format. The 8 MSBs of the 10-bit value are stored in this register.
D7
D6
D5
D4
01
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Table 14. Interrupt Status 2 Register Bit Descriptions
Bit Function
Table 20. Internal Temperature Value MSBs
D4 1 when VDD value is greater than the corresponding VHIGH
D7
T9
01
D6
T8
01
D5
T7
01
D4
T6
01
D3
T5
01
D2
T4
01
D1
T3
01
D0
T2
01
limit.
1 when VDD is less than or equal to the corresponding VLOW
limit.
1 Default settings at power-up.
Internal Temperature Value/VDD Value Register LSBs
(Read-Only) [Address 0x03]
This 8-bit, read-only register stores the 2 LSBs of the 10-bit
temperature reading from the internal temperature sensor
and the 2 LSBs of the 10-bit supply voltage reading.
Rev. B | Page 28 of 44
ADT7316/ADT7317/ADT7318
Table 26. DAC B (ADT7317) LSBs
External Temperature Value Register MSBs (Read-Only)
[Address 0x08]
This 8-bit, read-only register stores the external temperature
value from the external temperature sensor in twos complement
format. The 8 MSBs of the 10-bit value are stored in this register.
D7
B1
01
D6
LSB
01
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
DAC B Register MSBs (Read/Write) [Address 0x13]
Table 21. External Temperature Value MSBs
This 8-bit read/write register contains the 8 MSBs of the DAC B
word. The value in this register is combined with the value in
the DAC B register LSBs and converted to an analog voltage on
the VOUT-B pin. On power-up, the voltage output on the VOUT-B
pin is 0 V.
D7
T9
01
D6
T8
01
D5
T7
01
D4
T6
01
D3
T5
01
D2
T4
01
D1
T3
01
D0
T2
01
1 Default settings at power-up.
DAC A Register LSBs (Read/Write) [Address 0x10]
This 8-bit read/write register contains the 4/2 LSBs of the
Table 27. DAC B MSBs
ADT7316/ADT7317 DAC A word, respectively. The value in
this register is combined with the value in the DAC A Register
MSBs and converted to an analog voltage on the VOUT-A pin.
On power-up, the voltage output on the VOUT-A pin is 0 V.
D7
MSB
01
D6
B8
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
1 Default settings at power-up.
Table 22. DAC A (ADT7316) LSBs
DAC C Register LSBs (Read/Write) [Address 0x14]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/ADT7317 DAC C word, respectively. The value in
this register is combined with the value in the DAC C register
MSBs and converted to an analog voltage on the VOUT-C pin.
On power-up, the voltage output on the VOUT-C pin is 0 V.
D7
B3
01
D6
B2
01
D5
B1
01
D4
LSB
01
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Table 23. DAC A (ADT7317) LSBs
D7
B1
01
D6
LSB
01
D5
D4
D3
D2
D1
D0
Table 28. DAC C (ADT7316) LSBs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
D7
B3
01
D6
B2
01
D5
B1
01
D4
LSB
01
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
DAC A Register MSBs (Read/Write) [Address 0x11]
1 Default settings at power-up.
This 8-bit read/write register contains the 8 MSBs of the DAC A
word. The value in this register is combined with the value in
the DAC A Register LSBs and converted to an analog voltage on
the VOUT-A pin. On power-up, the voltage output on the VOUT-A
pin is 0 V.
Table 29. DAC C (ADT7317) LSBs
D7
B1
01
D6
LSB
01
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Table 24. DAC A MSBs
DAC C Register MSBs (Read/Write) [Address 0x15]
D7
MSB
01
D6
B8
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
This 8-bit read/write register contains the 8 MSBs of the DAC C
word. The value in this register is combined with the value in
the DAC C register LSBs and converted to an analog voltage on
the VOUT-C pin. On power-up, the voltage output on the VOUT-C
pin is 0 V.
1 Default settings at power-up.
DAC B Register LSBs (Read/Write) [Address 0x12]
This 8-bit read/write register contains the 4/2 LSBs of the
Table 30. DAC C MSBs
ADT7316/ADT7317 DAC B word, respectively. The value in
this register is combined with the value in the DAC B register
MSBs and converted to an analog voltage on the VOUT-B pin.
On power-up, the voltage output on the VOUT-B pin is 0 V.
D7
MSB
01
D6
B8
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
1 Default settings at power-up.
Table 25. DAC B (ADT7316) LSBs
D7
B3
01
D6
B2
01
D5
B1
01
D4
LSB
01
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1 Default settings at power-up.
Rev. B | Page 29 of 44
ADT7316/ADT7317/ADT7318
DAC D Register LSBs (Read/Write) [Address 0x16]
Table 35. Control Configuration 1 Bit Descriptions
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/ADT7317 DAC D word, respectively. The value in
this register is combined with the value in the DAC D register
MSBs and converted to an analog voltage on the VOUT-D pin.
On power-up, the voltage output on the VOUT-D pin is 0 V.
Bit
Function
C0
This bit enables/disables conversions in round robin
mode and single-channel mode. The
ADT7316/ADT7317/ ADT7318 power up in round-robin
mode, but monitoring is not initiated until this bit is set.
0 = Stop monitoring (default).
Table 31. DAC D (ADT7316) LSBs
1 = Start monitoring.
C1:4 Reserved. Only write 0s.
D7
B3
01
D6
B2
01
D5
B1
01
D4
LSB
01
D3
D2
D1
D0
C5
C6
0 = Enable INT/INT output. 1 = Disable INT/INT output.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Configures INT/INT output polarity. 0 = Active low.
1 = Active high.
1 Default settings at power-up.
PD
Power-Down Bit. Setting this bit to 1 puts the ADT7316/
ADT7317/ADT7318 into standby mode. In this mode,
both the ADC and the DACs are fully powered down, but
the serial interface is still operational. To power up the
part again, write 0 to this bit.
Table 32. DAC D (ADT7317) LSBs
D7
B1
01
D6
LSB
01
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Control Configuration 2 Register (Read/Write)
[Address 0x19]
This configuration register is an 8-bit, read/write register that
is used to set up some of the operating modes of the ADT7316/
ADT7317/ADT7318.
1 Default settings at power-up.
DAC D Register MSBs (Read/Write) [Address 0x17]
This 8-bit read/write register contains the 8 MSBs of the DAC D
word. The value in this register is combined with the value in
the DAC D register LSBs and converted to an analog voltage on
the VOUT-D pin. On power-up, the voltage output on the VOUT-D
pin is 0 V.
Table 36. Control Configuration 2
D7
C7
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
Table 33. DAC D MSBs
D7
MSB
01
D6
B8
01
D5
B7
01
D4
B6
01
D3
B5
01
D2
B4
01
D1
B3
01
D0
B2
01
1 Default settings at power-up.
Table 37. Control Configuration 2
1 Default settings at power-up.
Bit
Function
C0:1
In single-channel mode, these bits select between VDD
the internal temperature sensor, and the external
temperature sensor for conversion.
00 = VDD (default).
01 = Internal temperature sensor.
10 = External temperature sensor.
11 = Reserved.
,
Control Configuration 1 Register (Read/Write)
[Address 0x18]
This configuration register is an 8-bit read/write register that
is used to setup some of the operating modes of the ADT7316/
ADT7317/ADT7318.
Table 34. Control Configuration 1
C2:3
C4
Reserved.
D7
PD
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
Selects between single-channel and round robin
conversion cycle. Default is round robin.
0 = Round robin.
1 = Single channel.
Default condition is to average every measurement on
all channels 16 times. This bit disables this averaging.
Channels affected are temperature and VDD
0 = Enable averaging.
1 = Disable averaging.
SMBus timeout on the serial clock puts a 25 ms limit
on the pulse width of the clock. Ensures that a fault
on the master SCL does not lock up the SDA line.
SMBus timeout.
1 Default settings at power-up.
C5
C6
.
0 = Disable.
1 = Enable SMBus timeout.
C7
Software reset. Setting this bit to 1 causes a software
reset. All registers and DAC outputs reset to their
default settings.
Rev. B | Page 30 of 44
ADT7316/ADT7317/ADT7318
Control Configuration 3 Register (Read/Write)
[Address 0x1A]
This configuration register is an 8-bit read/write register that
is used to set up some of the operating modes of the ADT7316/
ADT7317/ADT7318.
Table 41. DAC Configuration
Bit
Function
Selects the output range of DAC A.
0 = 0 V to VREF
1 = 0 V to 2 VREF
Selects the output range of DAC B.
0 = 0 V to VREF
1 = 0 V to 2 VREF
Selects the output range of DAC C.
0 = 0 V to VREF
1 = 0 V to 2 VREF
Selects the output range of DAC D.
0 = 0 V to VREF
1 = 0 V to 2 VREF
D0
.
.
D1
.
Table 38. Control Configuration 3
.
D7
C7
01
D6
C6
01
D5
C5
01
D4
C4
01
D3
C3
01
D2
C2
01
D1
C1
01
D0
C0
01
D2
.
.
1 Default settings at power-up.
D3
.
.
Table 39. Control Configuration 3
Bit Function
00 = MSB write to any DAC register generates an LDAC
command, which updates that DAC only.
D4:5
Selects between fast and normal ADC conversion speeds
for all three monitoring channels.
C0
01 = MSB write to DAC B or DAC D register generates
an LDAC command, which updates DAC A, DAC B or DAC
C, DAC D, respectively.
10 = MSB write to DAC D register generates an LDAC
command, which updates all 4 DACs.
0 = ADC clock at 1.4 kHz.
1 = ADC clock at 22.5 kHz. D+ and D− analog filters are
disabled.
On the ADT7316 and ADT7317, this bit selects between
8-bit and 10-bit DAC output resolution on the thermal
voltage output feature. Default = 8 bits. This bit has no
effect on the ADT7318 output because this part has only
an 8-bit DAC. In the ADT7318 case, write 0 to this bit.
0 = 8-bit resolution.
C1
11 = LDAC command generated from LDAC register.
Setting this bit allows the external VREF to bypass the
reference buffer when supplying DAC A and DAC B.
Setting this bit allows the external VREF to bypass the
reference buffer when supplying DAC C and DAC D.
D6
D7
1 = 10-bit resolution.
C2 Reserved. Only write 0.
LDAC Configuration Register (Write-Only)
[Address 0x1C]
This configuration register is an 8-bit write register that is used
0 = LDAC pin controls updating of DAC outputs.
1 = DAC configuration register and LDAC configuration
register control the updating of the DAC outputs.
C3
LDAC
to control the updating of the quad DAC outputs if the
pin is disabled and Bit D4 and Bit D5 of the DAC Configuration
register are both set to 1. It also selects either the internal or
external VREF for all four DACs. Bit D0 to Bit D3 in this register
are self-clearing, that is, reading back from this register always
gives 0s for these bits.
C4 Reserved. Only write 0.
C5 Setting this bit selects DAC A voltage output to be
proportional to the internal temperature measurement.
C6 Setting this bit selects DAC B voltage output to be
proportional to the external temperature measurement.
C7 Reserved. Only write 0.
Table 42. LDAC Configuration
DAC Configuration Register (Read/Write) [Address 0x1B]
This configuration register is an 8-bit, read/write register that
is used to control the output ranges of all four DACs and to
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
LDAC
control the loading of the DAC registers if the
pin is
1 Default settings at power-up.
disabled (Bit C3 = 1, Control Configuration 3 register).
Table 43. LDAC Configuration
Table 40. DAC Configuration
Bit
Function
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
D0
Writing 1 to this bit generates the LDAC command to
update the DAC A output only.
D1
D2
D3
D4
Writing 1 to this bit generates the LDAC command to
update the DAC B output only.
Writing 1 to this bit generates the LDAC command to
update the DAC C output only.
Writing 1 to this bit generates the LDAC command to
update the DAC D output only.
Selects either internal VREF or external VREF-AB for DAC A,
DAC B, DAC C and DAC D.
1 Default settings at power-up.
0 = External VREF
1 = Internal VREF
D5:D7 Reserved. Only write 0s.
.
.
Rev. B | Page 31 of 44
ADT7316/ADT7317/ADT7318
Interrupt Mask 1 Register (Read/Write) [Address 0x1D]
This mask register is an 8-bit, read/write register that can be
Table 48. Internal Temperature Offset
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
INT
used to mask out any interrupts that can cause the INT/
pin to go active.
1 Default settings at power-up.
Table 44. Interrupt Mask 1
External Temperature Offset Register (Read/Write)
[Address 0x20]
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
This register contains the offset value for the external tempera-
ture channel. A twos complement number can be written to this
register which is then added to the measured result before it is
stored or compared to limits. In this way, one-point calibration
can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this
may be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change. As
it is an 8-bit register, the temperature resolution is 1°C.
1 Default settings at power-up.
Table 45. Interrupt Mask 1 Bit Descriptions
Bit
Function
0 = Enable internal THIGH interrupt.
1 = Disable internal THIGH interrupt.
0 = Enable internal TLOW interrupt.
1 = Disable internal TLOW interrupt.
0 = Enable external THIGH interrupt.
1 = Disable external THIGH interrupt.
0 = Enable external TLOW interrupt.
1 = Disable external TLOW interrupt.
D0
D1
D2
Table 49. External Temperature Offset
D3
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
0 = Enable external temperature fault interrupt.
1 = Disable external temperature fault interrupt.
Reserved. Only write 0s.
D4
D5: 7
1 Default settings at power-up.
Internal Analog Temperature Offset Register (Read/Write)
[Address 0x21]
Interrupt Mask 2 Register (Read/Write) [Address 0x1E]
This mask register is an 8-bit read/write register that can be
This register contains the offset value for the internal thermal
voltage output. A twos complement number can be written to
this register which is then added to the measured result before
it is converted by DAC A. Varying the value in this register has
the effect of varying the temperature span. For example, the
output voltage can represent a temperature span of −128°C to
+127°C or even 0°C to 127°C. In essence, this register changes
the position of 0 V on the temperature scale. Anything other
than −128°C to +127°C produces an upper dead band on the
DAC A output. As it is an 8-bit register, the temperature
resolution is 1°C. The default value is −40°C.
INT
used to mask out any interrupts that can cause the INT/
pin to go active.
Table 46. Interrupt Mask 2
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
Table 47. Interrupt Mask 2 Bit Descriptions
Bit
Function
D0:D3
D4
Reserved. Only write 0s.
0 = Enable VDD interrupts.
1 = Disable VDD interrupts.
Reserved. Only write 0s.
Table 50. Internal Analog Temperature Offset
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
11
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
01
D5:7
1 Default settings at power-up.
Internal Temperature Offset Register (Read/Write)
[Address 0x1F]
This register contains the offset value for the internal tempera-
ture channel. A twos complement number can be written to this
register which is then added to the measured result before it is
stored or compared to limits. In this way, a one-point calibration
can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this
may be a very simple method to vary the characteristics of the
measurement channel if the thermal characteristics change. As
it is an 8-bit register, the temperature resolution is 1°C.
Rev. B | Page 32 of 44
ADT7316/ADT7317/ADT7318
External Analog Temperature Offset Register (Read/Write)
[Address 0x22]
Internal THIGH Limit Register (Read/Write) [Address 0x25]
This limit register is an 8-bit read/write register that stores
the twos complement of the internal temperature upper limit
This register contains the offset value for the external thermal
voltage output. A twos complement number can be written to
this register which is then added to the measured result before it
is converted by DAC B. Varying the value in this register has the
affect of varying the temperature span. For example, the output
voltage can represent a temperature span of −128°C to +127°C
or even 0°C to 127°C. In essence, this register changes the posi-
tion of 0 V on the temperature scale. Anything other than −128°C
to +127°C produces an upper dead band on the DAC B output.
As it is an 8-bit register, the temperature resolution is 1°C. The
default value is −40°C.
INT
that causes an interrupt and activates the INT/
output (if
enabled). For this to happen, the measured internal temperature
value has to be greater than the value in this register. As it is an
8-bit register, the temperature resolution is 1°C. The default
value is 100°C.
Positive Temperature = Limit Register Code (dec)
Negative Temperature = Limit Register Code (dec) – 256
Table 54. Internal THIGH Limit
D7
D7
01
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
01
D0
D0
01
Table 51. External Analog Temperature
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
11
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
Internal TLOW Limit Register (Read/Write) [Address 0x26]
This limit register is an 8-bit, read/write register that stores the
twos complement of the internal temperature lower limit that
1 Default settings at power-up.
VDD VHIGH Limit Register (Read/Write) [Address 0x23]
This limit register is an 8-bit read/write register that stores the
DD upper limit that causes an interrupt and activates the INT/
INT
INT
causes an interrupt and activates the INT/
output (if enabled).
For this to happen, the measured internal temperature value has
to be more negative than or equal to the value in this register.
As it is an 8-bit register, the temperature resolution is 1°C. The
default value is −55°C.
V
output (if enabled). For this to happen, the measured VDD
value has to be greater than the value in this register. The default
value is 5.46 V.
Positive Temperature = Limit Register Code (dec)
Negative Temperature = Limit Register Code (dec) – 256
Table 52. VDD VHIGH Limit
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
11
D1
D1
11
D0
D0
11
Table 55. Internal TLOW Limit
D7
D7
11
D6
D6
11
D5
D5
01
D4
D4
01
D3
D3
11
D2
D2
01
D1
D1
01
D0
D0
11
1 Default settings at power-up.
VDD VLOW Limit Register (Read/Write) [Address 0x24]
This limit register is an 8-bit read/write register that stores the
DD lower limit that causes an interrupt and activates the INT/
INT
1 Default settings at power-up.
External THIGH Limit Register (Read/Write) [Address 0x27]
This limit register is an 8-bit, read/write register that stores
the twos complement of the external temperature upper limit
V
output (if enabled). For this to happen, the measured VDD
value has to be less than or equal to the value in this register.
The default value is 2.7 V.
INT
that causes an interrupt and activates the INT/
output (if
enabled). For this to happen, the measured external tempera-
ture value has to be greater than the value in this register. As it
is an 8-bit register, the temperature resolution is 1°C. The
default value is −1°C.
Table 53. VDD VLOW Limit
D7
D7
01
D6
D6
11
D5
D5
11
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
11
D0
D0
01
Positive Temperature = Limit Register Code (dec)
Negative Temperature = Limit Register Code (dec) – 256
1 Default settings at power-up.
Table 56. External THIGH Limit
D7
D7
11
D6
D6
11
D5
D5
11
D4
D4
11
D3
D3
11
D2
D2
11
D1
D1
11
D0
D0
11
1 Default settings at power-up.
Rev. B | Page 33 of 44
ADT7316/ADT7317/ADT7318
Manufacturer’s ID Register (Read-Only) [Address 0x4E]
This register contains the manufacturers identification number.
Analog Devices, Inc.’s ID is 0x41.
External TLOW Limit Register (Read/Write) [Address 0x28]
This limit register is an 8-bit, read/write register that stores the
twos complement of the external temperature lower limit that
INT
causes an interrupt and activates the INT/
output (if enabled).
Silicon Revision Register (Read-Only) [Address 0x4F]
This register is divided into the 4 LSBs representing the stepping
and the 4 MSBs representing the version. The stepping contains
the manufacturer’s code for minor revisions or steppings to the
silicon. The version is the ADT7316/ADT7317/ ADT7318
version number.
For this to happen, the measured external temperature value
has to be more negative than or equal to the value in this regis-
ter. As it is an 8-bit register, the temperature resolution is 1°C.
The default value is 0°C.
Positive Temperature = Limit Register Code (dec)
Negative Temperature = Limit Register Code (dec) – 256
SPI Lock Status Register (Read-Only) [Address 0x7F]
Bit D0 (LSB) of this read-only register indicates whether the SPI
interface is locked. Writing to this register causes the device to
malfunction. The default value is 0x00.
0 = I2C interface.
1 = SPI interface selected and locked.
Table 57. External TLOW Limit
D7
D7
01
D6
D6
01
D5
D5
01
D4
D4
01
D3
D3
01
D2
D2
01
D1
D1
01
D0
D0
01
1 Default settings at power-up.
Device ID Register (Read-Only) [Address 0x4D]
This 8-bit, read-only register indicates which part the device is
in the model range. ADT7316 = 0x01, ADT7317 = 0x09, and
ADT7318 = 0x05.
V
V
DD
DD
ADT7316/
ADT7317/
ADT7318
10kΩ
10kΩ
CS
SDA
SCL
2
I C ADDRESS = 1001 000
ADD
Figure 48. Typical I2C Interface Connection
ADT7316/
ADT7317/
ADT7318
LOCK AND
SELECT SPI
CS
V
DD
SPI FRAMING
EDGE
820Ω 820Ω 820Ω
DIN
SCLK
DOUT
Figure 49. Typical SPI Interface Connection
Rev. B | Page 34 of 44
ADT7316/ADT7317/ADT7318
A
B
C
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
A
B
C
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
Figure 50. Serial Interface—Selecting and Locking SPI Protocol
1
1
9
1
9
SCL
SDA
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
START BY
MASTER
ACKNOWLEDGE BY
ADT7316/ADT7317/ADT7318
ACKNOWLEDGE BY STOP BY
ADT7316/ADT7317/ADT7318 MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 51. I2C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. B | Page 35 of 44
ADT7316/ADT7317/ADT7318
SERIAL INTERFACE
There are two serial interfaces that can be used on this part, the
I2C and the SPI interface. The device powers up with the serial
calculated using CRC-8. The frame clock sequence (FCS)
conforms to CRC-8 by the polynomial:
interface in I2C mode, but it is not locked into this mode. To
C(x) = x8 + x2 + x1 + 1
2
CS
stay in I C mode, it is recommended that the user ties the
Consult SMBus for more information.
The serial bus protocol operates as follows:
line to either VCC or GND. It is not possible to lock the I2C
mode, but it is possible to select and lock the SPI mode.
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follow. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
To select and lock the interface into the SPI mode, a number
CS
of pulses must be sent down the
section describes how this is done.
(Pin 4) line. The following
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI Lock Status register (Address 0x7F) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and power
up again. A software reset does not reset the serial interface.
W
address (MSB first) plus an R/ bit, which determines the
direction of the data transfer, that is, whether data is to be
written to or read from the slave device. The peripheral
whose address corresponds to the transmitted address
responds by pulling the data line low during the low period
before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus now remain idle, while the
selected device waits for data to be read from or written to
SERIAL INTERFACE SELECTION
2
CS
The
line controls the selection between I C and SPI.
Figure 50 shows the selection process necessary to lock the
SPI interface mode.
W
it. If the R/ bit is 0, the master writes to the slave device.
To communicate to the ADT7316/ADT7317/ADT7318 using
W
If the R/ bit is 1, the master reads from the slave device.
CS
the SPI protocol, send three pulses down the
line, as shown
2. Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition
when the clock is high may be interpreted as a stop signal.
in Figure 50. On the third rising edge (marked as C in Figure 50),
the part selects and locks the SPI interface. The user is limited
to communicating to the device using the SPI protocol.
CS
As per most SPI standards, the
line must be low during every
SPI communication to the ADT7316/ADT7317/ ADT7318 and
high all other times. Typical examples of how to connect the
dual interface as I2C or SPI are shown in Figure 48 and Figure 49.
The following sections describe in detail how to use the I2C
and SPI protocols associated with the ADT7316/ADT7317/
ADT7318.
3. When all data bytes have been read or written, stop condi-
tions are established. In write mode, the master pulls the
data line high during the 10th clock pulse to assert a stop
condition. In read mode, the master device pulls the data
line high during the low period before the ninth clock
pulse. This is known as no acknowledge. The master takes
the data line low during the low period before the 10th
clock pulse, then high during the 10th clock pulse to assert
a stop condition.
I2C SERIAL INTERFACE
Like all I2C-compatible devices, the ADT7316/ADT7317/
ADT7318 have a 7-bit serial address. The 4 MSBs of this
address for the ADT7316/ADT7317/ADT7318 are set to
1001. The 3 LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low
gives a serial bus address of 1001 000, leaving it floating gives
the address 1001 010, and setting it high gives the address
1001 011. The recommended pull-up resistor value is 10 kΩ.
Any number of bytes of data may be transferred over the serial
bus in one operation. However, reads and writes cannot be mixed
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
The I2C address set up by the ADD pin is not latched by the device
until after this address has been sent twice. On the eighth SCL
cycle of the second valid communication, the serial bus address
is latched in. This is the SCL cycle directly after the device has
seen its own I2C serial bus address. Any subsequent changes on
this pin have no effect on the I2C serial bus address.
There is a programmable SMBus timeout. When this is enabled
the SMBus times out after 25 ms of no activity. To enable it, set
Bit 6 of the Control Configuration 2 register (Address 0x19). The
power-up default is with the SMBus timeout disabled.
The ADT7316/ADT7317/ADT7318 support SMBus packet
error checking (PEC) and its use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC byte is
Rev. B | Page 36 of 44
ADT7316/ADT7317/ADT7318
Writing to the ADT7316/ADT7317/ADT7318
SPI SERIAL INTERFACE
Depending on the register being written to, there are two
different writes for the ADT7316/ADT7317/ADT7318. It is
not possible to do a block write to this part, that is, no I2C
auto-increment.
The SPI serial interface of the ADT7316/ADT7317/ADT7318
CS CS
consists of four wires, , SCLK, DIN, and DOUT. The
used to select the device when more than one device is connected
CS
is
to the serial clock and data lines. The
is also used to distinguish
between any two separate serial communications (see Figure 58).
The SCLK is used to clock data in and out of the part. The DIN
line is used to write to the registers and the DOUT line is used
to read data back from the registers. The recommended pull-up
resistor value is between 500 Ω to 820 Ω. Strong pull ups are
needed when serial clock speeds (which are close to the maximum
limit) are used or when the SPI interface lines are experiencing
large capacitive loading. Larger resistor values can be used for
pull-up resistors when the serial clock speed is reduced.
Writing to the Address Pointer Register for a Subsequent
Read
To read data from a particular register, the address pointer
register must contain the address of that register. If it does
not, the correct address must be written to the address pointer
register by performing a single-byte write operation, as shown
in Figure 51. The write operation consists of the serial bus address
followed by the address pointer byte. No data is written to any
of the data registers. A read operation is then performed to read
the register.
The part operates in slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface
is designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
Writing Data to a Register
All registers are 8-bit registers so only one byte of data can be
written to each register. Writing a single byte of data to one of
these read/write registers consists of the serial bus address, the
data register address written to the address pointer register,
followed by the data byte written to the selected data register.
This is illustrated in Figure 52. To write to a different register,
another start or repeated start is required. If more than one byte
of data is sent in one communication operation, the addressed
register is repeatedly loaded until the last data byte is sent.
There are two types of serial operations, a read and a write.
Command words are used to distinguish between a read and a
write operation, as shown in Table 58. Address auto-increment
is possible in SPI mode.
Table 58. SPI Command Words
Write
Read
0x90 (1001 0000)
0x91 (1001 0001)
Reading Data from the ADT7316/ADT7317/ADT7318
Reading data from the ADT7316/ADT7317/ADT7318 is done
in a 1-byte operation. Reading back the contents of a register is
shown in Figure 56. The register address previously had been
set up by a single byte write operation to the address pointer
register. To read from another register, write to the address
pointer register again to set up the relevant register address.
Therefore, block reads are not possible, that is, no I2C auto-
increment.
1
9
1
9
SCL
1
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
R/W
SDA
START BY
ACKNOWLEDGE BY
ACKNOWLEDGE BY
MASTER
ADT7316/ADT7317/ADT7318
ADT7316/ADT7317/ADT7318
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP BY
MASTER
ACKNOWLEDGE BY
ADT7316/ADT7317/ADT7318
FRAME 3
DATA BYTE
Figure 52. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
Rev. B | Page 37 of 44
ADT7316/ADT7317/ADT7318
Write Operation
time. In Figure 54, the register address section provides the first
register address that is written to. Subsequent data bytes are
written into sequential writable registers. Therefore, after each
data byte has been written into a register, the address pointer
register auto-increments its value to the next available register.
The address pointer register auto-increments from Address
0x00 to Address 0x3F and loops back to start all over again at
Address 0x00 when it reaches Address 0x3F.
Figure 54 and Figure 55 show the timing diagrams for a write
operation to the ADT7316/ADT7317/ADT7318. Data is clocked
CS
into the registers on the rising edge of SCLK. When the
is high, the DIN and DOUT lines are in three-state mode. Only
CS
line
when the
goes from a high to a low does the part accept any
data on the DIN line. In SPI mode, the address pointer register
is capable of an auto-increment to the next register in the register
map without having to load the address pointer register each
1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE BY
ADT7316/ADT7317/ADT7318
START BY
MASTER
NO ACKNOWLEDGE BY STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM ADT7316/ADT7317/ADT7318
Figure 53. I2C — Reading a Single Byte of Data From a Selected Register
CS
1
8
1
8
SCLK
DIN
D2
D1
D6
D7
D7
START
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D0
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
D7
D4
D3
D1
D6
D5
D2
D0
DIN (CONTINUED)
STOP
DATA BYTE
Figure 54. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
CS
1
8
1
8
SCLK
DIN
D2
D6
D7
D1
D7
START
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D0
STOP
WRITE COMMAND
REGISTER ADDRESS
Figure 55. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. B | Page 38 of 44
ADT7316/ADT7317/ADT7318
CS
1
8
1
8
SCLK
X
X
D6
X
X
DIN
D7
D5
X
D4
X
D3
X
D1
X
D0
X
X
X
X
D2
X
X
X
D0
D7
D6
D5
D4
D3
D2
D1
DOUT
X
STOP
START
READ COMMAND
DATA BYTE 1
Figure 56. SPI —Reading a Single Byte of Data From a Selected Register
CS
1
8
1
8
SCLK
DIN
D6
X
D7
D5
X
D4
X
D3
X
D1
X
D0
X
X
X
X
X
X
X
D2
X
DOUT
X
X
D7
D6
D5
D4
D3
D2
D0
X
D1
START
DATA BYTE 1
READ COMMAND
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
X
X
X
X
X
X
X
X
DOUT (CONTINUED)
D6
D5
D4
D3
D1
D0
D7
D2
STOP
DATA BYTE 2
Figure 57. SPI—Reading Two Bytes of Data From Two Sequential Registers
CS
SPI
READ OPERATION
WRITE OPERATION
CS
Figure 58. SPI—Correct Use of During SPI Communication
Read Operation
following eight clock cycles, the data contained in the register
selected by the address pointer register is output onto the
DOUT line. Data is output onto the DOUT line on the falling
edge of SCLK. Figure 57 shows the procedure when reading
data from two sequential registers. Multiple data reads are
possible in SPI interface mode as the address pointer register is
auto-incremental. The address pointer register auto-increments
from Address 0x00 to Address 0x3F and loops back to start all
over again at Address 0x00 when it reaches Address 0x3F.
Figure 56 and Figure 57 show the timing diagrams necessary
to accomplish correct read operations. To read back from a
register, first write to the address pointer register with the
address of the register to read from, as shown in Figure 53.
Figure 56 shows the procedure for reading back a single byte
of data. The read command is first sent to the part during the
first eight clock cycles. As the read command is being sent,
irrelevant data is output onto the DOUT line. During the
Rev. B | Page 39 of 44
ADT7316/ADT7317/ADT7318
INT
INT
SMBUS/SPI INT/
One or more INT/
outputs can be connected to a common
SMBALERT
SMBALERT
line connected to the master. When a
INT
The ADT7316/ADT7317/ADT7318 INT/
output is an
line is pulled low by one of the devices, the following procedure
occurs (see Figure 59).
interrupt line that signals an over-limit/under-limit event on
any of the measurement channels if the interrupt on that event
has not been disabled. The ADT7316/ADT7317/ADT7318 are
MASTER
RECEIVES
SMBALERT
INT
slave-only devices and use the SMBus/SPI INT/
only means to signal other devices that an event has occurred.
INT
as their
ALERT RESPONSE
ADDRESS
NO
ACK
START
RD ACK DEVICE ADDRESS
STOP
The INT/
the outputs of several devices to be wire-AND’ed together when
INT
pin has an open-drain configuration that allows
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
the INT/
ration 1 register (Address 0x18) to set the active polarity of the
INT
pin is active low. Use C6 of the Control Configu-
INT
SMBALERT
ARA
Figure 59. INT/
Responds to
SMBALERT
1.
is pulled low.
INT/
INT
output. The power-up default is active low. The INT/
output can be disabled or enabled by setting C5 of the
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
Control Configuration 1 register (Address 0x18) to 1 or 0,
respectively.
INT
3. The devices whose INT/
output is low respond to the
INT
The INT/
output becomes active when either the internal
alert response address and the master reads its device
address. Because the device address is 7 bits long, an LSB
of 1 is added. The address of the device is now known and
it can be interrogated in the usual way.
temperature value, the external temperature value, or the VDD
value exceeds the values in their corresponding THIGH/VHIGH or
INT
TLOW/VLOW registers. The INT/
output goes inactive again
when a conversion result indicates that all measurement channels
are within their trip limits, and when the status register associ-
ated with the out-of-limit event is read. The two interrupt status
INT
4. If more than one devices INT/
output is low, the one
with the lowest device address has priority, in accordance
with typical SMBus specifications.
INT
registers show which event caused the INT/
pin to go active.
output requires an external pull-up resistor. This
can be connected to a voltage different from VDD provided that
INT
INT
The INT/
5. Once the ADT7316/ADT7317/ADT7318 has responded
INT
to the alert response address, it resets its INT/
output,
the maximum voltage rating of the INT/
output pin is not
provided that the condition that caused the out-of-limit
event no longer exists and the status register associated with
exceeded. The value of the pull-up resistor depends on the
application but should be large enough to avoid excessive sink
SMBALERT
the out-of-limit event is read. If the
line remains
INT
currents at the INT/
output, which can heat the chip and
low, the master sends the ARA again. It continues to do this
affect the temperature reading.
SMBALERT
until all devices whose
responded.
outputs were low have
SMBUS Alert Response
MASTER
ACK
MASTER
NACK
DEVICE ACK
MASTER
RECEIVES
INT
The INT/
when the SMBus/I2C interface is selected. It is an open-drain
INT
pin behaves the same way as a SMBus alert pin
SMBALERT
ALERT RESPONSE
DEVICE
ADDRESS
NO
ACK
START
RD ACK
ACK
PEC
STOP
output and requires a pull-up to VDD. Several INT/
can be wire-AND’ed together so that the common line goes low
INT
outputs
ADDRESS
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS DEVICE SENDS
ITS ADDRESS ITS PEC DATA
if one or more of the INT/
outputs goes low. The polarity
pin must be set for active low for a number of
INT
INT
of the INT/
outputs to be wire-AND’ed together. The INT/
SMBALERT
INT
SMBALERT
ARA with
Figure 60. INT/
Responds to
output can
function. Slave devices on the SMBus
typically cannot signal to the master that they want to talk, but
SMBALERT SMBALERT
Packet Error Checking (PEC)
operate as a
the
function allows them to do so.
is
used in conjunction with the SMBus general call address.
Rev. B | Page 40 of 44
ADT7316/ADT7317/ADT7318
LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from noise,
particularly when measuring the very small voltages from a
remote diode sensor. Take the following precautions:
•
Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/ solder joints
are used, make sure that they are in both the D+ and D−
paths and at the same temperature. Thermocouple effects
should not be a major problem as 1°C corresponds to about
240 μV, and thermocouple voltages are about 3 μV/°C of
the temperature difference. Unless there are two thermo-
couples with a big temperature differential between them,
thermocouple voltages should be much less than 200 mV.
•
Place the ADT7316/ADT7317/ADT7318 as close as
possible to the remote sensing diode. Provided that the
worst noise sources, such as clock generators, data/address
buses, and CRTs are avoided, this distance can be 4 inches
to 8 inches.
•
•
Route the D+ and D− tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground
plane under the tracks if possible.
Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended.
•
•
Place 0.1 μF bypass and 2200 pF input filter capacitors
close to the ADT7316/ADT7317/ADT7318.
If the distance to the remote sensor is more than 8 inches,
the use of the twisted pair cable is recommended. This
works for distances from 6 feet to 12 feet.
•
•
For really long distances (up to 100 feet), use shielded twisted
pair, such as Belden #8451 microphone cable. Connect the
twisted pair to D+ and D− and the shield to GND close to
the ADT7316/ADT7317/ADT7318. Leave the remote end
of the shield unconnected to avoid ground loops.
GND
10 MIL
10 MIL
D+
D–
10 MIL
10 MIL
10 MIL
10 MIL
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect
the measurement. When using long cables, the filter capacitor
may be reduced or removed.
GND
10 MIL
Figure 61. Arrangement of Signal Tracks
Cable resistance can also introduce errors. Series resistance
of 1 Ω introduces about 0.5°C error.
Rev. B | Page 41 of 44
ADT7316/ADT7317/ADT7318
OUTLINE DIMENSIONS
0.197
0.193
0.189
16
1
9
8
0.158
0.154
0.150
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 62. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADT7318ARQ
ADT7318ARQ-REEL
ADT7318ARQ-REEL7
ADT7318ARQZ1
ADT7318ARQZ-REEL1
ADT7318ARQZ-REEL71
ADT7317ARQ
ADT7317ARQ-REEL
ADT7317ARQ-REEL7
ADT7317ARQZ1
ADT7317ARQZ-REEL1
ADT7317ARQZ-REEL71
ADT7316ARQ
ADT7316ARQ-REEL
ADT7316ARQ-REEL7
ADT7316ARQZ1
ADT7316ARQZ-REEL1
ADT7316ARQZ-REEL71
EVAL-ADT7316EB
Temperature Range
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
−40°C to +120°C
DAC Resolution
8-Bits
8-Bits
8-Bits
8-Bits
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
Package Option
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
Ordering Quantity
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
98
2,500
1,000
98
1,000
1,000
98
2,500
1,000
8-Bits
8-Bits
10-Bits
10-Bits
10-Bits
10-Bits
10-Bits
10-Bits
12-Bits
12-Bits
12-Bits
12-Bits
12-Bits
12-Bits
1 Z = Pb-free part.
Rev. B | Page 42 of 44
ADT7316/ADT7317/ADT7318
NOTES
Rev. B | Page 43 of 44
ADT7316/ADT7317/ADT7318
NOTES
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02661-0-1/07(B)
Rev. B | Page 44 of 44
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