ADT7317ARU_技术文档

PRELIMINARY TECHNICAL DATA

SPI/I²C^RCompatible, 10-Bit Digital Temperature

a

Preliminary Technical Data

Sensor and Quad Voltage Output 12/10/8-Bit DAC

ADT7316/7317/7318

FEATURES

GENERAL DESCRIPTION

ADT7316 - Four 12-Bit DACs

ADT7317 - Four 10-Bit DACs

ADT7318 - Four 8-Bit DACs

Buffered Voltage Output

The ADT7316/7317/7318 combines a 10-Bit Tempera-

ture-to-Digital Converter and a quad 12/10/8-Bit DAC

respectively, in a 16-Lead QSOP package. This includes a

bandgap temperature sensor and a 10-bit ADC to monitor

and digitize the temperature reading to a resolution of

0.25 ^oC. The ADT7316/17/18 operates from a single

+2.7 V to + 5.5 V supply. The output voltage of the DAC

ranges from 0 V to V_DD, with an output voltage settling

time of typ 7 msec. The ADT7316/17/18 provides two

serial interface options, a four-wire serial interface which

is compatible with SPI^TM, QSPI^TM, MICROWIRE^TMand

DSP interface standards; and a two-wire I²C interface. It

features a standby mode that is controlled via the serial

interface.

Guaranteed Monotonic By Design Over All Codes

10-Bit Temperature to Digital Converter

Temperature range:

-40^oC to +125^oC

Temperature Sensor Accuracy of 2^oC

Supply Range : + 2.7 V to + 5.5 V

DAC Output Range: 0 - V_REF

Power-Down Current 1µA

Internal 2.25 V_RefOption

Double-BufferedInputLogic

Buffered / Unbuffered Reference Input Option

Power-on Reset to Zero Volts

Simultaneous Update of Outputs (LDAC Function)

On-Chip Rail-to-Rail Output Buffer Amplifier

The reference for the four DACs is derived either inter-

nally or from two reference pins (one per DAC pair) .The

outputs of all DACs may be updated simultaneously using

the software LDAC function or external LDAC pin. The

ADT7316/7317/7318 incorporates a power-on-reset cir-

cuit, which ensures that the DAC output powers-up to

zero volts and it remains there until a valid write takes

place.

I²C, SPI^TM, QSPI^TM, MICROWIRE^TMand DSP-Compatible 5-

wire Serial Interface

16-Lead TSSOP Package

APPLICATIONS

Portable Battery Powered Instruments

Personal Computers

TelecommunicationsSystems

Electronic Test Equipment

Domestic Appliances

The ADT7316/7317/7318’s wide supply voltage range,

low supply current and SPI/I²C-compatible interface,

make it ideal for a variety of applications, including per-

sonal computers, office equipment and domestic appli-

ances.

V

AB

REF

Process Control

2.25 V V

REF

INTERNAL

REFERENCE

GAIN-

SELECT

L OGIC

LD A C

LDAC

FUNCTIONAL BLOCK DIAGRAM

INPUT & DAC

REGISTER

STRING

DAC A

V

A

B UFFER

BUFFER

OUT

INPUT & DAC

REGISTER

STRING

DAC B

B

OUT

INPUT & DAC

REGISTER

STRING

DAC C

C

D

BUFFER

O UT

CS

INTERFACE

L OGIC

STRIN G

DAC D

INPUT & DAC

REGISTER

V

SCL/SCL K

O UT

SDA/D

IN

POWER-DOWN

LOGIC

ON-CHIP

TEMP.

SENSOR

D

/ADD

OUT

2.25 V V

REF

ANALOG

MUX

V

CD

REF

ADDRESS

REGISTER

L IMIT

COMPARATOR

TEMP VALU E

REGISTER

GND

CONFIG.

REGISTER

A/D

CONVERTER

T

MASK

HIGH

V

DD

T

STATUS

LOW

D+ D-

/

ALERT O TI

I²C is a registered trademark of Philips Corporation

* Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, INC.

MICROWIREisatrademarkofNationalSemiconductorCorporation.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

REV. PrH 07/’01

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

Analog Devices, Inc., 2001

PRELIMINARY TECHNICAL DATA

ADT7316/ADT7317/ADT7318-SPECIFICATIONS

Preliminary Technical Data

(V_DD=2.7 V to 5.5 V, GND=0 V, REF_IN=2.25 V, unless otherwise noted)

Parameter¹

Min

Typ

Max

Units

Conditions/Comments

DC PERFORMANCE^3,4

DAC

ADT7318

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

ADT7317

0.15

0.02

1

0.25

Guaranteed Monotonic by design over all codes

Resolution

10

0.5

0.05

Bits

LSB

Relative Accuracy

Differential Nonlinearity

ADT7316

4

0.5

Resolution

12

2

0.02

Bits

LSB

Relative Accuracy

Differential Nonlinearity

INTERNAL TEMPERATURE

SENSOR

16

1

Accuracy

2

3

°C

T_A= 0°C to +85°C

T_A= -40°C to +125°C

Resolution

10

Bits

EXTERNAL TEMPERATURE

SENSOR

Accuracy

2

3

°C

T_A= 0°C to +85°C

°C

T_A= -40°C to +125°C

Resolution

10

Bits

Update Rate, t_R

Temperature Conversion Time

Offset Error

400

25

0.4

0.15

20

tbd

-12

-5

-60

200

µs

3

1

60

tbd

% of FSR

mV

Gain Error

Lower Deadband

Upper Deadband

Offset Error Drift⁵

Gain Error Drift⁵

DCPowerSupplyRejectionRatio⁵

DC Crosstalk⁵

LowerDeadbandexistsonlyifOffsetErrorisNegative

Upper Deadband exists if V_REF= V_DD

mV

ppmofFSR/°C

dB

∆V_DD

=

10%

µV

DAC REFERENCE INPUT⁵

V_REFInput Range

1

0.25

37

V_DD

V

kΩ

MΩ

dB

Buffered Reference Mode

Unbuffered Reference Mode

Normal Operation

Buffered reference mode and Power-Down Mode

Frequency=10KHz

V_REFInput Range

V_REFInput Impedance

45

>10

-90

-80

Reference Feedthrough

Channel-toChannel Isolation

Frequency=10KHz

OUTPUT CHARACTERISTICS⁵

Minimum Output Voltage⁶

Maximum Output Voltage⁶

DC Output Impedance

0.001

V_DD-0.001

V

This is a measure of the minimum and maximum drive

V capability of the output amplifier

0.5

25

16

2.5

5

Ω

m A

µs

Short Circuit Current

V_DD= +5V

V_DD= +3V

Power Up Time

Coming out of Power Down Mode. V_DD= +5 V

Coming out of Power Down Mode. V_DD= +3 V

µs

DIGITAL INPUTS⁵

Input Current

1

0.8

0.6

µ A

V

V_IN= 0V to V_DD

V_DD= +5V 10%

V_DD= +3V 10%

V_IL, Input Low Voltage

V

_IH, Input High Voltage

2

V

Pin Capacitance

2

10

pF

All Digital Inputs

DIGITAL OUTPUT

Output High Voltage, V_OH

Output Low Voltage, V_OL

Output High Current, I_OH

Output Capacitance, C_OUT

ALERTOutputSaturationVoltage

2.4

V

m A

pF

V

I_SOURCE= I_SINK= 200 µA

I_OL= 3 mA

V_OH= 5 V

0.4

1

50

0.8

I_OUT= 4 mA

REV. PrH

–2–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

Parameter¹

Min

Typ

Max

Units

Conditions/Comments

I²CTIMINGCHARACTERISTICS^7,8

SerialClockPeriod,t₁

2.5

0

µs

ns

Fast-Mode I²C. See Figure 1

See Figure 1

Data In Setup Time to SCL High, t₂

DataOutStableafterSCLLow, t₃

SDA Low Setup Time to SCL Low

(StartCondition),t₄

50

See Figure 1

SDAHighHoldTimeafterSCLHigh

(StopCondition),t₅

ns

See Figure 1

SDAandSCLFallTime, t₆

90

SPITIMINGCHARACTERISTICS^9,10

CS to SCLK Setup Time, t₁

SCLKHighPulsewidth,t₂

SCLKLowPulse, t₃

0

50

ns

See Figure 2

DataAccessTimeafter

11

SCLKFallingedge,t₄

35

40

ns

See Figure 2

DataSetupTimePrior

to SCLK Rising Edge, t₅

DataHoldTimeafter

20

SCLKRisingEdge,t₆

0

ns

See Figure 2

CS to SCLK Hold Time, t₇

CS toDOUTHighImpedance

POWER REQUIREMENTS

V_DD

2.7

0.85

1

5.5

1.3

3

V

mA

µA

I_DD(Normal Mode)⁹

I_DD(Power Down Mode)

V_IH= V_DDand V_IL= GND

V_DD= +4.5V to +5.5V, V_IH=V_DDand V_IL=GND

0.5

tbd

1

tbd

µA

µ W

V_DD= +2.7V to +3.6V, V_IH=V_DDand V_IL=GND

V_DD= +2.7 V. Using Normal Mode

V_DD= +2.7 V. Using Shutdown Mode

Power Dissipation

tbd

Notes:

¹SeeTerminology

²Temperature ranges are as follows: B Version: -40°C to +125°C.

³DC specifications tested with the outputs unloaded.

⁴Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)

⁵GuaranteedbyDesignandCharacterization, notproductiontested

⁶In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V_REF=V_DD

and "Offset plus Gain" Error must be positive.

⁷The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I²C specification. Switching off the input filters improves the transfer

rate but has a negative affect on the EMC behaviour of the part.

⁸Guaranteed by design. Not tested in production.

9

Guaranteed by design and characterization, not production tested.

¹⁰All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of 1.6 V.

¹¹Measured with the load circuit of Figure 3.

12

I

spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

DD

Specifications subject to change without notice.

t

1

SCL

t

2

5

4

SDA

DATA IN

t

3

SDA

DATA O UT

t

6

Figure 1. Diagram for I²C Bus Timing

REV. PrH

–3–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

CS

t₁

t₇

t₂

SCLK

DOUT

1

2

3

4

8

t₃

t₈

t₄

DB7

DB6

t₅

DB5

DB0

LSB

DB8

MSB

t₆

DB7

MSB

DB5

DIN

DB6

DB0

LSB

DB8

MSB

Figure 2. Diagram for SPI Bus Timing

DACACCHARACTERISTICS¹

(V_DD= +2.7V to +5.5 V; R_L=2kW to GND; C_L=200pF to GND; All

specifications T_MINto T_MAXunless otherwise noted.)

Parameter²

Min Typ @ 25°C

Max

Units

Conditions/Comments

Output Voltage Settling Time

ADT7318

ADT7317

V_REF=V_DD=+5V

6

7

8

9

10

µs

1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)

1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)

1/4 Scale to 3/4 Scale change (400 Hex to

C00 Hex)

ADT7316

Slew Rate

0.7

12

1

0.5

3

V/µs

nV-s

kHz

dB

Major-Code Change Glitch Energy

Digital Feedthrough

Digital Crosstalk

1 LSB change around major carry.

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

200

-70

V

_REF=2V 0.1Vpp

V_REF=2.5V 0.1Vpp. Frequency=10kHz.

NOTES

¹GuaranteedbyDesignandCharacterization, notproductiontested

²SeeTerminology

Specifications subject to change without notice.

I

200␮A

OL

TO

OUTPUT

1.6V

C

L

50pF

200␮A

I

OL

Figure 3. Load Circuit for Access Time and Bus Relinquish Time

–4–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS*

ADT7316/7317/7318

V_DDto GND

–0.3 V to +7 V

Analog Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Reference input voltage to GND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

–0.3 V to V_DD+ 0.3 V

–0.3 V to V_DD+ 0.3V

–40°C to +105°C

–65°C to +150°C

+150°C

16-Lead TSSOP Package

Power Dissipation

θ_JAThermal Impedance

Reflow Soldering

(T_jmax - T_A) / θ_JA

150 °C/W (QSOP)

Peak Temperature

Time of Peak Temperature

+220 +/- 0°C

10 sec to 40 sec

*StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanent

damage to the device. This is a stress rating only; functional operation of the device

attheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthis

specification is not implied. Exposure to absolute maximum rating conditions for

extendedperiodsmayaffectdevicereliability.

PIN CONFIGURATION

QSOP

V

-B

-A

V

-C

-D

1

16

15

14

13

12

11

10

9

out

2

3

4

5

6

7

8

V

-AB

-CD

ref

ADT7316/

7317/7318

CS

SCL/SCLK

SDA/DIN

DOUT/ADD

LDAC

GND

VDD

D+

TOP VIEW

(Not to Scale)

D-

/O

ALERT TI

ORDERING GUIDE

Model

Temperature Range

DAC Resolution

Package Description

Package Options

ADT7318ARU

ADT7317ARU

ADT7316ARU

–40°C to +125°C

-40°C to +125°C

8-Bits

10-Bits

12-Bits

16-Lead QSOP

RQ-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADT7316/7317/7318 feature proprietary ESD protection circuitry, permanent damage may

occurondevicessubjectedtohighenergyelectrostaticdischarges. Therefore, properESDprecautions

arerecommendedtoavoidperformancedegradationorlossoffunctionality.

WARNING!

ESD SENSITIVE DEVICE

REV. PrH

–5–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

ADT7318 PIN ꢀUNCTION DESCRIPTION

1

Mnemonic

Description

V_OUTB

A

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2

V_OUT

3

V_REFAB

Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input

to each or both of the DACs A and B. It has an input range from 0.25 V to V_DDin unbuffered

mode and from 1 V to V_DDin buffered mode.

4

CS

SPI Active low control Input. This is the frame synchronization signal for the input data.

When CS goes low, it enables the input register and data is transferred in on the rising edges

of the following serial clocks and transferred out on the falling edges.

5

6

7

8

9

GND

V_DD

Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.

Positive Supply Voltage, +2.65 V to +5.25 V.The supply should be decoupled to ground.

Positive connection to external temperature sensor

D +

D-

Negative connection to external temperature sensor

ALERT/OTI

ALERT - SMBus Alert. Open-Drain output. Over temperature indicator, becomes active low

when temperature exceeds either internal or external temperature high limits.

OTI - SPI Temperature Indicator. The output polarity of this pin can be set to give an active

low or active high interrupt when temperature high limits are exceeded.

10

11

LDAC

Active low control input that transfers the contents of the input registers to their respective

DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input

registers have new data. This allows simultaneous update of all DAC outputs. Alternatively

this pin can be tied permanently low.

DOUT/ADD

SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is

clocked out at the falling edge of SCLK.

ADD, I²C serial bus address selection pin. Logic input. During the first valid I²C bus commu-

nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/

18. Any subsequent changes on this pin will have no affect on the I²C serial bus address. A low

on this pin gives the address 1001 000, leaving it floating gives the address 1001 001 and set-

ting it high gives the address 1001 010.

12

SDA/DIN

SDA - I²C Serial Data Input. I²C serial data to be loaded into the parts registers is provided

on this input.

DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on

this input. Data is clocked into a register on the rising edge of SCLK.

13

14

SCL/SCLK

V_REFCD

Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock

data out of any register of the ADT7316/7317/7318 and also to clock data into any register

that can be written to.

Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input

to each or both of the DACs C and D. It has an input range from 0.25 V to V_DDin unbuffered

mode and from 1 V to V_DDin buffered mode.

15

16

V_OUT

D

C

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

V_OUT

–6–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ADT7316/7317/7318

TERMINOLOGY

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the

impulse injected into the analog output when the code in

the DAC register changes state. It is normally specified as

the area of the glitch in nV secs and is measured when the

digital code is changed by 1 LSB at the major carry transi-

tion (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to

011 . . . 11).

RELATIVE ACCURACY

Relative accuracy or integral nonlinearity (INL) is a mea-

sure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

function. Typical INL versus Code plots can be seen in

TPCs 1, 2, and 3.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference be-

tween the measured change and the ideal 1 LSB change

between any two adjacent codes. A specified differential

nonlinearity of 1 LSB maximum ensures monotonicity.

This DAC and Temperature Sensor ADC is guaranteed

monotonic by design. Typical DAC DNL versus Code

plots can be seen in TPCs 4, 5, and 6.

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected

into the analog output of a DAC from the digital input

pins of the device but is measured when the DAC is not

being written to the. It is specified in nV secs and is mea-

sured with a full-scale change on the digital input pins,

i.e., from all 0s to all 1s or vice versa.

OFFSET ERROR

DIGITAL CROSSTALK

This is a measure of the offset error of the DAC and the

output amplifier. (See Figures 4 and 5.) It can be negative

or positive. It is expressed in mV.

This is the glitch impulse transferred to the output of one

DAC at midscale in response to a full-scale code change

(all 0s to all 1s and vice versa) in the input register of

another DAC. It is measured in standalone mode and is

expressed in nV secs.

GAIN ERROR

This is a measure of the span error of the DAC. It is the

deviation in slope of the actual DAC transfer characteristic

from the ideal expressed as a percentage of the full-scale

range.

ANALOG CROSSTALK

This is the glitch impulse transferred to the output of one

DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-

scale code change (all 0s to all 1s and vice versa) while

keeping LDAC high. Then pulse LDAC low and monitor

the output of the DAC whose digital code was not

changed. The area of the glitch is expressed in nV secs.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with

changes in temperature. It is expressed in (ppm of full-

scale range)/°C.

GAIN ERROR DRIFT

DAC-TO-DAC CROSSTALK

This is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-

scale range)/°C.

This is the glitch impulse transferred to the output of one

DAC due to a digital code change and subsequent out-

put change of another DAC. This includes both digital

and analog crosstalk. It is measured by loading one of the

DACs with a full-scale code change (all 0s to all 1s and

vice versa) with LDAC low and monitoring the output of

another DAC. The energy of the glitch is expressed in nV

secs.

DC POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by

changes in the supply voltage. PSRR is the ratio of the

change in V_OUTto a change in V_DDfor full-scale output of

the DAC. It is measured in dBs. V_REFis held at 2 V and

V_DDis varied 10ꢀ.

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth.

The multiplying bandwidth is a measure of this. A sine

wave on the reference (with full-scale code loaded to the

DAC) appears on the output. The multiplying band-

width is the frequency at which the output amplitude falls

to 3 dB below the input.

DC CROSSTALK

This is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is

measured with a full-scale output change on one DAC

while monitoring another DAC. It is expressed in µV.

REFERENCE FEEDTHROUGH

TOTAL HARMONIC DISTORTION

This is the ratio of the amplitude of the signal at the

DAC output to the reference input when the DAC output

is not being updated (i.e., LDAC is high). It is expressed

in dBs.

This is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used

as the reference for the DAC, and the THD is a measure of

the harmonics present on the DAC output. It is measured

in dBs.

CHANNEL-TO-CHANNEL ISOLATION

This is the ratio of the amplitude of the signal at the out-

put of one DAC to a sine wave on the reference input of

another DAC. It is measured in dBs.

REV. PrH

–7–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318 Preliminary Technical Data

GAIN ERROR

+

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

DAC CODE

ACTUA L

IDEAL

LOWER

DEADBAND

CODES

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

Figure 4. Transfer Function with Negative Offset

GAIN ERROR

+

OFFSET ERROR

UPPER

DEADBAND

CODES

OUTPUT

VOLTAGE

ACTUAL

IDEAL

POSITIVE

OFFSET

ERROR

FULL SCALE

DAC CODE

Figure 5. Transfer Function with Positive Offset (V_REF= V_DD

)

–8–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data ADT7316/7317/7318

1.0

0.5

0

12

8

3

2

1

0

T

= 25؇ C

A

T

V

= 25؇C

A

T

V

= 25؇ C

A

V

= 5V

DD

= 5V

DD

= 5V

DD

4

0

-1

-4

-8

-0.5

-2

-3

-1.0

-12

0

50

100

150

CODE

200

250

0

1000

2000

3000

4000

0

200

400

600

800

1000

CODE

TPC 1. ADT7318 Typical INL Plot

TPC 2. ADT7317 Typical INL Plot

TPC 3. ADT7316 Typical INL Plot

0.

3

2

1

0.6

T

V

= 2 5 ؇C

T

= 25؇C

A

= 5 V

V

= 5V

DD

0.4

0.2

0

- 0.

1

-0.2

2

-0.4

-0.6

3

0

5 0

1 00

1 5 0

2 00

2 5

0

200

400

600

800

1000

C ODE

CODE

TPC 5. ADT7317 Typical DNL Plot

TPC 6. ADT7316 Typical DNL Plot

TPC 4. ADT7318 Typical DNL Plot

0.5

1

V

T

= 5V

V

= 5V

= 3V

DD

V

= 5V

= 2V

0.4

0.3

0.2

0.1

0

DD

= 25 C

؇

A

REF

MAX INL

0.25

0

0.5

0

MAX DNL

GAIN ERROR

-0.1

MIN DNL

MIN INL

3

OFFSET ERROR

MIN DNL

-0.2

-0.3

-0.4

-0.5

-0.25

-0.5

MIN INL

80

-1

0

1

2

4

5

؊40

0

40

120

؊40

0

40

80

120

ؠ

V

- V

ؠ

REF

TEMPERATURE -

C

TEMPERATURE -

C

TPC 7. ADT7318 INL and DNL

Error vs V_REF

TPC 8. ADT7318 INL Error and DNL

Error vs Temperature

TPC 9. ADT7318 Offset Error and Gain

Error vs Temperature

REV. PrH

–9–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

0.2

0.1

5

4

3

2

600

500

T

= 25 C

؇

A

V

= 2V

5V SOURCE

3V SOURCE

REF

GAIN ERROR

0

T

V

= 25؇C

A

= 5V

= 2V

DD

400

300

200

100

-0.1

REF

-0.2

-0.3

-0.4

-0.5

OFFSET ERROR

1

0

3V SINK

5V SINK

-0.6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

ZERO-SCALE

FULL-SCALE

V

- Volts

DD

SINK/SOURCE CURRENT - mA

CODE

TPC 10. Offset Error and Gain

Error vs V_DD

TPC 11. V_OUTSource and Sink Current

Capability

TPC 12. Supply Current vs. DAC Code

600

0.5

0.4

T

V

؇

= 25 C

-40؇C

A

5µs

= 5V

+25؇C

DD

REF

500

= 5V

CH1

CH2

V

A

OUT

400

+105؇C

0.3

300

200

100

0

SCLK

-40

C

؇

0.2

0.1

0

+25 C

؇

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

+105 C

؇

2.5

3.5

4.5

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

4.0

- Volts

5.0

3.

0

V

- Volts

DD

TPC 13. Supply Current vs. Supply Volt- TPC 14. Power-Down Current vs. Supply TPC 15. Half-Scale Settling (1/4 to 3/4

age

Voltage

Scale Code Change)

10

0

2.50

2.49

T

V

= 25؇C

A

= 5V

DD

= 2V

REF

-10

CH1

V

A

OUT

-20

-30

2.4

8

-40

PD

CH2

-50

-60

CH1 500mV, CH2 5.00V, TIME BASE = 1␮s/DIV

2.47

0.01

0.1

1

10

100

1k

10k

1␮s/DIV

FREQUENCY - kHz

TPC 16. Exiting Power-Down to Midscale TPC 17. ADT7316 Major-Code Transition TPC18. MultiplyingBandwidth(Small-

GlitchEnergy

Signal Frequency Response)

–10–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ADT7316/7317/7318

0.02

V

T

= 5V

DD

= 25

؇

C

A

0.01

0

-0.01

-0.02

0

1

2

3

4

5

6

150ns/DIV

V

- Volts

REF

TPC 19. Full-Scale Error vs. V_REF

TPC 20. DAC-to-DAC Crosstalk

REV. PrH

–11–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

FUNCTIONAL DESCRIPTION - DAC

Preliminary Technical Data

DAC Reference Inputs

There is a reference pin for each pair of DACs. The refer-

ence inputs are buffered but can also be individually con-

figured as unbuffered. The advantage with the buffered

input is the high impedance it presents to the voltage

source driving it. However if the unbuffered mode is used,

the user can have a reference voltage as low as 0.25 V and

as high as V_DDsince there is no restriction due to head-

room and footroom of the reference amplifier.

The ADT7316/7317/7318 has quad resistor-string DACs

fabricated on a CMOS process with a resolutions of 12,

10 and 8 bits respectively. They contain four output buffer

amplifiers and is written to via I²C serial interface or SPI

serial interface. Selection between the two types of inter-

face is done on the first valid serial communication. If the

first valid serial communication to the part is I²C then the

internal interface circuit will be locked to I²C communica-

tion. The same holds for SPI interfacing.

The ADT7316/7317/7318 operates from a single supply

of 2.5 V to 5.5 V and the output buffer amplifiers provide

rail-to-rail output swing with a slew rate of 0.7V/µs.

DACs A and B share a common reference input, namely

V_REFAB. DACs C and D share a common reference input,

namely V_REFCD. Each reference input may be buffered to

draw virtually no current from the reference source, or

unbuffered to give a reference input range from GND to

V_DD. The devices have a power-down mode, in which all

DACs may be turned off completely with a high-imped-

ance output.

R

TO OUTPUT

R

AMPLIꢀIER

Digital-to-Analog Section

R

The architecture of one DAC channel consists of a resis-

tor-string DAC followed by an output buffer amplifier.

The voltage at the V_REFpin provides the reference voltage

for the corresponding DAC. Figure 4 shows a block dia-

gram of the DAC architecture. Since the input coding to

the DAC is straight binary, the ideal output voltage is

given by:

Figure 5. Resistor String

If there is a buffered reference in the circuit , there is no

need to use the on-chip buffers. In unbuffered mode the

input impedance is still large at typically 90 kΩ per refer-

ence input for 0-V_REFmode and 45 kΩ for 0-2V_REFmode.

V_REF* D

V_OUT= ----------

2^N

where D=decimal equivalent of the binary code which is

loaded to the DAC register;

The buffered/unbuffered option is controlled by the con-

figuration register (see data register descriptions).

0-255 for ADT7318 (8-Bits)

0-1023 for ADT7317 (10-Bits)

0-4095 for ADT7316 (12-Bits)

There is also an option to use the internal temperature

reference. This option is controlled by the configuration

register.

N = DAC resolution.

Output Amplifier

V

AB

REꢀ

The output buffer amplifier is capable of generating out-

put voltages to within 1mV of either rail. Its actual range

depends on the value of V_REF, GAIN and offset error.

If a gain of 1 is selected (GAIN=0) the output range is

GAIN MODE

REꢀERENCE

BUꢀꢀER

(GAIN= 1 or 2)

BUꢀ

0.001 V to V_REF

.

V

A

OUT

If a gain of 2 is selected (GAIN=1) the output range is

0.001 V to 2V_REF. However because of clamping the maxi-

mum output is limited to V_DD- 0.001V.

RESISTOR

STRING

DAC

REGISTER

INPUT

REGISTER

OUTPUT BUꢀꢀER

AMPLIꢀIER

The output amplifier is capable of driving a load of 2kΩ

to GND or V_DD,in parallel with 500pF to GND or V_DD

The source and sink capabilities of the output amplifier

can be seen in the plot in TPC tbd.

.

Figure 4. Single DAC channel architecture

The slew rate is 0.7V/µs with a half-scale settling time to

+/-0.5 LSB (at 8 bits) of 6µs.

Resistor String

The resistor string section is shown in Figure 5. It is sim-

ply a string of resistors, each of value R. The digital code

loaded to the DAC register determines at what node on

the string the voltage is tapped off to be fed into the out-

put amplifier. The voltage is tapped off by closing one of

the switches connecting the string to the amplifier. Be-

cause it is a string of resistors, it is guaranteed monotonic.

FUNCTIONAL DESCRIPTION - Temperature Sensor

The ADT7316/7317/7318 contains a two-channel A to D

converter with special input signal conditioning to enable

operation with external and on-chip diode temperature

sensors. When the ADT7316/7317/7318 is operating nor-

–12–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ADT7316/7317/7318

mally, the A to D converter operates in a free-running

mode. The analog input multiplexer alternately selects

either the on-chip temperature sensor to measure its inter-

nal temperature, or a external temperature sensor. These

signals are digitized by the ADC and the results stored in

the Internal and External Temperature Value Registers.

stored in two's complement format, as shown in Table 1.

The thermal characteristics of the measurement sensor

could change and therefore an offset is added to the mea-

sured value to enable the transfer function to match the

thermal characteristics. This offset is added before the

temperature data is stored. The offset value used is stored

in the Internal Temperature Offset Register.

The measured results are compared with the Internal and

External, High, Low and the temperature limits are stored

in on-chip registers. Out of limit comparisons generate

flags that are stored in the Status Register and one or

more out-of limit results will cause the ALERT/OTI out-

put to pull low.

EXTERNAL TEMPERATURE MEASUREMENT

The ADT7316/7317/7318 can measure the temperature of

one external diode sensor or diode-connected transistor.

The forward voltage of a diode or diode-connected tran-

sistor, operated at a constant current, exhibits a negative

temperature coefficient of about -2mV/^oC. Unfortunately,

the absolute value of V_be, varies from device to device, and

individual calibration is required to null this out, so the

technique is unsuitable for mass-production.

Theoretically, the temperature sensor and ADC can mea-

sure temperatures from -128^oC to +127^oC with a resolu-

tion of 0.25^oC. However, temperatures below T_MINand

above T_MAXare outside the operating temperature range of

the device, so internal temperature measurements outside

this range are not possible. Temperature measurement

from -128^oC to +127^oC is possible using an external sen-

sor.

The technique used in the ADT7316/7317/7318 is to

measure the change in V_bewhen the device is operated at

two different currents.

This is given by:

Temperature measurement is initiated by a couple of

methods. The first method uses an internal clock count-

down of 20ms and then a conversion is preformed. The

internal oscillator is the only circuit that’s powered up

between conversions and once it times out, every 20ms, a

wake-up signal is sent to power-up the rest of the cir-

cuitry. A monostable is activated at the beginning of the

wake-up signal to ensure that sufficient time is given to

the power-up process. The monostable typically takes 4 µs

to time out. It then takes typically 25µs for each conver-

sion to be completed. The temperature is measured 16

times and internally averaged to reduce noise. The new

temperature value is loaded into the Temperature Value

Register and ready for reading by the I²C or SPI interface.

The user has the option of disabling the averaging by set-

ting a bit in one of the configuration registers. The

ADT7316/7317/7318 defaults on power-up with the aver-

aging enabled.

∆V_be= KT/q x ln(N)

where:

K is Boltzmann’s constant

q is charge on the carrier

T is absolute temperature in Kelvins

N is ratio of the two currents

Figure 6 shows the input signal conditioning used to mea-

sure the output of an external temperature sensor. This

figure shows the external sensor as a substrate transistor,

provided for temperature monitoring on some micropro-

cessors, but it could equally well be a discrete transistor.

If a discrete transistor is used, the collector will not be

grounded, and should be linked to the base. If a PNP

transistor is used the base is connected to the D- input and

the emitter to the D+ input. If an NPN transistor is used,

the emitter is connected to the D- input and the base to

the D+ input.

A temperature measurement is also initiated every time the

oneshot method is used. This method requires the user to

write to the Oneshot register when a temperature measure-

ment is needed. Writing to the Oneshot register will start

a temperature conversion directly after the write operation.

The track/hold goes into hold approximately 4µs

(monostable time-out) and a conversion is then initiated.

Typically 25µs later the conversion is complete. As with

the previous method, the temperature is measured 16

times and internally averaged to reduce noise. The Tem-

perature Value Register is then loaded with a new tem-

perature value. If averaging is disabled for the automatic

method then it subsequently applies to the Oneshot

method also.

We recommend that a 2N3906 be used as the external

transistor.

To prevent ground noise interfering with the measure-

ment, the more negative terminal of the sensor is not ref-

erenced to ground, but is biased above ground by an

internal diode at the D- input. As the sensor is operating

in a noisy environment, C1 is provided as a noise filter.

See the section on layout considerations for more informa-

tion on C1.

To measure ∆V_be, the sensor is switched between operating

currents of I and N x I. The resulting waveform is passed

through a lowpass filter to remove noise, thence to a chop-

per-stabilized amplifier that performs the functions of

amplification and rectification of the waveform to produce

a DC voltage proportional to ∆V_be. This voltage is mea-

sured by the ADC to give a temperature output in 8-bit

two’s complement format. To further reduce the effects of

noise, digital filtering is performed by averaging the re-

sults of 16 measurement cycles.

MEASUREMENT METHOD

INTERNALTEMPERATUREMEASUREMENT

The ADT7316/7317/7318 contains an on-chip bandgap

temperature sensor, whose output is digitized by the on-

chip ADC. The temperature data is stored in the Internal

Temperature Value Register. As both positive and nega-

tive temperatures can be measured, the temperature data is

REV. PrH

–13–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318 Preliminary Technical Data

V

DD

I

N x I

I

BIAS

OPTIONAL CAPACITOR, UP TO

3nF MAX. CAN BE ADDED TO

IMPROVE HIGH FREQUENCY

NOISE REJECTION IN NOISY

ENVIRONMENTS

V

OUT+

D+

C1

D-

TO ADC

REMOTE

SENSING

V

TRANSISTOR

(2N3906)

OUT-

BIAS

DIODE

LOWPASS FILTER

= 65kHz

f

c

Figure 6. Signal Conditioning for External Diode temperature Sensors

TEMPERATURE VALUE FORMAT

Temperature Conversion Formula:

One LSB of the ADC corresponds to 0.25°C. The ADC

can theoretically measure a temperature span of 255 °C.

The internal temperature sensor has a practical low value

limit of -40 °C due to device maximum ratings. It is pos-

sible to measure the full temperature span using the exter-

nal temperature sensor. The temperature data format is

shown in Tables 1.

1. Positive Temperature = ADC Code/4

2. Negative Temperature = (ADC Code* - 512)/4

*DB9 is removed from the ADC Code

ADT7316/7317/7318 REGISTERS

The ADT7316/17/18 contains registers that are used to

store the results of external and internal temperature mea-

surements, high and low temperature limits, set output

DAC voltage levels, configure and control the device. A

description of these registers follows, and further details

are given in Tables 2 to 11.

The result of the internal or external temperature mea-

surements is stored in the temperature value registers, and

is compared with limits programmed into the Internal or

External High and Low Registers.

TABLE 1. Temperature Data Format (Internal and Ex-

ternal Temperature)

Table 2. List of ADT7813 Registers

RD/WR

Address

Name

Power-on

Default

Temperature

Digital Output

-40 °C

11 0110 0000

11 1001 1100

11 1101 1000

11 1111 1111

00 0000 0000

00 0000 0001

00 0010 1000

00 0110 0100

00 1100 1000

01 0010 1100

01 1001 0000

01 1010 0100

3Eh

3Fh

7Eh

7Fh

Manufacturer’s ID

Die Revision Register

Test 1 Register

41h

00h

-25 °C

-10 °C

-0.25 °C

0 °C

Test 2 Register

+0.25 °C

+10 °C

+25 °C

+50 °C

+75 °C

+100 °C

+105 °C

00h

01h

02h

03h

04h

05h

One Shot Register

Configuration Register 1

Configuration Register 2

DAC (LDAC) Mask Register

Mask Register

00h

Internal Temperature Offset Register

06h

External Temperature Offset Register

–14–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data ADT7316/7317/7318

07h

08h

09h

0Ah

0Bh

Internal Temp. High

Internal Temp. Low

External Temp. High

External Temp. Low

DAC A High Register

28h

00h

28h

00h

Bit

Name

Function

7

6

5

4

3

IHigh

ILow

1 when Int. High Temp. is exceeded

1 when Int. Low Temp. is exceeded

1 when Ext. High Temp. is exceeded

1 when Ext. Low Temp is exceeded

1 when Ext Sensor is open circuit

EHigh

ELow

Open

0Ch DAC A Low Register (ADT7316/17 only) 00h

0Dh DAC B High Register 00h

0Eh DAC B Low Register (ADT7316/17 only) 00h

0Fh DAC C High Register 00h

10h DAC C Low Register (ADT7316/17 only) 00h

11h DAC D High Register 00h

12h DAC D Low Register (ADT7316/17 only) 00h

CONFIGURATION REGISTER 1

This Configuration Register is an 8-bit read/write register

that is used to set the operating modes of the ADT7316/

17/18. The 5 MSBs are used to set the operating modes,

see Table 7. D0, D1 and D2 are used for factory settings

and must have zeros written to them during normal opera-

tion.

13h

14h

15h

16h

17h

Interrupt Status Register

00h

Table VI. Configuration Register 1

Int. Temp. Value Register (8 MSBs)

Int. Temp. Value Register (2 LSBs)

Ext. Temp. Value Register (8 MSBs)

Ext. Temp. Value Register (2 LSB)

D7

TI

D6

PD

0*

D5

REF LDAC LDAC N/A

0* 0* 0* 0*

D4

D3

D2

D1

N/A

0*

D0

N/A

0*

*Default settings at Power-up.

Table VII.

Configuration Register 1 Settings

Function

MANUFACTURER’S ID REGISTER (8-BITS)

This register contains the company identification number

for this chip.

Bit

D7

TI

0 = Temperature Indicator ALERT/TI

Enable

1 = Temperature Indicator ALERT/TI

Disable

DIE REVISION REGISTER

This register is divided into the four lsbs representing the

Stepping and the four msbs representing the Version. The

Stepping contains the manufacturers code for minor revi-

sions or steppings to the device. The Version is the

ADT7316/17/18 version number. Since the ADT7316/17/

18 is the first part in this family, it’s version number is

0000b.

D6

PD

This bit is used to power down the DAC

and temperature sensor circuits. In

powerdown mode the serial interface is

still active and the user is capable of

communicating with any register.

1 = Powerdown mode , 0 = Power-up

mode

TEST 1 AND TEST 2 REGISTERS

These registers are used by the manufacturer for testing

purposes. Writing to these registers during normal opera-

tion may lead to erroneous events

D5

REF

1 = External, 0 = Internal

ONE-SHOT REGISTER

D4

D3

Function

The One-Shot Register is a write only register. It is used

to initiate a single temperature conversion and comparison

cycle when the ADT7316/17/18 is in standby mode, after

which the device returns to standby. This is not a data

register as such and it is the write operation that causes the

one-shot conversion. The data written to this address is

irrelevant and is not stored.

0

LSB write to the DAC register generates

LDAC which updates the single addressed

DAC only.

0

1

LSB write to the DAC register generates

LDAC which updates the 2 DACs (in

pairs of DACs A&B or DACs C&D due

to buffer limitations).

INTERRUPT STATUS REGISTER

This 8-bit read only register reflects the status of any of

the interrupts that can cause the ALERT/TI pin to go

active.

1

0

1

LSB write to the DAC register generates

LDAC which updates all four DACs

simultaneously.

LDAC generated from LDAC Register

(4 Bits, 1 per DAC)

Table IV. Status Register (Write)

REV. PrH

–15–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

DACs. Bit 4 is reserved and writing to this bit will have

no affect.

CONFIGURATION REGISTER 2

This Configuration Register is an 8-bit read/write register

that is used to set the operating modes of the ADT7316/

17/18. The 4 MSBs are used to set the operating modes,

see Table XX. D0, D1, D2 and D3 are used for factory

settings and must have zeros written to them during nor-

mal operation.

Table X. Interrupt Mask Register

D7

D6

D5

D4

D3

D2

D1

D0

IH* EH* Open* 0*

LDAC*

* Default setting is 0.

Table xx. Configuration Register 2

Setting D5 to D7 to a 1 will mask out the interrupts rep-

resented by these bits. IH represents the interrupt caused

by Internal T_HIGHregister. EH represents the interrupt

caused by External T_HIGHregister. Open represents the

interrupt caused by an open circuit on D⁺and D^-.

D7

G

D6

Buf_AB Buf_CD

0* 0*

D5

D4

Pol

0*

D3

AR

0*

D2

AI

0*

D1

N/A N/A

0* 0*

D0

0*

* Default settings at Power-up

Table VII.

Function

LDAC Register

Bits

Table xx. Configuration Register 2 Settings

Function

D3

D2

D1

D0

Enables/disables LDAC to update DAC A

Enables/disables LDAC to update DAC B

Enables/disables LDAC to update DAC C

Enables/disables LDAC to update DAC D

Bit

D7

Gain

This bit changes the output range of

all four DACs.

0 = Output range of 0 V to V_ref

1 = Output range of 0 V to 2V_ref

D6

D5

Buf_AB

This bit controls whether the internal

or external reference to DACs A and B

is buffered or unbuffered.

0 = Unbuffered Int/Ext V_ref

1 = Buffered Int/Ext V_ref

Setting D0 to D3 to a 1 disables the LDAC. Example by

setting the register to a value of 1010 (0Ah), this disables

the LDAC in updating DACs A and C.

INTERNAL TEMPERATURE VALUE REGISTER (8

MSBS)

Buf_CD

Polarity

This bit controls whether the internal

or external reference to DACs C and

D is buffered or unbuffered.

0 = Unbuffered Int/Ext V_ref

This Internal Temperature Value Register is a 8-bit read-

only register which stores the temperature reading from

the internal temperature sensor in twos complement for-

mat. This 8 MSBs of the internal temperature reading is

stored in this register.

1 = Buffered Int/Ext V_ref

D4

D3

This bit controls the output polarity of

pin 1 (ALERT/TI).

0 = Active low ALERT/TI

Table xx. Internal Temperature Value Register (First

Read)

1 = Active high ALERT/TI

D7

D6

D5

D4

D3

D2

D1

D0

Alert Reset Reset the ALERT/TI pin if set to 1.

The next temperature conversion will

have the ability to activate the

MSB

B8

B7

B6

B5

B4

B3

B2

ALERT/TI function. The bit status is

not stored, thus this bit will be “0” if

read.

INTERNAL TEMPERATURE VALUE REGISTER (2

LSBS)

This Internal Temperature Value Register is a 8-bit read-

only register which stores the temperature reading from

the internal temperature sensor in twos complement for-

mat. The 2 LSBs of the internal temperature reading is

stored in this register.

D2

Auto

Setting this bit to a 1 enables the Ad-

dress Pointer to be auto-incremented

when reading from or writing to the

registers in Table xx.

0 = Auto-Increment disabled

1 = Auto-Increment enabled

Table xx.

Internal Temperature Value Register (Second

Read)

DAC (LDAC) MASK REGISTER

USE ??????

D7

D6

LSB

D5

D4

D3

D2

D1

D0

B1

0

MASK REGISTER (R/W)

This register can be used to mask out any of the interrupts

that can cause ALERT/TI to go active and can also mask

out the capability of the LDAC signal to update the

–16–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

EXTERNAL TEMPERATURE VALUE REGISTER (8

MSBS)

This External Temperature Value Register is a 8-bit read-

only register which stores the temperature reading from

the external temperature sensor in twos complement for-

mat. The 8 MSBs of the external temperature reading is

stored in this register.

ADT7316/7317/7318

EXTERNAL T_HIGHREGISTER

The External T_HIGHRegister is an 8-bit read/write register

which stores the upper limit that will activate the ALERT/

TI output. Therefore if the value in the Temperature

Value Register is greater than the value in the T_HIGHRegis-

ter, then the ALERT/TI pin is activated (that is if

ALERT/TI is enabled in the Configuration Register). As

it is an 8-bit register the temperature resolution is 1^oC.

Table xx.

External Temperature Value Register (First

Read)

Table X. External T_LOWRegister

D7

MSB

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

B8

B7

B6

B5

B4

B3

B2

MSB B6

B5

B4

B3

B2

B1

B0

EXTERNAL TEMPERATURE VALUE REGISTER (2

LSBS)

EXTERNAL T_LOWREGISTER

The External T_LOWRegister is an 8-bit read/write register

which stores the lower limit that will deactivate the

ALERT/TI output. Therefore if the value in the Tem-

perature Value Register is less than the value in the T_LOW

Register, the ALERT/TI pin is deactivated (that is if

ALERT/TI is enabled in the Configuration Register). As

it is an 8-bit register the temperature resolution is 1^oC.

This External Temperature Value Register is a 8-bit read-

only register which stores the temperature reading from

the external temperature sensor in twos complement for-

mat. The 2 LSBs of the external temperature reading is

stored in this register.

Table xx.

External Temperature Value Register (Second

Read)

Table X. External T_LOWRegister

D7

D6

LSB

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

B1

0

MSB B6

B5

B4

B3

B2

B1

B0

INTERNAL T_HIGHREGISTER

DAC A HIGH REGISTER

The Internal T_HIGHRegister is an 8-bit read/write register

which stores the upper limit that will activate the ALERT/

TI output. Therefore if the value in the Temperature

Value Register is greater than the value in the T_HIGHRegis-

ter, then the ALERT/TI pin is activated (that is if

This 8-bit read/write register contains the digital data for

DAC A to convert to an analog representation. As the

ADT7318 has only an 8-bit DAC this register is all that is

is need for it’s DAC A. But in the case of the ADT7316

(12-Bit) and ADT7317 (10-Bit) this register contains the

8 MSBs of the DAC A word.

ALERT/TI is enabled in the Configuration Register). As

it is an 8-bit register the temperature resolution is 1^oC.

Table xx. DAC A High Register

Table VIIII. Internal T_HIGHRegister

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

MSB B6

B5

B4

B3

B2

B1

B0

MSB B6

B5

B4

B3

B2

B1

B0

DAC A LOW REGISTER (ADT7316/17 ONLY)

This 8-bit read/write register conatins the LSBs of the

DAC A word. In the case of the ADT7317 the 2 LSBs are

stored here and for the ADT7316 the 4 LSBs are stored

here.

INTERNAL T_LOWREGISTER

The Internal T_LOWRegister is an 8-bit read/write register

which stores the lower limit that will deactivate the

ALERT/TI output. Therefore if the value in the Tem-

perature Value Register is less than the value in the T_LOW

Register, the ALERT/TI pin is deactivated (that is if

ALERT/TI is enabled in the Configuration Register). As

it is an 8-bit register the temperature resolution is 1^oC.

Table xx. ADT7317 DAC A Low Register

D7

D6

D5

D4

D3

D2

D1

D0

B1

LSB

0

Table X. Internal T_LOWRegister

Table xx. ADT7316 DAC A Low Register

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

MSB B6

B5

B4

B3

B2

B1

B0

B3

B2

B1

LSB

0

REV. PrH

–17–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

DAC B HIGH REGISTER

Preliminary Technical Data

DAC C HIGH REGISTER

This 8-bit read/write register contains the digital data for

DAC B to convert to an analog representation. As the

ADT7318 has only an 8-bit DAC this register is all that is

is need for it’s DAC B. But in the case of the ADT7316

(12-Bit) and ADT7317 (10-Bit) this register contains the

8 MSBs of the DAC B word.

This 8-bit read/write register contains the digital data for

DAC C to convert to an analog representation. As the

ADT7318 has only an 8-bit DAC this register is all that is

is need for it’s DAC C. But in the case of the ADT7316

(12-Bit) and ADT7317 (10-Bit) this register contains the

8 MSBs of the DAC C word.

Table xx. DAC B High Register

Table xx. DAC C High Register

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

MSB B6

B5

B4

B3

B2

B1

B0

MSB B6

B5

B4

B3

B2

B1

B0

DAC B LOW REGISTER (ADT7316/17 ONLY)

DAC C LOW REGISTER (ADT7316/17 ONLY)

This 8-bit read/write register conatins the LSBs of the

DAC B word. In the case of the ADT7317 the 2 LSBs are

stored here and for the ADT7316 the 4 LSBs are stored

here.

This 8-bit read/write register conatins the LSBs of the

DAC C word. In the case of the ADT7317 the 2 LSBs are

stored here and for the ADT7316 the 4 LSBs are stored

here.

Table xx. ADT7317 DAC B Low Register

Table xx. ADT7317 DAC C Low Register

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

B1

LSB

0

B1

LSB

0

Table xx. ADT7316 DAC B Low Register

Table xx. ADT7316 DAC C Low Register

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

B3

B2

B1

LSB

0

B3

B2

B1

LSB

0

1

9

1

9

SCL

SDA

W

1

0

1

A2

A1

A0

R/

P7

P6

P5

P4

P3

P2

P1

P0

START BY

MASTER

ACK. BY

ADT7316/17/18

ACK. BY

ADT7316/17/18

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS B YTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

Figure xx. I²C - Writing to the Address Pointer Register to select a register for a subsequent Read operation

1

9

1

9

SCL

SDA

W

R/

1

0

1

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

START BY

MASTER

ACK. BY

ADT7316/17/18

ACK. BY

ADT7316/17/18

FRAME 1

SERIAL BUS ADDRESS B YTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

STOP BY

ADT7316/17/18 MASTER

FRAME 3

DATA BYTE

Figure xx. I²C - Writing to the Address Pointer Register followed by a single byte of data to the selected register

–18–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

DAC D HIGH REGISTER

ADT7316/7317/7318

Table xx. ADT7316 DAC D Low Register

This 8-bit read/write register contains the digital data for

DAC D to convert to an analog representation. As the

ADT7318 has only an 8-bit DAC this register is all that is

is need for it’s DAC D. But in the case of the ADT7316

(12-Bit) and ADT7317 (10-Bit) this register contains the

8 MSBs of the DAC D word.

D7

D6

D5

D4

D3

D2

D1

D0

B3

B2

B1

LSB

0

ADT7316/7317/7318 SERIAL INTERFACE

Table xx. DAC D High Register

There are two serial interfaces that can be used on this

part, I²C and SPI. The first valid serial communication

protocol selects the type of interface. The following sec-

tions describe in detail how to use these interfaces.

D7

D6

D5

D4

D3

D2

D1

D0

MSB B6

B5

B4

B3

B2

B1

B0

I²C SERIAL INTERFACE

Like all I²C-compatible devices, the ADT7316/7317/7318

has an 7-bit serial address. The four MSBs of this address

for the ADT7316/7317/7318 are set to 1001. The three

LSBs are set by pin 11, ADD. The ADD pin can be con-

figured three ways to give three different address options;

low, floating and high. Setting the ADD pin low gives a

serial bus address of 1001 000, leaving it floating gives the

address 1001 001 and setting it high gives the address

1001 010.

DAC D LOW REGISTER (ADT7316/17 ONLY)

This 8-bit read/write register conatins the LSBs of the

DAC D word. In the case of the ADT7317 the 2 LSBs are

stored here and for the ADT7316 the 4 LSBs are stored

here.

Table xx. ADT7317 DAC D Low Register

D7

D6

D5

D4

D3

D2

D1

D0

B1

LSB

0

The serial bus protocol operates as follows:

9

1

9

1

SCL

SDA

W

R/

0

1

A2

A1

A 0

P7

P6

P5

P4

P3

P2

P1

P0

START BY

MASTER

ACK. BY

ADT7316/17/18

ACK. BY

ADT7316/17/18

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

1

9

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D6

D4

D1

D0

D6

D3

D1

D7

D5

D3

D2

D7

D5

D4

D2

D0

ACK. BY

STOP BY

ADT7316/17/18

ADT7316/17/18 MASTER

FRAME 3

FRAME 4

DATA BYTE

Figure xx. I²C - Writing to the Address Pointer followed by two data bytes to two Registers with Auto-Increment enabled

1

9

1

9

SCL

SDA

1

0

1

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

W

R/

ACK. BY

ADT7316/17/18

START BY

MASTER

NO ACK. BY STOP BY

MASTER MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRA ME 2

SINGLE DATA BYTE FROM ADT7316/17/18

Figure xx. I²C - Reading a single byte of data from a selected register

REV. PrH

–19–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

Preliminary Technical Data

1. The master initiates data transfer by establishing a

START condition, defined as a high to low transition

on the serial data line SDA whilst the serial clock line

SCL remains high. This indicates that an address/data

stream will follow. All slave peripherals connected to

the serial bus respond to the START condition, and

shift in the next 8 bits, consisting of a 7-bit address

(MSB first) plus a R/W bit, which determines the direc-

tion of the data transfer, i.e. whether data will be writ-

ten to or read from the slave device.

WRITING TO THE ADT7316/7317/7318

Depending on the register being written to, there are three

different writes for the ADT7316/7317/7318.

Writing to the Address Pointer Register for a subsequent

read.

In order to read data from a particular register, the Ad-

dress Pointer Register must contain the address of that

register. If it does not, the correct address must be written

to the Address Pointer Register by performing a single-

byte write operation, as shown in Figure x. The write

operation consists of the serial bus address followed by the

address pointer byte. No data is written to any of the data

registers. A read operation is then performed to read the

register.

The peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low

during the low period before the ninth clock pulse,

known as the Acknowledge Bit. All other devices on the

bus now remain idle whilst the selected device waits for

data to be read from or written to it. If the R/W bit is a

0 then the master will write to the slave device. If the

R/W bit is a 1 the master will read from the slave de-

vice.

Writing a single byte of data to a Register.

All registers are 8-bit registers so only one byte of data

can be written to each register. Writing a single byte of

data to one of these Read/Write registers consists of the

serial bus address, the data register address written to the

Address Pointer Register, followed by the data byte written

to the selected data register. This is illustrated in Figure

x.

2. Data is sent over the serial bus in sequences of 9 clock

pulses, 8 bits of data followed by an Acknowledge Bit

from the receiver of data. Transitions on the data line

must occur during the low period of the clock signal

and remain stable during the high period, as a low to

high transition when the clock is high may be inter-

preted as a STOP signal.

Writing multiple bytes of data to Registers in sequence

In order to write multiple bytes of data in one write opera-

tion the AI bit in Configuration 2 Register must be set to

1. This particular write operation allows data to be written

to registers with sequential addresses without having to

load the Address Pointer Register each time a register is

being written to. The write operation consists of the serial

bus address, the address of the first register to be written

to, followed by the data bytes for each register, as shown

in Figure xx. After each register has been loaded with it’s

data byte, the Address Pointer register increments until all

input data bytes have been loaded or until it reaches the

last read/write register in Table xx, DAC D Low Regis-

ter. The Address Pointer Register will not loop around to

the top of the Register Table.

3. When all data bytes have been read or written, stop

conditions are established. In WRITE mode, the master

will pull the data line high during the 10th clock pulse

to assert a STOP condition. In READ mode, the mas-

ter device will pull the data line high during the low

period before the 9th clock pulse. This is known as No

Acknowledge. The master will then take the data line

low during the low period before the 10th clock pulse,

then high during the 10th clock pulse to assert a STOP

condition.

Any number of bytes of data may be transferred over the

serial bus in one operation, but it is not possible to mix

read and write in one operation, because the type of opera-

tion is determined at the beginning and cannot subse-

quently be changed without starting a new operation.

READING DATA FROM THE ADT7316/7317/7318

Reading data from the ADT7316/7317/7318 can be done

in at least a one byte operation and up to a maximum of a

1

9

1

9

SCL

W

0

A2

A0

R/

D14

D10

D9

D8

SDA

1

A1

D15

D13

D12

D11

START BY

MASTER

ACK. BY

ADT7316/17

ACK. BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7316/17 DAC A HIGH REGISTER

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D6

D5

D3

D1

D7

D4

D2

D0

NO ACK. BY STOP BY

MASTER MASTER

FRAME 3

DATA BYTE FROM ADT7316/17 DA C A LOW REGISTER

Figure xx. I²C - Reading Temperature Value from DAC A High Register and DAC A Low Register

–20–

REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ADT7316/7317/7318

xx byte operation. Reading back the contents of the one

register is a single byte read operation as shown in Figure

x. The register address previously having been set up by a

single byte write operation to the Address Pointer Regis-

ter. If the AI bit in Configuration 2 Register is set to 0

and once the register address has been set up, any number

of reads can be subsequently done from that register with-

out having to write to the Address Pointer Register again.

If you want to read from another register then you will

have to write to the Address Pointer Register again to set

up the relevant register address.

4. Once the ADT7316/17/18 responds to the ARA, it will

reset it’s ALERT output, provided that the error condition

that caused the ALERT no longer exists. If the

SMBALERT line remains low, the master will resend the

ARA again and so on until all devices whose ALERT out-

puts were low have responded.

The ALERT output becomes active when the value in the

Temperature Value Register exceeds the value in the

T_HIGHRegister. It is reset when a write operation to the

Configuration 2 Register sets D3 to a 1 or when the tem-

perature falls below the value stored in the T_LOWRegister.

If the AI bit is set to 1 then it is possible to read data from

a number of registers whose addresses are in sequence. A

two byte read operation is shown in Figure x. The same

rules apply for a two byte read as a single byte read except

that the Address Pointer Register is incremented after each

register is read.

The ALERT output requires an external pull-up resistor.

This can be connected to a voltage different from V_DD

provided the maximum voltage rating of the ALERT out-

put pin is not exceeded. The value of the pull-up resistor

depends on the application, but should be as large as pos-

sible to avoid excessive sink currents at the ALERT out-

put, which can heat the chip and affect the temperature

reading.

SMBUS ALERT

The ADT7316/7317/7318 ALERT output is an SMBus

interrupt line for devices that want to trade their ability to

master for an extra pin. The ADT7316/7317/7318 is a

slave only device and uses the SMBUS ALERT to signal

the host device that it wants to talk. The SMBUS ALERT

on the ADT7316/7317/7318 is used as an over tempera-

ture indicator.

SPI SERIAL INTERFACE

The SPI serial interface of the ADT7316/7317/7318 con-

sists of four wires, CS, SCLK, DIN and DOUT. The CS

is used to select the device when more than one device is

connected to the serial clock and data lines. The SCLK is

used to clock data in and out of the part. The DIN line is

used to write to the registers and the DOUT line is used

to read data back from the registers.

The ALERT pin has an open-drain configuration which

allows the ALERT outputs of several I²C devices to be

wired-AND together when the ALERT pin is active low.

Use D4 of the Configuration 2 Register to set the active

polarity of the ALERT output. The power-up default is

active low. The ALERT function can be disabled or en-

abled by setting D7 of Configuration 1 Register to a 1 or

0 respectively.

The part operates in a slave mode and requires an exter-

nally applied serial clock to the SCLK input. The serial

interface is designed to allow the part to be interfaced to

systems that provide a serial clock that is synchronized to

the serial data.

There are two types of serial operations, a read and a

write. Command words are used to distinguish between a

read and a write operation. These command words are

given in Table xx.

The host device can process the ALERT interrupt and

simultaneously access all SMBUS ALERT devices

through the alert response address. Only the device which

pulled the ALERT low will acknowledge the ARA (Alert

Response Address). If more than one device pulls the

ALERT pin low, the highest priority (lowest address)

device will win communication rights via standard I²C

arbitration during the slave address transfer.

Table xx. SPI COMMAND WORDS

WRITE

READ

90h (1001 0000)

92h (1001 0010)

94h (1001 0100)

91h (1001 0001)

93h (1001 0011)

95h (1001 0101)

MASTER

RECEIVES

SMBALERT

Write Operation

Figure xx. shows the timing diagram for a write operation

to the ADT7316/7317/7318. Data is clocked into the

registers on the rising edge of SCLK. When the CS line is

high the DIN and DOUT lines are in three-state mode.

Only when the CS goes from a high to a low does the part

accept any data on the DIN line. If the Address Pointer

Register has it’s auto-increment enabled then from Figure

xx. the register address gives the first register that will be

written to. Subsequent data bytes will be written into se-

quential writable registers. Thus after each data byte has

been written into a register, the Address Pointer Register

auto increments it’s value to the next available register. If

the auto-increment is disabled and more than one data

byte has been sent to the part in the write operation then

MASTER SENDS ARA AND

DEVICE SENDS

READ COMMAND

IT’S ADDRESS

Figure xx. Use of SMBALERT

1. SMBALERT pulled low

2.Master initiates a read operation and sends the Alert

Response Address (ARA = 0001 100). This is a general

call address that must not be used as a specific device

address.

3. The device whose ALERT output is low responds to

the Alert Response Address and the master reads it’s de-

vice address.

REV. PrH

–21–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318

the part will ignore all data bytes after the first one. To

overwrite the contents of a register another write operation

will have to be performed.

Preliminary Technical Data

OTI Interrupt

The OTI pin can be used to signal an over temperature

event. If the temperature in either the Internal or External

Temperature Value Registers exceeds the T_HIGH(Internal

or External) Registers then the OTI line goes active. Of

course nothing happens if the OTI Interrupt is disabled,

D7 of Configuration Register 1. The OTI interrupt will

be cleared when the temperature goes below the value in

the T_LOW(Internal or External) registers, depending on

whether the internal or external temperature sensor caused

the interrupt. The OTI interrupt can also be cleared by

setting D3 of Configuration Register 2.

Read Operation

Figures xx to xx show the timing diagrams necessary to

acomplish correct read operations. To read back from a

register you first have to write to the Address Pointer Reg-

ister with the address of the register you wish to read

from. This operation is shown in Figure xx. Figure xx

shows the procedure for reading back a single byte of data.

The read command is first sent to the part during the first

8 clock cycles, during the following 8 clock cycles the

data contained in the register selected by the Address

Pointer register is outputted onto the DOUT line. Data is

outputted onto the DOUT line on the rising edge of

SCLK. Figure xx. shows the procedure when reading data

from two sequential registers. Multiple data reads is only

possible if the auto-increment for the Address Pointer

Register has been enabled. If the auto-increment is dis-

abled then the second data byte in Figure xx. will contain

the same as the first data byte because it would have come

from the same register.

CS

1

8

1

SCLK

D7

D6

D5

D3

D1

D0

D5

D2

D0

D_IN

D7

D4

D2

D6

D4

D3

D1

START

WRITE COMMAND

REGISTER ADDRESS

CS (CONTINUED)

1

8

SCLK (CONTINUED)

D6

D3

D1

D_IN(CONTINUED)

D7

D5

D4

D2

D0

DATA BYTE

Figure xx. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register

CS

1

8

1

SCLK

D_IN

D7

D6

D5

D3

D1

D0

D5

D2

D0

D7

D4

D2

D6

D4

D3

D1

STOP

START

WRITE COMMAND

REGISTER ADDRESS

Figure xx. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation

–22– REV. PrH

PRELIMINARY TECHNICAL DATA

Preliminary Technical Data

ADT7316/7317/7318

CS

1

8

1

SCLK

X

D6

X

D5

X

D3

X

D1

X

D0

X

D_IN

D7

X

D4

X

D2

X

D7

D_OUT

D6

D5

D4

D3

D2

D1

D0

STOP

START

READ COMMAND

DATA BYTE 1

Figure xx. SPI - Reading a single byte of data from a selected register

CS

1

8

1

SCLK

X

D6

X

D5

X

D3

X

D1

X

D0

X

D_IN

D7

D4

X

D2

X

D7

D_OUT

X

D6

D5

D4

D3

D2

D1

D0

START

READ COMMAND

DATA BYTE 1

CS (CONTINUED)

1

8

SCLK (CONTINUED)

X

D

_IN(CONTINUED)

D6

D3

D1

D_OUT(CONTINUED)

D7

D5

D4

D2

D0

STOP

DATA BYTE 2

Figure xx. SPI - Reading a two bytes byte of data from a two sequential registers

REV. PrH

–23–

PRELIMINARY TECHNICAL DATA

ADT7316/7317/7318 Preliminary Technical Data

Outline Dimensions

(Dimensions shown in inches and mm )

16-Lead QSOP Package

( RQ-16 )

0.197 (5.00)

0.189 (4.80)

16

9

8

0.157 (3.99)

0.150 (3.81)

0.244 (6.20)

0.228 (5.79)

1

PIN 1

0.069 (1.75)

0.053 (1.35)

0.059 (1.50)

MAX

8^o

0^o

0.010 (0.25)

0.004 (0.10)

0.012 (0.30)

0.008 (0.20)

0.025

(0.64)

SEATING

PLANE

0.010 (0.20)

0.007 (0.18)

BSC

–24–

REV. PrH


型号：	ADT7317ARU
厂家：	ADI
描述：	Switch/Digital Output Temperature Sensor, DIGITAL TEMP SENSOR-SERIAL, 10BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT, QSOP-16 输出元件传感器换能器
文件：	总24页 (文件大小：274K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADT7317ARU [ADI]

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