ADT7318ARQ [ADI]
SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC; SPI / I2C兼容， 10位数字温度传感器和四通道电压输出12 /10/ 8位DAC
| 型号： | ADT7318ARQ |
| 厂家： | 
ADI |
| 描述： | SPI/I2C Compatible, 10-Bit Digital Temperature Sensor and Quad Voltage Output 12/10/8-Bit DAC |
| 文件： | 总32页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
SPI/I2C Compatible, 10-Bit Digital Temperature
a
Preliminary Technical Data
Sensor and Quad Voltage Output 12/10/8-Bit DAC
ADT7316/7317/7318
FEATURES
GENERAL DESCRIPTION
ADT7316 - Four 12-Bit DACs
ADT7317 - Four 10-Bit DACs
ADT7318 - Four 8-Bit DACs
Buffered Voltage Output
The ADT7316/7317/7318 combines a 10-Bit Tempera-
ture-to-Digital Converter and a quad 12/10/8-Bit DAC
respectively, in a 16-Lead QSOP package. This includes a
bandgap temperature sensor and a 10-bit ADC to monitor
and digitize the temperature reading to a resolution of
0.25oC. The ADT7316/17/18 operates from a single
+2.7V to +5.5V supply. The output voltage of the DAC
ranges from 0 V to 2VREF , with an output voltage settling
time of typ 7 msec. The ADT7316/17/18 provides two
serial interface options, a four-wire serial interface which
is compatible with SPITM, QSPITM, MICROWIRETM and
DSP interface standards; and a two-wire I2C interface. It
features a standby mode that is controlled via the serial
interface.
Guaranteed Monotonic By Design Over All Codes
10-Bit Temperature to Digital Converter
Temperature range:
-40oC to +125oC
Temperature Sensor Accuracy of 0.5oC
Supply Range : + 2.7 V to + 5.5 V
DAC Output Range: 0 - 2VREF
Power-Down Current 1µA
Internal 2.25 VRef Option
Double-BufferedInputLogic
Buffered / Unbuffered Reference Input Option
Power-on Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
On-Chip Rail-to-Rail Output Buffer Amplifier
The reference for the four DACs is derived either inter-
nally or from two reference pins (one per DAC pair) .The
outputs of all DACs may be updated simultaneously using
the software LDAC function or external LDAC pin. The
ADT7316/7317/7318 incorporates a power-on-reset cir-
cuit, which ensures that the DAC output powers-up to
zero volts and it remains there until a valid write takes
place.
I2C , SPITM, QSPITM, MICROWIRETM and DSP-Compatible 4-
wire Serial Interface
16-Lead QSOP Package
APPLICATIONS
Portable Battery Powered Instruments
Personal Computers
TelecommunicationsSystems
Electronic Test Equipment
Domestic Appliances
The ADT7316/7317/7318’s wide supply voltage range,
low supply current and SPI/I2C-compatible interface,
make it ideal for a variety of applications, including per-
sonal computers, office equipment and domestic appli-
ances.
Process Control
ADDRESS POINTER
REGISTER
ON-CHIP
TEMPERATURE
SENSOR
INTERNAL TEMPERATURE
VALUE REGISTER
STRING
DAC A
DAC A
REGISTERS
VOUT-A
THIGH LIMIT
2
REGISTERS
TLOW LIMIT
VDD
D+
D-
7
8
A-TO-D
CONVERTER
REGISTERS
ANALOG
MUX
LIMIT
COMPARATOR
DA C B
REGISTERS
STRING
DA C B
VALUE
REGISTER
VOUT-B
1
VDD Lim it
REGISTERS
CONTROL CONFIG. 1
REGISTER
DAC C
REGISTERS
VDD
STRING
DA C C
EXTERNAL TEMPERATURE
VALUE REGISTER
VOUT-C
16
SENSOR
CONTROL CONFIG. 2
REGISTER
STRING
DA C D
DAC D
REGISTERS
VOUT-D
CONTROL CONFIG. 3
REGISTER
15
10
DAC CONFIGURATION
REGISTER
GAIN
SELECT DOWN
LOGIC
POWER
ADT7316/17/18
LDAC CONFIGURATION
REGISTER
LOGIC
STATUS
REGISTERS
INTERRUPT MASK
REGISTERS
INTERRUPT
SMB us/SPI INTERFACE
INTERNAL TEMP
SENSOR
14
VREF-CD
6
VDD
5
GND
3
9
4
13
12
11
DOUT/ADD
VREF-A B
LDAC
CS SCL/SCLK SDA/DIN
FUNCTIONAL BLOCK DIAGRAM
REV. PrN 02/02
I2C is a registered trademark of Philips Corporation
* Protected by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, INC.
MICROWIREisatrademarkofNationalSemiconductorCorporation.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADT7316/ADT7317/ADT7318-SPECIFICATIONS1
(VDD=2.7 V to 5.5 V, GND=0 V, REFIN=2.25 V, unless otherwise noted)
Parameter2
Min
Typ
Max
Units
Conditions/Comments
DACDCPERFORMANCE3,4
ADT7318
Resolution
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
ADT7317
8
0.15
tbd
Bits
LSB
LSB
LSB
1
tbd
0.25
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
0.02
Resolution
10
Bits
LSB
LSB
LSB
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
ADT7316
0.5
tbd
0.05
4
tbd
0.5
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
Resolution
12
2
tbd
0.02
0.4
Bits
LSB
LSB
Relative Accuracy
Relative Accuracy
Differential Nonlinearity
Offset Error
16
tbd
0.9
3
Excluding Offset and Gain errors
Guaranteed Monotonic by design over all codes
LSB
% of FSR
Offset Error Match
Gain Error
Gain Error Match
0.5
1.25
0.5
60
LSB
% of FSR
LSB
0.3
20
Lower Deadband
mV
Lower Deadband exists only if Offset Error is
Negative. See Figure 5.
Upper Deadband
tbd
tbd
mV
Upper Deadband exists if VREF = VDD and Offset
plus Gain Error is positive. See Figure 6.
Offset Error Drift6
Gain Error Drift6
-12
-5
-60
200
ppmofFSR/°C
ppmofFSR/°C
dB
DCPowerSupplyRejectionRatio6
DC Crosstalk6
∆VDD
=
10%
µV
RL = 2 KΩ to GND or VDD
THERMALCHARACTERISTICS
InternalReferenceused.
INTERNALTEMPERATURE
SENSOR
Accuracy @ VDD=3.3V
2
3
°C
°C
°C
TA = 0°C to +85°C
TA = -40°C to +125°C
TA = 0°C to +85°C
TA = -40°C to +125°C
Accuracy @ VDD=5V
2
3
°C
Resolution
10
Bits
Long Term Drift
0.5
°C/1000hrs
EXTERNAL TEMPERATURE
SENSOR
External Transistor = 2N3906.
TA = 0°C to +85°C.
Accuracy @ VDD=3.3V
2
3
°C
°C
°C
TA = -40°C to +125°C
TA = 0°C to +85°C
Accuracy @ VDD=5V
Resolution
2
3
°C
TA = -40°C to +125°C
10
Bits
Update Rate, tR
TBD
TBD
TBD
180
11
µs
µs
µs
µA
µA
Round Robin5 enabled
Round Robin disabled
TemperatureConversionTime
Output Source Current
High Level
Low Level
VOLTAGE OUTPUT
8-Bit DAC Output
Resolution
1
°C
Scale Factor
8.79
17.58
mV/°C
mV/°C
0-VREF Output. TA = -40°C to +125°C
0-2VREF Output. TA = -40°C to +125°C
10-Bit DAC Output
Resolution
0.25
°C
REV. PrN
–2–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Parameter2
Scale Factor
Min
Typ
Max
Units
Conditions/Comments
2.2
4.39
mV/°C
mV/°C
0-VREF Output. TA = -40°C to +125°C
0-2VREF Output. TA = -40°C to +125°C
DAC ERTERNAL
REFERENCE INPUT6
VREF Input Range
1
VDD
VDD
V
V
Buffered Reference Mode
Unbuffered Reference Mode
Unbuffered Reference Mode. 0-2 VREF Output Range.
Unbuffered Reference Mode. 0- VREF Output Range.
Buffered reference mode and Power-Down Mode
Frequency=10KHz
VREF Input Range
VREF Input Impedance
0.25
37
74
45
90
>10
-90
-75
kΩ
kΩ
MΩ
dB
dB
Reference Feedthrough
Channel-toChannel Isolation
Frequency=10KHz
ON-CHIP REFERENCE
Reference Voltage6
2.25
80
V
Temperature Coefficient6
ppm/°C
OUTPUT CHARACTERISTICS6
Output Voltage7
0.001
VDD-0.001
V
This is a measure of the minimum and maximum drive
capability of the output amplifier
DC Output Impedance
Short Circuit Current
0.5
25
16
2.5
5
Ω
m A
m A
µs
VDD = +5V
VDD = +3V
Power Up Time
Coming out of Power Down Mode. VDD = +5 V
Coming out of Power Down Mode. VDD = +3 V
µs
DIGITAL INPUTS6
Input Current
1
0.8
0.6
µ A
V
V
VIN = 0V to VDD
VDD = +5V 10%
VDD = +3V 10%
VIL, Input Low Voltage
V
IH, Input High Voltage
1.89
2.4
V
pF
ns
Pin Capacitance
SCL, SDA Glitch Rejection
3
10
50
All Digital Inputs
Input Filtering Suppresses Noise Spikes of Less than 50
ns
DIGITAL OUTPUT
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
ALERTOutputSaturationVoltage
V
V
m A
pF
V
ISOURCE = ISINK = 200 µA
IOL = 3 mA
0.4
1
50
0.8
VOH = 5 V
IOUT = 4 mA
I2CTIMINGCHARACTERISTICS8,9
SerialClockPeriod,t1
2.5
0
µs
ns
ns
Fast-Mode I2C. See Figure 1
See Figure 1
Data In Setup Time to SCL High, t2
DataOutStableafterSCLLow, t3
SDA Low Setup Time to SCL Low
(StartCondition),t4
50
50
See Figure 1
SDAHighHoldTimeafterSCLHigh
(StopCondition),t5
ns
ns
See Figure 1
See Figure 1
SDAandSCLFallTime, t6
90
SPITIMINGCHARACTERISTICS10,11
CS to SCLK Setup Time, t1
SCLKHighPulsewidth,t2
SCLKLowPulse, t3
0
50
50
ns
ns
ns
See Figure 2
See Figure 2
See Figure 2
DataAccessTimeafter
12
SCLKFallingedge,t4
35
40
ns
ns
See Figure 2
See Figure 2
DataSetupTimePrior
to SCLK Rising Edge, t5
DataHoldTimeafter
20
SCLKRisingEdge,t6
0
0
ns
ns
ns
See Figure 2
See Figure 2
See Figure 2
CS to SCLK Hold Time, t7
CS to DOUT High Impedance, t8
POWER REQUIREMENTS
VDD
2.7
5.5
50
V
ms
VDD Settling Time
VDD settles to within 10% of it’s final voltage
level.
REV. PrN
–3–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
IDD (Normal Mode)13
0.85
1
1.3
3
mA
µA
VIH = VDD and VIL = GND
VDD = +4.5V to +5.5V, VIH=VDD and VIL=GND
IDD (Power Down Mode)
0.5
tbd
tbd
1
tbd
tbd
µA
µ W
µ W
VDD = +2.7V to +3.6V, VIH=VDD and VIL=GND
VDD = +2.7 V. Using Normal Mode
VDD = +2.7 V. Using Shutdown Mode
Power Dissipation
tbd
tbd
Notes:
1 Temperature ranges are as follows: A Version: -40°C to +125°C.
2 SeeTerminology.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5 SeeTerminology.
6 GuaranteedbyDesignandCharacterization, notproductiontested
7 In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, VREF=VDD
"Offset plus Gain" Error must be positive.
,
8 The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I2C specification. Switching off the input filters improves the transfer
rate but has a negative affect on the EMC behaviour of the part.
9 Guaranteed by design. Not tested in production.
10
Guaranteed by design and characterization, not production tested.
11 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
12 Measured with the load circuit of Figure 3.
13
I
spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
DD
Specifications subject to change without notice.
DACACCHARACTERISTICS1
(VDD = +2.7V to +5.5 V; RL=4k7Ω to GND; CL=200pF to GND;
4K7Ω to VDD; All specifications TMIN to TMAX unless otherwise noted.)
Parameter2
Min Typ @ 25°C
Max
Units
Conditions/Comments
Output Voltage Settling Time
ADT7318
ADT7317
VREF=VDD=+5V
1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
1/4 Scale to 3/4 Scale change (400 Hex to
C00 Hex)
6
7
8
8
9
10
µs
µs
µs
ADT7316
Slew Rate
0.7
12
0.5
1
0.5
3
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
1 LSB change around major carry.
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
200
-70
VREF=2V 0.1Vpp
VREF=2.5V 0.1Vpp. Frequency=10kHz.
NOTES
1GuaranteedbyDesignandCharacterization, notproductiontested
2SeeTerminology
Specifications subject to change without notice.
t
1
SCL
t
t
t
2
5
4
SDA
DATA IN
t
3
SDA
DATA O UT
t
6
Figure 1. Diagram for I2C Bus Timing
–4–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
CS
t1
t7
t2
2
1
3
SCLK
DOUT
8
4
t3
t8
t4
DBX
DBX
DB7
MSB
DBX
t5
DBX
t6
DB7
MSB
DB5
DIN
DB6
DB0
LSB
DB8
MSB
Figure 2. Diagram for SPI Bus Timing
I
200A
OL
TO
OUTPUT
PIN
1.6V
C
L
50pF
200A
I
OL
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
DD
V
4Κ7Ω
To DAC
Output
4Κ7Ω
200pF
Figure 4. Load Circuit for DAC Outputs
REV. PrN
–5–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
ABSOLUTE MAXIMUM RATINGS*
VDD to GND
–0.3 V to +7 V
Table 1. I2C Address Selection
I2C Address
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3V
–40°C to +125°C
–65°C to +150°C
+150°C
ADD Pin
Low
1001 000
1001 010
1001 011
Float
High
16-Lead QSOP Package
Power Dissipation
(Tj max - TA) / θJA
θJA Thermal Impedance
Reflow Soldering
150 °C/W (QSOP)
Peak Temperature
Time of Peak Temperature
+220 +/- 0°C
10 sec to 40 sec
*StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanent
damage to the device. This is a stress rating only; functional operation of the device
attheseoranyotherconditionsabovethoseindicatedintheoperationalsectionofthis
specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectdevicereliability.
PIN CONFIGURATION
QSOP
V
V
-B
-A
1
2
3
4
5
6
7
8
V
-C
-D
16
15
14
13
12
11
10
out
out
out
out
V
V
V
-AB
-CD
ref
ref
ADT7316/
7317/7318
SCL/SCLK
SDA/DIN
CS
GND
VDD
D+
TOP VIEW
(Not to Scale)
DOUT/ADD
INTERRUPT
LDAC
9
D-
ORDERING GUIDE
Model
Temperature Range
DAC Resolution
Package Description
Package Options
ADT7318ARQ
ADT7317ARQ
ADT7316ARQ
–40°C to +125°C
-40°C to +125°C
-40°C to +125°C
8-Bits
10-Bits
12-Bits
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
RQ-16
RQ-16
RQ-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADT7316/7317/7318 feature proprietary ESD protection circuitry, permanent damage may
occurondevicessubjectedtohighenergyelectrostaticdischarges. Therefore, properESDprecautions
arerecommendedtoavoidperformancedegradationorlossoffunctionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
ADT7316/7317/7318 PIN FUNCTION DESCRIPTION
Pin
1
Mnemonic
Description
VOUTB
A
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2
VOUT
3
VREFAB
Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input
to each or both of the DACs A and B. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
4
CS
SPI Active low control Input. This is the frame synchronization signal for the input data.
When CS goes low, it enables the input register and data is transferred in and out on the ris-
ing edges of the following serial clocks. This pin must be kept high for I2C mode of operation.
CS is also used as a control pin when selecting the serial interface type after power-up.
5
6
7
8
9
GND
VDD
Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.
Positive Supply Voltage, +2.7 V to +5.5 V.The supply should be decoupled to ground.
Positive connection to external temperature sensor
D +
D-
Negative connection to external temperature sensor
LDAC
Active low control input that transfers the contents of the input registers to their respective
DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data. This allows simultaneous update of all DAC outputs. Bit C3 of Con-
trol Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the
loading of DAC registers.
10 INTERRUPT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active
high interrupt when temperature, VDD and AIN limits are exceeded. Default is active low.
11
DOUT/ADD
SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is
clocked out at the falling edge of SCLK.
ADD, I2C serial bus address selection pin. Logic input. During the first valid I2C bus commu-
nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/
18. Any subsequent changes on this pin will have no affect on the I2C serial bus address. A low
on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and set-
ting it high gives the address 1001 011.
12
SDA/DIN
SDA - I2C Serial Data Input. I2C serial data to be loaded into the parts registers is provided
on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.
13
14
SCL/SCLK
VREFCD
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock
data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.
Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input
to each or both of the DACs C and D. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
15
16
VOUT
D
C
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
VOUT
REV. PrN
–7–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
TERMINOLOGY
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the
DAC output to the reference input when the DAC output
is not being updated (i.e., LDAC is high). It is expressed
in dBs.
RELATIVE ACCURACY
Relative accuracy or integral nonlinearity (INL) is a mea-
sure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. Typical INL versus Code plots can be seen in
TPCs 1, 2, and 3.
CHANNEL-TO-CHANNEL ISOLATION
This is the ratio of the amplitude of the signal at the out-
put of one DAC to a sine wave on the reference input of
another DAC. It is measured in dBs.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference be-
tween the measured change and the ideal 1 LSB change
between any two adjacent codes. A specified differential
nonlinearity of 1 LSB maximum ensures monotonicity.
This DAC and Temperature Sensor ADC is guaranteed
monotonic by design. Typical DAC DNL versus Code
plots can be seen in TPCs 4, 5, and 6.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the
impulse injected into the analog output when the code in
the DAC register changes state. It is normally specified as
the area of the glitch in nV secs and is measured when the
digital code is changed by 1 LSB at the major carry transi-
tion (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).
OFFSET ERROR
This is a measure of the offset error of the DAC and the
output amplifier. (See Figures 5 and 6.) It can be negative
or positive. It is expressed in mV.
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected
into the analog output of a DAC from the digital input
pins of the device but is measured when the DAC is not
being written to the. It is specified in nV secs and is mea-
sured with a full-scale change on the digital input pins,
i.e., from all 0s to all 1s or vice versa.
OFFSET ERROR MATCH
This is the difference in Offset Error between any two
channels.
GAIN ERROR
This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale
range.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one
DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of
another DAC. It is measured in stand-alone mode and is
expressed in nV secs.
GAIN ERROR MATCH
This is the difference in Gain Error between any two
channels.
ANALOG CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa) while
keeping LDAC high. Then pulse LDAC low and monitor
the output of the DAC whose digital code was not
changed. The area of the glitch is expressed in nV secs.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with
changes in temperature. It is expressed in (ppm of full-
scale range)/°C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-
scale range)/°C.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one
DAC due to a digital code change and subsequent out-
put change of another DAC. This includes both digital
and analog crosstalk. It is measured by loading one of the
DACs with a full-scale code change (all 0s to all 1s and
vice versa) with LDAC low and monitoring the output of
another DAC. The energy of the glitch is expressed in nV
secs.
DC POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the
change in VOUT to a change in VDD for full-scale output of
the DAC. It is measured in dBs. VREF is held at 2 V and
VDD is varied 10ꢀ.
DC CROSSTALK
MULTIPLYING BANDWIDTH
This is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC
while monitoring another DAC. It is expressed in µV.
The amplifiers within the DAC have a finite bandwidth.
The multiplying bandwidth is a measure of this. A sine
wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying band-
width is the frequency at which the output amplitude falls
to 3 dB below the input.
–8–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measure of
the harmonics present on the DAC output. It is measured
in dBs.
ROUND ROBIN
This term is used to describe the ADT7316/17/18 cycling
through the available measurement channels in sequence
taking a measurement on each channel.
GAIN ERROR
+
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
ACTUA L
IDEAL
LOWER
DEADBAND
CODES
AMPLIFIER
FOOTROOM
NEGATIVE
OFFSET
ERROR
Figure 5. Transfer Function with Negative Offset
GAIN ERROR
+
OFFSET ERROR
UPPER
DEADBAND
CODES
OUTPUT
VOLTAGE
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
FULL SCALE
DAC CODE
Figure 6. Transfer Function with Positive Offset (VREF = VDD
)
REV. PrN
–9–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
1.0
0.5
0
12
8
3
2
1
0
T
= 25؇ C
A
T
V
= 25؇C
A
T
V
= 25؇ C
A
V
= 5V
DD
= 5V
DD
= 5V
DD
4
0
-1
-4
-8
-0.5
-2
-3
-1.0
-12
0
50
100
150
CODE
200
250
0
1000
2000
3000
4000
0
200
400
600
800
1000
CODE
CODE
TPC 1. ADT7318 Typical INL Plot
TPC 2. ADT7317 Typical INL Plot
TPC 3. ADT7316 Typical INL Plot
0.
0.
0.
3
2
1
0.6
1
T
V
= 2 5 ؇C
T
= 25؇C
T
= 25؇C
A
A
A
= 5 V
V
= 5V
V
= 5V
DD
DD
DD
0.4
0.2
0
0.5
0
0
- 0.
- 0.
- 0.
1
-0.2
-0.5
2
-0.4
-0.6
3
-1
0
5 0
1 00
1 5 0
2 00
2 5
0
200
400
600
800
1000
0
1000
2000
3000
4000
C ODE
CODE
CODE
TPC 5. ADT7317 Typical DNL Plot
TPC 6. ADT7316 Typical DNL Plot
TPC 4. ADT7318 Typical DNL Plot
0.5
0.5
1
V
T
= 5V
V
V
= 5V
= 3V
DD
V
V
= 5V
= 2V
0.4
0.3
0.2
0.1
0
DD
DD
= 25 C
؇
A
REF
REF
MAX INL
MAX INL
0.25
0
0.5
0
MAX DNL
MAX DNL
GAIN ERROR
-0.1
MIN DNL
MIN INL
3
OFFSET ERROR
MIN DNL
-0.2
-0.3
-0.4
-0.5
-0.25
-0.5
-0.5
MIN INL
80
-1
0
1
2
4
5
؊40
0
40
120
؊40
0
40
80
120
ؠ
V
- V
ؠ
REF
TEMPERATURE -
C
TEMPERATURE -
C
TPC 7. ADT7318 INL and DNL
Error vs VREF
TPC 8. ADT7318 INL Error and DNL
Error vs Temperature
TPC 9. ADT7318 Offset Error and Gain
Error vs Temperature
–10–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
0.2
0.1
5
4
3
2
600
500
T
= 25 C
؇
A
V
= 2V
5V SOURCE
3V SOURCE
REF
GAIN ERROR
0
T
V
V
= 25؇C
A
= 5V
= 2V
DD
400
300
200
100
-0.1
REF
-0.2
-0.3
-0.4
-0.5
OFFSET ERROR
1
0
3V SINK
5V SINK
-0.6
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
ZERO-SCALE
FULL-SCALE
V
- Volts
DD
SINK/SOURCE CURRENT - mA
CODE
TPC 10. Offset Error and Gain
Error vs VDD
TPC 11. VOUT Source and Sink Current
Capability
TPC 12. Supply Current vs. DAC Code
600
0.5
0.4
T
V
V
؇
= 25 C
-40؇C
A
= 5V
+25؇C
DD
REF
500
= 5V
CH1
CH2
V
A
OUT
400
+105؇C
0.3
300
200
100
0
SCLK
-40
C
؇
0.2
0.1
0
+25 C
؇
CH1 1V, CH2 5V, TIME BASE= 1s/DIV
+105 C
؇
2.5
3.5
4.5
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.0
- Volts
5.0
3.
0
V
V
- Volts
DD
DD
TPC 13. Supply Current vs. Supply Volt- TPC 14. Power-Down Current vs. Supply TPC 15. Half-Scale Settling (1/4 to 3/4
age
Voltage
Scale Code Change)
10
0
2.50
2.49
T
V
V
= 25؇C
A
= 5V
DD
= 2V
REF
-10
CH1
V
A
OUT
-20
-30
2.4
8
-40
PD
CH2
-50
-60
CH1 500mV, CH2 5.00V, TIME BASE = 1s/DIV
2.47
0.01
0.1
1
10
100
1k
10k
1s/DIV
FREQUENCY - kHz
TPC 16. Exiting Power-Down to Midscale TPC 17. ADT7316 Major-Code Transition TPC18. MultiplyingBandwidth(Small-
GlitchEnergy
Signal Frequency Response)
REV. PrN
–11–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
0.02
V
T
= 5V
DD
= 25
؇
C
A
0.01
0
-0.01
-0.02
0
1
2
3
4
5
6
150ns/DIV
V
- Volts
REF
TPC 19. Full-Scale Error vs. VREF
TPC 20. DAC-to-DAC Crosstalk
2
0
1.5
1
0.5
0
5.5V
0
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
-0.5
-1
3.3V
-1.5
-2
0
0
0
0
0
0
0
0
TEMPERATURE('C)
TITLE
TPC 21. PSRR vs Supply Ripple Frequency
TPC 22. Temperature Error @ 3.3 V and 5.5 V
–12–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
FUNCTIONAL DESCRIPTION - DAC
The ADT7316/7317/7318 has quad resistor-string DACs
fabricated on a CMOS process with a resolutions of 12,
10 and 8 bits respectively. They contain four output buffer
amplifiers and is written to via I2C serial interface or SPI
serial interface. See Serial Interface Selection section for
more information.
VREFAB
Int VREF
GA IN MODE
(GAIN=1 OR 2)
REFERENCE
BUFFER
BUF
VOUT
A
The ADT7316/7317/7318 operates from a single supply
of 2.7 V to 5.5 V and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7V/µs.
DACs A and B share a common reference input, namely
VREFAB. DACs C and D share a common reference input,
namely VREFCD. Each reference input may be buffered to
draw virtually no current from the reference source, or
unbuffered to give a reference input range from GND to
VDD. The devices have a power-down mode, in which all
DACs may be turned off completely with a high-imped-
ance output.
RESISTOR
STRING
DAC
REGISTER
INPUT
REGISTER
OUTPUT BUFFER
AMPLIFIER
Figure 7. Single DAC channel architecture
Resistor String
The resistor string section is shown in Figure 9. It is sim-
ply a string of resistors, each of value R. The digital code
loaded to the DAC register determines at what node on
the string the voltage is tapped off to be fed into the out-
put amplifier. The voltage is tapped off by closing one of
the switches connecting the string to the amplifier. Be-
cause it is a string of resistors, it is guaranteed monotonic.
Each DAC output will not be updated until it receives the
LDAC command. Therefore while the DAC registers
would have been written to with a new value, this value
will not be represented by a voltage output until the DACs
have received the LDAC command. Reading back from
any DAC register prior to issuing an LDAC command
will result in the digital value that corresponds to the
DAC output voltage. Thus the digital value written to the
DAC register cannot be read back until after the LDAC
command has been initiated. This LDAC command can
be given by either pulling the LDAC pin low, setting up
Bits D4 and D5 of DAC Configuration register(Address =
1Bh) or using the LDAC register(Address = 1Ch).
DAC Reference Inputs
There is a reference pin for each pair of DACs. The refer-
ence inputs are buffered but can also be individually con-
figured as unbuffered.
VRE F-AB
2.25 V
Internal V
Digital-to-Analog Section
R EF
The architecture of one DAC channel consists of a resis-
tor-string DAC followed by an output buffer amplifier.
The voltage at the VREF pin or the on-chip reference of
2.25 V provides the reference voltage for the correspond-
ing DAC. Figure 7 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
VREF * D
STRING
DAC A
STRING
DAC B
Figure 8. DAC Reference Buffer Circuit
VOUT = ----------
2N
The advantage with the buffered input is the high imped-
ance it presents to the voltage source driving it. However
if the unbuffered mode is used, the user can have a refer-
ence voltage as low as 0.25 V and as high as VDD since
there is no restriction due to headroom and footroom of
the reference amplifier.
where D=decimal equivalent of the binary code which is
loaded to the DAC register;
0-255 for ADT7318 (8-Bits)
0-1023 for ADT7317 (10-Bits)
0-4095 for ADT7316 (12-Bits)
N = DAC resolution.
REV. PrN
–13–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
nominal value by the time 50ms has elasped then it is
recommended that a measurement be taken on the VDD
channel before a temperature measurement is taken.
R
R
R
TEMPERATURE SENSOR
The ADT7316/7317/7318 contains a two-channel A to D
converter with special input signal conditioning to enable
operation with external and on-chip diode temperature
sensors. When the ADT7316/7317/7318 is operating nor-
mally, the A to D converter operates in a free-running
mode. When in Round Robin mode the analog input mul-
tiplexer sequently selects the VDD input channel, on-chip
temperature sensor to measure its internal temperature and
then the external temperature sensor. These signals are
digitized by the ADC and the results stored in the various
Value Registers.
TO OUTPUT
AMPLIFIER
R
R
The measured results are compared with the Internal and
External, THIGH, TLOW limits. These temperature limits are
stored in on-chip registers. If the temperature limits are
not masked out then any out of limit comparisons generate
flags that are stored in Interrupt Status 1 Register and one
or more out-of limit results will cause the INTERRUPT
output to pull either high or low depending on the output
polarity setting.
Figure 9. Resistor String
If there is a buffered reference in the circuit , there is no
need to use the on-chip buffers. In unbuffered mode the
input impedance is still large at typically 90 kΩ per refer-
ence input for 0-VREF output mode and 45 kΩ for 0-2VREF
output mode.
The buffered/unbuffered option is controlled by the DAC
Configuration Register (address 1Bh, see data register
descriptions). The LDAC Configuration register controls
the option to select between internal and external voltage
references. The default setting is for external reference
selected.
Theoretically, the temperature sensor and ADC can mea-
sure temperatures from -128oC to +127oC with a resolu-
tion of 0.25oC. However, temperatures outside TA are
outside the guaranteed operating temperature range of the
device. Temperature measurement from -128oC to
+127oC is possible using an external sensor.
Output Amplifier
Temperature measurement is initiated by three methods.
The first method is applicable when the part is in single
channel measurement mode. It uses an internal clock
countdown of 20ms and then a conversion is preformed.
The internal oscillator is the only circuit that’s powered
up between conversions and once it times out, every 20ms,
a wake-up signal is sent to power-up the rest of the cir-
cuitry. A monostable is activated at the beginning of the
wake-up signal to ensure that sufficient time is given to
the power-up process. The monostable typically takes 4 µs
to time out. It then takes typically 25µs for each conver-
sion to be completed. The temperature is measured 16
times and internally averaged to reduce noise. The total
time to measure a temperature channel is typically 400us
(25us x 16). The new temperature value is loaded into the
Temperature Value Register and ready for reading by the
I2C or SPI interface. The user has the option of disabling
the averaging by setting a bit (Bit 5) in the Control Con-
figuration Register 2 (address 19h). The ADT7316/7317/
7318 defaults on power-up with the averaging enabled.
The output buffer amplifier is capable of generating out-
put voltages to within 1mV of either rail. Its actual range
depends on the value of VREF, GAIN and offset error.
If a gain of 1 is selected (Bits 0-3 of DAC Configuration
register = 0) the output range is 0.001 V to VREF
.
If a gain of 2 is selected (Bits 0-3 of DAC Configuration
register = 1) the output range is 0.001 V to 2VREF. How-
ever because of clamping the maximum output is limited
to VDD - 0.001V.
The output amplifier is capable of driving a load of 2kΩ
to GND or VDD, in parallel with 500pF to GND or VDD
The source and sink capabilities of the output amplifier
can be seen in the plot in TPC 11.
.
The slew rate is 0.7V/µs with a half-scale settling time to
+/-0.5 LSB (at 8 bits) of 6µs.
FUNCTIONAL DESCRIPTION
Temperature measurement is also initiated after every read
or write to the part when the part is in single channel mea-
surement mode. Once serial communication has started,
any conversion in progress is stopped and the ADC reset.
Conversion will start again immediately after the serial
communication has finished. The temperature measure-
ment proceeds normally as described above.
POWER-UP TIME
On power-up it is important that no communication to the
part is initiated until 200ms after Vcc has settled. During
this 200ms the part is performing a calibration routine and
any communication to the device will interrupt this rou-
tine and could cause erroneous temperature measurements.
VDD must have settled to within 10ꢀ of it’s final value
after 50ms power-on time has elasped. Therefore once
power is applied to the ADT7316/17/18, it can be ad-
dressed 250ms later. If it not possible to have VDD at it’s
The third method is applicable when the part is in round
robin measurement mode. The part measures both the
–14–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
internal and external temperature sensors as it cycles
through all possible measurement channels. The two tem-
perature channels are measured each time the part runs a
round robin sequence. In round robin mode the part is
continously measuring.
6 V
11 0110 1101
11 1011 0110
11 1111 1111
36D
3B6
3FF
6.5 V
7 V
ON-CHIP REFERENCE
VDD MONITORING
The ADT7316/17/18 has an on-chip 1.2 V band-gap
refernece which is gained up by a switched capacitor am-
plifier to give an output of 2.25 V. The amplifier is only
powered up at the start of the conversion phase and is
powered down at the end of conversion. On power-up the
default mode is to have the internal reference selected as
the reference for the DAC and ADC. The internal refer-
ence is always used when measuring the internal and ex-
ternal temperature sensors.
The ADT7316/17/18 also has the capability of monitoring
it’s own power supply. The part measures the voltage on
it’s VDD pin to a resolution of 10 bits. The resultant value
is stored in two 8-bit registers, the two LSBs stored in
register address 03h and the eight MSBs are stored in
register address 06h. This allows the user to have the op-
tion of just doing a one byte read if 10-bit resolution is not
important. The measured result is compared with VHIGH
and VLOW limits. If the VDD interrupt is not masked out
then any out of limit comparison generates a flag in Inter-
rupt Status 2 Register and one or more out-of-limit results
will cause the INTERRUPT output to pull either high or
low depending on the output polarity setting.
ROUND ROBIN MEASUREMENT
On power-up the ADT7316/17/18 goes into Round Robin
mode but monitoring is disabled. Setting Bit C0 of Con-
figuration Register 1 to a 1 enables conversions. It se-
quences through the three channels of VDD , Internal
temperature sensor and External temperature sensor and
takes a measurement from each. At intervals of tbd ms
another measurement cycle is performed on all three chan-
nels. This method of taking a measurement on all three
channels in one cycle is called Round Robin. Setting Bit 4
of Control Configuration 2 (address 19h) disables the
Round Robin mode and in turn sets up the single channel
mode. The single channel mode is where only one chan-
nel, eg. Internal temperature sensor, is measured in each
conversion cycle.
Measuring the voltage on the VDD pin is regarded as moni-
toring a channel. Therefore, along with the Internal and
External temperature sensors the VDD voltage makes up
the third and final monitoring channel. You can select the
VDD channel for single channel measurement by setting Bit
C4 = 1 and setting Bit 0 to Bit 2 to all 0’s in Control
Configuration 2 register.
When measuring the VDD value the reference for the ADC
is sourced from the Internal Reference. Table 2 shows the
data format. As the max VCC voltage measurable is 7 V,
internal scaling is performed on the VCC voltage to match
the 2.25V internal reference value. Below is an example of
how the transfer function works.
The time taken to monitor all channels will normally not
be of interest, as the most recently measured value can be
read at any time.
VDD = 5 V
For applications where the Round Robin time is impor-
tant, it can be easily calculated.
ADC Reference = 2.25 V
1 LSB = ADC Reference / 2^10 = 2.25 / 1024 =
2.197mV
As mentioned previously a conversion on each temperature
channel takes 25 us and on the VDD channel it takes 15 us.
Each channel is measured 16 times and internally aver-
aged to reduce noise.
Scale Factor = Fullscale VCC / ADC Reference = 7 / 2.25
= 3.11
Conversion Result = VDD / ((7/Scale Factor) x LSB size)
The total cycle time for voltage and temperature channels
is therefore nominally :
= 5 / (3.11 x 2.197mV)
= 2DBh
(2 x 16 x 25) + (16 x 15) = 1.04 ms
SINGLE CHANNEL MEASUREMENT
TABLE 2. VDD Data Format, VREF = 2.25V
Setting C4 of Control Configuration 2 register enables the
single channel mode and allows the ADT7316/17/18 to
focus on one channel only. A channel is selected by writ-
ing to Bits 0:2 in register Control Configuration 2 regis-
ter. For example, to select the VDD channel for monitoring
write to the Control Configuration 2 register and set C4
to 1 (if not done so already), then write all 0’s to bits 0 to
2 . All subsequent conversions will be done on the VDD
channel only. To change the channel selection to the In-
ternal temperature channel, write to the Control Configu-
ration 2 register and set C0 = 1. When measuring in
single channel mode there is a time delay of TBD us be-
tween each measurement. A measurement is also initiated
after every read or write operation.
VDD Value
Digital Output
Binary
Hex
2.5 V
3 V
01 0110 1110
01 1011 0111
10 0000 0000
10 0100 1001
10 1001 0010
10 1101 1011
11 0010 0100
16E
1B7
200
249
292
2DB
324
3.5 V
4 V
4.5 V
5 V
5.5 V
REV. PrN
–15–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
V
DD
I
I
BIAS
N x I
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
V
OUT+
D+
C1
D-
TO ADC
REMOTE
SENSING
V
TRANSISTOR
(2N3906)
OUT-
BIAS
DIODE
LOWPASS FILTER
= 65kHz
f
c
Figure 10. Signal Conditioning for External Diode temperature Sensors
MEASUREMENT METHOD
where:
INTERNAL TEMPERATURE MEASUREMENT
K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents
The ADT7316/7317/7318 contains an on-chip bandgap
temperature sensor, whose output is digitized by the on-
chip ADC. The temperature data is stored in the Internal
Temperature Value Register. As both positive and nega-
tive temperatures can be measured, the temperature data is
stored in two's complement format, as shown in Table 3.
The thermal characteristics of the measurement sensor
could change and therefore an offset is added to the mea-
sured value to enable the transfer function to match the
thermal characteristics. This offset is added before the
temperature data is stored. The offset value used is stored
in the Internal Temperature Offset Register.
Figure 10 shows the input signal conditioning used to
measure the output of an external temperature sensor.
This figure shows the external sensor as a substrate tran-
sistor, provided for temperature monitoring on some mi-
croprocessors, but it could equally well be a discrete
transistor.
If a discrete transistor is used, the collector will not be
grounded, and should be linked to the base. If a PNP
transistor is used the base is connected to the D- input and
the emitter to the D+ input. If an NPN transistor is used,
the emitter is connected to the D- input and the base to
the D+ input.
EXTERNAL TEMPERATURE MEASUREMENT
The ADT7316/7317/7318 can measure the temperature of
one external diode sensor or diode-connected transistor.
The forward voltage of a diode or diode-connected tran-
sistor, operated at a constant current, exhibits a negative
temperature coefficient of about -2mV/oC. Unfortunately,
the absolute value of Vbe, varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass-production.
We recommend that a 2N3906 be used as the external
transistor.
To prevent ground noise interfering with the measure-
ment, the more negative terminal of the sensor is not ref-
erenced to ground, but is biased above ground by an
internal diode at the D- input. As the sensor is operating
in a noisy environment, C1 is provided as a noise filter.
See the section on layout considerations for more informa-
tion on C1.
The time taken to measure the external temperature can
be reduced by setting C0 of Control Config. 3 register
(1Ah). This increases the ADC clock speed from 1.4KHz
to 22KHz but the analog filters on the D+ and D- input
pins are switched off to accommodate the higher clock
speeds. Running at the slower ADC speed, the time taken
to measure the external temperature is TBD while on the
fast ADC this time is reduced to TBD.
To measure ∆Vbe, the sensor is switched between operating
currents of I and N x I. The resulting waveform is passed
through a lowpass filter to remove noise, thence to a chop-
per-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a DC voltage proportional to ∆Vbe. This voltage is mea-
sured by the ADC to give a temperature output in 8-bit
two’s complement format. To further reduce the effects of
noise, digital filtering is performed by averaging the re-
sults of 16 measurement cycles.
The technique used in the ADT7316/7317/7318 is to
measure the change in Vbe when the device is operated at
two different currents.
This is given by:
∆Vbe = KT/q x ln(N)
–16–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
V
DD
I
N x I
I
BIAS
V
OUT+
TO ADC
V
OUT-
BIAS
DIODE
INTERNAL
SENSE
TRANSISTOR
Figure 11. Top Level Structure of Internal Temperature Sensor
LAYOUT CONSIDERATIONS
5. Place 0.1µF bypass and 2200pF input filter capacitors
Digital boards can be electrically noisy environments, and
care must be taken to protect the analog inputs from
noise, particularly when measuring the very small voltages
from a remote diode sensor. The following precautions
should be taken:
close to the ADT7316/17/18.
6. If the distance to the remote sensor is more than 8
inches, the use of twisted pair cable is recommended.
This will work up to about 6 to 12 feet.
7. For really long distances (up to 100 feet) use shielded
twisted pair such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D- and the shield
to GND close to the ADT7316/17/18. Leave the re-
mote end of the shield unconnected to avoid ground
loops.
1. Place the ADT7316/17/18 as close as possible to the
remote sensing diode. Provided that the worst noise
sources such as clock generators, data/address buses and
CRTs are avoided, this distance can be 4 to 8 inches.
2. Route the D+ and D- tracks close together, in parallel,
with grounded guard tracks on each side. Provide a
ground plane under the tracks if possible.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect
the measurement. When using long cables, the filter ca-
pacitor may be reduced or removed.
3. Use wide tracks to minimize inductance and reduce
noise pickup. 10 mil track minimum width and spacing
is recommended.
Cable resistance can also introduce errors. 1⍀ series resis-
tance introduces about 0.5oC error.
GND
10 mil.
10 mil.
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25°C. The ADC
can theoretically measure a temperature span of 255 °C.
The internal temperature sensor is guaranteed to a low
value limit of -40 °C. It is possible to measure the full
temperature span using the external temperature sensor.
The temperature data format is shown in Tables 3.
D+
D-
10 mil.
10 mil.
10 mil.
10 mil.
GND
10 mil.
The result of the internal or external temperature mea-
surements is stored in the temperature value registers, and
is compared with limits programmed into the Internal or
External High and Low Registers.
Figure 12. Arrangement of Signal Tracks
4. Try to minimize the number of copper/solder joints,
which can cause thermocouple effects. Where copper/
solder joints are used, make sure that they are in both
the D+ and D- path and at the same temperature.
TABLE 3. Temperature Data Format (Internal and Ex-
ternal Temperature)
Thermocouple effects should not be a major problem as
1oC corresponds to about 240µV, and thermocouple
voltages are about 3µV/oC of temperature difference.
Unless there are two thermocouples with a big tempera-
ture differential between them, thermocouple voltages
should be much less than 200mV.
Temperature
Digital Output
DB9..........DB0
-40 °C
11 0110 0000
REV. PrN
–17–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
S/W Reset
Internal
Temp
INTERRUPT
STATUS
REGISTER 1
(TEMP and Ext.
Diode Check)
External
Temp
V
DD
INTERRUPT
MASK
WATCHDOG
LIMIT
INTERRUPT
(Latched Output)
REGISTERS
COMPARISONS
INTERRUPT
STATUS
REGISTER 2
Diode
Fault
(VDD)
INTERRUPT
ENABLE BIT
CONTROL
CONFIGURATION
REGISTER 1
Read Reset
Figure 13. ADT7316/17/18 Interrupt Structure
-25 °C
11 1001 1100
Interrupt Status 1 Register (address = 00h) and Interrupt
Status 2 Register (address = 01h). One or more out-of
limit results will cause the INTERRUPT output to pull
either high or low depending on the output polarity set-
ting.
-10 °C
11 1101 1000
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
01 1010 0100
01 1111 0100
-0.25 °C
0 °C
Figure 13 shows the interrupt structure for the ADT7316/
17/18. It gives a block diagram representation of how the
various measurement channels affect the INTERRUPT
pin.
+0.25 °C
+10 °C
+25 °C
+50 °C
+75 °C
+100 °C
+105 °C
+125 °C
THERMAL VOLTAGE OUTPUT
The ADT7316/17/18 has the capability of outputting a
voltage that is proportional to temperature. DAC A output
can be configured to reperesent the temperature of the
internal sensor while DAC B output can be configured to
reperesent the external temperature sensor. Bits 5 and 6 of
Control Configuration 3 register select the temperature
proportional output voltage. Each time a temperature
measurement is taken the DAC output is updated. The
output resolution ADT7318 is 8 bits with 1°C change
corresponding to one LSB change. The output resolution
for the ADT7316 and ADT7317 is capable of 10 bits with
0.25°C change corresponding to one LSB change. The
default output resolution for the ADT7316 and ADT7317
is 8 bits. To increase this to 10 bits, set bit 1=1 of Con-
trol Configuration 3 register. The default output range is
0V-VREF and this can be increased to 0V-2VREF. Increasing
the outout voltage span to 2VREF can be done by setting
D0 = 1 for DAC A (Internal Temperature Sensor) and
D1 = 1 for DAC B (External Temperature Sensor) in
DAC Configuration register (address 1Bh).
Temperature Conversion Formula:
1. Positive Temperature = ADC Code/4
2. Negative Temperature = (ADC Code* - 512)/4
*DB9 is removed from the ADC Code
INTERRUPTS
The measured results from the inetrnal temperature sen-
sor, external temperature sensor and the VDD pin are com-
pared with the
THIGH/VHIGH and TLOW/VLOW limits. These
limits are stored in on-chip registers. Please note that the
limit registers are 8 bits long while the conversion results
are 10 bits long. If the limits are not masked out then any
out of limit comparisons generate flags that are stored in
The output voltage is capable of tracking a max tempera-
ture range of -128°C to +127°C but the default setting is -
40°C to +127°C. If the output voltage range is 0V-VREF
–18–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
(VREF = 2.25 V) then this corresponds to 0V representing -
40°C and 1.48V representing +127°C. This of course will
0.75V
1V
+3
-85
43
+17
-71
+57
give an upper deadband between 1.48V and VREF
.
1.12V
1.47V
1.5V
2V
+23
-65
+63
The Internal and External Analog Temperature Offset
registers can be used to vary this upper deadband and con-
sequently the temperature that 0V corresponds to. Tables
4 and 5 give examples of how this is done using a DAC
output voltage span of VREF and 2VREF respectivily. Simply
write in the temperature value, in 2’s complement format,
that you want 0V to start at. For example, if you are using
the DAC A output and you want 0V to start at -40°C then
program D8h into the Internal Analog Temperature Off-
set register (address 21h). This is an 8-bit register and
thus only has a temperature offset resolution of 1°C for all
device models. Use the following formulas to determine
the value to program into the offset registers.
+43
-45
+83
+45
-43
+85
+73
-15
+113
+127
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
2.25V
2.5V
2.75V
3V
+88
0
+102
+116
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
+14
+28
+42
+56
+70
+85
+99
+113
+127
3.25V
3.5V
3.75V
4V
Negative temperatures : -
Offset Register Code(d)* = (0V Temp) + 128
*D7 of Offset Register Code is set to 1 for negative temperatures.
Example : -
4.25V
4.5V
Offset Register Code(d) = (-40) + 128
= 88d = 58h
* Upper deadband has been reached. DAC output is not capable of increasing.
Reference Figure 6.
Since a negative temperature has been inputted into the
equation, DB7 (MSB) of the Offset Register code is set to
a 1. Therefore 58h becomes D8h.
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output :-
58h + DB7(1)
D8h
Positive temperatures : -
8-Bit Temp = (DAC O/P ÷ 1 LSB) + ( 0V Temp)
Offset Register Code(d) = 0V Temp
Offset Register Code (d) = 10d = 0Ah
For example, if the output is 1.5V, VREF = 2.25 V, 8-bit
DAC has an LSB size = 2.25V/255 = 8.82x10-3, and 0V
Temp is at -128°C then the resultant temperature works
out to be :-
Example : -
(1.5 ÷8.82x10-3) + (-128) = +42°C
Table 4. Thermal Voltage Output (0V-VREF
)
O/P Voltage
0V
Default °C
-40
Max °C
-128
-71
Sample °C
0
The following equation is used to work out the various
temperatures for the corresponding 10-bit DAC output :-
0.5V
+17
+56
10-Bit Temp = ((DAC O/P ÷ 1 LSB)x0.25) + ( 0V Temp)
1V
+73
-15
+113
For example, if the output is 0.4991V, VREF = 2.25 V, 10-
bit DAC has an LSB size = 2.25V/1024 = 2.197x10-3, and
0V Temp is at -40°C then the resultant temperature works
out to be :-
1.12V
1.47V
1.5V
+87
-1
+127
+127
UDB*
UDB*
UDB*
+39
+42
+99
+127
UDB*
UDB*
UDB*
UDB*
((0.4991 ÷2.197x10-3)x0.25) + (-40) = +16.75°C
2V
Figure 14 shows a graph of DAC output vs temperature
for a VREF = 2.25 V.
2.25V
* Upper deadband has been reached. DAC output is not capable of increasing.
Reference Figure 6.
Table 5. Thermal Voltage Output, (0V-2VREF
)
O/P Voltage
0V
Default °C
-40
Max °C
-128
Sample °C
0
0.25V
0.5V
-26
-114
14
+12
-100
+28
REV. PrN
–19–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
2nd READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
2.25
UNLOCK ASSOCIATED
MSB REGISTERS
2.10
1.95
1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0.00
0 V = -128'C
Figure 16. Phase 2 of 10-Bit Read
0 V = -40'C
If an MSB register is read first, it’s corresponding LSB
register is not locked thus leaving the user with the option
of just reading back 8 bits (MSB) of a 10-bit conversion
result. Reading an MSB register first does not lock up
other MSB registers and likewise reading an LSB register
first does not lock up other LSB registers.
Table 6. List of ADT7316/7317/7318 Registers
RD/WR
Address
Name
Power-on
Default
0 V = 0'C
00h
01h
02h
03h
04h
05h
06h
07h
08h
Interrupt Status 1
Interrupt Status 2
00h
00h
-128 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100 110 120 127
Temperature ('C)
RESERVED
Internal Temp & VDD LSBs
External Temp LSBs
RESERVED
00h
00h
Figure 14. DAC Output vs Temperature, VREF = 2.25 V
ADT7316/7317/7318 REGISTERS
The ADT7316/17/18 contains registers that are used to
store the results of external and internal temperature mea-
surements, VDD value measurements, high and low tem-
perature and supply voltage limits, set output DAC
voltage levels, configure multipurpose pins and generally
control the device. A description of these registers follows.
VDD MSBs
00h
00h
00h
Internal Temperature MSBs
External Temp MSBs
The register map is divided into registers of 8-bits long.
Each register has it’s own indvidual address but some
consist of data that is linked with other registers. These
registers hold the 10-bit conversion results of measure-
ments taken on the Temperature and VDD channels. For
example, the 8 MSBs of the VDD measurement are stored
in register address 06h while the 2 LSBs are stored in
register address 03h. The link involved between these
types of registers is that when the LSB register is read first
then the MSB registers associated with that LSB register
are locked to prevent any updates. To unlock these MSB
registers the user has only to read any one of them, which
will have the affect of unlocking all previously locked
MSB registers. So for the example given above if register
03h was read first then MSB registers 06h and 07h would
be locked to prevent any updates to them. If register 06h
was read then this register and register 07h would be sub-
sequently unlocked.
09h-0Fh
RESERVED
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
DAC A LSBs (ADT7316/17 only)
DAC A MSBs
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
D8h
DAC B LSBs (ADT7316/17 only)
DAC B MSBs
DAC C LSBs (ADT7316/17 only)
DAC C MSBs
DAC D LSBs (ADT7316/17 only)
DAC D MSBs
Control CONFIG 1
Control CONFIG 2
Control CONFIG 3
DAC CONFIG
1st READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
LDAC CONFIG
LOCK ASSOCIATED
MSB REGISTERS
Interrupt Mask 1
Figure 15. Phase 1 of 10-Bit Read
Interrput Mask 2
Internal Temp Offset
External Temp Offset
Internal Analog Temp Offset
–20–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
22h
23h
24h
25h
26h
27h
28h
External Analog Temp Offset
D8h
C9h
62h
64h
C9h
FFh
00h
Bit
Function
VDD VHIGH Limit
D4
1 when VDD value exceeds corrosponding VHIGH and
VLOW limits
VDD VLOW Limit
Internal THIGH Limit
Internal TLOW Limit
External THIGH
INTERNAL TEMPERATURE VALUE/VDD VALUE REG-
ISTER LSBs (Read only) [Add. = 03h]
External TLOW
This Internal Temperature Value and VDD Value Register
is a 8-bit read-only register. It stores the two LSBs of the
10-bit temperature reading from the internal temperature
sensor and also the two LSBs of the 10-bit supply voltage
reading.
29h-4CH
RESERVED
4Dh
4Eh
4Fh
Device ID
01h/05h/09h
41h
Table 9. Internal Temp/VDD LSBs
Manufacturer’s ID
Silicon Revision
D7
D6
D5
D4
D3
V1
0*
D2
LSB
0*
D1
T1
0*
D0
00h
N/A N/A N/A N/A
LSB
0*
N/A N/A N/A N/A
50h-FFh
RESERVED
*Default settings at Power-up.
Bit
Function
Interrupt Status 1 Register (Read only) [Add. = 00h]
This 8-bit read only register reflects the status of some of
the interrupts that can cause the INTERRUPT pin to go
active. This register is reset by a read operation or by a
software reset.
D0
D1
D2
D3
LSB of Internal Temperature Value
B1 of Internal Temperature Value
LSB of VDD Value
Table 7. Interrupt Status 1 Register
B1 of VDD Value
D7
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
0*
0*
0*
0*
0*
EXTERNAL TEMPERATURE VALUE REGISTER
LSBS (Read only) [Add. = 04h]
*Default settings at Power-up.
This External Temperature Value is a 8-bit read-only
register. It stores the two LSBs of the 10-bit temperature
reading from the external temperature sensor.
Bit
Function
D0
D1
D2
D3
D4
1 when Internal Temp Value exceeds THIGH limit
1 when Internal Temp Value exceeds TLOW limit
1 when External Temp Value exceeds THIGH limit
1 when External Temp Value exceeds TLOW limit
Table 10. External Temperature LSBs
D7
D6
D5
D4
D3
D2
D1
T1
0*
D0
N/A N/A N/A N/A
N/A
N/A
N/A
N/A
LSB
0*
N/A N/A N/A N/A
1 indicates a fault (open or short) for the external
temperature sensor.
*Default settings at Power-up.
Bit
Function
Interrupt Status 2 Register (Read only) [Add. = 01h]
This 8-bit read only register reflects the status of the VDD
interrupt that can cause the INTERRUPT pin to go ac-
tive. This register is reset by a read operation or by a soft-
ware reset.
D0
D1
LSB of External Temperature Value
B1 of External Temperature Value
Table 8. Interrupt Status 1 Register
VDD VALUE REGISTER MSBS (Read only) [Add. = 06h]
This 8-bit read only register stores the supply voltage
value. The 8 MSBs of the 10-bit value are stored in this
register.
D7
D6
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A
0*
N/A
N/A
N/A N/A
*Default settings at Power-up.
Table 11. VDD Value MSBs
REV. PrN
–21–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
DAC A REGISTER MSBS (Read/Write) [Add. = 11h]
This 8-bit read/write register contains the 8 MSBs of the
DAC A word. The value in this register is combined with
the value in the DAC A Register LSBs and converted to
an analog voltage on the VOUTA pin. On power-up the
voltage output on the VOUTA pin is 0 V.
D7
V9
0*
D6
V8
0*
D5
V7
0*
D4
V6
0*
D3
V5
0*
D2
V4
0*
D1
V3
0*
D0
V2
0*
*Default settings at Power-up.
Table 16. DAC A MSBs
INTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 07h]
This 8-bit read only register stores the Internal Tempera-
ture value from the internal temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
D7
MSB B8
0* 0*
D6
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
*Default settings at Power-up.
Table 12.
Internal Temperature Value MSBs
DAC B REGISTER LSBS (Read/Write) [Add. = 12h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC B word respectivily. The value in
this register is combined with the value in the DAC B
Register MSBs and converted to an analog voltage on the
D7
T9
0*
D6
T8
0*
D5
D4
T6
0*
D3
T5
0*
D2
T4
0*
D1
T3
0*
D0
T2
0*
T7
0*
VOUTB pin. On power-up the voltage output on the VOUT
B
*Default settings at Power-up.
pin is 0 V.
EXTERNAL TEMPERATURE VALUE REGISTER
MSBS (Read only) [Add. = 08h]
Table 17. DAC B (ADT7316) LSBs
This 8-bit read only register stores the External Tempera-
ture value from the external temperature sensor in twos
complement format. The 8 MSBs of the 10-bit value are
stored in this register.
D7
B3
0*
D6
B2
0*
D5
B1
0*
D4
LSB
0*
D3
D2
D1
D0
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
*Default settings at Power-up.
Table 13.
External Temperature Value MSBs
D7
T9
0*
D6
T8
0*
D5
D4
T6
0*
D3
T5
0*
D2
T4
0*
D1
T3
0*
D0
T2
0*
Table 18. DAC B (ADT7317) LSBs
T7
0*
D7
B2
0*
D6
LSB N/A N/A
0* N/A N/A
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
*Default settings at Power-up.
*Default settings at Power-up.
DAC A REGISTER LSBS (Read/Write) [Add. = 10h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC A word respectivily. The value in
this register is combined with the value in the DAC A
Register MSBs and converted to an analog voltage on the
DAC B REGISTER MSBS (Read/Write) [Add. = 13h]
This 8-bit read/write register contains the 8 MSBs of the
DAC B word. The value in this register is combined with
the value in the DAC B Register LSBs and converted to
an analog voltage on the VOUTB pin. On power-up the
voltage output on the VOUTB pin is 0 V.
VOUTA pin. On power-up the voltage output on the VOUT
A
pin is 0 V.
Table 14. DAC A (ADT7316) LSBs
Table 19. DAC B MSBs
D7
B3
0*
D6
B2
0*
D5
B1
0*
D4
LSB
0*
D3
D2
D1
D0
D7
MSB B8
0* 0*
D6
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
*Default settings at Power-up.
*Default settings at Power-up.
Table 15. DAC A (ADT7317) LSBs
DAC C REGISTER LSBS (Read/Write) [Add. = 14h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC C word respectivily. The value in
this register is combined with the value in the DAC C
Register MSBs and converted to an analog voltage on the
D7
B2
0*
D6
LSB N/A N/A
0* N/A N/A
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
VOUTC pin. On power-up the voltage output on the VOUT
pin is 0 V.
C
*Default settings at Power-up.
–22–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Table 20. DAC C (ADT7316) LSBs
Table 25. DAC D MSBs
D7
B3
0*
D6
B2
0*
D5
B1
0*
D4
LSB
0*
D3
D2
D1
D0
D7
MSB B8
0* 0*
D6
D5
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
B7
0*
*Default settings at Power-up.
*Default settings at Power-up.
Table 21. DAC C (ADT7317) LSBs
CONTROL CONFIGURATION 1 REGISTER (Read/
Write) [Add. = 18h]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
D7
B2
0*
D6
LSB N/A N/A
0* N/A N/A
D5
D4
D3
D2
D1
D0
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
Table 26.
Control Configuration 1
*Default settings at Power-up.
D7
PD
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
DAC C REGISTER MSBS (Read/Write) [Add. = 15h]
This 8-bit read/write register contains the 8 MSBs of the
DAC C word. The value in this register is combined with
the value in the DAC C Register LSBs and converted to
an analog voltage on the VOUTC pin. On power-up the
voltage output on the VOUTC pin is 0 V.
*Default settings at Power-up.
Bit
Function
Table 22. DAC C MSBs
C0
This bit enables/disables conversions in Round
Robin mode. ADT7316/17/18 powers up in
Round Robin mode but monitoring is not initi-
ated until this bit is set. Default = 0.
D7
MSB B8
0* 0*
D6
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
0 = Disable Round Robin monitoring.
1 = Enable Round Robin monitoring.
*Default settings at Power-up.
C1:4
C5
RESERVED. Only write 0’s.
DAC D REGISTER LSBS (Read/Write) [Add. = 16h]
This 8-bit read/write register contains the 4/2 LSBs of the
ADT7316/7317 DAC D word respectivily. The value in
this register is combined with the value in the DAC D
Register MSBs and converted to an analog voltage on the
0
1
Enable INTERRUPT
Disable INTERRUPT
C6
C7
Configures INTERRUPT output polarity.
0
1
Active low
Active High
VOUTD pin. On power-up the voltage output on the VOUT
D
pin is 0 V.
Power-down Bit. Setting this bit to 1 puts the
ADT7316/17/18 into standby mode. In this
mode both ADC and DACs are fully powered
down, but serial interface is still operational. To
Table 23. DAC D (ADT7316) LSBs
D7
B3
0*
D6
B2
0*
D5
B1
0*
D4
LSB
0*
D3
D2
D1
D0
power up the part again just write 0 to this bit
.
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
CONTROL CONFIGURATION 2 REGISTER (Read/
Write) [Add. = 19h]
*Default settings at Power-up.
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Table 24. DAC D (ADT7317) LSBs
D7
B2
0*
D6
LSB N/A N/A
0* N/A N/A
D5
D4
D3
D2
D1
D0
Table 27.
Control Configuration 2
N/A
N/A
N/A N/A
N/A N/A
N/A
N/A
D7
C7
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
*Default settings at Power-up.
DAC D REGISTER MSBS (Read/Write) [Add. = 17h]
This 8-bit read/write register contains the 8 MSBs of the
DAC D word. The value in this register is combined with
the value in the DAC D Register LSBs and converted to
an analog voltage on the VOUTD pin. On power-up the
voltage output on the VOUTD pin is 0 V.
*Default settings at Power-up.
Bit
Function
REV. PrN
–23–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
C2:0
In single channel mode these bits select between
DD, the internal temperature sensor and the
external temperature sensor for conversion. De-
C3
0 = LDAC pin controls updating of DAC out-
puts.
1 = DAC Configration register and LDAC Con-
figuration register control updating of DAC
outputs.
V
fault is VDD
.
000 = VDD
001 = Internal Temperature Sensor.
010 = External Temperature Sensor
011 - 111 = RESERVED
C4
C5
RESERVED. Only write 0.
Setting this bit selects DAC A voltage output to
be proportional to the internal temperature mea-
surement.
C3
C4
RESERVED
Selects between single channel and Round Robin
conversion cycle. Default is Round Robin.
0 = Round Robin.
C6
C7
Setting this bit selects DAC B voltage output to
be proportional to the external temperature mea-
surement.
1 = Single Channel.
RESERVED. Only write 0.
C5
C6
C7
Default condition is to average every measure-
ment on all channels 16 times. This bit disables
this averaging. Channels consist of temperature,
DAC CONFIGURATION REGISTER (Read/Write)
[Add. = 1Bh]
analog inputs and VDD
.
This configuration register is an 8-bit read/write register
that is used to control the output ranges of all four DACs
and also to control the loading of the DAC registers if the
LDAC pin is disabled (bit C3 = 1, Control Configuration
3 register).
0 = Enable averaging.
1 = Disable averaging.
SMBus timeout on the serial clock puts a max
limit on the pulse width of the clock. Ensures
that a fault on the master SCL does not lock up
the SDA line.
0 = Disable SMBus Timeout.
1 = Enable SMBus Timeout.
Table 29.
DAC Configuration
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Software Reset. Setting this bit to a 1 causes a
software reset. All registers and DAC outputs
will reset to their default settings.
D4
0*
*Default settings at Power-up.
CONTROL CONFIGURATION 3 REGISTER (Read/
Write) [Add. = 1Ah]
This configuration register is an 8-bit read/write register
that is used to setup some of the operating modes of the
ADT7316/17/18.
Bit
Function
Selects the output range of DAC A.
D0
0 = 0 V to VREF
.
1 = 0 V to 2VREF
.
D1
D2
D3
Selects the output range of DAC B.
0 = 0 V to VREF
1 = 0 V to 2VREF
Table 28.
Control Configuration 3
.
D7
C7
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
.
Selects the output range of DAC C.
0 = 0 V to VREF
1 = 0 V to 2VREF
.
.
*Default settings at Power-up.
Selects the output range of DAC D.
0 = 0 V to VREF
1 = 0 V to 2VREF
.
Bit
Function
.
C0
Selects between fast and normal ADC conver-
sion speeds for all three monitoring channels.
0 = ADC clock at 1.4 KHz.
D5:D4 00
MSB write to any DAC register generates
LDAC command which updates that
DAC only.
MSB write to DAC B or DAC D register
generates LDAC command which up-
dates DACs A, B or DACs C, D.
MSB write to DAC D register generates
LDAC command which updates all 4
DACs.
1 = ADC clock at 22.5 KHz.
01
10
11
C1
On the ADT7316 and ADT7317, this bit selects
between 8 bits and 10 bits DAC output resolu-
tion on the Thermal Voltage Output feature.
Default = 8 bits. This bit has no affect on the
ADT7318 output as this part has only an 8-bit
DAC. In the ADT7318 case, write 0 to this bit.
0 = 8 bits resolution.
LDAC command generated from LDAC
register.
1 = 10 bits resolution.
C2
RESERVED. Only write 0’s.
–24–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
*Default settings at Power-up.
D6
D7
Setting this bit allows the external VREF to bypass
the reference buffer when supplying DACs A
and B.
Bit
Function
Setting this bit allows the external VREF to bypass
the reference buffer when supplying DACs C
and D.
D0
0 = Enable internal THIGH interrupt.
1 = Disable internal THIGH interrupt.
D1
D2
D3
D4
0 = Enable internal TLOW interrupt.
1 = Disable internal TLOW interrupt.
LDAC CONFIGURATION REGISTER (Write only)
[Add. = 1Ch]
0 = Enable external THIGH interrupt.
1 = Disable external THIGH interrupt.
This configuration register is an 8-bit write register that is
used to control the updating of the quad DAC outputs if
the LDAC pin is disabled and Bits 4 and 5 of DAC Con-
figuration register are both set to 1. Also selects VREF for
all four DACs. All of the bits in this register are self clear-
ing i.e. reading back from this register will always give
0’s.
0 = Enable external Tlow interrupt.
1 = Disable external Tlow interrupt.
0 = Enable external temperature fault interrupt.
1 = Disable external temperature fault interrupt.
D5:D7 RESERVED. Only write 0’s.
Table 30.
LDAC Configuration
INTERRUPT MASK 2 REGISTER (Read/Write) [Add. =
1Eh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can can cause the
INTERRUPT pin to go active.
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D4
0*
*Default settings at Power-up.
Table 32. Interrupt Mask 2
Bit
Function
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D0
Writing a 1 to this bit will generate the LDAC
command to update DAC A output only.
D1
D2
D3
D4
Writing a 1 to this bit will generate the LDAC
command to update DAC B output only.
*Default settings at Power-up.
Bit
Function
Writing a 1 to this bit will generate the LDAC
command to update DAC C output only.
D0:D3 RESERVED. Only write 0’s.
Writing a 1 to this bit will generate the LDAC
command to update DAC D output only.
D4
0 = Enable VDD interrupts.
1 = Disable VDD interrupts.
Selects either internal or external VREFAB for
DACs A and B.
D5:D7 RESERVED. Only write 0’s.
0 = External VREF
1 = Internal VREF
INTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 1Fh]
D5
Selects either internal or external VREFCD for
DACs C and D.
0 = External VREF
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the mea-
sured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolu-
tion is 1oC.
1 = Internal VREF
D6:D7 RESERVED. Only write 0’s.
INTERRUPT MASK 1 REGISTER (Read/Write) [Add. =
1Dh]
This mask register is an 8-bit read/write register that can
be used to mask out any interrupts that can can cause the
INTERRUPT pin to go active.
Table 33.
Internal Temperature Offset
Table 31. Interrupt Mask 1
D7
D7
0*
D6
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D6
0*
*Default settings at Power-up.
REV. PrN
–25–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
EXTERNAL TEMPERATURE OFFSET REGISTER
(Read/Write) [Add. = 20h]
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
1*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
This register contains the Offset Value for the Internal
Temperature Channel. A 2's complement number can be
written to this register which is then 'added' to the mea-
sured result before it is stored or compared to limits. In
this way a sort of one-point calibration can be done
whereby the whole transfer function of the channel can be
moved up or down. From a software point of view this
may be a very simple method to vary the characteristics of
the measurement channel if the thermal characteristics
change. As it is an 8-bit register the temperature resolu-
tion is 1oC.
*Default settings at Power-up.
VDD VHIGH LIMIT REGISTER (Read/Write) [Add. = 23h]
This limit register is an 8-bit read/write register which
stores the VDD upper limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured VDD value has to be greater than the
value in this register. Default value is 5.5 V.
Table 37. VDD VHIGH Limit
Table 34.
External Temperature Offset
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
0*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
1*
D7
D7
0*
D6
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D6
0*
*Default settings at Power-up.
*Default settings at Power-up.
VDD VLOW LIMIT REGISTER (Read/Write) [Add. = 24h]
This limit register is an 8-bit read/write register which
stores the VDD lower limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured VDD value has to be less than the
value in this register. Default value is 2.7 V.
INTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write) [Add. = 21h]
This register contains the Offset Value for the Internal
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the mea-
sured result before it is converted by DAC A. Varying the
value in this register has the affect of varying the tempera-
ture span. For example, the output voltage can represent a
temperature span of -128oC to +127oC or even 0oC to
+127oC. In essence this register changes the position of
0V on the temperature scale. Anything other than -128oC
to +127oC will produce an upper deadband on the DAC A
output. As it is an 8-bit register the temperature resolution
is 1oC. Default value is -40oC.
Table 38. VDD VHIGH Limit
D7
D7
0*
D6
D6
1*
D5
D5
1*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
1*
D0
D0
0*
*Default settings at Power-up.
INTERNAL THIGH LIMIT REGISTER (Read/Write) [Add.
= 25h]
Table 35.
Internal Analog Temperature Offset
This limit register is an 8-bit read/write register which
stores the 2’s complement of the internal temperature
upper limit that will cause an interrupt and activate the
INTERRUPT output (if enabled). For this to happen the
measured Internal Temperature Value has to be greater
than the value in this register. As it is an 8-bit register the
temperature resolution is 1oC. Default value is +100oC.
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
1*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
*Default settings at Power-up.
EXTERNAL ANALOG TEMPERATURE OFFSET
REGISTER (Read/Write)[Add. = 22h]
Table 39. Internal THIGH Limit
This register contains the Offset Value for the External
Thermal Voltage output. A 2's complement number can
be written to this register which is then 'added' to the mea-
sured result before it is converted by DAC B. Varying the
value in this register has the affect of varying the tempera-
ture span. For example, the output voltage can represent a
temperature span of -128oC to +127oC or even 0oC to
+127oC. In essence this register changes the position of
0V on the temperature scale. Anything other than -128oC
to +127oC will produce an upper deadband on the DAC B
output. As it is an 8-bit register the temperature resolution
is 1oC. Default value is -40oC.
D7
D7
0*
D6
D6
1*
D5
D5
1*
D4
D4
0*
D3
D3
0*
D2
D2
1*
D1
D1
0*
D0
D0
0*
*Default settings at Power-up.
INTERNAL TLOW LIMIT REGISTER (Read/Write) [Add.
26h]
This limit register is an 8-bit read/write register which
stores the 2’s complement of the internal temperature
lower limit that will cause an interrupt and activate the
INTERRUPT output (if enabled). For this to happen the
measured Internal Temperature Value has to be more
Table 36.
External Analog Temperature Offset
–26–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
negative than the value in this register. As it is an 8-bit
Table 41. External THIGH Limit
register the temperature resolution is 1oC. Default value is
-55oC.
D7
D7
1*
D6
D6
1*
D5
D5
1*
D4
D4
1*
D3
D3
1*
D2
D2
1*
D1
D1
1*
D0
D0
1*
Table 40. Internal TLOW Limit
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
0*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
1*
*Default settings at Power-up.
EXTERNAL TLOW LIMIT REGISTER (Read/Write) [Add.
= 28h]
If pins 7 and 8 are configured for the external temperature
sensor then this limit register is an 8-bit read/write regis-
ter which stores the 2’s complement of the external tem-
perature lower limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured External Temperature Value has to
be more negative than the value in this register. As it is an
8-bit register the temperature resolution is 1oC.
*Default settings at Power-up.
EXTERNAL THIGH LIMIT REGISTER (Read/Write) [Add.
= 27h]
If pins 7 and 8 are configured for the external temperature
sensor then this limit register is an 8-bit read/write regis-
ter which stores the 2’s complement of the external tem-
perature upper limit that will cause an interrupt and
activate the INTERRUPT output (if enabled). For this to
happen the measured External Temperature Value has to
be greater than the value in this register. As it is an 8-bit
register the temperature resolution is 1oC.
Table 42. External TLOW Limit
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
1
9
1
9
SCL
SDA
W
1
0
0
1
A2
A1
A0
R/
P7
P6
P5
P4
P3
P2
P1
P0
ACK. BY
START BY
MASTER
ACK. BY
ADT7316/17/18
STOP BY
MASTER
ADT7316/17/18
FRAME 1
SERIAL BUS ADDRESS B YTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 17. I2C - Writing to the Address Pointer Register to select a register for a subsequent Read operation
1
1
9
1
9
SCL
SDA
W
R/
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
START BY
MASTER
ACK. BY
ADT7316/17/18
ACK. BY
ADT7316/17/18
FRAME 1
SERIAL BUS ADDRESS B YTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
STOP BY
ADT7316/17/18 MASTER
FRAME 3
DATA BYTE
Figure 18. I2C - Writing to the Address Pointer Register followed by a single byte of data to the selected register
REV. PrN –27–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
0*
0*
0*
0*
0*
0*
0*
0*
ADT7316/17/18 version number. The ADT7316/17/18’s
version number is 0000b.
*Default settings at Power-up.
ADT7316/7317/7318 SERIAL INTERFACE
There are two serial interfaces that can be used on this
part, I2C and SPI. A valid serial communication protocol
selects the type of interface.
DEVICE ID REGISTER (READ ONLY) [ADD. = 4DH]
This 8-bit read only register indicates which part the de-
vice is in the model range. ADT7316 = 01h, ADT7317 =
05h and ADT7318 = 09h.
SERIAL INTERFACE SELECTION
The CS line controls the selection between I2C and SPI. If
CS is held high during a valid I2C communication then
the serial interface selects the I2C mode once the correct
serial bus address has been recognised.
MANUFACTURER’S ID REGISTER (Read only) [Add.
= 4Eh]
This register contains the manufacturers identification
number. ADI’s is 41h.
To set the interface to SPI mode the CS line must be low
during a valid SPI communication. This will cause the
interface to select the SPI mode once the correct read or
write command has been recognised. As per most SPI
standards the CS line must be low during every SPI com-
munication to the ADT7316/17/18 and high all other
times.
SILICON REVISION REGISTER (Read only) [Add. =
4Fh]
This register is divided into the four lsbs representing the
Stepping and the four msbs representing the Version. The
Stepping contains the manufacturers code for minor revi-
sions or steppings to the silicon. The Version is the
1
9
1
9
SCL
1
0
0
1
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
W
R/
SDA
ACK. BY
ADT7316/17/18
START BY
MASTER
NO ACK. BY STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRA ME 2
SINGLE DATA BYTE FROM ADT7316/17/18
Figure 19. I2C - Reading a single byte of data from a selected register
CS
1
8
8
1
SCLK
DIN
D7
D6
D5
D3
D1
D0
D5
D2
D0
D7
D4
D2
D6
D4
D3
D1
START
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
D6
D3
D1
DIN (CONTINUED)
D7
D5
D4
D2
D0
DATA BYTE
Figure 20. SPI - Writing to the Address Pointer Register followed by a single byte of data to the selected register
–28– REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
data to be read from or written to it. If the R/W bit is a
0 then the master will write to the slave device. If the
R/W bit is a 1 the master will read from the slave de-
vice.
The following sections describe in detail how to use these
interfaces.
I2C SERIAL INTERFACE
Like all I2C-compatible devices, the ADT7316/7317/7318
has an 7-bit serial address. The four MSBs of this address
for the ADT7316/7317/7318 are set to 1001. The three
LSBs are set by pin 11, ADD. The ADD pin can be con-
figured three ways to give three different address options;
low, floating and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
address 1001 010 and setting it high gives the address
1001 011.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the receiver of data. Transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a STOP signal.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse
to assert a STOP condition. In READ mode, the mas-
ter device will pull the data line high during the low
period before the 9th clock pulse. This is known as No
Acknowledge. The master will then take the data line
low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a STOP
condition.
There is a programmable SMBus timout. When this is
enabled the SMBus will timeout after 25 ms of no activity.
To enable it, set Bit 6 of Control Configuration 2 regis-
ter. The power-up default is with the SMBus timeout
disabled.
The ADT7316/17/18 supports SMBus Packet Error
Checking (PEC) and it’s use is optional. It is triggered by
supplying the extra clocks for the PEC byte. The PEC is
calculated using CRC-8. The Frame Clock Sequence
(FCS) conforms to CRC-8 by the polynominal :
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix
read and write in one operation, because the type of opera-
tion is determined at the beginning and cannot subse-
quently be changed without starting a new operation.
C(x) = x8 + x2 + x1 + 1
Consult SMBus specification for more information.
WRITING TO THE ADT7316/7317/7318
Depending on the register being written to, there are two
different writes for the ADT7316/7317/7318. It is not
possible to do a block write to this part i.e no I2C auto-
increment.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
START condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. This indicates that an address/data
stream will follow. All slave peripherals connected to
the serial bus respond to the START condition, and
shift in the next 8 bits, consisting of a 7-bit address
(MSB first) plus a R/W bit, which determines the direc-
tion of the data transfer, i.e. whether data will be writ-
ten to or read from the slave device.
Writing to the Address Pointer Register for a subsequent
read.
In order to read data from a particular register, the Ad-
dress Pointer Register must contain the address of that
register. If it does not, the correct address must be written
to the Address Pointer Register by performing a single-
byte write operation, as shown in Figure 17. The write
operation consists of the serial bus address followed by the
address pointer byte. No data is written to any of the data
registers. A read operation is then performed to read the
register.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit. All other devices on the
bus now remain idle whilst the selected device waits for
CS
1
8
8
1
SCLK
D7
D6
D5
D3
D1
D0
D5
D2
D0
DIN
D7
D4
D2
D6
D4
D3
D1
STOP
START
WRITE COMMAND
REGISTER ADDRESS
Figure 21. SPI - Writing to the Address Pointer Register to select a register for a subsequent read operation
REV. PrN –29–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Writing data to a Register.
having been set up by a single byte write operation to the
Address Pointer Register. If you want to read from another
register then you will have to write to the Address Pointer
Register again to set up the relevant register address. Thus
block reads are not possible i.e. no I2C auto-increment.
All registers are 8-bit registers so only one byte of data
can be written to each register. Writing a single byte of
data to one of these Read/Write registers consists of the
serial bus address, the data register address written to the
Address Pointer Register, followed by the data byte written
to the selected data register. This is illustrated in Figure
18. To write to a different register, another START or
repeated START is required. If more than one byte of
data is sent in one communication operation, the ad-
dressed register will be repeately loaded until the last data
byte has been sent.
SPI SERIAL INTERFACE
The SPI serial interface of the ADT7316/7317/7318 con-
sists of four wires, CS, SCLK, DIN and DOUT. The CS
is used to select the device when more than one device is
connected to the serial clock and data lines. The SCLK is
used to clock data in and out of the part. The DIN line is
used to write to the registers and the DOUT line is used
to read data back from the registers.
READING DATA FROM THE ADT7316/7317/7318
Reading data from the ADT7516/7517/7518 is done in a
one byte operation. Reading back the contents of a register
is shown in Figure 19. The register address previously
The part operates in a slave mode and requires an exter-
nally applied serial clock to the SCLK input. The serial
CS
1
8
8
1
SCLK
X
D6
X
D5
X
D3
X
D1
X
D0
X
X
X
X
DIN
D7
X
D4
X
D2
X
X
X
X
X
D7
DOUT
D6
D5
D4
D3
D2
D1
D0
STOP
START
READ COMMAND
DATA BYTE 1
Figure 22. SPI - Reading a single byte of data from a selected register
CS
1
8
8
1
SCLK
X
D6
X
D5
X
D3
X
D1
X
D0
X
X
X
X
DIN
D7
X
D4
X
D2
X
X
X
X
X
D7
DOUT
D6
D5
D4
D3
D2
D1
D0
START
READ COMMAND
DATA BYTE 1
CS (CONTINUED)
1
8
SCLK (CONTINUED)
X
X
X
X
X
X
X
X
D
IN (CONTINUED)
D6
D3
D1
DOUT (CONTINUED)
D7
D5
D4
D2
D0
STOP
DATA BYTE 2
Figure 23. SPI - Reading a two bytes of data from two sequential registers
–30–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
interface is designed to allow the part to be interfaced to
systems that provide a serial clock that is synchronized to
the serial data.
The INTERRUPT pin has an open-drain configuration
which allows the outputs of several devices to be wired-
AND together when the INTERRUPT pin is active low.
Use D6 of the Control Configuration 1 Register to set the
active polarity of the INTERRUPT output. The power-up
default is active low. The INTERRUPT function can be
disabled or enabled by setting D5 of Control Configura-
tion 1 Register to a 1 or 0 respectively.
There are two types of serial operations, a read and a
write. Command words are used to distinguish between a
read and a write operation. These command words are
given in Table 43. Address auto-increment is possible in
SPI mode
The INTERRUPT output becomes active when either the
Internal Temperature Value, the External Temperature
Value or the VDD Value exceed the values in their corre-
sponding THIGH/VHIGH or TLOW/VLOW Registers. The IN-
TERRUPT output goes inactive again when a conversion
result has the measured value back within the trip limits.
Table 43. SPI COMMAND WORDS
WRITE
READ
90h (1001 0000)
91h (1001 0001)
Write Operation
The INTERRUPT output requires an external pull-up
resistor. This can be connected to a voltage different from
VDD provided the maximum voltage rating of the INTER-
RUPT output pin is not exceeded. The value of the pull-
up resistor depends on the application, but should be as
large enough to avoid excessive sink currents at the IN-
TERRUPT output, which can heat the chip and affect the
temperature reading.
Figures 20 and 21 show the timing diagrams for a write
operation to the ADT7316/7317/7318. Data is clocked
into the registers on the rising edge of SCLK. When the
CS line is high the DIN and DOUT lines are in three-
state mode. Only when the CS goes from a high to a low
does the part accept any data on the DIN line. In SPI
mode the Address Pointer Register is capable of auto-
incrementing to the next register in the register map with-
out having to load the Address Pointer register each time.
In Figure 20 the register address portion of the diagram
gives the first register that will be written to. Subsequent
data bytes will be written into sequential writable registers.
Thus after each data byte has been written into a register,
the Address Pointer Register auto increments it’s value to
the next available register. The Address Pointer Register
will auto-increment from 00h to 3Fh and will loop back
to start all over again at 00h when it reaches 3Fh.
Read Operation
Figures 22 and 23 show the timing diagrams necessary to
accomplish correct read operations. To read back from a
register you first have to write to the Address Pointer Reg-
ister with the address of the register you wish to read
from. This operation is shown in Figure 21. Figure 22
shows the procedure for reading back a single byte of data.
The read command is first sent to the part during the first
8 clock cycles, during the following 8 clock cycles the
data contained in the register selected by the Address
Pointer register is outputted onto the DOUT line. Data is
outputted onto the DOUT line on the falling edge of
SCLK. Figure 23 shows the procedure when reading data
from two sequential registers. Multiple data reads are
possible in SPI interface mode as the Address Pointer
Register is auto-incremental. The Address Pointer Regis-
ter will auto-increment from 00h to 3Fh and will loop
back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INTERRUPT
The ADT7316/17/18 INTERRUPT output is an interrupt
line for devices that want to trade their ability to master
for an extra pin. The ADT7316/17/18 is a slave only de-
vice and uses the SMBus/SPI INTERRUPT to signal the
host device that it wants to talk. The SMBus/SPI INTER-
RUPT on the ADT7316/17/18 is used as an over/under
limit indicator.
REV. PrN
–31–
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
Outline Dimensions
(Dimensions shown in inches and mm )
16-Lead QSOP Package
( RQ-16 )
0.197 (5.00)
0.189 (4.80)
16
9
8
0.157 (3.99)
0.150 (3.81)
0.244 (6.20)
0.228 (5.79)
1
PIN 1
0.069 (1.75)
0.053 (1.35)
0.059 (1.50)
MAX
8o
0o
0.010 (0.25)
0.004 (0.10)
0.012 (0.30)
0.008 (0.20)
0.025
(0.64)
SEATING
PLANE
0.010 (0.20)
0.007 (0.18)
BSC
–32–
REV. PrN
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