ADT7517ARQZ_技术文档

SPI-/I²C-Compatible, Temperature Sensor,

4-Channel ADC and Quad Voltage Output

ADT7516/ADT7517/ADT7519

FEATURES

PIN CONFIGURATION

ADT7516: four 12-bit DACs

ADT7517: four 10-bit DACs

ADT7519: four 8-bit DACs

Buffered voltage output

Guaranteed monotonic by design over all codes

10-bit temperature-to-digital converter

10-bit 4-channel ADC

V

-B

-A

1

2

3

4

5

6

7

8

16

15

V

-C

-D

OUT

V

OUT

ADT7516/

ADT7517/

ADT7519

V

-IN

14 AIN4

REF

CS

13 SCL/SCLK

12 SDA/DIN

11 DOUT/ADD

10 INT/INT

TOP VIEW

(Not to Scale)

GND

V

DD

D+/AIN1

D–/AIN2

9

LDAC/AIN3

DC input bandwidth

Input range: 0 V to 2.28 V

Figure 1.

Temperature range: −40°C to +120°C

Temperature sensor accuracy: 0.5°C typ

Supply range: 2.7 V to 5.5 V

DAC output range: 0 V to 2 V_REF

Power-down current: <10 μA

Internal 2.28 V_REFoption

Double-buffered input logic

Buffered reference input

GENERAL DESCRIPTION

The ADT7516/ADT7517/ADT7519¹combine a 10-bit tempera-

ture-to-digital converter, a 10-bit 4-channel ADC, and a quad

12-/10-/8-bit DAC, respectively, in a 16-lead QSOP package.

The parts also include a band gap temperature sensor and a

10-bit ADC to monitor and digitize the temperature reading to

a resolution of 0.25°C.

Power-on reset to 0 V DAC output

Simultaneous update of outputs (LDAC function)

On-chip, rail-to-rail output buffer amplifier

SPI^®, I²C^®, QSPI™, MICROWIRE™, and DSP compatible

4-wire serial interface

The ADT7516/ADT7517/ADT7519 operate from a single 2.7 V

to 5.5 V supply. The input voltage range on the ADC channels is

0 V to 2.28 V, and the input bandwidth is dc. The reference for

the ADC channels is derived internally. The output voltage of

the DAC ranges from 0 V to V_DD, with an output voltage settling

time of 7 μs typical.

SMBus packet error checking (PEC) compatible

16-lead QSOP package

The ADT7516/ADT7517/ADT7519 provide two serial interface

options: a 4-wire serial interface that is compatible with SPI,

QSPI, MICROWIRE, and DSP interface standards, and a 2-wire

SMBus/I²C interface. They feature a standby mode that is

controlled through the serial interface.

APPLICATIONS

Portable battery-powered instruments

Personal computers

Smart battery chargers

Telecommunications systems

Electronic text equipment

Domestic appliances

The reference for the four DACs is derived either internally or

from a reference pin. The outputs of all DACs can be updated

simultaneously using the software LDAC function or the

Process control

LDAC

external

pin. The ADT7516/ADT7517/ADT7519

incorporate a power-on reset circuit, ensuring that the DAC

output powers up to 0 V and remains there until a valid write

takes place.

The wide supply voltage range, low supply current, and SPI-/

I²C-compatible interface of the ADT7516/ADT7517/ADT7519

make them ideal for a variety of applications, including

personal computers, office equipment, and domestic appliances.

¹Protected by U.S. Patent Numbers: 6,169,442; 5,867,012; and 5,764,174. Other patents pending.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADT7516/ADT7517/ADT7519

TABLE OF CONTENTS

Features .............................................................................................. 1

Terminology.................................................................................... 17

Theory of Operation ...................................................................... 19

Power-Up Calibration................................................................ 19

Conversion Speed....................................................................... 19

Function Description—Voltage Output.................................. 20

Functional Description—Analog Inputs................................. 23

ADC Transfer Function............................................................. 23

Functional Description—Measurement.................................. 25

ADT7516/ADT7517/ADT7519 Registers............................... 28

Serial Interface............................................................................ 37

SMBus Alert Response .............................................................. 42

Outline Dimensions....................................................................... 43

Ordering Guide .......................................................................... 43

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

DAC AC Characteristics.............................................................. 6

Timing Diagrams.......................................................................... 7

Functional Block Diagram .............................................................. 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Functional Descriptions........................ 10

Typical Performance Characteristics ........................................... 11

REVISION HISTORY

8/04—Rev. 0 to Rev. A

10/06—Rev. A to Rev. B

Updated Format...................................................................... Universal

Deleted ADT7518

Added ADT7519..................................................................... Universal

Change to Internal V_REFValue .............................................................5

Change to Equation.............................................................................26

Updated Format..................................................................Universal

Changes to Features..........................................................................1

Changes to General Description.....................................................1

Changes to Specifications.................................................................3

Changes to Absolute Maximum Ratings........................................9

Changes to Table 10........................................................................28

Changes to ADT7516/ADT7517/ADT7519 Registers Section......28

Changes to Serial Interface Section...............................................37

Changes to Ordering Guide...........................................................44

7/03—Initial Version: Rev. 0

Rev. B | Page 2 of 44

ADT7516/ADT7517/ADT7519

SPECIFICATIONS

Temperature range is as follows: A version: −40°C to +120°C, V_DD= 2.7 V to 5.5 V, GND = 0 V, REF_IN= 2.25 V, unless otherwise noted.

Table 1.

Parameter¹

DAC DC PERFORMANCE^{2, 3}

Min

Typ

Max

Unit

Conditions/Comments

ADT7519

Resolution

8

Bits

LSB

Relative Accuracy

Differential Nonlinearity

ADT7517

0.15

0.02

1

0.25

Guaranteed monotonic over all codes

Resolution

10

0.5

0.05

Bits

LSB

Relative Accuracy

Differential Nonlinearity

ADT7516

4

0.5

Resolution

12

2

0.02

0.4

0.3

Bits

LSB

% of FSR

mV

Relative Accuracy

Differential Nonlinearity

Offset Error

Gain Error

Lower Deadband

16

0.9

2

65

20

Lower deadband exists only if offset error is

negative, see Figure 40

Upper Deadband

60

100

mV

Upper deadband exists if V_REF= V_DDand off-set

plus gain error is positive, see Figure 41

Offset Error Drift⁴

Gain Error Drift⁴

–12

–5

ppm of FSR/°C

DC Power Supply Rejection Ratio⁴

DC Crosstalk⁴

–60

200

dB

μV

∆V_DD= 10%

See Figure 5

ADC DC ACCURACY

Resolution

Total Unadjusted Error (TUE)

Offset Error

Maximum V_DD= 5 V

10

3

2

0.5

2

Bits

2

% of FSR

Hz

V_DD= 2.7 V to 5.5 V

V_DD= 3.3 V 10%

Gain Error

ADC BANDWIDTH

ANALOG INPUTS

DC

Input Voltage Range

0

2.28

V_DD

1

V

μA

pF

MΩ

AIN1 to AIN4, C4 = 0 in Control Configuration 3

DC Leakage Current

Input Capacitance

Input Resistance

5

10

20

THERMAL CHARACTERISTICS

Internal Temperature Sensor

Accuracy @ V_DD= 3.3 V 10%

Internal reference used, averaging on

T_A= 85°C

T_A= 0°C to +85°C

T_A= –40°C to +120°C

T_A= 0°C to +85°C

T_A= –40°C to +120°C

Equivalent to 0.25°C

Drift over 10 years if part is operated at 55°C

1.5

3

5

3

5

°C

Bits

°C

0.5

2

Accuracy @ V_DD= 5 V 5%

3

Resolution

Long-Term Drift

10

0.25

Rev. B | Page 3 of 44

ADT7516/ADT7517/ADT7519

Parameter¹

Min

Typ

Max

Unit

Conditions/Comments

External transistor = 2N3906

T_A= 85°C

T_A= 0°C to +85°C

T_A= −40°C to +120°C

T_A= 0°C to +85°C

T_A= −40°C to +120°C

Equivalent to 0.25°C

High level

External Temperature Sensor

Accuracy @ V_DD= 3.3 V 10%

1.5

3

5

3

5

°C

Accuracy @ V_DD= 5 V 5%

2

3

°C

Resolution

Output Source Current

10

Bits

μA

180

11

Low level

Thermal Voltage Output

8-Bit DAC Output

Resolution

1

°C

Scale Factor

8.97

17.58

mV/°C

0 V to V_REFoutput, T_A= −40°C to +120°C

0 V to 2 V_REFoutput, T_A= −40°C to +120°C

10-Bit DAC Output

Resolution

0.25

°C

Scale Factor

2.2

4.39

mV/°C

0 V to V_REFoutput, T_A= −40°C to +120°C

0 V to 2 V_REFoutput, T_A= −40°C to +120°C

Single channel mode

CONVERSION TIMES

Slow ADC

V_DD/AIN

11.4

712

ms

μs

Averaging (16 samples) on

Averaging off

Internal Temperature

External Temperature

11.4

712

24.22

1.51

ms

μs

ms

Averaging (16 samples) on

Averaging off

Averaging (16 samples) on

Averaging off

Fast ADC

V_DD/AIN

712

μs

ms

μs

ms

μs

Averaging (16 samples) on

Averaging off

Averaging (16 samples) on

Averaging off

Averaging (16 samples) on

Averaging off

44.5

2.14

134

14.25

890

Internal Temperature

External Temperature

ROUND ROBIN UPDATE RATE⁵

Time to complete one measurement cycle

through all channels

Slow ADC @ 25°C

Averaging On

Averaging Off

Averaging On

Averaging Off

79.8

4.99

94.76

9.26

ms

AIN1 and AIN2 are selected on Pin 7 and Pin 8

D+ and D– are selected on Pin 7 and Pin 8

Fast ADC @ 25°C

Averaging On

Averaging Off

Averaging On

Averaging Off

6.41

ms

μs

ms

AIN1 and AIN2 are selected on Pin 7 and Pin 8

D+ and D– are selected on Pin 7 and Pin 8

400.84

21.77

3.07

DAC EXTERNAL REFERENCE INPUT⁴

V_REFInput Range

1

V_DD

V

Buffered reference

V_REFInput Impedance

Reference Feedthrough

Channel-to-Channel Isolation

>10

–90

–75

MΩ

dB

Buffered reference and power-down mode

Frequency = 10 kHz

Rev. B | Page 4 of 44

ADT7516/ADT7517/ADT7519

Parameter¹

Min

Typ

Max

Unit

Conditions/Comments

ON-CHIP REFERENCE

Reference Voltage⁴

Temperature Coefficient⁴

OUTPUT CHARACTERISTICS⁴

Output Voltage⁶

2.2662 2.28

80

2.2938

V

ppm/°C

0.001

V_DD− 0.1

V

This is a measure of the minimum and maximum

drive capability of the output amplifier

DC Output Impedance

Short Circuit Current

0.5

25

16

2.5

5

Ω

mA

μs

V_DD= 5 V

V_DD= 3 V

Power-Up Time

Coming out of power-down mode, V_DD= 5 V

Coming out of power-down mode, V_DD= 3.3 V

μs

DIGITAL INPUTS⁴

Input Current

1

0.8

μA

V

pF

ns

V_IN= 0 V to V_DD

V_IL, Input Low Voltage

V_IH, Input High Voltage

Pin Capacitance

1.89

3

10

50

All digital inputs

Input filtering suppresses noise spikes of less

than 50 ns

SCL, SDA Glitch Rejection

LDAC Pulse Width

20

ns

Edge triggered input

DIGITAL OUTPUT

Digital High Voltage, V_OH

Output Low Voltage, V_OL

Output High Current, I_OH

Output Capacitance, C_OUT

INT/INT Output Saturation Voltage

2.4

V

mA

pF

V

I_SOURCE= I_SINK= 200 μA

I_OL= 3 mA

V_OH= 5 V

0.4

1

50

0.8

I

_OUT= 4 mA

I²C TIMING CHARACTERISTICS^{7, 8}

Serial Clock Period, t₁

Data In Setup Time to SCL High, t₂

Data Out Stable after SCL Low, t₃

SDA Low Setup Time to SCL

Low (Start Condition), t₄

2.5

50

0

μs

ns

Fast mode I²C, see Figure 2

See Figure 2

50

SDA High Hold Time after SCL

High (Stop Condition), t₅

50

ns

See Figure 2

SDA and SCL Fall Time, t₆

SDA and SCL Rise Time, t₇

SPI TIMING CHARACTERISTICS^{4, 10}

CS to SCLK Setup Time, t₁

SCLK High Pulse Width, t₂

SCLK Low Pulse Width, t₃

Data Access Time after SCLK

300

ns

See Figure 2

300⁹

0

ns

See Figure 3

50

35

11

Falling Edge, t₄

Data Setup Time Prior to SCLK

Rising Edge, t₅

Data Hold Time after SCLK

Rising Edge, t₆

20

0

ns

See Figure 3

CS to SCLK Hold Time, t₇

0

μs

ns

See Figure 3

CS to DOUT High Impedance, t₈

40

POWER REQUIREMENTS

V_DD

V_DDSettling Time

I_DD(Normal Mode)¹²

2.7

5.5

50

3

V

ms

mA

V_DDsettles to within 10% of its final voltage level

V_DD= 3.3 V, V_IH= V_DD, and V_IL= GND

V_DD= 5 V, V_IH= V_DD, and V_IL= GND

2.2

3

Rev. B | Page 5 of 44

ADT7516/ADT7517/ADT7519

Parameter¹

Min

Typ

Max

10

33

Unit

μA

mW

μW

Conditions/Comments

I_DD(Power-Down Mode)

V_DD= 3.3 V, V_IH= V_DD, and V_IL= GND

V_DD= 5 V, V_IH= V_DD, and V_IL= GND

V_DD= 3.3 V, normal mode

Power Dissipation

V_DD= 3.3 V, shutdown mode

¹See the Terminology section.

²DC specifications are tested with the outputs unloaded.

³Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).

⁴Guaranteed by design and characterization, not production tested.

⁵Round robin is the continuous sequential measurement of the following channels: V_DD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.

⁶For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (V_REF= V_DD), the offset

plus gain error must be positive.

⁷The SDA and SCL timing is measured with the input filters turned on to meet the fast mode I²C specification. Switching off the input filters improves the transfer rate

but has a negative effect on the EMC behavior of the part.

⁸Guaranteed by design, not production tested. All I²C timing specifications are for fast mode operation but the interface is still capable of handling the slower standard

rate specifications.

9

The interface is also capable of handling the I²C standard mode rise time specification of 1000 ns.

¹⁰All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD), and timed from a voltage level of 1.6 V.

¹¹Measured with the load circuit shown in Figure 4.

¹²The I_DDspecification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.

DAC AC CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, R_L= 4.7 kΩ to GND, C_L= 200 pF to GND, 4.7 kΩ to V_DD, all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter^{1, 2}

Min

Typ³

Max

Unit

Conditions/Comments

Output Voltage Settling Time

ADT7519

ADT7517

V_REF= V_DD= 5 V

6

7

8

9

10

μs

1/4 scale to 3/4 scale change (0x40 to 0xC0)

1/4 scale to 3/4 scale change (0x100 to 0x300)

1/4 scale to 3/4 scale change (0x400 to 0xC00)

ADT7516

Slew Rate

0.7

12

0.5

1

0.5

3

V/μs

nV-s

kHz

dB

Major-Code Change Glitch Energy

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

1 LSB change around major carry

200

–70

V_REF= 2 V 0.1 V p-p

V_REF= 2.5 V 0.1 V p-p; frequency = 10 kHz

¹See the Terminology section.

²Guaranteed by design and characterization, not production tested.

³At 25°C.

Rev. B | Page 6 of 44

ADT7516/ADT7517/ADT7519

TIMING DIAGRAMS

t₁

SCL

t₅

t₂

t₄

SDA

DATA IN

t₃

SDA

DATA OUT

t₆

Figure 2. I²C Bus Timing Diagram

CS

t₁

t₂

t₇

SCLK

DIN

t₆

t₃

t₅

t₈

D7

X

D6

X

D5

X

D4

D3

X

D2

D1

D0

X

t₄

DOUT

X

D7

D6

D5

D4

D3

D2

D1

D0

Figure 3. SPI Bus Timing Diagram

200µA

I

OL

TO OUTPUT

1.6V

C

L

50pF

200µA

I

OH

Figure 4. Load Circuit for Access Time and Bus Relinquish Time

V

DD

4.7kΩ

TO DAC

OUTPUT

4.7kΩ

200pF

Figure 5. Load Circuit for DAC Outputs

Rev. B | Page 7 of 44

ADT7516/ADT7517/ADT7519

FUNCTIONAL BLOCK DIAGRAM

INTERNAL

TEMPERATURE

VALUE REGISTER

ADT7516/ADT7517/ADT7519

ON-CHIP

TEMPERATURE

ADDRESS POINTER

REGISTER

SENSOR

EXTERNAL

T

LIMIT

HIGH

REGISTERS

TEMPERATURE

VALUE REGISTER

T

LIMIT

LOW

REGISTERS

DAC A

STRING

DAC A

7

8

D+/AIN1

D–/AIN2

LDAC/AIN3

AIN4

2

1

V

-A

-B

-C

-D

OUT

REGISTERS

V

LIMIT

CC

REGISTERS

LIMIT

COMPARATOR

A-TO-D

ANALOG

MUX

CONVERTER

AIN LIMIT

HIGH

REGISTERS

DAC B

REGISTERS

STRING

DAC B

9

14

AIN

REGISTERS

LIMIT

LOW

V

DD

DAC C

REGISTERS

STRING

DAC C

16

15

VALUE REGISTER

CONTROL CONFIG. 1

REGISTER

AIN1

VALUE REGISTER

CONTROL CONFIG. 2

REGISTER

V

DD

SENSOR

DAC D

REGISTERS

STRING

DAC D

AIN2

VALUE REGISTER

CONTROL CONFIG. 3

REGISTER

AIN3

GAIN

SELECT

LOGIC

POWER-

DOWN

LOGIC

DAC CONFIGURATION

REGISTERS

VALUE REGISTER

AIN4

VALUE REGISTER

LDAC CONFIGURATION

REGISTERS

10

INT/INT

INTERRUPT MASK

REGISTERS

STATUS

REGISTERS

INTERNAL

REFERENCE

SPI/SMBus INTERFACE

6

5

4

13

12

11

9

3

V

GND

CS

SCL

SDA

ADD

LDAC/AIN3

V

-IN

REF

DD

Figure 6. Functional Block Diagram for the ADT7516/ADT7517/ADT7519

Rev. B | Page 8 of 44

ADT7516/ADT7517/ADT7519

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

–0.3 V to +7 V

Analog Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

Reference Input Voltage to GND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

Power Dissipation¹

–0.3 V to V_DD+ 0.3 V

–40°C to +120°C

–65°C to +150°C

150°C

Table 4. I²C Address Selection

ADD Pin

I²C Address

1001 000

1001 010

1001 011

Low

Float

High

(T_Jmax – T_A)/θ_JA

Thermal Impedance²

θ_JAJunction-to-Ambient

θ_JCJunction-to-Case

105.44°C/W

38.8°C/W

IR Reflow Soldering

Peak Temperature

ESD CAUTION

220°C (0°C/5°C)

Time at Peak Temperature

Ramp-Up Rate

Ramp-Down Rate

Time 25°C to Peak Temperature

IR Reflow Soldering (Pb-Free Package)

Peak Temperature

10 sec to 20 sec

3°C/sec maximum

–6°C/sec maximum

6 min maximum

260°C (+0°C)

Time at Peak Temperature

Ramp-Up Rate

Ramp-Down Rate

20 sec to 40 sec

3°C/sec maximum

–6°C/sec maximum

8 min maximum

Time 25°C to Peak Temperature

¹Values relate to the package being used on a 4-layer board.

²Junction-to-case resistance is applicable to components featuring a

preferential flow direction, for example, components mounted on a heat

sink. Junction-to-ambient resistance is more useful for air cooled PCB-

mounted components.

Rev. B | Page 9 of 44

ADT7516/ADT7517/ADT7519

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

V

-B

1

2

3

4

5

6

7

8

16

V

-C

OUT

V

-A

15

V

-D

OUT

ADT7516/

ADT7517/

ADT7519

V

-IN

CS

14 AIN4

REF

13 SCL/SCLK

12 SDA/DIN

11 DOUT/ADD

10 INT/INT

TOP VIEW

(Not to Scale)

GND

V

DD

D+/AIN1

D–/AIN2

9

LDAC/AIN3

Figure 7. Pin Configuration (QSOP Package)

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

V_OUT-B

V_OUT-A

V_REF-IN

CS

Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to V_DD.

SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables

the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial

clocks. It is recommended that this pin be tied high to V_DDwhen operating the serial interface in I²C mode.

5

6

7

GND

V_DD

D+/AIN1

Ground Reference Point. Ground reference point for all circuitry on the part. Analog and digital ground.

Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.

D+: Positive Connection to External Temperature Sensor.

AIN1: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V_DD.

D–: Negative Connection to External Temperature Sensor.

AIN2: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V_DD.

8

9

D–/AIN2

LDAC/AIN3 LDAC: Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A

falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum

pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows

simultaneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is

with the LDAC pin controlling the loading of the DAC registers.

AIN3: Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V_DD.

10

11

INT/INT

Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when

temperature, V_DD, or AIN limits are exceeded. The default is active low. Open-drain output, needs a pull-up resistor.

DOUT/ADD DOUT: SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the

falling edge of SCLK. Open-drain output, needs a pull-up resistor.

ADD: I²C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the Address 1001 000; leaving it floating

gives the Address 1001 010; and setting it high gives the address 1001 011. The I²C address set up by the ADD pin is

not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid

communication, the serial bus address is latched in. Any subsequent change on this pin has no effect on the I²C serial

bus address.

12

13

SDA/DIN

SCL/SCLK

SDA: I²C Serial Data Input/Output. I²C serial data to be loaded into the registers of the part and read from these

registers is provided on this pin. Open-drain configuration, needs a pull-up resistor.

DIN: SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into

a register on the rising edge of SCLK. Open-drain configuration, needs a pull-up resistor.

Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of

the ADT7516/ADT7517/ADT7519, and also to clock data into any register that can be written to. Open-drain

configuration, needs a pull-up resistor.

14

15

16

AIN4

V_OUT-D

V_OUT-C

Analog Input. Single-ended analog input channel. Input range is 0 V to 2.28 V or 0 V to V_DD.

Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Rev. B | Page 10 of 44

ADT7516/ADT7517/ADT7519

TYPICAL PERFORMANCE CHARACTERISTICS

0.10

0.08

0.06

0.04

0.02

0

0.20

0.15

0.10

0.05

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.05

–0.10

–0.15

–0.20

0

50

100

150

200

250

0

50

100

150

200

250

DAC CODE

Figure 8. ADT7519 Typical DAC INL Plot

Figure 11. ADT7519 Typical DAC DNL Plot

0.6

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.2

–0.4

–0.6

0

200

400

600

800

1000

0

200

400

600

800

1000

DAC CODE

Figure 9. ADT7517 Typical DAC INL Plot

Figure 12. ADT7517 Typical DAC DNL Plot

1.0

0.8

2.5

2.0

1.5

0.6

0.4

1.0

0.2

0.5

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.5

–1.0

–1.5

–2.0

–2.5

0

500

1000

1500

2000

2500

3000

3500 4000

0

500

1000

1500

2000

2500

3000

3500 4000

DAC CODE

Figure 10. ADT7516 Typical DAC INL Plot

Figure 13. ADT7516 Typical DAC DNL Plot

Rev. B | Page 11 of 44

ADT7516/ADT7517/ADT7519

0.30

10

5

0.25

OFFSET ERROR

INL WCP

0.20

0.15

0.10

0

V

= 2.25V

REF

–5

0.05

0

DNL WCP

–10

DNL WCN

INL WCN

GAIN ERROR

–15

–20

–0.05

–0.10

1.0 1.5

2.0

2.5

3.0

(V)

3.5

4.0

4.5

5.0

2.7

3.3

3.6

4.0

(V)

4.5

5.0

5.5

V

DD

REF

Figure 14. ADT7519 DAC INL and DNL Error vs. V_REF

Figure 17. DAC Offset Error and Gain Error vs. V_DD

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0

2.505

2.500

2.495

2.490

2.485

2.480

2.475

2.470

2.465

INL WCP

INL WCN

SOURCE CURRENT

SINK CURRENT

DNL WCP

DNL WCN

V

= 5V

DD

–0.02

–0.04

–0.06

REF

DAC OUTPUT

LOADED TO MIDSCALE

–40

–10

20

50

80

110

0

1

2

3

4

5

6

TEMPERATURE (°C)

CURRENT (mA)

Figure 15. ADT7519 DAC INL Error and DNL Error vs. Temperature

Figure 18. DAC V_OUTSource and Sink Current Capability

1.98

0

DAC OUTPUT UNLOADED

–0.2

1.96

1.94

1.92

1.90

1.88

1.86

OFFSET ERROR

–0.4

–0.6

–0.8

–1.0

–1.2

DAC OUTPUT LOADED

–1.4

GAIN ERROR

–1.6

–1.8

0

500 1000

1500

2000

2500

3000

3500

4000

–40

–20

0

20

40

60

80

100

120

DAC CODE

TEMPERATURE (°C)

Figure 19. Supply Current vs. DAC Code

Figure 16. DAC Offset Error and Gain Error vs. Temperature

Rev. B | Page 12 of 44

ADT7516/ADT7517/ADT7519

2.00

1.95

1.90

1.85

1.80

1.75

1.8

1.6

ADC OFF

DAC OUTPUTS AT 0V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

0

2

4

6

8

10

V

(V)

CC

TIME (µs)

Figure 20. Supply Current vs. Supply Voltage @ 25°C

Figure 23. Exiting Power-Down to Midscale

0.4700

0.4695

0.4690

0.4685

0.4680

0.4675

0.4670

0.4665

0.4660

0.4655

0.4650

7

6

5

4

3

2

1

0

2

4

6

8

10

2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

V

(V)

TIME (µs)

CC

Figure 24. ADT7516 DAC Major Code Transition Glitch Energy;

011…11 to 100...00

Figure 21. Power-Down Current vs. Supply Voltage @ 25°C

0.4730

0.4725

0.4720

0.4715

0.4710

0.4705

0.4700

0.4695

0.4690

0.4685

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

0

2

4

6

8

10

TIME (µs)

Figure 25. ADT7516 DAC Major Code Transition Glitch Energy;

100…00 to 011…11

Figure 22. DAC Half-Scale Settling (1/4 to 3/4 Scale Code Change)

Rev. B | Page 13 of 44

ADT7516/ADT7517/ADT7519

0

–10

–20

–30

–40

–50

–60

V

= 5V

DD

= 25°C

±100mV RIPPLE ON V

CC

T

A

V

= 2.25V

= 3.3V

REF

–2

DD

TEMPERATURE = 25°C

–4

–6

–8

–10

–12

1

10

100

1

2

3

4

5

FREQUENCY (kHz)

V

(V)

REF

Figure 26. DAC Full-Scale Error vs. V_REF

Figure 29. PSRR vs. Supply Ripple Frequency

2.329

2.328

2.327

2.326

2.325

2.324

2.323

2.322

1.5

1.0

0.5

0

V

= 5V

DD

EXTERNAL TEMPERATURE @ 5V

INTERNAL TEMPERATURE @ 3.3V

= 5V

REF

DAC OUTPUT LOADED

TO MIDSCALE

–0.5

–1.0

EXTERNAL TEMPERATURE @ 3.3V

INTERNAL TEMPERATURE @ 5V

–30

0

40

85

120

0

1

2

3

4

5

TEMPERATURE (°C)

TIME (µs)

Figure 27. DAC-to-DAC Crosstalk

Figure 30. Internal Temperature Error @ 3.3 V and 5 V

3

2

1.0

0.8

V

= 3.3V

DD

0.6

OFFSET ERROR

1

0.4

0.2

0

–1

–2

–3

–4

–0.2

–0.4

–0.6

–0.8

–1.0

GAIN ERROR

–40

–20

0

20

40

60

80

100

120

0

200

400

600

800

1000

TEMPERATURE (°C)

ADC CODE

Figure 31. ADC Offset Error and Gain Error vs. Temperature

Figure 28. ADC INL with V_REF= V_DD(3.3 V)

Rev. B | Page 14 of 44

ADT7516/ADT7517/ADT7519

3

2

1

0

10

8

V

= 3.3V

DD

COMMON-MODE

VOLTAGE = 100mV

OFFSET ERROR

6

4

2

0

–1

–2

–3

–2

–4

–6

GAIN ERROR

2.7

3.1

3.5

3.9

4.3

(V)

4.7

5.1

5.5

1

100

200

300

400

500

600

V

NOISE FREQUENCY (Hz)

DD

Figure 32. ADC Offset Error and Gain Error vs. V_DD

Figure 35. External Temperature Error vs. Common-Mode Noise Frequency

15

70

V

= 3.3V

DD

V

= 3.3V

TEMPERATURE = 25°C

DD

DIFFERENTIAL-MODE

VOLTAGE = 100mV

10

5

60

50

40

30

20

10

0

D+ TO GND

0

–5

D+ TO V

CC

–10

–15

–20

–25

–10

0

10

20

30

40

50

60

70

80

90 100

1

100

200

300

400

500

600

PCB LEAKAGE RESISTANCE (MΩ)

NOISE FREQUENCY (MHz)

Figure 33. External Temperature Error vs. PCB Leakage Resistance

Figure 36. External Temperature Error vs. Differential-

Mode Noise Frequency

0.6

0.4

0

V

= 3.3V

DD

V

= 3.3V

DD

–10

–20

–30

–40

–50

–60

0.2

0

–0.2

–0.4

–0.6

±250mV

1

100

200

300

400

500

600

0

5

10

15

20

25

30

35

40

45

50

NOISE FREQUENCY (Hz)

CAPACITANCE (nF)

Figure 37. Internal Temperature Error vs. Power Supply Noise Frequency

Figure 34. External Temperature Error vs. Capacitance Between D+ and D–

Rev. B | Page 15 of 44

ADT7516/ADT7517/ADT7519

0

140

EXTERNAL TEMPERATURE

120

–5

100

INTERNAL TEMPERATURE

–10

–15

–20

–25

80

60

40

TEMPERATURE OF

ENVIRONMENT

20

0

CHANGED HERE

0

10

100

1k

10k

100k

1M

10M

1

10

20

30

40

50

60

TIME (s)

FREQUENCY (Hz)

Figure 38. Temperature Sensor Response to Thermal Shock

Figure 39. DAC Multiplying Bandwidth (Small Signal Frequency Response)

Rev. B | Page 16 of 44

ADT7516/ADT7517/ADT7519

TERMINOLOGY

Unfortunately, integrated circuits cannot be evaluated at room

temperature (25°C) for 10 years or so to determine this shift.

Manufacturers perform accelerated lifetime testing of integrated

circuits by operating ICs at elevated temperatures (between

125°C and 150°C) over a shorter period (typically between

500 hours and 1000 hours). As a result, the lifetime of an

integrated circuit is significantly accelerated due to the increase

in rates of reaction within the semiconductor material.

Relative Accuracy

Relative accuracy or integral nonlinearity (INL) is a measure of

the maximum deviation, in LSBs, from a straight line passing

through the endpoints of the transfer function. Typical INL vs.

code plots are shown in Figure 8, Figure 9, and Figure 10.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 0.9 LSB maximum

ensures monotonicity. Typical DAC DNL vs. code plots can be

seen in Figure 11, Figure 12, and Figure 13.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by

changes in the supply voltage. PSRR is the ratio of the change in

V_OUTto a change in V_DDfor full-scale output of the DAC. It is

measured in dB. V_REFis held at 2 V and V_DDis varied 10ꢀ.

Total Unadjusted Error (TUE)

Total unadjusted error is a comprehensive specification that

includes the sum of the relative accuracy error, gain error, and

offset error under a specified set of conditions.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is

measured with a full-scale output change on one DAC while

monitoring another DAC. It is expressed in ꢁV.

Offset Error

Offset error is a measure of the offset error of the DAC and the

output amplifier (see Figure 40 and Figure 41). It can be

negative or positive, and it is expressed in mV.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is, LDAC is high). It is expressed in dB.

Offset Error Match

Offset error match is the difference in offset error between any

two channels.

Channel-to-Channel Isolation

Gain Error

Channel-to-channel isolation is the ratio of the amplitude of the

signal at the output of one DAC to a sine wave on the reference

input of another DAC. It is measured in dB.

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the actual DAC transfer characteristic from

the ideal expressed as a percentage of the full-scale range.

Major Code Transition Glitch Energy

Gain Error Match

Gain error match is the difference in gain error between any

two channels.

Major code transition glitch energy is the energy of the impulse

injected into the analog output when the code in the DAC

register changes state. It is normally specified as the area of the

glitch in nV-s and is measured when the digital code is changed

by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00

or 100 . . . 00 to 011 . . . 11).

Offset Error Drift

Offset error drift is a measure of the change in offset error

with changes in temperature. It is expressed in ppm of

full-scale range/°C.

Digital Feedthrough

Gain Error Drift

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device. However, it is measured when the DAC is not being

written to. It is specified in nV-s and is measured with a full-

scale change on the digital input pins, that is, from all 0s to all

1s or vice versa.

Gain error drift is a measure of the change in gain error

with changes in temperature. It is expressed in ppm of

full-scale range/°C.

Long-Term Temperature Drift

Long-term temperature drift is a measure of the change in

temperature error with the passage of time. It is expressed in °C.

The concept of long-term stability has been used for many years

to describe the amount an IC parameter shifts during its

lifetime. This is a concept that has typically been applied to both

voltage references and monolithic temperature sensors.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s and vice versa) in the input register of another

DAC. It is measured in standalone mode and is expressed in nV-s.

Rev. B | Page 17 of 44

ADT7516/ADT7517/ADT7519

Analog Crosstalk

GAIN ERROR

+

OFFSET ERROR

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

code change (all 0s to all 1s and vice versa) while keeping

OUTPUT

VOLTAGE

LDAC

high. Then pulse

low and monitor the output of

the DAC whose digital code was not changed. The area of the

glitch is expressed in nV-s.

NEGATIVE

DAC-to-DAC Crosstalk

DAC CODE

OFFSET

ERROR

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s and vice versa) with

ACTUAL

IDEAL

LOWER

DEADBAND

CODES

LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nV-s.

AMPLIFIER

FOOTROOM

Multiplying Bandwidth

The multiplying bandwidth is a measure of the finite bandwidth

of the amplifiers within the DAC. A sine wave on the reference

(with full-scale code loaded to the DAC) appears on the output.

The multiplying bandwidth is the frequency at which the output

amplitude falls to 3 dB below the input.

NEGATIVE

OFFSET

ERROR

Figure 40. DAC Transfer Function with Negative Offset

Total Harmonic Distortion (THD)

GAIN ERROR

THD is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used as

the reference for the DAC, and the THD is a measure of the

harmonics present on the DAC output, expressed in dB.

+

OFFSET ERROR

UPPER

DEADBAND

CODES

OUTPUT

VOLTAGE

Round Robin

The term round robin is used to describe the ADT7516/ADT7517/

ADT7519 cycling through the available measurement channels

in sequence, taking a measurement on each channel.

ACTUAL

IDEAL

POSITIVE

OFFSET

ERROR

DAC Output Settling Time

DAC CODE

FULL-SCALE

DAC output settling time is the time required, following a

prescribed data change, for the output of a DAC to reach and

remain within 0.5 LSB of the final value. A typical prescribed

change is from 1/4 scale to 3/4 scale.

Figure 41. DAC Transfer Function with Positive Offset (V_REF= V_DD

)

Rev. B | Page 18 of 44

ADT7516/ADT7517/ADT7519

THEORY OF OPERATION

DAC A and DAC B outputs can be configured to give a voltage

output proportional to the temperature of the internal and

external temperature sensors, respectively.

Directly after the power-up calibration routine, the ADT7516/

ADT7517/ADT7519 go into idle mode. In this mode, the

devices are not performing any measurements and are fully

powered up. All four DAC outputs are at 0 V.

The dual serial interface defaults to the I²C protocol on power-

up. To select and lock in the SPI protocol, follow the selection

process as described in the Serial Interface Selection section.

The I²C protocol cannot be locked in, though the SPI protocol

is automatically locked in on selection. The interface can be

To begin monitoring, write to the Control Configuration 1

register (Address 0x18) and set Bit C0 = 1. The ADT7516/

ADT7517/ADT7519 go into the power-up default measurement

mode (round robin). The devices proceed to take measurements

on the V_DDchannel, internal temperature sensor channel,

external temperature sensor channel (AIN1 and AIN2), AIN3,

and finally AIN4. After they finish taking measurements on the

AIN4 channel, the devices immediately loop back to start

taking measurements on the V_DDchannel and repeat the same

cycle as before. This loop continues until the monitoring is

stopped by resetting Bit C0 of the Control Configuration 1

register to 0.

switched back to be I²C on selection when the device is powered

2

CS

off and on. When using I C, the

V_DDor GND.

pin should be tied to either

There are a number of different operating modes on the

ADT7516/ADT7517/ADT7519 devices and all of them can be

controlled by the configuration registers. These features consist

INT

of enabling and disabling interrupts, polarity of the INT/

pin, enabling and disabling the averaging on the measurement

channels SMBus timeout, and software reset.

It is also possible to continue monitoring as well as switching to

single-channel mode by writing to the Control Configuration 2

register (Address 0x19) and setting Bit C4 = 1. Further explana-

tion of the single-channel and round robin measurement modes

is given in later sections. All measurement channels have

averaging enabled on them at power-up. Averaging forces the

devices to take an average of 16 readings before giving a final

measured result. To disable averaging and consequently

decrease the conversion time by a factor of 16, set Bit C5 = 1 in

the Control Configuration 2 register.

POWER-UP CALIBRATION

It is recommended that no communication to the part be

initiated until approximately 5 ms after V_DDhas settled to

within 10ꢀ of its final value. It is generally accepted that most

systems take a maximum of 50 ms to power up. Power-up time

is directly related to the amount of decoupling on the voltage

supply line.

During the 5 ms after V_DDhas settled, the part is performing a

calibration routine. Any communication to the device during

calibration interrupts this routine, and can cause erroneous

temperature measurements. If it is not possible to have V_DDat its

nominal value by the time 50 ms has elapsed or if communication

to the device has started prior to V_DDsettling, it is recommended

that a measurement be taken on the V_DDchannel before a

temperature measurement is taken. The V_DDmeasurement is

used to calibrate out any temperature measurement error due to

different supply voltage values.

There are four single-ended analog input channels on the

ADT7516/ADT7517/ADT7519, AIN1 to AIN4. AIN1 and

AIN2 are multiplexed with the external temperature sensor

terminals (D+ and D−). Bit C1 and Bit C2 of the Control

Configuration 1 register (Address 0x18) are used to select

between AIN1/AIN2 and the external temperature sensor.

The input range on the analog input channels is dependent on

whether the ADC reference used is the internal V_REFor V_DD. To

meet linearity specifications, it is recommended that the maximum

CONVERSION SPEED

V_DDvalue is 5 V. Bit C4 of the Control Configuration 3 register

be used to select between the internal reference and V_DDas the

ADC reference of the analog inputs.

The internal oscillator circuit used by the ADC has the capability

to output two different clock frequencies. This means that the

ADC is capable of running at two different speeds when doing a

conversion on a measurement channel. Thus, the time taken to

perform a conversion on a channel can be reduced by setting

Bit C0 of the Control Configuration 3 register (Address 0x1A).

This increases the ADC clock speed from 1.4 kHz to 22 kHz. At

the higher clock speed, the analog filters on the D+ and D–

input pins (external temperature sensors) are switched off. This

is why the power-up default setting is to have the ADC working

at the slow speed. The typical times for fast and slow ADC

speeds are given in the Specifications section.

Controlling the DAC outputs can be done by writing to the MSB

and LSB registers of the DAC (Address 0x10 to Address 0x17).

The power-up default setting is to have a low going pulse on the

LDAC

pin (Pin 9) controlling the updating of the DAC outputs

from the DAC registers. Alternatively, one can configure the

updating of the DAC outputs to be controlled by means other

LDAC

than the

pin by setting Bit C3 = 1 of the Control

Configuration 3 register (Address 0x1A). The DAC configura-

tion register (Address 0x1B) and the LDAC configuration

register (Address 0x1C) can now be used to control the DAC

updating. These two registers also control the output range of

the DACs and select between the internal or external reference.

Rev. B | Page 19 of 44

ADT7516/ADT7517/ADT7519

The ADT7516/ADT7517/ADT7519 power up with averaging

on. This means every channel is measured 16 times and inter-

nally averaged to reduce noise. The conversion time can also be

sped up by turning off the averaging. This is done by setting

Bit C5 of the Control Configuration 2 register (Address 0x19) to 1.

0 to 255 for ADT7519 (8 bits)

0 to 1023 for ADT7517 (10 bits)

0 to 4095 for ADT7516 (12 bits)

N = DAC resolution.

Resistor String

FUNCTION DESCRIPTION—VOLTAGE OUTPUT

The resistor string section is shown in Figure 43. It is simply a

string of resistors, each of approximately 603 Ω. The digital

code loaded to the DAC register determines at which node on

the string the voltage is tapped off to be fed into the output

amplifier. The voltage is tapped off by closing one of the

switches connecting the string to the amplifier. Because it is a

string of resistors, it is guaranteed monotonic.

Digital-to-Analog Converters

The ADT7516/ADT7517/ADT7519 have four resistor string

DACs fabricated on a CMOS process with resolutions of 12, 10,

and 8 bits, respectively. They contain four output buffer amplifiers

and are written to via I²C serial interface or SPI serial interface.

See the Serial Interface section for more information.

V

-IN

REF

The ADT7516/ADT7517/ADT7519 operate from a single

supply of 2.7 V to 5.5 V, and the output buffer amplifiers

provide rail-to-rail output swing with a slew rate of 0.7 V/μs. All

four DACs share a common reference input, V_REF-IN. The

reference input is buffered to draw virtually no current from the

reference source because it offers the source a high impedance

input. The devices have a power-down mode to completely turn

off all DACs with a high impedance output.

REFERENCE

BUFFER

INT V

DAC

REF

GAIN MODE

(GAIN = 1 OR 2)

V

-A

OUT

INPUT

REGISTER

RESISTOR

STRING

REGISTER

OUTPUT BUFFER

AMPLIFIER

Each DAC output is not updated until it receives the LDAC

command. Therefore, though the DAC registers would have

been written to with a new value, this value is not represented

by a voltage output until the DACs receive the LDAC command.

Reading back from any DAC register prior to issuing an LDAC

command results in the digital value that corresponds to the

DAC output voltage. Thus, the digital value written to the DAC

register cannot be read back until after the LDAC command has

been initiated. This LDAC command can be given by either

Figure 42. Single DAC Channel Architecture

R

TO OUTPUT

AMPLIFIER

R

LDAC

pulling the

pin low (falling edge loads DACs), setting up

Bit D4 and Bit D5 of the DAC configuration register

(Address 0x1B), or using the LDAC register (Address 0x1C).

R

LDAC

When using the

the low going pulse width should be 20 ns minimum. The

LDAC

pin to control the DAC register loading,

pin has to go high and low again before the DAC

registers can be reloaded.

Figure 43. Resistor String

Digital-to-Analog Section

V

-IN

REF

The architecture of one DAC channel consists of a resistor string

DAC followed by an output buffer amplifier. The voltage at the

2.28V

INTERNAL V

V_REF-IN pin or the on-chip reference of 2.28 V provides the

REF

reference voltage for the corresponding DAC. Figure 42 shows a

block diagram of the DAC architecture. Because the input

coding to the DAC is straight binary, the ideal output voltage is

given by

STRING

DAC A

STRING

DAC B

V_REF× D

V_OUT

=

2^N

STRING

DAC C

where:

STRING

DAC D

D = decimal equivalent of the binary code that is loaded to the

DAC register

Figure 44. DAC Reference Buffer Circuit

Rev. B | Page 20 of 44

ADT7516/ADT7517/ADT7519

DAC Reference Inputs

corresponding to 1 LSB change. The default output resolution

for the ADT7516 and ADT7517 is 8 bits. To increase this to

10 bits, set C1 = 1 in the Control Configuration 3 register. The

default output range is 0 V to V_REFand this can be increased to

0 V to 2 V_REF. Increasing the output voltage span to 2 V_REFcan

be done by setting D0 = 1 for DAC A (internal temperature

sensor) and D1 = 1 for DAC B (external temperature sensor) in

the DAC configuration register (Address 0x1B).

There is an input reference pin for the DACs. This reference

input is buffered (see Figure 44).

The advantage of the buffered input is the high impedance it

presents to the voltage source driving it. The user can have an

external reference voltage as low as 1 V and as high as V_DD. The

restriction of 1 V is due to the footroom of the reference buffer.

LDAC

The

configuration register controls the option to select

The output voltage is capable of tracking a maximum tempera-

ture range of −128°C to +127°C, but the default setting is

−40°C to +127°C. If the output voltage range is 0 V to V_REF-IN

(V_REF-IN = 2.25 V), then this corresponds to 0 V representing

−40°C, and 1.48 V representing +127°C. This, of course, gives

between internal and external voltage references. The default

selection is external reference.

Output Amplifier

The output buffer amplifier can generate output voltages to

within 1 mV of either rail. Its actual range depends on the value

of V_REF, gain, and offset error.

an upper deadband between 1.48 V and V_REF

.

The internal and external analog temperature offset registers

can be used to vary this upper deadband and, consequently, the

temperature that 0 V corresponds to. Table 6 and Table 7 give

examples of how this is done using a DAC output voltage span

of V_REFand 2 V_REF, respectively. Simply write in the temperature

value, in twos complement format, at which 0 V is to start. For

example, if using the DAC A output and 0 V to start at −40°C,

program 0xD8 into the internal analog temperature offset

register (Address 0x21). This is an 8-bit register and has a

temperature offset resolution of only 1°C for all device models.

Use Equation 1 to Equation 4 to determine the value to

program into the offset registers.

If a gain of 1 is selected (Bit 0 to Bit 3 of the DAC configuration

register = 0), the output range is 0.001 V to V_REF

.

If a gain of 2 is selected (Bit 0 to Bit 3 of the DAC configuration

register = 1), the output range is 0.001 V to 2 V_REF. Because

of clamping, however, the maximum output is limited to

V_DD− 0.001 V.

The output amplifier can drive a load of 4.7 kΩ to GND or V_DD

in parallel with 200 pF to GND or V_DD(see Figure 5). The

source and sink capabilities of the output amplifier can be seen

in the plot of Figure 18.

,

The slew rate is 0.7 V/ꢁs with a half-scale settling time to

0.5 LSB (at 8 bits) of 6 ꢁs.

Table 6. Thermal Voltage Output (0 V to V_REF

)

O/P Voltage (V) Default °C

Max °C

−128

−71

Sample °C

0

+56

+113

+127

UDB¹

Thermal Voltage Output

0

−40

0.5

1

+17

+73

The ADT7516/ADT7517/ADT7519 can output voltages that are

proportional to temperature. DAC A output can be configured

to represent the temperature of the internal sensor and the DAC B

output can be configured to represent the external temperature

sensor. Bit C5 and Bit C6 of the Control Configuration 3 register

select the temperature proportional output voltage. Each time a

temperature measurement is taken, the DAC output is updated.

The output resolution for the ADT7519 is 8 bits with 1°C change

corresponding to 1 LSB change. The output resolution for the

ADT7516 and ADT7517 is capable of 10 bits with 0.25°C change

−15

1.12

1.47

1.5

2

+87

−1

+39

+42

+99

+127

UDB¹

2.25

+127

¹Upper deadband has been reached. DAC output is not capable of increasing.

See Figure 41.

V

DD

I

N × I

I

BIAS

OPTIONAL CAPACITOR, UP TO

3nF MAX. CAN BE ADDED TO

IMPROVE HIGH FREQUENCY

NOISE REJECTION IN NOISY

ENVIRONMENTS

V

OUT+

D+

REMOTE

C1

TO ADC

SENSING

TRANSISTOR

(2N3906)

D–

BIAS

DIODE

V

OUT–

LOW-PASS

FILTER

f_C= 65kHz

Figure 45. Signal Conditioning for External Diode Temperature Sensor

Rev. B | Page 21 of 44

ADT7516/ADT7517/ADT7519

V

DD

I

N × I

I

BIAS

V

OUT+

TO ADC

INTERNAL

BIAS

DIODE

V

OUT–

SENSE

TRANSISTOR

Figure 46. Top Level Structure of Internal Temperature Sensor

For example,

Table 7. Thermal Voltage Output (0 V to 2 V_REF

)

Offset Register Code (d) = 10d = 0x0A

O/P Voltage (V)

Default °C

Max °C

–128

–114

–100

–85

–71

–65

–45

–43

Sample °C

0

+14

+28

+43

+57

+63

+83

+85

+113

+127

UDB¹

0

–40

–26

+12

+3

+17

+23

+43

+45

The following equation is used to work out the various

temperatures for the corresponding 8-bit DAC output:

0.25

0.5

0.75

1

1.12

1.47

1.5

2

2.25

2.5

2.75

3

3.25

3.5

3.75

4

8-Bit Temp = (DAC O/P)/1 LSB + (0 V Temp)

(3)

For example, if the output is 1.5 V, V_REF-IN= 2.25 V, 8-bit DAC

has an LSB size = 2.25 V/256 = 8.79 × 10^–3, and 0 V temp is at

−128°C, then the resultant temperature is

1.5/(8.79 × 10⁻³) + (−128) = +43°C

+73

+88

–15

0

The following equation is used to work out the various

temperatures for the corresponding 10-bit DAC output:

+102

+116

UDB¹

+14

+28

+42

+56

+70

+85

+99

+113

+127

10-Bit Temp = [(DAC O/P)/1 LSB] × 0.25 + (0 V Temp) (4)

For example, if the output is 0.4991 V, V_REF-IN = 2.25 V, 10-bit

DAC has an LSB size = 2.25 V/1024 = 2.197 × 10^–3, and 0 V

temperature is at −40°C, then the resulting temperature is

[0.4991/(2.197 × 10^–3)] × 0.25 + (–40) = +16.75°C

Figure 47 shows a graph of the DAC output vs. temperature for

a V_REF-IN = 2.25 V.

4.25

4.5

2.25

2.10

1.95

¹Upper deadband has been reached. DAC output is not capable of increasing.

See Figure 41.

0V = –128°C

1.80

1.65

1.50

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0

For negative temperatures,

Offset Register Code (d) = (0 V Temp) + 128

(1)

0V = –40°C

where D7 of Offset Register Code is set to 1 for negative

temperatures.

For example,

0V = 0°C

Offset Register Code (d) = −40 + 128 = 88d = 0x58

Since a negative temperature has been inserted into the

equation, DB7 (MSB) of the offset register code is set to 1.

Therefore, 0x58 becomes 0xD8.

–128–110 –90 –70 –50 –30 –10 10 30 50 70 90 110 127

TEMPERATURE (°C)

0x58 + DB7(1) = 0xD8

For positive temperatures,

Figure 47. DAC Output vs. Temperature V_REF-IN = 2.25 V

Offset Register Code (d) = 0 V Temp

(2)

Rev. B | Page 22 of 44

ADT7516/ADT7517/ADT7519

the comparator to become unbalanced. The control logic and

the DAC are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back into

a balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 51 shows the ADC transfer function for the

analog inputs.

FUNCTIONAL DESCRIPTION—ANALOG INPUTS

Single-Ended Inputs

The ADT7516/ADT7517/ADT7519 offer four single-ended

analog input channels. The analog input range is from 0 V to

2.28 V, or 0 V to V_DD. To maintain the linearity specification, it

is recommended that the maximum V_DDvalue be set at 5 V.

Selection between the two input ranges is done by Bit C4 of the

Control Configuration 3 register (Address 0x1A). Setting this

bit to 0 sets up the analog input ADC reference to be sourced

from the internal voltage reference of 2.28 V. Setting the bit to 1

ADC TRANSFER FUNCTION

The output coding of the ADT7516/ADT7517/ADT7519 analog

inputs is straight binary. The designed code transitions occur

midway between successive integer LSB values (that is, 1/2 LSB,

3/2 LSB). The LSB is V_DD/1024 or internal V_REF/1024, internal

sets up the ADC reference to be sourced from V_DD

.

The ADC resolution is 10 bits and is mostly suitable for dc

input signals. Bits[C1:C2] of the Control Configuration 1

register (Address 0x18) are used to set up Pin 7 and Pin 8 as

AIN1 and AIN2. Figure 48 shows the overall view of the

4-channel analog input path.

V_REF= 2.28 V. The ideal transfer characteristic is shown in

Figure 51.

111...111

111...110

M

U

L

T

I

AIN1

AIN2

AIN3

AIN4

111...000

011...111

TO ADC

VALUE

REGISTER

10-BIT

ADC

P

L

E

X

E

R

1LSB = INT V

REF

/1024

1LSB = V /1024

DD

000...010

000...001

000...000

Figure 48. Quad Analog Input Path

0V 1/2LSB

+V

– 1LSB

REF

ANALOG INPUT

Converter Operation

Figure 51. Single-Ended Transfer Function

The analog input channels use a successive approximation ADC

based on a capacitor DAC. Figure 49 and Figure 50 show simpli-

fied schematics of the ADC. Figure 49 shows the ADC during

acquisition phase. SW2 is closed and SW1 is in Position A.

The comparator is held in a balanced condition and the

sampling capacitor acquires the signal on AIN.

To work out the voltage on any analog input channel, the

following method can be used:

1 LSB = reference (V)/1024

Convert value read back from AIN value register into decimal.

AIN voltage = AIN value (d) × LSB size

where d = decimal.

INT V

V

REF

DD

REF

CAP DAC

SAMPLING

CAPACITOR

A

For example, if internal reference is used, V_REF= 2.28 V.

AIN value = 512d

AIN

SW1

B

ACQUISITION

PHASE

1 LSB size = 2.28 V/1024 = 2.226 × 10⁻³

SW2

AIN voltage = 512 × 2.226 × 10⁻³= 1.14 V

CONTROL

LOGIC

REF/2

Analog Input ESD Protection

COMPARATOR

Figure 52 shows the input structure on any of the analog input

pins that provide ESD protection. The diode provides the main

ESD protection for the analog inputs. Care must be taken that

the analog input signal never drops below the GND rail by

more than 200 mV. If this happens, the diode becomes forward-

biased and starts conducting current into the substrate. The

4 pF capacitor is the typical pin capacitance and the resistor is a

lumped component made up of the on resistance of the

multiplexer switch.

Figure 49. ADC Acquisition Phase

INT V

V

DD

REF

CAP DAC

SAMPLING

CAPACITOR

A

AIN

SW1

B

CONVERSION

PHASE

SW2

CONTROL

LOGIC

REF/2

COMPARATOR

Figure 50. ADC Conversion Phase

When the ADC eventually goes into conversion phase (see

Figure 50), SW2 opens and SW1 moves to Position B, causing

Rev. B | Page 23 of 44

ADT7516/ADT7517/ADT7519

100Ω

voltage limits are not masked out, then any out-of-limit compari-

sons generate flags that are stored in the Interrupt Status 1

register (Address = 0x00) and one or more out-of-limit results

AIN

4pF

INT

cause the INT/

output to pull either high or low depending

Figure 52. Equivalent Analog Input ESD Circuit

on the output polarity setting. It is good design practice to mask

out interrupts for channels that are of no concern to the

application. Figure 53 shows the interrupt structure for the

ADT7516/ ADT7517/ADT7519. It gives a block diagram

representation of how the various measurement channels affect

AIN Interrupts

The measured results from the AIN inputs are compared with

the AIN V_HIGH(greater than comparison) and V_LOW(less than or

equal to comparison) limits. An interrupt occurs if the AIN

inputs exceed or equal the limit registers. These voltage limits

are stored in on-chip registers. Note that the limit registers are

8 bits long and the AIN conversion result is 10 bits long. If the

INT

the INT/

pin.

S/W RESET

INTERNAL

TEMP

INTERRUPT

STATUS

REGISTER

(TEMP AND

AIN1 TO AIN4)

EXTERNAL

TEMP

V

DD

WATCHDOG

LIMIT

COMPARISONS

INTERRUPT

INT/INT

(LATCHED OUTPUT)

MASK

REGISTERS

DIODE

FAULT

INTERRUPT

STATUS

REGISTER 2

(V

)

DD

AIN1 TO AIN4

INT/INT

ENABLE BIT

READ RESET

CONTROL

CONFIGURATION

REGISTER 1

Figure 53. ADT7516/ADT7517/ADT7519 Interrupt Structure

Rev. B | Page 24 of 44

ADT7516/ADT7517/ADT7519

Temperature measurement is also initiated after every read or

write to the part when the part is in either single-channel

measurement mode or round robin measurement mode.

FUNCTIONAL DESCRIPTION—MEASUREMENT

Temperature Sensor

The ADT7516/ADT7517/ADT7519 contain an ADC with

special input signal conditioning to enable operation with

external and on-chip diode temperature sensors. When the

ADT7516/ADT7517/ADT7519 operate in single-channel mode,

the ADC continually processes the measurement taken on one

channel only. This channel is preselected by Bits[C0:C2] in the

Control Configuration 2 register (Address 0x19). When in

round robin mode, the analog input multiplexer sequentially

selects the V_DDinput channel, the on-chip temperature sensor

to measure its internal temperature, either the external tempera-

ture sensor or AIN1 and AIN2, AIN3, and then AIN4. These

signals are digitized by the ADC and the results are stored in

the various value registers.

Once serial communication has started, any conversion in

progress stops and the ADC resets. Conversion restarts

immediately after the serial communication has finished. The

temperature measurement proceeds normally as described above.

V_DDMonitoring

The ADT7516/ADT7517/ADT7519 also have the ability to

monitor their own power supply. The part measures the voltage

on its V_DDpin to a resolution of 10 bits. The resulting value is

stored in two 8-bit registers; the two LSBs are stored in register

Address 0x03 and the eight MSBs are stored in register

Address 0x06. This allows the option of doing just a 1-byte read

if 10-bit resolution is not important. The measured result is

compared with the V_HIGHand V_LOWlimits. If the V_DDinterrupt is

not masked, any out-of-limit comparison generates a flag in the

Interrupt Status 2 register and one or more out-of-limit results

The measured results from the temperature sensors are com-

pared with the internal and external T_HIGHand T_LOWlimits.

These temperature limits are stored in on-chip registers. If the

temperature limits are not masked, any out-of-limit comparisons

generate flags that are stored in the Interrupt Status 1 register.

INT

cause the INT/

output to pull either high or low, depending

on the output polarity setting.

INT

One or more out-of-limit results cause the INT/

output to

Measuring the voltage on the V_DDpin is regarded as monitoring

a channel along with the internal, external, and AIN channels.

The user can select the V_DDchannel for single-channel

measurement by setting Bit C4 = 1 and setting Bits[C0:C2] to all

0s in the Control Configuration 2 register.

pull either high or low depending on the output polarity setting.

Theoretically, the temperature measuring circuit can measure

temperatures from −128°C to +127°C with a resolution of

0.25°C. However, temperatures outside T_Aare outside the

guaranteed operating temperature range of the device.

Temperature measurement from −128°C to +127°C is possible

using an external sensor.

When measuring the V_DDvalue, the reference for the ADC is

sourced from the internal reference. Table 8 shows the data

format. As the maximum measurable V_DDvoltage is 7 V,

internal scaling is performed on the V_DDvoltage to match the

2.28 V internal reference value. Following is an example of how

the transfer function works:

Temperature measurement is initiated by three methods. The

first method is applicable when the part is in single-channel

measurement mode. The temperature is measured 16 times and

internally averaged to reduce noise. In single-channel mode, the

part is continuously monitoring the selected channel, that is, as

soon as one measurement is taken another one is started on the

same channel. The total time to measure a temperature channel

with the ADC operating at slow speed is typically 11.4 ms

(712 ꢁs × 16) for the internal temperature sensor and 24.22 ms

(1.51 ms × 16) for the external temperature sensor. The new

temperature value is stored in two 8-bit registers and is ready

for reading by the I²C or SPI interface. The user has the option

of disabling the averaging by setting Bit 5 in the Control

Configuration 2 register (Address 0x19). The ADT7516/

ADT7517/ADT7519 default on power-up is with averaging

enabled.

V

_DD= 5 V

ADC Reference = 2.28 V

1 LSB = ADC Reference/2¹⁰

= 2.28/1024

= 2.226 mV

Scale Factor = Full-Scale V_CC/ADC Reference

= 7/2.28

= 3.07

Conversion Result = V_DD/(Scale Factor × LSB size)

= 5/(3.07 × 2.226 mV)

= 0x2DC

The second method is applicable when the part is in round

robin measurement mode. The part measures both the internal

and external temperature sensors as it cycles through all

possible measurement channels. The two temperature channels

are measured each time the part runs a round robin sequence.

In round robin mode, the part is continuously measuring all

channels.

Rev. B | Page 25 of 44

ADT7516/ADT7517/ADT7519

writing to Bits[C0:C2] in the Control Configuration 2 register.

For example, to select the V_DDchannel for monitoring, write to

the Control Configuration 2 register and set C4 to 1 (if not done

so already), then write all 0s to Bits[C0:C2]. All subsequent

conversions are done on the V_DDchannel only. To change the

channel selection to the internal temperature channel, write to

the Control Configuration 2 register and set C0 = 1. When

measuring in single channel mode, conversions on the channel

selected occur directly after each other. Any communication to

the ADT7516/ADT7517/ADT7519 stops the conversions, but

they are restarted once the read or write operation is completed.

Table 8. V_DDData Format (V_REF= 2.28 V)

Digital Output

V_DDValue (V)

Binary

Hex

18B

1B7

200

249

292

2DC

325

36E

3B7

3FF

2.7

3

3.5

4

4.5

5

5.5

6

01 1000 1011

01 1011 0111

10 0000 0000

10 0100 1001

10 1001 0010

10 1101 1100

11 0010 0101

11 0110 1110

11 1011 0111

11 1111 1111

Temperature Measurement Method

6.5

7

Internal Temperature Measurement

The ADT7516/ADT7517/ADT7519 contain an on-chip band

gap temperature sensor whose output is digitized by the on-chip

ADC. The temperature data is stored in the internal temperature

value register. Because both positive and negative temperatures

can be measured, the temperature data is stored in twos comple-

ment format, as shown in Table 9. The thermal characteristics

of the measurement sensor can change and, therefore, an offset

is added to the measured value to enable the transfer function

to match the thermal characteristics. This offset is added before

the temperature data is stored. The offset value used is stored in

the internal temperature offset register.

On-Chip Reference

The ADT7516/ADT7517/ADT7519 have an on-chip 1.2 V band

gap reference that is gained up by a switched capacitor amplifier

to give an output of 2.28 V. The amplifier is powered up for the

duration of the device monitoring phase and is powered down

once monitoring is disabled. This saves on current consumption.

The internal reference is used as the reference for the ADC. The

ADC is used for measuring V_DD, internal temperature sensor,

external temperature sensor, and AIN inputs. The internal

reference is always used when measuring V_DD, and the internal

and external temperature sensors. The external reference is the

default power-up reference for the DACs.

External Temperature Measurement

The ADT7516/ADT7517/ADT7519 can measure the temperature

of one external diode sensor or diode-connected transistor.

Round Robin Measurement

On power-up, the ADT7516/ADT7517/ADT7519 go into round

robin mode, but monitoring is disabled. Setting Bit C0 of the

Control Configuration 1 register to 1 enables conversions. It

sequences through all the available channels, taking a

measurement from each in the following order: V_DD, internal

temperature sensor, external temperature sensor (AIN1 and

AIN2), AIN3, and AIN4. Pin 7 and Pin 8 can be configured to

be either external temperature sensor pins or standalone analog

input pins. Once conversion is completed on the AIN4 channel,

the device loops around for another measurement cycle. This

method of taking a measurement on all the channels in one

cycle is called round robin. Setting Bit C4 of Control

The forward voltage of a diode or diode connected transistor,

operated at a constant current, exhibits a negative temperature

coefficient of about −2 mV/°C. Unfortunately, because the

absolute value of V_BEvaries from device to device, and

individual calibration is required to null this out, the technique

is unsuitable for mass production.

The technique used in the ADT7516/ADT7517/ADT7519 is to

measure the change in V_BEwhen the device is operated at two

different currents. This is given by

ΔV_BE= kT/q × ln(N)

where:

Configuration 2 (Address 0x19) disables the round robin mode

and in turn sets up the single-channel mode. In single-channel

mode, only one channel (for example, the internal temperature

sensor) is measured in each conversion cycle.

k is Boltzmann’s constant.

q is the charge on the carrier.

T is the absolute temperature in kelvins.

N is the ratio of the two currents.

The time taken to monitor all channels is normally not of

interest, because the most recently measured value can be read

at any time. For applications where the round robin time is

important, typical times at 25°C are given in the Specifications

section.

Figure 45 shows the input signal conditioning used to measure

the output of an external temperature sensor. This figure shows

the external sensor as a substrate transistor, provided for

temperature monitoring on some microprocessors, but it can

equally well be a discrete transistor.

Single Channel Measurement

If a discrete transistor is used, the collector is not grounded, and

should be linked to the base. If a PNP transistor is used, the

base is connected to the D− input and the emitter to the D+

Setting C4 of the Control Configuration 2 register enables the

single channel mode and allows the ADT7516/ADT7517/

ADT7519 to focus on one channel only. A channel is selected by

Rev. B | Page 26 of 44

ADT7516/ADT7517/ADT7519

input. If an NPN transistor is used, the emitter is connected to

the D− input and the base to the D+ input.

•

Try to minimize the number of copper/solder joints

because they can cause thermocouple effects. Where

copper/solder joints are used, make sure that they are in

both the D+ and D− path and are at the same temperature.

A 2N3906 is recommended as the external transistor.

To prevent ground noise from interfering with the

Thermocouple effects should not be a major problem

because 1°C corresponds to about 240 ꢁV, and

thermocouple voltages are about 3 ꢁV/°C of temperature

difference. Unless there are two thermocouples with a big

temperature differential between them, thermocouple

voltages should be much less than 200 mV.

measurement, the more negative terminal of the sensor is not

referenced to ground, but is biased above ground by an internal

diode at the D− input. As the sensor is operating in a noisy

environment, C1 is provided as a noise filter. See the Layout

Considerations section for more information on C1.

To measure ꢂV_BE, the sensor is switched between operating

currents of I and N × I. The resulting waveform is passed

through a low-pass filter to remove noise, then to a chopper

stabilized amplifier that performs the functions of amplification

and rectification of the waveform to produce a dc voltage

proportional to ꢂV_BE. This voltage is measured by the ADC to

give a temperature output in 10-bit twos complement format.

To further reduce the effects of noise, digital filtering is

performed by averaging the results of 16 measurement cycles.

•

Place 0.1 ꢁF bypass and 2200 pF input filter capacitors

close to the ADT7516/ADT7517/ADT7519.

If the distance to the remote sensor is more than 8 inches,

the use of twisted-pair cable is recommended. This works

up to about 6 feet to 12 feet.

•

For long distances (up to 100 feet), use shielded twisted-

pair cable, such as Belden® #8451 microphone cable. Connect

the twisted pair to D+ and D− and the shield to GND, close

to the ADT7516/ADT7517/ADT7519. Leave the remote

end of the shield unconnected to avoid ground loops.

Layout Considerations

Digital boards can be electrically noisy environments and care

must be taken to protect the analog inputs from noise, particu-

larly when measuring the very small voltages from a remote

diode sensor. The following precautions should be taken:

Because the measurement technique uses switched current

sources, excessive cable and/or filter capacitance can affect the

measurement. When using long cables, the filter capacitor can

be reduced or removed.

•

Place the ADT7516/ADT7517/ADT7519 as close as

possible to the remote sensing diode. Provided that the

worst noise sources such as clock generators, data/address

buses, and CRTs are avoided, this distance can be 4 inches

to 8 inches.

Cable resistance can also introduce errors. Series resistance of

1 Ω introduces about 0.5°C error.

Temperature Value Format

One LSB of the ADC corresponds to 0.25°C. The ADC can

theoretically measure a temperature span of 255°C. The internal

temperature sensor is guaranteed to a low value limit of −40°C.

It is possible to measure the full temperature span using the

external temperature sensor. The temperature data format is

shown in Table 9.

•

Route the D+ and D− tracks close together, in parallel,

with grounded guard tracks on each side. Provide a ground

plane under the tracks, if possible.

Use wide tracks to minimize inductance and reduce noise

pickup. A 10 mil track minimum width and spacing is

recommended.

The result of the internal or external temperature measurements

is stored in the temperature value registers, and is compared

with limits programmed into the internal or external high and

low registers.

GND

10MIL

D+

D–

10MIL

GND

10MIL

Figure 54. Arrangement of Signal Tracks

Rev. B | Page 27 of 44

ADT7516/ADT7517/ADT7519

conversion results of measurements taken on the temperature,

_DD, and AIN channels. For example, the eight MSBs of the V_DD

Table 9. Temperature Data Format

(Internal and External Temperature)

V

measurement are stored in Register Address 0x06 and the two

LSBs are stored in Register Address 0x03. These types of

registers are linked so that when the LSB register is read first,

the MSB registers associated with that LSB register are locked to

prevent any updates. To unlock these MSB registers, the user only

has to read any one of them; this has the effect of unlocking all

previously locked MSB registers. Therefore, for the preceding

example, if Register 0x03 is read first, MSB Register 0x06 and

Register 0x07 would be locked to prevent any updates to them.

If Register 0x06 is read, this register and Register 0x07 would be

subsequently unlocked.

Temperature

Digital Output

11 0110 0000

11 1001 1100

11 1101 1000

11 1111 1111

00 0000 0000

00 0000 0001

00 0010 1000

00 0110 0100

00 1100 1000

01 0010 1100

01 1001 0000

01 1010 0100

01 1111 0100

–40°C

–25°C

–10°C

–0.25°C

0°C

+0.25°C

+10°C

+25°C

+50°C

+75°C

FIRST READ

COMMAND

LSB

REGISTER

OUTPUT

DATA

+100°C

+105°C

+125°C

LOCK ASSOCIATED

MSB REGISTERS

Temperature conversion formula:

Figure 55. Phase 1 of 10-Bit Read

Positive Temperature = ADC Code/4

Negative Temperature = (ADC Code – 512)/4

where DB9 is removed from the ADC Code in the Negative

Temperature equation.

SECOND READ

COMMAND

MSB

REGISTER

OUTPUT

DATA

Interrupts

UNLOCK ASSOCIATED

MSB REGISTERS

The measured results from the internal temperature sensor,

external temperature sensor, V_DDpin, and AIN inputs are

compared with the T_HIGH/V_HIGH(greater than comparison) and

T_LOW/V_LOW(less than or equal to comparison) limits. An

interrupt occurs if the measurement exceeds or equals the limit

registers. These limits are stored in on-chip registers. Note that

the limit registers are 8 bits long and the conversion results are

10 bits long. If the limits are not masked, any out-of-limit

comparisons generate flags that are stored in the Interrupt

Status 1 register (Address 0x00) and Interrupt Status 2 register

(Address 0x01). One or more out-of-limit results cause the

Figure 56. Phase 2 of 10-Bit Read

If an MSB register is read first, its corresponding LSB register is

not locked, leaving the user with the option of just reading back

8 bits (MSB) of a 10-bit conversion result. Reading an MSB

register first does not lock other MSB registers, and likewise,

reading an LSB register first does not lock other LSB registers.

Table 10. ADT7516/ADT7517/ADT7519 Registers

R/W

Power-On

Default

Address Name

INT

INT/

output to pull either high or low depending on the

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C to

0x0F

0x10

0x11

0x12

0x13

Interrupt Status 1

Interrupt Status 2

Reserved

Internal Temp and V_DDLSBs

External Temp and AIN1 to AIN4 LSBs

Reserved

0x00

output polarity setting. It is good design practice to mask out

interrupts for channels that are of no concern to the application.

0x00

No default value

0x00

Figure 53 shows the interrupt structure for the ADT7516/

ADT7517/ADT7519. It gives a block diagram representation of

how the various measurement channels affect the INT/

INT

pin.

V_DDMSBs

ADT7516/ADT7517/ADT7519 REGISTERS

Internal Temp MSBs

External Temp MSBs/AIN1 MSBs

AIN2 MSBs

AIN3 MSBs

AIN4 MSBs

The ADT7516/ADT7517/ADT7519 contain registers that are

used to store the results of external and internal temperature

measurements, V_DDvalue measurements, analog input measure-

ments, high and low temperature limits, supply voltage and

analog input limits, set output DAC voltage levels, configure

multipurpose pins, and generally to control the device. A

description of these registers follows.

Reserved

0x00

DAC A LSBs (ADT7516/ADT7517 Only)

DAC A MSBs

DAC B LSBs (ADT7516/ADT7517 Only)

DAC B MSBs

0x00

The register map is divided into registers of 8 bits. Each register

has its own individual address, but some consist of data that is

linked with other registers. These registers hold the 10-bit

Rev. B | Page 28 of 44

ADT7516/ADT7517/ADT7519

Table 11.

Bit Function

R/W

Power-On

Default

Address Name

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

DAC C LSBs (ADT7516/ADT7517 only)

DAC C MSBs

DAC D LSBs (ADT7516/ADT7517 only)

DAC D MSBs

Control Configuration 1

Control Configuration 2

Control Configuration 3

DAC Configuration

LDAC Configuration

Interrupt Mask 1

0x00

0xD8

0xC7

0x62

0x64

0xC9

0xFF

0x00

D0 1 when the internal temperature value exceeds T_HIGHlimit.

Any internal temperature reading greater than the set limit

causes an out-of-limit event.

D1 1 when internal temperature value exceeds T_LOWlimit. Any

internal temperature reading less than or equal to the set

limit causes an out-of-limit event.

D2 This status bit is linked to the configuration of Pin 7 and

Pin 8. If configured for external temperature sensor, this bit

is 1 when the external temperature value exceeds T_HIGH

limit. The default value for this limit register is –1°C, so any

external temperature reading greater than the set limit

causes an out-of-limit event. If configured for AIN1 and

AIN2, this bit is 1 when AIN1 input voltage exceeds V_HIGHor

Interrupt Mask 2

Internal Temp Offset

External Temp Offset

Internal Analog Temp Offset

External Analog Temp Offset

V_DDV_HIGHLimit

V_DDV_LOWLimit

Internal T_HIGHLimit

Internal T_LOWLimit

V_LOWlimits.

D3 1 when external temperature value exceeds T_LOWlimit. The

default value for this limit register is 0°C, so any external

temperature reading less than or equal to the set limit

causes an out-of-limit event.

D4 1 indicates a fault (open or short) for the external

temperature sensor.

D5 1 when AIN2 voltage is greater than its corresponding V_HIGH

limit. 1 when AIN2 voltage is less than or equal to its

corresponding V_LOWlimit.

D6 1 when AIN3 voltage is greater than its corresponding V_HIGH

limit. 1 when AIN3 voltage is less than or equal to its

corresponding V_LOWlimit.

External T_HIGH/AIN1 V_HIGHLimits

External T_LOW/AIN1 V_LOWLimits

Reserved

0x29 to

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31 to

0x4C

0x4D

0x4E

0x4F

AIN2 V_HIGHLimit

AIN2 V_LOWLimit

AIN3 V_HIGHLimit

AIN3 V_LOWLimit

AIN4 V_HIGHLimit

AIN4 V_LOWLimit

Reserved

0xFF

0x 00

0xFF

0x00

0xFF

0x00

D7 1 when AIN4 voltage is greater than its corresponding V_HIGH

limit. 1 when AIN4 voltage is less than or equal to its

corresponding V_LOWlimit.

Interrupt Status 2 Register (Read-Only) [Address = 0x01]

This 8-bit read-only register reflects the status of the V_DD

INT

interrupt that can cause the INT/

pin to go active. This

register is reset by a read operation, provided that any out-of-

limit event has been corrected. It is also reset by a software reset.

Device ID

Manufacturer’s ID

Silicon Revision

0x03/0x0B/0x07

0x41

Check register

for current

D7

D6

D5

D4

0¹

D3

D2

D1

D0

N/A

¹Default settings at power-up.

silicon revision

0x50 to

0x7E

0x7F

0x80 to

0xFF

Reserved

0x00

Table 12.

Bit Function

SPI Lock Status

Reserved

0x00

D4 1 when V_DDvalue is greater than its corresponding V_HIGH

limit. 1 when V_DDis less than or equal to its corresponding

V

_LOWlimit.

Interrupt Status 1 Register (Read-Only) [Address 0x00]

Internal Temperature Value/V_DDValue Register LSBs

(Read-Only) [Address = 0x03]

This 8-bit read-only register reflects the status of some of the

INT

interrupts that can cause the INT/

pin to go active. This

This 8-bit read-only register stores the two LSBs of the 10-bit

temperature reading from the internal temperature sensor and

the two LSBs of the 10-bit supply voltage reading.

register is reset by a read operation, provided that any out-of-

limit event has been corrected. It is also reset by a software reset.

D7

D6

D5

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

D7

D6

D5

D4

D3

V1

0¹

D2

LSB

0¹

D1

T1

0¹

D0

LSB

0¹

N/A

¹Default settings at power-up.

N/A

¹Default settings at power-up.

Rev. B | Page 29 of 44

ADT7516/ADT7517/ADT7519

Table 13.

temperature value is stored in twos complement format. The

eight MSBs of the 10-bit value are stored in this register.

Bit

D0

D1

D2

D3

Function

LSB of internal temperature value.

Bit 1 of internal temperature value.

LSB of V_DDvalue.

D7

T/A9

0¹

D6

T/A8

0¹

D5

T/A7

0¹

D4

T/A6

0¹

D3

T/A5

0¹

D2

T/A4

0¹

D1

T/A3

0¹

D0

T/A2

0¹

Bit 1 of V_DDvalue.

¹Default settings at power-up.

External Temperature Value and Analog Input 1 to

Analog Input 4 Register LSBs (Read-Only) [Address = 0x04]

AIN2 Register MSBs (Read) [Address = 0x09]

This 8-bit read register contains the eight MSBs of the AIN2

analog input voltage word. The value in this register is combined

with Bits[D2:D3] of the external temperature value and Analog

Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the

full 10-bit conversion result of the analog value on the AIN2 pin.

This is an 8-bit, read-only register. Bits[D2:D7] store the two

LSBs of the analog inputs AIN2 to AIN4. Bits[D0:D1] store the

two LSBs of either the external temperature value or AIN1 input

value. The type of input for D0 and D1 is selected by Bits[C1:C2]

of the Control Configuration Register 1.

D7

MSB

0¹

D6

A8

0¹

D5

A7

0¹

D4

A6

0¹

D3

A5

0¹

D2

A4

0¹

D1

A3

0¹

D0

A2

0¹

D7

A4

0¹

D6

D5

A3

0¹

D4

A3_LSB

0¹

D3

A2

0¹

D2

A2_LSB

0¹

D1

T/A

0¹

D0

A4_LSB

0¹

T/A_LSB

0¹

¹Default settings at power-up.

AIN3 Register MSBs (Read) [Address = 0x0A]

Table 14.

This 8-bit read register contains the eight MSBs of the AIN3

analog input voltage word. The value in this register is combined

with Bits[D4:D5] of the external temperature value and Analog

Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the

full 10-bit conversion result of the analog value on the AIN3 pin.

Bit

D0

D1

D2

D3

D4

D5

D6

D7

Function

LSB of external temperature value or AIN1 value.

Bit 1 of external temperature value or AIN1 value.

LSB of AIN2 value.

Bit 1 of AIN2 value.

LSB of AIN3 value.

Bit 1 of AIN3 value.

LSB of AIN4 value.

Bit 1 of AIN4 value.

D7

MSB

0¹

D6

A8

0¹

D5

A7

0¹

D4

A6

0¹

D3

A5

0¹

D2

A4

0¹

D1

A3

0¹

D0

A2

0¹

¹Default settings at power-up.

AIN4 Register MSBs (Read) [Address = 0x0B]

V_DDValue Register MSBs (Read-Only) [Address = 0x06]

This 8-bit read register contains the eight MSBs of the AIN4

analog input voltage word. The value in this register is combined

with Bits[D6:D7] of the external temperature value and Analog

Input 1 to Analog Input 4 register LSBs, Address 0x04, to give the

full 10-bit conversion result of the analog value on the AIN4 pin.

This 8-bit read-only register stores the supply voltage value. The

eight MSBs of the 10-bit value are stored in this register.

D7

V9

x¹

D6

V8

x¹

D5

V7

x¹

D4

V6

x¹

D3

V5

x¹

D2

V4

x¹

D1

V3

x¹

D0

V2

x¹

D7

MSB

0¹

D6

A8

0¹

D5

A7

0¹

D4

A6

0¹

D3

A5

0¹

D2

A4

0¹

D1

A3

0¹

D0

A2

0¹

¹Loaded with V_DDvalue after power-up.

Internal Temperature Value Register MSBs (Read-Only)

[Address = 0x07]

¹Default settings at power-up.

This 8-bit read-only register stores the internal temperature value

from the internal temperature sensor in twos complement format.

The eight MSBs of the 10-bit value are stored in this register.

DAC A Register LSBs (Read/Write) [Address = 0x10]

This 8-bit read/write register contains the 4/2 LSBs of the

ADT7516/ADT7517 DAC A word, respectively. The value in

this register is combined with the value in the DAC A register

MSBs and converted to an analog voltage on the V_OUT-A pin.

On power-up, the voltage output on the V_OUT-A pin is 0 V.

D7

T9

0¹

D6

T8

0¹

D5

T7

0¹

D4

T6

0¹

D3

T5

0¹

D2

T4

0¹

D1

T3

0¹

D0

T2

0¹

¹Default settings at power-up.

ADT7516

External Temperature Value or Analog Input AIN1

Register MSBs (Read-Only) [Address = 0x08]

D7

B3

0¹

D6

B2

0¹

D5

B1

0¹

D4

LSB

0¹

D3

D2

D1

D0

N/A

This 8-bit read-only register stores, if selected, the external

temperature value or the analog input AIN1 value. Selection is

done in the Control Configuration 1 register. The external

¹Default settings at power-up.

Rev. B | Page 30 of 44

ADT7516/ADT7517/ADT7519

ADT7517

ADT7516

D7

B1

0¹

D6

LSB

0¹

D5

D4

D3

D2

D1

D0

D7

B3

0¹

D6

B2

0¹

D5

B1

0¹

D4

LSB

0¹

D3

D2

D1

D0

N/A

¹Default settings at power-up.

DAC A Register MSBs (Read/Write) [Address = 0x11]

ADT7517

This 8-bit read/write register contains the eight MSBs of the

DAC A word. The value in this register is combined with the

value in the DAC A register LSBs and converted to an analog

voltage on the V_OUT-A pin. On power-up, the voltage output on

the V_OUT-A pin is 0 V.

D7

B1

0¹

D6

LSB

0¹

D5

D4

D3

D2

D1

D0

N/A

¹Default settings at power-up.

DAC C Register MSBs (Read/Write) [Address = 0x15]

D7

MSB

0¹

D6

B8

0¹

D5

B7

0¹

D4

B6

0¹

D3

B5

0¹

D2

B4

0¹

D1

B3

0¹

D0

B2

0¹

This 8-bit read/write register contains the eight MSBs of the

DAC C word. The value in this register is combined with the

value in the DAC C register LSBs and converted to an analog

voltage on the V_OUT-C pin. On power-up, the voltage output on

the V_OUT-C pin is 0 V.

¹Default settings at power-up.

DAC B Register LSBs (Read/Write) [Address = 0x12]

This 8-bit read/write register contains the 4/2 LSBs of the

D7

MSB B8

0¹0¹

D6

D5

B7

0¹

D4

B6

0¹

D3

B5

0¹

D2

B4

0¹

D1

B3

0¹

D0

B2

0¹

ADT7516/ADT7517 DAC B word, respectively. The value in

this register is combined with the value in the DAC B register

MSBs and converted to an analog voltage on the V_OUT-B pin. On

power-up, the voltage output on the V_OUT-B pin is 0 V.

¹Default settings at power-up.

DAC D Register LSBs (Read/Write) [Address = 0x16]

ADT7516

This 8-bit read/write register contains the 4/2 LSBs of the

D7

B3

0¹

D6

B2

0¹

D5

B1

0¹

D4

LSB

0¹

D3

D2

D1

D0

ADT7516/ADT7517 DAC D word, respectively. The value in

this register is combined with the value in the DAC D register

MSBs and converted to an analog voltage on the V_OUT-D pin.

On power-up, the voltage output on the V_OUT-D pin is 0 V.

N/A

¹Default settings at power-up.

ADT7517

ADT7516

D7

B1

0¹

D6

LSB

0¹

D5

D4

D3

D2

D1

D0

D7

B3

0¹

D6

B2

0¹

D5

B1

0¹

D4

LSB

0¹

D3

D2

D1

D0

N/A

¹Default settings at power-up.

DAC B Register MSBs (Read/Write) [Address = 0x13]

ADT7517

This 8-bit read/write register contains the eight MSBs of the

DAC B word. The value in this register is combine with the

value in the DAC B register LSBs and converts to an analog

voltage on the V_OUT-B pin. On power-up, the voltage output on

the V_OUT-B pin is 0 V.

D7

B1

0¹

D6

LSB

0¹

D5

D4

D3

D2

D1

D0

N/A

¹Default settings at power-up.

DAC D Register MSBs (Read/Write) [Address = 0x17]

D7

MSB

0¹

D6

B8

0¹

D5

B7

0¹

D4

B6

0¹

D3

B5

0¹

D2

B4

0¹

D1

B3

0¹

D0

B2

0¹

This 8-bit read/write register contains the eight MSBs of the

DAC D word. The value in this register combines with the value

in the DAC D register LSBs and converts to an analog voltage

on the V_OUT-D pin. On power-up, the voltage output on the

¹Default settings at power-up.

V_OUT-D pin is 0 V.

DAC C Register LSBs (Read/Write) [Address = 0x14]

This 8-bit read/write register contains the 4/2 LSBs of the

D7

MSB

0¹

D6

B8

0¹

D5

B7

0¹

D4

B6

0¹

D3

B5

0¹

D2

B4

0¹

D1

B3

0¹

D0

B2

0¹

ADT7516/ADT7517 DAC C word, respectively. The value in

this register is combined with the value in the DAC C register

MSBs and converted to an analog voltage on the V_OUT-C pin.

On power-up, the voltage output on the V_OUT-C pin is 0 V.

¹Default settings at power-up.

Rev. B | Page 31 of 44

ADT7516/ADT7517/ADT7519

Control Configuration 1 Register (Read/Write)

[Address = 0x18]

Table 17.

Bit

Function

[C0:C2] In single-channel mode, these bits select between V_DD,

the internal temperature sensor, external temperature

sensor/AIN1, AIN2, AIN3, and AIN4 for conversion. The

default is V_DD.

This configuration register is an 8-bit read/write register that is

used to set up some of the operating modes of the ADT7516/

ADT7517/ADT7519.

000 = V_DD.

Table 15. Control Configuration 1

001 = internal temperature sensor.

010 = external temperature sensor/AIN1.

(Bits[C1:C2] of the Control Configuration 1 register

affect this selection).

D7

PD

0¹

D6

C6

0¹

D5

C5

0¹

D4

C4

0¹

D3

C3

0¹

D2

C2

0¹

D1

C1

0¹

D0

C0

0¹

¹Default settings at power-up.

011 = AIN2.

100 = AIN3.

101 = AIN4.

110 to 111 = reserved.

Table 16.

Bit

Function

C0

This bit enables/disables conversions in round robin

and single-channel mode.

ADT7516/ADT7517/ADT7519 powers up in round

robin mode but monitoring is not initiated until this bit

is set. The default = 0.

0 = stop monitoring.

1 = start monitoring.

C3

C4

Reserved.

Selects between single-channel and round robin

conversion cycle. The default is round robin.

0 = round robin.

1 = single channel.

C5

Default condition is to average every measurement on

all channels 16 times. This bit disables this averaging.

Channels affected are temperature, analog inputs, and

V_DD.

0 = enable averaging.

1 = disable averaging.

SMBus timeout on the serial clock puts a 25 ms limit

on the pulse width of the clock, ensuring that a fault

on the master SCL does not lock up the SDA line.

0 = disable SMBus timeout.

[C1:C2] Selects between the two different analog inputs on

Pin 7 and Pin 8. ADT7516/ADT7517/ADT7519 powers

up with AIN1 and AIN2 selected.

00 = AIN1 and AIN2 selected.

01 = undefined.

10 = external TDM selected.

11 = undefined.

Selects between digital (LDAC) and analog inputs

(AIN3) on Pin 9. When AIN3 is selected, Bit C3 of the

Control Configuration 3 register is masked and has no

effect until LDAC is selected as the input on Pin 9.

0 = LDAC selected.

C6

C7

C3

1 = enable SMBus timeout.

Software Reset. Setting this bit to 1 causes a software

reset. All registers and DAC outputs reset to their

default settings.

1 = AIN3 selected.

C4

C5

Reserved. Write 0 only.

0 = enable INT/INT output.

1 = disable INT/INT output.

Control Configuration 3 Register (Read/Write)

[Address = 0x1A]

This configuration register is an 8-bit read/write register that is

used to set up some of the operating modes of the ADT7516/

ADT7517/ADT7519.

C6

PD

Configures INT/INT output polarity.

0 = active low.

1 = active high.

Power-Down Bit. Setting this bit to 1 puts the

ADT7516/ADT7517/ADT7519 into standby mode. In

this mode, both ADC and DACs are fully powered

down, but the serial interface is still operational. To

power up the part again, just write 0 to this bit.

D7

C7

0¹

D6

C6

0¹

D5

C5

0¹

D4

C4

0¹

D3

C3

0¹

D2

C2

0¹

D1

C1

0¹

D0

C0

0¹

¹Default settings at power-up.

Control Configuration 2 Register (Read/Write)

[Address = 0x19]

This configuration register is an 8-bit read/write register that is

used to set up some of the operating modes of the ADT7516/

ADT7517/ADT7519.

D7

C7

0¹

D6

C6

0¹

D5

C5

0¹

D4

C4

0¹

D3

C3

0¹

D2

C2

0¹

D1

C1

0¹

D0

C0

0¹

¹Default settings at power-up.

Rev. B | Page 32 of 44

ADT7516/ADT7517/ADT7519

Table 18.

Bit

Function

Bit Function

[D4:D5] 00 = MSB write to any DAC register generates LDAC

command that updates that DAC only.

C0 Selects between fast and slow ADC conversion speeds.

0 = ADC clock at 1.4 kHz.

01 = MSB write to DAC B or DAC D register generates

LDAC command that updates DAC A and DAC B or

DAC C and DAC D, respectively.

10 = MSB write to DAC D register generates LDAC

command that updates all four DACs.

1 = ADC clock at 22.5 kHz. D+ and D– analog filters are

disabled.

C1 On the ADT7516 and ADT7517, this bit selects between

8-bit and 10-bit DAC output resolution on the thermal

voltage output feature. The default is 8 bits. This bit has no

effect on the ADT7519 output because this part has only

an 8-bit DAC. For the ADT7519, write 0 to this bit.

0 = 8-bit resolution.

11 = LDAC command generated from LDAC register.

[D6:D7] Reserved. Write 0s only.

LDAC Configuration Register (Write-Only)[Address = 0x1C]

1 = 10-bit resolution.

This configuration register is an 8-bit write register that is used

C2 Reserved. Write 0 only.

C3 0 = LDAC pin controls updating of DAC outputs.

1 = DAC configuration register and LDAC configuration

register control updating of DAC outputs.

C4 Selects the ADC reference to be either internal V_REFor V_DD

to control the updating of the quad DAC outputs if the

LDAC

pin is disabled and Bits[D4:D5] of the DAC configuration

register are both set to 1. Also selects either the internal or the

external V_REFfor all four DACs. Bits[D0:D3] in this register are

self-clearing, that is, reading back from this register always gives

0s for these bits.

for analog inputs.

0 = internal V_REF.

1 = V_DD.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

C5 Setting this bit selects DAC A voltage output to be

proportional to the internal temperature measurement.

C6 Setting this bit selects DAC B voltage output to be

proportional to the external temperature measurement.

¹Default settings at power-up.

Table 20.

C7 Reserved. Write 0 only.

Bit

Function

DAC Configuration Register (Read/Write) [Address = 0x1B]

D0

Writing a 1 to this bit generates the LDAC command

to update DAC A output only.

Writing a 1 to this bit generates the LDAC command

to update DAC B output only.

Writing a 1 to this bit generates the LDAC command

to update DAC C output only.

Writing a 1 to this bit generates the LDAC command

to update DAC D output only.

Selects either internal V_REFor external V_REFfor DAC A

and DAC B.

0 = external V_REF

1 = internal V_REF

This configuration register is an 8-bit read/write register that is

used to control the output ranges of all four DACs and also to

D1

D2

D3

D4

LDAC

control the loading of the DAC registers if the

pin is

disabled (Bit C3 = 1, Control Configuration 3 register).

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

¹Default settings at power-up.

.

Table 19.

Bit

Function

Selects the output range of DAC A.

0 = 0 V to V_REF

1 = 0 V to 2 V_REF

Selects the output range of DAC B.

0 = 0 V to V_REF

1 = 0 V to 2 V_REF

Selects the output range of DAC C.

0 = 0 V to V_REF

1 = 0 V to 2 V_REF

Selects the output range of DAC D.

0 = 0 V to V_REF

1 = 0 V to 2 V_REF

D5

Selects either internal V_REFor external V_REFfor DAC C

and DAC D.

D0

0 = external V_REF

1 = internal V_REF

.

[D6:D7] Reserved. Write 0s only.

D1

D2

D3

.

Interrupt Mask 1 Register (Read/Write) [Address = 0x1D]

.

This mask register is an 8-bit read/write register that can be

used to mask any interrupts that can cause the INT/

go active.

INT

.

pin to

.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

D0

0¹

.

D1

0¹

.

¹Default settings at power-up.

Rev. B | Page 33 of 44

ADT7516/ADT7517/ADT7519

External Temperature Offset Register (Read/Write)

[Address = 0x20]

Table 21.

Bit Function

This register contains the offset value for the external temperature

channel. A twos complement number can be written to this

register and is then added to the measured result before it is

stored or compared to limits. In this way, a one-point calibration

can be done, whereby the whole transfer function of the channel

can be moved up or down. From a software point of view, this

can be a very simple method to vary the characteristics of the

measurement channel if the thermal characteristics change.

Because it is an 8-bit register, the temperature resolution is 1°C.

D0 0 = enable internal T_HIGHinterrupt.

1 = disable internal T_HIGHinterrupt.

D1 0 = enable internal T_LOWinterrupt.

1 = disable internal T_LOWinterrupt.

D2 0 = enable external T_HIGHinterrupt or AIN1 interrupt.

1 = disable external T_HIGHinterrupt or AIN1 interrupt.

D3 0 = enable external T_LOWinterrupt.

1 = disable external T_LOWinterrupt.

D4 0 = enable external temperature fault interrupt.

1 = disable external temperature fault interrupt.

D5 0 = enable AIN2 interrupt.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

1 = disable AIN2 interrupt.

D6 0 = enable AIN3 interrupt.

¹Default settings at power-up.

1 = disable AIN3 interrupt.

D7 0 = enable AIN4 interrupt.

Internal Analog Temperature Offset Register

(Read/Write) [Address = 0x21]

1 = disable AIN4 interrupt.

Interrupt Mask 2 Register (Read/Write) [Address = 0x1E]

This register contains the offset value for the internal thermal

voltage output. A twos complement number can be written to

this register and then added to the measured result before it is

converted by DAC A. Varying the value in this register has the

effect of varying the temperature span. For example, the output

voltage can represent a temperature span of −128°C to +127°C

or even 0°C to +127°C. In essence, this register changes the

position of 0 V on the temperature scale. Temperatures other

than −128°C to +127°C produce an upper deadband on the

DAC A output. Because it is an 8-bit register, the temperature

resolution is 1°C. The default value is −40°C.

This mask register is an 8-bit read/write register that can be

used to mask any interrupts that can cause the INT/

pin to

INT

go active.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

D0

0¹

D1

0¹

¹Default settings at power-up.

Table 22.

Bit

Function

[D0:D3]

D4

Reserved. Write 0s only.

0 = enable V_DDinterrupts.

1 = disable V_DDinterrupts.

D7

1¹

D6

1¹

D5

0¹

D4

1¹

D3

1¹

D2

0¹

D1

0¹

D0

0¹

[D5:D7]

Reserved. Write 0s only.

¹Default settings at power-up.

Internal Temperature Offset Register (Read/Write)

[Address = 0x1F]

External Analog Temperature Offset Register

(Read/Write) [Address = 0x22]

This register contains the offset value for the internal temperature

channel. A twos complement number can be written to this

register and then added to the measured result before it is stored

or compared to limits. In this way, a one-point calibration can

be done, whereby the whole transfer function of the channel

can be moved up or down. From a software point of view, this

can be a very simple method to vary the characteristics of the

measurement channel if the thermal characteristics change.

Because it is an 8-bit register, the temperature resolution is 1°C.

This register contains the offset value for the external thermal

voltage output. A twos complement number can be written to

this register and then added to the measured result before it is

converted by DAC B. Varying the value in this register has the

effect of varying the temperature span. For example, the output

voltage can represent a temperature span of −128°C to +127°C

or even 0°C to +127°C. In essence, this register changes the

position of 0 V on the temperature scale. Temperatures other

than −128°C to +127°C produce an upper deadband on the

DAC B output. Because it is an 8-bit register, the temperature

resolution is 1°C. The default value is −40°C.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

D7

1¹

D6

1¹

D5

0¹

D4

1¹

D3

1¹

D2

0¹

D1

0¹

D0

0¹

¹Default settings at power-up.

Rev. B | Page 34 of 44

ADT7516/ADT7517/ADT7519

V_DDV_HIGHLimit Register (Read/Write) [Address = 0x23]

External T_HIGH/AIN1 V_HIGHLimit Register (Read/Write)

[Address = 0x27]

This limit register is an 8-bit read/write register that stores the

If Pin 7 and Pin 8 are configured for the external temperature

sensor, this limit register is an 8-bit read/write register that

stores the twos complement of the external temperature upper

V

INT/

_DDupper limit, and causes an interrupt and activates the

INT

output (if enabled). For this to happen, the measured

V_DDvalue has to be greater than the value in this register. The

INT

limit, and causes an interrupt and activates the INT/

output

default value is 5.46 V.

(if enabled). For this to happen, the measured external

temperature value has to be greater than the value in this

register. Because it is an 8-bit register, the temperature

resolution is 1°C. The default value is −1°C.

D7

1¹

D6

1¹

D5

0¹

D4

0¹

D3

0¹

D2

1¹

D1

1¹

D0

1¹

¹Default settings at power-up.

Positive Temperature = Limit Register Code (d)

V_DDV_LOWLimit Register (Read/Write) [Address = 0x24]

Negative Temperature = Limit Register Code (d) − 256

This limit register is an 8-bit read/write register that stores the

If Pin 7 and Pin 8 are configured for AIN1 and AIN2 inputs,

this limit register is an 8-bit read/write register that stores the

AIN1 input upper limit, and causes an interrupt and activates

V_DDlower limit, and causes an interrupt and activates the

INT

INT/

output (if enabled). For this to happen, the measured

V_DDvalue has to be less than or equal to the value in this

register. The default value is 2.7 V.

INT

the INT/

output (if enabled). For this to happen, the

measured AIN1 value has to be greater than the value in this

register. Because it is an 8-bit register, the resolution is four

times less than the resolution of the 10-bit ADC. Because the

power-up default settings for Pin 7 and Pin 8 are AIN1 and

AIN2 inputs, the default value for this limit register is full-scale

voltage.

D7

0¹

D6

1¹

D5

1¹

D4

0¹

D3

0¹

D2

0¹

D1

1¹

D0

0¹

¹Default settings at power-up.

Internal T_HIGHLimit Register (Read/Write) [Address = 0x25]

D7

1¹

D6

1¹

D5

1¹

D4

1¹

D3

1¹

D2

1¹

D1

1¹

D0

1¹

This limit register is an 8-bit read/write register that stores the twos

complement of the internal temperature upper limit, and causes

INT

an interrupt and activates the INT/

output (if enabled). For this

¹Default settings at power-up.

to happen, the measured internal temperature value has to be

greater than the value in this register. Because it is an 8-bit register,

the temperature resolution is 1°C. The default value is +100°C.

External T_LOW/AIN1 V_LOWLimit Register (Read/Write)

[Address = 0x28]

Positive Temperature = Limit Register Code (d)

If Pin 7 and Pin 8 are configured for the external temperature

sensor, this limit register is an 8-bit read/write register that

stores the twos complement of the external temperature lower

Negative Temperature = Limit Register Code (d) − 256

D7

0¹

D6

1¹

D5

1¹

D4

0¹

D3

0¹

D2

1¹

D1

0¹

D0

0¹

INT

limit, and causes an interrupt and activates the INT/

output

(if enabled). For this to happen, the measured external

temperature value has to be more negative than or equal to the

value in this register. Because it is an 8-bit register, the

temperature resolution is 1°C. The default value is 0°C.

¹Default settings at power-up.

Internal T_LOWLimit Register (Read/Write) [Address = 0x26]

Positive Temperature = Limit Register Code (d)

This limit register is an 8-bit read/write register that stores the

twos complement of the internal temperature lower limit, and

Negative Temperature = Limit Register Code (d) − 256

INT

causes an interrupt and activates the INT/

output (if enabled).

If Pin 7 and Pin 8 are configured for AIN1 and AIN2 inputs,

this limit register is an 8-bit read/write register that stores the

AIN1 input lower limit, and causes an interrupt and activates

For this to happen, the measured internal temperature value has

to be more negative than or equal to the value in this register.

Because it is an 8-bit register, the temperature resolution is 1°C.

The default value is −55°C.

INT

the INT/

output (if enabled). For this to happen, the

measured AIN1 value has to be less than or equal to the value in

this register. Because it is an 8-bit register, the resolution is four

times less than the resolution of the 10-bit ADC. Because the

power-up default settings for Pin 7 and Pin 8 are AIN1 and

AIN2 inputs, the default value for this limit register is 0 V.

Positive Temperature = Limit Register Code (d)

Negative Temperature = Limit Register Code (d) − 256

D7

1¹

D6

1¹

D5

0¹

D4

0¹

D3

1¹

D2

0¹

D1

0¹

D0

1¹

¹Default settings at power-up.

Rev. B | Page 35 of 44

ADT7516/ADT7517/ADT7519

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

¹Default settings at power-up.

AIN2 V_HIGHLimit Register (Read/Write) [Address = 0x2B]

AIN4 V_HIGHLimit Register (Read/Write) [Address = 0x2F]

This limit register is an 8-bit read/write register that stores the

AIN2 input upper limit, and causes an interrupt and activates

This limit register is an 8-bit read/write register that stores the

AIN4 input upper limit, and causes an interrupt and activates

the INT/

output (if enabled). For this to happen, the

the INT/

output (if enabled). For this to happen, the

INT

measured AIN2 value has to be greater than the value in this

register. Because it is an 8-bit register, the resolution is four

times less than the resolution of the 10-bit ADC. The default

value is full-scale voltage.

measured AIN4 value has to be greater than the value in this

register. Because it is an 8-bit register, the resolution is four

times less than the resolution of the 10-bit ADC. The default

value is full-scale voltage.

D7

1¹

D6

1¹

D5

1¹

D4

1¹

D3

1¹

D2

1¹

D1

1¹

D0

1¹

D7

1¹

D6

1¹

D5

1¹

D4

1¹

D3

1¹

D2

1¹

D1

1¹

D0

1¹

¹Default settings at power-up.

AIN2 V_LOWLimit Register (Read/Write) [Address = 0x2C]

AIN4 V_LOWLimit Register (Read/Write) [Address = 0x30]

This limit register is an 8-bit read/write register that stores the

AIN2 input lower limit, and causes an interrupt and activates

This limit register is an 8-bit read/write register that stores the

AIN4 input lower limit, and causes an interrupt and activates

the INT/

output (if enabled). For this to happen, the meas-

the INT/ output (if enabled). For this to happen, the measured

INT

ured AIN2 value has to be less than or equal to the value in this

register. Because it is an 8-bit register, the resolution is four times

less than the resolution of the 10-bit ADC. The default value is 0 V.

AIN4 value has to be less than or equal to the value in this register.

Because it is an 8-bit register, the resolution is four times less

than the resolution of the 10-bit ADC. The default value is 0 V.

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

D7

0¹

D6

0¹

D5

0¹

D4

0¹

D3

0¹

D2

0¹

D1

0¹

D0

0¹

¹Default settings at power-up.¹Default settings at power-up.

¹Default settings at power-up.

AIN3 V_HIGHLimit Register (Read/Write) [Address = 0x2D]

Device ID Register (Read-Only) [Address = 0x4D]

This limit register is an 8-bit read/write register that stores the

AIN3 input upper limit, and causes an interrupt and activates

This 8-bit read-only register indicates the part model of the

device: ADT7516 = 0x03, ADT7517 = 0x07, and ADT7519 = 0x0B.

the INT/

output (if enabled). For this to happen, the

INT

Manufacturer’s ID Register (Read-Only) [Address = 0x4E]

measured AIN3 value has to be greater than the value in this

register. Because it is an 8-bit register, the resolution is four

times less than the resolution of the 10-bit ADC. The default

value is full-scale voltage.

This register contains the manufacturer’s identification number.

ID number of Analog Devices, Inc. is 0x41.

Silicon Revision Register (Read-Only) [Address = 0x4F]

This register is divided into the four LSBs representing the

stepping and the four MSBs representing the version. The

stepping contains the manufacturer’s code for minor revisions

or steppings to the silicon. The version is the ADT7516/

ADT7517/ADT7519 version number.

D7

1¹

D6

1¹

D5

1¹

D4

1¹

D3

1¹

D2

1¹

D1

1¹

D0

1¹

¹Default settings at power-up.

AIN3 V_LOWLimit Register (Read/Write) [Address = 0x2E]

SPI Lock Status Register (Read-Only) [Address = 0x7F]

This limit register is an 8-bit read/write register that stores the

AIN3 input lower limit, and causes an interrupt and activates

the INT/

ured AIN3 value has to be less than or equal to the value in this

register. Because it is an 8-bit register, the resolution is four times

less than the resolution of the 10-bit ADC. The default value is 0 V.

Bit D0 (LSB) of this read-only register indicates whether or not

the SPI interface is locked. Writing to this register causes the

device to malfunction. The default value is 0x00.

output (if enabled). For this to happen, the meas-

INT

0 = I²C interface.

1 = SPI interface selected and locked.

Rev. B | Page 36 of 44

ADT7516/ADT7517/ADT7519

CS

As per most SPI standards, the

line must be low during

SERIAL INTERFACE

There are two serial interfaces that can be used on this part, I²C

and SPI. The device powers up with the serial interface in I²C

mode, but it is not locked into this mode. To stay in I²C mode, it

every SPI communication to the ADT7516/ADT7517/ADT7519

and high all other times. Typical examples of how to connect the

dual interface as I²C or SPI are shown in Figure 57 and Figure 58.

The following sections describe in detail how to use the I²C and

SPI protocols associated with the ADT7516/ADT7517/ADT7519.

CS

is recommended that the user tie the

line to either V_CCor

GND. It is not possible to lock the I²C mode, but it is possible to

select and lock the SPI mode.

V

DD

To select and lock the interface into the SPI mode, a number of

DD

ADT7516/

ADT7517/

ADT7519

CS

pulses must be sent down the

line (Pin 4). The following

10kΩ

section describes how this is done.

CS

Once the SPI communication protocol has been locked in, it

cannot be unlocked while the device is still powered up. Bit D0

of the SPI lock status register (Address 0x7F) is set to 1 when a

successful SPI interface lock has been accomplished. To reset

the serial interface, the user must power down the part and

power it up again. A software reset does not reset the serial

interface.

SDA

SCL

2

I C ADDRESS = 1001 000

ADD

Figure 57. Typical I²C Interface Connection

ADT7516/

ADT7517/

ADT7519

LOCK AND

Serial Interface Selection

SELECT SPI

2

CS

The

line controls the selection between I C and SPI.

CS

Figure 59 shows the selection process necessary to lock the SPI

interface mode.

V

DD

SPI FRAMING

EDGE

To communicate to the ADT7516/ADT7517/ADT7519 using

820Ω 820Ω 820Ω

CS

the SPI protocol, send three pulses down the

line as shown

DIN

SCLK

DOUT

in Figure 59. On the third rising edge (marked as C in Figure 59),

the part selects and locks the SPI interface. The user is now

limited to communicating to the device using the SPI protocol.

Figure 58. Typical SPI Interface Connection.

A

B

C

CS

(START HIGH)

SPI LOCKED ON

THIRD RISING EDGE

SPI FRAMING

EDGE

A

B

C

CS

(START LOW)

SPI LOCKED ON

THIRD RISING EDGE

SPI FRAMING

EDGE

Figure 59. Serial Interface—Selecting and Locking SPI Protocol

Rev. B | Page 37 of 44

ADT7516/ADT7517/ADT7519

I²C Serial Interface

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low to high

transition when the clock is high can be interpreted as a

stop signal.

Like all I²C-compatible devices, the ADT7516/ADT7517/

ADT7519 have a 7-bit serial address. The four MSBs of this

address for the ADT7516/ADT7517/ADT7519 are set to 1001.

The three LSBs are set by Pin 11, ADD. The ADD pin can be

configured three ways to give three different address options:

low, floating, and high. Setting the ADD pin low gives a serial bus

address of 1001 000, leaving it floating gives the Address 1001 010,

and setting it high gives the Address 1001 011. The recommended

pull-up resistor value is 10 kΩ.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10^thclock pulse to assert a

stop condition. In read mode, the master device pulls the

data line high during the low period before the ninth clock

pulse. This is known as no acknowledge. The master then

takes the data line low during the low period before the 10^th

clock pulse, and then high during the 10^thclock pulse to

assert a stop condition.

There is an enable/disable bit for the SMBus timeout. When this

is enabled, the SMBus times out after 25 ms of no activity. To

enable it, set Bit 6 of the Control Configuration 2 register. The

power-on default is with the SMBus timeout disabled.

The ADT7516/ADT7517/ADT7519 support SMBus packet

error checking (PEC), but its use is optional. It is triggered by

supplying the extra clocks for the PEC byte. The PEC is

calculated using CRC-8. The frame clock sequence (FCS)

conforms to CRC-8 by the polynomial

Any number of bytes of data can be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

C(x) = x⁸+ x²+ x¹+ 1

Consult the SMBus specification for more information.

The serial bus protocol operates as follows:

The I²C address set up by the ADD pin is not latched by the

device until after this address has been sent twice. On the eighth

SCL cycle of the second valid communication, the serial bus

address is latched in. This is the SCL cycle directly after the

device has seen its own I²C serial bus address. Any subsequent

changes on this pin have no effect on the I²C serial bus address.

1. The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on the serial

data line (SDA) while the serial clock line (SCL) remains

high. This indicates that an address/data stream follows.

All slave peripherals connected to the serial bus respond to

the start condition and shift in the next eight bits,

Writing to the ADT7516/ADT7517/ADT7519

Depending on the register being written to, there are two different

writes for the ADT7516/ADT7517/ADT7519. It is not possible

to do a block write to this part, that is, no I²C auto-increment.

W

consisting of a 7-bit address (MSB first) plus a R/ bit; this

determines the direction of the data transfer, that is,

whether data is written to or read from the slave device.

Writing to the Address Pointer Register for a

Subsequent Read

The peripheral whose address corresponds to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the acknowledge bit. All other devices on the bus now

remain idle while the selected device waits for data to be

To read data from a particular register, the address pointer

register must contain the address of that register. If it does not,

the correct address must be written to the address pointer

register by performing a single-byte write operation, as shown

in Figure 60. The write operation consists of the serial bus

address followed by the address pointer byte. No data is written

to any of the data registers. A read operation is then performed

to read the register.

W

read from or written to it. If the R/ bit is 0, the master

W

writes to the slave device. If the R/ bit is 1, the master

reads from the slave device.

1

9

1

9

SCL

1

0

1

A2

A1

A0

R/W

ACK. BY

P7

P6

P5

P4

P3

P2

P1

P0

SDA

START BY

ACK. BY

ADT7516/ADT7517/ADT7519 MASTER

STOP BY

MASTER

ADT7516/ADT7517/ADT7519

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

Figure 60. I²C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

Rev. B | Page 38 of 44

ADT7516/ADT7517/ADT7519

1

9

1

9

SCL

SDA

0

1

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

R/W

ACK. BY

START BY

MASTER

ACK. BY

ADT7516/ADT7517/ADT7519

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

STOP BY

MASTER

ACK. BY

ADT7516/ADT7517/ADT7519

FRAME 3

DATA BYTE

Figure 61. I²C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

1

9

1

9

SCL

SDA

0

1

A2

A1

A0 R/W

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY

ADT7616/ADT7517/ADT7519

START BY

MASTER

NO ACK. BY STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

SINGLE DATA BYTE FROM ADT7516/ADT7517/ADT7519

Figure 62. I²C—Reading a Single Byte of Data from a Selected Register

Writing Data to a Register

CS

is also used to

to the serial clock and data lines. The

distinguish between any two separate serial communications

(see Figure 67 for a graphical explanation). The SCLK is used to

clock data in and out of the part. The DIN line is used to write

to the registers, and the DOUT line is used to read data back

from the registers. The recommended pull-up resistor value is

between 500 Ω and 820 Ω. Strong pull-ups are needed when

serial clock speeds that are close to the maximum limit are used

or when the SPI interface lines are experiencing large capacitive

loading. Larger resistor values can be used for pull-up resistors

when the serial clock speed is reduced.

All registers are 8-bit registers, therefore only one byte of data

can be written to each register. Writing a single byte of data to

one of these read/write registers consists of the serial bus

address, the data register address written to the address pointer

register, followed by the data byte written to the selected data

register. This is illustrated in Figure 61. To write to a different

register, another start or repeated start is required. If more than

one byte of data is sent in one communication operation, the

addressed register is repeatedly loaded until the last data byte

has been sent.

The part operates in slave mode and requires an externally

applied serial clock to the SCLK input. The serial interface is

designed to allow the part to be interfaced to systems that

provide a serial clock that is synchronized to the serial data.

Reading Data from the ADT7516/ADT7517/ADT7519

Reading data from the ADT7516/ADT7517/ADT7519 is done

in a one-byte operation. Reading back the contents of a register

is shown in Figure 62. The register address had previously been

set up by a single-byte write operation to the address pointer

register. To read from another register, write to the address

pointer register again to set up the relevant register address.

Thus, block reads are not possible, that is, no I²C auto-increment.

There are two types of serial operations, read and write.

Command words are used to distinguish read operations from

write operations. These command words are given in Table 23.

Address auto-increment is possible in SPI mode.

SPI Serial Interface

Table 23. SPI Command Words

The SPI serial interface of the ADT7516/ADT7517/ADT7519

Write

Read

CS

consists of four wires:

, SCLK, DIN, and DOUT. The

is

0x90 (1001 0000)

0x91 (1001 0001)

used to select the device when more than one device is connected

Rev. B | Page 39 of 44

ADT7516/ADT7517/ADT7519

CS

8

1

8

1

SCLK

DIN

D6

D2

D1

D7

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D0

START

WRITE COMMAND

REGISTER ADDRESS

CS (CONTINUED)

1

8

SCLK (CONTINUED)

D7

D6

D4

D3

D1

D5

D2

D0

DIN (CONTINUED)

STOP

DATA BYTE

Figure 63. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register

Write Operation

Read Operation

Figure 63 shows the timing diagram for a write operation to the

ADT7516/ADT7517/ADT7519. Data is clocked into the

Figure 64 to Figure 66 show the timing diagrams necessary to

accomplish correct read operations. To read back from a

register, first write to the address pointer register with the

address of the register to be read from. This operation is shown

in Figure 64. Figure 65 shows the procedure for reading back a

single byte of data. The read command is first sent to the part

during the first eight clock cycles. As the read command is

being sent, irrelevant data is output onto the DOUT line.

During the following eight clock cycles, the data contained in

the register selected by the address pointer register is output

onto the DOUT line. Data is output onto the DOUT line on the

falling edge of SCLK. Figure 66 shows the procedure when

reading data from two sequential registers. Multiple data reads

are possible in the SPI interface mode as the address pointer

register is auto-incremental. The address pointer register auto-

increments from 0x00 to 0x3F and loops back to start again at

0x00 when it reaches 0x3F.

CS

registers on the rising edge of SCLK. When the

the DIN and DOUT lines are in three-state mode. Only when

CS

line is high,

the

goes from a high to a low does the part accept any data

on the DIN line. In SPI mode, the address pointer register is

capable of auto-incrementing to the next register in the register

map without having to load the address pointer register each

time. In Figure 63, the register address portion gives the first

register that is written to. Subsequent data bytes are written into

sequential writable registers. Thus, after each data byte has been

written into a register, the address pointer register auto-

increments its value to the next available register. The address

pointer register auto-increments from 0x00 to 0x3F and loops

back to start again at 0x00 when it reaches 0x3F.

Rev. B | Page 40 of 44

ADT7516/ADT7517/ADT7519

CS

1

8

1

8

SCLK

DIN

D2

D1

D6

D7

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

D0

STOP

START

WRITE COMMAND

REGISTER ADDRESS

Figure 64. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation

CS

1

8

1

8

SCLK

X

D6

X

DIN

D7

D5

X

D4

X

D3

X

D1

X

D0

X

D2

X

D0

X

D7

D6

D5

D4

D3

D2

D1

DOUT

STOP

START

DATA BYTE 1

READ COMMAND

Figure 65. SPI—Reading a Single Byte of Data From a Selected Register

CS

1

8

1

8

SCLK

DIN

X

D6

X

D5

X

D1

X

D7

X

D4

X

D3

X

D2

X

D0

X

DOUT

X

D7

D6

D5

D4

D3

D2

D1

D0

START

READ COMMAND

DATA BYTE 1

CS (CONTINUED)

1

8

SCLK (CONTINUED)

DIN (CONTINUED)

X

DOUT (CONTINUED)

D6

D5

D4

D3

D1

D0

D7

D2

STOP

DATA BYTE 2

Figure 66. SPI—Reading Two Bytes of Data from Two Sequential Registers

CS

SPI

READ OPERATION

WRITE OPERATION

CS

Figure 67. SPI—Correct Use of during SPI Communication

Rev. B | Page 41 of 44

ADT7516/ADT7517/ADT7519

SMBALERT

INT

SMBus/SPI INT/

allows them to do so.

is used in conjunction with

the SMBus general call address.

INT

The ADT7516/ADT7517/ADT7519 INT/

outputs are an

INT

interrupt line for devices that want to trade their ability to

One or more INT/

outputs can be connected to a common

master for an extra pin. The ADT7516/ADT7517/ADT7519 are

SMBALERT

line connected to the master. When the

line is pulled low by one of the devices, the

INT

slave devices and use the SMBus/SPI INT/

to signal the host

INT

device that it wants to talk to. The SMBus/SPI INT/

on the

following procedure occurs as shown in Figure 68:

SMBALERT

ADT7516/ADT7517/ADT7519 is used as an over/under limit

indicator.

1.

is pulled low.

2. Master initiates a read operation and sends the alert

response address (ARA = 0001 100). This general call

address must not be used as a specific device address.

INT

The INT/

outputs of several devices to be wire-AND’ed together when the

INT

pin has an open-drain configuration that allows the

INT/

register to set the active polarity of the INT/

INT

pin is active low. Use C6 of the Control Configuration 1

INT

3. A device whose INT/

output is low responds to the

INT

output. The

alert response address and the master reads its device

address. As the device address is seven bits long, an LSB of

1 is added. The address of the device is now known and it

can be interrogated in the usual way.

power-up default is active low. The INT/

output can be

disabled or enabled by setting C5 of the Control Configuration 1

register to 1 or 0, respectively.

INT

The INT/

output becomes active when either the internal

INT

4. If INT/

output of more than one device is low, the one

temperature value, the external temperature value, V_DDvalue, or

any of the AIN input values exceed the values in their

corresponding T_HIGH/V_HIGHor T_LOW/V_LOWregisters. The

with the lowest device address has priority in accordance

with normal SMBus specifications.

5. When the ADT7516/ADT7517/ADT7519 have responded

INT

INT/

output goes inactive again when a conversion result

INT

to the alert response address, they reset their INT/

has the measured value back within the trip limits and when the

status register associated with the out-of-limit event is read. The

two interrupt status registers show the event that caused the

output, provided that the condition that caused the out-of-

limit event no longer exists and that the status register

associated with the out-of-limit event is read. If the

INT

INT/

The INT/

can be connected to a voltage different from V_DD, provided the

INT

pin to go active.

SMBALERT

line remains low, the master sends the ARA

again. It continues to do this until all devices whose

INT

output requires an external pull-up resistor. This

SMBALERT

outputs were low have responded.

maximum voltage rating of the INT/

output pin is not

exceeded. The value of the pull-up resistor depends on the

application but should be large enough to avoid excessive sink

MASTER

RECEIVES

SMBALERT

INT

currents at the INT/

output because they can heat the chip

ALERT RESPONSE

NO

ACK

START

RD ACK DEVICE ADDRESS

STOP

and affect the temperature reading.

ADDRESS

SMBUS ALERT RESPONSE

MASTER SENDS

ARA AND READ

COMMAND

DEVICE SENDS

ITS ADDRESS

INT

The INT/

when the SMBus/I²C interface is selected. It is an open-drain

INT

pin behaves the same way as an SMBus alert pin

INT

SMBALERT

ARA

Figure 68. INT/

Responds to

output and requires a pull-up to V_DD. Several INT/

can be wire-AND’ed together, so that the common line goes low

INT

outputs

MASTER

ACK

MASTER

NACK

DEVICE ACK

MASTER

if one or more of the INT/

outputs goes low. The polarity of

pin must be set active low for a number of outputs

to be wire-AND’ed together.

INT

RECEIVES

SMBALERT

INT

the INT/

ALERT RESPONSE

ADDRESS

DEVICE

ADDRESS

NO

ACK

START

RD ACK

ACK

PEC

STOP

MASTER SENDS

ARA AND READ

COMMAND

SMBALERT

function.

The INT/

Slave devices on the SMBus cannot normally signal to the

SMBALERT

output can operate as an

DEVICE SENDS DEVICE SENDS

ITS ADDRESS ITS PEC DATA

INT

SMBALERT

ARA

Figure 69. INT/

Responds to

master that they want to talk, but the

function

with Packet Error Checking (PEC)

Rev. B | Page 42 of 44

ADT7516/ADT7517/ADT7519

OUTLINE DIMENSIONS

0.197

0.193

0.189

16

1

9

8

0.158

0.154

0.150

0.244

0.236

0.228

PIN 1

0.069

0.053

0.065

0.049

8°

0°

0.010

0.004

0.025

BSC

0.012

0.008

0.050

0.016

SEATING

PLANE

0.010

0.006

COPLANARITY

0.004

COMPLIANT TO JEDEC STANDARDS MO-137-AB

Figure 70. 16-Lead Shrink Small Outline Package [QSOP]

(RQ-16)

Dimensions shown in inches

ORDERING GUIDE

DAC

Package

Ordering

Model

Temperature Range

Resolution

Description

Package Option

RQ-16

Quantity

ADT7519ARQ

–40°C to +120°C

8 Bits

16-Lead QSOP

Evaluation Board

98

ADT7519ARQ-REEL

ADT7519ARQ-REEL7

ADT7519ARQZ¹

ADT7519ARQZ-REEL¹

ADT7519ARQZ-REEL7¹

ADT7517ARQ

ADT7517ARQ-REEL

ADT7517ARQ-REEL7

ADT7517ARQZ¹

ADT7517ARQZ-REEL¹

ADT7517ARQZ-REEL7¹

ADT7516ARQ

ADT7516ARQ-REEL

ADT7516ARQ-REEL7

ADT7516ARQZ¹

ADT7516ARQZ-REEL¹

ADT7516ARQZ-REEL7¹

EVAL-ADT7516EB

2,500

1,000

98

2,500

1,000

98

2,500

1,000

98

2,500

1,000

98

2,500

1,000

98

2,500

1,000

10 Bits

12 Bits

¹Z = Pb-free part.

Rev. B | Page 43 of 44

ADT7516/ADT7517/ADT7519

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent.

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

C02883-0-10/06(B)

Rev. B | Page 44 of 44


型号：	ADT7517ARQZ
厂家：	ADI
描述：	SPI-/I2C-Compatible, Temperature Sensor,4-Channel ADC and Quad Voltage Output SPI / I2C兼容，温度传感器， 4通道ADC和四路电压输出传感器换能器温度传感器输出元件
文件：	总44页 (文件大小：1144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADT7517ARQZ [ADI]

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