ADT7518ARQ-REEL [ADI]
SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC; SPI / I2C兼容，温度传感器， 4通道ADC和四路电压输出DAC
| 型号： | ADT7518ARQ-REEL |
| 厂家： | 
ADI |
| 描述： | SPI/I2C Compatible, Temperature Sensor, 4-Channel ADC and Quad Voltage Output DAC |
| 文件： | 总40页 (文件大小：1349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI/I2C Compatible, Temperature Sensor,
4-Channel ADC and Quad Voltage Output DAC
ADT7518
FEATURES
APPLICATIONS
Four 8-bit DACs
Portable battery-powered instruments
Buffered voltage output
Personal computers
Guaranteed monotonic by design over all codes
10-bit temperature-to-digital converter
10-bit 4-channel ADC
Smart battery chargers
Telecommunications systems
Electronic text equipment
Domestic appliances
DC input bandwidth
Input range: 0 V to 2.25 V
Process control
Temperature range: –40°C to +120°C
Temperature sensor accuracy of typ: 0.5°C
Supply range: 2.7 V to 5.5 V
PIN CONFIGURATION
DAC output range: 0 V to 2 VREF
Power-down current: 1 µA
Internal 2.25 VREF option
Double-buffered input logic
Buffered reference input
Power-on reset to 0 V DAC output
Simultaneous update of outputs (LDAC function)
On-chip rail-to-rail output buffer amplifier
V
V
-B
1
2
3
4
5
6
7
8
16
15
V
V
-C
OUT
OUT
OUT
OUT
-A
-D
V
-IN
14 AIN4
REF
ADT7518
TOP VIEW
CS
13 SCL/SCLK
12 SDA/DIN
11 DOUT/ADD
10 INT/INT
GND
(Not to Scale)
V
DD
D+/AIN1
D–/AIN2
9
LDAC/AIN3
Figure 1.
SPI®, I2C®, QSPI™, MICROWIRE™, and DSP-compatible
4-wire serial interface
SMBus packet error checking (PEC)-compatible
16-lead QSOP package
The reference for the four DACs is derived either internally or
from a reference pin. The outputs of all DACs may be updated
simultaneously using the software LDAC function or the exter-
GENERAL DESCRIPTION
The ADT75181 combines a 10-bit temperature-to-digital
converter, a 10-bit 4-channel ADC, and a quad 8-bit DAC, in a
16-lead QSOP package. The part also includes a band gap
temperature sensor and a 10-bit ADC to monitor and digitize
the temperature reading to a resolution of 0.25°C.
LDAC
nal
pin. The ADT7518 incorporates a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write takes place.
The ADT7518’s wide supply voltage range, low supply current,
and SPI-/I2C-compatible interface make it ideal for a variety of
applications, including personal computers, office equipment,
and domestic appliances.
The ADT7518 operates from a single 2.7 V to 5.5 V supply. The
input voltage range on the ADC channels is 0 V to 2.25 V, and
the input bandwidth is dc. The reference for the ADC channels
is derived internally. The output voltage of the DAC ranges
from 0 V to VDD, with an output voltage settling time of 7 ms
typical.
It is recommended that new designs use the ADT7519 rather
than the ADT7518. The ADT7518’s internal and external temp-
erature accuracy spec is only valid when not using the internal
reference for the on-chip DAC. The ADT7519 does not have
this limitation.
The ADT7518 provides two serial interface options: a 4-wire
serial interface that is compatible with SPI, QSPI, MICROWIRE,
and DSP interface standards, and a 2-wire SMBus/I2C interface.
It features a standby mode that is controlled through the serial
interface.
1 Protected by the following U.S. Patent Numbers: 6,169,442; 5,867,012;
5,764174. Other patents pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADT7518
TABLE OF CONTENTS
Specifications..................................................................................... 3
Conversion Speed....................................................................... 17
Function Description—Voltage Output.................................. 18
Functional Description—Analog Inputs................................. 20
ADC Transfer Function............................................................. 21
Functional Description—Measurement.................................. 22
ADT7518 Registers .................................................................... 25
Serial Interface............................................................................ 33
SMBus Alert Response............................................................... 38
Outline Dimensions....................................................................... 40
Ordering Guide .......................................................................... 40
DAC AC Characteristics.............................................................. 6
Functional Block Diagram .............................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Functional Descriptions.......................... 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
Power-Up Calibration................................................................ 17
REVISION HISTORY
8/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated Format...................................................................... Universal
Separate ADT7518 from
ADT7516/ADT7517/ADT7518 Data Sheet........................ Universal
Change to Equation.............................................................................25
7/03—Revision 0: Initial Version
Rev. A | Page 2 of 40
ADT7518
SPECIFICATIONS
Table 1. Temperature range is as follows: A version: –40°C to +120°C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless
otherwise noted.
Parameter1
DAC DC PERFORMANCE2,3
Min
Typ
Max
Unit
Conditions/Comments
Resolution
8
Bits
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Lower Deadband
0.15
0.02
0.4
0.3
20
1
0.25
2
2
65
LSB
LSB
% of FSR
% of FSR
mV
Guaranteed monotonic over all codes.
Lower deadband exists only if offset error is
negative. See Figure 8.
Upper Deadband
60
100
mV
Upper deadband exists if VREF = VDD and offset
plus gain error is positive. See Figure 9.
Offset Error Drift4
Gain Error Drift4
–12
–5
ppm of FSR/°C
ppm of FSR/°C
DC Power Supply Rejection Ratio4
DC Crosstalk4
–60
200
dB
µV
∆VDD = 10%.
See Figure 5.
Max VDD = 5 V.
ADC DC ACCURACY
Resolution
Total Unadjusted Error (TUE)
Offset Error
10
3
0.5
2
Bits
2
% of FSR
% of FSR
% of FSR
Hz
Gain Error
ADC BANDWIDTH
ANALOG INPUTS5
Input Voltage Range
DC
0
0
2.25
VDD
1
V
V
µA
pF
MΩ
AIN1 to AIN4. C4 = 0 in Control Configuration 3.
AIN1 to AIN4. C4 = 0 in Control Configuration 3.
DC Leakage Current
Input Capacitance
Input Resistance
5
10
20
THERMAL CHARACTERISTICS6
Internal reference used. Averaging on.
INTERNAL TEMPERATURE SENSOR
Accuracy @ VDD = 3.3 V 10%
1.5
3
5
3
5
°C
°C
°C
°C
°C
Bits
°C
TA = 85°C.
TA= 0°C to +85°C.
0.5
2
2
TA = –40°C to +120°C.
TA = 0°C to +85°C.
TA = –40°C to +120°C.
Equivalent to 0.25°C.
Drift over 10 years if part is operated at 55°C.
External transistor = 2N3906.
Accuracy @ VDD = 5 V 5%
3
Resolution
Long-Term Drift
THERMAL CHARACTERISTICS6
EXTERNAL TEMPERATURE SENSOR
Accuracy @ VDD = 3.3 V 10%
10
0.25
1.5
3
5
3
5
°C
°C
°C
°C
TA = 85°C.
TA = 0°C to +85°C.
TA = –40°C to +120°C.
TA = 0°C to +85°C.
TA = –40°C to +120°C.
Equivalent to 0.25°C.
High Level.
Accuracy @ VDD = 5 V 5%
2
3
°C
Resolution
Output Source Current
10
Bits
µA
µA
180
11
Low Level.
THERMAL CHARACTERISTICS6
Thermal Voltage Output
8-Bit DAC Output
Resolution
1
°C
Rev. A | Page 3 of 40
ADT7518
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
Scale Factor
8.97
17.58
mV/°C
mV/°C
0 V to VREF output. TA = –40°C to +120°C.
0 V to 2 VREF output. TA = –40°C to +120°C.
Single channel mode.
CONVERSION TIMES
Slow ADC
VDD/AIN
11.4
712
ms
µs
Averaging (16 samples) on.
Averaging off.
Internal Temperature
External Temperature
11.4
712
24.22
1.51
ms
µs
ms
ms
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Fast ADC
VDD/AIN
712
µs
µs
ms
µs
ms
µs
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
Averaging (16 samples) on.
Averaging off.
44.5
2.14
134
14.25
890
Internal Temperature
External Temperature
ROUND ROBIN UPDATE RATE5
Time to complete one measurement cycle
through all channels.
Slow ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
79.8
4.99
94.76
9.26
ms
ms
ms
ms
AIN1 and AIN2 are selected on Pins 7 and 8.
AIN1 and AIN2 are selected on Pins 7 and 8.
D+ and D– are selected on Pins 7 and 8.
D+ and D– are selected on Pins 7 and 8.
Fast ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
6.41
ms
µs
ms
ms
AIN1 and AIN2 are selected on Pins 7 and 8.
AIN1 and AIN2 are selected on Pins 7 and 8.
D+ and D– are selected on Pins 7 and 8.
D+ and D– are selected on Pins 7 and 8.
400.84
21.77
3.07
DAC EXTERNAL REFERENCE INPUT4
VREF Input Range
1
VDD
V
Buffered reference.
VREF Input Impedance
Reference Feedthrough
Channel-to-Channel Isolation
ON-CHIP REFERENCE
Reference Voltage4
Temperature Coefficient4
OUTPUT CHARACTERISTICS4
Output Voltage 7
>10
–90
–75
MΩ
dB
dB
Buffered reference and power-down mode.
Frequency = 10 kHz.
Frequency = 10 kHz.
2.25
80
V
ppm/°C
0.001
VDD − 0.1
V
This is a measure of the minimum and maximum
drive capability of the output amplifier.
DC Output Impedance
Short-Circuit Current
0.5
25
16
2.5
5
Ω
mA
mA
µs
VDD = 5 V.
VDD = 3 V.
Power-Up Time
Coming out of power-down mode. VDD = 5 V.
Coming out of power-down mode. VDD = 3.3 V.
µs
DIGITAL INPUTS4
Input Current
1
0.8
µA
V
V
pF
ns
VIN = 0 V to VDD.
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
1.89
20
3
10
50
All digital inputs.
Input filtering suppresses noise spikes of less
than 50 ns.
SCL, SDA Glitch Rejection
LDAC Pulse Width
ns
Edge triggered input.
Rev. A | Page 4 of 40
ADT7518
Parameter1
Min
Typ
Max
Unit
Conditions/Comments
DIGITAL OUTPUT
Digital High Voltage, VOH
Output Low Voltage, VOL
Output High Current, IOH
Output Capacitance, COUT
INT/INT Output Saturation Voltage
2.4
V
V
mA
pF
V
ISOURCE = ISINK = 200 µA.
IOL = 3 mA.
VOH = 5 V.
0.4
1
50
0.8
I
OUT = 4 mA.
I2C TIMING CHARACTERISTICS 8, 9
Serial Clock Period, t1
Data In Setup Time to SCL High, t2
Data Out Stable after SCL Low, t3
SDA Low Setup Time to SCL
Low (Start Condition), t4
2.5
50
0
µs
ns
ns
ns
Fast Mode I2C. See Figure 2.
See Figure 2.
See Figure 2.
50
SDA High Hold Time after SCL
High (Stop Condition), t5
50
ns
ns
See Figure 2.
See Figure 2.
SDA and SCL Fall Time, t6
SPI TIMING CHARACTERISTICS4, 10
CS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
90
35
0
ns
ns
ns
ns
See Figure 3.
See Figure 3.
See Figure 3.
50
50
Data Access Time after SCLK
11
Falling Edge, t4
Data Setup Time Prior to SCLK
Rising Edge, t5
Data Hold Time after SCLK Rising
Edge, t6
20
0
ns
ns
See Figure 3.
See Figure 3.
CS to SCLK Hold Time, t7
0
µs
ns
See Figure 3.
See Figure 3.
CS to DOUT High Impedance, t8
40
POWER REQUIREMENTS
VDD
VDD Settling Time
IDD (Normal Mode) 12
2.7
5.5
50
3
V
ms
mA
mA
µA
µA
mW
µW
VDD settles to within 10% of its final voltage level.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD, and VIL = GND.
VDD = 3.3 V, VIH = VDD, and VIL = GND.
VDD = 5 V, VIH = VDD, and VIL = GND.
VDD = 3.3 V. Normal mode.
2.2
3
IDD (Power-Down Mode)
Power Dissipation
10
10
10
33
VDD = 3.3 V. Shutdown mode.
1 See the Terminology section.
2 DC specifications are tested with the outputs unloaded.
3 Linearity is tested using a reduced code range: ADT7518 (Code 8 to 255).
4 Guaranteed by design and characterization, not production tested.
5 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.
6 The temperature accuracy specifications are valid when the internal reference is not being used by the on-chip DAC. For new designs, the ADT7519 is recommended
as it does not have this limitation.
7 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset
plus gain error must be positive.
8 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate
but has a negative effect on the EMC behavior of the part.
9 Guaranteed by design, not production tested.
10 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.
11 Measured with the load circuit shown in Figure 4.
12 The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.
Rev. A | Page 5 of 40
ADT7518
DAC AC CHARACTERISTICS1
Table 2. VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD; all specifications TMIN to TMAX, unless
otherwise noted.
Parameter2
Min
Typ3
Max
Unit
Conditions/Comments
Output Voltage Settling Time
ADT7518
VREF = VDD = 5 V
1/4 scale to 3/4 scale change (40h to C0h)
6
8
µs
Slew Rate
0.7
12
0.5
1
0.5
3
V/µs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
1 LSB change around major carry
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
200
–70
VREF = 2 V 0.1 V p-p
VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz.
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 @ 25°C.
t1
SCL
t5
t2
t4
SDA
DATA IN
t3
SDA
DATA OUT
t6
Figure 2. I2C Bus Timing Diagram
CS
t1
t2
t7
SCLK
DIN
t6
t3
t5
t8
D7
X
D6
X
D5
D4
D3
X
D2
D1
D0
X
X
X
X
X
X
X
X
X
t4
DOUT
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. SPI Bus Timing Diagram
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200µA
I
OH
Figure 4. Load Circuit for Access Time and Bus Relinquish Time
V
DD
4.7kΩ
TO DAC
OUTPUT
4.7kΩ
200pF
Figure 5. Load Circuit for DAC Outputs
Rev. A | Page 6 of 40
ADT7518
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
TEMPERATURE
VALUE REGISTER
ADT7518
ON-CHIP
TEMPERATURE
ADDRESS POINTER
REGISTER
SENSOR
EXTERNAL
T
LIMIT
HIGH
REGISTERS
TEMPERATURE
VALUE REGISTER
T
LIMIT
LOW
REGISTERS
DAC A
STRING
DAC A
7
8
D+/AIN1
D–/AIN2
LDAC/AIN3
AIN4
2
1
V
V
V
V
-A
-B
-C
-D
OUT
OUT
OUT
OUT
REGISTERS
LIMIT
COMPARATOR
V
LIMIT
CC
REGISTERS
A-TO-D
ANALOG
MUX
AIN
HIGH
REGISTERS
LIMIT
CONVERTER
DAC B
REGISTERS
STRING
DAC B
9
14
AIN
REGISTERS
LIMIT
LOW
V
DD
DAC C
REGISTERS
STRING
DAC C
16
15
VALUE REGISTER
CONTROL CONFIG. 1
REGISTER
AIN1
VALUE REGISTER
CONTROL CONFIG. 2
REGISTER
V
DD
SENSOR
DAC D
REGISTERS
STRING
DAC D
AIN2
CONTROL CONFIG. 3
REGISTER
VALUE REGISTER
AIN3
GAIN
SELECT
LOGIC
POWER-
DOWN
LOGIC
DAC CONFIGURATION
REGISTERS
VALUE REGISTER
AIN4
LDAC CONFIGURATION
REGISTERS
VALUE REGISTER
10
INT/INT
INTERRUPT MASK
REGISTERS
STATUS
REGISTERS
INTERNAL
REFERENCE
SPI/SMBus INTERFACE
6
5
4
13
12
11
9
3
V
GND
CS
SCL
SDA
ADD
LDAC/AIN3
V
-IN
REF
DD
Figure 6.
Rev. A | Page 7 of 40
ADT7518
ABSOLUTE MAXIMUM RATINGS
Table 3.
Table 4. I2C Address Selection
Parameter
Rating
ADD Pin
I2C Address
VDD to GND
–0.3 V to +7 V
Low
Float
High
1001 000
1001 010
1001 011
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead QSOP Package
Power Dissipation1
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
–40°C to +120°C
–65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
(TJ max – TA)/θJA
Thermal Impedance2
θJA Junction-to-Ambient
θJC Junction-to-Case
105.44°C/W
38.8°C/W
IR Reflow Soldering
Peak Temperature
Time at Peak Temperature
Ramp-Up Rate
220°C (0°C/5°C)
10 sec to 20 sec
2°C/sec to 3°C/sec
–6°C/sec
1 Values relate to package being used on a 4-layer board.
2 Junction-to-case resistance is applicable to components featuring a
preferential flow direction, e.g., components mounted on a heat sink.
Junction-to-ambient resistance is more useful for air cooled PCB-mounted
components.
Ramp-Down Rate
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 8 of 40
ADT7518
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
V
-B
1
2
3
4
5
6
7
8
16
V
-C
OUT
OUT
V
-A
15
V
-D
OUT
OUT
V
-IN
CS
14 AIN4
REF
ADT7518
TOP VIEW
13 SCL/SCLK
12 SDA/DIN
11 DOUT/ADD
10 INT/INT
GND
(Not to Scale)
V
DD
D+/AIN1
D–/AIN2
9
LDAC/AIN3
Figure 7. Pin Configuration QSOP
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic Description
1
2
3
4
VOUT-B
VOUT-A
VREF-IN
CS
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to VDD.
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables
the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial
clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode.
5
6
7
GND
VDD
D+/AIN1
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
D+. Positive Connection to External Temperature Sensor. AIN1. Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to VDD.
8
9
D–/AIN2
D–. Negative Connection to External Temperature Sensor.
AIN2. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
LDAC/AIN3 LDAC. Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A
falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simul-
taneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is
with the LDAC pin controlling the loading of the DAC registers.
AIN3. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
10
11
INT/INT
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature,VDD, or AIN limits are exceeded. The default is active low. Open-drain output—needs a pull-up resistor.
DOUT/ADD SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling
edge of SCLK. Open-drain output—needs a pull-up resistor.
ADD. I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000; leaving it floating
gives the address 1001 010; and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the
I2C serial bus address.
12
13
SDA/DIN
SCL/SCLK
SDA. I2C Serial Data Input/Output. I2C serial data to be loaded into the part’s registers and read from these registers is
provided on this pin. Open-drain configuration—needs a pull-up resistor.
DIN. SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into
a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7518 and also to clock data into any register that can be written to. Open-drain configuration—needs a pull-
up resistor.
14
15
16
AIN4
VOUT-D
VOUT-C
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to VDD.
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Rev. A | Page 9 of 40
ADT7518
TERMINOLOGY
Relative Accuracy
increase in rates of reaction within the semiconductor material.
Relative accuracy or integral nonlinearity (INL) is a measure of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the transfer function. Typical INL
versus code plots can be seen in Figure 10, Figure 11, and
Figure 12.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for full-scale output of the DAC. It is measured
in dB. VREF is held at 2 V and VDD is varied 10%.
Differential Nonlinearity
DC Crosstalk
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 0.9 LSB
maximum ensures monotonicity. Typical DAC DNL versus code
plots can be seen in Figure 13, Figure 14, and Figure 15.
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.
Reference Feedthrough
Total Unadjusted Error (TUE)
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.
Total unadjusted error is a comprehensive specification that
includes the sum of the relative accuracy error, gain error, and
offset error under a specified set of conditions.
Channel-to-Channel Isolation
Offset Error
This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.
This is a measure of the offset error of the DAC and the output
amplifier (see Figure 8 and Figure 9). It can be negative or
positive, and it is expressed in mV.
Major-Code Transition Glitch Energy
Offset Error Match
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011...1 to 100...00 or
100...00 to 011...11).
This is the difference in offset error between any two channels.
Gain Error
This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic
from the ideal expressed as a percentage of the full-scale range.
Digital Feedthrough
Gain Error Match
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-s and is measured with a full-scale change on
the digital input pins, i.e., from all 0s to all 1s or vice versa.
This is the difference in gain error between any two channels.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Gain Error Drift
Digital Crosstalk
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.
Long Term Temperature Drift
This is a measure of the change in temperature error over time.
It is expressed in °C. The concept of long-term stability has been
used for many years to describe the amount an IC’s parameter
shifts during its lifetime. This is a concept that has typically
been applied to both voltage references and monolithic temp-
erature sensors. Unfortunately, integrated circuits cannot be
evaluated at room temperature (25°C) for 10 years or so to
determine this shift. Manufacturers perform accelerated lifetime
testing of integrated circuits by operating ICs at elevated temp-
eratures (between 125°C and 150°C) over a shorter period
(typically between 500 and 1,000 hours). As a result, the lifetime
of an integrated circuit is significantly accelerated due to the
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
LDAC
(all 0s to all 1s and vice versa) while keeping
high. Then
LDAC
pulse
low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Rev. A | Page 10 of 40
ADT7518
DAC-to-DAC Crosstalk
GAIN ERROR
+
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
OFFSET ERROR
OUTPUT
VOLTAGE
LDAC
change (all 0s to all 1s and vice versa) with
low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.
NEGATIVE
OFFSET
ERROR
Multiplying Bandwidth
DAC CODE
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
ACTUAL
IDEAL
LOWER
DEADBAND
CODES
Total Harmonic Distortion
AMPLIFIER
FOOTROOM
This is the difference between an ideal sine wave and its atten-
uated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output, expressed in dB.
NEGATIVE
OFFSET
ERROR
Round Robin
This term is used to describe the ADT7518 cycling through the
available measurement channels in sequence, taking a measure-
ment on each channel.
Figure 8. DAC Transfer Function with Negative Offset
GAIN ERROR
DAC Output Settling Time
+
OFFSET ERROR
This is the time required, following a prescribed data change, for
the output of a DAC to reach and remain within 0.5 LSB of the
final value. A typical prescribed change is from 1/4 scale to
3/4 scale.
UPPER
DEADBAND
CODES
OUTPUT
VOLTAGE
ACTUAL
IDEAL
POSITIVE
OFFSET
ERROR
DAC CODE
FULL SCALE
Figure 9. DAC Transfer Function with Positive Offset (VREF = VDD
)
Rev. A | Page 11 of 40
ADT7518
TYPICAL PERFORMANCE CHARACTERISTICS
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.20
INL WCP
INL WCN
0.15
0.10
0.05
0
DNL WCP
–0.05
–0.10
–0.15
–0.20
–0.02
–0.04
–0.06
DNL WCN
20
0
50
100
150
200
250
–40
–10
50
80
110
TEMPERATURE (°C)
DAC CODE
Figure 13. ADT7518 DAC INL Error and DNL Error vs. Temperature
Figure 10. ADT7518 Typical DAC INL Plot
0.10
0.08
0.06
0.04
0.02
0
0
–0.2
OFFSET ERROR
–0.4
–0.6
–0.8
–1.0
–1.2
–0.02
–0.04
–0.06
–0.08
–0.10
–1.4
GAIN ERROR
–1.6
–1.8
–40
–20
0
20
40
60
80
100
120
0
50
100
150
200
250
TEMPERATURE (°C)
DAC CODE
Figure 14. DAC Offset Error and Gain Error vs. Temperature
Figure 11. ADT7518 Typical DAC DNL Plot
10
0.30
0.25
0.20
0.15
0.10
0.05
0
OFFSET ERROR
INL WCP
5
0
V
= 2.25V
REF
–5
DNL WCP
–10
DNL WCN
INL WCN
GAIN ERROR
–15
–20
–0.05
–0.10
2.7
3.3
3.6
4.0
(V)
4.5
5.0
5.5
1.0 1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
V
V
DD
REF
Figure 15. DAC Offset Error and Gain Error vs. VDD
Figure 12. ADT7518 DAC INL and DNL Error vs, VREF
Rev. A | Page 12 of 40
ADT7518
2.505
2.500
2.495
2.490
2.485
2.480
2.475
2.470
2.465
7
6
5
4
3
2
1
0
SOURCE CURRENT
SINK CURRENT
V
V
= 5V
DD
= 5V
REF
DAC OUTPUT
LOADED TO MIDSCALE
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
(V)
0
1
2
3
4
5
6
V
CC
CURRENT (mA)
Figure 19. Power-Down Current vs. Supply Voltage @ 25°C
Figure 16. DAC VOUT Source and Sink Current Capability
4.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
OFFSET ERROR
GAIN ERROR
0
2
4
6
8
10
–40
–20
0
20
40
60
C)
80
100
120
TIME (µs)
TEMPERATURE (
°
Figure 20. DAC Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 17. Supply Current vs. DAC Code
2.00
1.95
1.90
1.85
1.80
1.75
1.8
1.6
ADC OFF
DAC OUTPUTS AT 0V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
0
2
4
6
8
10
V
(V)
CC
TIME (µs)
Figure 18. Supply Current vs. Supply Voltage @ 25°C
Figure 21. Exiting Power-Down to Midscale
Rev. A | Page 13 of 40
ADT7518
0.4700
0.4695
0.4690
0.4685
0.4680
0.4675
0.4670
0.4665
0.4660
0.4655
2.329
2.328
2.327
2.326
2.325
2.324
2.323
2.322
V
V
= 5V
DD
= 5V
REF
DAC OUTPUT LOADED
TO MIDSCALE
0.4650
0
2
4
6
8
10
0
1
2
3
4
5
TIME (µs)
TIME (µs)
Figure 22. ADT7518 DAC Major Code Transition Glitch Energy;
0...11 to 100...00
Figure 25. DAC-to-DAC Crosstalk
0.4730
0.4725
0.4720
0.4715
0.4710
0.4705
0.4700
0.4695
0.4690
0.4685
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
200
400
600
800
1000
0
2
4
6
8
10
ADC CODE
TIME (µs)
Figure 26. ADC INL with Ref = VDD (3.3 V)
Figure 23. ADT7518 DAC Major Code Transition Glitch Energy;
100…00 to 011…11
0
0
–10
–20
–30
–40
–50
–60
V
= 5V
= 25°C
DD
±100mV RIPPLE ON V
CC
T
A
V
V
= 2.25V
REF
= 3.3V
–2
DD
TEMPERATURE = 25°C
–4
–6
–8
–10
–12
1
2
3
4
5
1
10
100
V
(V)
FREQUENCY (kHz)
REF
Figure 27. PSRR vs. Supply Ripple Frequency
Figure 24. DAC Full-Scale Error vs. VREF
Rev. A | Page 14 of 40
ADT7518
15
10
1.5
1.0
0.5
0
V
= 3.3V
DD
TEMPERATURE = 25°C
EXTERNAL TEMPERATURE @ 5V
INTERNAL TEMPERATURE @ 3.3V
5
D+ TO GND
0
–5
D+ TO V
CC
–10
–15
–20
–25
–0.5
–1.0
EXTERNAL TEMPERATURE @ 3.3V
INTERNAL TEMPERATURE @ 5V
–30
0
40
85
120
0
10
20
30
40
50
60
70
80
90 100
TEMPERATURE (°C)
PCB LEAKAGE RESISTANCE (MΩ)
Figure 28. Internal Temperature Error @ 3.3 V and 5 V
Figure 31. External Temperature Error vs. PCB Leakage Resistance
3
2
0
V
= 3.3V
DD
V
= 3.3V
DD
–10
–20
–30
–40
–50
–60
OFFSET ERROR
1
0
–1
–2
–3
–4
GAIN ERROR
–40
–20
0
20
40
60
80
100
120
0
5
10
15
20
25
30
35
40
45
50
TEMPERATURE (°C)
CAPACITANCE (nF)
Figure 29. ADC Offset Error and Gain Error vs. Temperature
Figure 32. External Temperature Error vs. Capacitance between D+ and D–
3
10
V
= 3.3V
DD
COMMON-MODE
VOLTAGE = 100mV
OFFSET ERROR
8
6
2
1
0
4
2
0
–1
–2
–4
–6
–2
–3
GAIN ERROR
2.7
3.1
3.5
3.9
4.3
(V)
4.7
5.1
5.5
1
100
200
300
400
500
600
V
NOISE FREQUENCY (Hz)
DD
Figure 33. External Temperature Error vs. Common-Mode Noise Frequency
Figure 30. ADC Offset Error and Gain Error vs. VDD
Rev. A | Page 15 of 40
ADT7518
70
60
50
40
30
20
10
0
140
120
100
80
EXTERNAL TEMPERATURE
V
= 3.3V
DD
DIFFERENTIAL-MODE
VOLTAGE = 100mV
INTERNAL TEMPERATURE
60
40
TEMPERATURE OF
ENVIRONMENT
CHANGED HERE
20
–10
1
0
0
10
20
30
40
50
60
100
200
300
400
500
600
NOISE FREQUENCY (MHz)
TIME (s)
Figure 34. External Temperature Error vs. Differential-Mode Noise Frequency
Figure 36. Temperature Sensor Response to Thermal Shock
0.6
0
V
= 3.3V
DD
0.4
0.2
–5
–10
0
–15
–20
–25
–0.2
–0.4
–0.6
±250mV
1
100
200
300
400
500
600
10
100
1k
10k
100k
1M
10M
1
NOISE FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 35. Internal Temperature Error vs. Power Supply Noise Frequency
Figure 37. DAC Multiplying Bandwidth (Small Signal Frequency Response)
Rev. A | Page 16 of 40
ADT7518
THEORY OF OPERATION
and DAC B outputs can be configured to give a voltage output
proportional to the temperature of the internal and external
temperature sensors, respectively.
Directly after the power-up calibration routine, the ADT7518
goes into idle mode. In this mode, the device is not performing
any measurements and is fully powered up. All four DAC
outputs are at 0 V.
The dual serial interface defaults to the I2C protocol on power-
up. To select and lock in the SPI protocol, follow the selection
process as described in the Serial Interface Selection section.
The I2C protocol cannot be locked in, while the SPI protocol is
automatically locked in on selection. The interface can be
switched back to be I2C on selection when the device is powered
off and on. When using I2C, the CS pin should be tied to either
VDD or GND.
To begin monitoring, write to the Control Configuration 1
register (Address 18h) and set Bit C0 = 1. The ADT7518 goes
into its power-up default measurement mode, which is round
robin. The device then to take measurements on the VDD chan-
nel, internal temperature sensor channel, external temperature
sensor channel, or AIN1 and AIN2, AIN3, and finally AIN4.
Once it finishes taking measurements on the AIN4 channel, the
device immediately loops back to start taking measurements on
the VDD channel and repeats the same cycle as before. This loop
continues until the monitoring is stopped by resetting Bit C0 of
the Control Configuration 1 register to 0. It is also possible to
continue monitoring as well as switching to single-channel
mode by writing to the Control Configuration 2 register
(Address 19h) and setting Bit C4 = 1. Further explanation of
the single-channel and round robin measurement modes is
given in later sections.
There are a number of different operating modes on the
ADT7518 devices and all of them can be controlled by the
configuration registers. These features consist of enabling and
INT
disabling interrupts, polarity of the INT/
pin, enabling and
disabling the averaging on the measurement channels SMBus
timeout and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part be ini-
tiated until approximately 5 ms after VDD has settled to within
10% of its final value. It is generally accepted that most systems
take a maximum of 50 ms to power up. Power-up time is
directly related to the amount of decoupling on the voltage
supply line.
All measurement channels have averaging enabled on them on
power-up. Averaging forces the device to take an average of 16
readings before giving a final measured result. To disable aver-
aging and consequently decrease the conversion time by a factor
of 16, set Bit C5 = 1 in the Control Configuration 2 register.
During the 5 ms after VDD has settled, the part is performing a
calibration routine. Any communication to the device during
calibration will interrupt this routine, and could cause erro-
neous temperature measurements. If it is not possible to have
VDD at its nominal value by the time 50 ms has elapsed or if
communication to the device has started prior to VDD settling, it
is recommended that a measurement be taken on the VDD chan-
nel before a temperature measurement is taken. The VDD
measurement is used to calibrate out any temperature measure-
ment error due to different supply voltage values.
There are four single-ended analog input channels on the
ADT7518: AIN1 to AIN4. AIN1 and AIN2 are multiplexed with
the external temperature sensor terminals D+ and D–. Bits C1
and C2 of the Control Configuration 1 register (Address 18h)
are used to select between AIN1/AIN2 and the external
temperature sensor. The input range on the analog input
channels is dependent on whether the ADC reference used is
the internal VREF or VDD. To meet linearity specifications, it is
recommended that the maximum VDD value is 5 V. Bit C4 of the
Control Configuration 3 register is used to select between the
internal reference or VDD as the analog inputs’ADC reference.
CONVERSION SPEED
The internal oscillator circuit used by the ADC has the capa-
bility to output two different clock frequencies. This means that
the ADC is capable of running at two different speeds when
doing a conversion on a measurement channel. Thus, the time
taken to perform a conversion on a channel can be reduced by
setting Bit C0 of the Control Configuration 3 register (Address
1Ah). This increases the ADC clock speed from 1.4 kHz to 22
kHz. At the higher clock speed, the analog filters on the D+ and
D– input pins (external temperature sensor) are switched off.
This is why the power-up default setting is to have the ADC
working at the slow speed. The typical times for fast and slow
ADC speeds are given in the specifications.
Controlling the DAC outputs can be done by writing to the
DACs’ MSB and LSB registers (Addresses 10h to 17h). The
power-up default setting is to have a low going pulse on the
pin (Pin 9) controlling the updating of the DAC outputs
LDAC
from the DAC registers. Alternatively, one can configure the
updating of the DAC outputs to be controlled by means other
than the
pin by setting Bit C3 = 1 of the Control Config-
LDAC
uration 3 register (Address 1Ah). The DAC Configuration
register (Address 1Bh) and the LDAC Configuration register
(Address 1Ch) can now be used to control the DAC updating.
These two registers also control the output range of the DACs
and selecting between the internal or external reference. DAC A
Rev. A | Page 17 of 40
ADT7518
The ADT7518 powers up with averaging on. This means every
channel is measured 16 times and internally averaged to reduce
noise. The conversion time can also be sped up by turning off
the averaging. This is done by setting Bit C5 of the Control
Configuration 2 register (Address 19h) to 1.
where:
D = decimal equivalent of the binary code that is loaded to the
DAC register:
0 to 255 for ADT7518 (8 bits)
N = DAC resolution
Resistor String
FUNCTION DESCRIPTION—VOLTAGE OUTPUT
Digital-to-Analog Converters
The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of approximately 603 Ω. The digital
code loaded to the DAC register determines at which node on
the string the voltage is tapped off to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because it is a
string of resistors, it is guaranteed monotonic.
The ADT7518 has four resistor string DACs fabricated on a
CMOS process with resolutions of 12, 10, and 8 bits, respec-
tively. They contain four output buffer amplifiers and are
written to via I2C serial interface or SPI serial interface. See
the Serial Interface section for more information.
The ADT7518 operates from a single supply of 2.7 V to 5.5 V,
and the output buffer amplifiers provide rail-to-rail output
swing with a slew rate of 0.7 V/µs. All four DACs share a com-
mon reference input, VREF-IN. The reference input is buffered to
draw virtually no current from the reference source because it
offers the source a high impedance input. The devices have a
power-down mode in which all DACs may be turned off
completely with a high impedance output.
V
-IN
REF
REFERENCE
BUFFER
INT V
DAC
REF
GAIN MODE
(GAIN = 1 OR 2)
V
-A
OUT
INPUT
REGISTER
RESISTOR
STRING
REGISTER
Each DAC output will not be updated until it receives the
LDAC command. Therefore, while the DAC registers would
have been written to with a new value, this value will not be
represented by a voltage output until the DACs have received
the LDAC command. Reading back from any DAC register
prior to issuing an LDAC command will result in the digital
value that corresponds to the DAC output voltage. Thus, the
digital value written to the DAC register cannot be read back
until after the LDAC command has been initiated. This LDAC
OUTPUT BUFFER
AMPLIFIER
Figure 38. Single DAC Channel Architecture
R
R
TO OUTPUT
AMPLIFIER
R
command can be given by either pulling the
pin low
LDAC
(falling edge loads DACs), setting up Bits D4 and D5 of the
DAC configuration register (Address 1Bh), or using the LDAC
register (Address 1Ch).
R
R
When using the
pin to control the DAC register loading,
LDAC
the low going pulse width should be 20 ns minimum. The
pin has to go high and low again before the DAC
LDAC
Figure 39. Resistor String
registers can be reloaded.
V
-IN
REF
Digital-to-Analog Section
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the VREF-IN pin or the on-chip reference of 2.25 V provides
the reference voltage for the corresponding DAC. Figure 38
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
2.25V
INTERNAL V
REF
STRING
DAC A
STRING
DAC B
STRING
DAC C
VREF ×D
VOUT
=
2N
STRING
DAC D
Figure 40. DAC Reference Buffer Circuit
Rev. A | Page 18 of 40
ADT7518
DAC Reference Inputs
V
REF and this can be increased to 0 V to 2 VREF. Increasing the
There is an input reference pin for the DACs. This reference
input is buffered (see Figure 40).
output voltage span to 2 VREF can be done by setting D0 = 1 for
DAC A (internal temperature sensor) and D1 = 1 for DAC B
(external temperature sensor) in the DAC configuration register
(Address 1Bh).
The advantage with the buffered input is the high impedance it
presents to the voltage source driving it. The user can have an
external reference voltage as low as 1 V and as high as VDD. The
restriction of 1 V is due to the footroom of the reference buffer.
The output voltage is capable of tracking a maximum temp-
erature range of –128°C to +127°C, but the default setting is
–40°C to +127°C. If the output voltage range is 0 V to VREF-IN
(VREF-IN = 2.25 V), then this corresponds to 0 V representing
–40°C, and 1.48 V representing +127°C. This, of course, will
LDAC
The
configuration register controls the option to select
between internal and external voltage references. The default
setting is for external reference selected.
give an upper deadband between 1.48 V and VREF
.
Output Amplifier
The internal and external analog temperature offset registers
can be used to vary this upper deadband and, consequently, the
temperature that 0 V corresponds to. Table 6 and Table 7 give
examples of how this is done using a DAC output voltage span
of VREF and 2 VREF, respectively. Simply write in the temperature
value, in twos complement format, at which 0 V is to start. For
example, if using the DAC A output and 0 V to start at –40°C,
program D8h into the internal analog temperature offset reg-
ister (Address 21h). This is an 8-bit register and has a temp-
erature offset resolution of only 1°C for all device models. Use
the formulas following the tables to determine the value to
program into the offset registers.
The output buffer amplifier can generate output voltages to
within 1 mV of either rail. Its actual range depends on the value
of VREF, gain, and offset error.
If a gain of 1 is selected (Bits 0 to 3 of the DAC configuration
register = 0), the output range is 0.001 V to VREF
.
If a gain of 2 is selected (Bits 0 to 3 of the DAC configuration
register = 1), the output range is 0.001 V to 2 VREF. Because of
clamping, however, the maximum output is limited to VDD
0.001 V.
−
The output amplifier can drive a load of 4.7 kΩ to GND or VDD,
in parallel with 200 pF to GND or VDD (see Figure 5). The
source and sink capabilities of the output amplifier can be seen
in the plot of Figure 16.
Table 6. Thermal Voltage Output (0 V to VREF
)
O/P Voltage (V) Default °C
Max °C
–128
–71
–15
–1
Sample °C
0
+56
+113
+127
UDB∗
UDB∗
UDB∗
UDB∗
0
–40
0.5
1
1.12
1.47
1.5
2
+17
+73
+87
+127
UDB∗
UDB∗
UDB∗
The slew rate is 0.7 V/µs with a half-scale settling time to
0.5 LSB (at 8 bits) of 6 µs.
Thermal Voltage Output
+39
The ADT7518 can output voltages that are proportional to
temperature. DAC A output can be configured to represent the
temperature of the internal sensor while DAC B output can be
configured to represent the external temperature sensor. Bits C5
and C6 of the Control Configuration 3 register select the temp-
erature proportional output voltage. Each time a temperature
measurement is taken, the DAC output is updated. The output
resolution for the ADT7518 is 8 bits with a 1°C change corres-
ponding to 1 LSB change. The default output range is 0 V to
+42
+99
2.25
+127
∗ Upper deadband has been reached. DAC output is not capable of
increasing. See Figure 9.
V
DD
I
N × I
I
BIAS
OPTIONAL CAPACITOR, UP TO
3nF MAX. CAN BE ADDED TO
IMPROVE HIGH FREQUENCY
NOISE REJECTION IN NOISY
ENVIRONMENTS
V
OUT+
D+
REMOTE
C1
TO ADC
SENSING
TRANSISTOR
(2N3906)
D–
BIAS
DIODE
V
OUT–
LOW-PASS
FILTER
fC = 65kHz
Figure 41. Signal Conditioning for External Diode Temperature Sensor
Rev. A | Page 19 of 40
ADT7518
V
DD
I
N × I
I
BIAS
V
OUT+
TO ADC
INTERNAL
SENSE
TRANSISTOR
BIAS
DIODE
V
OUT–
Figure 42. Top Level Structure of Internal Temperature Sensor
Table 7. Thermal Voltage Output (0 V to 2 VREF
)
Example:
Offset Register Code (d) = 10d = 0Ah
O/P Voltage (V)
Default °C
Max °C
–128
–114
–100
–85
Sample °C
0
+14
+28
+43
+57
+63
+83
+85
+113
+127
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
0
–40
–26
+12
+3
The following equation is used to work out the various
temperatures for the corresponding 8-bit DAC output:
0.25
0.5
0.75
1
8- Bit Temp= DAC O / P ÷1LSB + 0V Temp
+17
–71
For example, if the output is 1.5 V, VREF-IN = 2.25 V, 8-bit DAC
has an LSB size = 2.25 V/256 = 8.79 x 10–3, and 0 V temperature
is at –128°C, then the resultant temperature is
1.12
1.47
1.5
2
+23
+43
+45
+73
–65
–45
–43
–15
1.5÷8.79×10−3
+ −128 = +43°C
( )
2.25
2.5
2.75
3
3.25
3.5
3.75
4
+88
0
Figure 43 shows a graph of the DAC output versus temperature
for a VREF-IN = 2.25 V.
+102
+116
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
UDB*
+14
+28
+42
+56
+70
+85
+99
+113
+127
2.25
2.10
1.95
0V = –128°C
1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0
0V = –40°C
4.25
4.5
* Upper deadband has been reached. DAC output is not capable of increasing.
See Figure 9.
0V = 0°C
Negative temperatures:
Offset Register Code
(d
)
=
0 V Temp
+128
–128–110 –90 –70 –50 –30 –10 10 30 50 70 90 110 127
where:
TEMPERATURE (°C)
D7 of Offset Register Code is set to 1 for negative temperatures.
Example:
Figure 43. DAC Output vs. Temperature VREF-IN = 2.25 V
FUNCTIONAL DESCRIPTION—ANALOG INPUTS
Single-Ended Inputs
Offset Register Code
d
=
(
−40
)
+128 = 88d = 58h
The ADT7518 offers four single-ended analog input channels.
The analog input range is from 0 V to 2.25 V, or 0 V to VDD. To
maintain the linearity specification, it is recommended that the
maximum VDD value be set at 5 V. Selection between the two
input ranges is done by Bit C4 of the Control Configuration 3
register (Address 1Ah). Setting this bit to 0 sets up the analog
input ADC reference to be sourced from the internal voltage
reference of 2.25 V. Setting the bit to 1 sets up the ADC
reference to be sourced from VDD.
Since a negative temperature has been inserted into the
equation, DB7 (MSB) of the offset register code is set to 1.
Therefore 58h becomes D8h.
58h + DB7(1) = D8h
Positive temperatures:
Offset Register Code (d) = 0 V Temp
Rev. A | Page 20 of 40
ADT7518
The ADC resolution is 10 bits and is mostly suitable for dc input
signals. Bits C1:2 of the Control Configuration 1 register
(Address 18h) are used to set up Pins 7 and 8 as AIN1 and
AIN2. Figure 44 shows the overall view of the 4-channel analog
input path.
ADC TRANSFER FUNCTION
The output coding of the ADT7518 analog inputs is straight
binary. The designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB). The LSB is
VDD/1024 or internal VREF/1024, internal VREF = 2.25 V. The ideal
transfer characteristic is shown in Figure 47.
M
U
L
T
I
AIN1
AIN2
AIN3
AIN4
TO ADC
VALUE
REGISTER
10-BIT
ADC
111...111
111...110
P
L
E
X
E
R
111...000
011...111
Figure 44. Quad Analog Input Path
1LSB = INT V
/1024
REF
1LSB = V /1024
DD
Converter Operation
000...010
000...001
000...000
The analog input channels use a successive approximation ADC
based on a capacitor DAC. Figure 45 and Figure 46 show
simplified schematics of the ADC. Figure 45 shows the ADC
during acquisition phase. SW2 is closed and SW1 is in position
A. The comparator is held in a balanced condition and the
sampling capacitor acquires the signal on AIN.
0V 1/2LSB
+V
– 1LSB
REF
ANALOG INPUT
Figure 47. Single-Ended Transfer Function
To work out the voltage on any analog input channel, the
following method can be used:
INT V
V
DD
REF
1 LSB = reference (v)/1024
REF
CAP DAC
SAMPLING
CAPACITOR
A
AIN
Convert the value read back from the AIN value register into a
decimal format.
SW1
B
ACQUISITION
PHASE
SW2
AIN voltage= AIN value(d)×LSB size
CONTROL
LOGIC
REF/2
COMPARATOR
d = decimal
Example:
Figure 45. ADC Acquisition Phase
INT V
REF
V
DD
Internal reference used. Therefore VREF = 2.25 V.
REF
CAP DAC
SAMPLING
AIN value = 512d
1LSB size =2.25V /1024 =2.197×10−3
CAPACITOR
A
AIN
SW1
B
CONVERSION
PHASE
AIN voltage =512×2.197×10−3 =1.125V
SW2
CONTROL
LOGIC
REF/2
Analog Input ESD Protection
COMPARATOR
Figure 48 shows the input structure on any of the analog input
pins that provides ESD protection. The diode provides the main
ESD protection for the analog inputs. Care must be taken that
the analog input signal never drops below the GND rail by
more than 200 mV. If this happens, the diode will become
forward-biased and start conducting current into the substrate.
The 4 pF capacitor is the typical pin capacitance and the resistor
is a lumped component made up of the on-resistance of the
multiplexer switch.
Figure 46. ADC Conversion Phase
When the ADC eventually goes into conversion phase (see
Figure 46), SW2 opens and SW1 moves to position B, causing
the comparator to become unbalanced. The control logic and
the DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 47 shows the ADC transfer function for the
analog inputs.
100Ω
AIN
4pF
Figure 48. Equivalent Analog Input ESD Circuit
Rev. A | Page 21 of 40
ADT7518
S/W RESET
INTERNAL
TEMP
INTERRUPT
STATUS
REGISTER
(TEMP AND
AIN1 TO AIN4)
EXTERNAL
TEMP
V
DD
WATCHDOG
LIMIT
COMPARISONS
INTERRUPT
MASK
REGISTERS
INT/INT
(LATCHED OUTPUT)
DIODE
FAULT
INTERRUPT
STATUS
REGISTER 2
(V
)
DD
AIN1–AIN4
INT/INT
ENABLE BIT
READ RESET
CONTROL
CONFIGURATION
REGISTER 1
Figure 49. Interrupt Structure
AIN Interrupts
The measured results from the temperature sensors are com-
pared with the internal and external THIGH, TLOW limits. These
temperature limits are stored in on-chip registers. If the temp-
erature limits are not masked, any out-of-limit comparisons
generate flags that are stored in the Interrupt Status 1 register.
The measured results from the AIN inputs are compared with
the AIN VHIGH (greater than comparison) and VLOW (less than or
equal to comparison) limits. An interrupt occurs if the AIN
inputs exceed or equal the limit registers. These voltage limits
are stored in on-chip registers. Note that the limit registers are
8 bits long while the AIN conversion result is 10 bits long. If the
voltage limits are not masked out, then any out-of-limit com-
parisons generate flags that are stored in the Interrupt Status 1
register (Address = 00h) and one or more out-of-limit results
One or more out-of-limit results will cause the INT/
output
INT
to pull either high or low depending on the output polarity
setting.
Theoretically, the temperature measuring circuit can measure
temperatures from –128°C to +127°C with a resolution of
0.25°C. However, temperatures outside TA are outside the
guaranteed operating temperature range of the device. Temp-
erature measurement from –128°C to +127°C is possible using
an external sensor.
will cause the INT/
output to pull either high or low
INT
depending on the output polarity setting. It is good design
practice to mask out interrupts for channels that are of no
concern to the application. Figure 49 shows the interrupt
structure for the ADT7518. It gives a block diagram
representation of how the various measurement channels affect
Temperature measurement is initiated by three methods. The
first method is applicable when the part is in single-channel
measurement mode. The temperature is measured 16 times and
internally averaged to reduce noise. In single-channel mode, the
part is continuously monitoring the selected channel, i.e., as
soon as one measurement is taken another one is started on the
same channel. The total time to measure a temperature channel
with the ADC operating at slow speed is typically 11.4 ms
(712 µs × 16) for the internal temperature sensor and 24.22 ms
(1.51 ms × 16) for the external temperature sensor. The new
temperature value is stored in two 8-bit registers and is ready
for reading by the I2C or SPI interface. The user has the option
of disabling the averaging by setting Bit 5 in the Control
Configuration 2 register (Address 19h). The ADT7518 defaults
on power-up with averaging enabled.
the INT/
pin.
INT
FUNCTIONAL DESCRIPTION—MEASUREMENT
Temperature Sensor
The ADT7518 contains an ADC with special input signal
conditioning to enable operation with external and on-chip
diode temperature sensors. When the ADT7518 is operating in
single-channel mode, the ADC continually processes the
measurement taken on one channel only. This channel is
preselected by Bits C0:C2 in the Control Configuration 2
register (Address 19h). When in round robin mode, the analog
input multiplexer sequentially selects the VDD input channel, the
on-chip temperature sensor to measure its internal temperature,
either the external temperature sensor or AIN1 and AIN2,
AIN3, and then AIN4. These signals are digitized by the ADC
and the results are stored in the various value registers.
Rev. A | Page 22 of 40
ADT7518
The second method is applicable when the part is in round
robin measurement mode. The part measures both the internal
and external temperature sensors as it cycles through all pos-
sible measurement channels. The two temperature channels are
measured each time the part runs a round robin sequence. In
round robin mode, the part continuously measures all channels.
Table 8. VDD Data Format (VREF = 2.25 V)
Digital Output
VDD Value (V)
Binary
Hex
18B
1B7
200
249
292
2DC
325
36E
3B7
3FF
2.7
3
3.5
4
4.5
5
5.5
6
01 1000 1011
01 1011 0111
10 0000 0000
10 0100 1001
10 1001 0010
10 1101 1100
11 0010 0101
11 0110 1110
11 1011 0111
11 1111 1111
Temperature measurement is also initiated after every read or
write to the part when the part is in either single-channel
measurement mode or round robin measurement mode.
Once serial communication has started, any conversion in
progress is stopped and the ADC is reset. Conversion starts
again immediately after the serial communication has finished.
The temperature measurement proceeds normally as described
in the preceding section.
6.5
7
On-Chip Reference
The ADT7518 has an on-chip 1.2 V band gap reference, which
is gained up by a switched capacitor amplifier to give an output
of 2.25 V. The amplifier is powered up for the duration of the
device monitoring phase and is powered down once monitoring
is disabled. This saves on current consumption. The internal
reference is used as the reference for the ADC. The ADC is used
for measuring VDD, internal temperature sensor, external temp-
erature sensor, and AIN inputs. The internal reference is always
used when measuring VDD, and the internal and external temp-
erature sensors. The external reference is the default power-up
reference for the DACs.
VDD Monitoring
The ADT7518 also has the ability to monitor its own power
supply. The part measures the voltage on its VDD pin to a
resolution of 10 bits. The resulting value is stored in two 8-bit
registers; the two LSBs are stored in register address 03h and the
eight MSBs are stored in Register Address 06h. This allows the
option of doing just a 1-byte read if 10-bit resolution is not
important. The measured result is compared with the VHIGH and
VLOW limits. If the VDD interrupt is not masked, any out-of-limit
comparison generates a flag in the Interrupt Status 2 register
Round Robin Measurement
and one or more out-of-limit results will cause the INT/
INT
output to pull either high or low, depending on the output
polarity setting.
On power-up, the ADT7518 goes into round robin mode but
monitoring is disabled. Setting Bit C0 of the Configuration
Register 1 to 1 enables conversions. It sequences through all the
available channels, taking a measurement from each in the
following order: VDD, internal temperature sensor, external
temperature sensor/(AIN1 and AIN2), AIN3, and AIN4. Pin 7
and Pin 8 can be configured to be either external temperature
sensor pins or standalone analog input pins. Once conversion is
completed on the AIN4 channel, the device loops around for
another measurement cycle. This method of taking a measure-
ment on all the channels in one cycle is called round robin.
Setting Bit C4 of Control Configuration 2 (Address 19h)
disables the round robin mode and in turn sets up the single-
channel mode. The single-channel mode is where only one
channel, e.g., the internal temperature sensor, is measured in
each conversion cycle.
Measuring the voltage on the VDD pin is regarded as monitoring
a channel along with the internal, external, and AIN channels.
The user can select the VDD channel for single-channel
measurement by setting Bit C4 = 1 and setting Bits C0:C2 to all
0s in the Control Configuration 2 register.
When measuring the VDD value, the reference for the ADC is
sourced from the internal reference. Table 8 shows the data
format. As the maximum VDD voltage measurable is 7 V, internal
scaling is performed on the VDD voltage to match the 2.25 V
internal reference value. Below is an example of how the
transfer function works.
V
DD = 5 V
ADC Reference = 2.25 V
1 LSB = ADC Reference/210
The time taken to monitor all channels will normally not be of
interest, since the most recently measured value can be read at
any time. For applications where the round robin time is impor-
tant, typical times at 25°C are given in the specifications.
= 2.25/1024
= 2.226 mV
Scale Factor = Full-Scale VCC/ADC Reference
= 7/2.25
= 3.07
Single-Channel Measurement
Setting C4 of the Control Configuration 2 register enables the
single-channel mode and allows the ADT7518 to focus on one
channel only. A channel is selected by writing to Bits C0:C2 in
the Control Configuration 2 register. For example, to select the
VDD channel for monitoring, write to the Control Configuration
Conversion Result = VDD/(Scale Factor × LSB size)
= 5/(3.07 × 2.226 mV)
= 2 DCh
Rev. A | Page 23 of 40
ADT7518
2 register and set C4 to 1 (if not done so already), then write all
0s to Bits C0:C2. All subsequent conversions will be done on the
VDD channel only. To change the channel selection to the inter-
nal temperature channel, write to the Control Configuration 2
register and set C0 = 1. When measuring in single-channel
mode, conversions on the channel selected occur directly after
each other. Any communication to the ADT7518 stops the
conversions, but they are restarted once the read or write
operation is completed.
To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to
ground, but is biased above ground by an internal diode at the
D– input. As the sensor is operating in a noisy environment, C1
is provided as a noise filter. See the Layout Considerations
section for more information on C1.
To measure ∆VBE, the sensor is switched between operating cur-
rents of I and N × I. The resulting waveform is passed through a
low-pass filter to remove noise, then to a chopper-stabilized
amplifier that performs the functions of amplification and recti-
fication of the waveform to produce a dc voltage proportional
to ∆VBE. This voltage is measured by the ADC to give a temper-
ature output in 10-bit twos complement format. To further
reduce the effects of noise, digital filtering is performed by
averaging the results of 16 measurement cycles.
Internal Temperature Measurement
The ADT7518 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip ADC. The
temperature data is stored in the Internal Temperature Value
register. Because both positive and negative temperatures can be
measured, the temperature data is stored in twos complement
format, as shown in Table 9. The thermal characteristics of the
measurement sensor could change and, therefore, an offset is
added to the measured value to enable the transfer function to
match the thermal characteristics. This offset is added before
the temperature data is stored. The offset value used is stored in
the internal temperature offset register.
Layout Considerations
Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particu-
larly when measuring the very small voltages from a remote
diode sensor. The following precautions should be taken:
1. Place the ADT7518 as close as possible to the remote
sensing diode. Provided that the worst noise sources such
as clock generators, data/address buses, and CRTs are
avoided, this distance can be 4 inches to 8 inches.
External Temperature Measurement
The ADT7518 can measure the temperature of one external
diode sensor or diode-connected transistor.
2. Route the D+ and D– tracks close together, in parallel, with
grounded guard tracks on each side. Provide a ground
plane under the tracks, if possible.
The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/°C. Unfortunately, because the
absolute value of VBE varies from device to device, and indivi-
dual calibration is required to null this out, the technique is
unsuitable for mass production.
3. Use wide tracks to minimize inductance and reduce noise
pickup. A 10 mil track minimum width and spacing is
recommended.
The technique used in the ADT7518 is to measure the change in
VBE when the device is operated at two different currents. This is
given by
GND
10 MIL
10 MIL
D+
D–
10 MIL
10 MIL
10 MIL
10 MIL
∆VBE = KT /q ×1n
(N )
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
GND
10 MIL
T is the absolute temperature in kelvins.
N is the ratio of the two currents.
Figure 50. Arrangement of Signal Tracks
Figure 41 shows the input signal conditioning used to measure
the output of an external temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for temp-
erature monitoring on some microprocessors, but it could
equally well be a discrete transistor.
4. Try to minimize the number of copper/solder joints, which
can cause thermocouple effects. Where copper/solder
joints are used, make sure that they are in both the D+ and
D– path and at the same temperature. Thermocouple
effects should not be a major problem because 1°C corres-
ponds to about 240 µV, and thermocouple voltages are
about 3 µV/°C of temperature difference. Unless there are
two thermocouples with a big temperature differential
between them, thermocouple voltages should be much less
than 200 mV.
If a discrete transistor is used, the collector is not grounded and
should be linked to the base. If a PNP transistor is used, the base
is connected to the D– input and the emitter to the D+ input. If
an NPN transistor is used, the emitter is connected to the D–
input and the base to the D+ input. A 2N3906 is recommended
as the external transistor.
Rev. A | Page 24 of 40
ADT7518
Interrupts
5. Place 0.1 µF bypass and 2,200 pF input filter capacitors
close to the ADT7518.
The measured results from the internal temperature sensor,
external temperature sensor, VDD pin, and AIN inputs are
compared with the THIGH/VHIGH (greater than comparison) and
TLOW/VLOW (less than or equal to comparison) limits. An inter-
rupt occurs if the measurement exceeds or equals the limit
registers. These limits are stored in on-chip registers. Note that
the limit registers are 8 bits long while the conversion results are
10 bits long. If the limits are not masked, any out-of-limit com-
parisons generate flags that are stored in the Interrupt Status 1
register (Address 00h) and Interrupt Status 2 register
6. If the distance to the remote sensor is more than 8 inches,
the use of twisted-pair cable is recommended. This will
work up to about 6 feet to 12 feet.
7. For long distances (up to 100 feet), use shielded twisted-
pair cable, such as Belden #8451 microphone cable.
Connect the twisted pair to D+ and D– and the shield to
GND close to the ADT7518. Leave the remote end of the
shield unconnected to avoid ground loops.
Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor may
be reduced or removed.
(Address 01h). One or more out-of-limit results will cause the
INT/
output to pull either high or low depending on the
INT
output polarity setting. It is good design practice to mask out
interrupts for channels that are of no concern to the application.
Cable resistance can also introduce errors. Series resistance of
1 Ω introduces about 0.5°C error.
Figure 49 shows the interrupt structure for the ADT7518. It
gives a block diagram representation of how the various
measurement channels affect the INT/
pin.
INT
Temperature Value Format
One LSB of the ADC corresponds to 0.25°C. The ADC can
theoretically measure a temperature span of 255°C. The internal
temperature sensor is guaranteed to a low value limit of –40°C.
It is possible to measure the full temperature span using the
external temperature sensor. The temperature data format is
shown in Table 9.
ADT7518 REGISTERS
The ADT7518 contains registers that are used to store the
results of external and internal temperature measurements, VDD
value measurements, analog input measurements, high and low
temperature limits, supply voltage and analog input limits, to set
output DAC voltage levels, to configure multipurpose pins, and
generally to control the device. A description of these registers
follows.
The result of the internal or external temperature measure-
ments is stored in the temperature value registers, and is com-
pared with limits programmed into the internal or external high
and low registers.
The register map is divided into registers of 8 bits. Each register
has its own individual address, but some consist of data that is
linked to other registers. These registers hold the 10-bit conver-
sion results of measurements taken on the temperature, VDD,
and AIN channels. For example, the eight MSBs of the VDD
measurement are stored in Register Address 06h, while the two
LSBs are stored in Register Address 03h. These types of registers
are linked such that when the LSB register is read first, the MSB
registers associated with that LSB register are locked to prevent
any updates. To unlock these MSB registers, the user has only to
read any one of them, which will have the effect of unlocking all
previously locked MSB registers. So, for the preceding example,
if Register 03h was read first, MSB Registers 06h and 07h would
be locked to prevent any updates to them. If Register 06h were
read, this register and Register 07h would be subsequently
unlocked.
Table 9. Temperature Data Format (Internal and External
Temperature)
Temperature
Digital Output
11 0110 0000
11 1001 1100
11 1101 1000
11 1111 1111
00 0000 0000
00 0000 0001
00 0010 1000
00 0110 0100
00 1100 1000
01 0010 1100
01 1001 0000
01 1010 0100
01 1111 0100
–40°C
–25°C
–10°C
–0.25°C
0°C
+0.25°C
+10°C
+25°C
+50°C
+75°C
+100°C
+105°C
+125°C
FIRST READ
COMMAND
LSB
REGISTER
OUTPUT
DATA
Temperature Conversion Formula:
Positive Temperature = ADC Code/4
Negative Temperature = (ADC Code* – 512)/4
*where DB9 is removed from the ADC code.
LOCK ASSOCIATED
MSB REGISTERS
Figure 51. Phase 1 of 10-Bit Read
Rev. A | Page 25 of 40
ADT7518
RD/WR
Address
Power-On
Default
SECOND READ
COMMAND
MSB
REGISTER
OUTPUT
DATA
Name
2Fh
AIN4 VHIGH Limit
AIN4 VLOW Limit
Reserved
FFh
00h
30h
UNLOCK ASSOCIATED
MSB REGISTERS
31h–4Ch
4Dh
Device ID
03h/0Bh/
07h
Figure 52. Phase 2 of 10-Bit Read
4Eh
Manufacturer’s ID
Silicon Revision
Reserved
41h
04h
00h
00h
00h
If an MSB register is read first, its corresponding LSB register is
not locked, leaving the user with the option of just reading back
8 bits (MSB) of a 10-bit conversion result. Reading an MSB
register first does not lock other MSB registers, and likewise
reading an LSB register first does not lock other LSB registers.
4Fh
50h–7Eh
7Fh
SPI Lock Status
Reserved
80h–FFh
Interrupt Status 1 Register (Read-Only) [Address = 00h]
Table 10. ADT7518 Registers
RD/WR
This 8-bit read-only register reflects the status of some of the
Power-On
Default
interrupts that can cause the INT/
pin to go active. This
INT
Address
Name
register is reset by a read operation, provided that any out-of-
limit event has been corrected. It is also reset by a software reset.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch–10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h–2Ah
2Bh
2Bh
2Ch
2Dh
2Eh
Interrupt Status 1
Interrupt Status 2
Reserved
00h
00h
Table 11. Interrupt Status 1 Register
Internal Temp and VDD LSBs
External Temp and AIN1 to AIN4 LSBs
Reserved
00h
00h
00h
xxh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
D8h
D8h
C7h
62h
64h
C9h
FFh
00h
D7
D6
D5
D4
D3
D2
D1
D0
0*
0*
0*
0*
0*
0*
0*
0*
*Default settings at power-up
VDD MSBs
Internal Temp MSBs
External Temp MSBs/AIN1 MSBs
AIN2 MSBs
Table 12.
Bit Function
D0 1 when the internal temperature value exceeds THIGH limit. Any
internal temperature reading greater than the set limit will
cause an out-of-limit event.
AIN3 MSBs
AIN4 MSBs
Reserved
D1 1 when internal temperature value exceeds TLOW limit. Any
internal temperature reading less than or equal to the set limit
will cause an out-of-limit event.
DAC A MSBs
Reserved
D2 This status bit is linked to the configuration of Pins 7 and 8. If
configured for the external temperature sensor, this bit is 1
when the external temperature value the exceeds THIGH limit.
The default value for this limit register is –1°C, so any external
temperature reading greater than the set limit will cause an
out-of-limit event. If configured for AIN1 and AIN2, this bit is 1
when AIN1 input voltage exceeds VHIGH or VLOW limits.
DAC B MSBs
Reserved
DAC C MSBs
Reserved
DAC D MSBs
Control Configuration 1
Control Configuration 2
Control Configuration 3
DAC Configuration
LDAC Configuration
Interrupt Mask 1
Interrupt Mask 2
Internal Temp Offset
External Temp Offset
Internal Analog Temp Offset
External Analog Temp Offset
VDD VHIGH Limit
D3 1 when external temperature value exceeds TLOW limit. The
default value for this limit register is 0°C, so any external
temperature reading less than or equal to the set limit will
cause an out-of-limit event.
D4 1 Indicates a fault (open or short) for the external temperature
sensor.
D5 1 when AIN2 voltage is greater than its corresponding VHIGH
limit. 1 when AIN2 voltage is less than or equal to its
corresponding VLOW limit.
D6 1 when AIN3 voltage is greater than its corresponding VHIGH
limit. 1 when AIN3 voltage is less than or equal to its
corresponding VLOW limit.
VDD VLOW Limit
D7 1 when AIN4 voltage is greater than its corresponding VHIGH
limit. 1 when AIN4 voltage is less than or equal to its
corresponding VLOW limit.
Internal THIGH Limit
Internal TLOW Limit
External THIGH/AIN1 VHIGH Limits
External TLOW/AIN1 VLOW Limits
Reserved
Interrupt Status 2 Register (Read-Only) [Address = 01h]
AIN2 VHIGH Limit
FFh
FFh
00h
FFh
00h
This 8-bit read-only register reflects the status of the VDD inter-
AIN2 VHIGH Limit
rupt that can cause the INT/
pin to go active. This register is
INT
AIN2 VLOW Limit
reset by a read operation, provided that any out-of-limit event
has been corrected. It is also reset by a software reset.
AIN3 VHIGH Limit
AIN3 VLOW Limit
Rev. A | Page 26 of 40
ADT7518
VDD Value Register MSBs (Read-Only) [Address = 6h]
Table 13. Interrupt Status 2 Register
D7
D6
D5
D4
D3
D2
D1
D0
This 8-bit read-only register stores the supply voltage value. The
eight MSBs of the 10-bit value are stored in this register.
N/A
N/A
N/A
0*
N/A
N/A
N/A
N/A
*Default settings at power-up.
Table 19. VDD Value MSBs
D7
V9
x*
D6
V8
x*
D5
V7
x*
D4
V6
x*
D3
V5
x*
D2
V4
x*
D1
V3
x*
D0
V2
x*
Table 14.
Bit Function
D4 1 when VDD value is greater than its corresponding VHIGH
limit. 1 when VDD is less than or equal to its corresponding
*Loaded with VDD value after power-up.
V
LOW limit.
Internal Temperature Value Register MSBs (Read-Only)
[Address = 07h]
Internal Temperature Value/VDD Value Register LSBs (Read-
Only) [Address = 03h]
This 8-bit read-only register stores the internal temperature
value from the internal temperature sensor in twos complement
format. The eight MSBs of the 10-bit value are stored in this
register.
This 8-bit read-only register stores the two LSBs of the 10-bit
temperature reading from the internal temperature sensor and
the two LSBs of the 10-bit supply voltage reading.
Table 15. Internal Temperature/VDD LSBs
Table 20. Internal Temperature Value MSBs
D7
D6
D5
D4
D3
V1
0*
D2
LSB
0*
D1
T1
0*
D0
LSB
0*
D7
T9
0*
D6
T8
0*
D5
T7
0*
D4
T6
0*
D3
T5
0*
D2
T4
0*
D1
T3
0*
D0
T2
0*
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
*Default settings at power-up
*Default settings at power-up
External Temperature Value or Analog Input AIN1 Register
MSBs (Read-Only) [Address = 08h]
Table 16.
Bit
D0
D1
D2
D3
Function
This 8-bit read-only register stores, if selected, the external
temperature value or the analog input AIN1 value. Selection is
done in the Control Configuration 1 register. The external
temperature value is stored in twos complement format. The
eight MSBs of the 10-bit value are stored in this register.
LSB of Internal Temperature Value
B1 of Internal Temperature Value
LSB of VDD Value
B1 of VDD Value
External Temperature Value and Analog Inputs 1 to 4
Register LSBs (Read-Only) [Address = 04h]
Table 21. External Temperature Value/Analog Inputs MSBs
D7
D6
D5
D4
D3
D2
D1
D0
This is an 8-bit read-only register. Bits D2:D7 store the two LSBs
of the analog inputs AIN2 to AIN4. Bits D0:D1 store the two
LSBs of either the external temperature value or AIN1 input
value. The type of input for D0 and D1 is selected by Bits C1:C2
of the Control Configuration Register 1.
T/A9
0*
T/A8
0*
T/A7
0*
T/A6
0*
T/A5
0*
T/A4
0*
T/A3
0*
T/A2
0*
*Default settings at power-up
AIN2 Register MSBs (Read) [Address = 09h]
This 8-bit read register contains the eight MSBs of the AIN2
analog input voltage word. The value in this register is com-
bined with Bits D2:3 of the external temperature value and
Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full
10-bit conversion result of the analog value on the AIN2 pin.
Table 17. External Temperature and AIN1 to AIN4 LSBs
D7
A4
0*
D6
D5
A3
0*
D4
D3
A2
0*
D2
D1
T/A
0*
D0
A4LSB
0*
A3LSB
0*
A2LSB
0*
T/ALSB
0*
*Default settings at power-up
Table 22. AIN2 MSBs
Table 18.
D7
MSB
0*
D6
A8
0*
D5
A7
0*
D4
A6
0*
D3
A5
0*
D2
A4
0*
D1
A3
0*
D0
A2
0*
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Function
LSB of External Temperature Value or AIN1 Value
Bit 1 of External Temperature Value or AIN1 Value
LSB of AIN2 Value
Bit 1 of AIN2 Value
LSB of AIN3 Value
Bit 1 of AIN3 Value
LSB of AIN4 Value
Bit 1 of AIN4 Value
*Default settings at power-up
AIN3 Register MSBs (Read) [Address = 0Ah]
This 8-bit read register contains the eight MSBs of the AIN3
analog input voltage word. The value in this register is com-
bined with Bits D4:5 of the external temperature value and
Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full
10-bit conversion result of the analog value on the AIN3 pin.
Rev. A | Page 27 of 40
ADT7518
Table 23. AIN3 MSBs
Table 26. DAC B
D7
MSB
0*
D6
A8
0*
D5
A7
0*
D4
A6
0*
D3
A5
0*
D2
A4
0*
D1
A3
0*
D0
A2
0*
D7
MSB
0*
D6
B8
0*
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
*Default settings at power-up
*Default settings at power-up
DAC C Register (Read/Write) [Address = 15h]
AIN4 Register MSBs (Read) [Address = 0Bh]
This 8-bit read/write register contains the eight bits of the DAC
C word. The value in this register is converted to an analog
voltage on the VOUT-C pin. On power-up, the voltage output on
the VOUT-C pin is 0 V.
This 8-bit read register contains the eight MSBs of the AIN4
analog input voltage word. The value in this register is com-
bined with Bits D6:7 of the external temperature value and
Analog Inputs 1 to 4 register LSBs, Address 04h, to give the full
10-bit conversion result of the analog value on the AIN4 pin.
Table 27. DAC C
D7
MSB B8
0* 0*
D6
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
Table 24. AIN4 MSBs
D7
MSB
0*
D6
A8
0*
D5
A7
0*
D4
A6
0*
D3
A5
0*
D2
A4
0*
D1
A3
0*
D0
A2
0*
*Default settings at power-up
*Default settings at power-up
DAC D Register (Read/Write) [Address = 17h]
DAC A Register (Read/Write) [Address = 11h]
This 8-bit read/write register contains the eight bits of the DAC
D word. The value in this register is converted to an analog
voltage on the VOUT-D pin. On power-up, the voltage output on
the VOUT-D pin is 0 V.
This 8-bit read/write register contains the eight bits of the DAC
A word. The value in this register is converted to an analog
voltage on the VOUT-A pin. On power-up, the voltage output on
the VOUT-A pin is 0 V.
Table 28. DAC D
Table 25. DAC A
D7
MSB
0*
D6
B8
0*
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
D7
MSB
0*
D6
B8
0*
D5
B7
0*
D4
B6
0*
D3
B5
0*
D2
B4
0*
D1
B3
0*
D0
B2
0*
*Default settings at power-up
*Default settings at power-up
Control Configuration 1 Register (Read/Write)
[Address = 18h]
DAC B Register (Read/Write) [Address = 13h]
This 8-bit read/write register contains the eight bits of the DAC
B word. The value in this register is converted to an analog
voltage on the VOUT-B pin. On power-up, the voltage output on
the VOUT-B pin is 0 V.
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7518.
Table 29. Control Configuration 1
D7
PD
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
*Default settings at power-up
Rev. A | Page 28 of 40
ADT7518
Table 30.
Bit
Function
Bit
Function
101 = AIN4.
C0
This bit enables/disables conversions in round robin
and single-channel mode. ADT7518 powers up in round
robin mode but monitoring is not initiated until this bit
is set. The default = 0.
0 = Stop monitoring.
1 = Start monitoring.
110–111 = Reserved.
Reserved.
C3
C4
Selects between single-channel and round robin conver-
sion cycle. The default is round robin.
0 = Round robin.
1 = Single channel.
C2:C1 Selects between the two different analog inputs on Pins
7 and 8. ADT7518 powers up with AIN1 and AIN2
selected.
C5
Default condition is to average every measurement on all
channels 16 times. This bit disables this averaging.
Channels affected are temperature, analog inputs, and
VDD.
0 = Enable averaging.
1 = Disable averaging.
00 = AIN1 and AIN2 selected.
01 = Undefined.
10 = External TDM selected.
11 = Undefined.
C6
C7
SMBus timeout on the serial clock puts a 25 ms limit on
the pulse width of the clock, ensuring that a fault on the
master SCL does not lock up the SDA line.
0 = Disable SMBus timeout.
1 = Enable SMBus timeout.
C3
Selects between digital (LDAC) and analog inputs (AIN3)
on Pin 9. When AIN3 is selected, Bit C3 of the Control
Configuration 3 register is masked and has no effect
until LDAC is selected as the input on Pin 9.
0 = LDAC selected.
1 = AIN3 selected.
Software Reset. Setting this bit to 1 causes a software
reset. All registers and DAC outputs will reset to their
default settings.
C4
C5
Reserved. Write 0 only.
0 = Enable INT/INT output.
1 = Disable INT/INT output.
Control Configuration 3 Register (Read/Write)
[Address = 1Ah]
C6
PD
Configures INT/INT output polarity.
0 = Active low.
1 = Active high.
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7518.
Power-Down Bit. Setting this bit to 1 puts the ADT7518
into standby mode. In this mode, both ADC and DACs
are fully powered down, but the serial interface is still
operational. To power up the part again, just write 0 to
this bit.
Table 33. Control Configuration 3
D7
C7
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
*Default settings at power-up
Control Configuration 2 Register (Read/Write)
[Address = 19h]
Table 34.
Bit
Function
This configuration register is an 8-bit read/write register that is
used to set up some of the operating modes of the ADT7518.
C0
Selects between fast and slow ADC conversion speeds.
0 = ADC clock at 1.4 kHz.
Table 31. Control Configuration 2
1 = ADC clock at 22.5 kHz. D+ and D– analog filters are
disabled.
D7
C7
0*
D6
C6
0*
D5
C5
0*
D4
C4
0*
D3
C3
0*
D2
C2
0*
D1
C1
0*
D0
C0
0*
C2:1 Reserved. Write 0 only.
C3
0 = LDAC pin controls updating of DAC outputs.
1 = DAC configuration register and LDAC configuration
register control updating of DAC outputs.
* Default settings at power-up
Table 32.
C4
Selects the ADC reference to be either internal VREF or VDD
for analog inputs.
Bit
Function
C2:0 In single-channel mode, these bits select between VDD,
the internal temperature sensor, external temperature
sensor/AIN1, AIN2, AIN3, and AIN4 for conversion. The
default is VDD.
0 = Internal VREF.
1 = VDD.
C5
C6
C7
Setting this bit selects DAC A voltage output to be
proportional to the internal temperature measurement.
000 = VDD.
001 = Internal temperature sensor.
010 = External temperature sensor/AIN1. (Bits C1:C2 of
the Control Configuration 1 register affect this selection).
Setting this bit selects DAC B voltage output to be
proportional to the external temperature measurement.
Reserved. Write 0 only.
011 = AIN2.
100 = AIN3.
Rev. A | Page 29 of 40
ADT7518
DAC Configuration Register (Read/Write)
[Address = 1Bh]
Table 38.
Bit
Function
This configuration register is an 8-bit read/write register that is
used to control the output ranges of all four DACs and also to
D0
Writing a 1 to this bit will generate the LDAC command
to update DAC A output only.
D1
D2
D3
D4
Writing a 1 to this bit will generate the LDAC command
to update DAC B output only.
LDAC
control the loading of the DAC registers if the
pin is
disabled (Bit C3 = 1, Control Configuration 3 register).
Writing a 1 to this bit will generate the LDAC command
to update DAC C output only.
Table 35. DAC Configuration
Writing a 1 to this bit will generate the LDAC command
to update DAC D output only.
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Selects either internal VREF or external VREF for DACs A
and B.
0 = External VREF
* Default settings at power-up
Table 36.
1 = Internal VREF
.
Bit
Function
Selects the output range of DAC A.
0 = 0 V to VREF
1 = 0 V to 2VREF
Selects the output range of DAC B.
0 = 0 V to VREF
1 = 0 V to 2VREF
Selects the output range of DAC C.
0 = 0 V to VREF
1 = 0 V to 2VREF
Selects the output range of DAC D.
0 = 0 V to VREF
1 = 0 V to 2VREF
D5
Selects either internal VREF or external VREF for DACs C
and D.
0 = External VREF
1 = Internal VREF
D0
.
.
D1
D2
D3
D6:D7 Reserved. Write 0s only.
.
Interrupt Mask 1 Register (Read/Write) [Address = 1Dh]
.
This mask register is an 8-bit read/write register that can be
used to mask any interrupts that can cause the INT/
go active.
pin to
INT
.
.
Table 39. Interrupt Mask 1
.
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D0
D0
0*
.
D1
0*
D5:D4 00 = A write to any DAC register generates LDAC
command that updates that DAC only.
01 = A write to DAC B or DAC D register generates
LDAC command that updates DACs A, B or DACs C, D,
respectively.
* Default settings at power-up
Table 40.
10 = A write to DAC D register generates LDAC
command that updates all four DACs.
11 = LDAC command generated from LDAC register.
Bit Function
D0 0 = Enable internal THIGH interrupt.
1 = Disable internal THIGH interrupt.
D1 0 = Enable internal TLOW interrupt.
1 = Disable internal TLOW interrupt.
D6:D7 Reserved. Write 0s only.
LDAC Configuration Register (Write-Only)
[Address = 1Ch]
D2 0 = Enable external THIGH interrupt or AIN1 interrupt.
1 = Disable external THIGH interrupt or AIN1 interrupt.
D3 0 = Enable external TLOW interrupt.
1 = Disable external TLOW interrupt.
This configuration register is an 8-bit write register that is used
to control the updating of the quad DAC outputs if the
pin is disabled and Bits D4:D5 of the DAC configuration reg-
ister are both set to 1. Also selects either the internal or external
VREF for all four DACs. Bits D0:D3 in this register are self-clear-
ing, i.e., reading back from this register will always give 0s for
these bits.
LDAC
D4 0 = Enable external temperature fault interrupt..
1 = Disable external temperature fault interrupt.
D5 0 = Enable AIN2 interrupt.
1 = Disable AIN2 interrupt.
D6 0 = Enable AIN3 interrupt.
1 = Disable AIN3 interrupt.
Table 37. LDAC Configuration
D7 0 = Enable AIN4 interrupt.
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
1 = Disable AIN4 interrupt.
* Default settings at power-up
Rev. A | Page 30 of 40
ADT7518
Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]
Internal Analog Temperature Offset Register (Read/Write)
[Address = 21h]
This mask register is an 8-bit read/write register that can be
This register contains the offset value for the internal thermal
voltage output. A twos complement number can be written to
this register, which is then added to the measured result before
it is converted by DAC A. Varying the value in this register has
the effect of varying the temperature span. For example, the
output voltage can represent a temperature span of –128°C to
+127°C or even 0°C to +127°C. In essence, this register changes
the position of 0 V on the temperature scale. Temperatures
other than –128°C to +127°C will produce an upper deadband
on the DAC A output. Because it is an 8-bit register, the
temperature resolution is 1°C. The default value is –40°C.
used to mask any interrupts that can cause the INT/
go active.
pin to
INT
Table 41. Interrupt Mask 2
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D0
D0
0*
D1
0*
* Default settings at power-up
Table 42.
Bit
Function
D0:D3
D4
Reserved. Write 0s only.
0 = Enable VDD interrupts.
1 = Disable VDD interrupts.
Table 45. Internal Analog Temperature Offset
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
1*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D5:D7
Reserved. Write 0s only.
Internal Temperature Offset Register (Read/Write)
[Address = 1Fh]
* Default settings at power-up
This register contains the offset value for the internal temp-
erature channel. A twos complement number can be written to
this register which is then added to the measured result before it
is stored or compared to limits. In this way, a one-point cali-
bration can be done whereby the whole transfer function of the
channel can be moved up or down. From a software point of
view, this may be a very simple method to vary the charac-
teristics of the measurement channel if the thermal charac-
teristics change. Because it is an 8-bit register, the temperature
resolution is 1°C.
External Analog Temperature Offset Register (Read/Write)
[Address = 22h]
This register contains the offset value for the external thermal
voltage output. A twos complement number can be written to
this register which is then added to the measured result before it
is converted by DAC B. Varying the value in this register has the
effect of varying the temperature span. For example, the output
voltage can represent a temperature span of –128°C to +127°C
or even 0°C to +127°C. In essence, this register changes the
position of 0 V on the temperature scale. Temperatures other
than –128°C to +127°C will produce an upper deadband on the
DAC B output. Because it is an 8-bit register, the temperature
resolution is 1°C. The default value is –40°C.
Table 43. Internal Temperature Offset
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
Table 46. External Analog Temperature Offset
* Default settings at power-up
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
1*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
0*
External Temperature Offset Register (Read/Write)
[Address = 20h]
This register contains the offset value for the external temp-
erature channel. A twos complement number can be written to
this register, which is then added to the measured result before
it is stored or compared to limits. In this way, a one-point cali-
bration can be done whereby the whole transfer function of the
channel can be moved up or down. From a software point of
view, this may be a very simple method to vary the charac-
teristics of the measurement channel if the thermal charac-
teristics change. Because it is an 8-bit register, the temperature
resolution is 1°C.
* Default settings at power-up
VDD VHIGH Limit Register (Read/Write) [Address = 23h]
This limit register is an 8-bit read/write register that stores the
VDD upper limit, which will cause an interrupt and activate the
INT/
VDD value has to be greater than the value in this register. The
default value is 5.46 V.
output (if enabled). For this to happen, the measured
INT
Table 47. VDD VHIGH Limit
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
1*
D1
D1
1*
D0
D0
1*
Table 44. External Temperature Offset
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
* Default settings at power-up
* Default settings at power-up
Rev. A | Page 31 of 40
ADT7518
VDD VLOW Limit Register (Read/Write) [Address = 24h]
input upper limit, which will cause an interrupt and activate the
INT/ output (if enabled). For this to happen, the measured
INT
This limit register is an 8-bit read/write register that stores the
VDD lower limit, which will cause an interrupt and activate the
AIN1 value has to be greater than the value in this register.
Because it is an 8-bit register, the resolution is four times less
than the resolution of the 10-bit ADC. Because the power-up
default settings for Pins 7 and 8 are AIN1 and AIN2 inputs, the
default value for this limit register is full-scale voltage.
INT/
output (if enabled). For this to happen, the measured
INT
VDD value has to be less than or equal to the value in this
register. The default value is 2.7 V.
Table 48. VDD VLOW Limit
D7
D7
0*
D6
D6
1*
D5
D5
1*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
1*
D0
D0
0*
Table 51. AIN1 VHIGH Limit
D7
D7
1*
D6
D6
1*
D5
D5
1*
D4
D4
1*
D3
D3
1*
D2
D2
1*
D1
D1
1*
D0
D0
1*
* Default settings at power-up
Internal THIGH Limit Register (Read/Write) [Address = 25h]
* Default settings at power-up
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature upper limit,
External TLOW/AIN1 VLOW Limit Register (Read/Write)
[Address = 28h]
which will cause an interrupt and activate the INT/
output
INT
If Pins 7 and 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature lower
(if enabled). For this to happen, the measured internal temp-
erature value has to be greater than the value in this register.
Because it is an 8-bit register, the temperature resolution is 1°C.
The default value is +100°C.
limit, which will cause an interrupt and activate the INT/
INT
output (if enabled). For this to happen, the measured external
temperature value has to be more negative than or equal to the
value in this register. Because it is an 8-bit register, the temp-
erature resolution is 1°C. The default value is 0°C.
Table 49. Internal THIGH Limit
D7
D7
0*
D6
D6
1*
D5
D5
1*
D4
D4
0*
D3
D3
0*
D2
D2
1*
D1
D1
0*
D0
D0
0*
If Pins 7 and 8 are configured for AIN1 and AIN2 inputs, this
limit register is an 8-bit read/write register that stores the AIN1
input lower limit, which will cause an interrupt and activate the
* Default settings at power-up
Internal TLOW Limit Register (Read/Write) [Address = 26h]
This limit register is an 8-bit read/write register that stores the
twos complement of the internal temperature lower limit, which
INT/
output (if enabled). For this to happen, the measured
INT
AIN1 value has to be less than or equal to the value in this reg-
ister. As it is an 8-bit register, the resolution is four times less
than the resolution of the 10-bit ADC. Because the power-up
default settings for Pins 7 and 8 are AIN1 and AIN2 inputs, the
default value for this limit register is 0 V.
will cause an interrupt and activate the INT/
output (if
INT
enabled). For this to happen, the measured internal temperature
value has to be more negative than or equal to the value in this
register. Because it is an 8-bit register, the temperature reso-
lution is 1°C. The default value is –55°C.
Table 52. AIN1 VLOW Limit
Table 50. Internal TLOW Limit
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
D7
D7
1*
D6
D6
1*
D5
D5
0*
D4
D4
0*
D3
D3
1*
D2
D2
0*
D1
D1
0*
D0
D0
1*
* Default settings at power-up
* Default settings at power-up
AIN2 VHIGH Limit Register (Read/Write) [Address = 2Bh]
External THIGH/AIN1 VHIGH Limit Register (Read/Write)
[Address = 27h]
This limit register is an 8-bit read/write register that stores the
AIN2 input upper limit, which will cause an interrupt and acti-
If Pins 7 and 8 are configured for the external temperature
sensor, this limit register is an 8-bit read/write register that
stores the twos complement of the external temperature upper
limit, which will cause an interrupt and activate the INT/
output (if enabled). For this to happen, the measured external
temperature value has to be greater than the value in this reg-
ister. Because it is an 8-bit register, the temperature resolution is
1°C. The default value is –1°C.
vate the INT/
output (if enabled). For this to happen, the
INT
measured AIN2 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
INT
Table 53. AIN2 VHIGH Limit
D7
D7
1*
D6
D6
1*
D5
D5
1*
D4
D4
1*
D3
D3
1*
D2
D2
1*
D1
D1
1*
D0
D0
1*
If Pins 7 and 8 are configured for AIN1 and AIN2 inputs, this
limit register is an 8-bit read/write register that stores the AIN1
* Default settings at power-up
Rev. A | Page 32 of 40
ADT7518
AIN2 VLOW Limit Register (Read/Write) [Address = 2Ch]
Table 57. AIN4 VHIGH Limit
D7
D7
1*
D6
D6
1*
D5
D5
1*
D4
D4
1*
D3
D3
1*
D2
D2
1*
D1
D1
1*
D0
D0
1*
This limit register is an 8-bit read/write register that stores the
AIN2 input lower limit, which will cause an interrupt and acti-
vate the INT/
output (if enabled). For this to happen, the
INT
* Default settings at power-up
AIN4 VLOW Limit Register (Read/Write) [Address = 30h]
measured AIN2 value has to be less than or equal to the value in
this register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is 0 V.
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit, which will cause an interrupt and
activate the INT/
the measured AIN4 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
output (if enabled). For this to happen,
INT
Table 54. AIN2 VLOW Limit
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
* Default settings at power-up
Table 58. AIN4 VLOW Limit
AIN3 VHIGH Limit Register (Read/Write) [Address = 2Dh]
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
This limit register is an 8-bit read/write register that stores the
AIN3 input upper limit, which will cause an interrupt and acti-
* Default settings at power-up
Device ID Register (Read-Only) [Address = 4Dh]
vate the INT/
output (if enabled). For this to happen, the
INT
measured AIN3 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
This 8-bit read-only register contains a device identifier byte:
ADT7518 = 0Bh.
Manufacturer’s ID Register (Read-Only) [Address = 4Eh]
This register contains the manufacturer’s identification number.
ADI’s ID number is 41h.
Table 55. AIN3 VHIGH Limit
D7
D7
1*
D6
D6
1*
D5
D5
1*
D4
D4
1*
D3
D3
1*
D2
D2
1*
D1
D1
1*
D0
D0
1*
Silicon Revision Register (Read-Only) [Address = 4Fh]
This register is divided into four LSBs representing the stepping
and the four MSBs representing the version. The stepping con-
tains the manufacturer’s code for minor revisions or steppings
to the silicon. The version is the ADT7518 version number.
* Default settings at power-up
AIN3 VLOW Limit Register (Read/Write) [Address = 2Eh]
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit, which will cause an interrupt and
SPI Lock Status Register (Read-Only) [Address = 7Fh]
activate the INT/
output (if enabled). For this to happen,
INT
Bit D0 (LSB) of this read-only register indicates whether or not
the SPI interface is locked. Writing to this register will cause the
device to malfunction. The default value is 00h.
0 = I2C interface.
the measured AIN3 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
1 = SPI interface selected and locked.
Table 56. AIN3 VLOW Limit
SERIAL INTERFACE
D7
D7
0*
D6
D6
0*
D5
D5
0*
D4
D4
0*
D3
D3
0*
D2
D2
0*
D1
D1
0*
D0
D0
0*
There are two serial interfaces that can be used on this part: I2C
and SPI. The device will power up with the serial interface in
I2C mode, but it is not locked into this mode. To stay in I2C
* Default settings at power-up
AIN4 VHIGH Limit Register (Read/Write) [Address = 2Fh]
mode, it is recommended that the user tie the
line to either
CS
VCC or GND. It is not possible to lock the I2C mode, but it is
possible to select and lock the SPI mode.
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit, which will cause an interrupt and acti-
vate the INT/
output (if enabled). For this to happen, the
INT
measured AIN4 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Rev. A | Page 33 of 40
ADT7518
A
B
C
CS
(START HIGH)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
A
B
C
CS
(START LOW)
SPI LOCKED ON
THIRD RISING EDGE
SPI FRAMING
EDGE
Figure 53. Serial Interface—Selecting and Locking SPI Protocol
To select and lock the interface into the SPI mode, a number of
pulses must be sent down the line (Pin 4). The following
ADT7518
LOCK AND
SELECT SPI
CS
section describes how this is done.
CS
V
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI lock status register (Address 7Fh) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and
power it up again. A software reset does not reset the serial
interface.
DD
SPI FRAMING
EDGE
820
Ω
820
Ω
820Ω
DIN
SCLK
DOUT
Figure 55. Typical SPI Interface Connection
I2C Serial Interface
Serial Interface Selection
The
line controls the selection between I2C and SPI.
CS
Like all I2C-compatible devices, the ADT7518 has a 7-bit serial
address. The four MSBs of this address for the ADT7518 are set
to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin
can be configured three ways to give three different address
options: low, floating, and high. Setting the ADD pin low gives a
serial bus address of 1001 000, leaving it floating gives the
address 1001 010, and setting it high gives the address 1001 011.
The recommended pull-up resistor value is 10 kΩ.
Figure 53 shows the selection process necessary to lock the SPI
interface mode.
To communicate to the ADT7518 using the SPI protocol, send
three pulses down the
third rising edge (marked as C in Figure 53), the part selects and
locks the SPI interface. The user is now limited to communi-
cating to the device using the SPI protocol.
line as shown in Figure 53. On the
CS
There is an enable/disable bit for the SMBus timeout. When this
is enabled, the SMBus will time out after 25 ms of no activity. To
enable it, set Bit 6 of the Control Configuration 2 register. The
power-on default is with the SMBus timeout disabled.
As per most SPI standards, the CS line must be low during
every SPI communication to the ADT7518 and high all other
times. Typical examples of how to connect the dual interface as
I2C or SPI is shown in Figure 54 and Figure 55. The following
sections describe in detail how to use the I2C and SPI protocols
associated with the ADT7518.
The ADT7518 supports SMBus packet error checking (PEC),
but its use is optional. It is triggered by supplying the extra
clocks for the PEC byte. The PEC is calculated using CRC-8.
The frame clock sequence (FCS) conforms to CRC-8 by the
polynominal
V
V
DD
DD
ADT7518
10kΩ
10kΩ
CS
C x
( )
= x8 + x2 + x1 +1
SDA
SCL
Consult the SMBus specification (www.smbus.org) for more
information.
2
I C ADDRESS = 1001 000
ADD
Figure 54. Typical I2C Interface Connection
Rev. A | Page 34 of 40
ADT7518
Writing to the Address Pointer Register for a
Subsequent Read
The serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of
To read data from a particular register, the address pointer
register must contain the address of that register. If it does not,
the correct address must be written to the address pointer
register by performing a single-byte write operation, as shown
in Figure 56. The write operation consists of the serial bus
address followed by the address pointer byte. No data is written
to any of the data registers. A read operation is then performed
to read the register.
a 7-bit address (MSB first) plus an R/ bit, which deter-
W
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
Writing Data to a Register
All registers are 8-bit registers, so only one byte of data can be
written to each register. Writing a single byte of data to one of
these read/write registers consists of the serial bus address, the
data register address written to the address pointer register,
followed by the data byte written to the selected data register.
This is illustrated in Figure 57. To write to a different register,
another start or repeated start is required. If more than one byte
of data is sent in one communication operation, the addressed
register will repeatedly load until the last data byte is sent.
The peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/ bit is 0 the master will write to
W
the slave device. If the R/ bit is 1, the master will read
W
from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low to high transition
when the clock is high may be interpreted as a stop signal.
Reading Data from the ADT7518
Reading data from the ADT7518 is done in a 1-byte operation.
Reading back the contents of a register is shown in Figure 58.
The register address had previously been set up by a single-byte
write operation to the address pointer register. To read from
another register, write to the address pointer register again to set
up the relevant register address. Thus, block reads are not
possible, i.e., no I2C autoincrement.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master will
pull the data line high during the 10th clock pulse to assert
a stop condition. In read mode, the master device will pull
the data line high during the low period before the ninth
clock pulse. This is known as No Acknowledge. The master
will then take the data line low during the low period
before the 10th clock pulse, and then high during the 10th
clock pulse to assert a stop condition.
SPI Serial Interface
The SPI serial interface of the ADT7518 consists of four wires:
, SCLK, DIN, and DOUT. The
line is used to select the
CS
device when more than one device is connected to the serial
clock and data lines. The line is also used to distinguish
CS
CS
between any two separate serial communications (see Figure 63
for a graphical explanation). The SCLK line is used to clock data
in and out of the part. The DIN line is used to write to the regis-
ters, and the DOUT line is used to read data back from the
registers. The recommended pull-up resistor value is between
500 Ω and 820 Ω.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.
The part operates in slave mode and requires an externally
applied serial clock to the SCLK input. The serial interface is
designed to allow the part to be interfaced to systems that
provide a serial clock that is synchronized to the serial data.
The I2C address set up by the ADD pin is not latched by the
device until after this address has been sent twice. On the eighth
SCL cycle of the second valid communication, the serial bus
address is latched in. This is the SCL cycle directly after the
device has seen its own I2C serial bus address. Any subsequent
changes on this pin will have no effect on the I2C serial bus
address.
There are two types of serial operations, read and write. Com-
mand words are used to distinguish read operations from write
operations. These command words are given in Table 59.
Address autoincrement is possible in SPI mode.
Writing to the ADT7518
Table 59. SPI Command Words
Depending on the register being written to, there are two
different writes for the ADT7518. It is not possible to do a block
write to this part, i.e., no I2C autoincrement.
Write
Read
90h (1001 0000)
91h (1001 0001)
Rev. A | Page 35 of 40
ADT7518
1
9
1
9
SCL
1
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
SDA
ACK. BY
ADT7518
START BY
MASTER
ACK. BY
ADT7518
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 56. I2C—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
1
1
9
1
9
SCL
SDA
0
0
1
A2
A1
A0
P7
P6
P5
P4
P3
P2
P1
P0
R/W
START BY
MASTER
ACK. BY
ADT7518
ACK. BY
ADT7518
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7518
STOP BY
MASTER
FRAME 3
DATA BYTE
Figure 57. I2C—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
1
9
1
9
SCL
SDA
1
0
0
1
A2
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADT7518
START BY
MASTER
NO ACK. BY STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM ADT7518
Figure 58. I2C—Reading a Single Byte of Data from a Selected Register
Write Operation
Read Operation
Figure 59 shows the timing diagram for a write operation to the
ADT7518. Data is clocked into the registers on the rising edge
Figure 60 to Figure 62 show the timing diagrams necessary to
accomplish correct read operations. To read back from a reg-
ister, first write to the address pointer register with the address
of the register to be read from. This operation is shown in
Figure 60. Figure 61 shows the procedure for reading back a
single byte of data. The read command is first sent to the part
during the first eight clock cycles. During the following eight
clock cycles, the data contained in the register selected by the
address pointer register is output onto the DOUT line. Data is
output onto the DOUT line on the falling edge of SCLK. Figure 62
shows the procedure when reading data from two sequential
registers. Multiple data reads are possible in the SPI interface
mode as the address pointer register is autoincremental. The
address pointer register will autoincrement from 00h to 3Fh and
will loop back to start again at 00h when it reaches 3Fh.
of SCLK. When the
line is high, the DIN and DOUT lines
CS
are in three-state mode. Only when the
goes from a high to a
CS
low does the part accept any data on the DIN line. In SPI mode,
the address pointer register is capable of autoincrementing to
the next register in the register map without having to load the
address pointer register each time. In Figure 59, the register
address portion gives the first register that will be written to.
Subsequent data bytes will be written into sequential writable
registers. Thus, after each data byte has been written into a
register, the address pointer register autoincrements its value to
the next available register. The address pointer register will
autoincrement from 00h to 3Fh and will loop back to start again
at 00h when it reaches 3Fh.
Rev. A | Page 36 of 40
ADT7518
CS
1
8
1
8
SCLK
DIN
D2
D1
D6
D7
D7
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D0
START
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
8
SCLK (CONTINUED)
D7
D4
D3
D1
D6
D5
D2
D0
DIN (CONTINUED)
STOP
DATA BYTE
Figure 59. SPI—Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
CS
1
8
1
8
SCLK
DIN
D2
D1
D6
D7
D7
D5
D4
D3
D1
D0
D6
D5
D3
D0
D2
D4
STOP
START
WRITE COMMAND
REGISTER ADDRESS
Figure 60. SPI—Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
CS
1
8
1
8
SCLK
X
X
D6
X
D5
X
D1
X
X
DIN
D7
D4
X
D3
X
D0
X
X
X
D2
X
X
X
X
D0
STOP
X
D7
D6
D5
D4
D3
D2
D1
DOUT
START
DATA BYTE 1
READ COMMAND
Figure 61. SPI—Reading a Single Byte of Data From a Selected Register
Rev. A | Page 37 of 40
ADT7518
CS
1
8
1
8
SCLK
DIN
X
X
D6
X
X
D7
D5
X
D4
X
D3
X
D1
X
D0
X
X
X
X
D2
X
X
DOUT
X
X
D7
D6
D5
D4
D3
D2
D1
D0
START
READ COMMAND
DATA BYTE 1
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
X
X
X
X
X
X
X
X
DOUT (CONTINUED)
D6
D5
D4
D3
D1
D0
D7
D2
STOP
DATA BYTE 2
Figure 62. SPI—Reading Two Bytes of Data From Two Sequential Registers
CS
SPI
READ OPERATION
WRITE OPERATION
CS
Figure 63. SPI—Correct Use of During SPI Communication
SMBus/SPI INT/
INT
interrupt status registers show which event caused the INT/
pin to go active.
INT
The ADT7518 INT/
output is an interrupt line for devices
INT
that want to trade their ability to master for an extra pin. It is a
slave device and uses the SMBus/SPI INT/ to signal the host
The INT/
output requires an external pull-up resistor. This
INT
can be connected to a voltage different from VDD, provided the
maximum voltage rating of the INT/ output pin is not
INT
device that it wants to talk to. The SMBus/SPI INT/
ADT7518 is used as an over/under limit indicator.
on the
INT
INT
exceeded. The value of the pull-up resistor depends on the
application but should be large enough to avoid excessive sink
The INT/
pin has an open-drain configuration that allows
INT
the outputs of several devices to be wired-AND’ed together
when the INT/ pin is active low. Use C6 of the Control
currents at the INT/
output, which can heat the chip and
INT
affect the temperature reading.
INT
Config-uration 1 register to set the active polarity of the
SMBUS ALERT RESPONSE
INT/
out-put. The power-up default is active low. The
INT
The INT/
pin behaves the same way as an SMBus alert pin
INT
when the SMBus/I2C interface is selected. It is an open-drain
output and requires a pull-up to VDD. Several INT/ outputs
INT/
output can be disabled or enabled by setting C5 of the
INT
Control Config-uration 1 register to 1 or 0, respectively.
INT
can be wire-AND’ed together, so that the common line will go
low if one or more of the INT/ outputs goes low. The polar-
The INT/ output becomes active when either the internal
INT
INT
pin must be set active low for a number of
temperature value, the external temperature value, VDD value, or
any of the AIN input values exceed the values in their corres-
ity of the INT/
INT
outputs to be wire-AND’ed together.
ponding THIGH/VHIGH or TLOW/VLOW registers. The INT/
out-
INT
put goes inactive again when a conversion result has the
measured value back within the trip limits and when the status
register associated with the out-of-limit event is read. The two
Rev. A | Page 38 of 40
ADT7518
The INT/
output can operate as an
function.
of-limit event is read. If the line remains low,
SMBALERT
the master will send the ARA again. It will continue to do
INT
Slave devices on the SMBus cannot normally signal to the
master that they want to talk, but the function
SMBALERT
this until all devices whose
outputs were low
SMBALERT
is used in conjunction with
SMBALERT
allows them to do so.
have responded.
SMBALERT
the SMBus general call address.
MASTER
RECEIVES
SMBALERT
One or more INT/ outputs can be connected to a com-
INT
ALERT RESPONSE
NO
ACK
START
RD ACK DEVICE ADDRESS
STOP
ADDRESS
mon
line connected to the master. When the
SMBALERT
line is pulled low by one of the devices, the
following procedure occurs, as shown in Figure 64.
SMBALERT
MASTER SENDS
ARA AND READ
COMMAND
DEVICE SENDS
ITS ADDRESS
INT
SMBALERT
ARA
Figure 64. INT/
Responds to
1. pulled low.
SMBALERT
2. Master initiates a read operation and sends the alert res-
ponse address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
MASTER
ACK
MASTER
NACK
DEVICE ACK
RD ACK
MASTER
RECEIVES
SMBALERT
ALERT RESPONSE
ADDRESS
DEVICE
NO
ACK
START
ACK
PEC
STOP
ADDRESS
3. The devices whose INT/
INT
output is low responds to the
MASTER SENDS
ARA AND READ
COMMAND
alert response address and the master reads its device
address. As the device address is seven bits long, an LSB of
1 is added. The address of the device is now known and it
can be interrogated in the usual way.
DEVICE SENDS DEVICE SENDS
ITS ADDRESS ITS PEC DATA
INT
SMBALERT
ARA
Figure 65. INT/
Responds to
With Packet Error Checking (PEC)
4. If more than one device’s INT/
INT
output is low, the one
with the lowest device address will have priority in accor-
dance with normal SMBus specifications.
5. Once the ADT7518 has responded to the alert response
address, it will reset its INT/
output, provided that the
INT
condition that caused the out-of-limit event no longer
exists and that the status register associated with the out-
Rev. A | Page 39 of 40
ADT7518
OUTLINE DIMENSIONS
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 66. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions in Inches
ORDERING GUIDE
DAC
Temperature Range Resolution
Package
Description
Minimum
Quantities/Reel
Model
Package Option
RQ-16
RQ-16
RQ-16
RQ-16
ADT7518ARQ
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
–40°C to +120°C
8 Bits
8 Bits
8 Bits
8 Bits
8 Bits
8 Bits
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
N/A
ADT7518ARQ-REEL
ADT7518ARQ-REEL7
ADT7518ARQZ1
ADT7518ARQZ-REEL1
ADT7518ARQZ-REEL71
2,500
1,000
N/A
2,500
1,000
RQ-16
RQ-16
1 Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04879-0-8/04(A)
Rev. A | Page 40 of 40
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