ADTR1107ACCZ-R7 [ADI]
6 GHz to 18 GHz, Front-End IC;
| 型号： | ADTR1107ACCZ-R7 |
| 厂家： | 
ADI |
| 描述： | 6 GHz to 18 GHz, Front-End IC 电信 电信集成电路 |
| 文件： | 总28页 (文件大小：929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6 GHz to 18 GHz, Front-End IC
Data Sheet
ADTR1107
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD_LNA VGG_LNA
VSS_SW CTRL_SW VDD_SW
Operates from 6 GHz to 18 GHz
25 dBm typical transmit state PSAT
22 dB typical transmit state small signal gain
18 dB typical receive state small signal gain
2.5 dB typical receive state noise figure
Coupled power amplifier output for power detection
RX_OUT
TX_IN
ANT
ADTR1107
APPLICATIONS
Phased array antenna
Military radar
Weather radar
VGG_PA
VDD_PA
CPLR_OUT
Figure 1.
Communication links
Electronic warfare
GENERAL DESCRIPTION
The ADTR1107 is a compact, 6 GHz to 18 GHz, front-end IC
with an integrated power amplifier, low noise amplifier (LNA),
and a reflective single-pole double-throw (SPDT) switch. These
integrated features make the device ideal for phased array antenna
and radar applications. The front-end IC offers 25 dBm of
saturated output power (PSAT) and 22 dB small signal gain in
transmit state, and 18 dB small signal gain and 2.5 dB noise
figure in receive state. The device has a directional coupler for
power detection. The input/outputs (I/Os) are internally matched
to 50 Ω. The ADTR1107 is supplied in a 5 mm × 5 mm,
24-terminal, land grid array (LGA) package.
Rev. A
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Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
ADTR1107
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Transmit State................................................................................9
Receive State................................................................................ 16
Theory of Operation ...................................................................... 23
Applications Information ............................................................. 24
Recommended Bias Sequencing .............................................. 24
Typical Application Circuit...................................................... 25
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 6
Thermal Resistance...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions ............................ 7
Interface Schematics .................................................................... 8
Typical Performance Characteristics............................................. 9
Interfacing the ADTR1107 to the ADAR1000 X Band and KU
Band Beamformer............................................................................ 26
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
4/2020—Rev. 0 to Rev. A
Changes to VDD_LNA Parameter, Table 4 ................................. 5
1/2020—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
ADTR1107
SPECIFICATIONS
Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off (VDD_LNA = 0 V,
VGG_LNA = 0 V), TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
6
Typ Max
Unit
Test Conditions/Comments
OVERALL FUNCTION
Frequency Range
TRANSMIT STATE
Small Signal Gain
Gain Flatness
14
GHz
19.5
21.5
0.8
13
dB
TX_IN to ANT
dB
Input Return Loss
Output Return Loss
Output 1 dB Compression (OP1dB)
dB
TX_IN to ANT
TX_IN to ANT
TX_IN to ANT
15
dB
21
23
dBm
dBm
dBm
dB
Saturated Output Power (PSAT
)
25
Output Third-Order Intercept (OIP3)
Noise Figure
31
TX_IN to ANT output power (POUT) per tone = 8 dBm
TX_IN to ANT
9
Coupling Factor
Isolation
23.5
dB
Coupling factor = ANT POUT − CPLR_OUT POUT
TX_IN to RX_OUT
ANT to RX_OUT
RF Settling Time
0.1 dB
40
64
dB
dB
Receive state off
Receive state off
17
22
ns
ns
50% CTRL_SW to 0.1 dB of final RF output
50% CTRL_SW to 0.05 dB of final RF output
0.05 dB
Switching Speed
Rise and Fall Time
Turn On and Turn Off Time
VDD_PA
tRISE, tFALL
tON, tOFF
2
ns
ns
V
10% to 90% of RF output
10
50% CTRL_SW to 90% of RF output
3.3
5.0
5.5
Quiescent Current (IDQ_PA)
220
mA
Adjust VGG_PA voltage between −1.75 V and
−0.25 V to achieve the desired IDQ_PA
Transmit state, VDD_PA = 5 V, IDQ_PA = 220 mA, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 0 V, receive state off, TA = 25°C,
unless otherwise noted.
Table 2.
Parameter
Symbol Min Typ Max
Unit
Test Conditions/Comments
OVERALL FUNCTION
Frequency Range
TRANSMIT STATE
Small Signal Gain
Gain Flatness
Input Return Loss
Output Return Loss
OP1dB
PSAT
OIP3
Noise Figure
Coupling Factor
Isolation
14
20
18
GHz
22
0.6
12
11
21.5
24
31.5
6.5
18
dB
dB
dB
dB
dBm
dBm
dBm
dB
TX_IN to ANT
TX_IN to ANT
TX_IN to ANT
TX_IN to ANT
TX_IN to ANT
TX_IN to ANT POUT per tone = 8 dBm
TX_IN to ANT
Coupling factor = ANT POUT − CPLR_OUT POUT
19
dB
TX_IN to RX_OUT
ANT to RX_OUT
39
64
dB
dB
Receive state off
Receive state off
Rev. A | Page 3 of 28
ADTR1107
Data Sheet
Parameter
Symbol Min Typ Max
Unit
Test Conditions/Comments
RF Settling Time
0.1 dB
0.05 dB
17
22
ns
ns
50% CTRL_SW to 0.1 dB of final RF output
50% CTRL_SW to 0.05 dB of final RF output
Switching Speed
Rise and Fall Time
Turn On and Turn Off Time tON, tOFF
VDD_PA
IDQ_PA
tRISE, tFALL
2
ns
ns
V
10% to 90% of RF output
50% CTRL_SW to 90% of RF output
10
5.0
220
3.3
5.5
mA
Adjust VGG_PA voltage between −1.75 V and −0.25 V to
achieve the desired IDQ_PA
Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off (VDD_PA = 0 V, VGG_PA = −1.75 V), TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
6
Typ
Max
Unit
Test Conditions/Comments
OVERALL FUNCTION
Frequency Range
RECEIVE STATE
Small Signal Gain
Gain Flatness
Input Return Loss
Output Return Loss
OP1dB
PSAT
OIP3
Noise Figure
Isolation
14
GHz
15.5
17.5
0.6
13
14
14
16
26
2.5
dB
ANT to RX_OUT
dB
dB
dB
dBm
dBm
dBm
dB
ANT to RX_OUT
ANT to RX_OUT
ANT to RX_OUT
12
ANT to RX_OUT POUT per tone = 0 dBm
ANT to RX_OUT
ANT to TX_IN
RX_OUT to TX_IN
RF Settling Time
0.1 dB
32
48
dB
dB
Transmit state off
Transmit state off
17
22
ns
ns
50% CTRL_SW to 0.1 dB of final RF output
50% CTRL_SW to 0.05 dB of final RF output
0.05 dB
Switching Speed
Rise and Fall Time
Turn On and Turn Off Time
VDD_LNA
tRISE, tFALL
tON, tOFF
2
ns
ns
V
10% to 90% of RF output
50% CTRL_SW to 90% of RF output
10
3.3
80
2.0
3.6
IDQ_LNA
mA
Self biased
Receive state, self biased, VDD_LNA = 3.3 V, VGG_LNA = 0 V, VDD_SW = 3.3 V, VSS_SW = −3.3 V, CTRL_SW = 3.3 V, transmit state
off, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
14
Typ
Max
Unit
Test Conditions/Comments
OVERALL FUNCTION
Frequency Range
RECEIVE STATE
Small Signal Gain
Gain Flatness
Input Return Loss
Output Return Loss
OP1dB
18
GHz
16
18
0.9
13
18
14
dB
dB
ANT to RX_OUT
dB
dB
dBm
dBm
ANT to RX_OUT
ANT to RX_OUT
ANT to RX_OUT
ANT to RX_OUT
12
PSAT
16.5
Rev. A | Page 4 of 28
Data Sheet
ADTR1107
Parameter
Symbol
Min
Typ
25.5
3
Max
Unit
dBm
dB
Test Conditions/Comments
ANT to RX_OUT POUT per tone = 0 dBm
ANT to RX_OUT
OIP3
Noise Figure
Isolation
ANT to TX_IN
RX_OUT to TX_IN
RF Settling Time
0.1 dB
26
46
dB
dB
Transmit state off
Transmit state off
17
22
ns
ns
50% CTRL_SW to 0.1 dB of final RF output
50% CTRL_SW to 0.05 dB of final RF output
0.05 dB
Switching Speed
Rise and Fall Time
Turn On and Turn Off Time
VDD_LNA
tRISE, tFALL
tON, tOFF
2
ns
ns
V
10% to 90% of RF output
50% CTRL_SW to 90% of RF output
10
3.3
80
2.0
3.6
IDQ_LNA
mA
Self biased
SPDT switch bias at VDD_SW = 3.3 V, VSS_SW = −3.3 V.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT
Positive
Negative
VDD_SW and VSS_SW
IDD_SW
ISS_SW
14
120
μA
μA
DIGITAL CONTROL INPUTS
Voltage
CTRL_SW
Low
High
0
1.2
0.8
3.3
V
V
Current (Low and High)
<1
μA
Rev. A | Page 5 of 28
ADTR1107
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
Transmit State (PA On), Receive State Off
VDD_PA
VGG_PA
Continuous Wave (CW) RF Input Power 20 dBm
(RFIN) at TX_IN
Continuous Power Dissipation (PDISS
5.5 V
−2 V to +0 V
)
1.71 W
THERMAL RESISTANCE
(TA = 85°C, Derate 18.98 mW/°C
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Above 85°C)
Receive State (LNA On), Transmit State Off
VDD_LNA
4 V
VGG_LNA
CW RFIN at ANT
PDISS (TA = 85°C, Derate 5.04 mW/°C
Above 85°C)
Transmit and Receive States
−2 V to +0.2 V
20 dBm
0.453 W
θ
JC is the thermal resistance from the operating portion of the
device to the outside surface of the package (case) closest to the
device mounting area.
1
Table 7. Thermal Resistance
Output Load Voltage Standing Wave
Ratio (VSWR)
VDD_SW Range
VSS_SW Range
VDD_CTRL Range
Channel Temperature
7:1
Package Type θJC Transmit State
θJC Receive State Unit
198.4 °C/W
CC-24-8 52.7
−0.3 V to +3.6 V
−3.6 V to +0.3 V
−0.3 V to VDD + 0.3 V
175°C
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with 36 thermal vias. Refer to the JEDEC standard JESD51 for
additional information.
ESD CAUTION
Maximum Peak Reflow Temperature
(Moisture Sensitivity Level 3, MSL3)1
260°C
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity (Human Body Model)
−40°C to +125°C
−40°C to +85°C
Class 1B
(Passed 500 V)
1 See the Ordering Guide section for more information.
Table 8. Signal Path Truth Table
State
CTRL_SW
RF Signal Path
TX_IN to ANT
ANT to RX_OUT
Transmit
Receive
Low
High
Rev. A | Page 6 of 28
Data Sheet
ADTR1107
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
RX_OUT
GND
GND
ANT
GND
GND
GND
GND
1
2
3
4
5
6
18
17
16
15
14
13
ADTR1107
TOP VIEW
GND
(Not to Scale)
TX_IN
GND
NOTES
1. NIC = NO INTERNAL CONNECTION.
SOLDER THESE PINS TO A LOW
IMPEDANCE GROUND PLANE.
2. EXPOSED PAD. MUST BE CONNECTED
TO RF/DC GROUND.
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 3, 4, 6, 11, 13 GND
to 16, 18, 22
Ground. Solder these pins to a low impedance ground plane.
2
5
7
8
9, 10
12
17
19
20
21
23
RX_OUT
TX_IN
Receive Path Output. This pin is dc-coupled to ground and ac matched to 50 Ω.
Transmit Path Input. This pin is dc-coupled to ground and ac matched to 50 Ω.
Power Amplifier Gate Bias. This pin is used to set the desired quiescent current of the amplifier.
Power Amplifier Drain Bias Voltage.
VGG_PA
VDD_PA
NIC
CPLR_OUT
ANT
VDD_SW
CTRL_SW
VSS_SW
VGG_LNA
No Internal Connection. Solder these pins to a low impedance ground plane.
Transmit Path Coupled Port. This port is used in connection with a detector to monitor transmitted power.
RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω.
SPDT Switch Positive Bias Voltage.
Switch Digital Control. This pin controls the state of the SPDT switch.
SPDT Switch Negative Bias Voltage.
LNA Gate Voltage Bias. This pin is used to set the desired quiescent current of the LNA. If this pin is
supplied with 0 V or is connected to ground, the LNA runs in self bias mode at a typical current of 80 mA.
24
VDD_LNA
EPAD
LNA Drain Voltage Bias.
Exposed Pad. Must be connected to RF/dc ground.
Rev. A | Page 7 of 28
ADTR1107
Data Sheet
INTERFACE SCHEMATICS
GND
VDD_LNA
Figure 3. GND Interface Schematic
Figure 8. VDD_LNA Interface Schematic
ANT
VGG_LNA
Figure 4. ANT Interface Schematic
Figure 9. VGG_LNA Interface Schematic
VDD_SW
VDD_SW
RX_OUT
8kΩ
CTRL_SW
Figure 5. CTRL_SW and VDD_SW Interface Schematic
Figure 10. RX_OUT Interface Schematic
VDD_PA
TX_IN
2.5kΩ
Figure 6. VDD_PA Interface Schematic
Figure 11. TX_IN Interface Schematic
VGG_PA
Figure 7. VGG_PA Interface Schematic
Rev. A | Page 8 of 28
Data Sheet
ADTR1107
TYPICAL PERFORMANCE CHARACTERISTICS
TRANSMIT STATE
30
26
24
22
20
18
16
14
12
25
20
15
10
S11 (dB)
S21 (dB)
S22 (dB)
5
0
+85°C
+25°C
–40°C
–5
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 12. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA,
Receive State Off
Figure 15. Gain vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
26
24
22
20
26
24
22
20
18
18
5.0V
250mA
220mA
200mA
180mA
150mA
16
16
14
12
4.0V
3.3V
14
12
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 13. Gain vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Figure 16. Gain vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–4
–8
–4
–8
–12
–16
–20
–12
–16
–20
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 14. Input Return Loss vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 17. Output Return Loss vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Rev. A | Page 9 of 28
ADTR1107
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 18. Reverse Isolation vs. Frequency for Various Temperatures,Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 21. CLPR_OUT Coupling Factor vs. Frequency for Various
Temperatures, Transmit State, Coupling Factor = ANT POUT − CPLR_OUT POUT
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
,
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 19. TX_IN to RX_OUT Isolation vs. Frequency for Various Temperatures,
Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 22. ANT to RX_OUT Isolation vs. Frequency for Various Temperatures,
Transmit State, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
16
16
+85°C
5.0V
4.0V
3.3V
+25°C
14
14
12
10
8
–40°C
12
10
8
6
6
4
4
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
Figure 20. Noise Figure vs. Frequency for Various Temperatures, Transmit
State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 23. Noise Figure vs. Frequency for Various VDD_PA, Transmit State,
Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Rev. A | Page 10 of 28
Data Sheet
ADTR1107
16
14
12
10
8
28
26
24
22
20
18
16
14
12
10
+85°C
+25°C
–40°C
250mA
220mA
200mA
180mA
150mA
6
4
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 24. Noise Figure vs. Frequency for Various IDQ_PA, Transmit State , Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
Figure 27. OP1dB vs. Frequency for Various Temperatures,Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
28
28
26
24
22
20
26
24
22
20
18
16
14
12
10
5.0V
4.0V
3.3V
18
250mA
220mA
200mA
180mA
150mA
16
14
12
10
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 25. OP1dB vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Figure 28. OP1dB vs. Frequency for Various IDQ_PA, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, Receive State Off
30
28
26
24
22
20
18
30
28
26
24
22
20
5.0V
4.0V
3.3V
18
16
14
12
10
16
+85°C
+25°C
–40°C
14
12
10
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 26. PSAT vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 29. PSAT vs. Frequency for Various VDD_PA, Transmit State, Path =
TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Rev. A | Page 11 of 28
ADTR1107
Data Sheet
30
28
26
24
22
20
18
16
14
12
10
35
30
25
20
15
10
5
+85°C
+25°C
–40°C
250mA
220mA
200mA
180mA
150mA
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 30. PSAT vs. Frequency for Various IDQ_PA,Transmit State, Path = TX_IN
to ANT, VDD_PA = 5 V, Receive State Off
Figure 33. PAE vs. Frequency for Various Temperatures, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off, PAE
Measured at PSAT
35
35
30
25
20
5.0V
30
4.0V
3.3V
25
20
15
10
5
15
10
5
250mA
220mA
200mA
180mA
150mA
0
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 31. Power Added Efficiency (PAE) vs. Frequency for Various VDD_PA,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off, PAE
Measured at PSAT
Figure 34. PAE vs. Frequency for Various IDQ_PA, Transmit State, Path = TX_IN
to ANT, VDD_PA = 5 V, Receive State Off, PAE Measured at PSAT
30
25
20
15
10
5
330
310
290
270
250
230
210
30
25
20
15
10
5
450
410
370
330
290
250
210
P
GAIN
PAE
OUT
I
_PA
DD
P
GAIN
PAE
OUT
I
_PA
DD
0
0
–20
–16
–12
–8
–4
0
4
8
–20
–16
–12
–8
–4
0
4
8
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 32. POUT, Gain, PAE and Power Amplifier Supply Current (IDD_PA) vs. Input
Power, 6 GHz, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
Figure 35. POUT, Gain, PAE and IDD_PA vs. Input Power, 10 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Rev. A | Page 12 of 28
Data Sheet
ADTR1107
30
450
410
370
330
290
250
210
30
25
20
15
10
5
330
310
290
270
250
230
P
GAIN
PAE
OUT
25
20
15
10
5
I
_PA
DD
P
GAIN
PAE
OUT
I
_PA
DD
0
–20
0
–20
210
5
–15
–10
–5
0
5
10
–15
–10
–5
0
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 36. POUT, Gain, PAE and IDD_PA vs. Input Power, 14 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 39. POUT, Gain, PAE and IDD_PA vs. Input Power, 18 GHz, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
2.0
40
35
30
25
20
15
MAX P
1.5
1.0
0.5
0
DISS
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
+85°C
10
+25°C
–40°C
5
0
–20
–15
–10
–5
0
5
10
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
INPUT POWER (dBm)
Figure 37. Power Dissipation vs. Input Power at TA = 85°C, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 40. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA,
Receive State Off
40
35
30
25
40
35
30
25
20
20
5.0V
250mA
15
15
4.0V
220mA
3.3V
200mA
180mA
150mA
10
10
5
0
5
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 38. OIP3 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Figure 41. OIP3 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off
Rev. A | Page 13 of 28
ADTR1107
Data Sheet
40
35
30
25
20
15
70
60
50
40
30
20
10
0
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
8dBm
6dBm
4dBm
10
5
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
4
5
6
7
8
P
/TONE (dBm)
OUT
Figure 45. Third-Order Intermodulation Distortion Relative to Carrier (IM3)
vs. POUT/Tone, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
Figure 42. OIP3 vs. Frequency for Various POUT/Tone, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
70
65
60
55
50
45
40
70
65
60
55
50
45
40
35
35
5.0V
4.0V
+85°C
30
30
25
3.3V
+25°C
–40°C
25
20
15
10
20
15
10
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
Figure 46. OIP2 vs. Frequency for Various VDD_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, IDQ_PA = 220 mA, Receive State Off
Figure 43. Output Second-Order Intercept (OIP2) vs. Frequency for Various
Temperatures, POUT/Tone = 8 dBm, Transmit State, Path = TX_IN to ANT,
VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
70
65
60
55
50
45
40
70
65
60
55
50
45
40
35
35
8dBm
250mA
6dBm
220mA
30
30
4dBm
200mA
180mA
25
20
15
10
25
150mA
20
15
10
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
Figure 47. OIP2 vs. Frequency for Various POUT/Tone, Transmit State, Path =
TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 44. OIP2 vs. Frequency for Various IDQ_PA, POUT/Tone = 8 dBm,
Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, Receive State Off
Rev. A | Page 14 of 28
Data Sheet
ADTR1107
400
0.2
0.1
6GHz
8GHz
375
350
325
300
275
250
225
200
10GHz
12GHz
14GHz
16GHz
18GHz
0
–0.1
–0.2
–0.3
–0.4
–0.5
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
–20
–15
–10
–5
0
5
10
–20
–15
–10
–5
0
5
10
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 48. IDD_PA vs. Input Power for Various Frequencies, Transmit State,
Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA = 220 mA, Receive State Off
Figure 50. Power Amplifier Gate Current (IGG_PA) vs. Input Power for Various
Frequencies, Transmit State, Path = TX_IN to ANT, VDD_PA = 5 V, IDQ_PA =
220 mA, Receive State Off
800
700
600
500
400
300
200
100
0
–100
–1.75
–1.50
–1.25
–1.00
–0.75
–0.50
–0.25
VGG_PA (V)
Figure 49. IDQ_PA vs. VGG_PA, VDD_PA = 5 V, Transmit State, Path = TX_IN to
ANT, VDD_PA = 5 V, Receive State Off
Rev. A | Page 15 of 28
ADTR1107
Data Sheet
RECEIVE STATE
25
22
20
18
16
14
12
10
8
20
15
S11 (dB)
S21 (dB)
S22 (dB)
10
5
0
–5
+85°C
+25°C
–40°C
–10
–15
–20
0
2
4
6
8
10 12 14 16 18 20 22 24 26
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 51. Broadband Gain and Return Loss vs. Frequency, 10 MHz to 26 GHz,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Figure 54. Gain vs. Frequency for Various Temperatures, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
22
20
18
16
14
22
20
18
16
14
50mA
100mA
85mA, SELF BIAS MODE
12
10
8
12
2.0V
3.0V
3.3V
3.6V
10
8
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 52. Gain vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
Figure 55. Gain vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–4
–4
–8
–12
–16
–20
–8
–12
–16
–20
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 53. Input Return Loss vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Figure 56. Output Return Loss vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Rev. A | Page 16 of 28
Data Sheet
ADTR1107
0
–10
–20
–30
–40
–50
–60
0
–10
–20
–30
–40
–50
–60
–70
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 57. Reverse Isolation vs. Frequency for Various Temperatures, Receive
State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA =
0 V, Transmit State Off
Figure 60. RX_OUT to TX_IN Isolation vs. Frequency for Various
Temperatures, Receive State, Path = ANT to RX_OUT, Self Biased Mode,
VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off
0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
+85°C
+25°C
–40°C
–10
–20
–30
–40
–50
+85°C
1.5
+25°C
–40°C
1.0
0.5
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
Figure 58. ANT to TX_IN Isolation vs. Frequency for Various Temperatures,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Figure 61. Noise Figure vs. Frequency for Various Temperatures, Receive
State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
2.0
2.0V
1.5
1.0
0.5
0
1.5
1.0
0.5
0
3.0V
3.3V
3.6V
50mA
100mA
85mA, SELF BIAS MODE
4
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 59. Noise Figure vs. Frequency for Various VDD_LNA, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
Figure 62. Noise Figure vs. Frequency for Various IDQ_LNA, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled
VGG_LNA, Transmit State Off
Rev. A | Page 17 of 28
ADTR1107
Data Sheet
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
2.0V
3.0V
3.3V
3.6V
6
6
+85°C
+25°C
–40°C
4
4
2
2
0
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 63. OP1dB vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Figure 66. OP1dB vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
22
20
18
16
14
12
22
20
18
16
14
12
10
8
10
50mA
100mA
8
85mA, SELF BIAS MODE
6
4
2
0
6
4
2
0
+85°C
+25°C
–40°C
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 64. OP1dB vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
Figure 67. PSAT vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State = Off
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
50mA
100mA
8
85mA, SELF BIAS MODE
2.0V
3.0V
3.3V
3.6V
6
4
2
0
6
4
2
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 65. PSAT vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off
Figure 68. PSAT vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off
Rev. A | Page 18 of 28
Data Sheet
ADTR1107
25
20
15
10
5
25
20
15
10
5
2.0V
3.0V
3.3V
3.6V
+85°C
+25°C
–40°C
0
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 69. PAE vs. Frequency for Various Temperatures, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off, PAE Measured at PSAT
Figure 72. PAE vs. Frequency for Various VDD_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V, Transmit State Off, PAE
Measured at PSAT
25
20
15
25
20
15
10
5
110
105
100
95
P
GAIN
PAE
OUT
I
_LNA
DD
10
90
50mA
100mA
85mA, SELF BIAS MODE
5
0
85
0
–5
80
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
–20 –18 –16 –14 –12 –10 –8
–6
–4
–2
0
2
INPUT POWER (dBm)
Figure 70. PAE vs. Frequency for Various IDQ_LNA, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Transmit State Off, PAE Measured at PSAT
Figure 73. POUT, Gain, PAE and IDD_LNA vs. Input Power, 6 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
25
20
15
10
5
110
105
100
95
25
20
15
10
5
110
105
100
95
P
GAIN
PAE
P
OUT
GAIN
PAE
OUT
I
_LNA
I
_LNA
DD
DD
90
90
0
85
0
85
–5
–20
80
–5
–20
80
–16
–12
–8
–4
0
4
–15
–10
–5
0
5
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 71. POUT, Gain, PAE and IDD_LNA vs. Input Power, 10 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
Figure 74. POUT, Gain, PAE and IDD_LNA vs. Input Power, 14 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA= 0 V,
Transmit State Off
Rev. A | Page 19 of 28
ADTR1107
Data Sheet
25
110
105
100
95
0.5
0.4
0.3
0.2
0.1
0
20
MAX P
DISS
P
GAIN
PAE
15
10
5
OUT
I
_LNA
DD
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
90
0
85
–5
80
–20 –18 –16 –14 –12 –10 –8
–6
–4
–2
0
2
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2
0
2
4
6
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 75. POUT, Gain, PAE and IDD_LNA vs. Input Power, 18 GHz, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Figure 78. Power Dissipation vs. Input Power at TA = 85°C, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
30
27
24
21
30
27
24
21
2.0V
3.0V
3.3V
3.6V
+85°C
+25°C
–40°C
18
18
15
15
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 76. OIP3 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
Figure 79. OIP3 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V,
Transmit State Off
30
25
20
15
30
25
20
15
50mA
100mA
85mA, SELF BIAS MODE
0dBm
5dBm
10
10
5
5
0
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY (GHz)
Figure 77. OIP3 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
Controlled VGG_LNA, Transmit State Off
Figure 80. OIP3 vs. Frequency for Various POUT/Tone, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Rev. A | Page 20 of 28
Data Sheet
ADTR1107
70
60
50
40
45
40
35
30
25
20
15
10
5
6GHz
30
20
10
0
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
+85°C
+25°C
–40°C
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
P
/TONE (dBm)
OUT
Figure 81. IM3 vs. POUT/Tone, Receive State, Path = ANT to RX_OUT, Self
Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V, Transmit State Off
Figure 84. OIP2 vs. Frequency for Various Temperatures, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
VGG_LNA = 0 V, Transmit State Off
45
40
35
30
25
20
45
40
35
30
25
20
15
10
5
50mA
100mA
85mA, SELF BIAS MODE
15
2.0V
3.0V
10
3.3V
3.6V
5
0
0
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
Figure 82. OIP2 vs. Frequency for Various VDD_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VGG_LNA = 0 V,
Transmit State Off
Figure 85. OIP2 vs. Frequency for Various IDQ_LNA, POUT/Tone = 0 dBm,
Receive State, Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V,
Controlled VGG_LNA, Transmit State Off
45
40
35
30
25
90
6GHz
8GHz
10GHz
12GHz
14GHz
16GHz
18GHz
85
80
75
70
0dBm
20
5dBm
15
10
5
0
6
7
8
9
10 11 12 13 14 15 16 17 18
FREQUENCY (GHz)
–20
–15
–10
–5
0
5
INPUT POWER (dBm)
Figure 83. OIP2 vs. Frequency for Various POUT/Tone, Receive State, Path =
ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Figure 86. IDD_LNA vs. Input Power for Various Frequencies, Receive State,
Path = ANT to RX_OUT, Self Biased Mode, VDD_LNA = 3.3 V, VGG_LNA = 0 V,
Transmit State Off
Rev. A | Page 21 of 28
ADTR1107
Data Sheet
120
100
80
60
40
20
0
120
100
80
60
40
20
0
–20
–1.5
–1.0
–0.5
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
_LNA (V)
VGG_LNA (V)
V
DD
Figure 88. IDQ_LNA vs. VDD_LNA, Self Biased Mode, VGG_LNA = 0 V, Receive
State, Path = ANT to RX_OUT, Transmit State Off
Figure 87. IDQ_LNA vs. VGG_LNA, VDD_LNA = 3.3 V, Controlled VGG_LNA,
Receive State, Path = ANT to RX_OUT, Transmit State Off
Rev. A | Page 22 of 28
Data Sheet
ADTR1107
THEORY OF OPERATION
The ADTR1107 is a multichip transmit/receive module that
consists of an LNA, a medium power amplifier, and a silicon
SPDT reflective switch. The ANT antenna port is dc-coupled to
0 V and no dc block is required at this port when the RF line
potential is equal to 0 V. The switch has an integrated driver to
perform logic functions internally and provides a simplified
complementary metal-oxide semiconductor (CMOS)/low
voltage transistor to transistor logic (LVTTL)-compatible
control interface. The driver features a single digital control
input pin, CTRL_SW. The logic level applied to CTRL_SW
determines whether the ADTR1107 is in transmit state or
receive state (see Table 8).
The receive path contains a self biased LNA with optional bias
control using the VGG_LNA pin for bias adjustment. For self
biased operation, the VGG_LNA pin is set to 0 V or connected
to ground. The receive path output (RX_OUT) is dc-coupled to
ground through an 8 kΩ resistor. No dc block is required at this
port when the RF line potential is equal to 0 V.
The transmit path contains a power amplifier. The bias
current is set using VGG_PA. The transmit path input (TX_IN)
is dc-coupled to ground through a 2.5 kΩ resistor. No dc block
is required at this port when the RF line potential is equal to 0 V.
A directional coupler is incorporated into the ADTR1107 to
allow for monitoring of the transmit power level.
Rev. A | Page 23 of 28
ADTR1107
Data Sheet
APPLICATIONS INFORMATION
The basic connections for operating the ADTR1107 are shown
in Figure 89. The power amplifier on the transmit path is biased
with +5 V on the VDD_PA pin and a voltage from −1.75 V to
−0.25 V is applied to the VGG_PA pin to achieve 220 mA
quiescent current.
The recommended bias sequence during receive state power-up
is as follows:
1. Connect all GND pins to ground.
2. Set the VDD_SW pin to 3.3 V.
3. Set the VSS_SW pin to −3.3 V.
4. Set the CTRL_SW pin to 3.3 V.
5. Set the VGG_PA pin to −1.75 V.
6. Set the VDD_PA pin to 0 V.
7. Set the VGG_LNA pin to 0 V.
8. Set the VDD_LNA pin to 3.3 V.
9. Apply the RF signal to the ANT pin.
The LNA on the receive path operates as either self biased or
external biased mode. For self biased mode, apply 3.3 V to the
VDD_LNA pin and leave the VGG_LNA pin supplied with 0 V
or connected to ground. For external biased mode, apply +3.3 V
to the VDD_LNA pin and adjust the VGG_LNA pin with a voltage
range of −1.5 V to 0 V to achieve the desired IDQ_PA.
The SPDT switch is biased with +3.3 V on the VDD_SW pin
and −3.3 V on the VSS_SW pin. The CTRL_SW pin sets the
path state shown in Table 8. High logic state is set at 3.3 V and
low logic state is set at 0 V.
The recommended receive state bias sequence during
power-down is as follows:
1. Turn off the RF signal.
2. Set the VDD_LNA pin to 0 V.
3. Set the CTRL_SW pin to 0 V.
4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.
All required decoupling capacitors for the dc power supply
lines are internal to the ADTR1107.
RECOMMENDED BIAS SEQUENCING
All measurements and data shown in this data sheet were taken
using the typical application circuit (see Figure 89) and biased
per the conditions in this section, unless otherwise noted. The
bias conditions described in this section are the operating
points recommended to optimize the overall device performance.
Operation using other bias conditions can result in performance
that differs from what is shown in the Typical Performance
Characteristics section. To obtain optimal performance while
not damaging the device, follow the recommended biasing
sequences described in this section and adhere to the values
shown in the Absolute Maximum Ratings section.
The recommended bias sequence during transmit state
power-up is as follows:
1. Connect all GND pins to ground.
2. Set the VDD_SW pin to 3.3 V.
3. Set the VSS_SW pin to −3.3 V.
4. Set the CTRL_SW pin to 0 V.
5. Set the VGG_LNA pin to 0 V.
6. Set the VDD_LNA pin to 0 V.
7. Set the VGG_PA pin to −1.75 V.
8. Set the VDD_PA pin to 5 V.
9. Increase the VGG_PA voltage to achieve the desired
I
DQ_PA.
10. Apply the RF signal to the TX_IN pin.
The recommended transmit state bias sequence during
power-down is as follows:
1. Turn off the RF signal.
2. Decrease the VGG_PA voltage to −1.75 V.
3. Set the VDD_PA pin to 0 V.
4. Set the VSS_SW pin to 0 V.
5. Set the VDD_SW pin to 0 V.
Rev. A | Page 24 of 28
Data Sheet
ADTR1107
TYPICAL APPLICATION CIRCUIT
+3.3V
0V/+3.3V
–3.3V
0V
+3.3V
RECEIVE PATH OUTPUT
1
2
3
4
5
6
18
17
16
15
14
13
GND
RX_OUT
GND
GND
TX_IN
GND
GND
ANT
GND
GND
GND
GND
ADTR1107
TRANSMIT PATH INPUT
COUPLED
OUTPUT
GND
+5V
–1.75V TO –0.25V
Figure 89. Typical Application Circuit
Rev. A | Page 25 of 28
ADTR1107
Data Sheet
INTERFACING THE ADTR1107 TO THE ADAR1000 X BAND AND KU BAND BEAMFORMER
ADTR1107 can be interfaced to the ADAR1000 X band and Ku
band quad beamformer IC, as shown in Figure 91. Note that
only a single channel of the ADAR1000 is shown in Figure 91
and additional components have been omitted for clarity. The
ADAR1000 provides multiple bias voltages and control signals,
resulting in a glueless interface and no need for any additional
control signals to the ADTR1107. The gate voltage for the
ADTR1107 power amplifier (VGG_PA) is provided by the
ADAR1000 PA_BIAS3 pin. One of four independent negative
gate voltages is needed for power amplifier gate biasing. Each
voltage is set by an 8-bit digital-to-analog converter (DAC)
with an output voltage range of 0 V to −4.8 V. The typical gate
voltage required to bias the ADTR1107 power amplifier is −1.1 V
(see Figure 49). This voltage can be asserted by the ADAR1000
TR input pin (rising edge enables the power amplifier) or by a
serial peripheral interface (SPI) write. Asserting the ADAR1000
TR pin switches the polarity of the ADAR1000 TR_SW_NEG pin
and TR_SW_POS pin. The TR_SW_POS pin can drive the
gates of up to four switches and can be used to control the
ADTR1107 SPDT switch.
The ADTR1107 CPLR_OUT coupler output can be tied back to
one of the four ADAR1000 RF detector inputs (DET1 to DET4).
These diode based RF detectors have an input range of −20 dBm to
+10 dBm. The coupling factor of the ADTR1107 directional
coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz. At
12 GHz, with a coupling factor of 22 dB and a maximum power
amplifier output of 26 dBm, the coupled output power is a
maximum of 4 dBm. If the coupler output is connected directly
to the detector input, this connection provides a detection range of
24 dB. Figure 90 shows the relationship between the ADTR1107
output power and the ADC code of the ADAR1000 detector at
12 GHz. In this case, the ADTR1107 output power is swept to a
maximum level of approximately 22 dBm.
100
10
1
While the ADTR1107 LNA gate voltage is self biased (the
VGG_LNA pin is connected to 0 V or grounded), the voltage
can also be controlled from the ADAR1000. In this case, there
is a single LNA_BIAS voltage (0 V to −4.8 V) controlled by an
8-bit DAC that can be used to bias four ADTR1107 devices
connected to each ADAR1000.
0.1
5
7
9
11
13
15
17
19
21
23
ADTR1107 OUTPUT POWER (dBm)
Figure 90. ADAR1000 RF Detector Output Code vs. ADTR1107 Output Power
at 12 GHz
Rev. A | Page 26 of 28
Data Sheet
ADTR1107
–5V
+3.3V
AVDD3
AVDD1
ADAR1000
TO PA
BIAS
DET3
LDO
1.8V
ADC
+5V
VDD_PA
VGG_PA
TX_IN
100kΩ
CPLR_OUT
PA_BIAS3
PA BIAS
TX3
RX3
ANT
ADTR1107
RX_OUT
1
LNA_BIAS
VGG_LNA
VSS_SW
–3.3V
LNA BIAS
VDD_LNA
+3.3V
VDD_SW
+3.3V
TR_SW_POS
TO ADDITIONAL LNA
GATES
SPI
1
LNA_BIAS IS A SINGLE PIN THAT CAN DRIVE UP TO FOUR GATES AND
IS AN OPTIONAL CONNECTION THAT CAN BE USED TO VARY THE BIAS
CURRENT OF THE ADTR1107.
Figure 91. Interfacing the ADTR1107 to the ADAR1000 X and Ku Band Beamformer, One Channel Shown
Rev. A | Page 27 of 28
ADTR1107
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.35
0.30
0.25
PIN 1
INDICATOR
AREA
0.50
0.45
0.40
PIN 1
INDICATOR
C 0.30 × 0.45
°
19
24
18
1
3.30 SQ
BSC
3.25 REF
SQ
EXPOSED
PAD
13
6
0.65
BSC
7
12
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.15
REF
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.13
MAX
0.70 REF
0.356
0.326
0.296
SECTION OF THIS DATA SHEET.
SEATING
PLANE
Figure 92. 24-Terminal Land Grid Array [LGA]
(CC-24-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADTR1107ACCZ
ADTR1107ACCZ-R7
ADTR1107-EVAL
Temperature Range
−40°C to +85°C
−40°C to +85°C
MSL Rating2
Package Description3
Package Option
CC-24-8
CC-24-8
3
3
24-Terminal Land Grid Array [LGA]
24-Terminal Land Grid Array [LGA]
Evaluation Board
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section for additional information.
3 The lead finish of the ADTR1107ACCZ and the ADTR1107ACCZ-R7 is nickel palladium gold (NiPdAu).
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D22146-4/20(A)
Rev. A | Page 28 of 28
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