ADUC7126BSTZ126I_技术文档

Precision Analog Microcontroller, 12-Bit Analog I/O, Large

Memory, ARM7TDMI MCU with Enhanced IRQ Handler

Data Sheet

ADuC7124/ADuC7126

On-chip peripherals

FEATURES

Analog input/output

2× fully I²C-compatible channels

SPI (20 MBPS in master mode, 10 MBPS in slave mode)

With 4-byte FIFO on input and output stages

2× UART channels

With 16-byte FIFO on input and output stages

Up to 40 GPIO port

Multichannel, 12-bit, 1 MSPS ADC

Up to 16 ADC channels

Fully differential and single-ended modes

0 V to V_REFanalog input range

12-bit voltage output DACs

All GPIOs are 5 V tolerant

4 DAC outputs available

4× general-purpose timers

On-chip voltage reference

Watchdog timer (WDT) and wake-up timer

Programmable logic array (PLA)

16 PLA elements

On-chip temperature sensor ( 3°C)

Voltage comparator

Microcontroller

16-bit, 6-channel PWM

Power supply monitor

Power

ARM7TDMI core, 16-bit/32-bit RISC architecture

JTAG port supports code download and debug

Clocking options

Specified for 3 V operation

Trimmed on-chip oscillator ( 3ꢀ)

External watch crystal

External clock source up to 41.78 MHz

41.78 MHz PLL with programmable divider

Memory

126 kB Flash/EE memory, 32 kB SRAM

In-circuit download, JTAG-based debug

Software-triggered in-circuit reprogrammability

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type

Interrupt on edge or level external pin inputs

Active mode: 11.6 mA at 5 MHz, 33.3 mA at 41.78 MHz

Packages and temperature range

Fully specified for −40°C to +125°C operation

64-lead LFCSP (ADuC7124) and 80-lead LQFP (ADuC7126)

Tools

Low cost QuickStart development system

Full third-party support

APPLICATIONS

Industrial control and automation systems

Smart sensors, precision instrumentation

Base station systems, optical networking

Patient monitoring

FUNCTIONAL BLOCK DIAGRAM

ADC0

12-BIT

DAC0

DAC

1MSPS

12-BIT ADC

MUX

12-BIT

DAC1

DAC

ADC15

TEMP

SENSOR

ADuC7124/ADuC7126

12-BIT

DAC

DAC2

DAC3

CMP0

CMP1

BAND GAP

REF

12-BIT

DAC

CMP

VECTORED

INTERRUPT

CONTROLLER

OUT

V

REF

OSC

AND PLL

ARM7TDMI-BASED MCU WITH

ADDITIONAL PERIPHERALS

XCLKI

XCLKO

8k × 32 SRAM

GPIO

PSM

PLA

63k × 16 FLASH/EEPROM

EXTERNAL

PWM

MEMORY

INTERFACE

2

4 GENERAL-

SPI, 2 × I C,

2 × UART

RST

POR

JTAG

PURPOSE TIMERS

Figure 1.

Rev. D

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ADuC7124/ADuC7126

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Band Gap Reference................................................................... 45

Nonvolatile Flash/EE Memory ..................................................... 46

Programming.............................................................................. 46

Flash/EE Memory Security ....................................................... 47

Flash/EE Control Interface ....................................................... 47

Execution Time from SRAM and Flash/EE............................ 50

Reset and Remap........................................................................ 50

Other Analog Peripherals.............................................................. 53

DAC.............................................................................................. 53

Power Supply Monitor............................................................... 55

Comparator................................................................................. 55

Oscillator and PLL—Power Control........................................ 56

Digital Peripheral ........................................................................... 60

General-Purpose Input/Output................................................ 60

Serial Port Mux........................................................................... 62

UART Serial Interface................................................................ 62

Serial Peripheral Interface......................................................... 68

I²C................................................................................................. 72

PWM General Overview........................................................... 80

Programmable Logic Array (PLA)........................................... 83

Processor Reference Peripherals................................................... 86

Interrupt System......................................................................... 86

IRQ ............................................................................................... 86

Fast Interrupt Request (FIQ) .................................................... 87

Vectored Interrupt Controller (VIC)....................................... 88

Timers.......................................................................................... 93

External Memory Interfacing ................................................... 99

Hardware Design Considerations .............................................. 103

Power Supplies.......................................................................... 103

Grounding and Board Layout Recommendations............... 104

Clock Oscillator........................................................................ 104

Power-On Reset Operation..................................................... 105

Outline Dimensions..................................................................... 106

Ordering Guide ........................................................................ 107

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 5

Specifications..................................................................................... 6

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 14

ESD Caution................................................................................ 14

Pin Configurations and Function Descriptions ......................... 15

Typical Performance Characteristics ........................................... 24

Terminology .................................................................................... 27

ADC Specifications .................................................................... 27

DAC Specifications..................................................................... 27

Overview of the ARM7TDMI Core............................................. 28

Thumb Mode (T)........................................................................ 28

Long Multiply (M)...................................................................... 28

EmbeddedICE (I) ....................................................................... 28

Exceptions ................................................................................... 28

ARM Registers ............................................................................ 28

Interrupt Latency........................................................................ 29

Memory Organization ................................................................... 30

Memory Access........................................................................... 30

Flash/EE Memory....................................................................... 30

SRAM........................................................................................... 30

Memory Mapped Registers....................................................... 30

ADC Circuit Overview .................................................................. 38

Transfer Function ....................................................................... 38

Typical Operation ....................................................................... 39

MMRs Interface.......................................................................... 39

Converter Operation.................................................................. 41

Driving the Analog Inputs ........................................................ 43

Calibration................................................................................... 44

Temperature Sensor ................................................................... 44

Rev. D | Page 2 of 110

Data Sheet

ADuC7124/ADuC7126

REVISION HISTORY

10/14—Rev. C to Rev. D

Changes to Figure 7 and Table 9 ...................................................14

Added Figure 8 and Table 10; Renumbered Sequentially..........18

Change to Figure 17 Caption.........................................................25

Change to Memory Mapped Registers Section...........................29

Change to Figure 26........................................................................30

Changes to Table 18 ........................................................................32

Changes to Table 21 ........................................................................33

Changes to Table 22 ........................................................................34

Moved Table 25................................................................................35

Change to Table 25..........................................................................35

Added Table 26................................................................................35

Change to Table 27..........................................................................36

Changes to Temperature Sensor Section .....................................42

Deleted Table 59; Renumbered Sequentially...............................43

Added Downloading (In-Circuit Programming) via I²

C Section ..........................................................................................44

Change to JTAG Access Section and Table 37.............................45

Changes to Table 45 ........................................................................46

Changes to RSTCFG Register Section..........................................49

Deleted Table 72 and Table 75.......................................................49

Deleted Table 78 ..............................................................................50

Changes to DAC Section, Table 62, and Table 64.......................51

Changes to References to ADC and the DACs Setion, Table 66,

Configuring DAC Buffers in Op Amp Mode Section,

Change

To CONV_{START .............................................................}Universal

CONV_START

Changes to Features Section ............................................................1

Changes to Pin 17 and Pin 30 Descriptions; Table 10................19

Changes to Flash/EE Memory Section and SRAM Section.......30

Changes to Table 13 ........................................................................32

Changes to Flash/EE Memory Section, Programming Section,

and Serial Downloading (In-Circuit Programming) Section ...46

Changes to Flash/EE Memory Security Section..........................47

Changes to Table 56 and Table 57 .................................................50

Changes to Table 69 ........................................................................56

Changes to Table 78 ........................................................................60

Changes to I²C Section ...................................................................72

Update Table 102.............................................................................73

Update Table 109.............................................................................76

Changes to Table 110 ......................................................................77

Changes to T1CAP Register ..........................................................96

5/12—Rev. B to Rev. C

Changed bit to byte in General Description Section....................4

Changes to Table 2 and Table 3 .......................................................8

Changes to Table 4 and to Figure 2 and Figure 3..........................9

Changes to Table 5 and Figure 4....................................................10

Changes to Table 6 and Figure 5....................................................11

Changes Table 7 and Figure 6........................................................12

Changes to Pin 50 and Pin 51 in Table 9......................................14

Changes to Serial Downloading (In-Circuit Programming)

Section...............................................................................................44

Changes to Table 77 ........................................................................59

Changes to Table 78 ........................................................................58

Changes to Table 90 ........................................................................60

Changes to Normal 450 UART Baud Rate Generation

Section...............................................................................................61

Changes to Serial Peripheral Interface Section ...........................66

Added equation to Timers Section and added Hr: Min: Sec

1/128 Format Section......................................................................91

Changes to Figure 69 ................................................................... 103

Updated Outline Dimensions..................................................... 104

Changes to Ordering Guide........................................................ 105

DACBCFG Register Section, and Table 67..................................52

Added DACBKEY1 Register Section and DACBKEY2 Register

Section ..............................................................................................53

Changes to Table 69 and Figure 45 ...............................................54

Changes to and External Crystal Selection and External Clock

Selection ...........................................................................................55

Changes to PLLCON Register and POWCON0 Register

Section ..............................................................................................56

Changes to Table 78 ........................................................................58

Changes to Table 81 ........................................................................59

Changes to Table 84 and Table 90.................................................60

Changes to Table 93, COM0FCR Register Section, COM1FCR

Register Section, and Table 94.......................................................63

Changes to Serial Peripheral Interface Section ...........................66

Change to SPI Registers Section....................................................67

Changes to SPIDIV Register Section and Table 101 ..................68

Change to I²C Master Transmit Register Section .......................73

Change to Table 109........................................................................74

Change to I²C Slave Status Registers Section...............................75

Change to Table 113........................................................................79

Changes to Table 114 Title and Figure 50....................................80

Change to IRQCLRE Register Register .......................................90

Change to Figure 54........................................................................92

Changes to Table 141, T1CLRI Register Section, and T1CAP

Register Section ...............................................................................93

Changes to Table 143 ......................................................................94

Added External Memory Interfacting Section, Table 145,

1/11—Rev A to Rev B

Changes to Table 1 ............................................................................5

10/10—Rev. 0 to Rev. A

Added ADuC7126..............................................................Universal

Changes to Features Section ............................................................1

Moved Figure 1..................................................................................1

Changes to Figure 1...........................................................................1

Changes to General Description Section .......................................4

Changes to Voltage Output at 25°C, Voltage TC, IOV_DDCurrent

in Active Mode, and IOV_DDCurrent in Pause Mode Parameters,

Table 1 .................................................................................................5

Change to Table 8 ............................................................................13

Changed REFGND to GND_REF......................................................13

Table 146, and Figure 57.................................................................96

Rev. D | Page 3 of 110

ADuC7124/ADuC7126

Data Sheet

Added XMCFG Register Section, Table 147, Table 148,

Change to Power-On Reset Operation Section and

Table 149, and Table 150................................................................ 97

Added Figure 58 and Figure 59..................................................... 98

Added Figure 60 and Figure 61..................................................... 99

Changes to Figure 62 to Figure 65.............................................. 100

Changes to Figure 67 and Figure 68........................................... 101

Figure 69 ........................................................................................ 102

Added Figure 71 ........................................................................... 103

Changes to Ordering Guide........................................................ 104

9/10—Revision 0: Initial Version

Rev. D | Page 4 of 110

Data Sheet

ADuC7124/ADuC7126

GENERAL DESCRIPTION

The ADuC7124/ADuC7126 are fully integrated, 1 MSPS,

12-bit data acquisition system incorporating high performance

multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory

on a single chip.

The ADuC7124/ADuC7126 contain an advanced interrupt

controller. The vectored interrupt controller (VIC) allows every

interrupt to be assigned a priority level. It also supports nested

interrupts to a maximum level of eight per IRQ and FIQ. When

IRQ and FIQ interrupt sources are combined, a total of 16

nested interrupt levels are supported.

The ADC consists of up to 12 single-ended inputs. An additional

four inputs are available but are multiplexed with the four DAC

output pins. The ADC can operate in single-ended or differen-

tial input mode. The ADC input voltage range is 0 V to VREF.

A low drift band gap reference, temperature sensor, and voltage

comparator complete the ADC peripheral set.

On-chip factory firmware supports in-circuit download via the

UART serial interface port or the I²C port, while nonintrusive

emulation is also supported via the JTAG interface. These fea-

tures are incorporated into a low cost QuickStart™ development

system supporting this MicroConverter® family.

The DAC output range is programmable to one of three voltage

ranges. The DAC outputs have an enhanced feature of being

able to retain their output voltage during a watchdog or soft-

ware reset sequence.

The parts contain a 16-bit PWM with six output signals.

For communication purposes, the parts contain 2× I²C channels

that can be individually configured for master or slave mode.

An SPI interface supporting both master and slave modes is

also provided. Thirdly, 2× UART channels are provided. Each

UART contains a configurable 16-byte FIFO with receive and

transmit buffers.

The devices operate from an on-chip oscillator and a PLL

generating an internal high frequency clock of 41.78 MHz.

This clock is routed through a programmable clock divider

from which the MCU core clock operating frequency is

generated. The microcontroller core is an ARM7TDMI®,

16-bit/32-bit RISC machine, which offers up to 41 MIPS of

peak performance. Thirty-two kilobytes of SRAM and 126 kB

of nonvolatile Flash/EE memory are provided on-chip. The

ARM7TDMI core views all memory and registers as a single

linear array.

The parts operate from 2.7 V to 3.6 V and is specified over an

industrial temperature range of −40°C to +125°C. When operat-

ing at 41.78 MHz, the power dissipation is typically 120 m W.

The ADuC7124 is available in a 64-lead LFCSP package. The

ADuC7126 is available in a 80-lead LQFP package.

Rev. D | Page 5 of 110

ADuC7124/ADuC7126

SPECIFICATIONS

Data Sheet

AV_DD= IOV_DD= 2.7 V to 3.6 V, V_REF= 2.5 V internal reference, f_CORE= 41.78 MHz, T_A= −40°C to +125°C, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

ADC Power-Up Time

DC Accuracy^{1, 2}

Eight acquisition clocks and f_ADC/2

5

μs

Resolution

Integral Nonlinearity

12

Bits

LSB

0.6

1.0

0.5

+0.7/−0.6

1

1.5

2.5 V internal reference

1.0 V external reference

2.5 V internal reference

1.0 V external reference

ADC input is a dc voltage

Differential Nonlinearity^{3, 4}

+1/−0.9

DC Code Distribution

ENDPOINT ERRORS⁵

Offset Error

Offset Error Match

Gain Error

Gain Error Match

1

2

1

2

5

LSB

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk

f_IN= 10 kHz sine wave, f_SAMPLE= 1 MSPS

Includes distortion and noise components

69

dB

−78

−75

−90

Measured on adjacent channels; input channels

not being sampled have a 25 kHz sine wave

connected to them

ANALOG INPUT

Input Voltage Ranges⁴

Differential Mode

6

V_CMV_REF/2

V

Single-Ended Mode

Leakage Current

Input Capacitance

0 to V_REF

6

V

µA

pF

1

24

During ADC acquisition

0.47 µF from V_REFto AGND

ON-CHIP VOLTAGE REFERENCE

Output Voltage

2.5

V

Accuracy

5

mV

ppm/°C

dB

Ω

ms

T_A= 25°C

Reference Temperature Coefficient

Power Supply Rejection Ratio

Output Impedance

Internal V_REFPower-On Time

EXTERNAL REFERENCE INPUT

Input Voltage Range

DAC CHANNEL SPECIFICATIONS

DC Accuracy⁷

15

80

45

1

0.625

AV_DD

V

R_L= 5 kΩ, C_L= 100 pF

Resolution

Relative Accuracy

Differential Nonlinearity

Offset Error

Gain Error⁸

12

2

Bits

LSB

mV

%

1

10

1.0

Guaranteed monotonic

2.5 V internal reference

Gain Error Mismatch

0.1

%

% of full scale on DAC0

Rev. D | Page 6 of 110

Data Sheet

ADuC7124/ADuC7126

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ANALOG OUTPUTS

Output Voltage Range 0

Output Voltage Range 1

Output Voltage Range 2

Output Impedance

DAC IN OP AMP MODE

DAC Output Buffer in Op Amp Mode

Input Offset Voltage

Input Offset Voltage Drift

Input Offset Current

Input Bias Current

0 to DAC_REF

0 to 2.5

0 to DACV_DD

0.5

V

Ω

DAC_REFrange: DACGND to DACV_DD

0.4

4

2

2.5

70

4.5

78

12

3.2

75

mV

µV/°C

nA

dB

MHz

dB

µs

V/µs

dB

Gain

5 kΩ load

R_L= 5 kΩ, C_L= 100 pF

Unity Gain Frequency

CMRR

Settling Time

Output Slew Rate

PSRR

R_L= 5 kΩ, C_L= 100 pF

DAC AC CHARACTERISTICS

Voltage Output Settling Time

Digital-to-Analog Glitch Energy

10

µs

nV-sec

1 LSB change at major carry (where maximum

number of bits simultaneously change in the

DACxDAT register)

COMPARATOR

Input Offset Voltage

Input Bias Current

Input Voltage Range

Input Capacitance

Hysteresis^{4, 6}

15

1

mV

µA

V

pF

mV

AGND

2

AV_DD– 1.2

15

8.5

4

Hysteresis can be turned on or off via the

CMPHYST bit in the CMPCON register

100 mV overdrive and configured with

CMPRES = 11

Response Time

µs

TEMPERATURE SENSOR

Voltage Output at 25°C

1.415

1.392

3.914

4.52

3

V

ADuC7124

ADuC7126

ADuC7124

ADuC7126

Voltage Temperature Coefficient

mV/°C

°C

Accuracy

A single point calibration is required

θ_JAThermal Impedance

64-Lead LFCSP

24

°C/W

POWER SUPPLY MONITOR (PSM)

IOV_DDTrip Point Selection

2.79

3.07

2.5

V

%

V

Two selectable trip points

Power Supply Trip Point Accuracy

POWER-ON RESET

Of the selected nominal trip point voltage

2.41

WATCHDOG TIMER (WDT)

Timeout Period

0

512

sec

FLASH/EE MEMORY

Endurance⁹

Data Retention¹⁰

10,000

20

Cycles

Years

T_J= 85°C

DIGITAL INPUTS

Logic 1 Input Current

Logic 0 Input Current

All digital inputs excluding XCLKI and XCLKO

V_IH= V_DDor V_IH= 5 V

V_IL= 0 V; except TDI, TDO, and RTCK

V_IL= 0 V; TDI, TDO, and RTCK

0.2

−40

−80

5

1

µA

pF

−60

−120

Input Capacitance

Rev. D | Page 7 of 110

ADuC7124/ADuC7126

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS³

All logic inputs excluding XCLKI

V_INL, Input Low Voltage

V_INH, Input High Voltage

LOGIC OUTPUTS

0.8

V

2.0

2.4

All digital outputs excluding XCLKO

I_SOURCE= 1.6 mA

I_SINK= 1.6 mA

V_OH, Output High Voltage

V_OL, Output Low Voltage¹¹

CRYSTAL INPUTS XCLKI and XCLKO

Logic Inputs, XCLKI Only

V_INL, Input Low Voltage

V_INH, Input High Voltage

XCLKI Input Capacitance

XCLKO Output Capacitance

INTERNAL OSCILLATOR

V

0.4

0.8

1.6

20

V

pF

kHz

%

32.768

3

MCU CLOCK RATE⁴

From 32 kHz Internal Oscillator

From 32 kHz External Crystal

Using an External Clock

326

41.78

kHz

CD = 7

CD = 0

T_A= 85°C

T_A= 125°C

Core clock = 41.78 MHz

MHz

0.05

44

41.78

START-UP TIME

At Power-On

From Pause/Nap Mode

66

ms

µs

ms

2.6

247

1.58

1.7

CD = 0

CD = 7

From Sleep Mode

From Stop Mode

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay

Element Propagation Delay

POWER REQUIREMENTS^{12, 13}

Power Supply Voltage Range

12

2.5

ns

From input pin to output pin

AV_DDto AGND and IOV_DDto IOGND 2.7

Analog Power Supply Currents

AV_DDCurrent

3.6

V

165

0.02

µA

ADC in idle mode

DACV_DDCurrent¹⁴

Digital Power Supply Current

IOV_DDCurrent in Active Mode

Code executing from Flash/EE

CD = 7

CD = 3

CD = 0 (41.78 MHz clock)

T_A= 85°C

8.1

12.5

17

50

mA

µA

11.6

33.3

20.6

110

600

IOV_DDCurrent in Pause Mode

IOV_DDCurrent in Sleep Mode

30

680

µA

T_A= 125°C

Additional Power Supply Currents

ADC

1.26

0.7

315

mA

µA

At 1 MSPS

At 62.5 kSPS

Per DAC

DAC

Rev. D | Page 8 of 110

Data Sheet

ADuC7124/ADuC7126

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

2.5 V reference, T_A= 25°C

ESD TESTS

HBM Passed Up To

FICDM Passed Up To

3

1.5

kV

¹All ADC channel specifications are guaranteed during normal core operation.

²Apply to all ADC input channels.

³Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).

⁴Not production tested but supported by design and/or characterization data on production release.

⁵Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 37. Based on external ADC

system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).

⁶The input signal can be centered on any dc common-mode voltage (V_CM) as long as this value is within the ADC voltage input range specified.

⁷DAC linearity is calculated using a reduced code range of 100 to 3995.

⁸DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V V_REF

.

⁹Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

¹⁰Retention lifetime equivalent at junction temperature (T_J) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

¹¹Test carried out with a maximum of eight I/Os set to a low output level.

¹²Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with

3.6 V supply, and sleep mode with 3.6 V supply.

¹³IOV_DDpower supply current increases typically by 2 mA during a Flash/EE erase cycle.

¹⁴This current must be added to the AV_DDcurrent.

TIMING SPECIFICATIONS

I²C Timing

Table 2. I²C Timing in Fast Mode (400 kHz)

Slave

Max

Master

Typ

Parameter

Description

Min

200

100

300

100

0

100

1.3

Unit

ns

µs

t_L

t_H

SCL low pulse width

SCL high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCL and SDA

Fall time for both SCL and SDA

1360

1140

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

t_R

740

400

800

200

300

ns

t_F

Table 3. I²C Timing in Standard Mode (100 kHz)

Slave

Parameter

Description

Min

4.7

4.0

250

0

4.7

4.0

4.7

Max

Unit

t_L

t_H

SCL low pulse width

SCL high pulse width

Start condition hold time

Data setup time

Data hold time

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCL and SDA

Fall time for both SCL and SDA

µs

ns

µs

ns

µs

ns

t_SHD

t_DSU

t_DHD

t_RSU

t_PSU

t_BUF

t_R

3.45

1

300

t_F

Rev. D | Page 9 of 110

ADuC7124/ADuC7126

Data Sheet

t_BUF

t_R

SDA (I/O)

MSB

LSB

ACK

MSB

t_F

t_DSU

t_DHD

t_PSU

t_R

t_SHD

t_RSU

t_H

1

2–7

8

9

1

SCL (I)

t_L

P

S

S(R)

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 2. I²C-Compatible Interface Timing

SPI Timing

Table 4. SPI Master Mode Timing (Phase Mode = 1)

Parameter

Description

Min

Typ

Max

Unit

ns

t_SL

t_SH

SCLK low pulse width¹

SCLK high pulse width¹

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

(SPIDIV + 1) × t_UCLK

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

25

1 × t_UCLK

2 × t_UCLK

5

12.5

Data output rise time

SCLK rise time

SCLK fall time

t_SF

ns

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DF

t_DR

MOSI

MISO

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 3. SPI Master Mode Timing (Phase Mode = 1)

Rev. D | Page 10 of 110

Data Sheet

ADuC7124/ADuC7126

Table 5. SPI Master Mode Timing (Phase Mode = 0)

Parameter

Description

Min

Typ

Max

Unit

ns

t_SL

t_SH

SCLK low pulse width¹

(SPIDIV + 1) × t_UCLK

SCLK high pulse width¹

Data output valid after SCLK edge

Data output setup before SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

Data output rise time

SCLK rise time

SCLK fall time

t_DAV

t_DOSU

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

25

75

1 × t_UCLK

2 × t_UCLK

5

12.5

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DOSU

t_DF

t_DR

MOSI

MISO

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 4. SPI Master Mode Timing (Phase Mode = 0)

Rev. D | Page 11 of 110

ADuC7124/ADuC7126

Data Sheet

Table 6. SPI Slave Mode Timing (Phase Mode = 1)

Parameter

Description

Min

Typ

Max

Unit

t_CS

CS to SCLK edge

200

ns

t_SL

t_SH

SCLK low pulse width

SCLK high pulse width

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

Data output rise time

SCLK rise time

SCLK fall time

CS high after SCLK edge

(SPIDIV + 1) × t_HCLK

ns

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

25

1 × t_UCLK

2 × t_UCLK

5

12.5

t_SF

t_SFS

0

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLK

(POLARITY = 1)

t_DAV

t_DF

t_DR

MISO

MOSI

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 5. SPI Slave Mode Timing (Phase Mode = 1)

Rev. D | Page 12 of 110

Data Sheet

ADuC7124/ADuC7126

Table 7. SPI Slave Mode Timing (Phase Mode = 0)

Parameter

Description

Min

Typ

Max

Unit

t_CS

CS to SCLK edge

200

ns

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

t_SF

t_DOCS

t_SFS

SCLK low pulse width

SCLK high pulse width

Data output valid after SCLK edge

Data input setup time before SCLK edge¹

Data input hold time after SCLK edge¹

Data output fall time

Data output rise time

SCLK rise time

SCLK fall time

Data output valid after CS edge

CS high after SCLK edge

(SPIDIV + 1) × t_HCLK

ns

25

1 × t_UCLK

2 × t_UCLK

5

12.5

25

0

¹t_UCLK= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.

CS

t_CS

t_SFS

SCLK

(POLARITY = 0)

t_SH

t_SL

t_SF

t_SR

SCLK

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

MISO

MOSI

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 6. SPI Slave Mode Timing (Phase Mode = 0)

Rev. D | Page 13 of 110

ADuC7124/ADuC7126

Data Sheet

ABSOLUTE MAXIMUM RATINGS

AGND = GND_REF= DACGND = GND_REF, T_A= 25°C, unless

otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 8.

Parameter

Rating

AV_DDto IOV_DD

AGND to DGND

−0.3 V to +0.3 V

−0.3 V to +6 V

−0.3 V to +5.3 V

−0.3 V to IOV_DD+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

IOV_DDto IOGND, AV_DDto AGND

Digital Input Voltage to IOGND

Digital Output Voltage to IOGND

V_REFto AGND

Analog Inputs to AGND

Analog Outputs to AGND

Only one absolute maximum rating can be applied at any one time.

ESD CAUTION

Operating Temperature Range, Industrial –40°C to +125°C

Storage Temperature Range

Junction Temperature

θ_JAThermal Impedance

64-Lead LFCSP

−65°C to +150°C

150°C

24°C/W

38°C/W

80-Lead LQFP

Peak Solder Reflow Temperature

SnPb Assemblies (10 sec to 30 sec)

RoHS Compliant Assemblies

(20 sec to 40 sec)

240°C

260°C

Rev. D | Page 14 of 110

Data Sheet

ADuC7124/ADuC7126

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

ADC4

ADC5

ADC6

ADC7

ADC8

1

2

3

4

5

6

7

8

9

48 P1.3/SPM3/CTS/I2C1SDA/PLAI[3]

47 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2

46 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3

45 P4.1/PLAO[9]/SOUT1

44 P4.0/PLAO[8]/SIN1

43 P1.6/SPM6/PLAI[6]

ADC9

ADCNEG

DACGND

42 P1.7/SPM7/DTR/SPICS/PLAO[0]

ADuC7124

TOP VIEW

(Not to Scale)

41 P3.7/PWM

40 P3.6/PWM

/PLAI[15]

/PLAI[14]

SYNC

DACV

DD

TRIP

DAC0/ADC12 10

DAC1/ADC13 11

TMS 12

39 IOV

DD

38 IOGND

P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0

37

36 P2.0/SPM9/PLAO[5]/CONV

TDI 13

/SOUT0

START

XCLKO 14

XCLKI 15

/PLAI[7] 16

35 IRQ1/P0.5/ADC

34 IRQ0/P0.4/PWM

33 RST

/PLAO[2]

/PLAO[1]

BUSY

TRIP

BM/P0.0/CMP

OUT

NC = NO CONNECT

NOTES

1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB TO ENSURE PROPER

HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 7. ADuC7124 Pin Configuration

Table 9. Pin Function Descriptions (ADuC7124 64-Lead LFCSP)

Pin No.

Mnemonic

Exposed Paddle

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

ADCNEG

Description

0

1

2

3

4

5

6

7

Exposed Paddle. The LFCSP_VQ has an exposed paddle that must be left unconnected.

Single-Ended or Differential Analog Input 4.

Single-Ended or Differential Analog Input 5.

Single-Ended or Differential Analog Input 6.

Single-Ended or Differential Analog Input 7.

Single-Ended or Differential Analog Input 8.

Single-Ended or Differential Analog Input 9.

Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be

connected to the ground of the signal to convert. This bias point must be between 0 V

and 1 V.

8

DACGND

Ground for the DAC. Typically connected to AGND.

9

DACV_DD

3.3 V Power Supply for the DACs. Must be connected to AV_DD.

10

DAC0/ADC12

DAC0 Voltage Output (DAC0).

Single-Ended or Differential Analog Input 12 (ADC12).

11

DAC1/ADC13

DAC1 Voltage Output (DAC1).

Single-Ended or Differential Analog Input 13 (ADC13).

12

13

TMS

TDI

JTAG Test Port Input, Test Mode Select. Debug and download access.

JTAG Test Port Input, Test Data In.

Rev. D | Page 15 of 110

ADuC7124/ADuC7126

Data Sheet

Pin No.

14

Mnemonic

XCLKO

Description

Output from the Crystal Oscillator Inverter.

15

XCLKI

Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator

Circuits.

16

BM/P0.0/CMP_OUT/PLAI[7]

Multifunction I/O Pin.

Boot mode (BM). The ADuC7124 enters download mode if BM is low at reset and

executes code if BM is pulled high at reset through a 1 kΩ resistor.

General-Purpose Input and Output Port 0.0 (P0.0).

Voltage Comparator Output (CMP_OUT

)

Programmable Logic Array Input Element 7 (PLAI[7]).

17

18

DGND

LV_DD

Ground for Core Logic.

2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a

0.47 μF capacitor to DGND only.

19

20

21

IOV_DD

IOGND

P4.6/PLAO[14]

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

Ground for GPIO. Typically connected to DGND.

General-Purpose Input and Output Port 4.6 (P4.6).

Programmable Logic Array Output Element 14 (PLAO[14]).

22

23

P4.7/PLAO[15]

General-Purpose Input and Output Port 4.7 (P4.7).

Programmable Logic Array Output Element 15 (PLAO[15]).

Multifunction Pin, Driven Low After Reset.

General-Purpose Output Port 0.6 (P0.6).

Timer1 Input (T1).

P0.6/T1/MRST/PLAO[3]

Power-On Reset Output (MRST).

Programmable Logic Array Output Element 3 (PLAO[3]).

24

25

26

TCK

TDO

JTAG Test Port Input, Test Clock. Debug and download access.

JTAG Test Port Output, Test Data Out.

General-Purpose Input and Output Port 3.0 (P3.0).

PWM Phase 0 (PWM0).

P3.0/PWM0/PLAI[8]

Programmable Logic Array Input Element 8 (PLAI[8]).

27

28

29

30

P3.1/PWM1/PLAI[9]

P3.2/PWM2/PLAI[10]

P3.3/PWM3/PLAI[11]

P0.3/TRST/ADC_BUSY

General-Purpose Input and Output Port 3.1 (P3.1).

PWM Phase 1 (PWM1).

Programmable Logic Array Input Element 9 (PLAI[9]).

General-Purpose Input and Output Port 3.2 (P3.2).

PWM Phase 2 (PWM2).

Programmable Logic Array Input Element 10 (PLAI[10]).

General-Purpose Input and Output Port 3.3 (P3.3).

PWM Phase 3 (PWM3).

Programmable Logic Array Input Element 11 (PLAI[11]).

General-Purpose Input and Output Port 0.3 (P0.3).

JTAG Test Port Input, Test Reset (TRST). JTAG reset input. Debug and download access. If

this pin is held low, JTAG access is not possible because the JTAG interface is held in reset

and P0.1/P0.2/P0.3 are configured as GPIO pins.

ADC_BUSYSignal Output (ADC_BUSY).

31

32

P3.4/PWM4/PLAI[12]

P3.5/PWM5/PLAI[13]

General-Purpose Input and Output Port 3.4 (P3.4).

PWM Phase 4 (PWM4).

Programmable Logic Array Input 12 (PLAI[12]).

General-Purpose Input and Output Port 3.5 (P3.5).

PWM Phase 5 (PWM5).

Programmable Logic Array Input Element 13 (PLAI[13]).

33

34

RST

Reset Input, Active Low.

IRQ0/P0.4/PWM_TRIP/PLAO[1]

Multifunction I/O Pin.

External Interrupt Request 0, Active High (IRQ0).

General-Purpose Input and Output Port 0.4 (P0.4).

PWM Trip External Input (PWM_TRIP).

Programmable Logic Array Output Element 1 (PLAO[1]).

Rev. D | Page 16 of 110

Data Sheet

ADuC7124/ADuC7126

Pin No.

Mnemonic

Description

35

IRQ1/P0.5/ADC_BUSY/PLAO[2]

Multifunction I/O Pin.

External Interrupt Request 1, Active High (IRQ1).

General-Purpose Input and Output Port 0.5 (P0.5).

ADC_BUSYSignal Output (ADC_BUSY).

Programmable Logic Array Output Element 2 (PLAO[2]).

36

37

P2.0/SPM9/PLAO[5]/CONV_START/SOUT0

P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0

General-Purpose Input and Output Port 2.0 (P2.0).

Serial Port Multiplexed (SPM9).

Programmable Logic Array Output Element 5 (PLAO[5]).

Start Conversion Input Signal for ADC (CONV_START).

UART0 Output (SOUT0).

General-Purpose Input and Output Port 0.7 (P0.7).

Output for External Clock Signal (ECLK).

Input to the Internal Clock Generator Circuits (XCLK).

Serial Port Multiplexed (SPM8).

Programmable Logic Array Output Element 4 (PLAO[4]).

UART0 Input (SIN0).

38

39

40

IOGND

IOV_DD

P3.6/PWM_TRIP/PLAI[14]

Ground for GPIO. Typically connected to DGND.

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

General-Purpose Input and Output Port 3.6 (P3.6).

PWM Safety Cutoff (PWM_TRIP).

Programmable Logic Array Input Element 14 (PLAI[14]).

41

42

P3.7/PWM_SYNC/PLAI[15]

General-Purpose Input and Output Port 3.7 (P3.7).

PWM Synchronization Input/Output (PWM_SYNC).

Programmable Logic Array Input Element 15 (PLAI[15]).

General-Purpose Input and Output Port 1.7 (P1.7).

Serial Port Multiplexed. UART, SPI (SPM7).

Data Terminal Ready (DTR).

P1.7/SPM7/DTR/SPICS/PLAO[0]

Chip Select (SPICS).

Programmable Logic Array Output Element 0 (PLAO[0]).

43

44

45

46

P1.6/SPM6/PLAI[6]

P4.0/PLAO[8]/SIN1

P4.1/PLAO[9]/SOUT1

General-Purpose Input and Output Port 1.6 (P1.6).

Serial Port Multiplexed (SPM6).

Programmable Logic Array Input Element 6 (PLAI[6]).

General-Purpose Input and Output Port 4.0 (P4.0).

Programmable Logic Array Output Element 8 (PLAO[8]).

UART1 Input (SIN1).

General-Purpose Input and Output Port 4.1 (P4.1).

Programmable Logic Array Output Element 9 (PLAO[9]).

UART1 Output (SOUT1).

P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 General-Purpose Input and Output Port 1.5 (P1.5).

Serial Port Multiplexed. UART, SPI (SPM5).

Data Carrier Detect (DCD).

Master Input, Slave Output (SPI MISO).

Programmable Logic Array Input Element 5 (PLAI[5]).

External Interrupt Request 3, Active High (IRQ3).

47

P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2

General-Purpose Input and Output Port 1.4 (P1.4).

Serial Port Multiplexed. UART, SPI (SPM4).

Ring Indicator (RI).

Serial Clock Input/Output (SPI SCLK).

Programmable Logic Array Input Element 4 (PLAI[4]).

External Interrupt Request 2, Active High (IRQ2).

48

49

P1.3/SPM3/CTS/I2C1SDA/PLAI[3]

P1.2/SPM2/RTS/I2C1SCL/PLAI[2]

General-Purpose Input and Output Port 1.3 (P1.3).

Serial Port Multiplexed. UART, I2C1 (SPM3).

Clear to Send (CTS).

I2C1 (I2C1SDA).

Programmable Logic Array Input Element 3 (PLAI[3]).

General-Purpose Input and Output Port 1.2 (P1.2).

Serial Port Multiplexed (SPM2).

Ready to Send (RTS).

I2C1 (I2C1SCL).

Programmable Logic Array Input Element 2 (PLAI[2]).

Rev. D | Page 17 of 110

ADuC7124/ADuC7126

Data Sheet

Pin No.

Mnemonic

Description

50

P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1]

General-Purpose Input and Output Port 1.1 (P1.1).

Serial Port Multiplexed (SPM1).

UART download pin, UART0 Output (SOUT0).

I2C0 (I2C0SDA).

Programmable Logic Array Input Element 1 (PLAI[1]).

51

P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0]

General-Purpose Input and Output Port 1.0 (P1.0).

Timer1 Input (T1).

Serial Port Multiplexed (SPM0).

UART download pin, UART0 Input (SIN0).

I2C0 (I2C0SCL).

Programmable Logic Array Input Element 0 (PLAI[0]).

52

53

54

P4.2/PLAO[10]

P4.3/PLAO[11]

P4.4/PLAO[12]

General-Purpose Input and Output Port 4.2 (P4.2).

Programmable Logic Array Output Element 10 (PLAO[10]).

General-Purpose Input and Output Port 4.3 (P4.3).

Programmable Logic Array Output Element 11 (PLAO[11]).

General-Purpose Input and Output Port 4.4 (P4.4).

Programmable Logic Array Output Element 12 (PLAO[12]).

55

56

RTCK

V_REF

JTAG Test Port Output, JTAG Return Test Clock.

2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using

the internal reference.

57

58

59

60

DAC_REF

AV_DD

AGND

GND_REF

External Voltage Reference for the DACs. Range: DACGND to DACV_DD.

3.3 V Analog Power.

Analog Ground. Ground reference point for the analog circuitry.

Ground Voltage Reference for the ADC. For optimal performance, the analog power

supply should be separated from IOGND and DGND.

61

62

63

ADC0

ADC1

ADC2/CMP0

Single-Ended or Differential Analog Input 0.

Single-Ended or Differential Analog Input 1.

Single-Ended or Differential Analog Input 2 (ADC2).

Comparator Positive Input (CMP0).

64

ADC3/CMP1

Single-Ended or Differential Analog Input 3 (ADC3).

Comparator Negative Input (CMP1).

Rev. D | Page 18 of 110

Data Sheet

ADuC7124/ADuC7126

80 79 78

76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

77

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

ADC4

ADC5

P1.3/SPM3/CTS/I2C1SDA/PLAI[3]

PIN 1

2

P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2

P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3

P4.1/SPM11/SOUT1/AD9/PLAO[9]

P4.0/SPM10/SIN1/AD8/PLAO[8]

P1.6/SPM6/PLAI[6]

3

ADC6

4

ADC7

5

ADC8

6

ADC9

7

ADC10

ADCNEG

DACGND

P1.7/SPM7/DTR/SPICS/PLAO[0]

8

P3.7/AD7/PWM

P3.6/AD6/PWM

/PLAI[15]

SYNC

9

/PLAI[14]

TRIP

ADuC7126

TOP VIEW

10

11

12

13

14

15

16

17

18

19

20

DACV

P2.2/RS/PWM1/PLAO[7]

P2.1/WS/PWM0/PLAO[6]

P2.3/SPM12/AE/SIN1

DD

DAC0/ADC12

DAC1/ADC13

DAC2/ADC14

DAC3/ADC15

TMS

IOV

DD

IOGND

P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0

TDI

P2.0/SPM9/PLAO[5]/CONV

P2.7/PWM3/MS3

/SOUT0

START

P0.1/PWM4/BLE

XCLKO

IRQ1/P0.5/ADC

/PLAO[2]/MS2

/PLAO[1]/MS1

BUSY

XCLKI

IRQ0/P0.4/PWM

TRIP

BM/P0.0/CMP

/PLAI[7]/MS0

RST

OUT

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 8. ADuC7126 Pin Configuration

Table 10. Pin Function Descriptions (ADuC7126 80-Lead LQFP)

Pin No. Mnemonic Description

1

2

3

4

5

6

7

8

ADC4

ADC5

ADC6

ADC7

ADC8

ADC9

ADC10

ADCNEG

Single-Ended or Differential Analog Input 4.

Single-Ended or Differential Analog Input 5.

Single-Ended or Differential Analog Input 6.

Single-Ended or Differential Analog Input 7.

Single-Ended or Differential Analog Input 8.

Single-Ended or Differential Analog Input 9.

Single-Ended or Differential Analog Input 10.

Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be

connected to the ground of the signal to convert. This bias point must be between 0 V

and 1 V.

9

10

DACGND

DACV_DD

Ground for the DAC. Typically connected to AGND.

3.3 V Power Supply for the DACs. Must be connected to AV_DD.

Rev. D | Page 19 of 110

ADuC7124/ADuC7126

Data Sheet

Pin No. Mnemonic

Description

11

12

13

14

DAC0/ADC12

DAC1/ADC13

DAC2/ADC14

DAC3/ADC15

DAC0 Voltage Output (DAC0).

Single-Ended or Differential Analog Input 12 (ADC12).

DAC1 Voltage Output (DAC1).

Single-Ended or Differential Analog Input 13 (ADC13).

DAC2 Voltage Output (DAC2).

Single-Ended or Differential Analog Input 14 (ADC14).

DAC3 Voltage Output (DAC3).

Single-Ended or Differential Analog Input 15 (ADC15).

15

16

17

TMS

TDI

P0.1/PWM4/BLE

JTAG Test Port Input, Test Mode Select. Debug and download access.

JTAG Test Port Input, Test Data In. Debug and download access.

General-Purpose Input and Output Port 0.1 (P0.1).

PWM Phase 4 (PWM4).

External Memory Byte Low Enable (BLE).

This pin does not work as GPIO on I²C versions of the chip.

18

19

XCLKO

XCLKI

Output from the Crystal Oscillator Inverter.

Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator

Circuits.

20

BM/P0.0/CMP_OUT/PLAI[7]/MS0

Multifunction I/O Pin.

Boot Mode Entry Pin (BM). The ADuC7126 enters UART download mode if BM is low at

reset and executes code if BM is pulled high at reset through a 1 kΩ resistor.. The

ADuC7126 enters I²C download mode in I²C version parts if BM is low at reset with a

flash address of 0x800014 = 0xFFFFFFFFF. The ADuC7126 executes code if BM is pulled

high at reset or if BM is low at reset with a flash address 0x800014 ≠ 0xFFFFFFFFF.

General-Purpose Input and Output Port 0.0 (P0.0).

Voltage Comparator Output/Programmable Logic Array Input Element 7 (CMP_OUT).

External Memory Select 0 (MS0). By default, this pin is configured as GPIO.

21

22

DGND

LV_DD

Ground for Core Logic.

2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47

μF capacitor to DGND only.

23

24

25

IOV_DD

IOGND

P4.6/AD14/PLAO[14]

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

Ground for GPIO. Typically connected to DGND.

General-Purpose Input and Output Port 4.6 (P4.6).

External Memory Interface (AD14).

Programmable Logic Array Output Element 14 (PLAO[14]).

26

27

P4.7/AD15/PLAO[15]

General-Purpose Input and Output Port 4.7 (P4.7).

External Memory Interface (AD15).

Programmable Logic Array Output Element 15 (PLAO[15]).

Multifunction Pin, Driven Low After Reset.

General-Purpose Output Port 0.6 (P0.6).

Timer1 Input (T1).

P0.6/T1/MRST/PLAO[3]/MS3

Power-On Reset Output (MRST).

Programmable Logic Array Output Element 3 (PLAO[3]).

External Memory Select 3 (MS3).

28

29

30

TCK

TDO

P0.2/PWM5/BHE

JTAG Test Port Input, Test Clock. Debug and download access.

JTAG Test Port Output, Test Data Out. Debug and download access.

General-Purpose Input and Output Port 0.2 (P0.2).

PWM Phase 5 (PWM5).

External Memory Byte High Enable (BHE).

This pin does not work as GPIO on I²C versions of the chip.

31

32

P3.0/AD0/PWM0/PLAI[8]

P3.1/AD1/PWM1/PLAI[9]

General-Purpose Input and Output Port 3.0 (P3.0).

External Memory Interface (AD0).

PWM Phase 0 (PWM0).

Programmable Logic Array Input Element 8 (PLAI[8]).

General-Purpose Input and Output Port 3.1 (P3.1).

External Memory Interface (AD1).

PWM Phase 1 (PWM1).

Programmable Logic Array Input Element 9 (PLAI[9]).

Rev. D | Page 20 of 110

Data Sheet

ADuC7124/ADuC7126

Pin No. Mnemonic

Description

33

34

35

P3.2/AD2/PWM2/PLAI[10]

General-Purpose Input and Output Port 3.2 (P3.2).

External Memory Interface (AD2).

PWM Phase 2 (PWM2).

Programmable Logic Array Input Element 10 (PLAI[10]).

General-Purpose Input and Output Port 3.3 (P3.3).

External Memory Interface (AD3).

PWM Phase 3 (PWM3).

Programmable Logic Array Input Element 11 (PLAI[11]).

General-Purpose Input and Output Port 2.4 (P2.4).

Serial Port Multiplexed (SPM13)

PWM Phase 0 (PWM0).

P3.3/AD3/PWM3/PLAI[11]

P2.4/SPM13/PWM0/MS0/SOUT1

External Memory Select 0 (MS0).

UART1 Output (SOUT1).

36

P0.3/TRST/A16/ADC_BUSY

General-Purpose Input and Output Port 0.3 (P0.3).

JTAG Test Port Input, Test Reset (TRST).JTAG Reset Input. Debug and download access. If

this pin is held low, JTAG access is not possible because the JTAG interface is held in

reset and P0.1/P0.2/P0.3 are configured as GPIO pins.

Address Line (A16).

ADC_BUSYSignal Output (ADC_BUSY).

37

38

39

P2.5/PWM1/MS1

General-Purpose Input and Output Port 2.5 (P2.5).

PWM Phase 1 (PWM1).

External Memory Select 1 (MS1).

General-Purpose Input and Output Port 2.6 (P2.6).

PWM Phase 2 (PWM2).

External Memory Select 2 (MS2).

P2.6/PWM2/MS2

P3.4/AD4/PWM4/PLAI[12]

General-Purpose Input and Output Port 3.4 (P3.4).

External Memory Interface (AD4).

PWM Phase 4 (PWM4).

Programmable Logic Array Input 12 (PLAI[12]).

40

P3.5/AD5/PWM5/PLAI[13]

General-Purpose Input and Output Port 3.5 (P3.5).

External Memory Interface (AD5).

PWM Phase 5 (PWM5).

Programmable Logic Array Input Element 13 (PLAI[13]).

41

42

RST

Reset Input, Active Low.

IRQ0/P0.4/PWM_TRIP/PLAO[1]/MS1

Multifunction I/O Pin.

External Interrupt Request 0, Active High (IRQ0).

General-Purpose Input and Output Port 0.4 (P0.4).

PWM Trip External Input (PWM_TRIP).

Programmable Logic Array Output Element 1 (PLAO[1]).

External Memory Select 1 (MS1)..

43

IRQ1/P0.5/ADC_BUSY/PLAO[2]/MS2

Multifunction I/O Pin.

External Interrupt Request 1, Active High (IRQ1).

General-Purpose Input and Output Port 0.5 (P0.5).

ADC_BUSYSignal Output (ADC_BUSY).

Programmable Logic Array Output Element 2 (PLAO[2]).

External Memory Select 2 (MS2).

44

45

P2.7/PWM3/MS3

General-Purpose Input and Output Port 2.7 (P2.7).

PWM Phase 3 (PWM3).

External Memory Select 3 (MS3).

General-Purpose Input and Output Port 2.0 (P2.0).

Serial Port Multiplexed (SPM9).

P2.0/SPM9/PLAO[5]/CONV_START/SOUT0

Programmable Logic Array Output Element 5 (PLAO[5]).

Start Conversion Input Signal for ADC (CONV_START).

UART0 Output (SOUT0).

46

47

P0.7/SPM8/ECLK/XCLK/PLAO[4]/SIN0

General-Purpose Input and Output Port 0.7 (P0.7).

Serial Port Multiplexed (SPM8).

Output for External Clock Signal (ECLK).

Input to the Internal Clock Generator Circuits (XCLK).

Programmable Logic Array Output Element 4 (PLAO[4]).

UART0 Input (SIN0).

IOGND

Ground for GPIO. Typically connected to DGND.

Rev. D | Page 21 of 110

ADuC7124/ADuC7126

Data Sheet

Pin No. Mnemonic

Description

48

49

IOV_DD

P2.3/SPM12/AE/SIN1

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

General-Purpose Input and Output Port 2.3 (P2.3).

Serial Port Multiplexed (SPM12).

External Memory Access Enable (AE).

UART1 Input (SIN1).

50

51

52

53

54

P2.1/WS/PWM0/PLAO[6]

P2.2/RS/PWM1/PLAO[7]

General-Purpose Input and Output Port 2.1 (P2.1).

External Memory Write Strobe (WS).

PWM Phase 0 (PWM0).

Programmable Logic Array Output Element 6 (PLAO[6]).

General-Purpose Input and Output Port 2.2 (P2.2).

External Memory Read Strobe (RS).

PWM Phase 1 (PWM1).

Programmable Logic Array Output Element 7 (PLAO[7]).

General-Purpose Input and Output Port 3.6 (P3.6).

External Memory Interface (AD6).

PWM Safety Cutouff (PWM_TRIP).

Programmable Logic Array Input Element 14 (PLAI[14]).

General-Purpose Input and Output Port 3.7 (P3.7).

External Memory Interface (AD7).

PWM Synchronization (PWM_SYNC).

Programmable Logic Array Input Element 15 (PLAI[15]).

P3.6/AD6/PWM_TRIP/PLAI[14]

P3.7/AD7/PWM_SYNC/PLAI[15]

P1.7/SPM7/DTR/SPICS/PLAO[0]

General-Purpose Input and Output Port 1.7 (P1.7).

Serial Port Multiplexed (SPM7).

Data Terminal Ready (DTR).

Chip Select (SPICS).

Programmable Logic Array Output Element 0 (PLAO[0]).

55

56

P1.6/SPM6/PLAI[6]

General-Purpose Input and Output Port 1.6 (P1.6).

Serial Port Multiplexed (SPM6).

Programmable Logic Array Input Element 6 (PLAI[6]).

General-Purpose Input and Output Port 4.0 (P4.0).

Serial Port Multiplexed (SPM10).

P4.0/SPM10/SIN1/AD8/PLAO[8]

UART1 Input (SIN1).

External Memory Interface (AD8).

Programmable Logic Array Output Element 8 (PLAO[8]).

57

58

P4.1/SPM11/SOUT1/AD9/PLAO[9]

General-Purpose Input and Output Port 4.1 (P4.1).

Serial Port Multiplexed (SPM11).

UART1 Output (SOUT1).

External Memory Interface (AD9).

Programmable Logic Array Output Element 9 (PLAO[9]).

P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3 General-Purpose Input and Output Port 1.5 (P1.5).

Serial Port Multiplexed (SPM5).

Data Carrier Detect (DCD).

Master Input, Slave Output (SPI MISO).

Programmable Logic Array Input Element 5 (PLAI[5]).

External Interrupt Request 3, Active High (IRQ3).

59

P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2

General-Purpose Input and Output Port 1.4 (P1.4).

Serial Port Multiplexed (SPM4).

Ring Indicator (RI).

Serial Clock Input/Output (SPI SCLK).

Programmable Logic Array Input Element 4 (PLAI[4]).

External Interrupt Request 2, Active High (IRQ2).

60

61

P1.3/SPM3/CTS/I2C1SDA/PLAI[3]

P1.2/SPM2/RTS/I2C1SCL/PLAI[2]

General-Purpose Input and Output Port 1.3 (P1.3).

Serial Port Multiplexed (SPM3).

Clear to Send (CTS).

I2C1 (I2C1SDA).

Programmable Logic Array Input Element 3 (PLAI[3]).

General-Purpose Input and Output Port 1.2 (P1.2).

Serial Port Multiplexed (SPM2).

Ready to Send (RTS).

I2C1 (I2C1SCL).

Programmable Logic Array Input Element 2 (PLAI[2]).

Rev. D | Page 22 of 110

Data Sheet

ADuC7124/ADuC7126

Pin No. Mnemonic

Description

62

P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1]

General-Purpose Input and Output Port 1.1 (P1.1).

Serial Port Multiplexed (SPM1).

UART0 Output (SOUT0).

I2C0 (I2C0SDA).

Programmable Logic Array Input Element 1 (PLAI[1]).

63

P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0]

General-Purpose Input and Output Port 1.0 (P1.0).

Timer1 Input (T1).

Serial Port Multiplexed (SPM0).

UART0 Input (SIN0).

I2C0 (I2C0SCL).

Programmable Logic Array Input Element 0 (PLAI[0]).

64

65

66

67

P4.2/AD10/PLAO[10]

P4.3/AD11/PLAO[11]

P4.4/AD12/PLAO[12]

P4.5/AD13/PLAO[13]/RTCK

General-Purpose Input and Output Port 4.2 (P4.2).

External Memory Interface (AD10).

Programmable Logic Array Output Element 10 (PLAO[10]).

General-Purpose Input and Output Port 4.3 (P4.3).

External Memory Interface (AD11).

Programmable Logic Array Output Element 11 (PLAO[11]).

General-Purpose Input and Output Port 4.4 (P4.4).

External Memory Interface (AD12).

Programmable Logic Array Output Element 12 (PLAO[12]).

General-Purpose Input and Output Port 4.5 (P4.5).

External Memory Interface (AD13).

Programmable Logic Array Output Element 13 (PLAO[13]).

JTAG Return Test Clock (RTCK).

68

69

70

IOV_DD

IOGND

V_REF

3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.

Ground for GPIO. Typically connected to DGND.

2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using

the internal reference.

71

72

DAC_REF

AV_DD

External Voltage Reference for the DACs. Range: DACGND to DACV_DD.

3.3 V Analog Power.

73, 74

75

AGND

GND_REF

Analog Ground. Ground reference point for the analog circuitry.

Ground Voltage Reference for the ADC. For optimal performance, the analog power

supply should be separated from IOGND and DGND.

76

77

78

79

ADC11

ADC0

ADC1

ADC2/CMP0

Single-Ended or Differential Analog Input 11.

Single-Ended or Differential Analog Input 0.

Single-Ended or Differential Analog Input 1.

Single-Ended or Differential Analog Input 2 (ADC2).

Comparator Positive Input (CMP0).

80

ADC3/CMP1

Single-Ended or Differential Analog Input 3 (ADC3).

Comparator Negative Input (CMP1).

Rev. D | Page 23 of 110

ADuC7124/ADuC7126

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.4

0.3

0.2

0.1

0

0.3

0.2

0.1

0

–0.1

–0.2

–0.1

–0.2

ADC CODES

Figure 11. Typical DNL Error,

Figure 9. Typical DNL Error,

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = DAC1/ADC13, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst Case Positive = 0.40 LSB, Code 607

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = ADC0, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst Case Positive = 0.38 LSB, Code 1567

Worst Case Negative= −0.27 LSB, Code 2486

Worst Case Negative= −0.24 LSB, Code 4094

0.6

0.5

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

ADC CODES

Figure 12. Typical INL Error,

Figure 10. Typical INL Error,

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = DAC1/ADC13, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst Case Positive = 0.58 LSB, Code 480

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = ADC0, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst Case Positive = 0.60 LSB, Code 1890

Worst Case Negative= −0.54 LSB, Code 3614

Worst Case Negative= −0.54 LSB, Code 3485

Rev. D | Page 24 of 110

Data Sheet

ADuC7124/ADuC7126

0.4

0.3

0.2

0.1

0

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.1

–0.2

ADC CODES

Figure 13. Typical DNL Error,

Figure 15. Typical DNL Error,

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst-Case Positive = 0.42 LSB, Code 3583

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = DAC3/ADC15, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst-Case Positive = 0.41 LSB, Code 2016

Worst-Case Negative = −0.32 LSB, Code 3073

Worst-Case Negative = −0.26 LSB, Code 3841

0.8

0.6

0.4

0.2

0

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.2

–0.4

–0.6

–0.8

ADC CODES

Figure 14. Typical INL Error,

Figure 16. Typical INL Error,

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = ADC8, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst-Case Positive = 0.64 LSB, Code 802

Temperature 25°C, V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = DAC3/ADC15, ADCCN = ADC0, Sampling Rate = 345 kHz

Worst-Case Positive = 0.55 LSB, Code 738

Worst-Case Negative = −0.69 LSB, Code 3485

Worst-Case Negative = −0.68 LSB, Code 3230

Rev. D | Page 25 of 110

ADuC7124/ADuC7126

Data Sheet

20

0

SNR: 69.85dB

SNR: 65.97dB

0

–20

THD: –79.91dB

THD: –78.63dB

PHSN: –82.93dB, 29.771kHz

PHSN: –77.83dB, 146.6038kHz

–20

–40

–60

–80

–100

–120

–140

–40

–60

–80

–100

–120

–140

0

50

100

150

174.1

0

50

100

FREQUENCY (kHz)

150

174.1

FREQUENCY (kHz)

Figure 17. SINAD, THD, and PHSN of ADC,

Figure 20. SINAD, THD, and PHSN of ADC,

_REF= Internal 2.5 V, Single-Ended Mode

V_REF= Internal 2.5 V, Single-Ended Mode

V

ADCCP = ADC0

ADCCP = ADC15/DAC3, ADCCN = ADC0

20

0

0.2

0.1

0

DAC0

DAC1

SNR: 67.10dB

THD: –79.79dB

PHSN: –76.14dB, 54.9738kHz

–20

–40

–60

–80

–100

–120

–140

–0.1

–0.2

0

50

100

FREQUENCY (kHz)

150

174.1

ADC CODES

Figure 18. SINAD, THD, and PHSN of ADC,

V_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = DAC1/ADC13, ADCCN = ADC0

Figure 21. DAC DNL Error,

DAC0 Max Positive DNL: 0.188951, DAC1 Max Positive DNL: 0.190343

DAC0 Max Negative DNL: −0.120081, DAC1 Max Negative DNL: −0.15697

2.0

20

0

DAC0

SNR: 67.44dB

1.5

THD: –82.33dB

DAC1

PHSN: –79.31dB, 54.9738kHz

1.0

0.5

–20

–40

–60

–80

–100

–120

–140

0

–0.5

–1.0

–1.5

–2.0

–2.5

0

50

100

150

174.1

FREQUENCY (kHz)

ADC CODES

Figure 22. DAC INL Error,

Figure 19. SINAD, THD, and PHSN of ADC,

DAC0 Max Positive INL: 1.84106, DAC1 Max Positive INL: 1.75312

DAC0 Max Negative INL: −0.887319, DAC1 Max Negative INL: −2.23708

V

_REF= Internal 2.5 V, Single-Ended Mode

ADCCP = ADC8, ADCCN = ADC0

Rev. D | Page 26 of 110

Data Sheet

ADuC7124/ADuC7126

TERMINOLOGY

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels there are, the smaller

the quantization noise becomes.

ADC SPECIFICATIONS

Integral Nonlinearity (INL)

The maximum deviation of any code from a straight line

passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point

½ LSB below the first code transition, and full scale, a point

½ LSB above the last code transition.

The theoretical signal to (noise + distortion) ratio for an ideal

N-bit converter with a sine wave input is given by

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

Thus, for a 12-bit converter, this is 74 dB.

Differential Nonlinearity (DNL)

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Total Harmonic Distortion

The ratio of the rms sum of the harmonics to the fundamental.

DAC SPECIFICATIONS

Offset Error

The deviation of the first code transition (0000…000) to

(0000…001) from the ideal, that is, ½ LSB.

Relative Accuracy

Otherwise known as endpoint linearity, relative accuracy is a

measure of the maximum deviation from a straight line passing

through the endpoints of the DAC transfer function. It is

measured after adjusting for zero error and full-scale error.

Gain Error

The deviation of the last code transition from the ideal AIN

voltage (full scale − 1.5 LSB) after the offset error has been

adjusted out.

Voltage Output Settling Time

The amount of time it takes the output to settle to within a

1 LSB level for a full-scale input change.

Signal to (Noise + Distortion) Ratio

The measured ratio of signal to (noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

Rev. D | Page 27 of 110

ADuC7124/ADuC7126

Data Sheet

OVERVIEW OF THE ARM7TDMI CORE

The ARM7® core is a 32-bit reduced instruction set computer

(RISC). It uses a single 32-bit bus for instruction and data. The

length of the data can be eight bits, 16 bits, or 32 bits. The

length of the instruction word is 32 bits.

EXCEPTIONS

ARM supports five types of exceptions and a privileged

processing mode for each type. The five types of exceptions are



Normal interrupt or IRQ. This is provided to service

general-purpose interrupt handling of internal and

external events.

The ARM7TDMI is an ARM7 core with four additional

features.



T support for the Thumb® (16-bit) instruction set.

D support for debug.

M support for long multiplications.

I includes the EmbeddedICE module to support embedded

system debugging.



Fast interrupt or FIQ. This is provided to service data

transfers or communication channels with low latency. FIQ

has priority over IRQ.



Memory abort.

Attempted execution of an undefined instruction.

Software interrupt instruction (SWI). This can be used to

make a call to an operating system.

THUMB MODE (T)

An ARM instruction is 32 bits long. The ARM7TDMI

processor supports a second instruction set that has been

compressed into 16 bits, called the Thumb instruction set.

Faster execution from 16-bit memory and greater code density

can usually be achieved by using the Thumb instruction set

instead of the ARM instruction set, which makes the

ARM7TDMI core particularly suitable for embedded

applications.

Typically, the programmer defines an interrupt as IRQ, but for

higher priority interrupt, that is, faster response time, the

programmer can define an interrupt as FIQ.

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose

registers and six status registers. Each operating mode has

dedicated banked registers.

However, the Thumb mode has two limitations:

When writing user-level programs, 15 general-purpose, 32-bit

registers (R0 to R14), the program counter (R15), and the current

program status register (CPSR) are usable. The remaining

registers are only used for system-level programming and

exception handling.



Thumb code typically requires more instructions for the

same job. As a result, ARM code is usually best for

maximizing the performance of time-critical code.

The Thumb instruction set does not include some of the

instructions needed for exception handling, which

automatically switches the core to ARM code for exception

handling.

When an exception occurs, some of the standard registers are

replaced with registers specific to the exception mode. All excep-

tion modes have replacement banked registers for the stack pointer

(R13) and the link register (R14), as represented in Figure 23.

The fast interrupt mode has more registers (R8 to R12) for fast

interrupt processing. This means that the interrupt processing

can begin without the need to save or restore these registers, and

therefore, save critical time in the interrupt handling process.

See the ARM7TDMI user guide for details on the core

architecture, the programming model, and both the ARM

and ARM Thumb instruction sets.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra instruc-

tions that perform 32-bit by 32-bit multiplication with a 64-bit

result and 32-bit by 32-bit multiplication-accumulation (MAC)

with a 64-bit result. These results are achieved in fewer cycles

than required on a standard ARM7 core.

R0

USABLE IN USER MODE

R1

SYSTEM MODES ONLY

R2

R3

R4

R5

R6

EmbeddedICE (I)

R7

R8_FIQ

R9_FIQ

R8

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and watch-

point registers that allow code to be halted for debugging purposes.

These registers are controlled through the JTAG test port.

R9

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R10

R11

R12

R13

R14

R15 (PC)

R13_UND

R13_IRQ

R14_UND

R14_IRQ

R13_ABT

R14_ABT

R13_SVC

R14_SVC

When a breakpoint or watchpoint is encountered, the processor

halts and enters debug state. Once in a debug state, the proces-

sor registers can be inspected as well as the Flash/EE, SRAM,

and memory mapped registers.

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

CPSR

SPSR_FIQ

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

USER MODE

Figure 23. Register Organization

Rev. D | Page 28 of 110

Data Sheet

ADuC7124/ADuC7126

More information relative to the model of the programmer and

the ARM7TDMI core architecture can be found in the

following materials from ARM:

At the end of this time, the ARM7TDMI executes the instruction

at 0x1C (FIQ interrupt vector address). The maximum total

time is 50 processor cycles, which is just under 1.2 µs in a

system using a continuous 41.78 MHz processor clock.

•

DDI0029G, ARM7TDMI Technical Reference Manual

DDI-0100, ARM Architecture Reference Manual

The maximum interrupt request (IRQ) latency calculation is

similar but must allow for the fact that FIQ has higher priority

and can delay entry into the IRQ handling routine for an

arbitrary length of time. This time can be reduced to 42 cycles if

the LDM command is not used. Some compilers have an option

to compile without using this command. Another option is to run

the part in Thumb mode where the time is reduced to 22 cycles.

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ)

consists of the following:

•

The longest time the request can take to pass through the

synchronizer

The minimum latency for FIQ or IRQ interrupts is a total of

five cycles, which consist of the shortest time the request can

take through the synchronizer plus the time to enter the

exception mode.

•

The time for the longest instruction to complete (the

longest instruction is an LDM) that loads all the registers

including the PC

The time for the data abort entry

The time for the FIQ entry

•

Note that the ARM7TDMI always runs in ARM (32-bit) mode

when in privileged modes, for example, when executing interrupt

service routines.

Rev. D | Page 29 of 110

ADuC7124/ADuC7126

Data Sheet

MEMORY ORGANIZATION

The ADuC7124/ADuC7126 incorporate three separate blocks

of memory: 32 kB of SRAM and two 64 kB blocks of on-chip

Flash/EE memory. There are 126 kB of on-chip Flash/EE memory

available to the user, and the remaining 2 kB are reserved for the

system kernel. These blocks are mapped as shown in Figure 24.

FLASH/EE MEMORY

The 128 kB of Flash/EE are organized as two banks of 32 k ×

16 bits. Block 0 starts at Address 0x90000 and finishses at

Address 0x9F700. In this block, 31 k × 16 bits is user space and

1 k × 16 bits is reserved for the factory-configured boot page.

The page size of this Flash/EE memory is 512 bytes.

Note that, by default, after a reset, the Flash/EE memory is

mirrored at Address 0x00000000. It is possible to remap the

SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP

MMR. This remap function is described in more detail in the

Flash/EE memory chapter.

Block 1 starts at Address 0x80000 and finishses at Address

0x90000. In this block, all 64 kB are available as user space. The

block is arranged in 32 k × 16 bits.

The 126 kB of Flash/EE are available to the user as code and

nonvolatile data memory. There is no distinction between data

and program because ARM code shares the same space. The

real width of the Flash/EE memory is 16 bits, meaning that, in

ARM mode (32-bit instruction), two accesses to the Flash/EE

are necessary for each instruction fetch. Therefore, it is recom-

mended that Thumb mode be used when executing from

Flash/EE memory for optimum access speed. The maximum

access speed for the Flash/EE memory is 41.78 MHz in Thumb

mode and 20.89 MHz in full ARM mode (see the Execution

Time from SRAM and Flash/EE section).

0xFFFFFFFF

MMRs

0xFFFF0000

RESERVED

0x0009F800

FLASH/EE

0x00080000

RESERVED

0x00047FFF

SRAM

0x00040000

RESERVED

0x0001FFFF

SRAM

REMAPPABLE MEMORY SPACE

(FLASH/EE OR SRAM)

The 32 kB of SRAM are available to the user, organized as

8 k × 32 bits, that is, 16 k words. ARM code can run directly from

SRAM at 41.78 MHz, given that the SRAM array is configured

as a 32-bit wide memory array (see the Execution Time from

SRAM and Flash/EE section).

0x00000000

Figure 24. Physical Memory Map

MEMORY ACCESS

The ARM7 core sees memory as a linear array of a 2³²byte

location where the different blocks of memory are mapped as

outlined in Figure 24.

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the

upper two pages of the memory array and accessed by indirect

addressing through the ARM7 banked registers.

The ADuC7124/ADuC7126 memory organization is configured

in little endian format: the least significant byte is located in the

lowest byte address and the most significant byte in the highest

byte address.

The MMR space provides an interface between the CPU and

all on-chip peripherals. All registers except the core registers

reside in the MMR area. All shaded locations shown in Figure 26

are unoccupied or reserved locations and should not be

accessed by user software. Table 11 to Table 29 show the full

MMR memory map.

BIT 31

BIT 0

BYTE 3 BYTE 2 BYTE 1 BYTE 0

.

0xFFFFFFFF

B

7

3

A

6

2

9

5

1

8

4

0

0x00000004

0x00000000

The access time reading or writing a MMR depends on the

advanced microcontroller bus architecture (AMBA) bus used

to access the peripheral. The processor has two AMBA buses:

the advanced high performance bus (AHB) used for system

modules, and the advanced peripheral bus (APB) used for the

lower performance peripheral. Access to the AHB is one cycle,

and access to the APB is two cycles. All peripherals on the

ADuC7124/ADuC7126 are on the APB except the Flash/EE

memory and the GPIOs.

32 BITS

Figure 25. Little Endian Format

Rev. D | Page 30 of 110

Data Sheet

ADuC7124/ADuC7126

0xFFFFFFFF

0xFFFFF880

FLASH CONTROL

INTERFACE 1

FLASH CONTROL

INTERFACE 0

0xFFFFF800

0xFFFFF400

0xFFFFF000

0xFFFF0F80

0xFFFF0B00

0xFFFF0A00

0xFFFF0900

0xFFFF0800

GPIO

EXTERNAL

MEMORY

PWM

PLA

SPI

I2C1

I2C0

UART1

UART0

DAC

0xFFFF0740

0xFFFF0700

0xFFFF0600

ADC

0xFFFF0500

0xFFFF048C

0xFFFF0440

0xFFFF0404

0xFFFF0360

0xFFFF0340

0xFFFF0320

BAND GAP

REFERENCE

POWER SUPPLY

MONITOR

PLL AND

OSCILLATOR CONTROL

WATCHDOG

TIMER

WAKE-UP

TIMER

GENERAL-PURPOSE

TIMER

TIMER 0

0xFFFF0300

0xFFFF0220

REMAP AND

SYSTEM CONTROL

INTERRUPT

CONTROLLER

0xFFFF0000

Figure 26. Memory Mapped Registers

Rev. D | Page 31 of 110

ADuC7124/ADuC7126

Data Sheet

Table 11. IRQ Base Address = 0xFFFF0000

Address

Name

Byte

4

1

4

1

4

Access Type

0xFFFF0000

0xFFFF0004

0xFFFF0008

0xFFFF000C

0xFFFF0010

0xFFFF0014

0xFFFF001C

0xFFFF0020

0xFFFF0024

0xFFFF0028

0xFFFF002C

0xFFFF0030

0xFFFF0034

0xFFFF0038

0xFFFF003C

0xFFFF0100

0xFFFF0104

0xFFFF0108

0xFFFF010C

0xFFFF011C

0xFFFF013C

IRQSTA

IRQSIG

IRQEN

IRQCLR

SWICFG

IRQBASE

IRQVEC

IRQP0

R

R/W

W

R/W

R

R/W

W

R/W

R

IRQP1

IRQP2

IRQP3

IRQCONN

IRQCONE

IRQCLRE

IRQSTAN

FIQSTA

FIQSIG

FIQEN

FIQCLR

FIQVEC

FIQSTAN

4

R/W

W

R

1

R/W

Table 12. System Control Base Address = 0xFFFF0200

Address

Name

Byte

Access Type

0xFFFF0220

0xFFFF0230

0xFFFF0234

0xFFFF0248

0xFFFF024C

0xFFFF0250

REMAP

RSTSTA

RSTCLR

RSTKEY0

RSTCFG

RSTKEY1

1

R/W

R

W

R/W

W

Table 13. Timer Base Address = 0xFFFF0300

Address

Name

Byte

2

1

4

2

1

4

2

1

2

Access Type

0xFFFF0300

0xFFFF0304

0xFFFF0308

0xFFFF030C

0xFFFF0320

0xFFFF0324

0xFFFF0328

0xFFFF032C

0xFFFF0330

0xFFFF0340

0xFFFF0344

0xFFFF0348

0xFFFF034C

0xFFFF0360

0xFFFF0364

0xFFFF0368

0xFFFF036C

T0LD

R/W

R

R/W

W

R/W

R

R/W

W

R

R/W

R

R/W

W

R/W

R

T0VAL

T0CON

T0CLRI

T1LD

T1VAL

T1CON

T1CLRI

T1CAP

T2LD

T2VAL

T2CON

T2CLRI

T3LD

T3VAL

T3CON

T3CLRI

R/W

W

1

Rev. D | Page 32 of 110

Data Sheet

ADuC7124/ADuC7126

Table 14. PLL/PSM Base Address = 0xFFFF0400

Address

Name

Byte

Access Type

0xFFFF0404

0xFFFF0408

0xFFFF040C

0xFFFF0410

0xFFFF0414

0xFFFF0418

0xFFFF0434

0xFFFF0438

0xFFFF043C

POWKEY1

POWCON0

POWKEY2

PLLKEY1

PLLCON

PLLKEY2

POWKEY3

POWCON1

POWKEY4

2

1

2

4

1

4

2

W

R/W

W

R/W

W

R/W

W

Table 15. PSM Base Address = 0xFFFF0440

Address

Name

Byte

Access Type

R/W

0xFFFF0440

0xFFFF0444

PSMCON

CMPCON

2

Table 16. Reference Base Address = 0xFFFF0480

Address

Name

Byte

Access Type

0xFFFF048C

REFCON

1

R/W

Table 17. ADC Base Address = 0xFFFF0500

Address

Name

Byte

Access Type

R/W

R

0xFFFF0500

0xFFFF0504

0xFFFF0508

0xFFFF050C

0xFFFF0510

0xFFFF0514

0xFFFF0530

0xFFFF0534

0xFFFF0544

0xFFFF0548

ADCCON

ADCCP

ADCCN

ADCSTA

ADCDAT

ADCRST

ADCGN

ADCOF

TSCON

2

1

4

1

2

1

2

R

R/W

TEMPREF

Table 18. DAC Address Base = 0xFFFF0600

Address

Name

Byte

Access Type

R/W

W

0xFFFF0600

0xFFFF0604

0xFFFF0608

0xFFFF060C

0xFFFF0610

0xFFFF0614

0xFFFF0618

0xFFFF061C

0xFFFF0650

0xFFFF0654

0xFFFF0658

DAC0CON

DAC0DAT

DAC1CON

DAC1DAT

DAC2CON

DAC2DAT

DAC3CON

DAC3DAT

DACBKEY1

DACBCFG

DACBKEY2

1

4

1

4

1

4

1

4

2

1

2

R/W

W

Rev. D | Page 33 of 110

ADuC7124/ADuC7126

Data Sheet

Table 19. UART0 Base Address = 0xFFFF0700

Address

Name

Byte

1

2

Access Type

Cycle

0xFFFF0700

0xFFFF0704

0xFFFF0708

0xFFFF070C

0xFFFF0710

0xFFFF0714

0xFFFF0718

0xFFFF072C

COM0TX

COM0RX

R/W

R

R/W

R

R/W

R

2

COM0DIV0

COM0IEN0

COM0DIV1

COM0IID0

COM0FCR

COM0CON0

COM0CON1

COM0STA0

COM0STA1

COM0DIV2

R

R/W

Table 20. UART1 Base Address = 0xFFFF0740

Address

Name

Byte

1

2

Access Type

Cycle

0xFFFF0740

0xFFFF0744

0xFFFF0748

0xFFFF074C

0xFFFF0750

0xFFFF0754

0xFFFF0758

0xFFFF076C

COM1TX

COM1RX

R/W

R

R/W

R

R/W

R

2

COM1DIV0

COM1IEN0

COM1DIV1

COM1IID0

COM1FCR

COM1CON0

COM1CON1

COM1STA0

COM1STA1

COM1DIV2

2

R

R/W

Table 21. I2C0 Base Address = 0xFFFF0800

Address

Name

Byte

2

1

2

1

2

1

Access Type

R/W

R

Cycle

0xFFFF0800

0xFFFF0804

0xFFFF0808

0xFFFF080C

0xFFFF0810

0xFFFF0814

0xFFFF0818

0xFFFF081C

0xFFFF0824

0xFFFF0828

0xFFFF082C

0xFFFF0830

0xFFFF0834

0xFFFF0838

0xFFFF083C

0xFFFF0840

0xFFFF0844

0xFFFF0848

0xFFFF084C

I2C0MCON

I2C0MSTA

I2C0MRX

I2C0MTX

I2C0MCNT0

I2C0MCNT1

I2C0ADR0

I2C0ADR1

I2C0DIV

I2C0SCON

I2C0SSTA

I2C0SRX

I2C0STX

I2C0ALT

I2C0ID0

I2C0ID1

I2C0ID2

I2C0ID3

I2C0FSTA

2

R

R/W

R

R/W

R

W

R/W

1

Rev. D | Page 34 of 110

Data Sheet

ADuC7124/ADuC7126

Table 22. I2C1 Base Address = 0xFFFF0900

Address

Name

Byte

2

1

2

1

2

1

Access Type

R/W

R

Cycle

0xFFFF0900

0xFFFF0904

0xFFFF0908

0xFFFF090C

0xFFFF0910

0xFFFF0914

0xFFFF0918

0xFFFF091C

0xFFFF0924

0xFFFF0928

0xFFFF092C

0xFFFF0930

0xFFFF0934

0xFFFF0938

0xFFFF093C

0xFFFF0940

0xFFFF0944

0xFFFF0948

0xFFFF094C

I2C1MCON

I2C1MSTA

I2C1MRX

I2C1MTX

I2C1MCNT0

I2C1MCNT1

I2C1ADR0

I2C1ADR1

I2C1DIV

I2C1SCON

I2C1SSTA

I2C1SRX

I2C1STX

I2C1ALT

I2C1ID0

I2C1ID1

I2C1ID2

I2C1ID3

I2C1FSTA

2

R

R/W

R

R/W

R

W

R/W

1

Table 23. SPI Base Address = 0xFFFF0A00

Address

Name

SPISTA

SPIRX

SPITX

SPIDIV

SPICON

Byte

Access Type

Cycle

0xFFFF0A00

0xFFFF0A04

0xFFFF0A08

0xFFFF0A0C

0xFFFF0A10

2

1

2

R

W

R/W

2

Table 24. PLA Base Address = 0xFFFF0B00

Address

Name

Byte

2

Access Type

R/W

R

Cycle

2

0xFFFF0B00

0xFFFF0B04

0xFFFF0B08

0xFFFF0B0C

0xFFFF0B10

0xFFFF0B14

0xFFFF0B18

0xFFFF0B1C

0xFFFF0B20

0xFFFF0B24

0xFFFF0B28

0xFFFF0B2C

0xFFFF0B30

0xFFFF0B34

0xFFFF0B38

0xFFFF0B3C

0xFFFF0B40

0xFFFF0B44

0xFFFF0B48

0xFFFF0B4C

0xFFFF0B50

0xFFFF0B54

PLAELM0

PLAELM1

PLAELM2

PLAELM3

PLAELM4

PLAELM5

PLAELM6

PLAELM7

PLAELM8

PLAELM9

PLAELM10

PLAELM11

PLAELM12

PLAELM13

PLAELM14

PLAELM15

PLACLK

1

2

4

1

2

PLAIRQ

PLAADC

PLADIN

PLADOUT

PLALCK

W

Rev. D | Page 35 of 110

ADuC7124/ADuC7126

Data Sheet

Table 25. PWM Base Address = 0xFFFF0F80

Address

Name

Byte

2

Access Type

R/W

W

Cycle

0xFFFF0F80

0xFFFF0F84

0xFFFF0F88

0xFFFF0F8C

0xFFFF0F90

0xFFFF0F94

0xFFFF0F98

0xFFFF0F9C

0xFFFF0FA0

0xFFFF0FA4

0xFFFF0FA8

0xFFFF0FAC

0xFFFF0FB0

0xFFFF0FB4

0xFFFF0FB8

PWMCON0

PWM0COM0

PWM0COM1

PWM0COM2

PWM0LEN

PWM1COM0

PWM1COM1

PWM1COM2

PWM1LEN

PWM2COM0

PWM2COM1

PWM2COM2

PWM2LEN

PWMCON1

PWMCLRI

2

Table 26. External Memory Base Address = 0xFFFFF000

Address

Name

Byte

Access Type

R/W

Cycle

0xFFFFF000

0xFFFFF010

0xFFFFF014

0xFFFFF018

0xFFFFF01C

0xFFFFF020

0xFFFFF024

0xFFFFF028

0xFFFFF02C

XMCFG

1

2

XM0CON

XM1CON

XM2CON

XM3CON

XM0PAR

XM1PAR

XM2PAR

XM3PAR

R/W

Rev. D | Page 36 of 110

Data Sheet

ADuC7124/ADuC7126

Table 27. GPIO Base Address = 0xFFFF0400

Address

Name

Byte

4

1

4

1

4

1

4

1

4

1

Access Type

R/W

W

Cycle

1

0xFFFFF400

0xFFFFF404

0xFFFFF408

0xFFFFF40C

0xFFFFF410

0xFFFFF420

0xFFFFF424

0xFFFFF428

0xFFFFF42C

0xFFFFF430

0xFFFFF434

0xFFFFF438

0xFFFFF43C

0xFFFFF440

0xFFFFF444

0xFFFFF448

0xFFFFF44C

0xFFFFF450

0xFFFFF454

0xFFFFF458

0xFFFFF45C

0xFFFFF460

0xFFFFF464

0xFFFFF468

0xFFFFF46C

GP0CON

GP1CON

GP2CON

GP3CON

GP4CON

GP0DAT

GP0SET

GP0CLR

GP0PAR

GP1DAT

GP1SET

GP1CLR

GP1PAR

GP2DAT

GP2SET

GP2CLR

GP2PAR

GP3DAT

GP3SET

GP3CLR

GP3PAR

GP4DAT

GP4SET

GP4CLR

GP4PAR

W

R/W

W

R/W

W

R/W

W

R/W

W

R/W

4

1

Table 28. Flash/EE Block 0 Base Address = 0xFFFFF800

Address

Name

Byte

Access Type

Cycle

0xFFFFF800

0xFFFFF804

0xFFFFF808

0xFFFFF80C

0xFFFFF810

0xFFFFF818

0xFFFFF81C

0xFFFFF820

FEE0STA

FEE0MOD

FEE0CON

FEE0DAT

FEE0ADR

FEE0SGN

FEE0PRO

FEE0HID

1

2

3

4

R

1

R/W

R

R/W

Table 29. Flash/EE Block 1 Base Address = 0xFFFFF880

Address

Name

Byte

Access Type

Cycle

0xFFFFF880

0xFFFFF884

0xFFFFF888

0xFFFFF88C

0xFFFFF890

0xFFFFF898

0xFFFFF89C

0xFFFFF8A0

FEE1STA

FEE1MOD

FEE1CON

FEE1DAT

FEE1ADR

FEE1SGN

FEE1PRO

FEE1HID

1

2

3

4

R

1

R/W

R

R/W

Rev. D | Page 37 of 110

ADuC7124/ADuC7126

Data Sheet

ADC CIRCUIT OVERVIEW

The analog-to-digital converter is a fast, multichannel, 12-bit

ADC. It can operate from 2.7 V to 3.6 V supplies and is capable

of providing a throughput of up to 1 MSPS when the clock source

is 41.78 MHz. This block provides the user with a multichannel

multiplexer, a differential track-and-hold, an on-chip reference,

and an ADC.

The ideal code transitions occur midway between successive

integer LSB values (that is, ½ LSB, 3⁄2 LSB, 5⁄2 LSB, … ,

FS − 3/2 LSB). The ideal input/output transfer characteristic

is shown in Figure 28.

1111 1111 1111

1111 1111 1110

1111 1111 1101

The ADC consists of a 12-bit successive approximation con-

verter based around two capacitor DACs. Depending on the

input signal configuration, the ADC can operate in one of

three different modes.

1111 1111 1100

FULL-

SCALE

4096

1LSB =



Fully differential mode, for small and balanced signals

Single-ended mode, for any single-ended signals

Pseudo differential mode, for any single-ended signals,

taking advantage of the common-mode rejection offered

by the pseudo differential input

0000 0000 0011

0000 0000 0010

0000 0000 0001

0000 0000 0000

0V 1LSB

+FS – 1LSB

VOLTAGE INPUT

The converter accepts an analog input range of 0 V to V_REFwhen

operating in single-ended or pseudo differential mode. In fully

differential mode, the input signal must be balanced around a

common-mode voltage (V_CM) in the 0 V to AV_DDrange with a

maximum amplitude of 2 × V_REF(see Figure 27).

Figure 28. ADC Transfer Function in Pseudo Differential or Single-Ended Mode

Fully Differential Mode

The amplitude of the differential signal is the difference between

the signals applied to the V_IN+and V_IN–pins (that is, V_IN+– V_IN–).

V_IN+is selected by the ADCCP register, and V_IN−is selected by

AV

DD

the ADCCN register. The maximum amplitude of the differential

signal is, therefore, –V_REFto +V_REFp-p (that is, 2 × V_REF). This is

regardless of the common mode (CM). The common mode is

the average of the two signals, for example, (V_IN++ V_IN–)/2, and

is, therefore, the voltage that the two inputs are centered on.

V

2V

CM

REF

V

CM

2V

REF

V

2V

CM

REF

This results in the span of each input being CM

V_REF/2. This

0

voltage must be set up externally, and its range varies with V_REF

(see the Driving the Analog Inputs section).

Figure 27. Examples of Balanced Signals in Fully Differential Mode

A high precision, low drift, factory calibrated, 2.5 V reference is

provided on chip. An external reference can also be connected as

described in the Band Gap Reference section.

The output coding is twos complement in fully differential mode

with 1 LSB = 2 × V_REF/4096, or 2 × 2.5 V/4096 = 1.22 mV when

V_REF= 2.5 V. The output result is 11 bits, but this is shifted by

one to the right. This allows the result in ADCDAT to be declared

as a signed integer when writing C code. The designed code

transitions occur midway between successive integer LSB values

(that is, ½ LSB, 3⁄2 LSB, 5⁄2 LSB, … , FS − 3⁄2 LSB). e ideal

input/output transfer characteristic is shown in Figure 29.

Single or continuous conversion modes can be initiated in the

software. An external CONV_STARTpin, an output generated from

the on-chip PLA, or a Timer0 or Timer1 overflow can also be

used to generate a repetitive trigger for ADC conversions.

A voltage output from an on-chip band gap reference propor-

tional to absolute temperature can also be routed through the

front-end ADC multiplexer, effectively an additional ADC channel

input. This facilitates an internal temperature sensor channel

that measures die temperature.

SIGN

BIT

0

1111 1111 1110

1111 1111 1100

1111 1111 1010

2 × V

REF

4096

1LSB =

TRANSFER FUNCTION

Pseudo Differential and Single-Ended Modes

0

1

0000 0000 0010

0000 0000 0000

1111 1111 1110

In pseudo differential or single-ended mode, the input range is

0 V to V_REF. The output coding is straight binary in pseudo

differential and single-ended modes with

1

0000 0000 0100

0000 0000 0010

0000 0000 0000

1 LSB = Full-Scale/4096, or

2.5 V/4096 = 0.61 mV, or

610 μV when V_REF= 2.5 V

–V

+ 1LSB

0LSB

+V

– 1LSB

REF

VOLTAGE INPUT (V + – V –)

IN IN

Figure 29. ADC Transfer Function in Differential Mode

Rev. D | Page 38 of 110

Data Sheet

ADuC7124/ADuC7126

TYPICAL OPERATION

MMRS INTERFACE

Once configured via the ADC control and channel selection

registers, the ADC converts the analog input and provides a

12-bit result in the ADC data register.

The ADC is controlled and configured via the eight MMRs.

ADCCON Register

Name:

ADCCON

0xFFFF0500

0x0600

The top four bits are the sign bits. The 12-bit result is placed in

Bit 16 to Bit 27 as shown in Figure 30. Again, it should be noted

that in fully differential mode, the result is represented in twos

complement format. In pseudo differential and single-ended

modes, the result is represented in straight binary format.

Address:

Default Value:

Access:

Read/write

31

27

16 15

0

ADCCON is an ADC control register that allows the program-

mer to enable the ADC peripheral, select the mode of operation

of the ADC (either in single-ended mode, pseudo differential

mode, or fully differential mode), and select the conversion

type. This MMR is described in Table 30.

SIGN BITS

12-BIT ADC RESULT

Figure 30. ADC Result Format

The same format is used in DACxDAT, simplifying the software.

Current Consumption

Table 30. ADCCON MMR Bit Descriptions

The ADC in standby mode, that is, powered up but not

converting, typically consumes 640 μA. The internal reference

adds 140 μA. During conversion, the extra current is 0.3 μA

multiplied by the sampling frequency (in kHz).

Bit

Value

Description

[15:14]

13

Reserved.

Set by the user to enable edge trigger mode.

Cleared by the user to enable level trigger

mode.

Timing

[12:10]

ADC clock speed.

Figure 31 gives details of the ADC timing. The user controls the

ADC clock speed and the number of acquisition clocks in the

ADCCON MMR. By default, the acquisition time is eight

clocks, and the clock divider is two. The number of extra clocks

(such as bit trial or write) is set to 19, which gives a sampling

rate of 774 kSPS. For conversion on temperature sensor, the

ADC acquisition time is automatically set to 16 clocks, and the

ADC clock divider is set to 32. When using multiple channels

including the temperature sensor, the timing settings revert to

the user-defined settings after reading the temperature sensor

channel.

000

f_ADC/1. This divider is provided to obtain

1 MSPS ADC with an external clock <41.78 MHz.

001

010

011

100

101

f_ADC/2 (default value).

f_ADC/4.

f_ADC/8.

f_ADC/16.

f_ADC/32.

[9:8]

ADC acquisition time.

Two clocks.

00

01

10

11

Four clocks.

Eight clocks (default value).

16 clocks.

ACQ

BIT TRIAL

WRITE

7

Enable start conversion.

ADC CLOCK

Set by the user to start any type of

conversion command.

Cleared by the user to disable a start

conversion (clearing this bit does not stop

the ADC when continuously converting).

CONV

START

ADC

6

5

Enable ADC_BUSY.

Set by the user to enable the ADC_BUSYpin.

Cleared by the user to disable the ADC_BUSYpin.

BUSY

DATA

ADCDAT

ADC power control.

Set by the user to place the ADC in normal

mode (the ADC must be powered up for at least

5 μs before it converts correctly).

ADCSTA = 0

ADCSTA = 1

ADC INTERRUPT

Cleared by the user to place the ADC in power-

down mode.

Figure 31. ADC Timing

[4:3]

Conversion mode.

Single-ended mode.

Differential mode.

Pseudo differential mode.

Reserved.

00

01

10

11

Rev. D | Page 39 of 110

ADuC7124/ADuC7126

Data Sheet

Table 31. ADCCP¹MMR Bit Designation

Bit

Value

Description

[2:0]

Conversion type.

Bit

Value

Description

000

001

010

011

Enable CONV_STARTpin as a conversion input.

Enable Timer1 as a conversion input.

Enable Timer0 as a conversion input.

[7:5]

[4:0]

Reserved.

Positive channel selection bits.

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

ADC0.

Single software conversion. Sets to 000 after

conversion (note that Bit 7 of ADCCON MMR

should be cleared after starting a single

software conversion to avoid further

ADC1.

ADC2.

ADC3.

conversions triggered by the CONV_STARTpin).

ADC4.

100

Continuous software conversion.

PLA conversion.

ADC5.

101

ADC6.

Other

Reserved.

ADC7.

ADC8.

ADCCP Register

ADC9.

Name:

ADCCP

0xFFFF0504

0x00

ADC10.

ADC11.

Address:

DAC0/ADC12.

Default Value:

Access:

DAC1/ADC13.

DAC2/ADC14.

Read/write

DAC3/ADC15.

ADCCP is an ADC positive channel selection register. This

MMR is described in Table 31.

Temperature sensor.

AGND (self-diagnostic feature).

Internal reference (self-diagnostic feature).

AV_DD/2.

Others Reserved.

¹ADC and DAC channel availability depends on part model. See the Ordering

Guide for details.

Rev. D | Page 40 of 110

Data Sheet

ADuC7124/ADuC7126

on P0.5 (see the General-Purpose Input/Output section) if

enabled in the ADCCON register.

ADCCN Register

Name:

ADCCN

0xFFFF0508

0x01

ADCDAT Register

Address:

Name:

ADCDAT

0xFFFF0510

0x00000000

Read only

Default Value:

Access:

Address:

Default Value:

Access:

Read/write

ADCCN is an ADC negative channel selection register. This

MMR is described in Table 32.

ADCDAT is an ADC data result register that holds the 12-bit

ADC result, as shown in Figure 30.

Table 32. ADCCN MMR Bit Designation

Bit

Value

Description

Reserved.

Negative channel selection bits.

ADC0.

ADCRST Register

[7:5]

[4:0]

Name:

ADCRST

0xFFFF0514

0x00

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

Address:

Default Value:

Access:

ADC1.

ADC2.

ADC3.

Read/write

ADC4.

ADC5.

ADCRST resets the digital interface of the ADC. Writing any value

to this register resets all the ADC registers to their default values.

ADC6.

ADC7.

ADCGN Register

ADC8.

Name:

ADCGN

ADC9.

ADC10.

Address:

Default Value:

Access:

0xFFFF0530

0x0200

ADC11.

DAC0/ADC12.

DAC1/ADC13.

DAC2/ADC14.

DAC3/ADC15.

Reserved.

AGND.

Read/write

ADCGN is a 10-bit gain calibration register.

ADCOF Register

Name:

ADCOF

Reserved.

Address:

Default Value:

Access:

0xFFFF0534

0x0200

Others Reserved.

ADCSTA Register

Read/write

Name:

ADCSTA

0xFFFF050C

0x00

ADCOF is a 10-bit offset calibration register.

Address:

CONVERTER OPERATION

Default Value:

Access:

The ADC incorporates a successive approximation (SAR)

architecture involving a charge-sampled input stage. This

architecture can operate in three different modes: differential,

pseudo differential, and single-ended.

Read only

ADCSTA is an ADC status register that indicates when an ADC

conversion result is ready. The ADCSTA register contains only

one bit, ADCReady (Bit 0), representing the status of the ADC.

This bit is set at the end of an ADC conversion, generating an

ADC interrupt. It is cleared automatically by reading the

ADCDAT MMR. When the ADC is performing a conversion,

the status of the ADC can be read externally via the ADC_BUSY

pin. This pin is high during a conversion. When the conversion

is finished, ADC_BUSYgoes back low. This information is available

Differential Mode

The ADuC7124/ADuC7126 each contains a successive approx-

imation ADC based on two capacitive DACs. Figure 32 and

Figure 33 show simplified schematics of the ADC in acquisition

and conversion phases, respectively. The ADC comprises con-

trol logic, a SAR, and two capacitive DACs. In Figure 32 (the

acquisition phase), SW3 is closed and SW1 and SW2 are in

Rev. D | Page 41 of 110

ADuC7124/ADuC7126

Data Sheet

Position A. The comparator is held in a balanced condition, and

the sampling capacitor arrays acquire the differential signal on

the input.

Single-Ended Mode

In single-ended mode, SW2 is always connected internally to

ground. The V_IN−pin can be floating. The input signal range on

V_IN+is 0 V to V_REF.

CAPACITIVE

DAC

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

CHANNEL+

CHANNEL–

AIN0

COMPARATOR

SW1

SW2

C

B

A

S

CONTROL

LOGIC

CHANNEL+

AIN0

MUX

SW3

A

B

SW1

CONTROL

LOGIC

AIN11

MUX

SW3

CHANNEL–

AIN11

V

REF

CAPACITIVE

DAC

CAPACITIVE

DAC

Figure 32. ADC Acquisition Phase

Figure 35. ADC in Single-Ended Mode

When the ADC starts a conversion, as shown in Figure 33, SW3

opens, and then SW1 and SW2 move to Position B. This causes

the comparator to become unbalanced. Both inputs are discon-

nected once the conversion begins. The control logic and the

charge redistribution DACs are used to add and subtract fixed

amounts of charge from the sampling capacitor arrays to bring

the comparator back into a balanced condition. When the

comparator is rebalanced, the conversion is complete. The

control logic generates the ADC output code. The output

impedances of the sources driving the V_IN+and V_IN–pins must

be matched; otherwise, the two inputs have different settling

times, resulting in errors.

Analog Input Structure

Figure 36 shows the equivalent circuit of the analog input structure

of the ADC. The four diodes provide ESD protection for the analog

inputs. Care must be taken to ensure that the analog input

signals never exceed the supply rails by more than 300 mV; this

can cause these diodes to become forward-biased and start

conducting into the substrate. These diodes can conduct up to

10 mA without causing irreversible damage to the part.

The C1 capacitors in Figure 36 are typically 4 pF and can be

primarily attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 100 Ω.

The C2 capacitors are the sampling capacitors of the ADC and

typically have a capacitance of 16 pF.

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

CHANNEL+

CHANNEL–

AIN0

SW1

SW2

AV

DD

CONTROL

LOGIC

MUX

SW3

A

B

AIN11

D

C2

R1

V

REF

CAPACITIVE

DAC

C1

D

Figure 33. ADC Conversion Phase

AV

DD

Pseudo Differential Mode

D

C2

In pseudo differential mode, Channel− is linked to the

ADCNEG pin of the ADuC7124/ADuC7126. In Figure 34,

ADCNEG is represented as V_IN−. SW2 switches between A

(Channel−) and B (V_REF). The ADCNEG pin must be connected

to ground or to a low voltage. The input signal on V_IN+can then

vary from V_IN−to V_REF+ V_IN−. Note that V_IN−must be chosen so

that V_REF+ V_IN−do not exceed AV_DD.

R1

C1

Figure 36. Equivalent Analog Input Circuit Conversion Phase: Switches Open,

Track Phase: Switches Closed

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

CHANNEL+

AIN0

SW1

SW2

CONTROL

LOGIC

MUX

SW3

A

B

AIN11

V

REF

CAPACITIVE

DAC

V

IN–

CHANNEL–

Figure 34. ADC in Pseudo Differential Mode

Rev. D | Page 42 of 110

Data Sheet

ADuC7124/ADuC7126

For ac applications, removing high frequency components from

the analog input signal is recommended by using an RC low-

pass filter on the relevant analog input pins. In applications

where harmonic distortion and signal-to-noise ratio are critical,

the analog input should be driven from a low impedance

source. Large source impedances significantly affect the ac

performance of the ADC. This can necessitate the use of an

input buffer amplifier. The choice of the op amp is a function of

the particular application. Figure 37 and Figure 38 give an

example of the ADC front end.

ADuC7124/

ADuC7126

ADC0

V

REF

ADC1

Figure 38. Buffering Differential Inputs

When no amplifier is used to drive the analog input, the source

impedance should be limited to values lower than 1 kΩ. The

maximum source impedance depends on the amount of total

harmonic distortion (THD) that can be tolerated. The THD

increases as the source impedance increases and the performance

degrades.

ADuC7124/

ADuC7126

10Ω

ADC0

0.01µF

DRIVING THE ANALOG INPUTS

Internal or external references can be used for the ADC. In

differential mode of operation, there are restrictions on the

common-mode input signal (V_CM), which is dependent upon

the reference value and supply voltage used to ensure that the

signal remains within the supply rails. Table 33 gives some

calculated V_CMminimum and V_CMmaximum values.

Figure 37. Buffering Single-Ended/Pseudo Differential Input

Table 33. V_CMRanges

AV_DD

V_REF

V_CMMinimum

1.25 V

1.024 V

0.75 V

V_CMMaximum

Signal Peak-to-Peak

3.3 V

2.5 V

2.05 V

2.276 V

2.55 V

1.75 V

1.976 V

2.25 V

2.5 V

2.048 V

1.25 V

2.5 V

2.048 V

1.25 V

2.048 V

1.25 V

2.5 V

2.048 V

1.25 V

3.0 V

1.25 V

1.024 V

0.75 V

Rev. D | Page 43 of 110

ADuC7124/ADuC7126

Data Sheet

K is the gain of the ADC in temperature sensor mode as

CALIBRATION

determined by characterization data. K = 0.2555°C/mV

for ADuC7124. K = 0.2212°C/mV for ADuC7126. This

corresponds to the 1/voltage temperature coefficient

specification from Table 1.

By default, the factory-set values written to the ADC offset

(ADCOF) and gain coefficient registers (ADCGN) yield opti-

mum performance in terms of end-point errors and linearity

for standalone operation of the part (see the Specifications

section). If system calibration is required, it is possible to

modify the default offset and gain coefficients to improve end-

point errors, but note that any modification to the factory-set

ADCOF and ADCGN values can degrade ADC linearity

performance.

Using the default values from Table 1 and without any

calibration, this equation becomes

T − 25°C = (V_ADC− 1415) × 0.2555 for ADuC7124

T − 25°C = (V_ADC−1392) × 0.2212 for ADuC7126

where V_ADCis in mV.

For system offset error correction, the ADC channel input stage

must be tied to AGND. A continuous software ADC conversion

loop must be implemented by modifying the value in ADCOF

until the ADC result (ADCDAT) reads Code 0 to Code 1. If the

ADCDAT value is greater than 1, ADCOF should be decremented

until ADCDAT reads Code 0 to Code 1. Offset error correction

is done digitally and has a resolution of 0.25 LSB and a range of

For better accuracy, the user should perform a single point

calibration at a controlled temperature value.

For the calculation with no calibration, use 25°C and 1415 mV

for the ADuC7124 and 1392mV for the ADuC7126. The idea

of a single point calibration is to use other known (T_REF, V_TREF

values to replace the common T = 25°C and 1415 mV for the

ADuC7124 and 1392 mV for the ADuC7126 for every part.

)

3.125% of V_REF

.

For system gain error correction, the ADC channel input stage

must be tied to V_REF. A continuous software ADC conversion

loop must be implemented to modify the value in ADCGN until

the ADC result (ADCDAT) reads Code 4094 to Code 4095. If the

ADCDAT value is less than 4094, ADCGN should be incremented

until ADCDAT reads Code 4094 to Code 4095. Similar to the

offset calibration, the gain calibration resolution is 0.25 LSB

For some users, it is not possible to obtain such a known pair.

For such cases, the ADuC7124/ADuC7126 comes with a single

point calibration value loaded in the TEMPREF register. For

more details on this register, see Table 35. During production

testing of the ADuC7124/ADuC7126, the TEMPREF register is

loaded with an offset adjustment factor. Each part has a

different value in the TEMPREF register. Using this single point

calibration, the same formula is still used.

with a range of 3% of V_REF

.

TEMPERATURE SENSOR

T – T_REF= (V_ADC– V_TREF) × K

The ADuC7124/ADuC7126 provide voltage outputs from an

on-chip band gap reference that is proportional to absolute

temperature. This voltage output can also be routed through the

front-end ADC multiplexer (effectively, an additional ADC

channel input), facilitating an internal temperature sensor

channel, measuring die temperature.

where:

T

V

_REF= 25°C but is not guaranteed.

_TREFcan be calculated using the TEMPREF register.

TSCON Register

Name:

TSCON

An ADC temperature sensor conversion differs from a standard

ADC voltage. The ADC performance specifications do not

apply to the temperature sensor.

Address:

0xFFFF0544

0x00

Default Value:

Access:

Chopping of the internal amplifier must be enabled using the

TSCON register. To enable this mode, the user must set Bit 0 of

TSCON. The user must also take two consecutive ADC readings

and average them in this mode.

Read/write

Table 34. TSCON MMR Bit Descriptions

Bit

[7:1]

0

Description

Reserved.

The ADCCON register must be configured to 0x37A3.

To calculate die temperature, use the following formula:

T – T_REF= (V_ADC– V_TREF) × K

Temperature sensor chop enable bit. This bit must

be set.

This bit is set to 1 to enable chopping of the internal

amplifier to the ADC.

This bit is cleared to disable chopping. This results in

incorrect temperature sensor readings.

where:

T is the temperature result.

T

_REF= 25°C.

For the ADuC7124, V_TREF= 1.415 V and for the ADuC7126,

_TREF= 1.392 V, which corresponds to T_REF= 25°C, as described

in Table 1.

_ADCis the average ADC result from two consecutive

conversions.

This bit is cleared by default.

V

Rev. D | Page 44 of 110

Data Sheet

ADuC7124/ADuC7126

response during ADC conversions. This reference can also be

connected to an external pin (V_REF) and used as a reference

for other circuits in the system. An external buffer is required

because of the low drive capability of the VREF output (<5 µA).

A programmable option also allows an external reference input

on the V_REFpin. Note that it is not possible to disable the

internal reference. Therefore, the external reference source must

be capable of overdriving the internal reference source.

TEMPREF Register

Name:

TEMPREF

Address:

Default Value:

Access:

0xFFFF0548

0xXXXX

Read/write

REFCON Register

Table 35. TEMPREF MMR Bit Descriptions

Bit

Description

Name:

REFCON

0xFFFF048C

0x00

[15:9]

8

Reserved.

Address:

Default Value:

Access:

Temperature reference voltage sign bit.

[7:0]

Temperature sensor offset calibration voltage.

To calculate the V_TEMPfrom the TEMPREF register,

perform the following calculation:

If TEMPREF sign is negative,

C_TREF= 2292 − TEMPREF[7:0]

where TEMPREF[8] = 1

Read/write

The band gap reference interface consists of an 8-bit MMR

REFCON, described in Table 36.

Or

Table 36. REFCON MMR Bit Descriptions

If TEMPREF sign is positive,

C_TREF= TEMPREF[7:0] + 2292

where TEMPREF[8] = 0.

Bit

[7:2]

1

Description

Reserved.

Finally,

Internal reference power-down bit.

V_TREF= ((C_TREF× V_REF)/4096) × 1000

Insert V_TREFinto

T − T_REF= (V_ADC− V_TREF) × K

Set this bit to 1 to power down the internal reference

source. This bit should be set when connecting an

external reference source.

Note that the ADC Code Value 2292 is a default value

when using the TEMPREF register. It is not an exact

value and must only be used with the TEMPREF

register.

Clear this bit to enable the internal reference.

This bit is cleared by default.

0

Internal reference output enable.

Set by the user to connect the internal 2.5 V reference

to the V_REFpin. The reference can be used for an

external component but must be buffered.

Cleared by the user to disconnect the reference from

the V_REFpin.

BAND GAP REFERENCE

Each ADuC7124/ADuC7126 provides on-chip band gap

references of 2.5 V, which can be used for the ADC and DAC.

This internal reference also appears on the V_REFpin. When using

the internal reference, a 0.47 µF capacitor must be connected from

the external V_REFpin to AGND to ensure stability and fast

To connect an external reference source to the ADuC7124/

ADuC7126, configure REFCON = 0x00. ADC and the DACs

can be configured to use same or a different reference resource

(see Table 66).

Rev. D | Page 45 of 110

ADuC7124/ADuC7126

Data Sheet

NONVOLATILE FLASH/EE MEMORY

The ADuC7124/ADuC7126 incorporate Flash/EE memory

technology on-chip to provide the user with nonvolatile, in-

circuit reprogrammable memory space.

Retention quantifies the ability of the Flash/EE memory to

retain its programmed data over time. Again, the parts are

qualified in accordance with the formal JEDEC Retention

Lifetime Specification (A117) at a specific junction temperature

(T_J= 85°C). As part of this qualification procedure, the Flash/EE

memory is cycled to its specified endurance limit (see the

Flash/EE Memory section) before data retention is character-

ized. This means that the Flash/EE memory is guaranteed to

retain its data for its fully specified retention lifetime every time

the Flash/EE memory is reprogrammed. In addition, note that

retention lifetime, based on the activation energy of 0.6 eV,

derates with T_Jas shown in Figure 39.

Like EEPROM, flash memory can be programmed in-system

at a byte level, although it must first be erased. The erase is

performed in page blocks. As a result, flash memory is often

and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer to the

ideal memory device that includes nonvolatility, in-circuit

programmability, high density, and low cost. Incorporated in

the ADuC7124/ADuC7126, Flash/EE memory technology

allows the user to update program code space in-circuit,

without the need to replace one-time programmable (OTP)

devices at remote operating nodes.

600

Flash/EE Memory

The ADuC7124/ADuC7126 contain two 64 kB arrays of Flash/EE

memory. In flash Block 0, the lower 62 kB is available to the

user, and the upper 2 kB of this Flash/EE program memory

array contain permanently embedded firmware, allowing in-circuit

serial download. The 2 kB of embedded firmware also contain a

power-on configuration routine that downloads factory cali-

brated coefficients to the various calibrated peripherals (band

gap references and so on). This 2 kB embedded firmware is

hidden from user code. It is not possible for the user to read, write,

or erase this page. In flash Block 1, all 64 kB of Flash/EE memory

are available to the user.

450

300

150

0

30

40

55

70

85

100

125

135

150

JUNCTION TEMPERATURE (°C)

Figure 39. Flash/EE Memory Data Retention

The 126 kB of Flash/EE memory can be programmed in-circuit,

using the serial download mode or the JTAG mode provided.

PROGRAMMING

The 126 kB of Flash/EE memory can be programmed in-circuit,

using the serial download mode or the provided JTAG mode.

Flash/EE Memory Reliability

The Flash/EE memory arrays on the parts are fully qualified for

two key Flash/EE memory characteristics: Flash/EE memory

cycling endurance and Flash/EE memory data retention.

Serial Downloading (In-Circuit Programming)

The ADuC7124/ADuC7126 facilitate code download via the

standard UART serial port. It is only available on UART0

(P1.0 and P1.1). The parts enter serial download mode after

a reset or power cycle if the BM pin is pulled low through

an external 1 kΩ resistor. When in serial download mode,

the user can download code to the full 126 kB of Flash/EE

memory while the device is in-circuit in its target application

hardware. An executable PC serial download is provided as

part of the development system for serial downloading via

the UART. The AN-724 application note describes the UART

download protocol.

Endurance quantifies the ability of the Flash/EE memory to be

cycled through many program, read, and erase cycles. A single

endurance cycle is composed of four independent, sequential

events, defined as

1. Initial page erase sequence.

2. Read/verify sequence (single Flash/EE).

3. Byte program sequence memory.

4. Second read/verify sequence (endurance cycle).

In reliability qualification, every half word (16-bit wide)

location of the three pages (top, middle, and bottom) in the

Flash/EE memory is cycled 10,000 times from 0x0000 to

0xFFFF. As indicated in Table 1, the Flash/EE memory

endurance qualification is carried out in accordance with

JEDEC Retention Lifetime Specification A117 over the

industrial temperature range of −40° to +125°C. The results

allow the specification of a minimum endurance figure over a

supply temperature of 10,000 cycles.

Downloading (In-Circuit Programming) via I²C

The ADuC7126BSTZ126I and ADuC7126BSTZ126IRL models

facilitate code download via the the I²C port. The models enter

download mode after a reset or power cycle if the BM pin is

pulled low through an external 1 kΩ resistor and Flash Address

0x80014 = 0xFFFFFFFF. Once in download mode, the user can

download code to the full 126 kB of Flash/EE memory while the

device is in-circuit in its target application hardware. An executable

PC I²C download is provided as part of the development system

Rev. D | Page 46 of 110

Data Sheet

ADuC7124/ADuC7126

for serial downloading via the I²C. A USB-to-I²C download

dongle can be purchased from Analog Devices, Inc. This board

connects to the USB port of a PC and to the I²C port of the

ADuC7126. The part number is USB-I2C/LIN-CONV-Z.

To remove or modify the protection, the same sequence is used

with a modified value of FEExPRO. If the key chosen is the

value 0xDEAD, the memory protection cannot be removed. Only a

mass erase unprotects the part, but it also erases all user code.

The AN-806 Application Note describes the protocol for serial

downloading via the I²C in more detail.

The sequence to write the key is illustrated in the following

example (this protects writing Page 4 to Page 7 of the Flash):

FEExPRO=0xFFFFFFFD;

FEExMOD=0x48;

FEExADR=0x1234;

FEExDAT=0x5678;

FEExCON= 0x0C;

//Protect Page 4 to 7

//Write key enable

//16 bit key value

//Write key command

JTAG Access

The JTAG protocol uses the on-chip JTAG interface to facilitate

code download and debug.

To access the part via the JTAG interface, the P0.0/BM pin must

be set high.

The same sequence should be followed to protect the part

permanently with FEExADR = 0xDEAD and FEExDAT =

0xDEAD.

When debugging, user code should not write to the P0.1, P0.2,

and P0.3 pins. If user code toggles any of these pins, JTAG debug

pods are not able to connect to the ADuC7124/ADuC7126.

If this happens, mass erase the part using the UART/I²C

downloader.

FLASH/EE CONTROL INTERFACE

Table 37. FEE0STA Register

Name

Address

Default Value

Access

FLASH/EE MEMORY SECURITY

FEE0STA

0xFFFFF800

0x0000

R

The 126 kB of Flash/EE memory available to the user can be

read and write protected. Bit 31 of the FEE0PRO/FEE0HID

MMR protects the 62 kB of Block 0 from being read through

JTAG and in UART programming mode. The other 31 bits of this

register protect writing to the Flash/EE memory; each bit protects

four pages, that is, 2 kB. Write protection is activated for all access

types. FEE1PRO and FEE1HID, similarly, protect flash Block 1.

Bit 31 of the FEE1PRO/FEE1HID MMR protects the 64 kB of

Block 1 from being read through JTAG. Bit 30 protects writing to

the top 8 pages of Block 1. The other 30 bits of this register

protect writing to the Flash/EE memory; each bit protects four

pages, that is, 2 kB

Table 38. FEE0MOD Register

Name

Address

Default Value

Access

FEE0MOD

0xFFFFF804

0x80

R/W

Table 39. FEE0CON Register

Name

Address

Default Value

Access

FEE0CON

0xFFFFF808

0x00

R/W

Table 40. FEE0DAT Register

Name

Address

Default Value

Access

FEE0DAT

0xFFFFF80C

0xXXXX

R/W

FEE0DAT is a 16-bit data register.

Three Levels of Protection

Table 41. FEE0ADR Register

•

Protection can be set and removed by writing directly into

FEExHID MMR. This protection does not remain after reset.

Protection can be set by writing into FEExPRO MMR. It

takes effect only after a save protection command (0x0C)

and a reset. The FEExPRO MMR is protected by a key to

avoid direct access. The key is saved once and must be

entered again to modify FEExPRO. A mass erase sets the

key back to 0xFFFF but also erases all the user code.

Flash can be permanently protected by using the FEExPRO

MMR and a particular key value of 0xDEADDEAD.

Entering the key again to modify the FEExPRO register is

not allowed.

Name

Address

Default Value

Access

FEE0ADR

0xFFFFF810

0x0000

R/W

•

FEE0ADR is a 16-bit address register.

Table 42. FEE0SGN Register

Name

Address

Default Value

Access

FEE0SGN

0xFFFFF818

0xFFFFFF

R

•

FEE0SGN is a 24-bit code signature.

Table 43. FEE0PRO Register

Name

Address

Default Value

Access

FEE0PRO

0xFFFFF81C

0x00000000

R/W

Sequence to Write the Key

FEE0PRO provides protection following subsequent reset MMR.

It requires a software key (see Table 56).

1. Write the bit in FEExPRO corresponding to the page to be

protected.

2. Enable key protection by setting Bit 6 of FEExMOD (Bit 5

must equal 0).

3. Write a 32-bit key in FEExADR and FEExDAT.

4. Run the write key command 0x0C in FEExCON; wait for

the read to be successful by monitoring FEExSTA.

5. Reset the part.

Table 44. FEE0HID Register

Name

Address

Default Value

Access

FEE0HID

0xFFFFF820

0xFFFFFFFF

R/W

FEE0HID provides immediate protection MMR. It does not

require any software keys (see Table 56).

Rev. D | Page 47 of 110

ADuC7124/ADuC7126

Data Sheet

Table 45. FEE1STA Register

Table 49. FEE1ADR Register

Name

Address

Default Value

Access

Name

Address

Default Value

0x0000

Access

FEE1STA

0xFFFFF880

0x0000

R

FEE1ADR

0xFFFFF890

R/W

Table 46. FEE1MOD Register

FEE1ADR is a 16-bit address register.

Name

Address

Default Value

Access

Table 50. FEE1SGN Register

FEE1MOD

0xFFFFF884

0x80

R/W

Name

Address

Default Value

Access

FEE1SGN

0xFFFFF898

0xFFFFFF

R

Table 47. FEE1CON Register

Name

Address

Default Value

Access

FEE1SGN is a 24-bit code signature.

FEE1CON

0xFFFFF888

0x00

R/W

Table 51. FEE1PRO Register

Table 48. FEE1DAT Register

Name

Address

Default Value

Access

Name

Address

Default Value

Access

FEE1PRO

0xFFFFF89C

0x00000000

R/W

FEE1DAT

0xFFFFF88C

0xXXXX

R/W

FEE1PRO provides protection following subsequent reset MMR.

It requires a software key (see Table 57).

FEE1DAT is a 16-bit data register.

Table 52. FEE1HID Register

Name

Address

Default Value

Access

FEE1HID

0xFFFFF8A0

0xFFFFFFFF

R/W

FEE1HID provides immediate protection MMR. It does not

require any software keys (see Table 57).

Command Sequence for Executing a Mass Erase

FEE0DAT = 0x3CFF;

FEE0ADR = 0xFFC3;

FEE0MOD = FEE0MOD|0x8; //Erase key enable

FEE0CON = 0x06;

//Mass erase

command

Table 53. FEExSTA MMR Bit Descriptions

Bit

Description

[15:6]

Reserved.

5

4

3

Reserved.

Flash/EE interrupt status bit.

Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the

FEExMOD register is set.

Cleared when reading the FEExSTA register.

2

1

0

Flash/EE controller busy.

Set automatically when the controller is busy.

Cleared automatically when the controller is not busy.

Command fail.

Set automatically when a command completes unsuccessfully.

Cleared automatically when reading the FEExSTA register.

Command complete.

Set by MicroConverter when a command is complete.

Cleared automatically when reading the FEExSTA register.

Rev. D | Page 48 of 110

Data Sheet

ADuC7124/ADuC7126

Table 54. FEExMOD MMR Bit Descriptions

Bit

[7:5]

4

Description

Reserved.

Flash/EE interrupt enable.

Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.

Cleared by the user to disable the Flash/EE interrupt.

3

Erase/write command protection.

Set by the user to enable the erase and write commands.

Cleared to protect the Flash/EE memory against the erase/write command.

2

Reserved. Should always be set to 0 by the user.

[1:0]

Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect.

Table 55. Command Codes in FEExCON

Code

0x00¹

0x01¹

0x02¹

0x03¹

Command

Description

Null

Idle state.

Single read

Single write

Erase/write

Load FEExDAT with the 16-bit data indexed by FEExADR.

Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 µs.

Erase the page indexed by FEExADR and write FEExDAT at the location pointed to by FEExADR. This operation

takes 20 ms.

Compare the contents of the location pointed to by FEExADR to the data in FEExDAT. The result of the

comparison is returned in FEExSTA, Bit 1.

0x04¹

Single verify

0x05¹

0x06¹

Single erase

Mass erase

Erase the page indexed by FEExADR.

Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental

execution, a command sequence is required to execute this instruction.

0x07

0x08

0x09

0x0A

0x0B

0x0C

Reserved

Signature

Protect

Reserved.

Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.

This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase

(0x06) or with the key.

0x0D

0x0E

0x0F

Reserved

Ping

Reserved.

No operation, interrupt generated.

¹The FEExCON register always reads 0x07 immediately after execution of any of these commands.

Rev. D | Page 49 of 110

ADuC7124/ADuC7126

Data Sheet

is needed to decode the new address of the program counter,

and then four cycles are needed to fill the pipeline. A data pro-

cessing instruction involving only the core register does not

require any extra clock cycles. However, if it involves data in

Flash/EE, an extra clock cycle is needed to decode the address

of the data, and two cycles are needed to get the 32-bit data from

Flash/EE. An extra cycle must also be added before fetching

another instruction. Data transfer instructions are more complex

and are summarized in Table 58.

Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions

Bit

Description

31

Read protection.

Cleared by the user to protect Block 0.

Set by the user to allow reading of Block 0.

[30:0]

Write protection for Page 123 to Page 0. Each bit

protects protects a group of 4 pages.

Cleared by the user to protect the pages when writing

to flash. Thus preventing an accidental write to specific

pages in flash.

Table 58. Execution Cycles in ARM/Thumb Mode

Set by the user to allow writing to the pages.

Fetch

Instructions Cycles

Dead

Time

Dead

Time

Data Access

Table 57. FEE1PRO and FEE1HID MMR Bit Descriptions

LD¹

LDH

LDM/PUSH

STR¹

STRH

2/1

1

N²

1

N¹

2

1

N¹

1

N¹

Bit

Description

31

Read protection.

2 × N²

Cleared by the user to protect Block 1.

Set by the user to allow reading of Block 1.

Write protection for Page 127 to Page 120.

2 × 20 ns

20 ns

2 × N × 20 ns¹

30

STRM/POP

Cleared by the user to protect the pages when writing

to flash. Thus preventing an accidental write to specific

pages in flash.

¹The SWAP instruction combines an LD and STR instruction with only one

fetch, giving a total of eight cycles + 40 ns.

²N is the number of data bytes to load or store in the multiple load/store

instruction (1 < N ≤ 16).

Set by the user to allow writing to the pages.

[29:0]

Write protection for Page 119 to Page 116 and for Page 0

to Page 3.

RESET AND REMAP

The ARM exception vectors are all situated at the bottom of the

memory array, from Address 0x00000000 to Address 0x00000020,

as shown in Figure 40.

Cleared by the user to protect the pages in writing.

Set by the user to allow writing to the pages.

EXECUTION TIME FROM SRAM AND FLASH/EE

0xFFFFFFFF

This section describes SRAM and Flash/EE access times during

execution for applications where execution time is critical.

Execution from SRAM

Fetching instructions from SRAM takes one clock cycle because

the access time of the SRAM is 2 ns, and a clock cycle is 24 ns

minimum. However, if the instruction involves reading or

writing data to memory, one extra cycle must be added if the

data is in SRAM (or three cycles if the data is in Flash/EE): one

cycle to execute the instruction and two cycles to get the 32-bit

data from Flash/EE. A control flow instruction (a branch

instruction, for example) takes one cycle to fetch but also takes

two cycles to fill the pipeline with the new instructions.

KERNEL

0x0009F800

0x00047FFF

FLASH/EE

INTERRUPT

SERVICE ROUTINES

0x00080000

0x00040000

SRAM

INTERRUPT

SERVICE ROUTINES

MIRROR SPACE

Execution from Flash/EE

0x00000020

ARM EXCEPTION

VECTOR ADDRESSES 0x00000000 0x00000000

Because the Flash/EE width is 16 bits and access time for 16-bit

words is 22 ns, execution from Flash/EE cannot be done in

one cycle (as can be done from SRAM when the CD bit = 0).

Also, some dead times are needed before accessing data for any

value of the CD bits.

Figure 40. Remap for Exception Execution

By default, and after any reset, the Flash/EE is mirrored at the

bottom of the memory array. The remap function allows the

programmer to mirror the SRAM at the bottom of the memory

array, which facilitates execution of exception routines from

SRAM instead of from Flash/EE. This means exceptions are

executed twice as fast, being executed in 32-bit ARM mode with

32-bit wide SRAM instead of 16-bit wide Flash/EE memory.

In ARM mode, where instructions are 32 bits, two cycles are

needed to fetch any instruction when CD = 0. In Thumb mode,

where instructions are 16 bits, one cycle is needed to fetch any

instruction.

Timing is identical in both modes when executing instructions

that involve using the Flash/EE for data memory. If the instruc-

tion to be executed is a control flow instruction, an extra cycle

Rev. D | Page 50 of 110

Data Sheet

ADuC7124/ADuC7126

Table 59. REMAP MMR Bit Descriptions

Table 60. RSTSTA MMR Bit Descriptions

(Address = 0xFFFF0220. Default Value = 0x00)

Bit

[7:3]

2

Description

Bit Name

Description

Reserved.

0

Remap

Remap bit.

Software reset.

Set by the user to remap the SRAM to Address

0x00000000.

Set by the user to force a software reset.

Cleared by setting the corresponding bit in RSTCLR.

Cleared automatically after reset to remap the

Flash/EE memory to Address 0x00000000.

1

0

Watchdog timeout.

Set automatically when a watchdog timeout occurs.

Cleared by setting the corresponding bit in RSTCLR.

Remap Operation

Power-on reset.

Set automatically when a power-on reset occurs.

Cleared by setting the corresponding bit in RSTCLR.

When a reset occurs on the ADuC7124/ADuC7126, execution

automatically starts in factory programmed, internal

configuration code. This kernel is hidden and cannot be accessed

by user code. If the part is in normal mode (BM pin is high), it

executes the power-on configuration routine of the kernel and

then jumps to the reset vector address, 0x00000000, to execute

the reset exception routine of the user.

RSTCLR Register

Name:

RSTCLR

0xFFFF0234

0x00

Address:

Because the Flash/EE is mirrored at the bottom of the memory

array at reset, the reset interrupt routine must always be written

in Flash/EE.

Default Value:

Access:

Write only

The remap is done from Flash/EE by setting Bit 0 of the REMAP

register. Caution must be taken to execute this command from

Flash/EE, above Address 0x00080020, and not from the bottom

of the array, because this is replaced by the SRAM.

Note that to clear the RSTSTA register, users must write the

Value 0x07 to the RSTCLR register.

RSTCFG Register

This operation is reversible. The Flash/EE can be remapped at

Address 0x00000000 by clearing Bit 0 of the REMAP MMR.

Caution must again be taken to execute the remap function

from outside the mirrored area. Any type of reset remaps the

Flash/EE memory at the bottom of the array.

Name:

RSTCFG

0xFFFF024C

0x05

Address:

Default Value:

Access:

Read/write

Reset Operation

There are four kinds of reset: external, power-on, watchdog

expiation, and software force. The RSTSTA register indicates

the source of the last reset, and RSTCLR allows clearing of the

RSTSTA register. These registers can be used during a reset

exception service routine to identify the source of the reset.

If RSTSTA is null, the reset is external.

Table 61. RSTCFG MMR Bit Descriptions

Bit

[7:3]

2

Description

Reserved. Always set to 0.

This bit is set to 1 to configure the DAC outputs to

retain their state after a watchdog or software reset.

This bit is cleared for the DAC pins and registers to

return to their default state.

The RSTCFG register allows different peripherals to retain their

state after a watchdog or software reset.

1

0

Reserved. Always set to 0.

RSTSTA Register

This bit is set to 1 to configure the GPIO pins to retain

their state after a watchdog or software reset.

Name:

RSTSTA

0xFFFF0230

0x01

This bit is cleared for the GPIO pins and registers to

return to their default state.

Address:

Default Value:

Access:

The RSTCFG write sequence is as follows:

1. Write Code 0x76 to Register RSTKEY1.

2. Write user value to Register RSTCFG.

3. Write Code 0xB1 to Register RSTKEY2.

Read only

Rev. D | Page 51 of 110

ADuC7124/ADuC7126

Data Sheet

RSTKEY0 Register

RSTKEY1 Register

Name:

RSTKEY0

0xFFFF0248

N/A

Name:

RSTKEY1

Address:

Default Value:

Access

Address:

Default Value:

Access:

0xFFFF0250

N/A

Write only

Rev. D | Page 52 of 110

Data Sheet

ADuC7124/ADuC7126

OTHER ANALOG PERIPHERALS

DAC

Table 65. DAC0DAT MMR Bit Descriptions

The ADuC7124/ADuC7126 incorporate two, or four, 12-bit

voltage output DACs on chip, depending on the model. Each

DAC has a rail-to-rail voltage output buffer capable of driving

5 kΩ/100 pF.

Bit

Description

[31:28]

[27:16]

[15:0]

Reserved.

12-bit data for DAC0.

Reserved.

Each DAC has three selectable ranges: 0 V to V_REF(internal

band gap 2.5 V reference), 0 V to DAC_REF, and 0 V to AV_DD.

DAC_REFis equivalent to an external reference for the DAC.

The signal range is 0 V to AV_DD.

Using the DACs

The on-chip DAC architecture consists of a DAC resistor string

followed by an output buffer amplifier. The functional equivalent

is shown in Figure 41.

MMRs Interface

Each DAC is independently configurable through a control

register and a data register. These two registers are identical for

the four DACs. Only DAC0CON (see Table 63) and DAC0DAT

(see Table 65) are described in detail in this section.

AV

DD

REF

V

DAC

R

DAC0

Table 62. DACxCON Registers

Name

Address

Default Value

0x00

Access

R/W

DAC0CON

DAC1CON

DAC2CON

DAC3CON

0xFFFF0600

0xFFFF0608

0xFFFF0610

0xFFFF0618

R

Table 63. DAC0CON MMR Bit Descriptions

Bit

[7:6]

5

Value Name

Description

Figure 41. DAC Structure

Reserved.

DACCLK DAC update rate.

As illustrated in Figure 41, the reference source for each DAC is

user selectable in software. It can be either AV_DD, V_REF, or DAC_REF

In 0 V-to-AV_DDmode, the DAC output transfer function spans

from 0 V to the voltage at the AV_DDpin. In 0 V-to-DAC_REFmode,

the DAC output transfer function spans from 0 V to the voltage at

the DAC_REFpin. In 0 V-to-V_REFmode, the DAC output transfer

Set by the user to update the DAC

using Timer1.

Cleared by the user to update the

DAC using HCLK (core clock).

.

4

DACCLR DAC clear bit.

Set by the user to enable normal

DAC operation.

function spans from 0 V to the internal 2.5 V reference, V_REF

.

Cleared by the user to reset the data

register of the DAC to 0.

The DAC output buffer amplifier features a true, rail-to-rail

output stage implementation. This means that, when unloaded,

each output is capable of swinging to within less than 5 mV of

both AV_DDand ground. Moreover, the DAC linearity specification

(when driving a 5 kꢀ resistive load to ground) is guaranteed

through the full transfer function except the 0 to 100 codes,

and, in 0 V-to-AV_DDmode only, Code 3995 to Code 4095.

3

Reserved. This bit should be left at 0.

DAC range bits.

Power-down mode. The DAC output

is in tristate.

0 V to DAC_REFrange.

0 V to V_REF(2.5 V) range.

0 V to AV_DDrange.

2

[1:0]

00

01

10

11

Linearity degradation near ground and V_DDis caused by satu-

ration of the output amplifier, and a general representation of its

effects (neglecting offset and gain error) is illustrated in Figure 42.

The dotted line in Figure 42 indicates the ideal transfer function,

and the solid line represents what the transfer function may

look like with endpoint nonlinearities due to saturation of the

output amplifier. Note that Figure 42 represents a transfer function

in 0 V-to-AV_DDmode only. In 0 V-to-V_REFor 0 V-to-DAC_REF

mode (with V_REF< AV_DDor DAC_REF< AV_DD), the lower nonlinear-

ity is similar. However, the upper portion of the transfer function

follows the ideal line right to the end (V_REFin this case, not AV_DD),

showing no signs of endpoint linearity errors.

Table 64. DACxDAT Registers

Name

Address

Default Value

0x00000000

Access

R/W

DAC0DAT

DAC1DAT

DAC2DAT

DAC3DAT

0xFFFF0604

0xFFFF060C

0xFFFF0614

0xFFFF061C

Rev. D | Page 53 of 110

ADuC7124/ADuC7126

Data Sheet

Configuring DAC Buffers in Op Amp Mode

AV

DD

AV – 100mV

DD

In op amp mode, the DAC output buffers are used as an op amp

with the DAC itself disabled.

If DACBCFG Bit 0 is set, ADC0 is the positive input to the op

amp, ADC1 is the negative input, and DAC0 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC0CON.

If DACBCFG Bit 1 is set, ADC2 is the positive input to the op

amp, ADC3 is the negative input, and DAC1 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC1CON.

100mV

0x00000000

0x0FFF0000

Figure 42. Endpoint Nonlinearities Due to Amplifier Saturation

If DACBCFG Bit 2 is set, ADC4 is the positive input to the op

amp, ADC5 is the negative input, and DAC2 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC2CON.

The endpoint nonlinearities conceptually illustrated in Figure 42

becomes worse as a function of output loading. Most of the

ADuC7124/ADuC7126 data sheet specifications assume a 5 kΩ

resistive load to ground at the DAC output. As the output is

forced to source or sink more current, the nonlinear regions at

the top or bottom (respectively) of Figure 42 become larger.

With larger current demands, this can significantly limit output

voltage swing.

If DACBCFG Bit 3 is set, ADC8 is the positive input to the op

amp, ADC9 is the negative input, and DAC3 is the output. In

this mode, the DAC should be powered down by clearing Bit 0

and Bit 1 of DAC3CON.

DACBCFG Register

References to ADC and the DACs

Name:

DACBCFG

0xFFFF0654

0x00

The ADC and DACs can be configured to use the internal V_REF

or an external reference as a reference source. The internal V_REF

must work with an external 0.47 µF capacitor.

Address:

Default Value:

Access:

Table 66. Reference Source Selection for the ADC and DACs

REFCON[0] DACxCON[1:0] Description

Read/write

0

00

ADC works with an external

reference. DACs are powered

down.

ADC works with an external

reference. DAC works with

Table 67. DACBCFG MMR Bit Descriptions

Bit

[7:4]

3

Description

Reserved. Always set to 0.

0

01

Set this bit to 1 to configure the DAC3 output

buffer in op amp mode.

DAC_REF

.

0

10

11

Reserved.

Clear this bit for the DAC buffer to operate as

normal.

ADC works with an external

reference. DACs work with

internal AV_DD.

ADC works with an internal V_REF

DACs are powered down.

2

1

0

Set this bit to 1 to configure the DAC2 output

buffer in op amp mode.

Clear this bit for the DAC buffer to operate as

normal.

1

00

01

.

ADC works with an external

reference. DACs work with

Set this bit to 1 to configure the DAC1 output

buffer in op amp mode.

Clear this bit for the DAC buffer to operate as

normal.

DAC_REF

ADC and DACs work with an

internal V_REF

.

1

10

11

.

Set this bit to 1 to configure the DAC0 output

buffer in op amp mode.

Clear this bit for the DAC buffer to operate as

normal.

ADC works with an internal V_REF

DACs work with an internal

AV_DD.

Note that if REFCON[1] = 1, the internal V_REFpowers down

and the ADC cannot use the internal V_REF

The DACBCFG write sequence is as follows:

.

1. Write Code 0x9A to Register DACBKEY1.

2. Write user value to Register DACBCFG.

3. Write Code 0x0C to Register DACBKEY2.

Rev. D | Page 54 of 110

Data Sheet

ADuC7124/ADuC7126

DACBKEY1 Register

Table 68. PSMCON MMR Bit Descriptions

Bit Name Description

Name:

DACBKEY1

0xFFFF0650

0x0000

3

CMP

Comparator bit. This is a read-only bit that

directly reflects the state of the comparator.

Read 1 indicates that the IOV_DDsupply is above

its selected trip point or that the PSM is in

power-down mode. Read 0 indicates that the

IOV_DDsupply is below its selected trip point. This

bit should be set before leaving the interrupt

service routine.

Address:

Default Value:

Access:

Write

DACBKEY2 Register

2

1

TP

Trip point selection bits.

0 = 2.79 V, 1 = 3.07 V.

Name:

DACBKEY2

0xFFFF0658

0x0000

Address:

PSMEN Power supply monitor enable bit.

Set to 1 to enable the power supply monitor

circuit.

Default Value:

Access:

Clear to 0 to disable the power supply monitor

circuit.

Write

0

PSMI

Power supply monitor interrupt bit. This bit is set

high by the MicroConverter when CMP goes low,

indicating low I/O supply. The PSMI bit can be

used to interrupt the processor. When CMP

returns high, the PSMI bit can be cleared by

writing a 1 to this location. A 0 write has no

effect. There is no timeout delay; PSMI can be

immediately cleared when CMP goes high.

POWER SUPPLY MONITOR

The power supply monitor regulates the IOV_DDsupply on the

ADuC7124/ADuC7126. It indicates when the IOV_DDsupply pin

drops below one of two supply trip points. The monitor

function is controlled via the PSMCON register. If enabled in

the IRQEN or FIQEN register, the monitor interrupts the core

using the PSMI bit in the PSMCON MMR. This bit is immediately

cleared when CMP goes high.

COMPARATOR

This monitor function allows the user to save working registers

to avoid possible data loss due to low supply or brown-out

conditions. It also ensures that normal code execution does not

resume until a safe supply level is established.

The ADuC7124/ADuC7126 integrate a voltage comparator. The

positive input is multiplexed with ADC2, and the negative input

has two options: ADC3 or DAC0. The output of the comparator

can be configured to generate a system interrupt, be routed

directly to the programmable logic array, start an ADC conver-

sion, or be on an external pin, CMP_OUT, as shown in Figure 43.

PSMCON Register

Name:

PSMCON

0xFFFF0440

0x0008

Address:

Default Value:

Access:

IRQ

ADC2/CMP0

MUX

ADC3/CMP1

MUX

Read/write

DAC0

P0.0/CMP

OUT

Figure 43. Comparator

Hysteresis

Figure 44 shows how the input offset voltage and hysteresis

terms are defined. Input offset voltage (V_OS) is the difference

between the center of the hysteresis range and the ground level.

This can either be positive or negative. The hysteresis voltage

(V_H) is ½ the width of the hysteresis range.

CMP

OUT

V

H

COMP0

V

OS

Figure 44. Comparator Hysteresis Transfer Function

Rev. D | Page 55 of 110

ADuC7124/ADuC7126

Data Sheet

Comparator Interface

Bit

Value Name

Description

1

CMPORI

Comparator output rising edge

interrupt.

Set automatically when a rising

edge occurs on the monitored

voltage (CMP0).

The comparator interface consists of a 16-bit MMR, CMPCON,

which is described in Table 69.

CMPCON Register

Name:

CMPCON

0xFFFF0444

0x0000

Cleared by user by writing a 1 to

this bit.

Address:

Default Value:

Access:

0

CMPOFI

Comparator output falling edge

interrupt.

Set automatically when a falling

edge occurs on the monitored

voltage (CMP0).

Read/write

Cleared by user by writing a 1 to

this bit.

Table 69. CMPCON MMR Bit Descriptions

Bit

Value Name

Description

OSCILLATOR AND PLL—POWER CONTROL

Clocking System

[15:11]

10

Reserved.

CMPEN

Comparator enable bit.

Set by the user to enable the

comparator.

Cleared by the user to disable the

comparator.

The ADuC7124/ADuC7126 integrate a 32.768 kHz 3% oscilla-

tor, a clock divider, and a PLL. The PLL locks onto a multiple

(1275) of the internal oscillator or an external 32.768 kHz crystal to

provide a stable 41.78 MHz clock (UCLK) for the system. To allow

power saving, the core can operate at this frequency or at binary

submultiples of it. The actual core operating frequency, UCLK/2^CD,

is referred to as HCLK. The default core clock is the PLL clock

divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency

can also come from an external clock on the ECLK pin as

shown in Figure 45. The core clock can be output on ECLK

when using an internal oscillator or external crystal.

[9:8]

[7:6]

5

CMPIN

Comparator negative input select

bits.

00

AV_DD/2.

01

ADC3 input.

DAC0 output.

Reserved.

10

11

CMPOC

Comparator output configuration

bits.

00

Reserved.

Note that, when the ECLK pin is used to output the core clock,

the output signal is not buffered and is not suitable for use as a

clock source to an external device without an external buffer.

01

10

Output on CMP_OUT

IRQ.

.

11

CMPOL

Comparator output logic state bit.

When low, the comparator output

is high if the positive input

(CMP0) is above the negative

input (CMP1). When high, the

comparator output is high if the

positive input is below the

negative input.

XCLKO

XCLKI

WATCHDOG

TIMER

INT. 32kHz*

OSCILLATOR

CRYSTAL

OSCILLATOR

OCLK

WAKEUP

TIMER

AT POWER UP

32.768kHz

41.78MHz

PLL

XCLK

[4:3]

CMPRES

00

Response time.

MDCLK

5 µs response time typical for

large signals (2.5 V differential).

17 µs response time typical for

small signals (0.65 mV

UCLK

ANALOG

PERIPHERALS

2

I C

CD

/2

differential).

CORE

HCLK

11

4 µs typical.

Reserved.

01/10

*32.768kHz ±3%

ECLK

2

CMPHYST Comparator hysteresis sit.

Set by user to have a hysteresis of

about 7.5 mV.

Figure 45. Clocking System

The selection of the clock source is in the PLLCON register. By

default, the part uses the internal oscillator feeding the PLL.

Cleared by user to have no

hysteresis.

Rev. D | Page 56 of 110

Data Sheet

ADuC7124/ADuC7126

External Crystal Selection

External Clock Selection

To switch to an external crystal, the user must follow this

procedure:

To switch to an external clock on P0.7, configure P0.7 in

Mode 1. The external clock can be up to 41.78 MHz, providing

the tolerance is 1%.

1. Enable the Timer2 interrupt and configure it for a timeout

period of >120 µs.

2. Follow the write sequence to the PLLCON register, setting

the MDCLK bits to 01 and clearing the OSEL bit.

Example source code:

T2LD = 5;

T2CON = 0x480;

3. Force the part into nap mode by following the correct write

sequence to the POWCON0 register.

IRQEN = 0x10;

4. When the part is interrupted from nap mode by the

Timer2 interrupt source, the clock source has switched to

the external clock.

//enable T2 interrupt

PLLKEY1 = 0xAA;

PLLCON = 0x03; //Select external clock

PLLKEY2 = 0x55;

Example source code:

T2LD = 5;

POWKEY1 = 0x01;

POWCON0 = 0x27;

Set core into nap mode

POWKEY2 = 0xF4;

//

T2CON = 0x480;

IRQEN = 0x10;

//enable T2 interrupt

Power Control System

PLLKEY1 = 0xAA;

PLLCON = 0x01;

PLLKEY2 = 0x55;

A choice of operating modes is available on the ADuC7124/

ADuC7126. Table 70 describes what part is powered on in the

different modes and indicates the power-up time.

POWKEY1 = 0x01;

Table 71 gives some typical values of the total current

consumption (analog + digital supply currents) in the different

modes, depending on the clock divider bits. The AC, DAC, I²C,

and SPI are turned off.

POWCON0 = 0x27; // Set core into nap mode

POWKEY2 = 0xF4;

In noisy environments, noise can couple to the external crystal

pins, and PLL may lose lock momentarily. A PLL interrupt is

provided in the interrupt controller. The core clock is immediately

halted, and this interrupt is serviced only when the lock is restored.

In case of crystal loss, the watchdog timer should be used. During

initialization, a test on the RSTSTA can determine if the reset

came from the watchdog timer.

Table 70. Operating Modes

Mode

Active

Pause

Nap

Sleep

Stop

Core

Peripherals

PLL

On

XTAL/T2/T3

IRQ0 to IRQ3

Start-Up/Power-On Time

66 ms at CD = 0

2.6 µs at CD = 0; 247 µs at CD = 7

1.58 ms

On

1.7 ms

Table 71. Typical Current Consumption at 25°C in mA, V_DD= 3.3 V

Mode

Active

Pause

Nap

Sleep

Stop

CD = 0

33.3

20.6

4.6

0.2

CD = 1

23.1

12.7

4.6

0.2

CD = 2

15.4

8.8

4.6

0.2

CD = 3

11.6

6.8

4.6

0.2

CD = 4

9.7

5.8

4.6

0.2

CD = 5

CD = 6

8.3

5.1

4.6

0.2

CD = 7

8.8

5.3

4.6

0.2

8.1

4.9

4.6

0.2

Rev. D | Page 57 of 110

ADuC7124/ADuC7126

Data Sheet

POWCON0 Register

MMRs and Keys

Name:

POWCON0

0xFFFF0408

0x0003

The operating mode, clocking mode, and programmable clock

divider are controlled via three MMRs, PLLCON (see Table 73),

and POWCONx. PLLCON controls the operating mode of the

clock system, POWCON0 controls the core clock frequency and

the power-down mode, and POWCON1 controls the clock

frequency to I²C and SPI.

Address:

Default Value:

Access:

Read/write

Table 72. PLLKEYx Registers

Table 75. POWCON0 MMR Bit Descriptions

Name

Address

Default Value

0x0000

Access

W

Bit

Value

Name

Description

PLLKEY1

PLLKEY2

0xFFFF0410

0xFFFF0418

7

Reserved.

[6:4]

PC

Operating modes.

Active mode.

Pause mode.

Nap mode.

000

001

010

011

PLLCON Register

Name:

PLLCON

0xFFFF0414

0x21

Sleep mode. IRQ0 to IRQ3 and Timer2

can wake up the part.

Address:

Default Value:

Access:

100

Stop mode. IRQ0 to IRQ3 can wake

up the part.

Read/write

Others

Reserved.

3

Reserved.

Table 73. PLLCON MMR Bit Descriptions

[2:0]

CD

CPU clock divider bits.

41.78 MHz.

20.89 MHz.

10.44 MHz.

5.22 MHz.

Bit

[7:6]

5

Value Name

Description

000

001

010

011

100

101

110

111

Reserved.

OSEL

32 kHz PLL input selection.

Set by the user to select the internal

32 kHz oscillator. Set by default.

Cleared by the user to select the

external 32 kHz crystal.

2.61 MHz.

1.31 MHz.

653 kHz.

[4:2]

[1:0]

Reserved.

326 kHz.

MDCLK Clocking modes.

00

01

10

11

Reserved.

To prevent accidental programming, a certain sequence must be

followed to write to the POWCONx register. The POWCON0

write sequence is as follows:

PLL. Default configuration.

Reserved.

External clock on the P0.7 Pin.

1. Write Code 0x01 to Register POWKEY1.

2. Write a user value to Register POWCON0.

3. Write Code 0xF4 to Register POWKEY2.

To prevent accidental programming, a certain sequence must be

followed to write to the PLLCON register.The PLLCON write

sequence is as follows:

Table 76. POWKEYx Registers

1. Write Code 0xAA to Register PLLKEY1.

2. Write user value to Register PLLCON.

3. Write Code 0x55 to Register PLLKEY2.

Name

Address

Default Value

0x0000

Access

W

POWKEY3

POWKEY4

0xFFFF0434

0xFFFF043C

Table 74. POWKEYx Registers

POWKEY3 and POWKEY4 are used to prevent accidental

programming to POWCON1.

Name

Address

Default Value

0x0000

Access

W

POWKEY1

POWKEY2

0xFFFF0404

0xFFFF040C

POWCON1 Register

Name:

POWCON1

0xFFFF0438

0x124

POWKEY1 and POWKEY2 are used to prevent accidental

programming to POWCON0.

Address:

Default Value:

Access:

Read/write

Rev. D | Page 58 of 110

Data Sheet

ADuC7124/ADuC7126

Table 77. POWCON1 MMR Bit Descriptions¹

The POWCON1 write sequence is as follows:

Bit

Value

Name

Description

1. Write Code 0x76 to Register POWKEY3.

2. Write user value to Register POWCON1.

3. Write Code 0xB1 to Register POWKEY4.

[15:12]

11

Reserved.

1

PWMPO

Clearing this bit powers

down the PWM. Always

clear to 00.

[10:9]

8

00

PWMCLKDIV

SPIPO

Clearing this bit powers

down the SPI.

[7:6]

SPICLKDIV

SPI block driving clock

divider bits.

00

01

10

11

41.78 MHz.

20.89 MHz.

10.44 MHz.

5.22 MHz.

5

I2C1PO

Clearing this bit powers

down I2C1.

[4:3]

I2C1CLKDIV

I2C0 block driving clock

divider bits.

00

01

10

11

41.78 MHz.

10.44 MHz.

5.22 MHz.

1.31 MHz.

2

I2C0PO

Clearing this bit powers

down I2C0.

[1:0]

I2C0CLKDIV

I2C1 block driving clock

divider bits.

00

01

10

11

41.78 MHz.

10.44 MHz.

5.22 MHz.

1.31 MHz.

¹Divided clock for SPI/I2C0/I2C1 must be greater than or equal to the CPU clock

as selected by POWCON0 [2:0].

Rev. D | Page 59 of 110

ADuC7124/ADuC7126

Data Sheet

DIGITAL PERIPHERAL

GENERAL-PURPOSE INPUT/OUTPUT

Table 78. GPIO Pin Function Descriptions

Configuration

The ADuC7124/ADuC7126 provide 40 general-purpose,

bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant,

meaning the GPIOs support an input voltage of 5 V.

Port Pin

BM/P0.0

00

01

10

11

0

1

2

GPIO

CMP

MS0

BLE⁴

BHE⁴

A16⁴

MS1⁴

MS2⁴

MS3⁴

PLAI[7]

TDI/P0.1¹

TDO/P0.2¹

TRST/P0.3¹

P0.4

P0.5

P0.6

GPIO/JTAG

GPIO/IRQ0

GPIO/IRQ1

GPIO

PWM4

PWM5

TRST

PWM_TRIP

ADC_BUSY

MRST

In general, many of the GPIO pins have multiple functions (see

the Pin Configurations and Function Descriptions section for

pin function definitions). By default, the GPIO pins are configured

in GPIO mode.

ADC_BUSY

PLAO[1]

PLAO[2]

PLAO[3]

PLAO[4]

PLAI[0]

PLAI[1]

PLAI[2]

PLAI[3]

PLAI[4]

PLAI[5]

PLAI[6]

PLAO[0]

All GPIO pins have an internal pull-up resistor (of about 100 kΩ),

and their drive capability is 1.6 mA. Note that a maximum of

20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR

registers, it is possible to enable/disable the pull-up resistors for

the following ports: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight

GPIOs of P1.

P0.7

GPIO

ECLK/XCLK²SIN0

P1.0

GPIO/T1

GPIO

SIN0

SOUT0

RTS³

CTS³

RI³

DCD³

DSR³

DTR³

SCL0³

SDA0³

SCL1³

SDA1³

SCLK³

MISO³

MOSI³

CS³

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

GPIO

GPIO/IRQ2

GPIO/IRQ3

GPIO

The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).

Each port is controlled by four or five MMRs.

GPIO

Note that the kernel changes P0.6 from its default configuration

at reset (MRST) to GPIO mode. If MRST is used for external

circuitry, an external pull-up resistor should be used to ensure

that the level on P0.6 does not drop when the kernel switches

mode. Otherwise, P0.6 goes low for the reset period. For example,

if MRST is required for power-down, it can be reconfigured in

GP0CON MMR.

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

GPIO

GPIO/RTCK⁵

GPIO

CONV_START

PWM0

SOUT0 PLAO[5]

WS⁴

PLAO[6]

PLAO[7]

SIN1

PWM1

RS⁴

AE⁴

PWM0

PWM1

PWM2

PWM3

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM_TRIP

PWM_SYNC

SIN1

MS0⁴

MS1⁴

MS2⁴

MS3⁴

AD0⁴

AD1⁴

AD2⁴

AD3⁴

AD4⁴

AD5⁴

AD6⁴

AD7⁴

AD8⁴

AD9⁴

AD10⁴

AD11⁴

AD12⁴

AD13⁴

AD14⁴

AD15⁴

SOUT1

The input level of any GPIO can be read at any time in the

GPxDAT MMR, even when the pin is configured in a mode

other than GPIO. The PLA input is always active.

3

PLAI[8]

PLAI[9]

PLAI[10]

PLAI[11]

PLAI[12]

PLAI[13]

PLAI[14]

PLAI[15]

PLAO[8]

PLAO[9]

PLAO[10]

PLAO[11]

PLAO[12]

PLAO[13]

PLAO[14]

PLAO[15]

When the ADuC7124/ADuC7126 enter a power-saving mode,

the GPIO pins retain their state. Also, note that, by setting

RSTCFG Bit 0, the GPIO pins can retain their state during a

watchdog or software reset.

4

SOUT1

¹These pins should not be used by user code .

²When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To

configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.

³See Table 90 for SPM configurations.

⁴External Memory Interface signals are only available on ADuC7126.

⁵In debug mode, the RTCK mode cannot be disabled.

Rev. D | Page 60 of 110

Data Sheet

ADuC7124/ADuC7126

Table 79. GPxCON Registers

Bit

16

Description

Name

Address

Default Value

0x00000000

Access

R/W

Pull-up disable Px.4.

Reserved.

GP0CON

GP1CON

GP2CON

GP3CON

GP4CON

0xFFFFF400

0xFFFFF404

0xFFFFF408

0xFFFFF40C

0xFFFFF410

15

[14:13]

12

Drive strength Px.3.

Pull-up disable Px.3.

Reserved.

11

R/W

[10:9]

8

Drive strength Px.2.

Pull-up disable Px.2.

Reserved.

GPxCON are the Port x control registers that select the function

of each pin of Port x, as described in Table 80.

7

[6:5]

4

Drive strength Px.1.

Pull-up disable Px.1.

Reserved.

Table 80. GPxCON MMR Bit Descriptions

Bit

Description

3

[31:30]

[29:28]

[27:26]

[25:24]

[23:22]

[21:20]

[19:18]

[17:16]

[15:14]

[13:12]

[11:10]

[9:8]

Reserved.

[2:1]

0

Drive strength Px.0.

Pull-up disable Px.0.

Select function of Px.7 pin.

Reserved.

Table 83. GPIO Drive Strength Control Bits Descriptions

Control Bits Value

Select function of Px.6 pin.

Reserved.

Description

00

01

1x

Medium drive strength.

Low drive strength.

High drive strength.

Select function of Px.5 pin.

Reserved.

Select function of Px.4 pin.

Reserved.

Select function of Px.3 pin.

Reserved.

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

HIGH DRIVE STRENGTH

Select function of Px.2 pin.

Reserved.

MEDIUM DRIVE STRENGTH

LOW DRIVE STRENGTH

[7:6]

[5:4]

Select function of Px.1 pin.

Reserved.

[3:2]

[1:0]

Select function of Px.0 pin.

Table 81. GPxPAR Registers

Name

Address

Default Value

0x20000000

0x00000000

0x000000FF

0x00222222

0x00000000

Access

R/W

GP0PAR

GP1PAR

GP2PAR

GP3PAR

GP4PAR

0xFFFFF42C

0xFFFFF43C

0xFFFFF44C

0xFFFFF45C

0xFFFFF46C

–24

–18

–12

–6

0

6

12

18

24

SINK/SOURCE CURRENT (mA)

R/W

Figure 46. Programmable Strength for High Level

0.5

0.4

The GPxPAR registers program the parameters for Port 0, Port 1,

Port 2, Port 3, and Port 4. Note that the GPxDAT MMR must

always be written after changing the GPxPAR MMR.

HIGH DRIVE STRENGTH

MEDIUM DRIVE STRENGTH

LOW DRIVE STRENGTH

0.3

Table 82. GPxPAR MMR Bit Descriptions

0.2

Bit

Description

0.1

31

Reserved.

0

[30:29]

28

Drive strength Px.7.

Pull-up disable Px.7.

Reserved.

–0.1

–0.2

–0.3

–0.4

27

[26:25]

24

Drive strength Px.6.

Pull-up disable Px.6.

Reserved.

23

–24

–18

–12

–6

0

6

12

18

24

[22:21]

20

Drive strength Px.5.

Pull-up disable Px.5.

Reserved.

SINK/SOURCE CURRENT (mA)

Figure 47. Programmable Strength for Low Level

19

[18:17]

Drive strength Px.4.

Rev. D | Page 61 of 110

ADuC7124/ADuC7126

Data Sheet

The drive strength bits can be written only once after reset.

Additional writing to related bits has no effect on drive strength.

The GPIO drive strength and pull-up disable are not always

adjustable for GPIO port. Some control bits cannot be changed.

See Table 78 for details.

Table 89. GPxCLR MMR Bit Descriptions

Bit

Description

[31:24]

[23:16]

Reserved.

Data Port x clear bit.

Set to 1 by the user to clear a bit on Port x; also clears

the corresponding bit in the GPxDAT MMR.

Cleared to 0 by the user; does not affect the data out.

Table 84. GPxDAT Registers

Name

Address

Default Value

0x000000XX

Access

R/W

[15:0]

Reserved.

GP0DAT

GP1DAT

GP2DAT

GP3DAT

GP4DAT

0xFFFFF420

0xFFFFF430

0xFFFFF440

0xFFFFF450

0xFFFFF460

SERIAL PORT MUX

The serial port mux multiplexes the serial port peripherals

(an SPI, UART, and two I²Cs) and the programmable logic array

(PLA) to a set of 10 GPIO pins. Each pin must be configured to

one of its specific I/O functions as described in Table 90.

R/W

The GPxDAT are Port x configuration and data registers. They

configure the direction of the GPIO pins of Port x, set the

output value for the pins configured as output, and store the

input value of the pins configured as input.

Table 90. SPM Configuration

GPIO UART

UART/I²C/SPI

(10)

PLA

(11)

SPM

(00)

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P0.7

P2.0

P4.0

P4.1

P2.3

P2.4

(01)

SPM0

SPM1

SPM2

SPM3

SPM4

SPM5

SPM6

SPM7

SPM8

SPM9

SPM10

SPM11

SPM12

SPM13

SIN0

SOUT0

RTS

CTS

RI

DCD

DSR

DTR

I2C0SCL

I2C0SDA

I2C1SCL

I2C1SDA

SCLK

MISO

MOSI

CS

PLAI[0]

PLAI[1]

PLAI[2]

PLAI[3]

PLAI[4]

PLAI[5]

PLAI[6]

PLAO[0]

PLAO[4]

PLAO[5]

PLAO[8]

PLAO[9]

SIN1

Table 85. GPxDAT MMR Bit Descriptions

Bit

Description

[31:24]

Direction of the data.

Set to 1 by the user to configure the GPIO pin as

an output.

Cleared to 0 by the user to configure the GPIO pin

as an input.

[23:16]

[15:8]

[7:0]

Port x data output.

Reflect the state of Port x pins at reset (read only).

Port x data input (read only).

ECLK/XCLK

CONV_START

SIN1

SOUT1

N/A

SIN0

SOUT0

AD8

AD9

AE

Table 86. GPxSET Registers

Name

Address

Default Value

0x000000XX

Access

GP0SET

GP1SET

GP2SET

GP3SET

GP4SET

0xFFFFF424

0xFFFFF434

0xFFFFF444

0xFFFFF454

0xFFFFF464

W

PWM0

MSO

SOUT1

Table 90 also details the mode for each of the SPMMUX pins.

This configuration has to be done via the GP0CON, GP1CON,

and GP2CON MMRs. By default, these 10 pins are configured

as GPIOs.

The GPxSET are data set Port x registers.

UART SERIAL INTERFACE

Table 87. GPxSET MMR Bit Descriptions

The UART peripheral is a full-duplex, universal, asynchronous

receiver/transmitter. The UART performs serial-to-parallel conver-

sions on data characters received from a peripheral device and

parallel-to-serial conversions on data characters received from

the CPU. The ADuC7124/ADuC7126 has been equipped with

two industry standard 16,450 type UARTs (UART0 and UART1).

Each UART features a fractional divider that facilitates high accu-

racy baud rate generation and is equipped with a 16-byte FIFO

for the transmitter and a 16-byte FIFO for the receiver. Both

UARTs can be configured as FIFO mode and non-FIFO mode.

Bit

Description

[31:24]

[23:16]

Reserved.

Data Port x set bit.

Set to 1 by the user to set a bit on Port x; also sets the

corresponding bit in the GPxDAT MMR.

Cleared to 0 by the user; does not affect the data output.

[15:0]

Reserved.

Table 88. GPxCLR Registers

Name

Address

Default Value

0x000000XX

Access

The serial communication adopts an asynchronous protocol,

which supports various word lengths, stop bits, and parity

generation options selectable in the configuration register.

GP0CLR

GP1CLR

GP2CLR

GP3CLR

GP4CLR

0xFFFFF428

0xFFFFF438

0xFFFFF448

0xFFFFF458

0xFFFFF468

W

The GPxCLR are data clear Port x registers.

Rev. D | Page 62 of 110

Data Sheet

ADuC7124/ADuC7126

Baud Rate Generation

Error is 0%, compared to 6.25% with the normal baud rate

generator.

There are two ways of generating the UART baud rate, using

normal 450 UART baud rate generation and using the fractional

divider.

UART Register Definitions

COM0TX Register

Normal 450 UART Baud Rate Generation

Name:

COM0TX

0xFFFF0700

0x00

The baud rate is a divided version of the core clock using the value

in the COMxDIV0 and COMxDIV1 MMRs (16-bit value, DL).

Address:

Default Value:

Access:

41.78MHz

^CD× 16 × 2 ×DL

Baud Rate =

2

Read/write

Table 91 gives some common baud rate values.

COM0TX is an 8-bit transmit register for UART0.

Table 91. Baud Rate Using the Normal Baud Rate Generator

COM1TX Register

Baud Rate

CD

DL

Actual Baud Rate

% Error

Name:

COM1TX

0xFFFF0740

0x00

9600

0

3

0x88

0x44

0x0B

0x11

0x08

0x01

9600

19,200

118,691

9600

20,400

0

3

0

19,200

115,200

9600

19,200

115,200

Address:

Default Value:

Access:

6.25

41.67

Read/write

163,200

COM1TX is an 8-bit transmit register for UART1.

The Fractional Divider

COM0RX Register

The fractional divider, combined with the normal baud rate

generator, produces a wider range of more accurate baud rates.

Name:

COM0RX

0xFFFF0700

0x00

FBEN

CORE

CLOCK

÷ 2

Address:

Default Value:

Access:

÷ 16DL

UART

÷ (M + N ÷ 2048)

Read only

Figure 48. Baud Rate Generation Options

COM0RX is an 8-bit receive register for UART0.

Calculation of the baud rate using fractional divider is as follows:

COM1RX Register

41.78 MHz

Baud Rate =

Name:

COM1RX

0xFFFF0740

0x00

N

2048









2

^CD×16×DL×2× M +





Address:

Default Value:

Access:

41.78 MHz

Baud Rate × 2^CD× 16 ×DL×2

N

M +

=

2048

Read only

For example, generation of 19,200 baud with CD bits = 3

(Table 91 gives DL = 0x08) is

COM1RX is an 8-bit receive register for UART1.

41.78 MHz

N

COM0DIV0 Register

M +

=

2048 19,200 ×2³×16×8×2

Name:

COM0DIV0

0xFFFF0700

0x00

N

=1.06

2048

Address:

Default Value:

Access:

where:

M = 1.

N = 0.06 × 2048 = 128.

Read/write

COM0DIV0 is a low byte divisor latch for UART0. COM0TX,

COM0RX, and COM0DIV0 share the same address location.

COM0TX and COM0RX can be accessed when Bit 7 in the

COM0CON0 register is cleared. COM0DIV0 can be accessed

when Bit 7 of COM0CON0 is set.

41.78 MHz

Baud Rate

=

128











2³×16×8×2×



2048

where:

Baud Rate = 19,200 bps.

Rev. D | Page 63 of 110

ADuC7124/ADuC7126

Data Sheet

COM1DIV0 Register

COM0DIV1 Register

Name:

COM1DIV0

Name:

COM0DIV1

0xFFFF0704

0x00

Address:

Default Value:

Access:

0xFFFF0740

0x00

Address:

Default Value:

Access:

Read/write

COM1DIV0 is a low byte divisor latch for UART1. COM1TX,

COM1RX, and COM1DIV0 share the same address location.

COM1TX and COM1RX can be accessed when Bit 7 in

COM1CON0 register is cleared. COM1DIV0 can be accessed

when Bit 7 of COM1CON0 is set.

COM0DIV1 is a divisor latch (high byte) register for UART0.

COM1DIV1 Register

Name:

COM1DIV1

0xFFFF0744

0x00

Address:

Default Value:

Access:

COM0IEN0 Register

Name:

COM0IEN0

0xFFFF0704

0x00

Read/write

Address:

Default Value:

Access:

COM1DIV1 is a divisor latch (high byte) register for UART1.

COM0IID0 Register

Read/write

Name:

COM0IID0

0xFFFF0708

0x01

COM0IEN0 is the interrupt enable register for UART0.

Address:

Default Value:

Access:

COM1IEN0 Register

Name:

COM1IEN0

0xFFFF0744

0x00

Read only

Address:

Default Value:

Access:

COM0IID0 is the interrupt identification register for UART0. It

also indicates if the UART is in FIFO mode.

Read/write

COM1IID0 Register

Name:

COM1IID0

0xFFFF0748

0x01

COM1IEN0 is the interrupt enable register for UART1.

Address:

Default Value:

Access:

Table 92. COMxIEN0 MMR Bit Descriptions

Bit

[7:4]

3

Name

Description

Reserved.

Read only

EDSSI

Modem status interrupt enable bit.

Set by the user to enable generation of an

interrupt if any of COMXSTA1[3:1] are set.

Cleared by the user.

COM1IID0 is the interrupt identification register for UART1. It

also indicates if the UART is in FIFO mode.

2

1

0

ELSI

Rx status interrupt enable bit.

Set by the user to enable generation of an

interrupt if any of COMxSTA0[3:0] are set.

Cleared by the user.

ETBEI

ERBFI

Enable transmit buffer empty interrupt.

Set by the user to enable interrupt when the

buffer is empty during a transmission.

Cleared by the user.

Enable receive buffer full interrupt.

In non-FIFO mode, set by the user to enable

an interrupt when buffer is full during a

reception. Cleared by the user.

In FIFO mode, set by the user to enable an

interrupt when trigger level is reached. It also

controls the character receive timeout

interrupt. Cleared by the user.

Rev. D | Page 64 of 110

Data Sheet

ADuC7124/ADuC7126

COM1FCR Register

Table 93. COMxIID0 MMR Bit Descriptions

Bit

Name

Description

Name:

COM1FCR

0xFFFF0748

0x00

[7:6] FIFOMODE

FIFO mode flag.

0x0: non-FIFO mode.

0x1: reserved.

0x2: reserved.

0x3: FIFO mode. Set automatically if

FIFOEN is set.

Address:

Default Value:

Access:

Read/write

[5:4] Reserved

The FIFO control register (FCR) is a write-only register at the

same address as the interrupt identification register (IIR), which

is a read-only register.

[3:1] STATUS[2:0] Interrupt status bits that work only when

NINT is set.

[000]: modem status interrupt. Cleared by

reading COMxSTA1. Priority 4.

[001]: for non-FIFO mode, transmit buffer

empty interrupt.

For FIFO mode, Tx FIFO is empty.

Cleared by writing COMxTX or reading

COMxIID0. Priority 3.

[010]: non-FIFO mode. Receive buffer data

ready interrupt. Cleared automatically by

reading COMxRX.

Table 94. COMxFCR MMR Bit Descriptions

Bit

Name

Description

[7:5] RXFIFOTL Receiver FIFO trigger level. RXFIFOTL sets the

trigger level for the receiver FIFO. When the

trigger level is reached, a receiver data-ready

interrupt is generated (if the interrupt

request is enabled). When the FIFO drops

below the trigger level, the interrupt is

cleared.

For FIFO mode, set trigger level reached.

Cleared automatically when FIFO drops

below the trigger level. Priority 2.

[011]: receive line status error interrupt.

Cleared by reading COMxSTA0. Priority 1.

[110]: Rx FIFO timeout interrupt (FIFO

mode only). Set automatically if there is at

least one byte in the Rx FIFO, and there is

no access to the Rx FIFO in the next four-

frames accessing cycle. Cleared by reading

COMxRX, setting RXRST, or when a new

byte arrives in the Rx FIFO¹. Priority 2.

[Other state]: reserved.

0x0: one byte.

0x1: two bytes.

0x2: four bytes.

0x3: six bytes.

0x4: eight bytes.

0x5: 10 bytes.

0x6: 12 bytes.

0x7: 14 bytes.

[4:3] Reserved

2

1

0

TXRST

RXRST

FIFOEN

Tx FIFO reset. Writing a 1 flushes the Tx FIFO.

Does not affect shift register. Note that

TXRST should be cleared manually to make

Tx FIFO work after flushing.

0

NINT

Set to disable interrupt flags by

STATUS[2:0]. Clear to enable interrupt.

Rx FIFO reset. Writing a 1 flushes the Rx FIFO.

Does not affect shift register. Note that

RXRST should be cleared manually to make

the Rx FIFO work after flushing.

¹A frame time is the time allotted for one start bit, n data bits, one parity bit,

and one stop bit. Here, n is the word length selected with the WLS bits in

COMxCON0.

WLS[1:0] = 00: timeout threshold = time for 32 bits = (1 + 5 + 1 + 1) × 4.

WLS[1:0] = 01: timeout threshold = time for 36 bits = (1 + 6 + 1 + 1) × 4.

WLS[1:0] = 10: timeout threshold = time for 40 bits = (1 + 7 + 1 + 1) × 4.

WLS[1:0] = 11: timeout threshold = time for 44 bits = (1 + 8 + 1 + 1) × 4.

Transmitter and receiver FIFOs mode enable.

FIFOEN must be set before other FCR bits are

written to. Set for FIFO mode. The transmitter

and receiver FIFOs are enabled. Cleared for

non-FIFO mode; the transmitter and receiver

FIFOs are disabled, and the FIFO pointers are

cleared.

COM0FCR Register

Name:

COM0FCR

0xFFFF0708

0x00

Address:

Default Value:

Access:

COM0CON0 Register

Name:

COM0CON0

0xFFFF070C

0x00

Read/write

Address:

The FIFO control register (FCR) is a write-only register at the

same address as the interrupt identification register (IIR), which

is a read-only register.

Default Value:

Access:

Read/write

COM0CON0 is the line control register for UART0.

Rev. D | Page 65 of 110

ADuC7124/ADuC7126

Data Sheet

COM1CON1 Register

COM1CON0 Register

Name:

COM1CON1

Name:

COM1CON0

0xFFFF074C

0x00

Address:

0xFFFF0750

0x00

Address:

Default Value:

Access:

Default Value:

Access:

Read/write

COM1CON1 is the modem control register for UART1.

COM1CON0 is the line control register for UART1.

Table 96. COMxCON1 MMR Bit Descriptions

Table 95. COMxCON0 MMR Bit Descriptions

Bit

[7:5]

4

Name

Description

Bit

Name Description

Reserved.

7

DLAB

Divisor latch access.

Set by the user to enable access to the

COMxDIV0 and COMxDIV1 registers.

Cleared by the user to disable access to

COMxDIV0 and COMxDIV1 and enable access to

COMxRX and COMxTX.

LOOPBACK Loop back.

Set by the user to enable loopback mode.

In loopback mode, SOUTx is forced high.

The modem signals are also directly con-

nected to the status inputs (RTS to CTS and

DTR to DSR).

6

5

4

3

BRK

SP

Set break.

Set by the user to force SOUTx to 0.

Cleared to operate in normal mode.

Cleared by the user to be in normal mode.

3

2

PEN

Parity enable bit.

Set by the user to transmit and check the

parity bit.

Cleared by the user for no parity transmission

or checking.

Stick parity.

Set by the user to force parity to defined values:

1 if EPS = 1 and PEN = 1, 0 if EPS = 0 and PEN = 1.

EPS

PEN

Even parity select bit.

Set for even parity.

Cleared for odd parity.

Stop

Stop bit.

Set by the user to transmit 1½ stop bits if

the word length is five bits or two stop bits

if the word length is six bits, seven bits, or

eight bits. The receiver checks the first stop

bit only, regardless of the number of stop

bits selected.

Parity enable bit.

Set by the user to transmit and check the

parity bit.

Cleared by the user for no parity transmission or

checking.

Cleared by the user to generate one stop

bit in the transmitted data.

2

Stop

Stop bit.

Set by the user to transmit 1½ stop bits if the word

length is five bits or two stop bits if the word

length is six bits, seven bits, or eight bits. The

receiver checks the first stop bit only, regardless

of the number of stop bits selected.

Cleared by the user to generate one stop bit in

the transmitted data.

1

0

RTS

DTR

Request to send.

Set by the user to force the RTS output to 0.

Cleared by the user to force the RTS output

to 1.

Data terminal ready.

Set by the user to force the DTR output to

0.

Cleared by the user to force the DTR output

to 1.

[1:0] WLS

Word length select:

00 = five bits, 01 = six bits, 10 = seven bits, 11 =

eight bits.

COM0CON1 Register

COM0STA0 Register

Name:

COM0CON1

0xFFFF0710

0x00

Name:

COM0STA0

0xFFFF0714

0xE0

Address:

Default Value:

Access:

Default Value:

Access:

Read/write

Read only

COM0CON1 is the modem control register for UART0.

COM0STA0 is the line status register for UART0.

Rev. D | Page 66 of 110

Data Sheet

ADuC7124/ADuC7126

COM1STA0 Register

Bit Name

1 OE

Description

Overrun error.

Name:

COM1STA0

0xFFFF0754

0xE0

For non-FIFO mode, set automatically if

data is overwritten before being read.

Cleared automatically.

Address:

Default Value:

Access:

For FIFO mode, set automatically if an

overrun error has been detected. An

overrun error occurs only after the FIFO

is full and the next character has been

completely received in the shift register.

The new character overwrites the

character in the shift register, but it is

not transferred to the FIFO.

Read only

COM1STA0 is the line status register for UART1.

Table 97. COMxSTA0 MMR Bit Descriptions

Bit Name

Description

0

DR

Data ready.

11 RX_error

Set automatically if PE, FE, or BI is set.

Cleared automatically when PE, FE, and

BI are cleared .

For non-FIFO mode, set automatically

when COMxRX is full. Cleared by reading

COMxRX.

For FIFO mode, set automatically when

there is at least one unread byte in the

COMxRX.

10 RX_timeout

Only for FIFO mode. Set automatically if

there is at least one byte in the Rx FIFO

and there is no access to the Rx FIFO in

the next 4-byte accessing cycle.

9

RX_triggered

Only for FIFO mode. Set automatically if

the Rx FIFO number exceeds the trigger

level, which is configured by the FIFO

control register COMxFCR[7:5]. Cleared

automatically when the Rx FIFO number

is equal to or less than the trigger level.

COM0STA1 Register

Name:

COM0STA1

0xFFFF0718

0x00

Address:

Default Value:

Access:

8

7

TX_full

Only for FIFO mode. Set automatically if

Tx FIFO is full. Cleared automatically

when Tx FIFO is not full.

Read only

TX_half_empty Only for FIFO mode. Set automatically if

the Tx FIFO is half empty (number of

bytes in Tx FIFO ≤ 8). Cleared automati-

cally when the Tx FIFO received bytes is

more than eight bytes.

COM0STA1 is a modem status register.

COM1STA1 Register

Name:

COM1STA1

Address:

Default Value:

Access:

0xFFFF0758

0x00

6

5

TEMT

COMxTX empty status bit.

For non-FIFO mode, both THR and TSR

are empty.

For FIFO mode, both Tx FIFO and TSR are

empty.

Read only

THRE

COMxTX and transmitter shift register

empty.

COM1STA1 is a modem status register.

For non-FIFO mode, transmitter hold

register (THR) empty or the content of

THR has been transferred to the

transmitter shift register (TSR).

For FIFO mode, Tx FIFO is empty, or the

last character in the FIFO has been

transferred to the transmitter shift

register (TSR).

Table 98. COMxSTA1 MMR Bit Descriptions

Bit Name Description

7

6

5

4

3

DCD

RI

Data carrier detect.

Ring indicator.

Data set ready.

Clear to send.

DSR

CTS

DDCD Delta DCD. Set automatically if DCD changed

state since last COMxSTA1 read. Cleared

automatically by reading COMxSTA1.

4

BI

Break error.

Set when SINx is held low for more than

the maximum word length.

Cleared automatically.

2

1

0

TERI

Trailing edge RI. Set if RI changed from 0 to 1

since COMxSTA1 last read. Cleared automatically

by reading COMxSTA1.

3

2

FE

PE

Framing error.

Set when an invalid stop bit occurs.

Cleared automatically.

DDSR Delta DSR. Set automatically if DSR changed state

since COMxSTA1 last read. Cleared automatically

by reading COMxSTA1.

Parity error.

Set when a parity error occurs.

Cleared automatically.

DCTS

Delta CTS. Set automatically if CTS changed state

since COMxSTA1 last read. Cleared automatically

by reading COMxSTA1.

Rev. D | Page 67 of 110

ADuC7124/ADuC7126

Data Sheet

COM0DIV2 Register

(data out) should be connected to the MOSI line in the slave

device (data in). The data is transferred as byte wide (8-bit)

serial data, MSB first.

Name:

COM0DIV2

0xFFFF072C

0x0000

Address:

SCLK (Serial Clock I/O) Pin

Default Value:

Access:

The master serial clock (SCLK) synchronizes the data being

transmitted and received through the MOSI SCLK period.

Therefore, a byte is transmitted/received after eight SCLK

periods. The SCLK pin is configured as an output in master

mode and as an input in slave mode.

Read/write

COM0DIV2 is a 16-bit fractional baud divide register for

UART0.

In master mode, polarity and phase of the clock are controlled

by the SPICON register, and the bit rate is defined in the

SPIDIV register as follows:

COM1DIV2 Register

Name:

COM1DIV2

0xFFFF076C

0x0000

Address:

Default Value:

Access:

f_UCLK

2(1 SPIDIV)

f_{SERIAL CLOCK}



The maximum speed of the SPI clock is independent of the

clock divider bits.

Read/write

COM1DIV2 is a 16-bit fractional baud divide register for UART1.

In slave mode, the SPICON register must be configured with

the phase and polarity of the expected input clock. The slave

accepts data from an external master up to 10 Mbps.

Table 99. COMxDIV2 MMR Bit Descriptions

Bit

Name

Description

In both master and slave modes, data is transmitted on one edge

of the SCLK signal and sampled on the other. Therefore, it is

important that the polarity and phase be configured the same

for the master and slave devices.

15

FBEN

Fractional baud rate generator enable bit.

Set by the user to enable the fractional

baud rate generator.

Cleared by the user to generate the baud

rate using the standard 450 UART baud

rate generator.

(SPI Chip Select Input) Pin

CS

In SPI slave mode, a transfer is initiated by the assertion of

,

[14:13]

Reserved.

which is an active low input signal. The SPI port then transmits

and receives 8-bit data until the transfer is concluded by deasser-

[12:11] FBM[1:0]

M if FBM = 0, M = 4 (see The Fractional

Divider section).

[10:0]

FBN[10:0] N (see The Fractional Divider section).

CS

tion of . In slave mode,

is always an input.

CS

In SPI master mode, the

is an active low output signal. It

asserts itself automatically at the beginning of a transfer and

deasserts itself upon completion.

SERIAL PERIPHERAL INTERFACE

The ADuC7124/ADuC7126 integrate a complete hardware serial

peripheral interface (SPI) on chip. SPI is an industry standard,

synchronous serial interface that allows eight bits of data to be

synchronously transmitted and simultaneously received, that is,

full duplex up to a maximum bit rate of 20 Mbps.

Configuring External Pins for SPI functionality

The SPI pins of the ADuC7124/ADuC7126 device are P1.4 to

P1.7.

P1.7 is the slave chip select pin. In slave mode, this pin is an

input and must be driven low by the master. In master mode,

this pin is an output and goes low at the beginning of a transfer

and high at the end of a transfer.

The SPI port can be configured for master or slave operation

and typically consists of four pins: MISO, MOSI, SCLK, and

CS

.

MISO (Master In, Slave Out) Pin

P1.4 is the SCLK pin.

The MISO pin is configured as an input line in master mode

and an output line in slave mode. The MISO line on the master

(data in) should be connected to the MISO line in the slave

device (data out). The data is transferred as byte wide (8-bit)

serial data, MSB first.

P1.5 is the master in, slave out (MISO) pin.

P1.6 is the master out, slave in (MOSI) pin.

To configure P1.4 to P1.7 for SPI mode, see the General-

Purpose Input/Output section.

MOSI (Master Out, Slave In) Pin

The MOSI pin is configured as an output line in master mode

and an input line in slave mode. The MOSI line on the master

Rev. D | Page 68 of 110

Data Sheet

ADuC7124/ADuC7126

SPI Registers

The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.

SPI Status Register

Name:

SPISTA

Address:

Default Value:

Access:

0xFFFF0A00

0x0000

Read only

Function:

This 32-bit MMR contains the status of the SPI interface in both master and slave modes.

Table 100. SPISTA MMR Bit Descriptions

Bit

Name

Description

[15:12]

11

Reserved.

SPIREX

SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the

SPIMDE bits in SPICON

This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.

SPI Rx FIFO status bits.

[10:8]

SPIRXFSTA[2:0]

[000] = Rx FIFO is empty.

[001] = one valid byte in the FIFO.

[010] = two valid bytes in the FIFO.

[011] = three valid bytes in the FIFO.

[100] = four valid bytes in the FIFO.

7

SPIFOF

SPI Rx FIFO overflow status bit.

Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt

except when SPIRFLH is set in SPICON.

Cleared when the SPISTA register is read.

SPI Rx IRQ status bit.

Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required

number of bytes has been received.

Cleared when the SPISTA register is read.

SPI Tx IRQ status bit.

6

SPIRXIRQ

SPITXIRQ

SPITXUF

5

Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number

of bytes has been transmitted.

Cleared when the SPISTA register is read.

SPI Tx FIFO underflow.

4

This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt

except when SPITFLH is set in SPICON.

Cleared when the SPISTA register is read.

SPI Tx FIFO status bits.

[3:1]

SPITXFSTA[2:0]

[000] = Tx FIFO is empty.

[001] = one valid byte in the FIFO.

[010] = two valid bytes in the FIFO.

[011] = three valid bytes in the FIFO.

[100] = four valid bytes in the FIFO.

SPI interrupt status bit.

0

SPIISTA

Set to 1 when an SPI-based interrupt occurs.

Cleared after reading SPISTA.

Rev. D | Page 69 of 110

ADuC7124/ADuC7126

Data Sheet

SPIRX Register

SPIDIV Register

Name:

SPIRX

Name:

SPIDIV

Address:

Default Value:

Access:

0xFFFF0A04

Address:

0xFFFF0A0C

0x00

Default Value: 0x00

Read only

Access:

Read/write

Function:

This 8-bit MMR is the SPI receive register.

Function:

This 8-bit MMR is the SPI baud rate selection

register.

SPITX Register

SPICON Register

Name:

SPITX

Name:

SPICON

Address:

0xFFFF0A08

Address:

0xFFFF0A10

Default Value:

Access:

0x00

Default Value: 0x0000

Write only

Access:

Read/write

Function:

This 8-bit MMR is the SPI transmit register.

Function:

This 16-bit MMR configures the SPI

peripheral in both master and slave modes.

Table 101. SPICON MMR Bit Descriptions

Bit Name Description

[15:14] SPIMDE

SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer.

[00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have

been received into the FIFO.

[01] = Tx interrupt occurs when two bytes have been transferred. Rx interrupt occurs when two or more bytes have

been received into the FIFO.

[10] = Tx interrupt occurs when three bytes have been transferred. Rx interrupt occurs when three or more bytes

have been received into the FIFO.

[11] = Tx interrupt occurs when four bytes have been transferred. Rx interrupt occurs when the Rx FIFO is full or four

bytes are present.

13

12

11

SPITFLH

SPIRFLH

SPICONT

SPI Tx FIFO flush enable bit.

Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required.

If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit.

Any writes to the Tx FIFO are ignored while this bit is set.

Clear this bit to disable Tx FIFO flushing.

SPI Rx FIFO flush enable bit.

Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required.

If this bit is set incoming, data is ignored and no interrupts are generated.

If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer.

Clear this bit to disable Rx FIFO flushing.

Continuous transfer enable.

Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available

in the SPITX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is

empty.

Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer.

If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle.

10

SPILP

Loopback enable bit.

Set by the user to connect MISO to MOSI and test software.

Cleared by the user to be in normal mode.

Rev. D | Page 70 of 110

Data Sheet

ADuC7124/ADuC7126

Bit

Name

Description

9

SPIOEN

Slave MISO output enable bit.

Set this bit for MISO to operate as normal.

Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared.

SPIRX overflow overwrite enable.

Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received.

Cleared by the user, the new serial byte received is discarded.

SPI transmits zeros when Tx FIFO is empty.

Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.

Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.

SPI transfer and interrupt mode.

Set by the user to initiate transfer with a write to the SPITX register. Interrupt occurs only when SPITX is empty.

Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when SPIRX is full.

LSB first transfer enable bit.

8

7

6

5

4

3

2

1

0

SPIROW

SPIZEN

SPITMDE

SPILF

Set by the user, the LSB is transmitted first.

Cleared by the user, the MSB is transmitted first.

SPIWOM

SPICPO

SPICPH

SPIMEN

SPIEN

SPI wire-OR’ed mode enable bit.

Set to 1 enable open-drain data output. External pull-ups required on data output pins.

Cleared for normal output levels.

Serial clock polarity mode bit.

Set by the user, the serial clock idles high.

Cleared by the user, the serial clock idles low.

Serial clock phase mode bit.

Set by the user, the serial clock pulses at the beginning of each serial bit transfer.

Cleared by the user, the serial clock pulses at the end of each serial bit transfer.

Master mode enable bit.

Set by the user to enable master mode.

Cleared by the user to enable slave mode.

SPI enable bit.

Set by the user to enable the SPI.

Cleared by the user to disable the SPI.

Rev. D | Page 71 of 110

ADuC7124/ADuC7126

Data Sheet

Configuring External Pins for I²C Functionality

The I²C pins of the ADuC7124/ADuC7126 device are P1.0 and

P1.1 for I2C0 and P1.2 and P1.3 for I2C1.

P1.0 and P1.2 are the I²C clock signals, and P1.1 and P1.3 are

the I²C data signals. For instance, to configure I2C0 pins (SCL0,

SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1

to enable I²C mode. On the other hand, to configure I2C1 pins

(SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must

be set to 1 to enable I²C mode, as shown in the General-Purpose

Input/Output section.

I²C

The ADuC7124/ADuC7126 incorporate two I²C peripherals

that can be configured as a fully I²C-compatible I²C bus master

device or as a fully I²C bus compatible slave device. Both I²C

channels are identical. Therefore, the following descriptions

apply to both channels.

The two pins used for data transfer, SDA and SCL, are configured

in a wire-AND’ed format that allows arbitration in a multimaster

system. These pins require external pull-up resistors. Typical

pull-up values are between 4.7 kΩ and 10 kΩ.

The I²C bus peripheral address in the I²C bus system is

programmed by the user. This ID can be modified any time a

transfer is not in progress. The user can configure the interface

to respond to four slave addresses.

Serial Clock Generation

The I²C master in the system generates the serial clock for a

transfer. The master channel can be configured to operate in

fast mode (400 kHz) or standard mode (100 kHz).

The transfer sequence of an I²C system consists of a master

device initiating a transfer by generating a start condition while

the bus is idle. The master transmits the slave device address

and the direction of the data transfer (read or/write) during the

initial address transfer. If the master does not lose arbitration

and the slave acknowledges, the data transfer is initiated. This

continues until the master issues a stop condition and the bus

becomes idle.

The bit rate is defined in the I2CxDIV MMR as follows:

f_UCLK

f_{SERIAL CLOCK}

=

(2 + DIVH) +(2 + DIVL)

where:

_UCLKis the clock before the clock divider.

f

DIVH is the high period of the clock.

DIVL is the low period of the clock.

The I²C peripheral can only be configured as a master or slave at

any given time. The same I²C channel cannot simultaneously

support master and slave modes.

The I²C interface on the ADuC7124/ADuC7126 includes the

following features:

Therefore, for 100 kHz operation,

DIVH = DIVL = 0xCF

and for 400 kHz

DIVH = 0x28, DIVL = 0x3C

The I2CxDIV register corresponds to DIVH:DIVL.

I²C Bus Addresses

•

Support for repeated start conditions. In master mode, the

ADuC7124/ADuC7126 can be programmed to generate a

repeated start. In slave mode, the ADuC7124/ADuC7126

recognizes repeated start conditions.

Slave Mode

In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3

registers contain the device IDs. The device compares the four

I2CxIDx registers to the address byte received from the bus

master. To be correctly addressed, the seven MSBs of either ID

register must be identical to the seven MSBs of the first received

address byte. The LSB of the ID registers (the transfer direction

bit) is ignored in the process of address recognition.

•

In master and slave mode, the part recognizes both 7-bit

and 10-bit bus addresses.

In I²C master mode, the ADuC7124/ADuC7126 supports

continuous reads from a single slave up to 512 bytes in a

single transfer sequence.

•

Clock stretching can be enabled by other devices on the

bus without causing any issues with the ADuC7124/

ADuC7126. However, the ADuC7124/ADuC7126 cannot

enable clock stretching.

In slave mode, the ADuC7124/ADuC7126 can be pro-

grammed to return a NACK. This allows the validiation of

checksum bytes at the end of I²C transfers.

The ADuC7124/ADuC7126 also support 10-bit addressing

mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one

10-bit address is supported in slave mode and is stored in the

I2CxID0 and I2CxID1 registers. The 10-bit address is derived as

follows:

I2CxID0[0] is the read/write bit and is not part of the I²C

address.

•

Bus arbitration in master mode is supported.

Internal and external loopback modes are supported for

I²C hardware testing in loopback mode.

I2CxID0[7:1] = Address Bits[6:0].

I2CxID1[2:0] = Address Bits[9:7].

I2CxID1[7:3] must be set to 11110b.

•

The transmit and receive circuits in both master and slave

mode contain 2-byte FIFOs. Status bits are available to the

user to control these FIFOs.

Rev. D | Page 72 of 110

Data Sheet

ADuC7124/ADuC7126

Master Mode

I²C Master Registers

I²C Master Control Register

In master mode, the I2CxADR0 register is programmed with

the I²C address of the device.

Name:

I2C0MCON, I2C1MCON

In 7-bit address mode, I2CxADR0[7:1] are set to the device

address. I2CxADR0[0] is the read/write bit.

Address:

0xFFFF0800, 0xFFFF0900

Default

Value:

0x0000, 0x0000

Read/write

In 10-bit address mode, the 10-bit address is created as follows:

I2CxADR0[7:3] must be set to 11110b.

I2CxADR0[2:1] = Address Bits[9:8].

I2CxADR1[7:0] = Address Bits[7:0].

I2CxADR0[0] is the read/write bit.

I²C Registers

Access:

Function: This 16-bit MMR configures the I²C peripheral in

master mode.

The I²C peripheral interfaces consists of a number of MMRs.

These are described in the I2C Master Registers section.

Table 102. I2CxMCON MMR Bit Descriptions

Bit

[15:9]

8

Name

Description

Reserved. These bits are reserved and should not be written to.

I²C transmission complete interrupt enable bit.

Set this bit to enable an interrupt on detecting a stop condition on the I²C bus.

I2CMCENI

Clear this bit to clear the interrupt source.

7

6

5

4

I2CNACKENI I²C no acknowledge (NACK) received interrupt enable bit.

Set this bit to enable interrupts when the I²C master receives a NACK.

Clear this bit to clear the interrupt source.

I2CALENI

I2CMTENI

I2CMRENI

I²C arbitration lost interrupt enable bit.

Set this bit to enable interrupts when the I²C master is unable to gain control of the I²C bus.

Clear this bit to clear the interrupt source.

I²C transmit interrupt enable bit.

Set this bit to enable interrupts when the I²C master has transmitted a byte.

Clear this bit to clear the interrupt source.

I²C receive interrupt enable bit.

Set this bit to enable interrupts when the I²C master receives data.

Cleared by user to disable interrupts when the I²C master is receiving data.

Reserved. A value of 0 should be written to this bit.

I²C internal loopback enable.

3

2

RESERVED

I2CILEN

Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their

respective input signals.

Cleared by the user to disable loopback mode.

I²C master backoff disable bit.

Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start

condition.

Clear this bit to wait until the I²C bus becomes free.

I²C master enable bit.

1

0

I2CBD

I2CMEN

Set by the user to enable I²C master mode.

Clear this bit to disable I²C master mode.

Rev. D | Page 73 of 110

ADuC7124/ADuC7126

Data Sheet

I²C Master Status Register

Name:

I2C0MSTA, I2C1MSTA

Address:

Default Value:

Access:

0xFFFF0804, 0xFFFF0904

0x0000, 0x0000

Read only

Function:

This 16-bit MMR is the I²C status register in master mode.

Table 103. I2CxMSTA MMR Bit Descriptions

Bit

Name

Description

[15:11]

10

Reserved.

I²C bus busy status bit.

I2CBBUSY

This bit is set to 1 when a start condition is detected on the I²C bus.

This bit is cleared when a stop condition is detected on the bus.

Master Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I²C transmission complete status bit.

9

8

I2CMRxFO

I2CMTC

This bit is set to 1 when a transmission is complete between the master and the slave it was

communicating with.

If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

Clear this bit to clear the interrupt source.

7

I2CMNA

I²C master NACK data bit.

This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer.

If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

6

5

I2CMBUSY

I2CAL

I²C master busy status bit.

Set to 1 when the master is busy processing a transaction.

Cleared if the master is ready or if another master device has control of the bus.

I²C arbitration lost status bit.

This bit is set to 1 when the I²C master is unable to gain control of the I²C bus.

If the I2CALENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

4

I2CMNA

I²C master NACK address bit.

This bit is set to 1 when a NACK condition is received by the master in response to an address.

If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I²C master receive request bit.

This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCON is set, an interrupt is

generated.

This bit is cleared in all other conditions.

I²C master transmit request bit.

This bit goes high if the Tx FIFO is empty or contains only one byte and the master has transmitted an

address + write. If the I2CMTENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.

This bit is cleared in all other conditions.

I²C master Tx FIFO status bits.

00 = I²C master Tx FIFO empty.

01 = one byte in master Tx FIFO.

10 = one byte in master Tx FIFO.

11 = I²C master Tx FIFO full.

3

I2CMRXQ

I2CMTXQ

I2CMTFSTA

2

[1:0]

Rev. D | Page 74 of 110

Data Sheet

ADuC7124/ADuC7126

I²C Master Receive Register

I²C Master Current Read Count Register

Name:

I2C0MRX, I2C1MRX

Name:

I2C0MCNT1, I2C1MCNT1

Address:

0xFFFF0808, 0xFFFF0908

Address:

0xFFFF0814, 0xFFFF0914

Default Value: 0x00

Default Value: 0x00, 0x00

Access:

Read only

Access:

Read only

Function:

This 8-bit MMR is the I²C master receive

register.

Function:

This 8-bit MMR holds the number of bytes

received so far during a read sequence with a

slave device.

I²C Master Transmit Register

I²C Address 0 Register

Name:

I2C0MTX, I2C1MTX

Name:

I2C0ADR0, I2C1ADR0

Address:

0xFFFF080C 0xFFFF090C

Address:

0xFFFF0818, 0xFFFF0918

Default Value: 0x00, 0x00

Default Value: 0x00

Access:

Read/write

Access:

Read/write

Function:

This 8-bit MMR is the I²C master transmit

register.

Function:

This 8-bit MMR holds the 7-bit slave address +

the read/write bit when the master begins

communicating with a slave.

I²C Master Read Count Register

Name:

I2C0MCNT0, I2C1MCNT0

Table 105. I2CxADR0 MMR in 7-Bit Address Mode

Bit Name Description

Address:

0xFFFF0810, 0xFFFF0910

[7:1] I2CADR These bits contain the 7-bit address of the

required slave device.

Default Value: 0x0000, 0x0000

Access:

Read/write

0

R/W

Bit 0 is the read/write bit.

When this bit = 1, a read sequence is

requested.

When this bit = 0, a write sequence is

requested.

Function:

This 16-bit MMR holds the required number

of bytes when the master begins a read

sequence from a slave device.

Table 106. I2CxADR0 MMR in 10-Bit Address Mode

Table 104. I2CxMCNT0 MMR Bit Descriptions

Bit

Name

Description

Bit

[15:9]

8

Name

Description

[7:3]

These bits must be set to [11110b] in 10-bit

address mode.

Reserved.

I2CRECNT Set this bit if more than 256 bytes are

required from the slave.

[2:1] I2CMADR These bits contain ADDR[9:8] in 10-bit

addressing mode.

Clear this bit when reading 256 bytes or

less.

0

R/W

Read/write bit.

When this bit = 1, a read sequence is

requested.

When this bit = 0, a write sequence is

requested.

[7:0]

I2CRCNT

These eight bits hold the number of bytes

required during a slave read sequence,

minus 1. If only a single byte is required,

these bits should be set to 0.

Rev. D | Page 75 of 110

ADuC7124/ADuC7126

Data Sheet

I²C Address 1 Register

Table 108. I2CxDIV MMR

Bit Name Description

[15:8] DIVH These bits control the duration of the high

Name:

I2C0ADR1, I2C1ADR1

Address:

0xFFFF081C, 0xFFFF091C

period of SCL.

[7:0]

DIVL

These bits control the duration of the low

period of SCL.

Default Value: 0x00

Access:

Read/write

I²C Slave Registers

I²C Slave Control Register

Function:

This 8-bit MMR is used in 10-bit addressing

mode only. This register contains the least

significant byte of the address.

Name:

I2C0SCON, I2C1SCON

Address:

0xFFFF0828, 0xFFFF0928

Table 107. I2CxADR1 MMR in 10-Bit Address Mode

Bit Name Description

Default Value: 0x0000

[7:0] I2CLADR These bits contain ADDR[7:0] in 10-bit

addressing mode.

Access:

Read/write

Function:

This 16-bit MMR configures the I²C

peripheral in slave mode.

I²C Master Clock Control Register

Name:

I2C0DIV, I2C1DIV

Address:

0xFFFF0824, 0xFFFF0924

Default Value: 0x1F1F

Access:

Read/write

Function:

This MMR controls the frequency of the I²C

clock generated by the master on to the SCL

pin. For further details, see the I²C section.

Table 109. I2CxSCON MMR Bit Descriptions

Bit

Name

Description

[15:11]

10

Reserved.

I2CSTXENI

Slave transmit interrupt enable bit.

Set this bit to enable an interrupt after a slave transmits a byte.

Clear this interrupt source.

9

8

7

I2CSRXENI

I2CSSENI

Slave receive interrupt enable bit.

Set this bit to enable an interrupt after the slave receives data.

Clear this interrupt source.

I²C stop condition detected interrupt enable bit.

Set this bit to enable an interrupt on detecting a stop condition on the I²C bus.

Clear this interrupt source.

I²C NACK enable bit.

I2CNACKEN

Set this bit to NACK the next byte in the transmission sequence.

Clear this bit to let the hardware control the ACK/NACK sequence.

Reserved. A value of 0 should be written to this bit.

I²C early transmit interrupt enable bit.

6

5

RESERVED

I2CSETEN

Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit

transmission.

Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit

transmission.

4

I2CGCCLR

I²C general call status and ID clear bit.

Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register.

Clear this bit at all other times.

Rev. D | Page 76 of 110

Data Sheet

ADuC7124/ADuC7126

Bit

Name

I2CHGCEN

Description

I²C hardware general call enable.

3

When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device

checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a

hardware general call. This is used if a device needs urgent attention from a master device without knowing

which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7124/

ADuC7126 watch for these addresses. The device that requires attention embeds its own address into the

message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.

The LSB of the I2CxALT register should always be written to 1, as per the I²C January 2000 bus specification.

Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.

Clear this bit to disable recognition of hardware general call commands.

2

I2CGCEN

I²C general call enable.

Set this bit to enable the slave device to acknowledge an I²C general call, Address 0x00 (write). The device then

recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hard-

ware) as the data byte, the I²C interface resets as per the I²C January 2000 bus specification. This command can

be used to reset an entire I²C system. If it receives a 0x04 (write programmable part of the slave address by

hardware) as the data byte, the general call interrupt status bit sets on any general call.

The user must take corrective action by reprogramming the device address.

Set this bit to allow the slave ACK I²C general call commands.

Clear this bit to disable recognition of general call commands.

I²C 10-bit address mode.

Set to 1 to enable 10-bit address mode.

Clear to 0 to enable normal address mode.

I²C slave enable bit.

1

0

ADR10EN

I2CSEN

Set by the user to enable I²C slave mode.

Clear this bit to disable I²C slave mode.

I²C Slave Status Registers

Name:

I2C0SSTA, I2C1SSTA

Address:

Default Value:

Access:

0xFFFF082C, 0xFFFF092C

0x0000, 0x0000

Read only

Function:

This 16-bit MMR is the I²C status register in slave mode.

Table 110. I2CxSSTA MMR Bit Descriptions

Bit

15

14

Name

Description

Reserved.

I2CSTA

This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is

received, or general calls are enabled and a general call code of (0x00) is received.

This bit is cleared on receiving a stop condition.

13

I2CREPS

This bit is set to 1 if a repeated start condition is detected.

This bit is cleared on receiving a stop condition. A read of the I2CxSSTA register also clears this bit.

[12:11]

I2CID[1:0]

I²C address matching register. These bits indicate which I2CxIDx register matches the received address.

[00] = received address matches I2CxID0.

[01] = received address matches I2CxID1.

[10] = received address matches I2CxID2.

[11] = received address matches I2CxID3.

10

I2CSS

I²C stop condition after start detected bit.

This bit is set to 1 when a stop condition is detected after a previous start and matching address.

When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.

This bit is cleared by reading this register.

Rev. D | Page 77 of 110

ADuC7124/ADuC7126

Data Sheet

Bit

Name

I2CGCID[1:0] I²C general call ID bits.

[00] = no general call received.

Description

[9:8]

[01] = general call reset and program address.

[10] = general program address.

[11] = general call matching alternative ID.

Note that these bits are not cleared by a general call reset command.

Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON.

7

I2CGC

I²C general call status bit.

This bit is set to 1 if the slave receives a general call command of any type.

If the command received is a reset command, then all registers return to their default states.

If the command received is a hardware general call, the Rx FIFO holds the second byte of the command

and this can be compared with the I2CxALT register.

Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON.

I²C slave busy status bit.

Set to 1 when the slave receives a start condition.

Cleared by hardware if the received address does not match any of the I2CxIDx registers, the slave device

receives a stop condition, or a repeated start address does not match any of the I2CxIDx registers.

I²C slave NACK data bit.

6

5

I2CSBUSY

I2CSNA

This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if a NACK was

returned because there was no data in the Tx FIFO or the I2CNACKEN bit was set in the I2CxSCON register.

This bit is cleared in all other conditions.

4

3

I2CSRxFO

I2CSRXQ

Slave Rx FIFO overflow.

This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.

This bit is cleared in all other conditions.

I²C slave receive request bit.

This bit is set to 1 when the slave Rx FIFO is not empty.

This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set.

The Rx FIFO must be read or flushed to clear this bit.

I²C slave transmit request bit.

2

I2CSTXQ

This bit is set to 1 when the slave receives a matching address followed by a read.

If the I2CSETEN bit in I2CxSCON = 0, this bit goes high just after the negative edge of SCL during the read

bit transmission.

If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the read

bit transmission.

This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set.

This bit is cleared in all other conditions.

I²C slave FIFO underflow status bit.

This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at

the rising edge of SCL during the read bit.

This bit is cleared in all other conditions.

I²C slave early transmit FIFO status bit.

1

0

I2CSTFE

I2CETSTA

If the I2CSETEN bit in I2CxSCON = 0, this bit goes high if the slave Tx FIFO is empty.

If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the write

bit transmission.

This bit asserts once only for a transfer.

This bit is cleared after being read.

Rev. D | Page 78 of 110

Data Sheet

ADuC7124/ADuC7126

I²C Slave Receive Registers

I²C Common Registers

I²C FIFO Status Register

Name:

I2C0SRX, I2C1SRX

Name:

I2C0FSTA, I2C1FSTA

Address:

0xFFFF0830, 0xFFFF0930

Address:

0xFFFF084C, 0xFFFF094C

Default Value: 0x00

Default Value: 0x0000

Access:

Read

This 8-bit MMR is the I²C slave receive register.

Access:

Read/write

Function:

These 16-bit MMRs contain the status of the

Rx/Tx FIFOs in both master and slave modes.

I²C Slave Transmit Registers

Name:

I2C0STX, I2C1STX

Table 111. I2CxFSTA MMR Bit Descriptions

Address:

0xFFFF0834, 0xFFFF0934

Bit

Name

Description

Default Value: 0x00

[15:10]

9

Reserved.

I2CFMTX

I2CFSTX

Set this bit to 1 to flush the master Tx

FIFO.

Access:

Write

8

Set this bit to 1 to flush the slave Tx FIFO.

I2CMRXSTA I²C master receive FIFO status bits.

Function:

This 8-bit MMR is the I²C slave transmit register.

[7:6]

I²C Hardware General Call Recognition Registers

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = one byte in FIFO.

Name:

I2C0ALT, I2C1ALT

[11] = FIFO full.

I2CMTXSTA I²C master transmit FIFO status bits.

Address:

0xFFFF0838, 0xFFFF0938

[5:4]

[3:2]

[1:0]

Default Value: 0x00

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = one byte in FIFO.

[11] = FIFO full.

I²C slave receive FIFO status bits.

Access:

Read/write

Function:

This 8-bit MMR is used with hardware general

calls when I2CxSCON Bit 3 is set to 1. This

register is used in cases where a master is unable

to generate an address for a slave, and instead, the

slave must generate the address for the master.

I2CSRXSTA

I2CSTXSTA

[00] = FIFO empty.

[01] = byte written to FIFO.

[10] = one byte in FIFO.

[11] = FIFO full.

I²C Slave Device ID Registers

I²C slave transmit FIFO status bits.

[00] = FIFO empty.

Name:

I2C0IDx, I2C1IDx

[01] = byte written to FIFO.

[10] = one byte in FIFO.

[11] = FIFO full.

Addresses:

0xFFFF093C = I2C1ID0

0xFFFF083C = I2C0ID0

0xFFFF0940 = I2C1ID1

0xFFFF0840 = I2C0ID1

0xFFFF0944 = I2C1ID2

0xFFFF0844 = I2C0ID2

0xFFFF0948 = I2C1ID3

0xFFFF0848 = I2C0ID3

Default Value: 0x00

Access:

Read/write

Function:

These 8-bit MMRs are programmed with I²C

bus IDs of the slave. See the I2C Bus Addresses

section for further details.

Rev. D | Page 79 of 110

ADuC7124/ADuC7126

Data Sheet

PWM GENERAL OVERVIEW

In all modes, the PWMxCOMx MMRs control the point at

which the PWM outputs change state. An example of the first pair

of PWM outputs (PWM0 and PWM1) is shown in Figure 49.

The ADuC7124/ADuC7126 integrate a 6-channel PWM

interface (PWM0 to PWM5). The PWM outputs can be

configured to drive an H-bridge or can be used as standard PWM

outputs. On power-up, the PWM outputs default to H-bridge

mode. This ensures that the motor is turned off by default. In

standard PWM mode, the outputs are arranged as three pairs of

PWM pins. The user has control over the period of each pair of

outputs and over the duty cycle of each individual output.

HIGH SIDE

(PWM0)

LOW SIDE

(PWM1)

Table 112. PWM MMRs

PWM0COM2

Name

Function

PWMCON0

PWM0COM0

PWM control.

Compare Register 0 for PWM Output 0 and

PWM Output 1.

PWM0COM1

PWM0COM0

PWM0COM1

PWM0COM2

PWM0LEN

Compare Register 1 for PWM Output 0 and

PWM Output 1.

Compare Register 2 for PWM Output 0 and

PWM Output 1.

Frequency control for PWM Output 0 and

PWM Output 1.

Compare Register 0 for PWM Output 2 and

PWM Output 3.

Compare Register 1 for PWM Output 2 and

PWM Output 3.

Compare Register 2 for PWM Output 2 and

PWM Output 3.

Frequency control for PWM Output 2 and

PWM Output 3.

Compare Register 0 for PWM Output 4 and

Output 5

PWM0LEN

Figure 49. PWM Timing

The PWM clock is selectable via PWMCON with one of the

following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or

256. The length of a PWM period is defined by PWMxLEN.

PWM1COM0

PWM1COM1

PWM1COM2

PWM1LEN

The PWM waveforms are set by the count value of the 16-bit

timer and the compare registers contents, as shown with the

PWM0 and PWM1 waveforms in Figure 49.

The low-side waveform, PWM1, goes high when the timer

count reaches PWM0LEN, and it goes low when the timer

count reaches the value held in PWM0COM2 or when the

high-side waveform (PWM0) goes low.

PWM2COM0

PWM2COM1

PWM2COM2

PWM2LEN

The high-side waveform, PWM0, goes high when the timer

count reaches the value held in PWM0COM0, and it goes low

when the timer count reaches the value held in PWM0COM1.

Compare Register 1 for PWM Output 4 and

Output 5

Compare Register 2 for PWM Output 4 and

Output 5

Frequency control for PWM Output 4 and

PWM Output 5.

PWMCON1

PWMCLRI

PWM control register

PWM interrupt clear.

Rev. D | Page 80 of 110

Data Sheet

ADuC7124/ADuC7126

Table 113. PWMCON0 MMR Bit Descriptions

Bit

Name

Description

14

SYNC

Enables PWM synchronization.

Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low

transition on the P3.7/PWM_SYNCpin.

Cleared by the user to ignore transitions on the P3.7/PWM_SYNCpin.

Set to 1 by the user to invert PWM5.

Cleared by the user to use PWM5 in normal mode.

Set to 1 by the user to invert PWM3.

Cleared by the user to use PWM3 in normal mode.

Set to 1 by the user to invert PWM1.

Cleared by the user to use PWM1 in normal mode.

13

12

11

10

PWM5INV

PWM3INV

PWM1INV

PWMTRIP

Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P3.6/PWM_TRIPor Pin P0.4/PWM_TRIP

)

is low, the PWMEN bit is cleared and an interrupt is generated.

Cleared by the user to disable the PWMTRIP interrupt.

If HOFF = 0 and HMODE = 1; note that, if not in H-bridge mode, this bit has no effect.

Set to 1 by the user to enable PWM outputs.

9

ENA

Cleared by the user to disable PWM outputs.

If HOFF = 1 and HMODE = 1, see Table 114.

[8:6]

PWMCP[2:0] PWM clock prescaler bits. Sets the UCLK divider.

[000] = UCLK/2.

[001] = UCLK/4.

[010] = UCLK/8.

[011] = UCLK/16.

[100] = UCLK/32.

[101] = UCLK/64.

[110] = UCLK/128.

[111] = UCLK/256.

5

4

POINV

HOFF

Set to 1 by the user to invert all PWM outputs.

Cleared by the user to use PWM outputs as normal.

High side off.

Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low.

Cleared by the user to use the PWM outputs as normal.

Load compare registers.

3

LCOMP

Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of

the PWM timer from 0x00 to 0x01.

Cleared by the user to use the values previously stored in the internal compare registers.

Direction control.

Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low.

Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low.

Enables H-bridge mode.¹

Set to 1 by the user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON.

Cleared by the user to operate the PWMs in standard mode.

Set to 1 by the user to enable all PWM outputs.

2

1

0

DIR

HMODE

PWMEN

Cleared by the user to disable all PWM outputs.

¹In H-bridge mode, HMODE = 1. See Table 114 to determine the PWM outputs.

Rev. D | Page 81 of 110

ADuC7124/ADuC7126

Data Sheet

Table 114. PWM Output Selection, HMODE = 1

Table 116. PWMCON1 MMR Bit Descriptions (Address =

0xFFFF0FB4; Default Value = 0x00)

PWMCON0 MMR¹

PWM Outputs²

ENA HOFF POINV DIR PWM0 PWM1 PWM2

PWM3

Bit

Value Name Description

0

X

1

0

1

0

X

0

1

X

0

1

0

1

0

HS

1

0

LS

1

HS

0

1

0

LS

0

1

7

CSEN

Set to 1 by the user to enable the PWM

to generate a convert start signal.

Cleared by user to disable the PWM

convert start signal.

[3:0]

CSD3

Convert start delay. Delays the convert

start signal by a number of clock

pulses.

HS

LS

¹X = don’t care.

²HS = high side, LS = low side.

CSD2

CSD1

CSD0

On power-up, PWMCON0 defaults to 0x12 (HOFF = 1 and

HMODE = 1). All GPIO pins associated with the PWM are

configured in PWM mode by default (see Table 115).

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Four clock pulses.

Eight clock pulses.

12 clock pulses.

16 clock pulses.

20 clock pulses.

24 clock pulses.

28 clock pulses.

32 clock pulses.

36 clock pulses.

40 clock pulses.

44 clock pulses.

48 clock pulses.

52 clock pulses.

56 clock pulses.

60 clock pulses.

64 clock pulses.

Table 115. Compare Registers

Name

Address

Default Value

0x0000

Access

R/W

PWM0COM0

PWM0COM1

PWM0COM2

PWM1COM0

PWM1COM1

PWM1COM2

PWM2COM0

PWM2COM1

PWM2COM2

0xFFFF0F84

0xFFFF0F88

0xFFFF0F8C

0xFFFF0F94

0xFFFF0F98

0xFFFF0F9C

0xFFFF0FA4

0xFFFF0FA8

0xFFFF0FAC

The PWM trip interrupt can be cleared by writing any value to

the PWMCLRI MMR. Note that, when using the PWM trip

interrupt, users should make sure that the PWM interrupt

has been cleared before exiting the ISR. This prevents

generation of multiple interrupts.

When calculating the time from the convert start delay to the

start of an ADC conversion, the user must take account of

internal delays. The following example shows the case of a delay

of four clocks. One additional clock is required to pass the

convert start signal to the ADC logic. Once the ADC logic

receives the convert start signal, an ADC conversion begins on

the next ADC clock edge (see Figure 50).

PWM Convert Start Control

The PWM can be configured to generate an ADC convert start

signal after the active low side signal goes high. There is a

programmable delay between the time that the low-side signal

goes high and the convert start signal is generated.

This is controlled via the PWMCON1 MMR. If the delay

selected is higher than the width of the PWM pulse, the

interrupt remains low.

UCLK

LOW SIDE

COUNT

PWM SIGNAL

TO CONVST

SIGNAL PASSED

TO ADC LOGIC

Figure 50. ADC Conversion

Rev. D | Page 82 of 110

Data Sheet

ADuC7124/ADuC7126

PLA MMRs Interface

The PLA peripheral interface consists of the 22 MMRs.

PROGRAMMABLE LOGIC ARRAY (PLA)

Every ADuC7124/ADuC7126 integrates a fully programmable

logic array (PLA) that consists of two independent but

interconnected PLA blocks. Each block consists of eight PLA

elements, giving each part a total of 16 PLA elements.

Table 118. PLAELMx Registers

Name

Address

Default Value

0x0000

Access

R/W

PLAELM0

PLAELM1

PLAELM2

PLAELM3

PLAELM4

PLAELM5

PLAELM6

PLAELM7

PLAELM8

PLAELM9

PLAELM10

PLAELM11

PLAELM12

PLAELM13

PLAELM14

PLAELM15

0xFFFF0B00

0xFFFF0B04

0xFFFF0B08

0xFFFF0B0C

0xFFFF0B10

0xFFFF0B14

0xFFFF0B18

0xFFFF0B1C

0xFFFF0B20

0xFFFF0B24

0xFFFF0B28

0xFFFF0B2C

0xFFFF0B30

0xFFFF0B34

0xFFFF0B38

0xFFFF0B3C

Each PLA element contains a two-input look up table that can

be configured to generate any logic output function based on

two inputs and a flip-flop. This is represented in Figure 51.

0

4

A

2

LOOK-UP

TABLE

B

3

1

Figure 51. PLA Element

In total, 40 GPIO pins are available on the ADuC7124/ADuC7126

for the PLA. These include 16 input pins and 16 output pins that

must be configured in the GPxCON register as PLA pins before

using the PLA. Note that the comparator output is also included

as one of the 16 input pins.

The PLAELMx are Element 0 to Element 15 control registers.

They configure the input and output mux of each element,

select the function in the look up table, and bypass/use the flip-

flop (see Table 119 and Table 122).

The PLA is configured via a set of user MMRs. The output(s) of

the PLA can be routed to the internal interrupt system, to the

CONV_STARTsignal of the ADC, to an MMR, or to any of the 16

PLA output pins.

Table 119. PLAELMx MMR Bit Descriptions

Bit

Value Description

[31:11]

[10:9]

[8:7]

6

Reserved.

Mux 0 control (see Table 122).

Mux 1 control (see Table 122).

The two blocks can be interconnected as follows:

Mux 2 control.



Output of Element 15 (Block 1) can be fed back to Input 0 of

Mux 0 of Element 0 (Block 0).

Set by the user to select the output of Mux 0. Cleared

by the user to select the bit value from PLADIN.

5

Mux 3 control.

Set by the user to select the input pin of the particular

element.



Output of Element 7 (Block 0) can be fed back to Input 0 of

Mux 0 of Element 8 (Block 1).

Cleared by the user to select the output of Mux 1.

Table 117. Element Input/Output¹

[4:1]

Look-up table control.

PLA Block 0

PLA Block 1

Input

P3.0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0.

NOR.

Element Input

Output

P1.7

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

Element

Output

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

B AND NOT A.

NOT A.

A AND NOT B.

NOT B.

EXOR.

0

1

2

3

4

5

6

7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P0.0

8

9

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

10

11

12

13

14

15

NAND.

AND.

EXNOR.

B.

NOT A OR B.

A.

¹Not all pins in this table are connected to external pins. However, they may

be routed internally via the PLA. See Table 122 for further details.

A OR NOT B.

OR.

1.

0

Mux 4 control.

Set by the user to bypass the flip-flop.

Cleared by the user to select the flip-flop (cleared by

default).

Rev. D | Page 83 of 110

ADuC7124/ADuC7126

Data Sheet

PLACLK Register

PLAIRQ Register

Name:

PLACLK

0xFFFF0B40

0x00

Name:

PLAIRQ

Address:

Default Value:

Access:

Address:

0xFFFF0B44

0x00000000

Read/write

Default Value:

Access:

Read/write

PLACLK is the clock selection for the flip-flops of Block 0 and

Block 1. Note that the maximum frequency when using the

GPIO pins as the clock input for the PLA blocks is 41.78 MHz.

PLAIRQ enables IRQ0 and/or IRQ1 and selects the source

of the IRQ.

Table 121. PLAIRQ MMR Bit Descriptions

Table 120. PLACLK MMR Bit Descriptions

Bit

Value

Description

Bit

Value

Description

[15:13]

12

Reserved.

7

Reserved.

PLA IRQ1 enable bit.

Set by the user to enable IRQ1 output from

PLA.

Cleared by the user to disable IRQ1 output

from PLA.

[6:4]

Block 1 clock source selection.

GPIO clock on P0.5.

GPIO clock on P0.0.

GPIO clock on P0.7.

HCLK.

000

001

010

011

100

101

110

111

[11:8]

PLA IRQ1 source.

PLA Element 0.

PLA Element 1.

PLA Element 15.

Reserved.

0000

0001

1111

OCLK (32.768 kHz).

Timer1 overflow.

UCLK.

[7:5]

4

Internal 32,768 oscillator.

Reserved.

PLA IRQ0 enable bit.

Set by the user to enable IRQ0 output from

PLA.

Cleared by the user to disable IRQ0 output

from PLA.

3

[2:0]

Block 0 clock source selection.

GPIO clock on P0.5.

GPIO clock on P0.0.

GPIO clock on P0.7.

HCLK.

000

001

010

011

100

101

Other

[3:0]

PLA IRQ0 source.

PLA Element 0.

PLA Element 1.

PLA Element 15.

0000

0001

1111

OCLK (32.768 kHz).

Timer1 overflow.

Reserved.

Table 122. Feedback Configuration

Bit

Value

PLAELM0

Element 15

Element 2

Element 4

Element 6

Element 1

Element 3

Element 5

Element 7

PLAELM1 to PLAELM7

Element 0

Element 2

Element 4

Element 6

PLAELM8

Element 7

Element 10

Element 12

Element 14

Element 9

Element 11

Element 13

Element 15

PLAELM9 to PLAELM15

Element 8

Element 10

Element 12

Element 14

Element 9

Element 11

Element 13

Element 15

[10:9]

00

01

10

11

[8:7]

00

01

10

11

Element 1

Element 3

Element 5

Element 7

Rev. D | Page 84 of 110

Data Sheet

ADuC7124/ADuC7126

PLAADC Register

Table 124. PLADIN MMR Bit Descriptions

Name:

PLAADC

Bit

Description

[31:16]

[15:0]

Reserved.

Address:

0xFFFF0B48

0x00000000

Read/write

Input bit to Element 15 to Element 0.

Default Value:

Access:

PLADOUT Register

Name:

PLADOUT

Address:

Default Value:

Access:

0xFFFF0B50

0x00000000

Read only

PLAADC is the PLA source for the ADC start conversion signal.

Table 123. PLAADC MMR Bit Descriptions

Bit

[31:5]

4

Value Description

Reserved.

PLADOUT is a data output MMR for PLA. This register is

always updated.

ADC start conversion enable bit.

Set by the user to enable ADC start

conversion from PLA.

Table 125. PLADOUT MMR Bit Descriptions

Cleared by the user to disable ADC start

conversion from PLA.

Bit

Description

[3:0]

ADC start conversion source.

PLA Element 0.

[31:16]

[15:0]

Reserved.

0000

0001

1111

Output bit from Element 15 to Element 0.

PLA Element 1.

PLALCK Register

PLA Element 15.

Name:

PLALCK

0xFFFF0B54

0x00

PLADIN Register

Address:

Name:

PLADIN

Default Value:

Access:

Address:

0xFFFF0B4C

0x00000000

Read/write

Write only

Default Value:

Access:

PLALCK is a PLA lock option. Bit 0 is written only once. When

set, it does not allow modification of any of the PLA MMRs,

except PLADIN. A PLA tool is provided in the development

system to easily configure the PLA.

PLADIN is a data input MMR for PLA.

Rev. D | Page 85 of 110

ADuC7124/ADuC7126

Data Sheet

PROCESSOR REFERENCE PERIPHERALS

INTERRUPT SYSTEM

Bit Description

21 PLA IRQ0

Comments

PLA Block 0 IRQ bit.

There are 25 interrupt sources on the ADuC7124/ADuC7126

that are controlled by the interrupt controller. All interrupts

are generated from the on-chip peripherals, except for the

software interrupt (SWI), which is programmable by the user.

The ARM7TDMI CPU core recognizes interrupts as one of

two types: a normal interrupt request (IRQ) and a fast interrupt

request (FIQ). All the interrupts can be masked separately.

22 XIRQ2 (GPIO IRQ2 )

23 XIRQ3 (GPIO IRQ3)

24 PLA IRQ1

External Interrupt 2.

External Interrupt 3.

PLA Block 1 IRQ bit.

25 PWM

PWM trip interrupt source bit.

IRQ

The IRQ is the exception signal to enter the IRQ mode of the

processor. It services general-purpose interrupt handling of

internal and external events.

The control and configuration of the interrupt system is

managed through a number of interrupt-related registers. The

bits in each IRQ and FIQ register represent the same interrupt

source as described in Table 126.

All 32 bits are logically OR’ed to create a single IRQ signal to the

ARM7TDMI core. Descriptions of the four 32-bit registers

dedicated to IRQ follow.

The ADuC7124/ADuC7126 contain a vectored interrupt control-

ler (VIC) that supports nested interrupts up to eight levels. The

VIC also allows the programmer to assign priority levels to all

interrupt sources. Interrupt nesting must be enabled by setting

the ENIRQN bit in the IRQCONN register. A number of extra

MMRs are used when the full-vectored interrupt controller is

enabled.

IRQSTA Register

IRQSTA is a read-only register that provides the current-enabled

IRQ source status (effectively a logic AND of the IRQSIG and

IRQEN bits). When set to 1, that source generates an active IRQ

request to the ARM7TDMI core. There is no priority encoder

or interrupt vector generation. This function is implemented in

software in a common interrupt handler routine.

IRQSTA/FIQSTA should be saved immediately upon entering

the interrupt service routine (ISR) to ensure that all valid

interrupt sources are serviced.

IRQSTA Register

Name:

IRQSTA

Table 126. IRQ/FIQ MMRs Bit Descriptions

Address:

0xFFFF0000

0x00000000

Read only

Bit Description

Comments

0

All interrupts OR’ed

This bit is set if any FIQ is active.

Default Value:

Access:

(FIQ only)

1

Software interrupt

User programmable interrupt

source.

IRQSIG Register

2

3

4

Timer0

Timer1

Timer2 or wake-up

timer

Timer3 or watchdog

timer

Flash Control 0

General-Purpose Timer 0.

General-Purpose Timer 1.

General-Purpose Timer 2 or

wake-up timer.

General-Purpose Timer 3 or

watchdog timer.

Flash controller for Block 0

interrupt.

IRQSIG reflects the status of the various IRQ sources. If a periph-

eral generates an IRQ signal, the corresponding bit in the

IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear

when the interrupt in the particular peripheral is cleared. All

IRQ sources can be masked in the IRQEN MMR. IRQSIG is

read only. This register should not be used in an interrupt

service routine for determining the source of an IRQ exception;

IRQSTA should only be used for this purpose.

5

6

7

Flash Control 1

Flash controller for Block 1

interrupt.

8

9

ADC

UART0

ADC interrupt source bit.

UART0 interrupt source bit.

UART1 interrupt source bit.

PLL lock bit.

I²C master interrupt source bit.

I²C slave interrupt source bit.

I²C master interrupt source bit.

I²C slave interrupt source bit.

SPI interrupt source bit.

External Interrupt 0.

IRQSIG Register

Name:

IRQSIG

10 UART1

11 PLL lock

Address:

0xFFFF0004

12 I2C0 master IRQ

13 I2C0 slave IRQ

14 I2C1 master IRQ

15 I2C1 slave IRQ

16 SPI

17 XIRQ0 (GPIO IRQ0 )

18 Comparator

19 PSM

Default Value: 0x00000000

Access: Read only

Voltage comparator source bit.

Power supply monitor.

20 XIRQ1 (GPIO IRQ1)

External Interrupt 1.

Rev. D | Page 86 of 110

Data Sheet

ADuC7124/ADuC7126

IRQEN Register

Likewise, a bit set to 1 in IRQEN clears, as a side effect, the

same bit in FIQEN. An interrupt source can be disabled in both

the IRQEN and FIQEN masks.

IRQEN provides the value of the current enable mask. When a

bit is set to 1, the corresponding source request is enabled to

create an IRQ exception. When a bit is set to 0, the correspond-

ing source request is disabled or masked, which does not create

an IRQ exception. The IRQEN register cannot be used to

disable an interrupt.

FIQSIG

FIQSIG reflects the status of the different FIQ sources. If a

peripheral generates an FIQ signal, the corresponding bit in

the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are

cleared when the interrupt in the particular peripheral is

cleared. All FIQ sources can be masked in the FIQEN MMR.

FIQSIG is read only.

IRQEN Register

Name:

IRQEN

Address:

0xFFFF0008

0x00000000

Read/write

FIQSIG Register

Default Value:

Access:

Name:

FIQSIG

Address:

Default Value:

Access:

0xFFFF0104

0x00000000

Read only

IRQCLR Register

IRQCLR is a write-only register that allows the IRQEN register

to clear to mask an interrupt source. Each bit that is set to 1

clears the corresponding bit in the IRQEN register without

affecting the remaining bits. The pair of registers, IRQEN and

IRQCLR, allow independent manipulation of the enable mask

without requiring an atomic read-modify-write.

FIQEN

FIQEN provides the value of the current enable mask. When a

bit is set to 1, the corresponding source request is enabled to

create an FIQ exception. When a bit is set to 0, the correspond-

ing source request is disabled or masked, which does not create

an FIQ exception. The FIQEN register cannot be used to disable an

interrupt.

This register should be used to disable an interrupt source only

during the following conditions:

•

In the interrupt sources interrupt service routine.

When the peripheral is temporarily disabled by its own

control register.

FIQEN Register

Name:

FIQEN

This register should not be used to disable an IRQ source if that

IRQ source has an interrupt pending or may have an interrupt

pending.

Address:

0xFFFF0108

Default Value: 0x00000000

IRQCLR Register

Access:

Read/write

Name:

IRQCLR

FIQCLR

Address:

0xFFFF000C

FIQCLR is a write-only register that allows the FIQEN register

to clear to mask an interrupt source. Each bit that is set to 1

clears the corresponding bit in the FIQEN register without

affecting the remaining bits. The pair of registers, FIQEN and

FIQCLR, allows independent manipulation of the enable mask

without requiring an atomic read-modify-write.

Default Value: 0x00000000

Access: Write only

FAST INTERRUPT REQUEST (FIQ)

The fast interrupt request (FIQ) is the exception signal to enter

the FIQ mode of the processor. It is provided to service data

transfer or communication channel tasks with low latency. The

FIQ interface is identical to the IRQ interface and provides the

second level interrupt (highest priority). Four 32-bit registers

are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.

This register should be used to disable an interrupt source only

during the following conditions:

•

In the interrupt sources interrupt service routine.

The peripheral is temporarily disabled by its own control

register.

Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ

signal to the core and to Bit 0 of both the FIQ and IRQ registers

(FIQ source).

This register should not be used to disable an IRQ source if that

IRQ source has an interrupt pending or may have an interrupt

pending.

The logic for FIQEN and FIQCLR does not allow an interrupt

source to be enabled in both IRQ and FIQ masks. A bit set to 1

in FIQEN clears, as a side effect, the same bit in IRQEN.

Rev. D | Page 87 of 110

ADuC7124/ADuC7126

Data Sheet

PROGRAMMABLE PRIORITY

PER INTERRUT

(IRQP0/IRQP1/IRQP2/IRQP3)

FIQCLR Register

Name:

FIQCLR

Address:

Default Value:

Access:

0xFFFF010C

0x00000000

Write only

IRQ_SOURCE

FIQ_SOURCE

INTERNAL

ARBITER

LOGIC

POINTER

FUNCTION

(IRQVEC)

INTERRUPT VECTOR

FIQSTA

FIQSTA is a read-only register that provides the current enabled

FIQ source status (effectively a logic AND of the FIQSIG and

FIQEN bits). When set to 1, that source generates an active FIQ

request to the ARM7TDMI core. There is no priority encoder

or interrupt vector generation. This function is implemented in

software in a common interrupt handler routine.

BITS[31:23]

UNUSED

BITS[22:7]

(IRQBASE)

BITS[6:2]

HIGHEST

PRIORITY

ACTIVE IRQ

BITS[1:0]

LSBs

Figure 52. Interrupt Structure

VECTORED INTERRUPT CONTROLLER (VIC)

The ADuC7124/ADuC7126 incorporate an enhanced interrupt

control system or (vectored interrupt controller). The vectored

interrupt controller for IRQ interrupt sources is enabled by set-

ting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN

enables the vectored interrupt controller for the FIQ interrupt

sources. The vectored interrupt controller provides the following

enhancements to the standard IRQ/FIQ interrupts:

FIQSTA Register

Name:

FIQSTA

Address:

0xFFFF0100

Default Value: 0x00000000

Access: Read only



Vectored interrupts—allows a user to define separate

interrupt service routine addresses for every interrupt

source. This is achieved by using the IRQBASE and

IRQVEC registers.

IRQ/FIQ interrupts—can be nested up to eight levels

depending on the priority settings. An FIQ still has a

higher priority than an IRQ. Therefore, if the VIC is

enabled for both the FIQ and IRQ and prioritization is

maximized, it is possible to have 16 separate interrupt

levels.

Programmed Interrupts

Because the programmed interrupts are not maskable, they are

controlled by another register (SWICFG) that writes into the

IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG

registers at the same time.



The 32-bit register dedicated to software interrupt is SWICFG

(described in Table 127). This MMR allows control of a pro-

grammed source interrupt.



Programmable interrupt priorities—using the IRQP0 to

IRQP3 registers, an interrupt source can be assigned an

interrupt priority level value between 0 and 7.

Table 127. SWICFG MMR Bit Descriptions

Bit

[31:3]

2

Description

Reserved.

Programmed interrupt FIQ. Setting/clearing this bit

corresponds to setting/clearing Bit 1 of FIQSTA and

FIQSIG.

VIC MMRs

IRQBASE Register

1

Programmed interrupt IRQ. Setting/clearing this bit

corresponds to setting/clearing Bit 1 of IRQSTA and

IRQSIG.

The vector base register, IRQBASE, is used to point to the start

address of memory used to store 32 pointer addresses. These

pointer addresses are the addresses of the individual interrupt

service routines.

0

Reserved.

Any interrupt signal must be active for at least the minimum

interrupt latency time to be detected by the interrupt controller

and to be detected by the user in the IRQSTA/FIQSTA register.

Name:

IRQBASE

Address:

0xFFFF0014

Default Value: 0x00000000

Access: Read/write

Table 128. IRQBASE MMR Bit Descriptions

Bit

[31:16] Read only

[15:0] R/W

Type

Initial Value

Reserved

0

Description

Always read as 0.

Vector base address.

Rev. D | Page 88 of 110

Data Sheet

ADuC7124/ADuC7126

IRQVEC Register

Bit

Name

Description

[18:16] T2PI

A priority level of 0 to 7 can be set for

Timer2.

The IRQ interrupt vector register, IRQVEC points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

15

Reserved.

[14:12] T1PI

A priority level of 0 to 7 can be set for

Timer1.

11

Reserved.

Name:

IRQVEC

[10:8]

T0PI

A priority level of 0 to 7 can be set for

Timer0.

Address:

0xFFFF001C

7

Reserved.

[6:4]

SWINTP

A priority level of 0 to 7 can be set for the

software interrupt source.

Default Value: 0x00000000

Access: Read only

[3:0]

Interrupt 0 cannot be prioritized.

IRQP1 Register

Table 129. IRQVEC MMR Bit Descriptions

Name:

IRQP1

Initial

Bit

Type Value Description

Address:

0xFFFF0024

[31:23]

[22:7]

[6:2]

R

0

Always read as 0.

Default Value: 0x00000000

Access: Read/write

R/W

R

IRQBASE register value.

Highest priority source. This is a

value between 0 and 27 represent-

ing the possible interrupt sources.

For example, if the highest currently

active IRQ is Timer 2, then these bits

are [00100].

Table 131. IRQP1 MMR Bit Descriptions

Bit

Name

Description

31

Reserved.

[1:0]

Reser

ved

0

Reserved bits.

[30:28] I2C1SPI

A priority level of 0 to 7 can be set for the

I2C1 slave.

Priority Registers

27

Reserved.

[26:24] I2C1MPI A priority level of 0 to 7 can be set for the

I2C1 master.

The IRQ interrupt vector register, IRQVEC points to a memory

address containing a pointer to the interrupt service routine of

the currently active IRQ. This register should only be read when

an IRQ occurs and IRQ interrupt nesting has been enabled by

setting Bit 0 of the IRQCONN register.

23

Reserved.

[22:20] I2C0SPI

A priority level of 0 to 7 can be set for the

I2C0 slave.

19

Reserved.

IRQP0 Register

[18:16] I2C0MPI A priority level of 0 to 7 can be set for the

I²C 0 master.

Name:

IRQP0

15

Reserved.

Address:

0xFFFF0020

[14:12] PLLPI

A priority level of 0 to 7 can be set for the

PLL lock interrupt.

Default Value: 0x00000000

Access: Read/write

11

Reserved.

[10:8]

UART1PI A priority level of 0 to 7 can be set for

UART1.

7

Reserved.

Table 130. IRQP0 MMR Bit Descriptions

[6:4]

UART0PI A priority level of 0 to 7 can be set for

UART0.

Bit

Name

Description

31

Reserved.

5

Reserved.

[30:28] Flash1PI

A priority level of 0 to 7 can be set for the

Flash Block 1 controller interrupt source.

[2:0]

ADCPI

A priority level of 0 to 7 can be set for the

ADC interrupt source.

27

Reserved.

[26:24] Flash0PI

A priority level of 0 to 7 can be set for the

Flash Block 0 controller interrupt source.

23

Reserved.

[22:20] T3PI

A priority level of 0 to 7 can be set for

Timer 3.

19

Reserved.

Rev. D | Page 89 of 110

ADuC7124/ADuC7126

Data Sheet

interrupt source priority level. In this default state, an FIQ does

have a higher priority than an IRQ.

IRQP2 Register

Name:

IRQP2

Name:

IRQCONN

0xFFFF0030

Address:

0xFFFF0028

Address:

Default Value: 0x00000000

Access: Read/write

Default Value: 0x00000000

Access: Read/write

Table 132. IRQP2 MMR Bit Descriptions

Bit

Name

Description

Table 134. IRQCONN MMR Bit Descriptions

31

Reserved.

Bit

Name

Description

[30:28] IRQ3PI

27

A priority level of 0 to 7 can be set for IRQ3.

Reserved.

31:2

Reserved. These bits are reserved and should

not be written to.

[26:24] IRQ2PI

23

A priority level of 0 to 7 can be set for IRQ2.

Reserved.

1

0

ENFIQN

ENIRQN

Setting this bit to 1 enables nesting of FIQ

interrupts. Clearing this bit means no nesting

or prioritization of FIQs is allowed.

[22:20] PLA0PI

A priority level of 0 to 7 can be set for PLA

IRQ0.

Setting this bit to 1 enables nesting of IRQ

interrupts. Clearing this bit means no nesting

or prioritization of IRQs is allowed.

19

Reserved.

[18:16] IRQ1PI

15

A priority level of 0 to 7 can be set for IRQ1.

Reserved.

IRQSTAN Register

[14:12] PSMPI

A priority level of 0 to 7 can be set for the

power supply monitor interrupt source.

If IRQCONN Bit 0 is asserted and IRQVEC is read, one of the

IRQSTAN[7:0] bits is asserted. The bit that asserts depends on

the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0

asserts, if Priority 1, then Bit 1 asserts, and so on. When a bit is

set in this register, all interrupts of that priority and lower are

blocked.

11

Reserved.

[10:8]

COMPI

A priority level of 0 to 7 can be set for the

comparator.

7

Reserved.

[6:4]

3

IRQ0PI

SPIPI

A priority level of 0 to 7 can be set for IRQ0.

Reserved.

To clear a bit in this register, all bits of a higher priority must be

cleared first. It is only possible to clear one bit at a time. For

example, if this register is set to 0x09, writing 0xFF changes the

register to 0x08, and writing 0xFF a second time changes the

register to 0x00.

[2:0]

A priority level of 0 to 7 can be set for SPI.

IRQP3 Register

Name:

IRQP3

Address:

0xFFFF002C

Name:

IRQSTAN

Default Value: 0x00000000

Access: Read/write

Address:

0xFFFF003C

Default Value: 0x00000000

Access: Read/write

Table 133. IRQP3 MMR Bit Descriptions

Bit

Name

PWMPI

PLA1PI

Description

Table 135. IRQSTAN MMR Bit Descriptions

[31:7]

[6:4]

3

Reserved.

Bit

Name

Description

A priority level of 0 to 7 can be set for PWM.

Reserved.

31:8

Reserved. These bits are reserved and should

not be written to.

[2:0]

A priority level of 0 to 7 can be set for PLA

IRQ1.

7:0

Setting these bits to 1 enables nesting of FIQ

interrupts. Clearing these bits means no

nesting or prioritization of FIQs is allowed.

IRQCONN Register

The IRQCONN register is the IRQ and FIQ control register. It

contains two active bits: the first to enable nesting and prioritiza-

tion of IRQ interrupts and the other to enable nesting and

prioritization of FIQ interrupts.

If these bits are cleared, FIQs and IRQs can still be used, but it is

not possible to nest IRQs or FIQs, nor is it possible to set an

Rev. D | Page 90 of 110

Data Sheet

ADuC7124/ADuC7126

FIQVEC Register

changes the register to 0x08 and writing 0xFF a second time

changes the register to 0x00.

The FIQ interrupt vector register, FIQVEC, points to a memory

address containing a pointer to the interrupt service routine of

the currently active FIQ. This register should be read only when

an FIQ occurs and FIQ interrupt nesting has been enabled by

setting Bit 1 of the IRQCONN register.

Name:

FIQSTAN

Address:

0xFFFF013C

Default Value: 0x00000000

Access: Read/write

Name:

FIQVEC

Address:

Default Value:

Access:

0xFFFF011C

0x00000000

Read only

Table 137. FIQSTAN MMR Bit Descriptions

Bit

Name

Description

31:8

Reserved. These bits are reserved and should

not be written to.

7:0

Setting this bit to 1 enables nesting of FIQ

interrupts. Clearing this bit means no nesting

or prioritization of FIQs is allowed.

Table 136. FIQVEC MMR Bit Descriptions

Initial

Bit

Type Value

Description

[31:23]

[22:7]

[6:2]

R

0

Always read as 0.

IRQBASE register value.

External Interrupts and PLA interrupts

R/W

The ADuC7124/ADuC7126 provide up to four external

interrupt sources and two PLA interrupt sources. These

external interrupts can be individually configured as level or

rising/falling edge triggered.

Highest priority source. This is a

value between 0 and 27,

representing the currently active

interrupt source. The interrupts are

listed in Table 126. For example, if

the highest currently active FIQ is

Timer2, then these bits are [00100].

To enable the external interrupt source or the PLA interrupt

source, the appropriate bit must first be set in the FIQEN or

IRQEN register. To select the required edge or level to trigger

on, the IRQCONE register must be appropriately configured.

[1:0]

0

Reserved.

FIQSTAN Register

To properly clear an edge-based external IRQ interrupt or an

edge-based PLA interrupt, set the appropriate bit in the IRQCLRE

register.

If IRQCONN Bit 1 is asserted and FIQVEC is read, one of the

FIQSTAN[7:0] bits is asserted. The bit that asserts depends on

the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts, if

Priority 1, Bit 1 asserts, and so forth.

IRQCONE Register

Name:

IRQCONE

0xFFFF0034

0x00000000

Read/write

When a bit is set in this register all interrupts of that priority

and lower are blocked.

Address:

Default Value:

Access:

To clear a bit in this register, all bits of a higher priority must be

cleared first. It is possible to clear only one bit at a time. For

example, if this register is set to 0x09, then writing 0xFF

Table 138. IRQCONE MMR Bit Descriptions

Bit

Value

Name

Description

[31:12]

[11:10]

Reserved. These bits are reserved and should not be written to.

PLA IRQ1 triggers on falling edge.

PLA IRQ1 triggers on rising edge.

PLA IRQ1 triggers on low level.

PLA IRQ1 triggers on high level.

11

10

01

00

11

10

01

00

PLA1SRC[1:0]

[9:8]

IRQ3SRC[1:0]

External IRQ3 triggers on falling edge.

External IRQ3 triggers on rising edge.

External IRQ3 triggers on low level.

External IRQ3 triggers on high level.

Rev. D | Page 91 of 110

ADuC7124/ADuC7126

Data Sheet

Bit

Value

11

10

01

00

11

10

01

00

11

10

01

00

11

10

01

00

Name

Description

[7:6]

IRQ2SRC[1:0]

External IRQ2 triggers on falling edge.

External IRQ2 triggers on rising edge.

External IRQ2 triggers on low level.

External IRQ2 triggers on high level.

PLA IRQ0 triggers on falling edge.

PLA IRQ0 triggers on rising edge.

PLA IRQ0 triggers on low level.

PLA IRQ0 triggers on high level.

External IRQ1 triggers on falling edge.

External IRQ1 triggers on rising edge.

External IRQ1 triggers on low level.

External IRQ1 triggers on high level.

External IRQ0 triggers on falling edge.

External IRQ0 triggers on rising edge.

External IRQ0 triggers on low level.

External IRQ0 triggers on high level.

[5:4]

[3:2]

[1:0]

PLA0SRC[1:0]

IRQ1SRC[1:0]

IRQ0SRC[1:0]

IRQCLRE Register

Name:

IRQCLRE

Address:

0xFFFF0038

0x00000000

Write only

Default Value:

Access:

Table 139. IRQCLRE MMR Bit Descriptions

Bit

Name

Description

[31:25]

24

Reserved. These bits are reserved and should not be written to.

PLA1CLRI

IRQ3CLRI

IRQ2CLRI

PLA0CLRI

IRQ1CLRI

A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edge-

triggered PLA IRQ1 interrupt.

23

22

21

20

A 1 must be written to this bit in the external IRQ3 interrupt service routine to clear an edge-

triggered IRQ3 interrupt.

A 1 must be written to this bit in the external IRQ2 interrupt service routine to clear an edge-

triggered IRQ2 interrupt.

A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edge-

triggered PLA IRQ0 interrupt.

A 1 must be written to this bit in the external IRQ1 interrupt service routine to clear an edge-

triggered IRQ1 interrupt.

[19:18]

17

Reserved. These bits are reserved and should not be written to.

IRQ0CLRI

A 1 must be written to this bit in the external IRQ0 interrupt service routine to clear an edge

triggered IRQ0 interrupt.

[16:0]

Reserved. These bits are reserved and should not be written to.

Rev. D | Page 92 of 110

Data Sheet

ADuC7124/ADuC7126

In normal mode, an IRQ is generated each time the value of the

counter reaches zero when counting down. It is also generated

each time the counter value reaches full scale when counting

up. An IRQ can be cleared by writing any value to clear the

register of that particular timer (TxCLRI).

TIMERS

The ADuC7124/ADuC7126 have four general-purpose

timers/counters.

•

Timer0

Timer1

When using an asynchronous clock-to-clock timer, the

interrupt in the timer block can take more time to clear

than the time it takes for the code in the interrupt routine to

execute. Ensure that the interrupt signal is cleared before

leaving the interrupt service routine. This can be done by

checking the IRQSTA MMR.

Timer2 or wake-up timer

Timer3 or watchdog timer

These four timers in their normal mode of operation can be

either free running or periodic.

In free-running mode, the counter decreases from the maxi-

mum value until zero scale is reached and starts again at the

minimum value. It also increases from the minimum value until

full scale is reached and starts again at the maximum value.

Hr: Min: Sec: 1/128 Format

Timer 1 and Timer 2 have an Hr: Min: Sec: hundreds format.

To use the timer in Hr: Min: Sec: hundreds format, the

32768 kHz clock and prescaler of 256 should be selected. The

hundreds field does not represent milliseconds, but 1/128 of a

second (256/32768).The bits representing the hour, minute,

and second are not consecutive in the register. This arrange-

ment applies to TxLD and TxVAL when using the Hr: Min: Sec:

hundreds format as set in TxCON[5:4]. See Table 140 for more

details.

In periodic mode, the counter decrements/increments from the

value in the load register (TxLD MMR) until zero/full scale is

reached and starts again at the value stored in the load register.

The timer interval is calculated as follows:

If the timer is set to count down, then

(

TxLD

)

× Prescaler

SourceClock

If the timer is set to count up, then

FullScale -TxLD

Interval =

Table 140. Hr: Min: Sec: Hundreds Format

Bit

Value

Description

[31:24]

[23:22]

[21:16]

[15:14]

[13:8]

7

0 to 23 or 0 to 255

hours

0

reserved

(

)

× Prescaler

Interval =

0 to 59

0

minutes

SourceClock

reserved

The value of a counter can be read at any time by accessing

its value register (TxVAL). Note that, when a timer is being

clocked from a clock other than a core clock, an incorrect

value may be read (due to asynchronous clock system). In this

configuration, TxVAL should always be read twice. If the two

readings are different, it should be read a third time to obtain

the correct value.

0 to 59

0

seconds

reserved

[6:0]

0 to 127

1/128 of second

Timers are started by writing in the control register of the

corresponding timer (TxCON).

Rev. D | Page 93 of 110

ADuC7124/ADuC7126

Data Sheet

Timer0 (RTOS Timer)

T0VAL Register

Timer0 is a general-purpose, 16-bit timer (count down) with a

programmable prescaler. The prescaler source is the core clock

frequency (HCLK) and can be scaled by a factor of 1, 16, or 256.

Name:

T0VAL

Address:

0xFFFF0304

0xFFFF

Timer0 can be used to start ADC conversions, as shown in the

block diagram in Figure 53.

Default Value:

Access:

Read only

16-BIT

LOAD

T0VAL is a 16-bit read-only register representing the current

state of the counter.

32.768kHz

OSCILLATOR

16-BIT

DOWN

COUNTER

PRESCALER

÷1, 16, OR 256

TIMER0 IRQ

UCLK

HCLK

ADC CONVERSION

T0CON Register

Name:

T0CON

TIMER0

VALUE

Figure 53. Timer0 Block Diagram

Address:

Default Value:

Access:

0xFFFF0308

0x0000

The Timer0 interface consists of four MMRs: T0LD, T0VAL,

T0CON, and T0CLRI.

Read/write

T0LD Register

T0CON is the configuration MMR described in Table 141.

Name:

T0LD

Address:

Default Value:

Access:

0xFFFF0300

0x0000

Read/write

T0LD is a 16-bit load register.

Rev. D | Page 94 of 110

Data Sheet

ADuC7124/ADuC7126

32-BIT

LOAD

Table 141. T0CON MMR Bit Descriptions

Bit

[31:8]

7

Value Description

32kHz OSCILLATOR

PRESCALER

÷1, 16, 256,

OR 32,768

32-BIT

UP/DOWN

COUNTER

HCLK

UCLK

P1.0

Reserved.

TIMER1 IRQ

ADC CONVERSION

Timer0 enable bit.

Set by the user to enable Timer0.

Cleared by the user to disable Timer0 by

default.

TIMER1

VALUE

CAPTURE

IRQ[19:0]

6

Timer0 mode.

Set by the user to operate in periodic mode.

Cleared by the user to operate in free-running

mode. Default mode.

Figure 54. Timer1 Block Diagram

[5:4]

Clock select bits.

HCLK.

The Timer1 interface consists of five MMRs: T1LD, T1VAL,

T1CON, T1CLRI, and T1CAP.

00

01

10

11

UCLK.

T1LD Register

32.768 kHz.

Name:

T1LD

Reserved.

[3:2]

[1:0]

Prescale.

Address:

Default Value:

Access:

0xFFFF0320

0x00000000

Read/write

00

01

10

11

Core clock/1. Default value.

Core clock/16.

Core clock/256.

Undefined. Equivalent to 00.

Reserved.

T1LD is a 32-bit load register.

T0CLRI Register

T1VAL Register

Name:

T0CLRI

Name:

T1VAL

Address:

0xFFFF030C

0xFF

Address:

Default Value:

Access:

0xFFFF0324

0xFFFFFFFF

Read only

Default Value:

Access:

Write only

T0CLRI is an 8-bit register. Writing any value to this register

clears the interrupt.

T1VAL is a 32-bit read-only register that represents the current

state of the counter.

Timer1 (General-Purpose Timer)

T1CON Register

Timer1 is a general-purpose, 32-bit timer (count down or count

up) with a programmable prescaler. The source can be the 32 kHz

external crystal, the undivided system, the core clock, or P1.1

(maximum frequency 41.78 MHz). This source can be scaled by

a factor of 1, 16, 256, or 32,768.

Name:

T1CON

Address:

Default Value:

Access:

0xFFFF0328

0x0000

Read/write

The counter can be formatted as a standard 32-bit value or as

hours: minutes: seconds: hundredths.

T1CON is the configuration MMR described in Table 142.

Timer1 has a capture register (T1CAP) that can be triggered by

a selected IRQ source initial assertion. This feature can be used

to determine the assertion of an event more accurately than the

precision allowed by the RTOS timer when the IRQ is serviced.

Timer1 can be used to start ADC conversions.

Rev. D | Page 95 of 110

ADuC7124/ADuC7126

Data Sheet

T1CAP Register

Table 142. T1CON MMR Bit Descriptions

Bit

Value Description

Name:

T1CAP

[31:18]

17

Reserved.

Address:

0xFFFF0330

0x00000000

Read

Event select bit.

Set by user to enable time capture of an event.

Cleared by the user to disable time capture of an

event.

Default Value:

Access:

[16:12]

[11:9]

Event select range, 0 to 25. These events are as

described in Table 126. All events are offset by

two, that is, Event 2 in Table 126 becomes Event

0 for the purposes of Timer0.

T1CAP is a 32-bit register. It holds the value contained in

T1VAL when a particular event occurrs. This event must be

selected in T1CON.

Clock select.

Core clock (41 MHz/2^CD).

Timer2 (Wake-Up Timer)

000

001

010

011

Timer2 is a 32-bit wake-up timer, count down or count up, with

a programmable prescaler. The prescaler is clocked directly from

one of four clock sources, including the core clock (default selec-

tion), the internal 32.768 kHz oscillator, the external 32.768 kHz

watch crystal, or the PLL undivided clock. The selected clock

source can be scaled by a factor of 1, 16, 256, or 32,768. The

wake-up timer continues to run when the core clock is disabled.

This gives a minimum resolution of 22 ns when the core is

operating at 41.78 MHz and with a prescaler of 1. Capture of

the current timer value is enabled if the Timer2 interrupt is

enabled via IRQEN[4] (see Table 126).

32.768 kHz.

UCLK.

P1.0 raising edge triggered.

8

Count up.

Set by the user for Timer1 to count up.

Cleared by the user for Timer1 to count down

by default.

7

6

Timer1 enable bit.

Set by the user to enable Timer1.

Cleared by the user to disable Timer1 by default.

Timer1 mode.

Set by the user to operate in periodic mode.

Cleared by the user to operate in free-running

mode. Default mode.

The counter can be formatted as a plain 32-bit value or as

hours: minutes: seconds: hundredths.

Timer2 reloads the value from T2LD either when Timer2

overflows or immediately when T2CLRI is written.

[5:4]

[3:0]

Format.

00

01

10

11

Binary.

Reserved.

The Timer2 interface consists of four MMRs, shown in

Table 143.

Hr: min: sec: hundredths (23 hours to 0 hour).

Hr: min: sec: hundredths (255 hours to 0 hour).

Prescale.

Table 143. Timer2 Interface Registers

Register Description

0000

0100

1000

1111

Source clock/1.

T2LD

32-bit register. Holds 32-bit unsigned integers.

Source clock/16.

T2VAL

32-bit register. Holds 32-bit unsigned integers. This

register is read only.

Source clock/256.

Source clock/32,768.

T2CLRI

T2CON

8-bit register. Writing any value to this register clears

the Timer2 interrupt.

Configuration MMR.

T1CLRI Register

Name:

T1CLRI

Timer2 Load Registers

Address:

0xFFFF032C

0xFF

Name:

T2LD

Default Value:

Access:

Address:

Default Value:

Access:

0xFFFF0340

0x00000

Write only

T1CLRI is an 8-bit register. Writing any value to this register

clears the Timer1 interrupt.

Read/write

T2LD is a 32-bit register, which holds the 32-bit value that is

loaded into the counter.

Rev. D | Page 96 of 110

Data Sheet

ADuC7124/ADuC7126

Timer2 Clear Register

Timer2 Value Register

Name:

T2CLRI

Name:

T2VAL

Address:

Default Value:

Access:

0xFFFF034C

0x00

Address:

Default Value:

Access:

0xFFFF0344

0x0000

Write only

Read only

This 8-bit write-only MMR is written (with any value) by user

code to refresh (reload) Timer2.

T2VAL is a 32-bit register that holds the current value of Timer2.

Timer2 Control Register

Name:

T2CON

Address:

Default Value:

Access:

0xFFFF0348

0x0000

Read/write

This 32-bit MMR configures the mode of operation for Timer2.

Table 144. T2CON MMR Bit Descriptions

Bit

Value Description

[31:11]

10:9]

Reserved.

Clock source select.

00

01

10

11

External 32.768 kHz watch crystal (default).

External 32.768 kHz watch crystal.

Internal 32.768 kHz oscillator.

HCLK.

8

Count up.

Set by the user for Timer2 to count up.

Cleared by the user for Timer2 to count down (default).

7

Timer2 enable bit.

Set by the user to enable Timer2.

Cleared by the user to disable Timer2 (default).

6

Timer2 mode.

Set by the user to operate in periodic mode.

Cleared by the user to operate in free-running mode (default).

[5:4]

Format.

00

01

10

11

Binary (default).

Reserved.

Hr: min: sec: hundredths (23 hours to 0 hours).

Hr: min: sec: hundredths (255 hours to 0 hours).

Prescaler.

[3:0]

0000

0100

1000

1111

Source clock/1 (default).

Source clock/16.

Source clock/256.

Source clock/32,768.

Rev. D | Page 97 of 110

ADuC7124/ADuC7126

Data Sheet

Timer3 (Watchdog Time)

T3VAL Register

Timer3 has two modes of operation: normal mode and

watchdog mode. The watchdog timer is used to recover from

an illegal software state. Once enabled, it requires periodic

servicing to prevent it from forcing a processor reset.

Name:

T3VAL

Address:

0xFFFF0364

0xFFFF

Default Value:

Access:

Normal Mode

Read only

Timer3 in normal mode is identical to Timer0, except for the

clock source and the count-up functionality. The clock source is

32 kHz from the PLL and can be scaled by a factor of 1, 16, or

256 (see Figure 55).

T3VAL is a 16-bit read-only register that represents the current

state of the counter.

T3CON Register

16-BIT

LOAD

Name:

T3CON

Address:

Default Value:

Access:

0xFFFF0368

0x0000

WATCHDOG

16-BIT

RESET

PRESCALER

÷ 1, 16 OR 256

32.768kHz

UP/DOWN

COUNTER

TIMER3 IRQ

Read/write

TIMER3

VALUE

T3CON is the configuration MMR described in Table 145.

Figure 55. Timer3 Block Diagram

Watchdog Mode

Table 145. T3CON MMR Bit Descriptions

Bit

[31:9]

8

Value

Description

Watchdog mode is entered by setting Bit 5 in the T3CON MMR.

Timer3 decreases from the value present in the T3LD register

until 0 is reached. T3LD is used as the timeout. The maximum

timeout can be 512 sec using the prescaler/256 and full scale in

T3LD. Timer3 is clocked by the internal 32 kHz crystal when

operating in the watchdog mode. Note that, to enter watchdog

mode successfully, Bit 5 in the T3CON MMR must be set after

writing to the T3LD MMR.

Reserved.

Count up.

Set by the user for Timer3 to count up.

Cleared by the user for Timer3 to count down

by default.

7

Timer3 enable bit.

Set by the user to enable Timer3.

Cleared by the user to disable Timer3 by

default.

If the timer reaches 0, a reset or an interrupt occurs, depending

on Bit 1 in the T3CON register. To avoid reset or interrupt, any

value must be written to T3CLRI before the expiration period.

This reloads the counter with T3LD and begins a new timeout

period.

6

Timer3 mode.

Set by the user to operate in periodic mode.

Cleared by the user to operate in free-running

mode (default mode).

5

Watchdog mode enable bit.

When watchdog mode is entered, T3LD and T3CON are write-

protected. These two registers cannot be modified until a reset

clears the watchdog enable bit, which causes Timer3 to exit

watchdog mode.

Set by the user to enable watchdog mode.

Cleared by the user to disable watchdog

mode by default.

4

Secure clear bit.

Set by the user to use the secure clear option.

Cleared by the user to disable the secure clear

option by default.

The Timer3 interface consists of four MMRs: T3LD, T3VAL,

T3CON, and T3CLRI.

T3LD Register

[3:2]

Prescale.

00

01

10

11

Source clock/1 by default.

Source clock/16.

Name:

T3LD

Address:

Default Value:

Access:

0xFFFF0360

0x0000

Source clock/256.

Undefined. Equivalent to 00.

1

0

Watchdog IRQ option bit.

Set by the user to produce an IRQ instead of a

reset when the watchdog reaches 0.

Cleared by the user to disable the IRQ option.

Read/write

T3LD is a 16-bit load register.

Reserved.

Rev. D | Page 98 of 110

Data Sheet

ADuC7124/ADuC7126

T3CLRI Register

The memory interface can address up to four 128 kB of

asynchronous memory (SRAM or/and EEPROM).

Name:

T3CLRI

The pins required for interfacing to an external memory are

shown in Table 146.

Address:

0xFFFF036C

0x00

Default Value:

Access:

Table 146. External Memory Interfacing Pins

Function

Write only

AD[15:0]

A16

MS[3:0]

WS

Address/data bus.

Extended addressing for 8-Bit memory only.

Memory select.

T3CLRI is an 8-bit register. Writing any value to this register on

successive occassions clears the Timer3 interrupt in normal

mode or resets a new timeout period in watchdog mode.

Write strobe.

RS

Read strobe.

Note that the user must perform successive writes to this

register to ensure resetting the timeout period.

AE

BHE, BLE

Address latch enable.

Byte write capability.

Secure Clear Bit (Watchdog Mode Only)

There are four external memory regions available as described

in Table 147. Associated with each region are the MS[3:0] pins.

These signals allow access to the particular region of external

memory. The size of each memory region can be 128 kB maxi-

mum, 64 k × 16 or 128 kB × 8. To access 128 kB with an 8-bit

memory, an extra address line (A16) is provided (see the example

in Figure 57). The four regions are configured independently.

The secure clear bit is provided for a higher level of protection.

When set, a specific sequential value must be written to T3CLRI

to avoid a watchdog reset. The value is a sequence generated

by the 8-bit linear feedback shift register (LFSR) polynomial =

X₈+ X₆+ X₅+ X + 1, as shown in Figure 56.

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

7

6

5

4

3

2

1

0

Table 147. Memory Regions

CLOCK

Address Start

0x10000000

0x20000000

0x30000000

0x40000000

Address End

0x1000FFFF

0x2000FFFF

0x3000FFFF

0x4000FFFF

Contents

Figure 56. 8-Bit LFSR

External Memory 0

External Memory 1

External Memory 2

External Memory 3

The initial value or seed is written to T3CLRI before entering

watchdog mode. After entering watchdog mode, a write to

T3CLRI must match this expected value. If it matches, the LFSR

is advanced to the next state when the counter reload occurs. If

it fails to match the expected state, a reset is immediately

generated, even if the count has not yet expired.

Each external memory region can be controlled through three

MMRs: XMCFG, XMxCON, and XMxPAR.

EEPROM

64k × 16-BIT

ADuC7126

The value 0x00 should not be used as an initial seed due to the

properties of the polynomial. The value 0x00 is always guaran-

teed to force an immediate reset. The value of the LFSR cannot

be read; it must be tracked/generated in software.

A16

AD15:AD0

D0:D15

A0:A15

LATCH

Example of a sequence:

AE

MS0

MS1

CS

1. Enter initial seed, 0xAA, in T3CLRI before starting Timer3

in watchdog mode.

WS

RS

WE

OE

2. Enter 0xAA in T3CLRI; Timer3 is reloaded.

3. Enter 0x37 in T3CLRI; Timer3 is reloaded.

4. Enter 0x6E in T3CLRI; Timer3 is reloaded.

5. Enter 0x66. 0xDC was expected; the watchdog resets the chip.

EXTERNAL MEMORY INTERFACING

RAM

128k × 8-BIT

D0:D7

A16

A0:A15

CS

WE

OE

The ADuC7124/ADuC7126 feature an external memory

interface. The external memory interface requires a larger

number of pins. The XMCFG MMR must be set to 1 to use the

external port.

Figure 57. Interfacing to External EEPROM/RAM

Although 32-bit addresses are supported internally, only the

lower 16 bits of the address are on external pins.

Rev. D | Page 99 of 110

ADuC7124/ADuC7126

Data Sheet

XMCFG Register

XMxPAR are registers that define the protocol used for

accessing the external memory for each memory region.

Name:

XMCFG

0xFFFFF000

0x00

Address:

Default Value:

Access:

Table 151. XMxPAR MMR Bit Descriptions

Bit

Description

15

Enable byte write strobe. This bit is only used for two

8-bit memory blocks sharing the same memory region.

Set by the user to gate the A0 output with the WS

output. This allows byte write capability without using

BHE and BLE signals.

Read/write

XMCFG is set to 1 to enable external memory access. This must

be set to 1 before any port pins can function as external memory

access pins. The port pins must also be individually enabled via

the GPxCON MMR.

Cleared by user to use BHE and BLE signals.

[14:12] Number of wait states on the address latch enable strobe.

11

10

Reserved.

Table 148. XMxCON Registers

Extra address hold time.

Name

Address

Default Value

0x00

Access

R/W

Set by the user to disable extra hold time.

Cleared by the user to enable one clock cycle of hold

on the address in read and write.

XM0CON

XM1CON

XM2CON

XM3CON

0xFFFFF010

0xFFFFF014

0xFFFFF018

0xFFFFF01C

9

Extra bus transition time on read.

Set by the user to disable extra bus transition time.

Cleared by the user to enable one extra clock before

and after the read strobe (RS).

XMxCON are the control registers for each memory region.

They allow the enabling/disabling of a memory region and

control the data bus width of the memory region.

8

Extra bus transition time on write.

Set by the user to disable extra bus transition time.

Cleared by the user to enable one extra clock before and

after the write strobe (WS).

Table 149. XMxCON MMR Bit Descriptions

Bit Description

[7:4]

[3:0]

Number of write wait states.

1

Selects data bus width.

Select the number of wait states added to the length of

the WS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default

value).

Set by the user to select a 16-bit data bus.

Cleared by the user to select an 8-bit data bus.

0

Enables memory region.

Number of read wait states.

Set by the user to enable memory region.

Cleared by the user to disable the memory region.

Select the number of wait states added to the length of

the RS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles

(default value).

Table 150. XMxPAR Registers

Figure 58, Figure 59, Figure 60, and Figure 61 show the timing

for a read cycle, a read cycle with address hold and bus turn

cycles, a write cycle with address and write hold cycles, and a

write cycle with wait sates, respectively.

Name

Address

Default Value

0x70FF

Access

R/W

XM0PAR

XM1PAR

XM2PAR

XM3PAR

0xFFFFF020

0xFFFFF024

0xFFFFF028

0xFFFFF02C

Rev. D | Page 100 of 110

Data Sheet

ADuC7124/ADuC7126

MCLK

AD[15:0]

MSx

ADDRESS

DATA

AE

RS

Figure 58. External Memory Read Cycle

MCLK

AD[15:0]

ADDRESS

DATA

EXTRA ADDRESS

HOLD TIME

XMxPAR (BIT 10)

MSx

AE

RS

BUS TURN OUT CYCLE

(BIT 9)

BUS TURN OUT CYCLE

(BIT 9)

Figure 59. External Memory Read Cycle with Address Hold and Bus Turn Cycles

Rev. D | Page 101 of 110

ADuC7124/ADuC7126

Data Sheet

MCLK

AD[15:0]

ADDRESS

DATA

EXTRA ADDRESS

HOLD TIME

(BIT 10)

MSx

AE

WS

WRITE HOLD ADDRESS

AND DATA CYCLES

(BIT 8)

WRITE HOLD ADDRESS

AND DATA CYCLES

(BIT 8)

Figure 60. External Memory Write Cycle with Address and Write Hold Cycles

MCLK

AD[15:0]

ADDRESS

DATA

MSx

AE

1 ADDRESS WAIT STATE

(BIT 14 TO BIT 12)

WS

1 WRITE STROBE WAIT STATE

(BIT 7 TO BIT 4)

Figure 61. External Memory Write Cycle with Wait States

Rev. D | Page 102 of 110

Data Sheet

ADuC7124/ADuC7126

HARDWARE DESIGN CONSIDERATIONS

Finally, note that the analog and digital ground pins on the

ADuC7124/ADuC7126 must be referenced to the same system

ground reference point at all times.

POWER SUPPLIES

The ADuC7124/ADuC7126 operational power supply voltage

range is 2.7 V to 3.6 V. Separate analog and digital power supply

pins (AV_DDand IOV_DD, respectively) allow AV_DDto be kept

relatively free of noisy digital signals often present on the

system IOV_DDline. In this mode, the part can also operate with

split supplies; that is, it can use different voltage levels for each

supply. For example, the system can be designed to operate

with an IOV_DDvoltage level of 3.3 V while the AV_DDlevel can be

at 3 V or vice versa. A typical split supply configuration is

shown in Figure 62.

IOV_DDSupply Sensitivity

The IOV_DDsupply is sensitive to high frequency noise because it

is the supply source for the internal oscillator and PLL circuits.

When the internal PLL loses lock, the clock source is removed

by a gating circuit from the CPU, and the ARM7TDMI core

stops executing code until the PLL regains lock. This feature

ensures that no flash interface timings or ARM7TDMI timings

are violated.

ANALOG

SUPPLY

DIGITAL

Typically, frequency noise greater than 50 kHz and 50 mV p-p

on top of the supply causes the core to stop working.

SUPPLY

+

–

+

–

10µF

ADuC7124/

ADuC7126

If decoupling values recommended in the Power Supplies

section do not sufficiently dampen all noise sources below

50 mV on IOV_DD, a filter such as the one shown in Figure 64 is

recommended.

AV

DD

IOV

DD

DACV

0.1µF

1µH

GND

REF

DACGND

AGND

DIGITAL

SUPPLY

10µF

+

ADuC7124/

ADuC7126

–

IOGND

IOV

DD

Figure 62. External Dual Supply Connections

0.1µF

As an alternative to providing two separate power supplies, the

user can reduce noise on AV_DDby placing a small series resistor

and/or ferrite bead between AV_DDand IOV_DDand then decoupling

AV_DDseparately to ground. An example of this configuration is

shown in Figure 63. With this configuration, other analog circuitry

(such as op amps, voltage reference, or any other analog circuitry)

can be powered from the AV_DDsupply line as well.

BEAD

IOGND

Figure 64. Recommended IOV_DDSupply Filter

Linear Voltage Regulator

The ADuC7124/ADuC7126 require a single 3.3 V supply, but

the core logic requires a 2.6 V supply. An on-chip linear

regulator generates the 2.6 V from IOV_DDfor the core logic. The

LV_DDpin is the 2.6 V supply for the core logic. An external

compensation capacitor of 0.47 µF must be connected between

LV_DDand DGND (as close as possible to these pins) to act as a

tank of charge as shown in Figure 65.

DIGITAL SUPPLY

ANALOG SUPPLY

10µF

+

10µF

–

ADuC7124/

ADuC7126

IOV

DD

AV

DD

IOV

0.1µF

ADuC7124/

ADuC7126

DGND

AGND

LV

DD

0.47µF

DGND

Figure 63. External Single Supply Connections

Notice that in both Figure 62 and Figure 63, a large value (10 µF)

reservoir capacitor sits on IOV_DD, and a separate 10 µF capacitor

sits on AV_DD. In addition, local small-value (0.1 µF) capacitors are

located at each AV_DDand IOV_DDpin of the chip. As per standard

design practice, be sure to include all of these capacitors and ensure

that the smaller capacitors are close to each AV_DDpin with trace

lengths as short as possible. Connect the ground terminal of

each of these capacitors directly to the underlying ground plane.

Figure 65. Voltage Regulator Connections

The LV_DDpin should not be used for any other chip. It is also

recommended to use excellent power supply decoupling on

IOV_DDto help improve line regulation performance of the on-

chip voltage regulator.

Rev. D | Page 103 of 110

ADuC7124/ADuC7126

Data Sheet

For example, do not power components on the analog side (as

seen in Figure 66b) with IOV_DDbecause that forces return

currents from IOV_DDto flow through AGND. Avoid digital

currents flowing under analog circuitry, which can occur if a

noisy digital chip is placed on the left half of the board (shown

in Figure 66c). If possible, avoid large discontinuities in the

ground plane(s), such as those formed by a long trace on the same

layer, because they force return signals to travel a longer path.

In addition, make all connections to the ground plane directly,

with little or no trace separating the pin from its via to ground.

GROUNDING AND BOARD LAYOUT

RECOMMENDATIONS

As with all high resolution data converters, special attention

must be paid to grounding and PC board layout of the

ADuC7124/ADuC7126-based designs to achieve optimum

performance from the ADCs and DAC.

Although the part has separate pins for analog and digital ground

(AGND and IOGND), the user must not tie these to two sepa-

rate ground planes unless the two ground planes are connected

very close to the part. This is illustrated in the simplified example

shown in Figure 66a. In systems where digital and analog

ground planes are connected together somewhere else (at the

power supply of the system, for example), the planes cannot be

reconnected near the part because a ground loop results. In these

cases, tie all the ADuC7124/ADuC7126 AGND and IOGND

pins to the analog ground plane, as illustrated in Figure 66b.

In systems with only one ground plane, ensure that the digital

and analog components are physically separated onto separate

halves of the board so that digital return currents do not flow

near analog circuitry (and vice versa).

When connecting fast logic signals (rise/fall time < 5 ns) to any of

the ADuC7124/ADuC7126 digital inputs, add a series resistor

to each relevant line to keep rise and fall times longer than 5 ns

at the input pins of the part. A value of 100 Ω or 200 Ω is

usually sufficient to prevent high speed signals from coupling

capacitively into the part and affecting the accuracy of ADC

conversions.

CLOCK OSCILLATOR

The clock source for the ADuC7124/ADuC7126 can be gener-

ated by the internal PLL or by an external clock input. To use

the internal PLL, connect a 32.768 kHz parallel resonant crystal

between XCLKI and XCLKO, and connect a capacitor from

each pin to ground as shown in Figure 67. The crystal allows the

PLL to lock correctly to give a frequency of 41.78 MHz. If no

external crystal is present, the internal oscillator is used to give

a typical frequency of 32.768 kHz 3ꢀ.

The ADuC7124/ADuC7126 can then be placed between the

digital and analog sections, as illustrated in Figure 66c.

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

a.

ADuC7124/

ADuC7126

XCLKI

AGND

DGND

12pF

32.768kHz

TO

INTERNAL

PLL

12pF

XCLKO

PLACE ANALOG

COMPONENTS

HERE

PLACE DIGITAL

COMPONENTS HERE

b.

Figure 67. External Parallel Resonant Crystal Connections

To use an external source clock input instead of the PLL (see

Figure 68), Bit 1 and Bit 0 of PLLCON must be modified. The

external clock uses P0.7 and XCLK.

AGND

DGND

ADuC7124/

ADuC7126

XCLKO

PLACE ANALOG

COMPONENTS HERE

PLACE DIGITAL

COMPONENTS HERE

XCLKI

c.

EXTERNAL

CLOCK

SOURCE

TO

FREQUENCY

DIVIDER

DGND

XCLK

Figure 68. Connecting an External Clock Source

Figure 66. System Grounding Schemes

Using an external clock source, the ADuC7124/ADuC7126

specified operational clock speed range is 50 kHz to 41.78 MHz

1ꢀ, which ensures correct operation of the analog peripherals

and Flash/EE.

In all of these scenarios, and in more complicated real-life

applications, the users should pay particular attention to the

flow of current from the supplies and back to ground. Make

sure the return paths for all currents are as close as possible to

the paths the currents took to reach their destinations.

Rev. D | Page 104 of 110

Data Sheet

ADuC7124/ADuC7126

3.3V

POWER-ON RESET OPERATION

IOV

LV

DD

An internal power-on reset (POR) is implemented on the

ADuC7124/ADuC7126. For LV_DDbelow 2.40 V typical, the

internal POR holds the part in reset. As LV_DDrises above 2.41 V,

an internal timer times out for typically 128 ms before the part

is released from reset. The user must ensure that the power

supply, IOV_DD, reaches a stable 2.7 V minimum level by this

time. Likewise, on power-down, the internal POR holds the part

in reset until LV_DDdrops below 2.40 V. Figure 69 illustrates the

operation of the internal POR in detail.

2.6V

2.41V TYP

DD

128ms TYP

POR

0.12ms TYP

MRST

Figure 69. Internal Power-On Reset Operation

Rev. D | Page 105 of 110

ADuC7124/ADuC7126

OUTLINE DIMENSIONS

Data Sheet

9.10

9.00 SQ

8.90

0.60 MAX

0.60

MAX

PIN 1

INDICATOR

49

48

64

1

PIN 1

INDICATOR

8.85

8.75 SQ

8.65

*

EXPOSED

PAD

0.50

BSC

4.85

4.70 SQ

4.55

0.50

0.40

0.30

33

32

16

17

0.25 MIN

BOTTOM VIEW

7.50 REF

TOP VIEW

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

0.30

0.23

0.18

SEATING

PLANE

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 70. 64-Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm x 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

14.20

14.00 SQ

13.80

0.75

0.60

0.45

1.60

MAX

80

61

60

1

12.20

12.00 SQ

11.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

20

41

0.15

0.05

21

40

SEATING

PLANE

0.08

COPLANARITY

VIEW A

0.50

BSC

0.27

0.22

0.17

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BDD

Figure 71. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-1)

Dimensions shown in millimeters

Rev. D | Page 106 of 110

Data Sheet

ADuC7124/ADuC7126

ORDERING GUIDE

ADC

DAC

Channels

Temperature

Downloader Range

Package

Description

Package

Option

Ordering

Quantity

Model¹

Channels

Flash/RAM

GPIO

ADuC7124BCPZ126

10

2

126 kB/32 kB

30

UART

−40°C to +125°C 64-Lead

LFCSP_VQ

CP-64-1

260

ADuC7124BCPZ126-RL

10

2

126 kB/32 kB

30

UART

−40°C to +125°C 64-Lead

LFCSP_VQ

CP-64-1

2500

ADuC7126BSTZ126

ADuC7126BSTZ126-RL

ADuC7126BSTZ126I

ADuC7126BSTZ126IRL 12

EVAL-ADuC7124QSPZ

12

4

126 kB/32 kB

40

UART

I²C

−40°C to +125°C 80-Lead LQFP

ST-80-1

119

1000

119

I²C

1000

ADuC7124

QuickStart

Development

System

EVAL-ADuC7126QSPZ

ADuC7126

QuickStart

Development

System

¹Z = RoHS Compliant Part.

Rev. D | Page 107 of 110

ADuC7124/ADuC7126

NOTES

Data Sheet

Rev. D | Page 108 of 110

Data Sheet

NOTES

ADuC7124/ADuC7126

Rev. D | Page 109 of 110

ADuC7124/ADuC7126

NOTES

Data Sheet

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09123-0-10/14(D)

Rev. D | Page 110 of 110


型号：	ADUC7126BSTZ126I
厂家：	ADI
描述：	Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler 时钟微控制器外围集成电路
文件：	总110页 (文件大小：1497K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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