ADUC812BS-REEL [ADI]
MSC-51 8K-Flash/256-RAM/640-EEPROM(543.84 k) ; MSC- 51 8K闪存/ 256 RAM / 640 - EEPROM ( 543.84 K)\n型号: | ADUC812BS-REEL |
厂家: | ADI |
描述: | MSC-51 8K-Flash/256-RAM/640-EEPROM(543.84 k)
|
文件: | 总31页 (文件大小:543K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MicroConverter™, Multichannel
12-Bit ADC with Embedded FLASH MCU
a
ADuC812
FEATURES
APPLICATIONS
ANALOG I/O
Intelligent Sensors (IEEE 1451.2-Compatible)
Battery Powered Systems (Portable PCs, Instruments,
Monitors)
8-Channel, High Accuracy 12-Bit ADC
On-Chip, 40 ppm/ꢁC Voltage Reference
High Speed 200 kSPS
Transient Capture Systems
DMA Controller for High Speed ADC-to-RAM Capture
Two 12-Bit Voltage Output DACs
On-Chip Temperature Sensor Function
MEMORY
8K Bytes On-Chip Flash/EE Program Memory
640 Bytes On-Chip Flash/EE Data Memory
On-Chip Charge Pump (No Ext. VPP Requirements)
256 Bytes On-Chip Data RAM
16M Bytes External Data Address Space
64K Bytes External Program Address Space
8051-COMPATIBLE CORE
12 MHz Nominal Operation (16 MHz Max)
Three 16-Bit Timer/Counters
DAS and Communications Systems
GENERAL DESCRIPTION
The ADuC812 is a fully integrated 12-bit data acquisition
system incorporating a high performance self-calibrating
multichannel ADC, two 12-bit DACs and programmable 8-bit
(8051-compatible) MCU on a single chip.
The programmable 8051-compatible core is supported by
8K bytes Flash/EE program memory, 640 bytes Flash/EE data
memory and 256 bytes data SRAM on-chip.
Additional MCU support functions include Watchdog Timer,
Power Supply Monitor and ADC DMA functions. 32 Program-
mable I/O lines, I2C-compatible, SPI and Standard UART
Serial Port I/O are provided for multiprocessor interfaces and
I/O expansion.
32 Programmable I/O lines
High Current Drive Capability—Port 3
Nine Interrupt Sources, Two Priority Levels
POWER
Specified for 3 V and 5 V Operation
Normal, Idle and Power-Down Modes
ON-CHIP PERIPHERALS
Normal, idle and power-down operating modes for both the
MCU core and analog converters allow for flexible power man-
agement schemes suited to low power applications. The part is
specified for 3 V and 5 V operation over the industrial tempera-
ture range and is available in a 52-lead, plastic quad flatpack
package.
UART Serial I/O
2-Wire (I2C®-Compatible) and SPI® Serial I/O
Watchdog Timer
Power Supply Monitor
FUNCTIONAL BLOCK DIAGRAM
P0.0
T/H
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
ADuC812
BUF
BUF
AIN0 (P1.0)
AIN7 (P1.7)
12-BIT
DAC0
DAC0
ADC
12-BIT
CONTROL
AND
DAC
CONTROL
SUCCESSIVE
AIN
MUX
APPROXIMATION
ADC
CALIBRATION
LOGIC
12-BIT
DAC1
DAC1
T0 (P3.4)
T1 (P3.5)
MICROCONTROLLER
T2 (P1.0)
T2EX (P1.1)
8051-COMPATIBLE
MICROCONTROLLER
POWER SUPPLY
MONITOR
3 ꢀ 16-BIT
TIMER/COUNTERS
2.5V
REF
TEMP
SENSOR
WATCHDOG
TIMER
2-WIRE
SPI
8K BYTES FLASH/EE
PROGRAM MEMORY
INT0 (P3.2)
INT1 (P3.3)
ALE
SERIAL I/O
BUF
640 BYTES FLASH/EE
DATA MEMORY
ON-CHIP SERIAL
DOWN LOADER
MUX
V
REF
PSEN
256 ꢀ 8 USER
OSC
UART
EA
RAM
C
REF
RESET
XTAL XTAL TxD RxD
SCLOCK
MISO
(P3.3)
AV
AGND DV
DGND
MOSI/
SDATA
DD
DD
1
2
(P3.0) (P3.1)
I2C is a registered trademark of Philips Corporation.
MicroConverter is a trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
ADuC812–SPECIFICATIONS1, 2
(AVDD = DVDD = +3.0 V or +5.0 V ꢂ 10%, VREF = 2.5 V Internal Reference,
MCLKIN = 16.0 MHz, DAC VOUT Load to AGND; RL = 10 kꢃ, CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.)
ADuC812BS
Parameter
VDD = 5 V
VDD = 3 V
Units
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
DC ACCURACY3, 4
Resolution
12
12
Bits
Integral Nonlinearity
± 1/2
± 1.5
± 1.5
± 1
± 1/2
LSB typ
LSB max
LSB typ
LSB typ
fSAMPLE = 100 kHz
fSAMPLE = 100 kHz
fSAMPLE = 200 kHz
fSAMPLE = 100 kHz. Guaranteed No
Missing Codes at 5 V
± 1.5
± 1
Differential Nonlinearity
CALIBRATED ENDPOINT ERRORS5, 6
Offset Error
± 5
± 1
1
± 6
± 1
1.5
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
± 2
Offset Error Match
Gain Error
1
± 2
1.5
Gain Error Match
USER SYSTEM CALIBRATION7
Offset Calibration Range
Gain Calibration Range
± 5
± 2.5
±±
± 2.5
% of VREF typ
% of VREF typ
DYNAMIC PERFORMANCE
fIN = 10 kHz Sine Wave
f
SAMPLE = 100 kHz
Signal-to-Noise Ratio (SNR)8
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
70
–78
–78
70
–78
–78
dB typ
dB typ
dB typ
ANALOG INPUT
Input Voltage Ranges
Leakage Current
0 to VREF
± 10
0 to VREF
Volts
µA max
µA typ
pF max
± 1
+1
20
Input Capacitance
20
TEMPERATURE SENSOR9
Voltage Output at +25°C
Voltage TC
600
–3.0
600
–3.0
mV typ
mV/°C typ
Measured On-Chip via a Typical
± 0.5 LSB (610 µV) Accurate ADC
DAC CHANNEL SPECIFICATIONS
DC ACCURACY10
Resolution
12
± 3
12
± 3
± 1
Bits
Relative Accuracy
Differential Nonlinearity
Offset Error
LSB typ
LSB typ
mV max
mV typ
mV max
mV typ
% typ
± 0.5
± 50
± 25
± 25
± 10
± 0.5
Guaranteed 12-Bit Monotonic
% of Full-Scale on DAC1
± 25
Full-Scale Error
± 10
± 0.5
Full-Scale Mismatch
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Resistive Load
Capacitive Load
Output Impedance
ISINK
0 to VREF
0 to VDD
10
100
0.5
0 to VREF
0 to VDD
10
100
0.5
V typ
V typ
kΩ typ
pF typ
Ω typ
50
50
µA typ
–2–
REV. 0
ADuC812
ADuC812BS
VDD = 5 V VDD = 3 V
Parameter
Units
Test Conditions/Comments
DAC AC CHARACTERISTICS
Voltage Output Settling Time
15
10
15
10
µs typ
Full-Scale Settling Time to
Within 1/2 LSB of Final Value
1 LSB Change at Major Carry
Digital-to-Analog Glitch Energy
nV sec typ
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
2.3/VDD
150
2.45/2.55
2.5
2.3/VDD
150
V min/max
kΩ typ
REFOUT Output Voltage
V min/max
V typ
2.5
40
REFOUT Tempco
40
ppm/°C typ
FLASH/EE MEMORY PERFORMANCE
CHARACTERISTICS11, 12
Endurance
10,000
50,000
10
Cycles min
Cycles typ
Years min
50,000
64
Data Retention
WATCHDOG TIMER
CHARACTERISTICS
Oscillator Frequency
64
kHz typ
POWER SUPPLY MONITOR
CHARACTERISTICS
Power Supply Trip Point Accuracy
± 2.5
% of Selected
Nominal Trip
Point Voltage
max
± 1.0
± 1.0
% of Selected
Nominal Trip
Point Voltage
typ
DIGITAL INPUTS
Input High Voltage (VINH
Input Low Voltage (VINL
Input Leakage Current (Port 0, EA)
)
)
2.4
0.8
± 10
± 1
V min
V max
µA max
µA typ
VIN = 0 V or VDD
VIN = 0 V or VDD
± 1
Logic 1 Input Current
(All Digital Inputs)
± 10
± 1
–80
–40
µA max
µA typ
µA max
µA typ
µA max
µA typ
pF typ
VIN = VDD
VIN = VDD
± 1
Logic 0 Input Current (Port 1, 2, 3)
–40
VIL = 450 mV
Logic 1-0 Transition Current (Port 1, 2, 3) –700
–400
Input Capacitance
V
V
IL = 2 V
IL = 2 V
–400
10
10
REV. 0
–3–
ADuC812–SPECIFICATIONS1, 2
ADuC812BS
Parameter
VDD = 5 V
VDD = 3 V
Units
Test Conditions/Comments
DIGITAL OUTPUTS
Output High Voltage (VOH
)
2.4
4.0
V min
V typ
VDD = 4.5 V to 5.5 V
ISOURCE = 80 µA
VDD = 2.7 V to 3.3 V
2.6
ISOURCE = 20 µA
Output Low Voltage (VOL
)
ALE, PSEN, Ports 0 and 2
0.4
0.2
0.4
0.2
± 10
± 5
V max
V typ
V max
V typ
µA max
µA typ
pF typ
ISINK = 1.6 mA
ISINK = 1.6 mA
ISINK = 8 mA
0.2
0.2
Port 3
I
SINK = 8 mA
Floating State Leakage Current
Floating State Output Capacitance
± 5
10
10
POWER REQUIREMENTS13, 14, 15
IDD Normal Mode16
42
32
26
8
25
18
15
7
mA max
mA typ
mA typ
mA typ
mA max
mA typ
mA typ
mA typ
µA max
µA typ
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 12 MHz
MCLKIN = 1 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 12 MHz
MCLKIN = 1 MHz
16
12
3
IDD Idle Mode
17
6
2
50
5
IDD Power-Down Mode17
50
5
NOTES
1Specifications apply after calibration.
2Temperature range –40°C to +85°C.
3Linearity is guaranteed during normal MicroConverter Core operation.
4Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.
5Measured in production at VDD = 5 V after Software Calibration Routine at +25°C only.
6User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.
7The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.
8SNR calculation includes distortion and noise components.
9The temperature sensor will give a measure of the die temperature directly, air temperature can be inferred from this result.
10DAC linearity is calculated using:
reduced code range of 48 to 4095, 0 to VREF range
reduced code range of 48 to 3995, 0 to VDD range
DAC output load = 10 kΩ and 50 pF.
11Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification A103 (Data Retention) and JEDEC Draft Specification All7 (Endurance).
12Endurance Cycling is evaluated under the following conditions:
Mode
= Byte Programming, Page Erase Cycling
Cycle Pattern
Erase Time
Program Time
= 00Hex to FFHex
= 20 ms
= 100 µs
13
I
at other MCLKIN frequencies is typically given by:
DD
Normal Mode (VDD = 5 V):
IDD = (1.6 × MCLKIN) + 6
IDD = (0.8 × MCLKIN) + 3
IDD = (0.75 × MCLKIN) + 6
IDD = (0.25 × MCLKIN) + 3
Normal Mode (VDD = 3 V):
Idle Mode (VDD = 5 V):
Idle Mode (VDD = 3 V):
Where MCLKIN is the oscillator frequency in MHz and resultant IDD values are in mA.
14
15
I
I
Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.
is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.
DD
DD
16Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on).
17EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.
Typical specifications are not production tested, but are supported by characterization data at initial product release.
Specifications subject to change without notice.
Please refer to User Guide, Quick Reference Guide, Application Notes and Silicon Errata Sheet at www.analog.com/microconverter for additional information.
–4–
REV. 0
ADuC812
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
PIN CONFIGURATION
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND . . . . . –0.3 V, DVDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V, DVDD + 0.3 V
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
P1.0/ADC0/T2
P1.1/ADC1/T2EX
P1.2/ADC2
P2.7/A15/A23
P2.6/A14/A22
P2.5/A13/A21
P2.4/A12/A20
DGND
PIN 1
IDENTIFIER
V
REF to AGND . . . . . . . . . . . . . . . . . . .–0.3 V, AVDD + 0.3 V
Analog Inputs to AGND . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V
Operating Temperature Range
3
4
P1.3/ADC3
5
AV
DD
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
6
DV
DD
AGND
ADuC812
TOP VIEW
(Not to Scale)
7
C
V
XTAL2 (OUTPUT)
XTAL1 (INPUT)
P2.3/A11/A19
P2.2/A10/A18
P2.1/A9/A17
REF
8
REF
9
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
DAC0
DAC1
10
11
12
13
Lead Temperature, Soldering
P1.4/ADC4
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
P2.0/A8/A16
P1.5/ADC5/SS
P1.6/ADC6
SDATA/MOSI
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
14 15 16 17 18 19 20 21 22 23 24 25 26
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
ADuC812BS
–40°C to +85°C
52-Lead Plastic Quad Flatpack
S-52
QuickStart™ Development System
Eval-ADuC812QS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
ADuC812
PIN FUNCTION DESCRIPTIONS
Mnemonic
Type Function
DVDD
AVDD
CREF
VREF
P
Digital Positive Supply Voltage, +3 V or +5 V nominal.
P
Analog Positive Supply Voltage, +3 V or +5 V nominal.
I
Decoupling pin for on-chip reference. Connect 0.1 µF between this pin and AGND.
I/O
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this
appears at the pin (once the ADC or DAC peripherals are enabled). This pin can be overdriven by an exter-
nal reference.
AGND
G
I
Analog Ground. Ground Reference point for the analog circuitry.
P1.0–P1.7
Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure
any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.
ADC0–ADC7
T2
I
I
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to
a 1 to 0 transition of the T2 input.
T2EX
I
Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for
Counter 2.
SS
I
Slave Select input for the SPI interface.
SDATA
SCLOCK
MOSI
MISO
DAC0
DAC1
RESET
I/O
I/O
I/O
I/O
O
User selectable, I2C-Compatible Input/Output pin or SPI Data Input/Output pin.
Serial Clock pin for I2C-Compatible or SPI serial interface clock.
SPI Master Output/Slave Input Data I/O pin for SPI interface.
Master Input/Slave Output Data I/O pin for SPI Serial Interface.
Voltage Output from DAC0.
O
Voltage Output from DAC1.
I
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the
device.
P3.0–P3.7
I/O
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions which are described below.
RxD
TxD
INT0
I/O
O
I
Receiver Data Input (asynchronous) or Data Input/ Output (synchronous) of serial (UART) port.
Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.
Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 0.
INT1
I
Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 1.
T0
I
I
I
Timer/Counter 0 Input.
Timer/Counter 1 Input.
T1
CONVST
Active low Convert Start Logic input for the ADC block when the external Convert start function is en-
abled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.
WR
O
O
O
I
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
Output of the inverting oscillator amplifier.
RD
XTAL2
XTAL1
DGND
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Digital Ground. Ground reference point for the digital circuitry.
G
I/O
P2.0–P2.7
(A8–A15)
(A16–A23)
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits
the high order address bytes during fetches from external program memory and middle and high order
address bytes during accesses to the external 24-bit external data memory space.
PSEN
O
Program Store Enable, Logic Output. This output is a control signal that enables the external program
memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.
–6–
REV. 0
ADuC812
Mnemonic
Type Function
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and middle byte for 24-bit
address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.
EA
I
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from
internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch
all instructions from external program memory.
P0.7–P0.0
(A0–A7)
I/O
Port 0 is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in that
state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus
during accesses to external program or data memory. In this application it uses strong internal pull-ups
when emitting 1s.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition and full scale, a point
1/2 LSB above the last code transition.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
DAC SPECIFICATIONS
Offset Error
Relative Accuracy
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.
Relative accuracy or endpoint linearity is a measure of the maxi-
mum deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.
Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.
Voltage Output Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.
REV. 0
–7–
ADuC812
ADuC812 ARCHITECTURE, MAIN FEATURES
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of bit
addressable memory space at bit addresses 00H through 7FH.
The ADuC812 is a highly integrated high accuracy 12-bit data
acquisition system. At its core, the ADuC812 incorporates a high
performance 8-bit (8051-Compatible) MCU with on-chip repro-
grammable nonvolatile Flash/EE program memory controlling a
multichannel (8-input channels), 12-bit ADC.
The SFR space is mapped in the upper 128 bytes of internal
data memory space. The SFR area is accessed by direct address-
ing only and provides an interface between the CPU and all on-
chip peripherals. A block diagram showing the programming
model of the ADuC812 via the SFR area is shown in Figure 3.
The chip incorporates all secondary functions to fully support the
programmable data acquisition core. These secondary functions
include User Flash/EE Data Memory, Watchdog Timer (WDT),
Power Supply Monitor (PSM) and various industry-standard
parallel and serial interfaces.
7FH
ADuC812 MEMORY ORGANIZATION
As with all 8051-compatible devices, the ADuC812 has separate
address spaces for Program and Data memory as shown in Fig-
ure 1. Also as shown in Figure 1, an additional 640 Bytes of
Flash/EE Data Memory are available to the user. The Flash/EE
Data Memory area is accessed indirectly via a group of control
registers mapped in the Special Function Register (SFR) area.
30H
2FH
BIT-ADDRESSABLE SPACE
(BIT ADDRESSES 0–7FH)
BANKS
SELECTED
VIA
20H
18H
10H
BITS IN PSW
1FH
17H
0FH
07H
11
10
01
00
PROGRAM MEMORY SPACE
READ ONLY
FFFFFFH
4 BANKS OF 8 REGISTERS
R0–R7
EXTERNAL
PROGRAM
MEMORY
SPACE
08H
00H
RESET VALUE OF
STACK POINTER
Figure 2. Lower 128 Bytes of Internal RAM
2000H
8K BYTE
ELECTRICALLY
640-BYTE
REPROGRAMMABLE
ELECTRICALLY
NONVOLATILE
1FFFH
EA = 1
REPROGRAMMABLE
FLASH/EE PROGRAM
NONVOLATILE
EA = 0
EXTERNAL
PROGRAM
MEMORY
SPACE
INTERNAL
8K BYTE
MEMORY
FLASH/EE DATA
FLASH/EE
PROGRAM
MEMORY
MEMORY
0000H
128-BYTE
DATA MEMORY SPACE
READ/WRITE
SPECIAL
8051-
SELF-CALIBRATING
FUNCTION
COMPATIBLE
8-CHANNEL
REGISTER
CORE
HIGH SPEED
AREA
FFFFFFH
9FH
(PAGE 159)
12-BIT ADC
640 BYTES
FLASH/EE DATA
MEMORY
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
ACCESSED
INDIRECTLY
VIA SFR
CONTROL REGISTERS
2 ꢀ 12-BIT DACs
SERIAL I/O
PARALLEL I/O
WDT
00H
(PAGE 0)
PSM
EXTERNAL
DATA
INTERNAL
DATA MEMORY
SPACE
MEMORY
SPACE
Figure 3. ADuC812 Programming Model
(24-BIT
ADDRESS
SPACE)
FFH
SPECIAL
FUNCTION
REGISTERS
ACCESSIBLE
BY DIRECT
ADDRESSING
ONLY
FFH
ACCESSIBLE
ADC CIRCUIT INFORMATION
General Overview
BY
INDIRECT
ADDRESSING
ONLY
UPPER
128
The ADC conversion block incorporates a 5 µs, 8-channel,
12-bit, single supply A/D converter. This block provides the
user with multichannel mux, track/hold, on-chip reference,
calibration features and A/D converter. All components in this
block are easily configured via a 3-register SFR interface.
80H
80H
7FH
ACCESSIBLE
BY
LOWER
128
DIRECT
AND
INDIRECT
ADDRESSING
00H
000000H
The A/D converter consists of a conventional successive-
approximation converter based around a capacitor DAC. The
converter accepts an analog input range of 0 to +VREF. A high
precision, low drift and factory calibrated 2.5 V reference is
Figure 1. ADuC812 Program and Data Memory Maps
–8–
REV. 0
ADuC812
Table I. ADCCON1 SFR Bit Designations
provided on-chip. The internal reference may be overdriven via
the external VREF pin. This external reference can be in the
Bit
Location
Bit
range 2.3 V to AVDD
.
Mnemonic
Description
Single step or continuous conversion modes can be initiated in
software or, alternatively, by applying a convert signal to an
external Pin 25 (CONVST). Timer 2 can also be configured
to generate a repetitive trigger for ADC conversions. The ADC
may be configured to operate in a DMA Mode whereby the
ADC block continuously converts and captures samples to an
external RAM space without any interaction from the MCU
core. This automatic capture facility can extend through a
16 MByte external Data Memory space.
ADCCON1.7 MD1
ADCCON1.6 MD0
The mode bits (MD1, MD0)
select the active operating mode
of the ADC as follows:
MD1 MD0 Active Mode
0
0
1
0
1
0
ADC powered down.
ADC normal mode
ADC powered down
if not executing a
conversion cycle.
ADC standby if not
executing a conver-
sion cycle.
The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal Offset and Gain calibration registers, a
software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
users target system.
1
1
ADCCON1.5 CK1
ADCCON1.4 CK0
The ADC clock divide bits (CK1,
CK0) select the divide ratio for
the master clock used to generate
the ADC clock. An ADC con-
version will require 16 ADC
clocks in addition to the selected
number of acquisition clocks (see
AQ0/AQ1 below). The divider
ratio is selected as follows:
A voltage output from an on-chip temperature sensor propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexor (effectively a 9th ADC channel
input) facilitating a temperature sensor implementation.
CK1 CK0 MCLK Divider
ADC Transfer Function
0
0
1
1
0
1
0
1
1
2
4
8
The analog input range for the ADC is 0 V to VREF. For this
range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when
VREF = 2.5 V. The ideal input/output transfer characteristic for
the 0 to VREF range is shown in Figure 4.
ADCCON1.3 AQ1
ADCCON1.2 AQ0
The ADC acquisition select bits
(AQ1, AQ0) select the time avail-
able for the input track/hold
amplifier to acquire the input
signal and is selected as follows:
OUTPUT
CODE
111...111
111...110
111...101
AQ1 AQ0 #ADC Clks
0
0
1
1
0
1
0
1
1
2
3
4
111...100
FS
1LSB =
4096
Note: for analog input source
impedances of <8 kΩ, the default
AQ0/AQ1 selection of 00, i.e., 1
Acquisition Clock will suffice. For
source impedances greater than
this, it is recommended that you
increase the acquisition clock
selection to 2, 3 or 4 clocks.
000...011
000...010
000...001
000...000
0V 1LSB
+FS
–1LSB
VOLTAGE INPUT
ADCCON1.1 T2C
ADCCON1.0 EXC
The Timer 2 conversion bit (T2C)
is set to enable the Timer 2 over-
flow bit to be used as the ADC
convert start trigger input.
Figure 4. ADuC812 ADC Transfer Function
SFR Interface to ADC Block
The ADC operation is fully controlled via three SFRs, namely:
The external trigger enable bit
(EXC) is set to allow the external
Pin 23 (CONVST) to be used as
the active low convert start input.
This input should be an active low
pulse (100 ns minimum pulsewidth)
at the required sample rate.
ADCCON1 – (ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.
SFR Address:
EFH
SFR Power-On Default Value: 20H
Bit Addressable:
MD1 MD0 CK1
REV. 0
NO
Note: In standby mode the ADC VREF circuits are maintained on, while in
powered down mode all ADC peripherals are powered down thus minimizing
current consumption. Typical ADC current consumption is 1.6 mA at VDD = 5 V.
CK0
AQ1 AQ0 T2C
EXC
–9–
ADuC812
ADCCON2 – (ADC Control SFR #2)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
ADCCON3 – (ADC Control SFR #3)
The ADCCON3 register gives user software an indication of
ADC busy status.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
D8H
00H
YES
SFR Address:
SFR Power On Default Value:
Bit Addressable:
F5H
00H
NO
ADCI DMA CCONV SCONV CS3 CS2 CS1 CS0
Table II. ADCCON2 SFR Bit Designations
BUSY RSVD RSVD RSVD CTYP CAL1 CAL0 CALST
Table III. ADCCON3 SFR Bit Designations
Bit
Location
Bit
Mnemonic Description
Bit
Bit
Location
Mnemonic Description
ADCCON2.7 ADCI
The ADC interrupt bit (ADCI) is
set by hardware at the end of a
single ADC conversion cycle or at
the end of a DMA block conver-
sion. ADCI is cleared by hardware
when the PC vectors to the ADC
Interrupt Service Routine.
The DMA mode enable bit (DMA)
is set by the user to initiate a pre-
configured ADC DMA mode opera-
tion. A more detailed description of
this mode is given below.
The continuous conversion bit
(CCONV) is set by the user to
initiate the ADC into a continuous
mode of conversion. In this mode
the ADC starts converting based on
the timing and channel configura-
tion already set up in the ADCCON
SFRs, the ADC automatically starts
an other conversion once a previous
conversion cycle has completed.
The single conversion bit
(SCONV) is set by the user to
initiate a single conversion cycle.
The SCONV bit is automatically
reset to “0” on completion of the
single conversion cycle.
ADCCON3.7 BUSY
The ADC busy status bit (BUSY)
is a read-only status bit that is set
during a valid ADC conversion or
calibration cycle. Busy is auto-
matically cleared by the core at the
end of conversion or calibration.
ADCCON2.6 DMA
ADCCON3.6 RSVD
ADCCON3.5 RSVD
ADCCON3.4 RSVD
ADCCON3.3 RSVD
ADCCON3.2 RSVD
ADCCON3.1 RSVD
ADCCON3.0 RSVD
ADCCON3.0–3.6 are reserved
(RSVD) for internal use. These
bits will read as zero and should
only be written as zero by user
software.
ADCCON2.5 CCONV
ADC Internal Reference
If the internal reference is being used, both the VREF and CREF
pins should be decoupled with 100 nF capacitors to AGND.
These decoupling capacitors should be placed very close to the
VREF and CREF pins. For specified performance, it is recom-
mended that when using an external reference, this reference
ADCCON2.4 SCONV
should be between 2.3 V and the analog supply AVDD
.
If the internal reference is required for use external to the
MicroConverter, it should be buffered at the VREF pin and a
100 nF capacitor should be connected from this pin to AGND.
The internal 2.5 V is factory calibrated to an absolute accuracy
of 2.5 V ± 50 mV. It should also be noted that the internal VREF
will remain powered down until either of the DACs or the ADC
peripheral blocks are powered on by their respective enable bits.
ADCCON2.3 CS3
ADCCON2.2 CS2
ADCCON2.1 CS1
ADCCON2.0 CS0
The channel selection bits (CS3-0)
allow the user to program the
ADC channel selection under
software control. Once a conver-
sion is initiated the channel
converted will be that pointed to
by these channel selection bits. In
DMA mode the channel selection
is derived from the channel ID
written to the external memory.
Calibration
The ADC block also has four associated calibration SFRs.
These SFR’s drive calibration logic ensuring optimum perfor-
mance from the 12-bit ADC at all times. As part of the power-
on reset configuration, these SFRs are configured automatically
and transparently from factory programmed calibration con-
stants. In many applications use of factory programmed calibra-
tion constants will suffice; however, these calibration SFRs may
be overwritten by user code to further compensate for system-
dependent offset and gain errors.
CS3 CS2 CS1 CS0 CH#
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
X
0
1
2
3
4
5
6
7
Calibration Overview
The ADC block incorporates calibration hardware that ensures
optimum performance from the ADC at all times. The calibra-
tion modes are exercised as part of the ADuC812 internal factory
final test routines. The factory calibration results are stored in
Flash memory and are automatically downloaded on any power-
on-reset event to initialize the ADC calibration registers. In
Temp Sensor
Other
Combinations
DMA STOP
1
1
1
1
–10–
REV. 0
ADuC812
many applications this autocalibration download function suf-
fices. Alternatively, a device calibration can be easily initiated by
user software to compensate for significant changes in operating
conditions (CLK frequency, analog input range, reference volt-
age and supply voltages).
STOP COMMAND
1
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
00000AH
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
CONVERT ADC CH#3
CONVERT TEMP SENSOR
CONVERT ADC CH#5
This in-circuit software calibration feature allows the user to
remove various system and reference related errors (whether it
be internal or external reference) and to make use of the full
dynamic range of the ADC by adjusting the analog input range
of the part for a specific system. Contact Analog Devices, Inc.
for further details on the implementation of the software calibra-
tion routine in your applications.
0
0
000000H
1
CONVERT ADC CH#2
Figure 6. Typical DMA External Memory Preconfiguration
ADC MODES OF OPERATION
Typical Operation
The DMA Enable bit (ADCCON2.6, DMA) can now be set to
initiate the DMA conversion and transfer of the results sequen-
tially into external memory. Remember that the DMA mode
will only progress if the user has preconfigured the ADC
conversion time and trigger modes via the ADCCON1 and 2
SFRs. The end of DMA conversion is signified by the ADC
interrupt bit ADCCON2.7.
Once configured via the ADCCON 1-3 SFRs (shown previ-
ously) the ADC will convert the analog input and provide an
ADC 12-bit result word in the ADCDATAH/L SFRs. The top
four bits of the ADCDATAH SFR will be written with the
channel selection bits to identify the channel result. The format
of the ADC 12-bit result word is shown in Figure 5.
At the end of ADC DMA Mode, the external data memory
contains the new ADC conversion results as shown in Figure 7.
It should be noted that the channel selection bits are still present
in the result words to identify the individual conversion results.
ADCDATAH SFR
CH–ID
TOP 4 BITS
HIGH 4 BITS OF
ADC RESULT WORD
STOP COMMAND
1
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
1
1
0
1
0
00000AH
ADCDATAL SFR
NO CONVERSION
RESULT WRITTEN HERE
LOW 8 BITS OF THE
ADC RESULT WORD
CONVERSION RESULT
FOR ADC CH#3
Figure 5. ADC Result Format
CONVERSION RESULT
FOR TEMP SENSOR
0
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum speed
of one sample every 5 µs (i.e., 200 kHz sampling rate). Therefore,
in an interrupt driven routine the user software is required to ser-
vice the interrupt, read the ADC result and store the result for
further post processing, all within 5 µs otherwise the next ADC
sample could be lost. In applications where the ADuC812 can-
not sustain the interrupt rate, an ADC DMA Mode is provided.
CONVERSION RESULT
FOR ADC CH#5
0
CONVERSION RESULT
FOR ADC CH#2
000000H
1
Figure 7. Typical External Memory Configuration Post
ADC DMA Operation
Micro Operation during ADC DMA Mode
The ADC DMA Mode is enabled via the DMA enable bit
(ADCCON2.6), which allows the ADC to sample continuously
as per configuration in ADCCON SFRs. Each sample result is
written into an external Static RAM (mapped in the data memory
space) without any interaction from the ADuC812 core. This
mode ensures the ADuC812 can capture a contiguous sample
stream even at full speed ADC update rates.
During ADC DMA mode the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, it should be noted that MCU
core accesses to Ports 0 and 2 (which, of course, are being used
by the DMA controller) are gated “OFF” during ADC DMA
mode of operation. This means that even though the instruction
that accesses the external Ports 0 or 2 will appear to execute, no
data will be seen at these external port pins as a result.
Before enabling ADC DMA mode the user must first configure
the external SRAM to which the ADC samples will be written.
This consists of writing the required ADC DMA channels into
the channel ID bits (the top four bits) in the external SRAM. A
typical preconfiguration of external memory is shown in Figure 6.
The MicroConverter core is interrupted once the requested
block of DMA data has been captured and written to external
memory allowing the service routine for this interrupt to post-
process the data without any real time, timing constraints.
Once the external data memory has been preconfigured, the
DMA address pointer (DMAP, DMAH and DMAL) SFRs are
written. These SFRs should be written with the DMA start
address in external memory. In Figure 6, for example, the DMA
start address is 000000H. The 3-byte start address should be
written in the following order: DMAL, DMAH and DMAP.
The end of a DMA table is signified by writing “1111” into the
channel selection bits field.
SFR Interface to the DAC Block
The ADuC812 incorporates two 12-bit DACs on-chip. DAC
operation is controlled via a single control special function
register and four data special function registers, namely:
DAC0L/DAC1L – Contains the lower 8-bit DAC byte.
DAC0H/DAC1H – Contains the high 4-bit DAC byte.
DACCON
– Contains general purpose control bits
required for DAC0 and DAC1 operation.
REV. 0
–11–
ADuC812
In normal mode of operation each DAC is updated when the
low DAC nibble (DACxL) SFR is written. Both DACs can be
updated simultaneously using the SYNC bit in the DACCON
SFR.
NONVOLATILE FLASH MEMORY
Flash Memory Overview
The ADuC812 incorporates Flash memory technology on-chip
to provide the user with a nonvolatile, in-circuit reprogram-
mable, code and data memory space.
In 8-bit mode of operation, the 8-bit byte written to the DACxL
registers is automatically routed to the top 8 bits of each 12-bit
DAC. The bit designations of the DACCON SFR are shown
below in Table IV.
Flash memory is the newest type of nonvolatile memory
technology and is based on a single transistor cell architecture.
This technology is basically an outgrowth of EPROM
technology and was developed through the late 1980s.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
FDH
04H
NO
Flash memory takes the flexible in-circuit reprogrammable
features of EEPROM and combines them with the space
efficient/density features of EPROM (see Figure 8).
MODE RNG1 RNG0 CLR1 CLR0 SYNC PD1 PD0
Table IV. DACCON SFR Bit Designations
Because Flash technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Bit
Location
Bit
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must be erased first; the erase being
performed in sector blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Mnemonic Description
DACCON.7 MODE
The DAC MODE bit sets the
overriding operating mode for
both DACs.
Set to “1” = 8-bit mode (Write 8
bits to DACxL SFR.
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
Set to “0” = 12-bit mode.
IN-CIRCUIT
REPROGRAMMABLE
SPACE EFFICIENT/
DENSITY
DACCON.6 RNG1
DACCON.5 RNG0
DACCON.4 CLR1
DAC1 range select bit.
Set to “1” = DAC1 range 0–VDD
Set to “0” = DAC1 range 0–VREF
.
.
FLASH/EE MEMORY
TECHNOLOGY
DAC0 range select bit.
Set to “1” = DAC0 range 0–VDD
Set to “0” = DAC0 range 0–VREF
.
.
Figure 8. Flash Memory Development
Overall, Flash/EE memory represents a step closer towards
the ideal memory device that includes nonvolatility, in-circuit
programmability, high density and low cost. Incorporated in
the ADuC812, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
DAC1 clear bit.
Set to “0” = DAC1 output forced
to 0 V.
Set to “1” = DAC1 output
normal.
DACCON.3 CLR0
DACCON.2 SYNC
DAC0 clear bit.
Set to “0” = DAC0 output forced
to 0 V.
Flash/EE Memory and the ADuC812
The ADuC812 provides two arrays of Flash/EE memory for
user applications.
Set to “1” = DAC0 output normal.
8K bytes of Flash/EE Program space are provided on-chip to
facilitate code execution without any external discrete ROM
device requirements. The program memory can be programmed
using conventional third party memory programmers. This array
can also be programmed in-circuit, using the serial download
mode provided.
DAC0/1 update synchronization
bit.
When set to “1” the DAC outputs
update as soon as the DACxL
SFRs are written.
The user can simultaneously up-
date both DACs by first updating
the DACxL/H SFRs while SYNC
is “0.”
A 640-Byte Flash/EE Data Memory space is also provided on-
chip. This may be used by the user as a general purpose non-
volatile scratchpad area. User access to this area is via a group of
six SFRs. This space can be programmed at a byte level, al-
though it must first be erased in 4-byte sectors.
Both DACs will then update
simultaneously when the SYNC
bit is set to “1.”
Using the Flash/EE Program Memory
This 8K Byte Flash/EE Program Memory array is mapped
into the lower 8K bytes of the 64K bytes program space ad-
dressable by the ADuC812 and will be used to hold user code
in typical applications.
DACCON.1 PD1
DACCON.0 PD0
DAC1 Power-Down Bit.
Set to “1” = Power-On DAC1.
Set to “0” = Power-Off DAC1.
DAC0 Power-Down Bit.
Set to “1” = Power-On DAC0.
Set to “0” = Power-Off DAC0.
–12–
REV. 0
ADuC812
+5V
The program memory array can be programmed in one of two
modes, namely:
PROGRAM
DATA
V
DD
P0
P1
GND
(D0–D7)
Serial Downloading (In-Circuit Programming)
ADuC812
PROGRAM MODE
(SEE TABLE V)
As part of its factory boot code, the ADuC812 facilitates serial
code download via the standard UART serial port. Serial down-
load mode is automatically entered on power-up if the external
pin, PSEN, is pulled low through an external resistor as shown
in Figure 9. Once in this mode, the user can download code to
the program memory array while the device is sited in its target
application hardware. A PC serial download executable is pro-
vided as part of the ADuC812 QuickStart development system.
PROGRAM
ADDRESS
(A0–A13)
(P2.0 = A0)
(P1.7 = A13)
P3
GND
PSEN
P2
V
RST
DD
XTAL1
XTAL2
WRITE ENABLE
STROBE
ALE
Figure 10. Flash/EE Memory Parallel Programming
The Serial Download protocol is detailed in a MicroConverter
Applications Note available from ADI.
Table V shows the normal parallel programming modes that can
be configured using Port 3 bits.
Table V. Flash Memory Parallel Programing Modes
Port Pins
(P3.0–P3.7)
.7 .6 .5 .4 .3 .2 .1 .0 Programming Mode
1
1
X
X
X
X
X
X
0
0
0
0
0
1
1
1
Erase Flash Program
Erase Flash User
Read Manufacture and
Chip ID
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
Program Byte
Read Byte
Reserved
Reserved
PULL PSEN LOW DURING RESET TO
Any Other Code
Redundant
CONFIGURE THE ADuC812
FOR SERIAL DOWNLOAD MODE
ADuC812
Using the Flash/EE Data Memory
PSEN
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH), 4-byte pages as shown in
Figure 11.
1kꢃ
9FH
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 9. Flash/EE Memory Serial Download Mode
Programming
Parallel Programming
The parallel programming mode is fully compatible with con-
ventional third party Flash or EEPROM device programmers. A
block diagram of the external pin configuration required to
support parallel programming is shown in Figure 10. In this
mode Ports P0, P1 and P2 operate as the external data and
address bus interface, ALE operates as the Write Enable strobe
and Port P3 is used as a general configuration port that config-
ures the device for various program and erase operations during
parallel programming. The high voltage (12 V) supply required
for Flash programming is generated using on-chip charge pumps
to supply the high voltage program lines.
00H
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 11. User Flash/EE Memory Configuration
As with other user peripherals the interface to this memory
space is via a group of registers mapped in the SFR space. A
group of four data registers (EDATA1-4) are used to hold the
4-byte page data just accessed. EADRL is used to hold the 8-bit
address of the page to be accessed. Finally, ECON is an 8-bit
control register that may be written with one of five Flash/EE
memory access commands to enable various read, write, erase
and verify modes.
REV. 0
–13–
ADuC812
Flash/EE Memory Write and Erase Times
The typical program/erase times for the User Flash/EE Memory
are:
A block diagram of the SFR registered interface to the User
Flash/EE Memory array is shown in Figure 12.
Erase Full Array (640 Bytes) – 20 ms
Erase Single Page (4 Bytes) – 20 ms
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
FUNCTION:
HOLDS THE 4-BYTE
PAGE WORD
Program Page (4 Bytes)
Read Page (4 Bytes)
– 250 µs
– Within Single Instruction Cycle
9FH
BYTE 1 BYTE 2 BYTE 3 BYTE 4
Using the Flash/EE Memory Interface
As with all Flash/EE memory architectures, the array can be pro-
grammed in system at a byte level, although it must be erased
first; the erasure being performed in page blocks (4-byte pages
in this case).
EADRL
EDATA1 (BYTE 1)
EDATA2 (BYTE 2)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
A typical access to the Flash/EE array will involve setting up the
page address to be accessed in the EADRL SFR, configuring the
EDATA1-4 with data to be programmed to the array (the
EDATA SFRs will not be written for read accesses) and finally
writing the ECON command word which initiates one of the
five modes shown in Table VI.
00H
BYTE 1 BYTE 2 BYTE 3 BYTE 4
ECON COMMAND
INTERPRETER LOGIC
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
FUNCTION:
ECON
HOLDS COMMAND WORD
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. At
this time the core microcontroller operation on the ADuC812
is idled until the requested Program/Read or Erase mode is
completed.
Figure 12. User Flash/EE Memory Control and
Configuration
ECON—Flash/EE Memory Control SFR
This SFR acts as a command interpreter and may be written
with one of five command modes to enable various read, pro-
gram and erase cycles as detailed in Table VI:
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a 2 machine cycle
MOV instruction (to write to the ECON SFR), the next
instruction will not be executed until the Flash/EE operation
is complete (250 µs or 20 ms later). This means that the core
will not respond to Interrupt requests until the Flash/EE
operation is complete, although the core peripheral functions
like Counter/Timers will continue to count and time as configured
throughout this pseudo-idle period.
Table VI. ECON–Flash/EE Memory Control Register
Command Modes
Command Byte Command Mode
01H
READ COMMAND
Results in four bytes being read into
EDATA 1–4 from memory page location
contained in EADRL .
ERASE-ALL
Although the 640-byte User Flash/EE array is shipped from the
factory pre-erased, i.e., Byte locations set to FFH, it is nonethe-
less good programming practice to include an erase-all routine
as part of any configuration/setup code running on the ADuC812.
02H
WRITE COMMAND
Results in four bytes (EDATA 1–4) being
written to memory page location in EADRL.
This write command assumes the de-
signated “write” page has been pre-erased.
An “ERASE-ALL” command consists of writing “06H” to the
ECON SFR, which initiates an erase of all 640 byte locations in
the Flash/EE array. This command coded in 8051 assembly
would appear as:
03H
04H
RESERVED COMMAND
“DO NOT USE”
MOV ECON, #06H
; Erase all Command
; 20 ms Duration
VERIFY COMMAND
Allows the user to verify if data in EDATA
1–4 is contained in page location designated
by EADRL. A subsequent read of the
ECON SFR will result in a “zero” being
read if the verification is valid, a nonzero
value will be read to indicate an invalid
verification.
PROGRAM A BYTE
In general terms, a byte in the Flash/EE array can only be
programmed if it has previously been erased. To be more spe-
cific, a byte can only be programmed if it already holds the value
FFH. Because of the Flash/EE architecture this erasure must
happen at a page level, therefore a minimum of four bytes (1 page)
will be erased when an erase command is initiated.
05H
ERASE COMMAND
Results in an erase of the 4-byte page
designated in EADRL.
A more specific example of the Program-Byte process is shown
graphically in Figure 13. In this example the user will write F3H
into the second byte on Page 03H of the User Flash/EE Memory
space.
06H
ERASE-ALL COMMAND
Results in erase of the full user memory
160-page (640 bytes) array.
However, Page 03H already contains four bytes of valid data,
and as the user is only required to modify one of these bytes, the
full page must be first read so that this page can then be erased
without the existing data being lost.
07H to FFH
RESERVED COMMANDS
Commands reserved for future use.
–14–
REV. 0
ADuC812
The new byte is then written to the EDATA2 SFR, followed by
an ERASE cycle that will ensure this page is erased before the
new page data EDATA1-4 is written back into memory.
06H A5H 32H 05H 0DH
05H A5H 32H 05H 0DH
04H A5H 32H 05H 0DH
03H A5H 32H 05H 0DH
02H A5H 32H 05H 0DH
01H A5H 32H 05H 0DH
00H A5H 32H 05H 0DH
READ PAGE 03H
MOV EADRL, #03H ;SET P PAGE
POINTER
MOV ECON, #01H ;INITIATE READ
MODE
If the user attempts to initiate a PROGRAM cycle (ECON
set to 02H) without an ERASE cycle (ECON set to 05H),
then only bit locations set to a “1” would be modified, i.e., the
Flash/EE memory byte location must be pre-erased to allow a
valid write access to the array. It should also be noted that the
time durations for an ERASE-ALL command (640 bytes) and
that for an ERASE page command (four bytes) are identical,
i.e., 20 ms.
EDATA4
EDATA3
EDATA2
EDATA1
0DH
05H
32H
A5H
EDATA4
EDATA3
EDATA2
EDATA1
0DH
05H
F3H
A5H
WRITE NEW BYTE
TO EDATA2
MOV EDATA2, #0F3H ;WRITE NEW
BYTE
06H A5H 32H 05H 0DH
05H A5H 32H 05H 0DH
04H A5H 32H 05H 0DH
03H FFH FFH FFH FFH
02H A5H 32H 05H 0DH
01H A5H 32H 05H 0DH
00H A5H 32H 05H 0DH
This example coded in 8051 assembly would appear as :
ERASE
ERASE PAGE 03H
AND WRITE NEW DATA
TO PAGE 03H
MOV ECON, #05
MOV ECON, #02H ;PROGRAM
PAGE
MOV
MOV
MOV
MOV
MOV
EADRL, #03H
ECON, #01H
EDATA2, #0F3H
ECON, #02H
ECON, #05H
; Set Page Pointer
; Read Page Command
; Write New Byte
; Erase Page Command
; Program Page Command
EDATA4
EDATA3
EDATA2
EDATA1
0DH
05H
F3H
A5H
;ERASE PAGE
06H A5H 32H 05H 0DH
05H A5H 32H 05H 0DH
04H A5H 32H 05H 0DH
03H A5H 32H 05H 0DH
02H A5H F3H 05H 0DH
01H A5H 32H 05H 0DH
00H A5H 32H 05H 0DH
WRITE
INTERRUPT SYSTEM
The ADuC812 provides nine interrupt sources with two priority
levels. Interrupt priority within a given level is shown in de-
scending order of priority in Figure 14, which gives a general
overview of the interrupt sources and illustrates the request and
control flags. The interrupt vector addresses for corresponding
interrupts are also included in Table VII.
Figure 13. User Flash/EE Memory Program Byte Example
HIGH PRIORITY
POWER SUPPLY
PSMI
MONITOR
PSCON.5
EPSM
LOW PRIORITY
IE2.1
EXTERNAL INT0
P3.2
IE0
TCON.1
ITO
TCON.0
EX0
PX0
IP.0
IE1.0
END OF ADC
OR ADC DMA
ADCI
MODE CONVERSION
AC2.7
EADC
IE1.6
PADC
IP.6
TIMER 0
OVERFLOW
TF0
TCON.5
ET0
PT0
IP.1
IE1.1
EXTERNAL INT1
P3.3
IE1
TCON.3
IT1
EX1
PX1
IP.2
TCON.2
IE1.2
TIMER 1
OVERFLOW
TF1
TCON.7
ET1
PT1
IP.3
I2CCON.0
IE1.3
I2CI
SPI/I2C
PORT
=1
=1
ISPI
ESI
PSI
SPICON.7
SCON.0
IE2.0
IP.7
RI
UART
TI
ES
IE1.4
PS
IP.4
SCON.1
T2CON.7
TIMER 2
TF2
OVERFLOW
=1
P1.1/T2EX
EXF2
ET2
PT2
IP.5
T2CON.6
EXEN.2
T2CON.3
IE1.5
Figure 14. Interrupt Request Sources
REV. 0
–15–
ADuC812
Table VII. Interrupt Vector Addresses
Bit
Bit
Location
Mnemonic Description
Interrupt Priority
Vector
Address
Within
Level
IE.1
ET0
The Timer 0 Overflow Interrupt
Enable bit (ET0) is set to “1” to
enable the Timer 0 interrupt.
Interrupt
Interrupt Name
PSMI
IE0
ADCI
TF0
IE1
TF1
Power Supply Monitor
External INT0
43H
03H
1
2
3
4
5
6
7
8
9
IE.0
EX0
The INT0 Interrupt Enable bit
(EX0) is set to “1” to enable the
external INT0 interrupt
End of ADC Conversion 33H
Timer 0 Overflow
External INT1
Timer 1 Overflow
Serial Interrupt
UART Interrupt
0BH
13H
1BH
3BH
23H
2BH
IE2 – (Interrupt Enable 2 SFR )
The IE2 register enables two additional interrupt sources.
I2CI/ISPI
RI/TI
TF2/EXF2 Timer 2 Interrupt
SFR Address:
SFR Power On Default Value:
Bit Addressable:
A9H
00H
NO
Use of Interrupts
To use any of the interrupts on the ADuC812, the following
three steps must be taken.
NU
NU
NU
NU
NU
NU
EPSM ESI
Table IX. Interrupt Enable 2 (IE2) SFR Bit Designations
1. Locate the interrupt service routine at the corresponding
Vector Address of that interrupt. See Table VII above.
Bit
Bit
2. Set the EA (enable all) bit in the IE SFR to “1.”
Location
Mnemonic
Description
3. Set the corresponding individual interrupt bit in the IE
or IE2 SFR to “1.”
IE2.7
IE2.6
IE2.5
IE2.4
IE2.3
IE2.2
IE2.1
NU
NU
NU
NU
NU
NU
EPSM
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
The Power Supply Monitor
Interrupt enable bit is set to “1”
to enable the PSM Interrupt.
The SPI/I2C Interrupt Enable bit
(ESI) is set to “1” to enable the
SPI or I2C interrupt.
Three SFRs are used to enable and set priority for the various
interrupts. The bit designations of these SFRs are shown in
Tables VIII, IX and X. It should be noted that while IE and IP
SFRs are bit addressable, IE2 is byte addressable only.
IE – (Interrupt Enable SFR)
The IE register enables the interrupt system and seven interrupt
sources.
IE2.0
ESI
SFR Address:
SFR Power On Default Value:
Bit Addressable:
A8H
00H
YES
IP – (Interrupt Priority SFR )
EA EADC ET2
ES
ET1
EX1
ET0
EX0
The IP register sets one of two main priority levels for the vari-
ous interrupt sources. Set the corresponding bit to “1” to con-
figure interrupt as high priority and to “0” to configure interrupt
as low priority.
Table VIII. Interrupt Enable (IE) SFR Bit Designations
Bit
Bit
SFR Address:
SFR Power On Default Value:
Bit Addressable:
B8H
00H
YES
Location
Mnemonic Description
IE.7
EA
The Global Interrupt Enable bit
(EA) must be set to “1” before any
interrupt source will be recognized
by the core. EA is set to “0” to dis-
able all interrupts.
The ADC Interrupt Enable bit
(EADC) is set to “1” to enable the
ADC interrupt.
The Timer 2 Overflow Interrupt
Enable bit (ET2) is set to “1” to
enable the Timer 2 interrupt.
The UART Serial Port Interrupt
Enable bit (ES) is set to “1” to en-
able the UART Serial Port Interrupt.
The Timer 1 Overflow Interrupt
Enable bit (ET1) is set to “1” to
enable the Timer 1 interrupt.
The INT1 Interrupt Enable bit
(EX1) is set to “1” to enable the
external INT1 interrupt.
PS1 PADC
PT2
PS
PT1
PX1 PT0
PX0
Table X. Interrupt Priority (IP) SFR Bit Designations
Bit
IE.6
IE.5
IE.4
IE.3
IE.2
EADC
ET2
ES
Bit
Location
Mnemonic Description
IP.7
IP.6
IP.5
IP.4
PSI
Sets SPI/I2C Interrupt Priority
PADC
PT2
PS
Sets ADC Interrupt Priority
Sets Timer 2 Interrupt Priority
Sets UART Serial Port Interrupt
Priority
IP.3
IP.2
PT1
PX1
Sets Timer 1 Interrupt Priority
Sets External INT1 Interrupt
Priority
ET1
EX1
IP.1
IP.0
PT0
PX0
Sets Timer 0 Interrupt Priority
Sets External INT0 Interrupt
Priority
–16–
REV. 0
ADuC812
ON-CHIP PERIPHERALS
In “Counter” function, the TLx register is incremented by a
1-to-0 transition at its corresponding external input pin, T0, T1
or T2.
The following sections give a brief overview of the various sec-
ondary peripherals also available on-chip. A quick reference to
the various SFR configuration registers used to control these
peripheral functions is given on the following pages.
ON-CHIP MONITORS
The ADuC812 integrates two on-chip monitor functions to
minimize code or data corruption during catastrophic program-
ming or other external system faults. Again, both monitor func-
tions are fully configurable via the SFR space.
PARALLEL I/O PORTS 0–3
The ADuC812 uses four general purpose data ports to exchange
data with external devices. In addition to performing general
purpose I/O, some ports are capable of external memory opera-
tions; others are multiplexed with an alternate function for the
peripheral features on the device. In general, when a peripheral
sharing a port pin is enabled, that pin may not be used as a
general purpose I/O pin.
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters an
erroneous state, possibly due to a programming error, electrical
noise or RFI. The Watchdog function can be permanently dis-
abled by clearing WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR. When enabled, the watchdog circuit
will generate a system reset if the user program fails to refresh
the watchdog within a predetermined amount of time. The
watchdog reset interval can be adjusted via the SFR prescale bits
from 16 to 204 ms.
Ports 0, 2 and 3 are bidirectional while Port 1 is an input only
port. All ports contain an output latch and input buffer, the I/O
Ports will also contain an output driver. Read and Write accesses
to Port 0–3 pins are performed via their corresponding special
function registers.
Port pins on Ports 0, 2 and 3 can be independently configured
as digital inputs or digital outputs via the corresponding port
SFR bits. Port 1 pins however, can be configured as digital
inputs or analog inputs only, Port 1 digital output capability is
not supported on this device.
POWER SUPPLY MONITOR
The Power Supply Monitor generates an interrupt when
the analog (AVDD) or digital (DVDD) power supplies to the
ADuC812 drop below one of five user-selectable voltage trip
points from 2.6 V to 4.6 V The interrupt bit will not be cleared
until the power supply has returned above the trip point for at
least 256 ms.
SERIAL I/O PORTS
UART Interface
The serial port is full duplex, meaning it can simultaneously
transmit and receive. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously re-
ceived byte has been read from the receive register. However, if
the first byte still hasn't been read by the time reception of the
second byte is complete, one of the bytes will be lost.
This monitor function ensures that the user can save working
registers to avoid possible data corruption due to the low supply
condition, and that code execution will not resume until a “safe”
supply level has been well established. The supply monitor is
also protected against spurious glitches triggering the interrupt
circuit.
The physical interface to the serial data network is via Pins
RxD(P3.0) and TxD(P3.1) and the serial port can be configured
into one of four modes of operation.
QuickStart DEVELOPMENT SYSTEM
The QuickStart Development System is a full featured, low cost
development tool suite supporting the ADuC812. The system
consists of the following PC-based (Win95-compatible) hard-
ware and software development tools.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously. The
system can be configured for Master or Slave operation.
Code Development: Full Assembler and C Compiler
(2K Code Limited)
Code Functionality: ADSIM812, Windows Code Simulator
Code Download: FLASH/EE UART-Serial Downloader
Code Debug: Serial Port Debugger
I2C-Compatible Serial Interface
The ADuC812 supports a 2-wire serial interface mode that is
I2C-compatible. This interface can be configured to be a Soft-
ware Master or Hardware Slave and is multiplexed with the SPI
serial interface port.
Misc: System includes CD-ROM documentation, power supply
and serial port cable.
TIMERS/COUNTERS
The ADuC812 has three 16-bit Timer/Counters, namely: Timer 0,
Timer 1 and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead
inherent in implementing timer/counter functionality in soft-
ware. Each Timer/Counter consists of two 8-bit registers THx
and TLx (x = 0, 1 and 2). All three can be configured to operate
either as timers or event counters.
In “Timer” function, the TLx register is incremented every
machine cycle. Thus one can think of it as counting machine
cycles. Since a machine cycle consists of 12 oscillator periods,
the maximum count rate is 1/12 of the oscillator frequency.
Figure 15. Typical QuickStart System Configuration
REV. 0
–17–
ADuC812
SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR)
area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on-
chip peripherals.
Figure 16 shows a full SFR memory map and SFR contents on Reset; NOT USED indicates unoccupied SFR locations. Unoccupied
locations in the SFR address space are not implemented; i.e., no register exists at this location. If an unoccupied location is read, an
unspecified value is returned. SFR locations reserved for on-chip testing are shaded (RESERVED) and should not be accessed by
user software.
SPICON1
DAC0L
DAC0H
DAC1L
DAC1H
DACCON
ISPI
FFH
WCOL
SPE
FDH
SP1M CPOL CPHA SPR1
SPR0
RESERVED NOT USED
BITS
0
0
0
0
0
0
0
FEH
0
0
0
0
0
FCH
0
0
0
0
FBH
0
FAH
0
F9H
0
F8H
0
F8H
00H F9H 00H FAH 00H FBH 00H FCH 00H FDH 04H
ADCOFSL3 ADCOFSH3 ADCGAINL3 ADCGAINH3 ADCCON3
B1
SPIDAT
RESERVED
BITS
BITS
F7H
MDO
F6H
0
0
0
F5H
MCO
F4H
F3H
0
F2H
F1H
0
F0H
0
0
0
0
0
F0H 00H F1H 00H F2H 20H F3H 00H F4H 00H F5H 00H
I2CCON1
F7H 00H
ADCCON1
MDE
EEH
MDI
ECH
I2CM I2CRS I2CTX
EBH
I2CI
E8H
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
EFH
EDH
0
0
0
0
0
EAH
E9H
0
0
0
0
EFH 20H
E8H 00H
ACC1
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
BITS
E7H
E6H
E5H
E4H
E3H
E2H
E1H
E0H
E0H
00H
ADCCON21 ADCDATAL ADCDATAH
PSMCON
DFH DCH
ADCI
DFH
DMA CCONV SCONV CS3
CS2
DAH
CS1
D9H
CS0
D8H
RESERVED RESERVED RESERVED RESERVED
DEH
0
0
0
DDH
0
DCH
0
DBH
D8H 00H D9H 00H DAH 00H
PSW1
D0H 00H
T2CON1
C8H 00H
WDCON1
C0H 00H
IP1
DMAL
D2H 00H D3H 00H D4H 00H
RCAP2L RCAP2H TL2
DMAH
DMAP
CY
D7H
AC
D6H
F0
D5H
RSI
D4H
RS0
D3H
OV
D2H
FI
D1H
P
D0H
RESERVED
RESERVED
RESERVED RESERVED RESERVED
0
0
TH2
TF2
CFH
EXF2
CEH
RCLK TCLK
CDH CCH
XEN
CBH
TR2
CAH
CNT2 CAP2
C9H
RESERVED RESERVED
0
0
0
C8H
0
CAH 00H CBH 00H CCH 00H CDH 00H
ETIM3
NOT
USED
C4H
EDARL
C6H 00H
EDATA3
PRE2
C7H
PRE1
PRE0
C5H
WDR1 WDR2 WDS
WDE
C0H
NOT USED
ECON
NOT USED
NOT USED
RESERVED
RESERVED
EDATA4
0
C6H
0
0
0
C3H
0
C2H
C1H
0
0
0
0
C4H C9H
EDATA1
ETIM1
ETIM2
EDATA2
PS1
BFH
PADC
PT2
BDH
PS
BCH
PT1
BBH
PX1
BAH
PT0
B9H
PX0
B8H
0
1
BEH
0
0
1
0
1
0
1
0
0
0
1
0
B8H 00H B9H 00H BAH 52H BBH 04H BCH 00H BDH 00H BEH 00H BFH 00H
P31
RD
B7H
WR
B6H
T1
B5H
T0
B4H
INT1
B3H
INT0
B2H
TxD
B1H
RxD
B0H
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
B0H FFH
IE1
IE2
EA
AFH
EADC
AEH
ET2
ADH
ES
ACH
ET1
ABH
EX1
AAH
ET0
A9H
EX0
A8H
NOT USED
NOT USED
NOT USED
A8H 00H A9H 00H
P21
NOT USED
NOT USED
I2CDAT
NOT USED
I2CADD
NOT USED
A7H
A6H
A5H
1
0
0
0
1
A4H
REN
A3H
A2H
1
0
0
0
1
A1H
A0H
A0H FFH
SCON1
SBUF
SM0
9FH
SM1
SM2
9DH
TB8
9BH
RB8
9AH
T1
99H
R1
98H
NOT USED
0
0
0
1
9EH
96H
0
9CH
98H 00H 99H 00H 9AH 00H 9BH 00H
P11, 2
SS/
95H
T2EX
91H
T2
90H
NOT USED
NOT USED
NOT USED
NOT USED
TH0
NOT USED
TH1
NOT USED
97H
0
0
1
94H
93H
92H
90H FFH
TCON1
TMOD
TL0
TL1
TF1
8FH
TR1
TF0
8DH
TR0
8CH
IE1
8BH
IT1
8AH
IE0
89H
IT0
88H
NOT USED
8EH
86H
88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 04H
P01
SP
DPL
DPH
DPP
PCON
RESERVED RESERVED
87H
85H
84H
83H
82H
81H
80H
80H FFH 81H 07H 82H 00H 83H 00H 84H 00H
87H 00H
SFR MAP KEY:
THESE BITS ARE CONTAINED IN THIS BYTE.
TCON
MNEMONIC
IT0
88H
MNEMONIC
SFR ADDRESS
IE0
89H
0
0
DEFAULT VALUE
88H 00H
DEFAULT VALUE
SFR ADDRESS
SFR NOTES:
1
2
SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT, THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT.
3
CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
Figure 16. Special Function Register Locations and Reset Values
–18–
REV. 0
ADuC812
DAC CONTROL REGISTER
DACCON
ADCCON3
ADC CONTROL REGISTER #3
ADC CONTROL REGISTER #1
ADCCON1
DACCON.7 MODESELECT (0 = 12 BIT, 1 = 8 BIT)
ADCCON3.7 BUSY INDICATOR FLAG
ADCCON1.7 ADC POWER CONTROL BITS
ADCCON1.6 [SHTDN, NORM, AUTOSHTDN,
AUTOSTBY]
ADCCON1.5 CONVERSION TIME = 16/ADCCLK
ADCCON1.4 ADCCLK = MCLK/[1, 2, 4, 8]
ADCCON1.3 ACQUISITION TIME SELECT BITS
ADCCON1.2 ACQ TIME = [1, 2, 3, 4]/ADCCLK
ADCCON1.1 TIMER2 CONVERT ENABLE
ADCCON1.0 EXTERNAL CONVST ENABLE
DACCON.6 DAC1 RANGE SELECT (0 = V
DACCON.5 DAC0 RANGE SELECT (0 = V
DACCON.4 CLEAR DAC1
, 1 = V
, 1 = V
)
)
REF
REF
DD
DD
(0 = ADC NOT ACTIVE)
ADCCON3.6 THIS BIT MUST CONTAIN ZERO
ADCCON3.5 THIS BIT MUST CONTAIN ZERO
ADCCON3.4 THIS BIT MUST CONTAIN ZERO
ADCCON3.3 THIS BIT MUST CONTAIN ZERO
ADCCON3.2 THIS BIT MUST CONTAIN ZERO
ADCCON3.1 THIS BIT MUST CONTAIN ZERO
ADCCON3.0 THIS BIT MUST CONTAIN ZERO
(0 = 0V, 1 = NORMAL OPERATION)
DACCON.3 CLEAR DAC0
(0 = 0V, 1 = NORMAL OPERATION)
DACCON.2 SYNCHRONOUS UPDATE
(1 = ASYNCHRONOUS)
DACCON.1 POWERDOWN DAC1 (0 = OFF, 1 = ON)
DACCON.0 POWERDOWN DAC0 (0 = OFF, 1 = ON)
ADCDATAH
ADC CONTROL REGISTER #2
ADC INTERRUPT FLAG
DMA MODE ENABLE
ADCCON2
ADCI
DMA
ADC DATA REGISTERS
ADCDATAL
DAC1H, DAC1L
DAC0H, DAC0L
DAC1 DATA REGISTERS
DAC0 DATA REGISTERS
DMA ADDRESS POINTER
DMAP, DMAH, DMAL
ADCGAINH
CCONV CONTINUOUS CONVERSION ENABLE BIT
SCONV SINGLE CONVERSION START BIT
ADC GAIN
ADCGAINL CALIBRATION COEFFICIENTS
CS3
CS2
CS1
CS0
INPUT CHANNEL SELECT BITS
0000–0111 = ADC0–ADC7
1XXX = TEMPERATURE SENSOR
1111 = "HALT" COMMAND
(IN DMA MODE ONLY)
ADCOFSH
ADCOFSL
ADC OFFSET
CALIBRATION COEFFICIENTS
Figure 17. ADC and DAC—Control and Configuration SFRs
P0
P1
PORT0 REGISTER (ALSO A0–A7 & D0–D7)
PORT1 REGISTER (ANALOG & DIGITAL INPUTS)
SBUF SERIAL PORT BUFFER REGISTER
PCON POWER CONTROL REGISTER
PCON.7 DOUBLE BAUD RATE CONTROL
PCON.4 ALE DISABLE
(0 = NORMAL, 1 = FORCES ALE HIGH)
PCON.3 GENERAL PURPOSE FLAG
PCON.2 GENERAL PURPOSE FLAG
PCON.1 POWER-DOWN CONTROL BIT
(RECOVERABLE WITH HARD RESET)
PCON.0 IDLE-MODE CONTROL
(RECOVERABLE WITH ENABLED
INTERRUPT)
WDCON WATCHDOG TIME
CONTROL REGISTER
PRE2 WATCHDOG TIMEOUT SELECTION BITS
PRE1 TIMEOUT = [16, 32, 64, 128, 256, 512, 1024,
PRE0 2048] ms
WDR1 WATCHDOG TIMER REFRESH BITS
WDR2 SET SEQUENTIALLY TO REFRESH
WATCHDOG
WDS WATCHDOG STATUS FLAG
WDE WATCHDOG ENABLE
T2EX TIMER/COUNTER 2 CAPTURE/RELOAD TRIGGER
T2
TIMER/COUNTER 2 EXTERNAL INPUT
P2
PORT2 REGISTER (ALSO A8–A15 & A16–A23)
P3
RD
WR
T1
T0
INT1
INT0
TxD
RxD
PORT3 REGISTER
EXTERNAL DATA MEMORY READ STROBE
EXTERNAL DATA MEMORY WRITE STROBE
TIMER/COUNTER 1 EXTERNAL INPUT
TIMER/COUNTER 0 EXTERNAL INPUT
EXTERNAL INTERRUPT 1
EXTERNAL INTERRUPT 0
SERIAL PORT TRANSMIT DATA LINE
SERIAL PORT RECEIVE DATA LINE
PSMCON POWER SUPPLY MONITOR
CONTROL REGISTER
PSMCON.7 (NOT USED)
PSMCON.6 PSM STATUS BIT
(1 = NORMAL/0 = FAULT)
PSMCON.5 PSM INTERRUPT BIT
PSMCON.4 TRIP POINT SELECT BITS
PSMCON.3 [4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
PSMCON.2
PSMCON.1 AVDD/DVDD FAULT INDICATOR
(1 = ADD/0 = DVDD)
PSMCON.0 PSM POWERDOWN CONTROL
(1 = ON/0 = OFF)
PSW
PROGRAM STATUS WORD
CY
AC
F0
CARRY FLAG
AUXILIARY CARRY FLAG
GENERAL PURPOSE FLAG 0
REGISTER BANK SELECT
CONTROL BITS
SCON SERIAL COMMUNICATIONS CONTROL REGISTER
RS1
SM0
SM1
UART MODE CONTROL BITS BAUD RATE:
RS0
OV
F1
ACTIVE REGISTER BANK = [0, 1, 2, 3]
OVERFLOW FLAG
GENERAL PURPOSE FLAG 1
PARITY OF ACC
00 - 8 BIT SHIFT REGISTER
01 - 8 BIT UART
F
/12
OSC
TIMER OVERFLOW
RATE/32 (ꢀ2)
P
10 - 9 BIT UART
11 - 9 BIT UART
F
/64 (ꢀ2)
OSC
DPP
DATA POINTER PAGE
TIMER OVERFLOW
RATE/32 (ꢀ2)
DPH, DPL (DPTR) DATA POINTER
SM2
IN MODES 2&3, ENABLES MULTIPROCESSOR
COMMUNICATION
ECON DATA FLASH MEMORY
COMMAND REGISTER
ACC
B
ACCUMULATOR
REN
TB8
RB8
TI
RECEIVE ENABLE CONTROL BIT
IN MODES 2&3, 9TH BIT TRANSMITTED
IN MODES 2&3, 9TH BIT RECEIVED
TRANSMIT INTERRUPT FLAG
01h READ
02h WRITE
04h VERIFY
05h ERASE
SP
STACK POINTER
03h (RESERVED) 06h ERASE ALL
RI
RECEIVE INTERRUPT FLAG
EADRL DATA FLASH MEMORY
ADDRESS REGISTER
EDATA1, EDATA2, EDATA3, EDATA4
DATA FLASH DATA REGISTERS
ETIM1, ETIM2, ETIM3
FLASH TIMING REGISTERS
Figure 18. 8051 Core, On-Chip Monitors and Flash/EE Data Memory SFRs
REV. 0
–19–
ADuC812
IE
EA
INTERRUPT ENABLE REGISTER #1
TCON
TF1
TIMER CONTROL REGISTER
SPICON SPI CONTROL REGISTER
ENABLE INTURRUPTS
(0 = ALL INTERRUPTS DISABLED)
ISPI
SPI INTERRUPT
TIMER1 OVERFLOW FLAG
(SET AT END OF SPI TRANSFER)
(AUTO CLEARED ON VECTOR TO ISR)
TIMER1 RUN CONTROL (0 = OFF, 1 = RUN)
TIMER0 OVERFLOW FLAG
EADC ENABLE ADCI (ADC INTERRUPT)
ET2
WCOL WRITE COLLISION ERROR FLAG
SPE
TR1
TF0
ENABLE TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
ENABLE RI/TI (SERIAL PORT INTERRUPT)
ENABLE TF1 (TIMER1 OVERFLOW INTERRUPT)
ENABLE IE1 (EXTERNAL INTERRUPT 1)
ENABLE TFO (TIMER0 OVERFLOW INTERRUPT)
ENABLE IE0 (EXTERNAL INTERRUPT 0)
SPI ENABLE
(0 = DISABLE, ALSO ENABLES SPI)
MASTER MODE SELECT (0 = SLAVE)
(AUTO CLEARED ON VECTOR TO ISR)
TIMER0 RUN CONTROL (0 = OFF, 1 = RUN)
EXTERNAL INT1 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE1 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
EXTERNAL INT0 FLAG
ES
SPIM
TR0
IE1
ET1
EX1
ET0
EX0
CPOL CLOCK POLARITY SELECT
(0 = SCLK IDLES LOW)
CPHA CLOCK PHASE SELECT
(0 = LEADING EDGE LATCH)
SPR1 SPI BITRATE SELECT BITS
IT1
IE0
(AUTO CLEARED ON VECTOR TO ISR)
IE0 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
IE2
INTERRUPT ENABLE REGISTER #2
SPR0 BITRATE = F
/ [4, 8, 32, 64]
IT0
OSC
IE2.1 ENABLE PSMI
(POWER SUPPLY MONITOR INTERRUPT)
IE2.0 ENABLE ISPI/I2CI
(SERIAL INTERFACE INTERRUPT)
TH0, TL0 TIMER0 REGISTERS
TH1, TL1 TIMER1 REGISTERS
SPIDAT
SPI DATA REGISTER
2
I2CCON I C CONTROL REGISTER
MDO
MDE
MASTER MODE SDATA OUTPUT BIT
MASTER MODE SDATA OUTPUT
ENABLE
MASTER MODE SCLK BIT
MASTER MODE SDATA INPUT BIT
MASTER MODE SELECT
T2CON
TF2
EXF2
TIMER2 CONTROL REGISTER
OVERFLOW FLAG
EXTERNAL FLAG
IP
PSI
INTERRUPT PRIORITY REGISTER
PRIORITY OF ISI/ISPI
(SERIAL INTERFACE INTERRUPT)
MCO
MDI
RCLK RECEIVE CLOCK ENABLE
(0 = TIMER1 USED FOR RxD CLK)
TCLK TRANSMIT CLOCK ENABLE
(0 = TIMER1 USED FOR TxD CLK)
EXEN2 EXTERNAL ENABLE
PADC PRIORITY OF ADCI (ADC INTERRUPT)
PT2
2
PRIORITY OF TF2/EXF2
I CM
2
(TIMER2 OVERFLOW INTERRUPT)
PRIORITY OF RI/TI (SERIAL PORT INTERRUPT)
PRIORITY OF TF1
I CRS SERIAL PORT RESET
2
PS
PT1
I CTX TRANSMISSION DIRECTION STATUS
2
I CI
SERIAL INTERFACE INTERRUPT
(0 = IGNORE T2EX, 1 = CAP/RL)
RUN CONTROL (0 = STOP, 1 = RUN)
(TIMER1 OVERFLOW INTERRUPT)
PRIORITY OF IE1 (EXTERNAL INT1)
PRIORITY OF TF0
(TIMER0 OVERFLOW INTERRUPT)
PRIORITY OF IE0 (EXTERNAL INT0)
TR2
2
PX1
PT0
I2CADD
I2CDAT
I C ADDRESS REGISTER
CNT2 TIMER/COUNTER SELECT
(0 = TIMER, 1 = COUNTER)
2
I C DATA REGISTER
CAP2 CAPTURE/RELOAD SELECT
(0 = RELOAD, 1 = CAPTURE)
PX0
TMOD
TIMER MODE REGISTER
TH2, TL2 TIMER2 REGISTER
TMOD.3/.7 GATE CONTROL BIT (0 = IGNORE INTx)
TMOD.2/.6 COUNTER/TIMER SELECT BIT (0 = TIMER)
TMOD.1/.5 TIMER MODE SELECTON BITS
TMOD.0/.4 [13 BIT T, 16 BIT T/C, 8 BIT T/C RELOAD,
2 ꢀ 8 BIT T]
RCAP2H, RCAP2L TIMER2 CAPTURE/RELOAD
(UPPER NIBBLE = TIMER1, LOWER NIBBLE = TIMER2)
Figure 19. Interrupt, Timer, SPI and I2C Control SFRs
–20–
REV. 0
ADuC812
TIMING SPECIFICATIONS1, 2, 3
AVDD = DVDD = +3.0 V or 5.0 V ꢂ 10%. All specifications TA = TMIN to TMAX unless otherwise noted.
12 MHz
Typ
Variable Clock
Parameter
Min
Max
Min
Typ
Max
Units Figure
CLOCK INPUT (External Clock Driven XTAL1)
tCK
XTAL1 Period
83.33
62.5
20
20
1000
ns
ns
ns
ns
ns
µs
20
20
20
20
20
tCKL
tCKH
tCKR
tCKF
XTAL1 Width Low
XTAL1 Width High
XTAL1 Rise Time
XTAL1 Fall Time
ADuC812 Machine Cycle Time
20
20
20
20
20
20
4
tCYC
1
12tCK
NOTES
1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1 and VIL max for
a Logic 0.
2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs.
3CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted.
4ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.
tCKR
tCKH
tCKL
tCKF
tCK
Figure 20. XTAL 1 Input
V
– 0.5V
CC
V
– 0.1V
V
V
– 0.1V
– 0.1V
LOAD
LOAD
0.2V + 0.9V
TEST POINTS
TIMING
REFERENCE
POINTS
CC
V
V
LOAD
LOAD
0.2V – 0.1V
CC
V
+ 0.1V
LOAD
LOAD
0.45V
Figure 21. Timing Waveform Characteristics
REV. 0
–21–
ADuC812
12 MHz
Max
Variable Clock
Min Max
Parameter
Min
Units Figure
EXTERNAL PROGRAM MEMORY
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tPHAX
ALE Pulsewidth
127
43
53
2tCK – 40
tCK – 40
tCK – 30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
22
22
22
22
22
22
22
22
22
22
22
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
234
145
4tCK – 100
3tCK – 105
53
205
tCK – 30
3tCK – 45
PSEN Pulsewidth
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN Low to Address Float
Address Hold After PSEN High
0
0
0
0
59
312
25
tCK – 25
5tCK – 105
25
MCLK
tLHLL
ALE (O)
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN (O)
tPXIZ
tPLAZ
tLLAX
tPXIX
INSTRUCTION
(IN)
PCL (OUT)
PORT 0 (I/O)
PORT 2 (O)
tAVIV
tPHAX
PCH
Figure 22. External Program Memory Read Cycle
–22–
REV. 0
ADuC812
12 MHz
Min
Variable Clock
Parameter
Max
Min
Max
Units Figure
EXTERNAL DATA MEMORY READ CYCLE
tRLRH
tAVLL
tLLAX
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tRLAZ
tWHLH
RD Pulsewidth
400
43
48
6tCK – 100
tCK – 40
tCK – 35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
23
23
23
23
23
23
23
23
23
23
23
Address Valid After ALE Low
Address Hold After ALE Low
RD Low to Valid Data In
Data and Address Hold After RD
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
RD Low to Address Float
RD or WR High to ALE High
252
5tCK – 165
0
0
97
2tCK –70
517
585
300
8tCK – 150
9tCK – 165
3tCK + 50
200
203
3tCK – 50
4tCK – 130
0
123
0
43
tCK – 40
6tCK – 100
MCLK
ALE (O)
PSEN (O)
RD (O)
tWHLH
tLLDV
tLLWL
tRLRH
tAVWL
tRLDV
tRHDZ
tLLAX
tRHDX
tAVLL
tRLAZ
A0–A7 (OUT)
DATA (IN)
PORT 0 (I/O)
PORT 2 (O)
tAVDV
A16–A23
A8–A15
Figure 23. External Data Memory Read Cycle
REV. 0
–23–
ADuC812
12 MHz
Min
Variable Clock
Parameter
Max
Min
Max
Units Figure
EXTERNAL DATA MEMORY WRITE CYCLE
tWLWH
tAVLL
tLLAX
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tWHLH
WR Pulsewidth
400
43
48
200
203
33
433
33
6tCK – 100
tCK – 40
tCK – 35
3tCK – 50
4tCK – 130
tCK – 50
7tCK – 150
tCK – 50
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
24
24
24
24
24
24
24
24
Address Valid After ALE Low
Address Hold After ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup Before WR
300
123
3tCK + 50
Data and Address Hold After WR
RD or WR High to ALE High
43
tCK – 40
6tCK – 100
MCLK
ALE (O)
PSEN (O)
WR (O)
tWHLH
tLLWL
tWLWH
tAVWL
tLLAX
tQVWX
tWHQX
tAVLL
tQVWH
DATA
PORT 0 (O)
PORT 2 (O)
A0–A7
A16–A23
A8–A15
Figure 24. External Data Memory Write Cycle
–24–
REV. 0
ADuC812
12 MHz
Min Typ Max
Variable Clock
Typ
Parameter
Min
Max
Units Figure
UART TIMING (Shift Register Mode)
tXLXL
tQVXH
tDVXH
tXHDX
tXHQX
Serial Port Clock Cycle Time
Output Data Setup to Clock
Input Data Setup to Clock
Input Data Hold After Clock
Output Data Hold After Clock
1.0
12tCK
µs
ns
ns
ns
ns
25
25
25
25
25
700
300
0
10tCK – 133
2tCK + 133
0
50
2tCK – 117
ALE (O)
tXLXL
TxD (OUTPUT CLOCK)
0
1
6
7
SET RI
OR
SET TI
tQVXH
tXHQX
MSB
BIT6
BIT1
LSB
RxD (OUTPUT DATA)
RxD (INPUT DATA)
tDVXH
tXHDX
MSB
BIT6
BIT1
LSB
Figure 25. UART Timing in Shift Register Mode
REV. 0
–25–
ADuC812
Parameter
Min
Max
Units
Figure
I2C COMPATIBLE INTERFACE TIMING
tL
tH
SCLOCK Low Pulsewidth
4.7
4.0
0.6
100
0
µs
µs
µs
ns
µs
µs
µs
26
26
26
26
26
26
26
SCLOCK High Pulsewidth
Start Condition Hold Time
Data Setup Time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
Data Hold Time
0.9
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time Between a STOP
Condition and a START Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulsewidth of Spike Suppressed
0.6
0.6
1.3
µs
ns
ns
ns
26
26
26
26
tR
tF
tSUP
300
300
50
1
NOTE
1Input filtering on both the SCLOCK and SDATA inputs suppress noise spikes which are less than 50 ns.
tBUF
tSUP
tR
SDATA (I/O)
MSB
LSB
ACK
MSB
tDSU
tDSU
tSHD
tDHD
tDHD
tRSU
tR
tH
tPSU
SCLK (I)
1
2-7
8
9
1
P
S
S(R)
tF
tSUP
tL
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 26. I2C-Compatible Interface Timing
–26–
REV. 0
ADuC812
Parameter
Min
Typ
Max
Units
Figure
SPI MASTER MODE TIMING (CPHA = 1)
tSL
tSH
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
330
330
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
27
27
27
27
27
27
27
27
tDAV
tDSU
tDHD
tDF
tDR
tSR
50
100
100
10
10
10
10
25
25
25
25
tSF
SCLOCK
(CPOL=0)
tSL
tSH
tSR
tSF
SCLOCK
(CPOL=1)
tDAV
tDR
tDF
LSB
MSB
BIT 6 – 1
MOSI
MISO
LSB IN
MSB IN
BIT 6 – 1
tDHD
tDSU
Figure 27. SPI Master Mode Timing (CPHA = 1)
REV. 0
–27–
ADuC812
Parameter
Min
Typ
Max
Units
Figure
SPI MASTER MODE TIMING (CPHA = 0)
tSL
tSH
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
330
330
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28
28
28
28
28
28
28
28
28
28
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Data Output Valid After SCLOCK Edge
Data Output Setup Before SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
50
150
100
100
10
10
10
10
25
25
25
25
SCLOCK
(CPOL=0)
tSL
tSH
tSF
tSR
SCLOCK
(CPOL=1)
tDAV
tDF
tDOSU
tDR
MSB
BIT 6 – 1
BIT 6 – 1
LSB
MOSI
MISO
MSB IN
LSB IN
tDSU tDHD
Figure 28. SPI Master Mode Timing (CPHA = 0)
–28–
REV. 0
ADuC812
Parameter
Min
Typ
Max
Units
Figure
SPI SLAVE MODE TIMING (CPHA = 1)
tSS
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
29
29
29
29
29
29
29
29
29
29
330
330
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SS High After SCLOCK Edge
50
100
100
10
10
10
10
25
25
25
25
tSF
tSFS
0
SS
tSFS
tSS
SCLOCK
(CPOL=0)
tSL
tSH
tSF
tSR
SCLOCK
(CPOL=1)
tDAV
tDR
tDF
MISO
MOSI
LSB
MSB
BIT 6 – 1
LSB IN
MSB IN
BIT 6 – 1
tDSU
tDHD
Figure 29. SPI Slave Mode Timing (CPHA = 1)
REV. 0
–29–
ADuC812
Parameter
Min
Typ
Max
Units
Figure
SPI SLAVE MODE TIMING (CPHA = 0)
tSS
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
30
30
30
30
30
30
30
30
30
30
330
330
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
Data Output Valid After SS Edge
SS High After SCLOCK Edge
50
100
100
10
10
10
10
25
25
25
25
20
tSF
tDOSS
tSFS
SS
tSFS
tSS
SCLOCK
(CPOL=0)
tSH
tSL
tSR
tSF
SCLOCK
(CPOL=1)
tDAV
tDOSS
tDF
tDR
MSB
BIT 6 – 1
BIT 6 – 1
LSB
MISO
MOSI
MSB IN
LSB IN
tDSU tDHD
Figure 30. SPI Slave Mode Timing (CPHA = 0)
–30–
REV. 0
ADuC812
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead Plastic Quad Flatpack
(S-52)
0.557 (14.15)
0.094 (2.39)
0.537 (13.65)
0.398 (10.11)
0.084 (2.13)
0.390 (9.91)
0.037 (0.95)
0.026 (0.65)
52
1
40
39
PIN 1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.012 (0.30)
0.006 (0.15)
0.008 (0.20)
0.006 (0.15)
13
14
27
26
0.014 (0.35)
0.010 (0.25)
0.0256
(0.65)
BSC
0.082 (2.09)
0.078 (1.97)
REV. 0
–31–
相关型号:
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8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PDSO28, 4.40 X 9.70 MM, MO-153AE, TSSOP-28
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