ADUC814_02_技术文档

MicroConverter^®, Small Package

a

12-Bit ADC with Embedded FLASH MCU

ADuC814

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Analog I/O

6-Channel 247 kSPS ADC

ADuC814

AIN0

12-Bit Resolution

BUF

DAC0

DAC1

DAC0

DAC1

ADC

CONTROL

LOGIC

DAC

CONTROL

LOGIC

12-BIT

ADC

AIN

MUX

T/H

ADC High Speed Data Capture Mode

Programmable Reference via On-Chip DAC for Low

Level Inputs

ADC Performance Down to V_REFof 0.1 V

Dual-Voltage Output DACs

AIN5

TEMP

MONITOR

12-Bit Resolution, 15 ␮s Settling Time

Memory

8 KBytes On-Chip Flash/EE Program Memory

640 Bytes On-Chip Flash/EE Data Memory

Flash/EE, 100-Year Retention, 100 K Cycles

Endurance

Three Levels of Flash/EE Program Memory Security

In-Circuit Serial Download (No External Hardware

Required)

8051-BASED MCU WITH ADDITIONAL

PERIPHERALS

POWER-

ON

RESET

INTERNAL

BAND GAP

VREF

8 KBYTES FLASH/EE PROGRAM MEMORY

640 BYTES FLASH/EE DATA MEMORY

256 BYTES USER RAM

PROG.

CLOCK

DIVIDER

3

؋

16-BIT

TIMER/COUNTERS

1

؋

WAKE-UP/RTC

TIMER

ON-CHIP MONITORS

POWER SUPPLY

MONITOR

VREF

CREF

BUF

WATCHDOG TIMER

OSC

AND

PLL

UART AND SPI

SERIAL I/O

10

؋

DIGITAL I/O PINS

256 Bytes On-Chip Data RAM

8051 Based Core

XTAL1 XTAL2

8051 Compatible Instruction Set

32 kHz External Crystal

On-Chip Programmable PLL (16.78 MHz Max)

Three 16-Bit Timer/Counters

11 Programmable I/O Lines

11 Interrupt Sources, Two Priority Levels

Power

Specified for 3 V and 5 V Operation

Normal: 3 mA @ 3 V (Core CLK = 2.1 MHz)

Power-Down: 15 ␮A at 3 V (32 kHz Running)

On-Chip Peripherals

GENERAL DESCRIPTION

The ADuC814 is a fully integrated 247 kSPS 12-bit data acquisi-

tion system incorporating a high performance multichannel ADC, an

8-bit MCU, and program/data Flash/EE memory on a single chip.

This low power device operates from a 32 kHz crystal with an

on-chip PLL generating a high frequency clock of 16.78 MHz.

This clock is in turn routed through a programmable clock divider

from which the MCU core clock operating frequency is generated.

The microcontroller core is an 8052 and is therefore 8051-

instruction-set compatible. 8 Kbytes of nonvolatile Flash/EE

program memory are provided on-chip. 640 bytes of nonvolatile

Flash/EE data memory and 256 bytes of RAM are also integrated

on-chip.

Power-On Reset Circuit (No Need for External

POR Device)

Temperature Monitor (؎1.5؇C)

Precision Voltage Reference

Time Interval Counter (Wake-Up/RTC Timer)

UART Serial I/O

The ADuC814 also incorporates additional analog functionality

with dual 12-bit DACs, a power supply monitor, and a band

gap reference.

SPI^®/I²C^®Compatible Serial I/O

Watchdog Timer (WDT) and Power Supply

Monitor (PSM)

On-chip factory firmware supports in-circuit serial download and

debug modes (via UART), as well as the single-pin emulation

mode via the DLOAD pin. The ADuC814 is supported by a

Package and Temperature Range

28-Lead TSSOP 4.4 mm

؋

9.7 mm Body Package

Fully Specified for –40؇C to +125؇C Operation

QuickStart

™ development system. This is a full featured low cost

system, consisting of PC-based (Windows^®compatible) hardware

and software development tools.

APPLICATIONS

The part operates from a single 3 V or 5 V supply over the

extended temperature range –40ЊC to +125ЊC. When operating

from 3 V supplies, the power dissipation for the part is below

10 mW. The ADuC814 is housed in a 28-lead TSSOP package.

Optical Networking—Laser Power Control

Base Station Systems—Power Amplifier Bias Control

Precision Instruments and Smart Sensors

Battery-Powered Systems and General Precision

System Monitors

MicroConverter is a registered trademark of Analog Devices, Inc.

SPI is a registered trademark of Motorola Inc.

I²C is a registered trademark of Phillips Corporation.

QuickStart is a trademark of Analog Devices, Inc.

Windows is a registered trademark of Microsoft Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADuC814–SPECIFICATIONS¹

(AV_DD= DV_DD= 2.7 V to 3.3 V or 4.5 V to 5.5 V. V_REF= 2.5 V Internal Reference.

XTAL1/XTAL2 = 32.768 kHz Crystal. All specifications T_MINto T_MAX, unless otherwise noted.)

Parameter

V_DD= 5 V

V_DD= 3 V

Unit

Test Conditions

ADC CHANNEL SPECIFICATIONS

A GRADE

DC ACCURACY^{2, 3}

Resolution

Integral Nonlinearity

f_SAMPLE= 147 kHz

12

2

1

4

2

12

2

1

4

2

2.5

5

Bits

LSB max

LSB typ

LSB max

LSB typ

2.5 V Internal Reference

Differential Nonlinearity

Integral Nonlinearity

Differential Nonlinearity

2.5

5

1 V External Reference

CALIBRATED ENDPOINT ERRORS^{4, 5}

Offset Error

Offset Error Match

Gain Error

5

1

5

1

5

1

5

1

LSB max

LSB typ

LSB max

LSB typ

Gain Error Match

DYNAMIC PERFORMANCE

f_IN= 10 kHz Sine Wave

f_SAMPLE= 147 kHz

Signal-to-Noise Ratio (SNR)⁶

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk⁷

62.5

–65

–80

62.5

–65

–80

dB typ

B GRADE

DC ACCURACY^{2, 3}

Resolution

Integral Nonlinearity

f_SAMPLE= 147 kHz

12

1

0.3

0.9

0.25

1.5

+1.5/–0.9

1

12

1

0.3

0.9

0.25

1.5

Bits

LSB max

LSB typ

LSB max

LSB typ

LSB max

LSB typ

2.5 V Internal Reference

Differential Nonlinearity

Integral Nonlinearity¹³

Differential Nonlinearity¹³

Code Distribution

1 V External Reference

ADC Input Is a DC Voltage

+1.5/–0.9

1

CALIBRATED ENDPOINT ERRORS^{4, 5}

Offset Error

Offset Error Match

Gain Error

2

1

2

1

3

1

3

1

LSB max

LSB typ

LSB max

LSB typ

Gain Error Match

DYNAMIC PERFORMANCE

f_IN= 10 kHz Sine Wave

f_SAMPLE= 147 kHz

Signal-to-Noise Ratio (SNR)⁶

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel-to-Channel Crosstalk⁷

71

dB typ

–85

–80

–85

–80

ANALOG INPUT

Input Voltage Ranges

Leakage Current

0 to V_REF

1

32

0 to V_REF

1

32

V

µA max

pF typ

Input Capacitance

TEMPERATURE MONITOR⁸

Voltage Output at 25°C

Voltage TC

Accuracy

650

–2

3

650

–2

3

mV typ

mV/°C typ

°C typ

Internal 2.5 V V_REF

External 2.5 V V_REF

1.5

°C typ

–2–

REV. 0

ADuC814

Parameter

V_DD= 5 V

V_DD= 3 V

Unit

Test Conditions

DAC CHANNEL SPECIFICATIONS

DAC Load to AGND

R_L= 10 kΩ, C_L= 100 pF

DC ACCURACY⁹

Resolution

12

3

–1

1/2

50

1

12

3

–1

1/2

50

1

Bits

Relative Accuracy

LSB typ

LSB max

LSB typ

mV max

% max

% typ

Differential Nonlinearity¹⁰

Guaranteed Monotonic

Offset Error

Gain Error

V_REFRange

AV_DDRange

1

Gain Error Mismatch

0.5

% typ

Of Full Scale on DAC1

ANALOG OUTPUTS

Voltage Range_0

Voltage Range_1

Output Impedance

I_SINK

0 to V_REF

0 to V_DD

0.5

0 to V_REF

0 to V_DD

0.5

V

DAC V_REF= 2.5 V

DAC V_REF= V_DD

Ω typ

µA typ

50

DAC AC SPECIFICATIONS

Voltage Output Settling Time

15

10

15

10

µs typ

Full-Scale Settling Time to

within 1/2 LSB of Final

Value

Digital-to-Analog Glitch Energy

nVs typ

1 LSB Change at Major Carry

REFERENCE INPUT/OUTPUT

REFERENCE OUTPUT¹¹

Output Voltage (V_REF

Accuracy

)

2.5

V

% max

Of V_REFMeasured at the

CREF Pin

Power Supply Rejection

47

57

dB typ

Reference Temperature Coefficient

Internal V_REFPower-On Time

100

80

100

80

ppm/ºC typ

ms typ

EXTERNAL REFERENCE INPUT¹²

13

Voltage Range (V_REF

)

0.1

V_DD

20

0.1

V_DD

20

V min

V max

kΩ typ

µA max

Input Impedance

Input Leakage

10

Internal Band Gap Deselected

via ADCCON2.6

POWER SUPPLY MONITOR (PSM)

_DDTrip Point Selection Range

V

2.63

2.93

3.08

4.63

2.63

2.93

3.08

4.63

V

Four Trip Points Selectable

in this Range Programmed

via TP1-0 in PSMCON

V_DDPower Supply Trip Point Accuracy

3.5

% max

WATCHDOG TIMER (WDT)¹³

Time-Out Period

0

ms min

ms max

Nine Time-Out Periods

Selectable in this Range

Programmed via PRE3-0 in

WDCON

2000

LOGIC INPUTS¹³

All Inputs Except SCLOCK, RESET,

and XTAL1

V_INL, Input Low Voltage

V_INH, Input High Voltage

0.8

2.0

0.4

2.0

V max

V min

REV. 0

–3–

ADuC814

SPECIFICATIONS (continued)

Parameter

V_DD= 5 V

V_DD= 3 V

Unit

Test Conditions

SCLOCK and RESET Only¹³

(Schmitt-Triggered Inputs)

V_T+

1.3

3.0

0.8

1.4

0.3

0.85

0.95

2.5

0.4

1.1

0.3

V min

V max

V min

V max

V min

V max

V_T–

V_T+– V_T–

0.85

INPUT CURRENTS

P1.2–P1.7, DLOAD

SCLOCK¹⁴

10

–10

–40

10

20

105

10

1

–180

–660

–360

–20

–75

–38

10

–3

–15

10

35

10

1

–70

–200

–100

–5

–25

–12

µA max

µA min

µA max

µA min

µA max

µA typ

µA min

µA max

µA typ

µA min

µA max

µA typ

V_IN= 0 V or V_DD

V_IN= 0 V, Internal Pull-Up

V

_IN= V_DD

RESET

V_IN= 0 V

V_IN= 5 V, 3 V Internal Pull-Down

V_IN= 5 V, 3 V

P1.0, P1.1, Port 3

(includes MISO, MOSI/SDATA, and SS)

V_IN= 2 V, V_DD= 5 V, 3 V

V_IN= 450 mV, V_DD= 5 V, 3 V

All Digital Inputs

INPUT CAPACITANCE

5

pF typ

CRYSTAL OSCILLATOR

(XTAL1 AND XTAL2)

Logic Inputs, XTAL1 Only

V_INLInput Low Voltage

0.8

3.5

18

0.4

2.5

18

V typ

pF typ

,

V_INHInput High Voltage

,

XTAL1 Input Capacitance

XTAL2 Output Capacitance

18

DIGITAL OUTPUTS

Output High Voltage (V_OH

)

2.4

V min

I_SOURCE= 1.6 mA

Output Low Voltage (V_OL

P1.0 and P1.1

SCLOCK, MISO, MOSI

All Other Outputs

)

0.4

V max

I_SINK= 10 mA, T_MAX= 85°C

I_SINK= 8 mA, T_MAX= 125°C

I_SINK= 4 mA

I

_SINK= 1.6 mA

MCU CORE CLOCK

MCU Clock Rate

131.1

16.78

131.1

16.78

kHz

MHz

Clock Rate Generated via

On-Chip PLL, Programmable

via CD2-0 in PLLCON

START-UP TIME

At Power-On

From Idle Mode

500

100

500

100

ms typ

␮s typ

From Power-Down Mode

OSC_PD Bit = 0 in

PLLCON SFR

Oscillator Running

Wake-Up with INT0 Interrupt

Wake-Up with SPI/I²C Interrupt

Wake-Up with TIC Interrupt

Wake-Up with External RESET

100

3

100

3

␮s typ

ms typ

–4–

REV. 0

ADuC814

Parameter

V_DD= 5 V

V_DD= 3 V

Unit

Test Conditions

START-UP TIME (continued)

Oscillator Powered Down¹⁵

OSC_PD Bit = 1 in PLLCON

Wake-Up with SPI/I²C Interrupt

Wake-Up with TIC Interrupt

150

3

400

3

ms typ

Wake-Up with External RESET

After External RESET in Normal Mode

After WDT Reset in Normal Mode

3

Controlled via WDCON

FLASH/EE MEMORY RELIABILITY

CHARACTERISTICS¹⁶

Endurance¹⁷

100,000

100

100,000

100

cycles min

years min

Data Retention¹⁸

POWER REQUIREMENTS^{19, 20}

Power Supply Voltages

AV_DD/DV_DD– AGND

2.7

3.3

V min

V max

V min

V max

AV_DD/DV_DD= 3 V Nominal

AV_DD/DV_DD= 5 V Nominal

4.5

5.5

Power Supply Currents – Normal Mode

DV_DDCurrent¹³

5

2.5

mA max

Core CLK = 2.097 MHz

(CD Bits in PLLCON = 3)

4

1.7

20

2

mA typ

mA max

mA typ

mA max

mA typ

mA max

AV_DDCurrent¹³

DV_DDCurrent

1.7

10

8

1.7

1.5

1.2

1.7

Core CLK = 16.78 MHz (max)

(CD Bits in PLLCON = 0)

16

AV_DDCurrent

1.7

3.5

2.8

1.7

DV_DDCurrent¹³

Core CLK = 131.2 kHz (min)

(CD Bits in PLLCON = 7)

AV_DDCurrent

Power Supply Currents – Idle Mode

DV_DDCurrent¹³

1.7

1.2

mA max

Core CLK = 2.097 MHz

(CD Bits in PLLCON = 3)

1.5

0.15

6

1

0.15

3

2.5

0.15

1

0.7

0.15

mA typ

mA max

mA typ

mA max

mA typ

mA max

AV_DDCurrent¹³

DV_DDCurrent¹³

Core CLK = 16.78 MHz (max)

(CD Bits in PLLCON = 0)

4

AV_DDCurrent¹³

DV_DDCurrent¹³

0.15

1.25

1.1

0.15

Core CLK = 131 kHz (min)

(CD Bits in PLLCON = 7)

AV_DDCurrent¹³

Power Supply Currents – Power-Down Mode

Core CLK = 2.097 MHz or

16.78 MHz

(CD Bits in PLLCON = 3 or 0)

Oscillator ON

DV_DDCurrent¹³

20

14

1

15

10

1

µA max

µA typ

µA max

µA typ

40

1

AV_DDCurrent

DV_DDCurrent

Oscillator OFF

20

1

AV_DDCurrent

Typical Additional Power Supply Currents

Core CLK = 2.097 MHz,

(CD Bits in PLLCON = 3)

AV_DD= DV_DD= 5 V

PSM Peripheral

ADC

DAC

50

1.5

150

µA typ

mA typ

µA typ

REV. 0

–5–

ADuC814

SPECIFICATIONS (continued)

NOTES

¹Temperature range –40ºC to +125ºC.

²ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also

guaranteed during normal MicroConverter core operation.

³ADC LSB size = V_REF/2^12, i.e., for 2.5 V, 1 LSB = 610 µV and for External V_REF= 1 V, 1 LSB = 244 µV.

⁴Offset and gain error and offset and gain error match are measured after factory calibration.

⁵Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these

specifications.

⁶SNR calculation includes distortion and noise components.

⁷Channel-to-channel crosstalk is measured on adjacent channels.

⁸The temperature monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.

⁹DAC linearity is calculated using:

Reduced Code Range of 48 to 4095, 0 to V_REFRange.

Reduced Code Range of 48 to 3950, 0 to V_DDRange.

DAC output load = 10 kΩ and 100 pF.

¹⁰DAC differential nonlinearity specified on 0 to V_REFand 0 to V_DDranges.

¹¹Power-up time for the internal reference will be determined by the value of the decoupling capacitor chosen for both the VREF and CREF pins.

¹²When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the VREF and CREF

pins need to be shorted together for correct operation.

¹³These numbers are not production tested but are guaranteed by design and/or characterization data on production release.

¹⁴Pins configured in I²C compatible mode or SPI mode; pins configured as digital inputs during this test.

¹⁵These typical specifications assume no loading on the XTAL2 pin. Any additional loading on the XTAL2 pin will increase the power-on times.

¹⁶Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.

¹⁷Endurance is qualified to 100 Kcycles as per JEDEC STD. 22 method A117 and measured at –40ºC, +25ºC, and +125ºC; typical endurance at +25ºC is 700 Kcycles.

¹⁸Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC STD. 22 method A117. Retention lifetime based on an activation energy of 0.6e V

will derate with junction temperature.

¹⁹Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:

Normal Mode: Reset and all digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, and core executing internal software loop.

Idle Mode: Reset and all digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, PCON.0 = 1, and core execution suspended in idle mode.

Power-Down Mode: Reset and all other digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, PCON.1 = 1, core execution suspended in

Power-Down Mode, and OSC turned ON or OFF via OSC_PD Bit (PLLCON.7) in PLLCON SFR.

²⁰DV_DDpower supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.

Specifications subject to change without notice.

Purchase of licensed I²C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Phillips I²C

Patent Rights to use the ADuC814 in an I²C system, provided that the system conforms to the I²C standard specifications as defined by Phillips.

–6–

REV. 0

ADuC814

TIMING SPECIFICATIONS^{1, 2, 3}

(AV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V, DV_DD= 2.7 V to 3.6 V or 4.75 V to 5.25 V; all

specifications T_MINto T_MAX, unless otherwise noted.)

32.768 kHz External Crystal

Parameter

Min

Typ

Max

Unit

Figure

CLOCK INPUT (External Clock Driven XTAL1)

t_CK

t_CKL

XTAL1 Period

XTAL1 Width Low

XTAL1 Width High

XTAL1 Rise Time

30.52

15.16

20

µs

1

µs

t_CKH

t_CKR

t_CKF

1/t_CORE

t_CORE

t_CYC

µs

ns

MHz

µs

XTAL1 Fall Time

20

ADuC814 Core Clock Frequency⁴

ADuC814 Core Clock Period⁵

ADuC814 Machine Cycle Time⁶

0.131

0.72

16.78

91.55

0.476

5.7

NOTES

¹AC inputs during testing are driven at DV_DD– 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V_IHmin for a Logic 1, and V_ILmax

for a Logic 0, as shown in Figure 2.

²For timing purposes, a port pin is no longer floating when a 100 mV change from the load voltage occurs. A port pin begins to float when a 100 mV change from the

loaded V_OH/V_OLlevel occurs, as shown in Figure 2.

³CLOAD for all outputs = 80 pF, unless otherwise noted.

⁴ADuC814 internal PLL locks onto a multiple 512 times the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the

system. The core can operate at this frequency or at a binary submultiple called Core_CLK, selected via the PLLCON SFR.

⁵This number is measured at the default Core_CLK operating frequency of 2.09 MHz.

⁶ADuC814 machine cycle time is nominally defined as 12/Core_CLK.

t_CKR

t_CKH

t_CKL

t_CKF

t_CK

Figure 1. XTAL1 Input

DV – 0.5V

DD

V

– 0.1V

+ 0.1V

V

– 0.1V

0.2DV

+ 0.9V

LOAD

TIMING

REFERENCE

POINTS

DD

V

LOAD

TEST POINTS

0.2DV 0.1V

LOAD

–

DD

V

+ 0.1V

LOAD

0.45V

Figure 2. Timing Waveform Characteristics

REV. 0

–7–

ADuC814

TIMING SPECIFICATIONS(continued)

16.78 MHz Core_CLK

Variable Core_CLK

Typ

Parameter

Min

Typ

Max

Min

Max

Unit Figure

UART TIMING (Shift Register Mode)

t_XLXL

t_QVXH

t_DVXH

t_XHDX

t_XHQX

Serial Port Clock Cycle Time

Output Data Setup to Clock

Input Data Setup to Clock

Input Data Hold after Clock

Output Data Hold after Clock

715

12t_CORE

µs

ns

3

463

252

0

10t_CORE– 133

2t_CORE+ 133

0

22

2t_CORE– 117

t_XLXL

TXD

01

67

(OUTPUT CLOCK)

SET RI

OR

SET TI

t_QVXH

t_XHQX

RXD

MSB

BIT 6

BIT 1

(OUTPUT DATA)

t_DVXH

t_XHDX

RXD

(INPUT DATA)

MSB

BIT 6

BIT 1

LSB

Figure 3. UART Timing in Shift Register Mode

–8–

REV. 0

ADuC814

Parameter

Min

Typ

Max

Unit

Figure

SPI MASTER MODE TIMING (CPHA = 1)

t_SL

t_SH

SCLOCK Low Pulsewidth

SCLOCK High Pulsewidth

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

Data Output Rise Time

SCLOCK Rise Time

SCLOCK Fall Time

*

630

ns

4

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

50

100

10

25

t_SF

*

Characterized under the following conditions:

a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.

b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MOSI

MISO

BITS 6–1

MSB

LSB

MSB IN

LSB IN

t_DSU

t_DHD

Figure 4. SPI Master Mode Timing (CPHA = 1)

REV. 0

–9–

ADuC814

TIMING SPECIFICATIONS(continued)

Parameter

Min

Typ

Max

Unit

Figure

SPI MASTER MODE TIMING (CPHA = 0)

t_SL

SCLOCK Low Pulsewidth

*

630

ns

5

t_SH

SCLOCK High Pulsewidth

*

t_DAV

t_DOSU

t_DSU

t_DHD

t_DF

Data Output Valid after SCLOCK Edge

Data Output Setup before SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

50

150

100

10

25

t_DR

t_SR

Data Output Rise Time

SCLOCK Rise Time

t_SF

SCLOCK Fall Time

*

Characterized under the following conditions:

a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.

b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SR

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

t_DOSU

MOSI

MISO

MSB

BITS 6–1

LSB

MSB IN

BITS 6–1

LSB IN

t_DSUt_DHD

Figure 5. SPI Master Mode Timing (CPHA = 0)

–10–

REV. 0

ADuC814

Parameter

Min

Typ

Max

Unit

Figure

SPI SLAVE MODE TIMING (CPHA = 1)

t_SS

t_SL

SS to SCLOCK Edge

SCLOCK Low Pulsewidth

0

ns

6

330

t_SH

SCLOCK High Pulsewidth

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

Data Output Rise Time

SCLOCK Rise Time

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

50

100

10

25

t_SF

t_SFS

SCLOCK Fall Time

SS High after SCLOCK Edge

0

SS

t_SFS

t_SS

t_DF

SCLOCK

(CPOL = 0)

t_SL

t_SR

t_SH

t_SF

SCLOCK

(CPOL = 1)

t_DAV

t_DF

t_DR

MISO

BITS 6–1

MSB

LSB

BITS 6–1

LSB IN

MOSI

MSB IN

t_DHD

t_DSU

Figure 6. SPI Slave Mode Timing (CPHA = 1)

REV. 0

–11–

ADuC814

Parameter

Min

Typ

Max

Unit

Figure

SPI SLAVE MODE TIMING (CPHA = 0)

t_SS

t_SL

t_SH

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

SS to SCLOCK Edge

0

ns

7

SCLOCK Low Pulsewidth

SCLOCK High Pulsewidth

Data Output Valid after SCLOCK Edge

Data Input Setup Time before SCLOCK Edge

Data Input Hold Time after SCLOCK Edge

Data Output Fall Time

Data Output Rise Time

SCLOCK Rise Time

SCLOCK Fall Time

SS to SCLOCK Edge

330

50

100

10

25

50

20

t_SF

t_SSR

t_DOSS

t_SFS

Data Output Valid after SS Edge

SS High after SCLOCK Edge

0

SS

t_SFS

t_SS

SCLOCK

(CPOL = 0)

t_SH

t_SL

t_SF

t_SR

SCLOCK

(CPOL = 1)

t_DAV

t_DOSS

t_DF

t_DR

BITS 6–1

MSB

LSB

MISO

MOSI

BITS 6–1

MSB IN

LSB IN

t_DSU

t_DHD

Figure 7. SPI Slave Mode Timing (CPHA = 0)

–12–

REV. 0

ADuC814

ABSOLUTE MAXIMUM RATINGS¹

(T_A= 25°C, unless otherwise noted.)

PIN CONFIGURATION

28-Lead TSSOP

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND². . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND³. . . . –0.3 V to AV_DD+ 0.3 V

Reference Input Voltage to AGND . . –0.3 V to AV_DD+ 0.3 V

Analog Input Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA

Reference Input Current (Indefinite) . . . . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DGND

DV

DD

DLOAD

P3.0/RXD

P3.1/TXD

P3.2/INT0

P3.3/INT1

XTAL2

XTAL1

3

4

SCLOCK

5

P3.7/MOSI

P3.6/MISO

P3.5/T1/SS/EXTCLK

P1.7/ADC5/DAC1

P1.6/ADC4/DAC0

P1.5/ADC3

P1.4/ADC2

CREF

6

ADuC814

7

P3.4/T0/CONVST

P1.0/T2

TOP VIEW

8

(Not to Scale)

9

P1.1/T2EX

RESET

10

11

12

13

14

P1.2/ADC0

P1.3/ADC1

θ

_JAThermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9°C/W

AV

DD

VREF

Lead Temperature, Soldering

AGND

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

²AGND and DGND are shorted internally on the ADuC814.

³Applies to P1.2 to P1.7 pins operating in analog or digital input modes.

ORDERING GUIDE

Package

Temperature

Range

Package

Option

Model

Description

ADuC814ARU

ADuC814BRU

–40°C to +125°C

Thin Shrink Small Outline Package

RU-28

QuickStart Development System Model

Description

EVAL-ADuC814QS

Development System for the ADuC814 MicroConverter Contains:

• Evaluation Board

• Serial Port Cable

• Windows Serial Downloader (WSD)

• Windows Debugger (DeBug)

• Windows ADuC814 Simulator (ADSIM)

• Windows ADC Analysis Software Program (WASP)

• 8051 Assembler (Metalink)

• Example Code

• Documentation

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADuC814 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–13–

ADuC814

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Type*

Function

1

2

DGND

DLOAD

S

I

Digital Ground. Ground reference point for the digital circuitry.

Enables Debug/Serial Download Mode when pulled high through a resistor on power-on

or RESET. In this mode, DLOAD may also be used as an external emulation I/O pin,

and therefore, the voltage level at this pin must not be changed during this mode of

operation since it may cause an emulation interrupt that will halt code execution. User

code is executed when this pin is pulled low on power-on or RESET.

3-7

P3.0–P3.4

I/O

P3.0–P3.4 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have

1s written to them are pulled high by the internal pull-up resistors, and in that state, can

be used as inputs. As inputs, Port 3 pins being pulled externally low will source current

because of the internal pull-up resistors. When driving a 0-to-1 output transition, a

strong pull-up is active during S1 of the instruction cycle. Port 3 pins also have various

secondary functions that are described below.

3

4

5

P3.0/RXD

P3.1/TXD

P3.2/INT0

I/O

Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) in Serial

(UART) Mode

Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) in Serial

(UART) Mode

Interrupt 0 programmable edge or level triggered interrupt input, that can be

programmed to one of two priority levels. This pin can also be used as a gate control

input to Timer 0.

6

P3.3/INT1

I/O

Interrupt 1 programmable edge or level triggered interrupt input, that can be programmed

to one of two priority levels. This pin can also be used as a gate control input to Timer 1.

7

P3.4/T0/CONVST I/O

Timer/Counter 0 Input and External Trigger Input for ADC Conversion Start

8-9

P1.0–P1.1

I/O

P1.0–P1.1 are bidirectional port pins with internal pull-up resistors. Port 1 pins that have

1s written to them are pulled high by the internal pull-up resistors, and in that state,

can be used as inputs. As inputs, Port 1 pins being pulled externally low will source

current because of the internal pull-up resistors. When driving a 0-to-1 output transi-

tion, a strong pull-up is active during S1 of the instruction cycle. Port 1 pins also have

various secondary functions that are described below.

8

P1.0/T2

I/O

Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is

incremented in response to a 1 to 0 transition of the T2 input.

9

10

P1.1/T2EX

RESET

I/O

I

Digital Input. Capture/reload trigger for Counter 2.

Reset Input. A high level on this pin while the oscillator is running resets the device.

There is an internal weak pull-down and a Schmitt trigger input stage on this pin.

11-12

P1.2–P1.3

I

These pins have no digital output drivers, i.e., they can only function as digital inputs, for

which 0 must be written to the Port Bit. These port pins also have the following

analog functionality.

11

12

13

14, 15

P1.2/ADC0

P1.3/ADC1

AV_DD

I

S

G

ADC Input Channel 0, Selected via ADCCON2 SFR

ADC Input Channel 1, Selected via ADCCON2 SFR

Analog Positive Supply Voltage, 3 V or 5 V

AGND

Analog Ground. Ground reference point for the analog circuitry.

–14–

REV. 0

ADuC814

Pin No.

Mnemonic

Type*

Function

16

VREF

I/O

Reference Input/Output. This pin is connected to the internal reference through a switch

and is the reference source for the analog-to-digital converter. The nominal internal

reference voltage is 2.5 V, which appears at the pin. This pin can be used to connect

an external reference to the analog-to-digital converter by setting ADCCON1.6 to 1.0.

Connect 0.1 µF between this pin and AGND.

17

18-21

CREF

P1.4–P1.7

I

Decoupling input for on-chip reference. Connect 0.1 µF between this pin and AGND.

These pins have no digital output drivers, i.e., they can only function as digital inputs,

for which 0 must be written to the Port Bit. These port pins also have the following

analog functionality.

18

19

20

P1.4/ADC2

P1.5/ADC3

P1.6/ADC4/DAC0 I/O

I

ADC Input Channel 2, Selected via ADCCON2 SFR

ADC Input Channel 4, Selected via ADCCON2 SFR. The voltage DAC Channel 0 can

also be configured to appear on P1.6

21

P1.7/ADC5/DAC1 I/O

ADC Input Channel 5, Selected via ADCCON2 SFR. The voltage DAC Channel 1 can

also be configured to appear on P1.7

22-24

P3.5–P3.7

P3.5/T1

I/O

P3.5–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have

1s written to them are pulled high by the internal pull-up resistors, and in that state, can

be used as inputs. As inputs, Port 3 pins being pulled externally low will source current

because of the internal pull-up resistors. When driving a 0-to-1 output transition, a

strong pull-up is active during S1 of the instruction cycle. Port 3 pins also have various

secondary functions that are described below.

Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable

these functions, Bit 0 of the CFG814 SFR must be set to 1.

This pin also functions as the slave select input for the SPI interface when the device is

operated in Slave Mode. P3.5 can also function as an input for an external clock. This clock

effectively bypasses the PLL. This function is enabled by setting Bit 1 of the CFG814 SFR.

22

P3.5/SS/EXTCLK I/O

23

24

25

26

27

28

P3.6/MISO

P3.7/MOSI

SCLOCK

XTAL1

XTAL2

DV_DD

I/O

I

O

S

SPI Master Input/Slave Output Data Input/Output Pin

SPI Master Output/Slave Input Data Input/Output Pin

Serial Clock Pin for SPI Serial Interface Clock

Input to the Crystal Oscillator Inverter

Output from the Crystal Oscillator Inverter

Analog Positive Supply Voltage, 3 V or 5 V

*I = Input, O = Output, I/O = Input and Output, and S = Supply.

NOTES

1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state, unless otherwise stated.

2. SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC814 hardware, unless otherwise stated.

3. User software should not write 1s to Reserved or Unimplemented Bits as they may be used in future products.

REV. 0

–15–

ADuC814

OUTLINE DIMENSIONS

28-Lead TSSOP Package

(RU-28)

Dimensions shown in millimeters and (inches)

9.80 (0.386)

9.60 (0.378)

28

15

4.50 (0.177)

4.30 (0.169)

6.50 (0.256)

6.25 (0.246)

14

1

PIN 1

0.15 (0.006)

0.05 (0.002)

1.10 (0.0433)

MAX

8؇

0؇

0.65 (0.0256)

BSC

0.30 (0.0118)

0.19 (0.0075)

0.70 (0.028)

0.50 (0.020)

SEATING

PLANE

0.20 (0.0079)

0.090 (0.0035)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE

ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE

FOR USE IN DESIGN

REV. 0

–16–


型号：	ADUC814_02
厂家：	ADI
描述：	MicroConverter, Small Package 12-Bit ADC with Embedded FLASH MCU 微转换器，小型封装的12位ADC，带有嵌入式闪存微控制器转换器闪存微控制器
文件：	总16页 (文件大小：280K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUC814_02 [ADI]

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