ADUCM3027BCBZ-R7_技术文档

Ultra Low Power Arm Cortex-M3 MCU with

Integrated Power Management

ADuCM3027/ADuCM3029

Data Sheet

Digital peripherals

FEATURES

3 SPI interfaces to enable glueless interface to sensors,

radios, and converters

EEMBC ULPMark™-CP score: 245.5

Ultra low power active and hibernate mode

Active mode dynamic current: 30 μA/MHz (typical)

Flexi mode: 300 μA (typical)

I²C and UART interfaces

SPORT for natively interfacing with converters and radios

Programmable GPIOs (44 in LFCSP and 34 in WLCSP)

3 general-purpose timers with PWM support

RTC and FLEX_RTC with SensorStrobe and time stamping

Programmable beeper

25-channel DMA controller

Clocking features

26 MHz clock: on-chip oscillator, external crystal oscillator

32 kHz clock: on-chip oscillator, low power crystal oscillator

Integrated PLL with programmable divider

Analog peripherals

Hibernate mode: 750 nA (typical)

Shutdown mode: 60 nA (typical)

ARM Cortex-M3 processor with MPU

Up to 26 MHz with serial wire debug interface

Power management

Single-supply operation (V_BAT): 1.74 V to 3.6 V

Optional buck converter for improved efficiency

Memory options

128 kB/256 kB of embedded flash memory with ECC

4 kB of cache memory to reduce active power

64 kB of configurable system SRAM with parity up to 32 kB

of SRAM retained in hibernate mode

Safety

Watchdog with dedicated on-chip oscillator

Hardware CRC with programmable polynomial

Multiparity bit protected SRAM

ECC protected embedded flash

12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

APPLICATIONS

Internet of Things (IoT)

Electronic shelf label (ESL) and signage

Smart infrastructure

Smart lock

Asset tracking

Smart machine, smart metering, smart building, smart city,

and smart agriculture

Wearables

Fitness and clinical

Machine learning and neural network

Security

TRNG

User code protection

Hardware cryptographic accelerator supporting AES-128,

AES-256, and SHA-256

FUNCTIONAL BLOCK DIAGRAM

26MHz CORE RATE

PLL

SERIAL WIRE

INSTRUCTION

RAM/CACHE

(32kB)

HFXTAL

LFXTAL

HFOSC

LFOSC

ARM

CORTEX-M3

POWER

MANAGEMENT

FLASH

(256kB)

MULTI-

LAYER

AMBA

BUS

BUCK

SRAM0

(16kB)

NVIC

WIC

MATRIX

MPU

REF BUFFER

SRAM1

(16kB)

TEMPERATURE

SENSOR

DMA

CRYPTO

(AES 128/256,

SHA 256)

ADC

SPORT

UART

TMR0

TMR1

TRNG

RTC0

RTC1

AHB-APB

BRIDGE

2

PROGRAMMABLE

CRC POLYNOMIAL

SPI

I C

TMR2

BEEPER GPIO

WDT

Figure 1.

Rev. B

Document Feedback

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Technical Support

http://www.analog.com

ADuCM3027/ADuCM3029

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

ARM Cortex-M3 Processor...................................................... 22

Memory Architecture ................................................................ 23

Cache Controller ........................................................................ 24

System and Integration Features .............................................. 24

On-Chip Peripheral Features.................................................... 28

Development Support................................................................ 29

Additional Information ............................................................. 29

Reference Designs ...................................................................... 29

MCU Test Conditions................................................................ 29

Driver Types................................................................................ 29

EEMBC ULPMark™-CP Score.................................................. 30

GPIO Multiplexing......................................................................... 31

Applications Information.............................................................. 33

About ADuCM3027/ADuCM3029 Silicon Anomalies ............ 36

Functionality Issues.................................................................... 36

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 39

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Product Highlights....................................................................... 3

Specifications..................................................................................... 4

Operating Conditions and Electrical Characteristics.............. 4

Embedded Flash Specifications.................................................. 4

Power Supply Current Specifications......................................... 5

ADC Specifications ...................................................................... 7

System Clocks ............................................................................... 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

Typical Performance Characteristics ........................................... 20

Theory of Operation ...................................................................... 22

REVISION HISTORY

5/2019—Rev. A to Rev. B

Change to MMRs (Peripheral Control and Status) Section ..... 23

Changes to Cache Controller Section and Booting Section..... 24

Changes to Programmable GPIOs Section................................. 26

Changes to I²C Section .................................................................. 28

Changes to Additional Information Section............................... 29

Changes to Figure 26...................................................................... 33

Changes to Figure 27...................................................................... 34

Changes to Figure 28...................................................................... 35

Added About ADuCM3027/ADuCM3029 Silicon Anomalies

Section, Table 30, Table 31, and Table 32; Renumbered

Change to Features Section ............................................................. 1

Changes to General Description Section ...................................... 3

Change to VBAT_ADC Current (I_{VBAT_ADC}) Parameter ,Table 7.......7

Added Crystal Equivalent Series Resistance Parameter, Table 8 ..... 8

Change to SPT_CLK Period Parameter, Table 12 ........................ 9

Changes to Figure 5 and Figure 6................................................. 10

Changed Timer PWM_OUT Cycle Timing Section to Timer

Pulse-Width Modulation (PWM) Output Cycle

Timing Section................................................................................ 14

Change to Figure 13 Caption ........................................................ 14

Change to Table 19 ......................................................................... 15

Changes to Figure 14 and Table 20............................................... 16

Changes to Figure 15 and Table 21............................................... 18

Changes to Figure 16 to Figure 19................................................ 20

Changes to Figure 20 and Figure 21............................................. 21

Sequentially ..................................................................................... 36

Added Table 33 ............................................................................... 37

Changes to Ordering Guide.......................................................... 39

12/2018—Revision A: Initial Version

Rev. B | Page 2 of 39

Data Sheet

ADuCM3027/ADuCM3029

GENERAL DESCRIPTION

The ADuCM3027/ADuCM3029 microcontroller units (MCUs)

are ultra low power microcontroller systems with integrated

power management for processing, control, and connectivity.

The MCU system is based on the ARM® Cortex®-M3 processor,

a collection of digital peripherals, embedded SRAM and flash

memory, and an analog subsystem which provides clocking,

reset, and power management capability in addition to an

analog-to-digital converter (ADC) subsystem. For a feature

comparison across the ADuCM3027/ADuCM3029 product

offerings, see Table 1.

To support low dynamic and hibernate power management, the

ADuCM3027/ADuCM3029 MCUs provide a collection of

power modes and features, such as dynamic and software

controlled clock gating and power gating.

The ADuCM3029-1 and ADuCM3029-2 MCU models share the

same features and functionality as that of the ADuCM3029 MCU.

All specifications pertaining to the ADuCM3027 and

ADuCM3029 are also applicable to the ADuCM3029-1 and

ADuCM3029-2.

For full details on the ADuCM3027/ADuCM3029 MCUs, refer to

the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with

Integrated Power Management Hardware Reference Manual.

Table 1. Product Flash Memory Options

Device

Embedded Flash Memory Size

ADuCM3029

ADuCM3027

256 kB

128 kB

PRODUCT HIGHLIGHTS

1. Industry leading ultralow power consumption.

2. Robust operation, including full voltage monitoring in

deep sleep modes, ECC support on flash, and parity error

detection on SRAM memory.

System features that are common across the ADuCM3027/

ADuCM3029/ADuCM3029-1/ADuCM3029-2 MCUs include

the following:

3. Leading edge security. Fast encryption provides read

protection to customer algorithms. Write protection

prevents device reprogramming by unauthorized code.

4. Failure detection of 32 kHz LFXTAL via interrupt.

5. SensorStrobe™ for precise time synchronized sampling of

external sensors. Works in hibernate mode, resulting in

drastic current reduction in system solutions. Current

consumption reduces by 10 times when using, for example,

the ADXL363 accelerometer. Software intervention is not

required after setup. No pulse drift due to software execution.

•

Up to 26 MHz ARM Cortex-M3 processor

Up to 256 kB of embedded flash memory with error

correction code (ECC)

Optional 4 kB cache for lower active power

64 kB system SRAM with parity

Power management unit (PMU)

Multilayer advanced microcontroller bus architecture

(AMBA) bus matrix

•

Central direct memory access (DMA) controller

Beeper interface

Serial port (SPORT), serial peripheral interface (SPI),

inter-integrated circuit (I²C), and universal asynchronous

receiver/transmitter (UART) peripheral interfaces

Cryptographic hardware support with advanced encryption

standard (AES) and secure hash algorithm (SHA)-256

Real-time clock (RTC)

•

General-purpose and watchdog timers

Programmable general-purpose input/output (GPIO) pins

Hardware cyclic redundancy check (CRC) calculator with

programmable generator polynomial

•

Power-on reset (POR) and power supply monitor (PSM)

12-bit successive approximation register (SAR) ADC

True random number generator (TRNG)

Rev. B | Page 3 of 39

ADuCM3027/ADuCM3029

Data Sheet

SPECIFICATIONS

OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

EXTERNAL BATTERY SUPPLY VOLTAGE^{1, 2}

INPUT VOLTAGE

High Level

V_BAT

1.74

3.0

3.6

V

V_IH

V_IL

2.5

V

V_BAT= 3.6 V

V_BAT= 1.74 V

Low Level

0.45

3.6

ADC SUPPLY VOLTAGE

OUTPUT VOLTAGE³

High Level

V_{BAT_ADC}

1.74

1.4

3.0

V_OH

V_OL

V

V_BAT= 1.74 V, I_OH= −1.0 mA

V_BAT= 1.74 V, I_OL= 1.0 mA

Low Level

0.4

INPUT CURRENT PULL-UP⁴

High Level

Low Level

I_IHPU

I_ILPU

0.01

10

0.2

100

µA

V_BAT= 3.6 V, V_IN= 3.6 V

V_BAT=3.6 V, V_IN= 0 V

THREE-STATE LEAKAGE CURRENT

High Level⁵

I_OZH

0.15

0.30

100

0.15

100

0.15

µA

pF

°C

V_BAT= 3.6 V, V_IN= 3.6 V

V_BAT= 3.6 V, V_IN= 0 V

T_J= 25°C

Pull-Up⁶

I_OZHPU

I_OZHPD

I_OZL

I_OZLPU

I_OZLPD

C_IN

Pull-Down⁷

Low Level⁵

Pull-Up⁶

Pull-Down⁷

INPUT CAPACITANCE

JUNCTION TEMPERATURE

T_J

−40

+85

T_AMBIENT= -40°C to +85°C

¹Value applies to VBAT_ANA1, VBAT_ANA2, VBAT_DIG1, and VBAT_DIG2 pins.

²Must remain powered (even if the associated function is not used).

³Applies to the output and bidirectional pins: P0_00 to P0_15, P1_00 to P1_15, and P2_00 to P2_11.

4

SYS_HWRST

Applies to the

input pin with pull-up.

⁵Applies to the three-state pins: P0_00 to P0_05, P0_08 to P0_15, P1_00 to P1_15, and P2_00 to P2_11.

⁶Applies to the three-state pins with pull-ups: P0_00 to P0_05, P0_07 to P0_15, and P1_00 to P1_11.

⁷Applies to the P0_06 three-state pin with pull-down.

EMBEDDED FLASH SPECIFICATIONS

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

FLASH

Endurance

Data Retention

10,000

Cycles

Years

10

Rev. B | Page 4 of 39

Data Sheet

ADuCM3027/ADuCM3029

POWER SUPPLY CURRENT SPECIFICATIONS

Active Mode

Table 4.

Parameter

ACTIVE MODE³

Min Typ¹Max²Unit

Test Conditions/Comments

Current consumption when V_BAT= 3.0 V

Buck Enabled

0.40 2.71 mA

0.98 1.29 mA

1.28 1.64 mA

0.95 1.36 mA

1.08 1.43 mA

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 6.5 MHz

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz

Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz

Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz

Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

1.37 1.78 mA

1.08 1.49 mA

Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz

Dynamic Current

30

1.75 8.05 mA

2.34 3.0 mA

1.78 2.48 mA

1.99 2.67 mA

µA/MHz Code executing from flash, cache enabled

Code executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz

Code executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz

Code executing from SRAM, peripheral clocks off, HCLK = 26 MHz

Code executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

2.55 3.29 mA

Code executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz,

PCLK = 26 MHz

2.03 2.74 mA

Code executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz

60

µA/MHz Code executing from flash, cache enabled

¹T_J= 25°C.

²T_J= 85°C.

³The code being executed is a prime number generation in a continuous loop, with HFOSC as the system clock source.

Flexi Mode

Table 5.

Parameter

Min Typ¹Max²Unit

Test Conditions/Comments

Current consumption when V_BAT= 3.0 V

Peripheral clocks off

Peripheral clocks on, PCLK = 26 MHz

Peripheral clocks off

FLEXI™ MODE

Buck Enabled

0.3

0.39 0.80

0.52 1.11

0.67

mA

Buck Disabled

0.7

1.38

Peripheral clocks on, PCLK = 26 MHz

¹T_J= 25°C.

²T_J= 85°C.

Rev. B | Page 5 of 39

ADuCM3027/ADuCM3029

Data Sheet

Deep Sleep Modes—V_BAT= 3.0 V

Table 6.

Parameter

Min Typ

Max Unit Test Conditions/Comments

HIBERNATE MODE

T_J= 25°C

V_BAT= 3.0V

0.75

0.77

0.79

0.81

0.78

0.83

0.93

2.0

2.4

2.6

3.0

2.05

2.1

µA

RTC1 and RTC0 disabled, 8 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 24 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 32 kB SRAM retained, LFXTAL off

RTC1 enabled, 8 kB SRAM retained, LFOSC as source for RTC1

RTC1 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1

RTC1 and RTC0 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 and RTC0

RTC1 and RTC0 disabled, 8 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 24 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 32 kB SRAM retained, LFXTAL off

RTC1 enabled, 8 kB SRAM retained, LFOSC as source for RTC1

RTC1 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1

RTC1 and RTC0 enabled, 8 kB SRAM retained, LFXTAL as source for RTC1 and RTC0

V_BAT= 3.0 V

T_J= 85°C

6.05

6.4

6.75

7.1

6.1

6.15

6.3

2.25

SHUTDOWN MODE¹

T_J= 25°C

0.31

0.056

0.49

0.26

µA

1.180 µA

0.95 µA

RTC0 enabled, LFXTAL as source for RTC0

RTC0 disabled

RTC0 enabled, LFXTAL as source for RTC0

RTC0 disabled

T_J= 85°C

¹Buck enable/disable does not affect power consumption.

Rev. B | Page 6 of 39

Data Sheet

ADuCM3027/ADuCM3029

ADC SPECIFICATIONS

Table 7.

Parameter^{1, 2}

Min Typ³

Max

Unit

Test Conditions/Comments

±.8 V (V_BAT)/±.25 V (internal/external V_REF)

INTEGRAL NONLINEARITY ERROR

64-Lead LFCSP

4

±±.6

±±.4

±±.8

LSB

4

3.0 V (V_BAT)/2.5 V (internal/external V_REF)

54-Ball WLCSP

±.8 V (V_BAT)/±.25 V (internal/external V_REF

)

DIFFERENTIAL NONLINEARITY ERROR

64-Lead LFCSP

−0.7 to +±.±5

−0.7 to +±.±

−0.75 to +±.2

LSB

±.8 V (V_BAT)/±.25 V (internal/external V_REF

4

3.0 V (V_BAT)/2.5 V (internal/external V_REF)

54-Ball WLCSP

±.8 V (V_BAT)/±.25 V (internal/external V_REF)

OFFSET ERROR

64-Lead LFCSP

54-Ball WLCSP

4

±0.5

LSB

±.8 V (V_BAT)/±.25 V (external V_REF)

3.0 V (V_BAT)/2.5 V (external V_REF)

4

±.8 V (V_BAT)/±.25 V (external V_REF

)

GAIN ERROR

64-Lead LFCSP

54-Ball WLCSP

±2.5

±0.5

±3.0

LSB

±.8 V (V_BAT)/±.25 V (external V_REF

4

3.0 V (V_BAT)/2.5 V (external V_REF

)

±.8 V (V_BAT)/±.25 V (external V_REF

)

5

VBAT_ADC CURRENT (I_{VBAT_ADC}

64-Lead LFCSP

54-Ball WLCSP

)

6

±04

±3±

±08

±.25

2.50

μA

V

±.8 V (V_BAT)/±.25 V (internal V_REF)

6

3.0 V (V_BAT)/2.5 V (internal V_REF)

6

±.8 V (V_BAT)/±.25 V (internal V_REF)

INTERNAL REFERENCE VOLTAGE

Internal reference, ±.25 V selected

Internal reference, 2.5 V selected

V

INTEGRAL NONLINEARITY ERROR

64-Lead LFCSP

54-Ball WLCSP

±.22 ±.25

±.275

2.545

±.275

2.545

±.8

V

±.25 V (internal)⁷

2.5 V (internal)

±.25 V (internal)

2.5 V (internal)

2.45 2.5

±.22 ±.25

2.45 2.5

0.0±

ADC SAMPLING FREQUENCY (f_S)⁸

MSPS

^±The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs.

²The specifications are characterized after performing internal ADC offset calibration.

³T_J= 25°C.

⁴f_IN= ±068 Hz, f_S= ±00 kSPS, internal reference in low power mode, 400,000 samples end point method used.

⁵Current consumption from VBAT_ADC supply when ADC is performing the conversion.

⁶f_IN= ±068 Hz, f_S= ±00 kSPS, internal reference in low power mode.

⁷No load current, C_L= 0.± μF and 4.7 μF, reference buffer low power mode is enabled.

⁸Effects of analog source impedance must be considered when selecting ADC sampling frequency.

Rev. B | Page 7 of 39

ADuCM3027/ADuCM3029

Data Sheet

SYSTEM CLOCKS

External Crystal Oscillator Specifications

Table 8.

Parameter

Symbol

Min

6

Typ

Max

10

Unit

Test Conditions/Comments

LOW FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (LFXTAL)

Frequency

External Capacitance from

SYS_LFXTAL_IN Pin to Ground and

from SYS_LFXTAL_OUT Pin to Ground

f_LFXTAL

C_LFXTAL

32,768

Hz

pF

External capacitors on SYS_LFXTAL_IN

and SYS_LFXTAL_OUT pins must be

selected considering the printed circuit

board (PCB) trace capacitance due to

routing

Crystal Equivalent Series Resistance

ESR_LFXTAL

30

kΩ

HIGH FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (HFXTAL)

Frequency

External Capacitance from

SYS_HFXTAL_IN Pin to Ground and

from SYS_HFXTAL_OUT Pin to Ground

f_HFXTAL

C_HFXTAL

26

MHz

pF

20

50

External capacitors on SYS_HFXTAL_IN

and SYS_HFXTAL_OUT pins must be

selected considering the PCB trace

capacitance due to routing

Crystal Equivalent Series Resistance

ESR_HFXTAL

Ω

On-Chip RC Oscillator Specifications

Table 9.

Parameter

Symbol

f_LFOSC

f_HFOSC

Min

Typ

Max

Unit

Hz

LOW FREQUENCY RC OSCILLATOR (LFOSC)

Frequency

30,800

25.09

32,768

26

34,407

26.728

HIGH FREQUENCY RC OSCILLATOR (HFOSC)

Frequency

MHz

System Clocks and PLL Specifications

Table 10.

Parameter

Symbol

Min

Typ

Max

Unit

PLL SPECIFICATIONS

PLL Input Clock Frequency¹

PLL Output Clock Frequency^{2, 3}

System Peripheral Clock (PCLK) Frequency

f_PLLIN

f_PLLOUT

f_PCLK

16

0.8125

26

60

26

MHz

Advanced High Performance Bus Clock (HCLK) Frequency

f_HCLK

¹The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC).

²For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13, PLL_NSEL =

26, PLL_DIV2 = 1 for PLL input clock = 16 MHz.

³For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8, PLL_NSEL = 30,

PLL_DIV2 = 0 for 16 MHz.

Rev. B | Page 8 of 39

Data Sheet

ADuCM3027/ADuCM3029

TIMING SPECIFICATIONS

Reset Timing

Table 11.

Parameter

Symbol

Min

Typ

Max

Unit

RESET TIMING REQUIREMENTS

SYS_HWRST Asserted Pulse Width Low¹

t_WRST

4

µs

¹Applies after power-up sequence is complete.

t_WRST

SYS_HWRST

Figure 2. Reset Timing

Serial Ports Timing

Table 12.

Parameter

Symbol Min

Typ Max Unit Test Conditions/Comments

EXTERNAL CLOCK SERIAL PORTS

Timing Requirements

Frame Sync Setup Before SPT_CLK¹

t_SFSE

t_HFSE

5

ns

Externally generated frame sync

in transmit or receive mode

Externally generated frame sync

in transmit or receive mode

Frame Sync Hold After SPT_CLK¹

Receive Data Setup Before Receive SPT_CLK¹

Receive Data Hold After SPT_CLK¹

SPT_CLK Width²

t_SDRE

t_HDRE

t_SCLKW

t_SPTCLK

5

8

38.5

77

ns

SPT_CLK Period²

Switching Characteristics³

Frame Sync Delay After SPT_CLK

t_DFSE

20

ns

Internally generated frame sync in

transmit or receive mode

Internally generated frame sync in

transmit or receive mode

Frame Sync Hold After SPT_CLK

t_HOFSE

2

1

Transmit Data Delay After Transmit SPT_CLK

Transmit Data Hold After Transmit SPT_CLK

INTERNAL CLOCK SERIAL PORTS

Timing Requirements¹

t_DDTE

t_HDTE

ns

Receive Data Setup Before SPT_CLK

Receive Data Hold After SPT_CLK

Switching Characteristics

t_SDRI

t_HDRI

25

0

ns

Frame Sync Delay After SPT_CLK ³

t_DFSI

20

ns

Internally generated frame sync in

transmit or receive mode

Internally generated frame sync in

transmit or receive mode

Frame Sync Hold After SPT_CLK ³

t_HOFSI

−8

Transmit Data Delay After SPT_CLK³

Transmit Data Hold After SPT_CLK³

SPT_CLK Width

t_DDTI

t_HDTI

t_SCLKIW

t_SPTCLK

ns

−7

t_PCLK− 1.5

(2 × t_PCLK) − 1

SPT_CLK Period

Not shown in Figure 3 to Figure 7

ENABLE AND THREE-STATE SERIAL PORTS

Switching Characteristics

Data Enable from Internal Transmit SPT_CLK³

Data Disable from Internal Transmit SPT_CLK³

t_DDTIN

t_DDTTI

5

ns

160

¹This specification is referenced to the sample edge.

²This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK.

³These specifications are referenced to the drive edge.

Rev. B | Page 9 of 39

ADuCM3027/ADuCM3029

Data Sheet

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSI

t_HOFSI

SPT_0AFS/SPT_0BFS

(FRAME SYNC)

t_SDRI

t_HDRI

SPT_AD0/SPT_BD0

(DATA CHANNEL A/B)

Figure 3. Serial Ports (Data Receive Mode through Internal Clock)

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSI

t_HOFSI

SPT_0AFS/SPT_0BFS

(FRAME SYNC)

t_DDTI

t_HDTI

SPT_AD0/SPT_BD0

(DATA CHANNEL A/B)

Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)

DRIVE EDGE

SAMPLE EDGE

t_SCLKW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSE

t_HOFSE

t_SFSE

t_HFSE

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

t_SDRE

t_HDRE

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 5. Serial Ports (Data Receive Mode through External Clock)

DRIVE EDGE

SAMPLE EDGE

t_SCLKW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSE

t_HOFSE

t_SFSE

t_HFSE

SPT_0AFS/SPT_0BFS

(FRAME SYNC)

t_DDTE

t_HDTE

SPT_AD0/SPT_BD0

(DATA CHANNEL A/B)

Figure 6. Serial Ports (Data Transmit Mode through External Clock)

Rev. B | Page 10 of 39

Data Sheet

ADuCM3027/ADuCM3029

DRIVE EDGE

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK INTERNAL)

t_DDTIN

t_DDTTI

SPT0_AD0/SPT0/BD0

(DATA CHANNEL A/B)

Figure 7. Enable and Three-State Serial Ports

Rev. B | Page 11 of 39

ADuCM3027/ADuCM3029

Data Sheet

SPI Timing

Table 13.

Parameter¹

Symbol

Min

Typ

Max

Unit

SPI MASTER MODE TIMING

Timing Requirements

Chip Select (CS) to Serial Clock (SCLK) Edge

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_CS

(0.5 × t_PCLK) − 3

t_PCLK− 3.5

5

ns

t_SL

t_SH

t_DSU

t_DHD

20

Data Output Valid After SCLK Edge

Data Output Setup Before SCLK Edge

CS High After SCLK Edge

t_DAV

t_DOSU

t_SFS

25

ns

t_PCLK− 2.2

(0.5 × t_PCLK) − 3

SPI SLAVE MODE TIMING

Timing Requirements

CS to SCLK Edge

t_CS

38.5

6

ns

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_SL

t_SH

t_DSU

t_DHD

8

Data Output Valid After SCLK Edge

Data Output Valid After CS Edge

CS High After SCLK Edge

t_DAV

t_DOCS

t_SFS

20

ns

38.5

¹These specifications are characterized with respect to double drive strength.

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

BIT 6 TO BIT 1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 8. SPI Master Mode Timing (Phase Mode = 1)

Rev. B | Page 12 of 39

Data Sheet

ADuCM3027/ADuCM3029

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

t_DOSU

MOSI

MISO

MSB

BIT 6 TO BIT 1

LSB

BIT 6 TO

BIT 1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 9. SPI Master Mode Timing (Phase = 0)

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

MISO

MOSI

MSB

BIT 6 TO BIT 1

LSB

LSB IN

MSB IN

t_DSU

t_DHD

Figure 10. SPI Slave Mode Timing (Phase Mode = 1)

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

t_DOCS

MISO

MSB

BIT 6 TO BIT 1

LSB

LSB IN

MOSI

MSB IN

t_DSU

t_DHD

Figure 11. SPI Slave Mode Timing (Phase Mode = 0)

Rev. B | Page 13 of 39

ADuCM3027/ADuCM3029

Data Sheet

I²C Specifications

Table 14.

Parameter

Symbol

Min

Typ

Max

Unit

I²C SCLK FREQUENCY

Standard Mode

Fast Mode

100

400

kHz

General-Purpose Port Timing

Table 15.

Parameter

Symbol

Min

Typ

Unit

TIMING REQUIREMENTS

General-Purpose Port Pin Input Pulse Width

t_WFI

4 × t_PCLK

ns

t_WFI

GPIO INPUT

Figure 12. General-Purpose Timing

RTC1 (FLEX_RTC) Specifications

Table 16.

Parameter

Symbol

Min

Typ

Max

Unit

SENSORSTROBE

Minimum Output Frequency

Maximum Output Frequency

RTC1 ALARM

0.5

16.384

Hz

kHz

Minimum Time Resolution

30.52

µs

Timer Pulse-Width Modulation (PWM) Output Cycle Timing

Table 17.

Parameter

Symbol

Min

Typ

Max

256 × (216 − 1)

Unit

SWITCHING REQUIREMENTS

Timer Pulse Width Output

t_PWMO

(4 × t_PCLK) − 6

ns

PWM OUTPUTS

t_PWMO

Figure 13. Timer PWM Output Cycle Timing

Rev. B | Page 14 of 39

Data Sheet

ADuCM3027/ADuCM3029

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 18.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required. θ_JAcan be used for a first-order

approximation of T_Jby the following equation:

Parameter

Rating

Supply

VBAT_ANA1, VBAT_ANA2, VBAT_ADC, −0.3 V to +3.6 V

VBAT_DIG1, VBAT_DIG2, and

VREF_ADC

T_J= T_A+ (θ_JA× P_D)

Analog

where:

VDCDC_CAP1N, VDCDC_CAP1P,

VDCDC_OUT, VDCDC_CAP2N, and

VDCDC_CAP2P

VLDO_OUT, SYS_HFXTAL_IN, SYS_

HFXTAL_OUT, SYS_LFXTAL_IN, and

SYS_LFXTAL_OUT

−0.3 V to +3.6 V

−0.3 V to +1.32 V

T_Jis junction temperature (°C).

T_Ais ambient temperature (°C).

P_Dis power dissipation (to calculate power dissipation).

Table 19. Thermal Resistance

Package Type

Digital Input/Output

P0_xx, P1_xx, P2_xx, and SYS_HWRST −0.3 V to +3.6 V

θ_JA

θ_JC

Unit

CP-64-16

26.3

1.0

°C/W

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. B | Page 15 of 39

ADuCM3027/ADuCM3029

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

12

10

8

6

4

2

13

11

9

7

5

3

1

SYS_

VDCDC_

CAP1P

SYS_

LFXTAL_IN

HFXTAL_OUT

VBAT_ANA1

VBAT_ADC

VLDO_OUT

CAP2N

A

VDCDC_

CAP2P

VDCDC_

CAP1N

SYS_

LFXTAL_OUT

SYS_

HFXTAL_IN

P2_03

VREF_ADC

P0_00

B

C

D

P2_05

P0_05

GND_ VREFADC VDCDC_OUT

VBAT_ANA2

GND_ANA

P0_02

P0_11

P0_01

P1_10

P0_03

P0_10

P2_06

P0_07

P2_04

P0_04

P0_06

SYS_HWRST

GND_DIG

P1_02

P1_03

E

F

P1_07

P1_08

P1_09

P1_04

P1_05

P2_01

VBAT_DIG1

P2_11

P1_06

P1_01

P0_13

P0_15

VBAT_DIG2

G

P0_12

P0_09

P0_08

P1_14

P1_00

H

BOTTOM VIEW

(BALL SIDE UP)

Not to Scale

Figure 14. ADuCM3027/ADuCM3029 54-Ball WLCSP Configuration

Table 20. ADuCM3027/ADuCM3029 54-Ball WLCSP Pin Function Descriptions

Pin No. Mnemonic

Signal Name

Description

A1

A3

A5

A7

A9

A11

VBAT_ANA1

SYS_HFXTAL_OUT Not Applicable

SYS_LFXTAL_IN

VDCDC_CAP1P

VDCDC_CAP2N

VLDO_OUT

Not Applicable

External Supply for Analog Circuits in the MCU.

High Frequency Crystal Output.

High Frequency Crystal Input.

Buck Converter Capacitor 1 Positive Terminal.

Buck Converter Capacitor 2 Negative Terminal.

Low Drop Out Regulator Output. This pin is only for connecting the

decoupling capacitor. Do not connect this pin to the external load.

Not Applicable

A13

B1

B3

VBAT_ADC

P0_00

SYS_HFXTAL_IN

Not Applicable

SPI0_CLK/SPT0_BCLK/GPIO00

Not Applicable

External Supply for Internal ADC.

GPIO. See the GPIO Multiplexing section for more information.

High Frequency Crystal Input.

B5

SYS_LFXTAL_OUT Not Applicable

Low Frequency Crystal Output.

B7

B9

B11

B13

C1

VDCDC_CAP1N

VDCDC_CAP2P

VREF_ADC

P2_03

Not Applicable

ADC0_VIN0/GPIO35

SPI0_CS0/SPT0_BCNV/

SPI2_RDY/GPIO03

Buck Converter Capacitor 1 Negative Terminal.

Buck Converter Capacitor 2 Positive Terminal.

External Reference Voltage for Internal ADC.

GPIO. See the GPIO Multiplexing section for more information.

P0_03

C3

C5

C7

P0_01

P0_02

VBAT_ANA2

SPI0_MOSI/SPT0_BFS/GPIO01

SPI0_MISO/SPT0_BD0/GPIO02

Not Applicable

GPIO. See the GPIO Multiplexing section for more information.

External Supply for Analog Circuits in the MCU.

Rev. B | Page 16 of 39

Data Sheet

ADuCM3027/ADuCM3029

Pin No. Mnemonic

Signal Name

Description

C9

VDCDC_OUT

Not Applicable

Buck Converter Output. This pin is only for connecting the decoupling

capacitor. Do not connect this pin to the external load.

C11

C13

D1

GND_VREFADC

P2_05

P0_10

Not Applicable

ADC0_VIN2/GPIO37

UART0_TX/GPIO10

SPI0_CS1/SYS_CLKIN/

SPI1_CS3/GPIO26

Ground for Internal ADC.

GPIO. See the GPIO Multiplexing section for more information.

D3

P1_10

D5

D7

D9

D11

D13

E1

E3

E5

E7

P0_11

GND_ANA

P2_04

P2_06

P0_05

P1_03

P1_02

GND_DIG

SYS_HWRST

P0_04

UART0_RX/GPIO11

Not Applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Reference for Analog Circuits in the MCU.

ADC0_VIN1/GPIO36

ADC0_VIN3/GPIO38

I2C0_SDA/GPIO05

SPI2_MOSI/GPIO19

SPI2_CLK/GPIO18

Not Applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Reference for Digital Circuits in the MCU.

Not Applicable

Hardware Reset Pin.

E9

I2C0_SCL/GPIO04

GPIO07/SWD0_DATA

GPIO06/SWD0_CLK

GPIO. See the GPIO Multiplexing section for more information.

E11

E13

F2

P0_07

P0_06

P2_01

XINT0_WAKE3/TMR2_OUT/GPIO33 GPIO. See the GPIO Multiplexing section for more information.

F4

F6

F8

P1_05

P1_04

P1_09

P1_08

P1_07

VBAT_DIG2

P0_15

P0_13

P1_01

SPI2_CS0/GPIO21

SPI2_MISO/GPIO20

SPI1_CS0/GPIO25

SPI1_MISO/GPIO24

SPI1_MOSI/GPIO23

Not Applicable

XINT0_WAKE0/GPIO15

XINT0_WAKE2/GPIO13

GPIO17/SYS_BMODE0

SPI1_CLK/GPIO22

GPIO. See the GPIO Multiplexing section for more information.

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section for more information.

F10

F12

G1

G3

G5

G7

G9

G11

P1_06

P2_11

SPI1_CS1/SYS_CLKOUT/GPIO43/

RTC1_SS1

G13

H2

H4

H6

H8

VBAT_DIG1

P1_00

P0_14

P1_14

P0_08

Not Applicable

External Supply for Digital Circuits in the MCU.

XINT0_WAKE1/GPIO16

TMR0_OUT/SPI1_RDY/GPIO14

SPI0_RDY/GPIO30

BPR0_TONE_N/GPIO08

BPR0_TONE_P/SPI2_CS1/GPIO09

GPIO. See the GPIO Multiplexing section for more information.

H10

H12

P0_09

P0_12

SPT0_AD0/GPIO12/

UART0_SOUT_EN

Rev. B | Page 17 of 39

ADuCM3027/ADuCM3029

Data Sheet

48 GND_DIG

47 P1_00

46 P0_14

45 P2_02

44 P1_14

43 P1_13

42 P1_12

41 P1_11

40 P0_08

39 P0_09

38 P1_01

37 P1_15

36 P2_00

35 P0_12

34 VBAT_DIG1

33 P2_11

VBAT_ANA1

1

2

3

4

5

6

7

8

9

SYS_HFXTAL_IN

SYS_HFXTAL_OUT

SYS_LFXTAL_IN

SYS_LFXTAL_OUT

VDCDC_CAP1N

VDCDC_CAP1P

VBAT_ANA2

ADuCM3027/ADuCM3029/

ADuCM3029-1/ADuCM3029-2

TOP VIEW

VDCDC_OUT

VDCDC_CAP2N 10

VDCDC_CAP2P 11

VLDO_OUT 12

VREF_ADC 13

VBAT_ADC 14

GND_VREFADC 15

P2_03 16

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED.

Figure 15. ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2 64-Lead LFCSP Configuration

Table 21. ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2, 64-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic

Signal Name

Not applicable

Description

1

2

3

4

5

6

7

8

9

VBAT_ANA1

SYS_HFXTAL_IN

External Supply for Analog Circuits in the MCU.

High Frequency Crystal Input.

High Frequency Crystal Output.

Low Frequency Crystal Input.

Low Frequency Crystal Output.

Buck Converter Capacitor 1 Negative Terminal.

Buck Converter Capacitor 1 Positive Terminal.

External Supply for Analog Circuits in the MCU

Buck Converter Output. This pin is only for connecting the decoupling

capacitor. Do not connect this pin to the external load.

SYS_HFXTAL_OUT Not applicable

SYS_LFXTAL_IN Not applicable

SYS_LFXTAL_OUT Not applicable

VDCDC_CAP1N

VDCDC_CAP1P

VBAT_ANA2

Not applicable

VDCDC_OUT

10

11

12

VDCDC_CAP2N

VDCDC_CAP2P

VLD0_OUT

Not applicable

Buck Converter Capacitor 2 Negative Terminal.

Buck Converter Capacitor 2 Positive Terminal.

Low Drop Out Regulator Output. This pin is only for connecting the

decoupling capacitor. Do not connect this pin to the external load.

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VREF_ADC

VBAT_ADC

GND_VREFADC

P2_03

P2_04

P2_05

P2_06

P2_07

P2_08

P2_09

P2_10

P0_05

SYS_HWRST

P0_04

P0_07

Not applicable

External Reference Voltage for Internal ADC.

External Supply for Internal ADC.

Ground for Internal ADC.

ADC0_VIN0/GPIO35

ADC0_VIN1/GPIO36

ADC0_VIN2/GPIO37

ADC0_VIN3/GPIO38

ADC0_VIN4/SPI2_CS3/GPIO39

ADC0_VIN5/SPI0_CS2/GPIO40

ADC0_VIN6/SPI0_CS3/GPIO41

ADC0_VIN7/SPI2_CS2/GPIO42

I2C0_SDA/GPIO05

GPIO. See the GPIO Multiplexing section.

Hardware Reset Pin.

Not applicable

I2C0_SCL/GPIO04

GPIO07/SWD0_DATA

GPIO06/SWD0_CLK

GPIO. See the GPIO Multiplexing section.

P0_06

Rev. B | Page 18 of 39

Data Sheet

ADuCM3027/ADuCM3029

Pin No. Mnemonic

Signal Name

Description

29

30

31

32

33

P1_09

P1_08

P1_07

P1_06

P2_11

SPI1_CS0/GPIO25

SPI1_MISO/GPIO24

SPI1_MOSI/GPIO23

SPI1_CLK/GPIO22

SPI1_CS1/SYS_CLKOUT/GPIO43/

RTC1_SS1

GPIO. See the GPIO Multiplexing section.

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

VBAT_DIG1

P0_12

P2_00

P1_15

P1_01

P0_09

P0_08

P1_11

P1_12

P1_13

P1_14

P2_02

P0_14

P1_00

GND_DIG

VBAT_DIG2

P0_15

P0_13

P2_01

P1_05

P1_04

P1_03

P1_02

P0_11

P0_10

P1_10

Not applicable

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section.

Ground Reference for Digital Circuits in the MCU.

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section.

SPT0_AD0/GPIO12

SPT0_AFS/GPIO32

SPT0_ACLK/GPIO31

GPIO17/SYS_BMODE0

BPR0_TONE_P/SPI2_CS1/GPIO09

BPR0_TONE_N/GPIO08

TMR1_OUT/GPIO27

GPIO28

GPIO29

SPI0_RDY/GPIO30

SPT0_ACNV/SPI1_CS2/GPIO34

TMR0_OUT/SPI1_RDY/GPIO14

XINT0_WAKE1/GPIO16

Not applicable

XINT0_WAKE0/GPIO15

XINT0_WAKE2/GPIO13

XINT0_WAKE3/TMR2_OUT/GPIO33 GPIO. See the GPIO Multiplexing section.

SPI2_CS0/GPIO21

SPI2_MISO/GPIO20

SPI2_MOSI/GPIO19

SPI2_CLK/GPIO18

UART0_RX/GPIO11

UART0_TX/GPIO10

GPIO. See the GPIO Multiplexing section.

SPI0_CS1/SYS_CLKIN/SPI1_CS3/

GPIO26

60

P0_03

SPI0_CS0/SPT0_BCNV/SPI2_RDY/

GPIO03

GPIO. See the GPIO Multiplexing section.

61

62

63

64

P0_02

P0_01

P0_00

GND_ANA

EPAD

SPI0_MISO/SPT0_BD0/GPIO02

SPI0_MOSI/SPT0_BFS/GPIO01

SPI0_CLK/SPT0_BCLK/GPIO00

Not applicable

GPIO. See the GPIO Multiplexing section.

Ground Reference for Analog Circuits in the MCU.

Exposed Pad. The exposed pad must be grounded.

Rev. B | Page 19 of 39

ADuCM3027/ADuCM3029

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16 through Figure 21 show the typical current voltage characteristics for the output drivers of the MCU. The curves represent the

current drive capability of the output drivers as a function of output voltage.

V

(V)

V

(V)

2.85

OH

1.2

1.3

1.4

1.5

1.6

V

1.7

1.8

2.70

5

2.75

2.80

2.90

V

2.95

3.00

5

4

, V

= 3.0V

, V

= 1.74V

TYPE A

OH BAT

4

3

V

TYPE A

V

OH

TYPE B

TYPE C

TYPE D

TYPE B

TYPE C

TYPE D

OH

3

OH

2

1

0

–1

–2

–3

–4

–5

–1

–2

–3

–4

–5

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

, V

= 3.0V

V

, V

= 1.74V

OL BAT

0.05

OL BAT

0.1

0.30

0

0.10

0.15

(V)

0.20

0.25

0.6

0

0.2

0.3

(V)

0.4

0.5

V

OL

V

OL

Figure 16. Output Double Drive Strength Characteristics (V_BAT= 1.74 V)

Figure 18. Output Double Drive Strength Characteristics (V_BAT= 3.0 V)

V

(V)

1.5

V

(V)

OH

1.2

1.3

1.4

1.6

1.7

2.75

2.80

2.85

2.90

2.95

3.00

2.5

2.0

2.5

V

, V

= 1.74V

V

, V

= 3.0V

OH BAT

2.0

V

TYPE A

TYPE B

V

TYPE A

OH

V

TYPE B

TYPE C

TYPE D

OH

1.5

TYPE C

TYPE D

OH

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

, V

= 1.74V

V

, V

= 3.0V

0.05

OL BAT

0.1

OL BAT

0

0.10

0.15

0.20

0.25

0.6

0

0.2

0.3

(V)

0.4

0.5

V

(V)

V

OL

Figure 17. Output Single Drive Strength Characteristics (V_BAT= 1.74 V)

Figure 19. Output Single Drive Strength Characteristics (V_BAT= 3.0 V)

Rev. B | Page 20 of 39

Data Sheet

ADuCM3027/ADuCM3029

V

(V)

V

(V)

OH

3.30

5

3.35

3.40

3.45

3.50

V

3.55

3.60

3.38 3.40 3.42 3.44 3.46 3.48 3.50 3.52 3.54 3.56 3.58

2.5

, V

= 3.6V

V

, V

= 3.6V

OH BAT

4

3

2.0

V

TYPE A

V

TYPE A

TYPE B

TYPE C

TYPE D

OH

TYPE B

TYPE C

TYPE D

V

OH

1.5

V

OH

2

1.0

1

0.5

0

–1

–2

–3

–4

–5

–0.5

–1.0

–1.5

–2.0

–2.5

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

, V = 3.6V

OL BAT

V

, V

= 3.6V

OL BAT

0

0.05

0.10

0.15

0.20

0.25

0

0.05

0.10

0.15

0.20

V

(V)

OL

V

(V)

OL

Figure 20. Output Double Drive Strength Characteristics (V_BAT= 3.6 V)

Figure 21. Output Single Drive Strength Characteristics (V_BAT= 3.6 V)

Rev. B | Page 21 of 39

ADuCM3027/ADuCM3029

Data Sheet

THEORY OF OPERATION

Code Region

ARM CORTEX-M3 PROCESSOR

The ARM Cortex-M3 core is a 32-bit reduced instruction set

computer (RISC). The length of the data can be 8 bits, 16 bits,

or 32 bits. The length of the instruction word is 16 bits or 32 bits.

Accesses in this region (0x0000 0000 to 0x0001 FC00 for the

ADuCM3027 and 0x0000 0000 to 0x0003 FFFF for the

ADuCM3029) are performed by the core and target the

memory and cache resources.

The processor has the following features:

SRAM Region



Cortex-M3 architecture

Accesses in this region (0x2000 0000 to 0x2004 7FFF) are

performed by the ARM Cortex-M3 core. The SRAM region of

the core can otherwise act as a data region for an application.



Thumb-2 instruction set architecture (ISA)

technology

Three-stage pipeline with branch speculation

Low latency interrupt processing with tail chaining

Single-cycle multiply

Hardware divide instructions

Nested vectored interrupt controller (NVIC)

(64 interrupts and 8 priorities)



Internal SRAM data region. This space can contain read/write

data. Internal SRAM can be partitioned between code and

data (SRAM region in M3 space) in 32 kB blocks. Access to

this region occurs at core clock speed with no wait states.

It also supports read/write access by the ARM Cortex-M3

core and read/write DMA access by system devices. It

supports exclusive memory accesses via the global

exclusive access monitor within the Cortex-M3 platform.

System memory mapped registers (MMRs). Various system

MMRs reside in this region.



Two hardware breakpoints and one watchpoint

(unlimited software breakpoints using Segger JLink)



Memory protection unit (MPU)



Eight region MPU with subregions and background

region



Programmable clock generator unit

System Region

Configurable for ultra low power operation



Accesses in this region (0xE000 0000 to 0xF7FF FFFF) are per-

formed by the ARM Cortex-M3 core and are handled within

the Cortex-M3 platform.

Deep sleep mode, dynamic power management

Programmable clock generator unit

ARM Cortex-M3 Memory Subsystem



CoreSight™ ROM. The read-only memory (ROM) table

entries point to the debug components of the processor.

ARM APB Peripheral. This space is defined by ARM and

occupies the bottom 256 kB/128 kB of the system (SYS) region

(0xE000 0000 to 0xE004 0000) depending on the device used.

The space supports read/write access by the M3 core to the

internal peripherals of the ARM core (NVIC, system control

space (SCS), wake-up interrupt controller (WIC)), and

CoreSight ROM. It is not accessible by system DMA.

The memory map of the ADuCM3027/ADuCM3029 is based

on the Cortex-M3 model from ARM. By retaining the standardized

memory mapping, it is easier to port applications across M3

platforms.



The ADuCM3027/ADuCM3029 application development is

based on memory blocks across code/SRAM regions. Internal

memory is available via internal SRAM and internal flash.

Rev. B | Page 22 of 39

Data Sheet

ADuCM3027/ADuCM3029

MMRs (Peripheral Control and Status)

MEMORY ARCHITECTURE

For the address space containing MMRs, refer to Figure 22.

These registers provide control and status for on-chip

peripherals of the ADuCM3027/ADuCM3029. For more

information about the MMRs, refer to the ADuCM302x Ultra

Low Power ARM Cortex-M3 MCU with Integrated Power

Management Hardware Reference.

The internal memory of the ADuCM3027/ADuCM3029 is

shown in Figure 22. The internal memory incorporates up to

256 kB of embedded flash memory for program code and

nonvolatile data storage, 32 kB of data SRAM, and 32 kB of

SRAM (configured as instruction space or data space).

SRAM Region

Flash Memory

This memory space contains the application instructions and

literal (constant) data that must be accessed in real-time. It

supports read/write access by the ARM Cortex-M3 core and

read/write DMA access by system peripherals. Byte, half-word,

and word accesses are supported.

The ADuCM3027/ADuCM3029 MCUs include 128 kB to

256 kB of embedded flash memory, which is accessed using a

flash controller. For memory available on each product, see

Table 1. The flash controller is coupled with a cache controller.

A prefetch mechanism is implemented in the flash controller to

optimize code performance.

SRAM is divided into 32 kB data SRAM and 32 kB instruction

SRAM. If instruction SRAM is not enabled, then the associated

32 kB can be mapped as data SRAM, resulting in 64 kB of data

SRAM.

Flash writes are supported by a key hole mechanism via

advanced peripheral bus (APB) writes to MMRs. The flash

controller provides support for DMA-based key hole writes.

Parity bit error detection (optional) is available on all SRAM

memories. Two parity bits are associated with each 32-bit word.

With respect to flash integrity, the devices support the

following:

When the cache controller is enabled, 4 kB of the instruction

SRAM is reserved as cache memory.



A fixed user key required for running protected

commands, including mass erase and page erase.

An optional and user definable user failure analysis key

(FAA key). Analog Devices personnel need this key while

performing failure analysis.

Users can select the SRAM configuration modes depending on

the instruction SRAM and cache needed.



In hibernate mode, 8 kB to 32 kB of the SRAM can be retained

in increments of 8 kB. 8 kB of data SRAM is always retained.

Users can additionally retain



An optional and user definable write protection for user

accessible memory.

8-bit ECC.



16 kB out of 32 kB of instruction SRAM

8 kB out of 32 kB of data SRAM

Rev. B | Page 23 of 39

ADuCM3027/ADuCM3029

Data Sheet

0x4001 0FE0

0x4001 0000

DMA0

RESERVED

ADC0

0x400F FFFF

RESERVED

0x4000 70C4

0x4000 7000

0x4004 C80C

0x4004 C000

0x4000 1044

POWER MGT, EXT IRQ,

CLOCKING, MISC MMR

REAL-TIME CLOCK 0 (RTC 0)

0x4000 1000

RESERVED

BEEPER 0

RESERVED

CRYPTO

RESERVED

0x4000 5C0C

0x4000 5C00

0x4004 406C

0x4004 4000

0x4000 0824

GENERAL-PURPOSE TIMER 2

0x4000 0800

RESERVED

UART 0

RESERVED

0x4000 5030

0x4000 5000

0x4004 0414

0x4004 0400

0x4000 0424

RANDOM NUMBER

GENERATOR

GENERAL-PURPOSE TIMER 1

0x4000 0400

RESERVED

SPI 1 MASTER/SLAVE

RESERVED

SPI 0 MASTER/SLAVE

RESERVED

0x4000 4438

0x4000 4400

0x4004 000C

0x4004 0000

0x4000 0424

PROGRAMMABLE

CRC ENGINE

GENERAL-PURPOSE TIMER 0

0x4000 0400

RESERVED

SPORT 0

RESERVED

0x4000 4038

0x4000 4000

0x4003 8078

0x4003 8000

0x2004 3FFF

RAM BANK 1 (16kB)

0x2004 0000

RESERVED

0x4000 3058

0x4000 3000

2

0x4002 4038

0x4002 4000

I C 0 MASTER/SLAVE

0x2000 3FFF

SPIH 0 MASTER/SLAVE

RESERVED

RAM BANK 0 (16kB)

0x2000 0000

RESERVED

WATCHDOG TIMER

RESERVED

0x1000 7FFF

0x4000 2C18

0x4000 2C00

0x4002 00B4

0x4002 0000

GPIO

INSTRUCTION SRAM (32kB)

0x1000 0000

RESERVED

0x4000 2040

0x4000 2000

SYSTEM ID AND DEBUG

ENABLE

0x4001 8088

0x4001 8000

0x0003 FFFC

FLASH CONTROLLER

RESERVED

256kB FLASH MEMORY

0x0000 0000

RESERVED

0x4000 1444

0x4000 1400

REAL-TIME CLOCK 1 (RTC1)

Figure 22. ADuCM3027/ADuCM3029 Memory Map—SRAM Mode 0

Table 22. Boot Modes

Boot Mode

CACHE CONTROLLER

Description

UART download mode.

Flash boot. Boot from integrated flash memory.

The ADuCM3027/ADuCM3029 MCUs have an optional 4 kB

instruction cache. In certain applications, enabling the cache

and executing the code can result in lower power consumption

rather than operating directly from flash. When enabling the

cache controller, 4 kB of instruction SRAM is reserved as cache

memory. In hibernate mode, the cache memory is not retained.

0

1

Power Management

The ADuCM3027/ADuCM3029 MCUs have an integrated

power management system that optimizes performance and

extends battery life of the devices.

SYSTEM AND INTEGRATION FEATURES

The power management system consists of the following:

The ADuCM3027/ADuCM3029 MCUs provide several features

that ease system integration.

•

Integrated 1.2 V low dropout regulator (LDO) and optional

capacitive buck regulator

Integrated power switches for low standby current in

hibernate and shutdown modes.

Reset

•

There are four types of resets: external, power-on, watchdog

timeout, and software system reset. The software system reset is

provided as part of the ARM Cortex-M3 core.

Additional power management features include the following:

•

Customized clock gating for active and Flexi™ modes

Power gating to reduce leakage in hibernate and shutdown

modes

SYS_HWRST

The

pin is toggled to perform a hardware reset.

Booting

The ADuCM3027/ADuCM3029 MCUs support two boot

modes: booting from internal flash and upgrading software

through UART download. If SYS_BMODE0 (Pin P1_01) is

pulled low during power-up or a hard reset, the MCU enters

into serial download mode. In serial download mode, an

on-chip routine initiates in the kernel, which configures the

UART port and communicates with the host to manage the

firmware upgrade via a specific serial download protocol.

•

Flexible sleep modes

Shutdown mode with no retention

Optional high efficiency buck converter to reduce power

Integrated low power oscillators

Power Modes

The PMU provides control of the ADuCM3027/ADuCM3029

power modes and allows the ARM Cortex-M3 to control the

clocks and power gating to reduce the power consumption.

Rev. B | Page 24 of 39

Data Sheet

ADuCM3027/ADuCM3029

Several power modes are available. Each mode provides an

additional low power benefit with a corresponding reduction in

functionality.

V

VDCDC_CAP1P

BAT

0.1µF

VDCDC_CAP1N

BUCK

ENABLED

VDCDC_OUT

Active Mode

0.47µF

VDCDC_CAP2P

VDCDC_CAP2N

In active mode, all peripherals can be enabled. Active power is

managed by optimized clock management. See Table 4 for

details on active mode power.

0.1µF

VLDO_OUT

Flexi Mode

0.47µF

In Flexi mode, the ARM Cortex-M3 core is clock gated, but the

remainder of the system is active. No instructions can be

executed in this mode, but DMA transfers can continue

between peripherals and memory as well as memory to

memory. See Table 5 for details on Flexi mode power.

LDO

NOTES

1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED,

THE FOLLOWING PINS MUST BE LEFT UNCONNECTED:

VDCDC_CAP1P, VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N

Figure 23. Buck Enabled Design

Hibernate Mode

For designs in which the optional buck is not used, the

following pins must be left unconnected: VDCDC_CAP1P,

VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, and

VDCDC_CAP2N.

This mode provides state retention, configurable SRAM and

port pin retention, a limited number of wake-up interrupts

(XINT0_WAKEn and UART0_RX), and, optionally, two

RTCs—RTC0 and RTC1 (FLEX_RTC).

Security Features

Shutdown Mode

The ADuCM3027/ADuCM3029 MCUs provide a combination

of hardware and software protection mechanisms that lock out

access to the devices in secure mode but grant access in open

mode. These mechanisms include password protected slave

boot mode (UART), as well as password protected serial wire

debug (SWD) interfaces.

This mode is the deepest sleep mode, in which all the digital

and analog circuits are powered down with an option to wake

from four possible wake-up sources: three external interrupts

and RTC0. The RTC0 can be optionally enabled in this mode

and the device can be periodically woken up by the RTC0

interrupt. See Table 6 for deep sleep (hibernate and shutdown)

mode specifications.

Mechanisms are provided to protect the device contents (flash,

SRAM, CPU registers, and peripheral registers) from being read

through an external interface by an unauthorized user, which is

referred to as read protection.

The following features are available for power management and

control:

•

A voltage range of 1.74 V to 3.6 V using a single supply

(such as the CR2032 coin cell battery).

It is possible to protect the device from being reprogrammed in

circuit with unauthorized code. This is referred to as in circuit

write protection.

•

GPIOs are driven directly from the battery. The pin state is

retained in hibernate and shutdown modes. The GPIO

configuration is only retained in hibernate mode.

Wake-up from external interrupt (via GPIOs), UART0_RX

interrupt, and RTCs for hibernate mode.

Wake-up from external interrupt (via GPIOs) and RTC0

for shutdown mode.

Optional high power buck converter for 1.2 V full on

support (for MCU use only). See Figure 23 for the

suggested external circuitry.

The devices can be configured with no protection, read

protection, or read and in circuit write protection. It is not

necessary to provide in circuit write protection without read

protection.

•

Cryptographic Accelerator

The cryptographic accelerator is a 32-bit APB DMA capable

peripheral. There are two 32-bit buffers provided for data

input/output operations. These buffers read in or read out

128 bits in four data accesses. Big endian and little endian data

formats are supported, as are the following modes:

•

Electronic code book (ECB) mode—AES mode

Counter (CTR) mode

Cipher block chaining (CBC) mode

Message authentication code (MAC) mode

Cipher block chaining-message authentication code

(CCM/CCM*) mode

•

SHA-256 modes

Rev. B | Page 25 of 39

ADuCM3027/ADuCM3029

Data Sheet

True Random Number Generator (TRNG)

Timers

The TRNG is used during operations where nondeterministic

values are required. These operations can include generating

challenges for secure communication or keys for an encrypted

communication channel. The generator can run multiple times

to generate a sufficient number of bits for the strength of the

intended operation. The TRNG can seed a deterministic

random bit generator.

The ADuCM3027/ADuCM3029 MCUs have three general-

purpose timers and a watchdog timer.

General-Purpose Timers

The ADuCM3027/ADuCM3029 MCUs have three identical

general-purpose timers, each with a 16-bit up and down

counter. The up and down counter can be clocked from one of

four user selectable clock sources. Any selected clock source

can be scaled down using a prescaler of 1, 16, 64, or 256.

Reliability and Robustness Features

The ADuCM3027/ADuCM3029 MCUs provide a number of

features that can enhance or help achieve certain levels of

system safety and reliability. While the level of safety is mainly

dominated by system considerations, the following features are

provided to enhance robustness.

Watchdog Timer (WDT)

The WDT is a 16-bit count down timer with a programmable

prescaler. The prescaler source is selectable and can be scaled by

a factor of 1, 16, or 256. The WDT is clocked by the 32 kHz on-

chip oscillator (LFOSC) and recovers from an illegal software

state. The WDT requires periodic servicing to prevent it from

forcing a reset or interrupt to the MCU.

ECC Enabled Flash Memory

The entire flash array can be protected to either correct single-

bit errors or detect two-bit errors per 64-bit flash data.

Analog-to-Digital Converter (ADC) Subsystem

Multiparity Bit Protected SRAM

The ADuCM3027/ADuCM3029 MCUs integrate a 12-bit SAR

ADC with up to eight external channels. Conversions can be

performed in single or autocycle mode. In single mode, the

ADC can be configured to convert on a particular channel by

selecting one of the channels. Autocycle mode is provided to

reduce MCU overhead of sampling and reading individual

channel registers. The ADC can also be used for temperature

sensing and measuring battery voltage using dedicated

channels. Temperature sensing and battery monitoring cannot

be included with external channels in autocycle mode.

Each word of the SRAM and cache memory is protected by

multiple parity bits to allow detection of random soft errors.

Software Watchdog

The on-chip watchdog timer can provide software-based

supervision of the ADuCM3027/ADuCM3029.

Cyclic Redundancy Check (CRC) Accelerator

The CRC accelerator computes the CRC for a block of memory

locations. The exact memory location can be in the SRAM,

flash, or any combination of MMRs. The CRC accelerator

generates a checksum that can be compared with an expected

signature.

A digital comparator triggers an interrupt if ADC input is above

or below a programmable threshold. The ADC0_VIN0,

ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 input channels

can be used with the digital comparator.

The main features of the CRC include the following:

Use the ADC in DMA mode to reduce MCU overhead by

moving ADC results directly into SRAM with a single interrupt

asserted when the required number of ADC conversions has

been completely logged to memory.



Generates a CRC signature for a block of data.

Supports programmable polynomial length of up to 32 bits.

Operates on 32 bits of data at a time.

Supports MSB first and LSB first CRC implementations.

Various data mirroring capabilities.

Initial seed to be programmed by user.

DMA controller (memory to memory transfer) used for

data transfer to offload the MCU.

Programmable GPIOs

The ADuCM3027 and ADuCM3029 MCUs have 44 and 34

GPIO pins in the LFCSP and WLCSP packages, respectively.

Note that the ADuCM3029-1 and ADuCM3029-2 models have

44 GPIO pins and are available in the LFCSP only. These GPIO

pins have multiple, configurable functions defined by user code.

They can be configured as an input/output and have

programmable pull-up resistors. All GPIO pins are functional

over the full supply range.

In deep sleep mode, the GPIO pins retain their state. On reset,

the GPIO pins tristate.

Rev. B | Page 26 of 39

Data Sheet

ADuCM3027/ADuCM3029

The main features of the ADC subsystem include the following:



Each channel, including temperature sensor and battery

monitoring, has a data register for conversion result.



12-bit resolution.

Programmable ADC update rate from 10 KSPS to

1.8 MSPS.

Integrated input multiplexer that supports up to eight

channels.

Clocking

The ADuCM3027/ADuCM3029 MCUs have the following

clocking options:



26 MHz



Temperature sensing support.

Battery monitoring support.

Software selectable on-chip reference voltage generation—

1.25 V and 2.5 V.



Internal oscillator—HFOSC (26 MHz)

External crystal oscillator—HFXTAL (26 MHz or

16 MHz)



GPIO clock in—SYS_CLKIN



Software selectable internal or external reference.

Autocycle mode—ability to automatically select a sequence

of input channels for conversion.



32 kHz



Internal oscillator—LFOSC

External crystal oscillator—LFXTAL



Averaging function—converted data on single-channel or

multiple channels can be averaged up to 256 samples.

Alert function—internal digital comparator for

ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and

ADC0_VIN3 channels. An interrupt is generated if the

digital comparator detects an ADC result above or below a

user defined threshold.

The clock options have software configurability with the

following exceptions:



HFOSC cannot be disabled when using an internal buck

regulator.

LFOSC cannot be disabled even if using LFXTAL.



Dedicated DMA channel support.

Table 23. RTC Features

Features

RTC0

RTC1 (FLEX_RTC)

Resolution of

Time Base

(Prescaling)

Counts time at 1 Hz in units of seconds. Operationally, Can prescale the clock by any power of two from 0 to 15. It can

RTC0 always prescales to 1 Hz (for example, divide by

32,768) and always counts real time in units of

seconds.

count time in units of any of these 16 possible prescale settings.

For example, the clock can be prescaled by 1, 2, 4, 8, …, 16,384, or

32,768.

Source Clock

LFXTAL.

Depending on the low frequency multiplexer (LFMUX)

configuration, the RTC is clocked by the LFXTAL or the LFOSC.

Wake-Up

Timer

Wake-up time is specified in units of seconds.

Supports alarm times down to a resolution of 30.52 μs, that is,

where the time is specified down to a specific 32 kHz clock cycle.

Number of

Alarms

One alarm only. Uses an absolute, nonrepeating

alarm time, specified in units of 1 sec.

Two alarms. One absolute alarm time and one periodic alarm,

repeating every 60 prescaled time units.

SensorStrobe

Mechanism

Not available.

SensorStrobe is an alarm mechanism in the RTC that sends an

output pulse via GPIOs to an external device to instruct the device

to take a measurement or perform some action at a specific time.

SensorStrobe events are schedule data specific target time

relative to the real-time count of the RTC. SensorStrobe can be

enabled in active, Flexi, and hibernate modes.

Input Capture Not available.

Input capture takes a snapshot of the RTC when an external

device signals an event via a transition on one of the GPIO inputs

to the ADuCM3027/ADuCM3029. Typically, an input-capture

event is triggered by an autonomous measurement or action on

such a device, which then signals to the ADuCM3027/

ADuCM3029 that the RTC must take a snapshot of time

corresponding to the event. Taking the snapshot can wake up the

ADuCM3027/ADuCM3029 and cause an interrupt to the CPU. The

CPU can subsequently obtain information from the RTC on the

exact 32 kHz cycle on which the input capture event occurred.

Rev. B | Page 27 of 39

ADuCM3027/ADuCM3029

Data Sheet

channels. The frame sync and clock can be shared. Some of the

ADCs and DACs require two control signals for their

conversion process. To interface with such devices, the

SPT0_ACNV and SPT0_BCNV signals are provided. To use

these signals, enable the timer enable mode. In this mode, a

PWM timer inside the module generates the programmable

SPT0_ACNV and SPT0_BCNV signals.

Beeper Driver

The ADuCM3027/ADuCM3029 MCUs have an integrated

audio driver for a beeper.

The beeper driver module in the ADuCM3027/ADuCM3029

MCUs generate a differential square wave of programmable

frequency. It drives an external piezoelectric sound component

with two terminals that connect to the differential square wave

output.

Serial ports operate in two modes:

•

Standard digital signal processor (DSP) serial mode

Timer enable mode

The beeper driver consists of a module that can deliver

frequencies ranging from 8 kHz to approximately 0.25 kHz; the

minimum frequency is determined by the maximum value of a

divide register that can be programmed to 127. This results in a

beeper frequency of

SPI Ports

The ADuCM3027/ADuCM3029 MCUs provide three SPIs. SPI

is an industry standard, full-duplex, synchronous serial inter-

face that allows eight bits of data to be synchronously

32.768 kHz/127 = 0.25802 kHz

transmitted and simultaneously received. Each SPI incorporates

two DMA channels that interface with the DMA controller. One

DMA channel transmits and the other receives. The SPI on the

MCU eases interfacing to external serial flash devices.

The beeper driver allows programmable tone durations in 4 ms

increments. Pulse (single-tone) and sequence (multitone)

modes provide versatile playback options.

In sequence mode, the beeper can be programmed to play any

number of tone pairs from 1 to 254 (2 tones to 508 tones) or be

programmed to play forever (until stopped by the user).

Interrupts are available to indicate the start or end of any beep,

the end of a sequence, or when the sequence is nearing

completion.

The SPI features include the following:

•

Serial clock phase mode and serial clock polarity mode

Loopback mode

Continuous and repeated transfer mode

Wired OR output mode

Read command mode for half-duplex operation (transmit

followed by receive)

Debug Capability

The ADuCM3027/ADuCM3029 MCUs support SWD. The

ADuCM3027/ADuCM3029 MCUs have a reduced flash patch

and breakpoint (FPB) unit with support for up to two hardware

breakpoints.

•

Flow control support in read command mode

Support for 3-pin SPI in read command mode

CS

Multiple

line support

software override support

CS

ON-CHIP PERIPHERAL FEATURES

The ADuCM3027/ADuCM3029 MCUs have a rich set of

peripherals connected to the core via several concurrent high

bandwidth buses, providing flexibility in system configuration

as well as excellent overall system performance (see Figure 1).

UART Port

The ADuCM3027/ADuCM3029 MCUs provide a full-duplex

UART port, which is fully compatible with PC standard UARTs.

The UART port provides a simplified UART interface to other

peripherals or hosts, supporting full-duplex, DMA, and

asynchronous transfers of serial data. The UART port includes

support for five to eight data bits, and none, even, or odd parity.

A frame is terminated by one, one and a half, or two stop bits.

The ADuCM3027/ADuCM3029 MCUs contain high speed

serial ports, an interrupt controller for flexible management of

interrupts from the on-chip peripherals or external sources, and

power management control functions to tailor the performance

and power characteristics of the MCU and system to many

application scenarios.

I²C

The ADuCM3027/ADuCM3029 MCUs provide an I²C bus

peripheral that has two pins for data transfer. SCL (Pin P0_04)

is a serial clock pin, and SDA (Pin P0_05) is a serial data pin.

The pins are configured in a wired AND format that allows

arbitration in a multimaster system. A master device can be

configured to generate the serial clock. The frequency is

programmed by the user in the serial clock divisor register. The

master channel can operate in fast mode (400 kHz) or standard

mode (100 kHz).

Serial Ports (SPORT)

The ADuCM3027/ADuCM3029 MCUs provide two single

direction half SPORTs or one bidirectional full SPORT. The

synchronous serial ports provide an inexpensive interface to a

wide variety of digital and mixed-signal peripheral devices such

as Analog Devices audio codecs, ADCs, and DACs. The serial

ports contain two data lines, a clock, and a frame sync. The data

lines can be programmed to either transmit or receive, and each

data line has a dedicated DMA channel.

Serial port data can be automatically transferred to and from

on-chip memory or external memory via dedicated DMA

Rev. B | Page 28 of 39

Data Sheet

ADuCM3027/ADuCM3029

DEVELOPMENT SUPPORT

MCU TEST CONDITIONS

Development support for the ADuCM3027/ADuCM3029 MCU

includes documentation, evaluation hardware, and

development software tools.

The ac signal specifications (timing parameters) appearing in

this data sheet include output disable time, output enable time,

and others. Timing is measured on signals when they cross the

voltage threshold (V_MEAS) level as described in Figure 24. All

delays (in nanoseconds or microseconds) are measured between

the point that the first signal reaches V_MEASand the point that

the second signal reaches V_MEAS. The value of V_MEASis set to

V_BAT/2. The tester pin electronics is shown in Figure 25.

Documentation

The ADuCM302x Ultra Low Power ARM Cortex-M3 MCU

with Integrated Power Management Hardware Reference details

the functionality of each block on the ADuCM3027/ADuCM3029

MCUs. It includes power management, clocking, memories, and

peripherals.

INPUT

OR

V

MEAS

Hardware

OUTPUT

The EV-COG-AD3029LZ is available to prototype sensor

configurations with the ADuCM3027/ADuCM3029 MCUs.

Figure 24. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

50Ω

Software

V

LOAD

T1

DUT

OUTPUT

The EV-COG-AD3029LZ includes a complete development and

debug environment for the ADuCM3027/ADuCM3029 MCUs.

The device family pack (DFP) for the ADuCM3027/

ADuCM3029 is provided for the IAR Embedded Workbench

for ARM, Keil™, and CrossCore® embedded studio (CCES)

environments.

70Ω

45Ω

ZO = 50Ω (IMPEDANCE)

TD = 4.04ns ± 1.18ns

50Ω

2pF

0.5pF

4pF

400Ω

The DFP also includes operating system (OS) aware drivers and

example code for all the peripherals on the devices.

NOTES

1. THE WORST-CASE TRANSMISSION LINE DELAY (TD) IS SHOWN AND

CAN BE USED FOR THE OUTPUT TIMINGANALYSIS TO REFLECT THE

TRANSMISSION LINE EFFECTAND MUST BE CONSIDERED.

TRANSMISSION LINE IS FOR LOAD ONLY AND DOES NOT AFFECT

THE DATA SHEET TIMING SPECIFICATIONS.

2. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING

FORA GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM

CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR

ANY TIMING DIFFERENCES.

ADDITIONAL INFORMATION

The following documentation that describe the ADuCM3027/

ADuCM3029 MCUs can be ordered from any Analog Devices

sales office or accessed electronically on the Analog Devices

website:

Figure 25. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)



ADuCM302x Ultra Low Power ARM Cortex-M3 MCU

with Integrated Power Management Hardware Reference.

DRIVER TYPES

Table 24 shows the driver types.

This data sheet describes the ARM Cortex-M3 core and

memory architecture used on the ADuCM3027/ADuCM3029

MCUs but does not provide detailed programming information

for the ARM processor. For more information about

programming the ARM processor, visit the ARM Infocenter

web page.

Table 24. Driver Types

Driver Type^{1, 2, 3}Associated Pins

Type A

P0_00 to P0_03, P0_07, P0_10 to P0_13,

P0_15, P1_00 to P1_10, P1_15, P2_00, P2_01,

P2_04 to P2_14, P3_00 to P3_03, and

SYS_HWRST

The applicable documentation for programming the ARM

Cortex-M3 processor include the following:

.

Type B

P0_08, P0_09, P0_14, P1_11 to P1_14, and

P2_02

P0_04 and P0_05

P0_06



ARM Cortex-M3 Devices Generic User Guide

ARM Cortex-M3 Technical Reference Manual

Type C

Type D

REFERENCE DESIGNS

¹In single drive mode, the maximum source/sink capacity is 2 mA.

²In double drive mode, the maximum source/sink capacity is 4 mA.

³At maximum drive capacity, only 16 GPIOs are allowed to switch at any

given point of time.

The Circuits from the Lab® page provides the following for the

ADuCM3027/ADuCM3029 reference design:



Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

Drill down links for components in each chain to selection

guides and application information

Reference designs applying best practice design techniques

Rev. B | Page 29 of 39

ADuCM3027/ADuCM3029

Data Sheet

Table 26. EEMBC ULPMark™-CP Profile Configuration

EEMBC ULPMARK™-CP SCORE

Profile Configuration

Value

Using the software configuration and the profile configuration

shown in the following tables, the EEMBC ULPMark-CP score

is 245.5.

Wakeup Timer Module

RTC1

Wakeup Timer Clock Source

Wakeup Timer Frequency

Wakeup Timer Accuracy

External crystal

32768 Hz

20 PPM

Table 25. EEMBC ULPMark™-CP Software Configuration

Software Configuration

Compiler Name and Version

Compiler Flags

Value

Active Power Mode Name

Active Mode Clock Configuration

Active Mode Voltage Integrity

Inactive Power Mode Name

Inactive Clock Configuration

Inactive Mode Voltage Integrity

Active mode

26 MHz (CPU), 32 kHz (RTC)

1.74 V

Hibernate

Off (CPU), 32 kHz (RTC)

1.74 V

IAR EWARM 7.50.2.10505

-Ohs --

endian=little --

cpu=Cortex-M3 -D

__ADuCM3029__

ULPBench Profile and Version

EnergyMonitor Software Version

Core Profile v1.1

V1.1.3

Rev. B | Page 30 of 39

Data Sheet

ADuCM3027/ADuCM3029

GPIO MULTIPLEXING

Table 27 through Table 29 show the signal multiplexing options for the GPIO pins.

Table 27. Signal Multiplexing for PORT 0

Availability

WLCSP LFCSP Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3

P0_00 Yes

P0_01 Yes

P0_02 Yes

P0_03 Yes

P0_04 Yes

P0_05 Yes

P0_06 Yes

P0_07 Yes

P0_08 Yes

P0_09 Yes

P0_10 Yes

P0_11 Yes

P0_12 Yes

P0_13 Yes

P0_14 Yes

P0_15 Yes

Yes

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

SWD0_CLK

SWD0_DATA

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13/XINT0_WAKE2

GPIO14

GPIO15/XINT0_WAKE0

SPI0_CLK

SPT0_BCLK

SPT0_BFS

SPT0_BD0

Not available

SPI2_RDY

SPI0_MOSI

SPI0_MISO

SPI0_CS0

I2C0_SCL

I2C0_SDA

GPIO06

SPT0_BCNV

Not available

SPI2_CS1

Not available

SPI1_RDY

Not available

UART0_SOUT_EN

Not available

GPIO07

BPR0_TONE_N

BPR0_TONE_P

UART0_TX

UART0_RX

SPT0_AD0

Not available

TMR0_OUT

Not available

Table 28. Signal Multiplexing for PORT 1

Availability

WLCSP LFCSP Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3

P1_00 Yes

P1_01 Yes

P1_02 Yes

P1_03 Yes

P1_04 Yes

P1_05 Yes

P1_06 Yes

P1_07 Yes

P1_08 Yes

P1_09 Yes

P1_10 Yes

P1_11 No

P1_12 No

P1_13 No

P1_14 Yes

P1_15 No

Yes

GPIO16/XINT0_WAKE1

SYS_BMODE0

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

Not available

GPIO17

SPI2_CLK

SPI2_MOSI

SPI2_MISO

SPI2_CS0

Not available

SYS_CLKIN

Not available

SPI1_CS3

Not available

SPI1_CLK

SPI1_MOSI

SPI1_MISO

SPI1_CS0

SPI0_CS1

Not available

SPT0_ACLK

TMR1_OUT

Not available

SPI0_RDY

Not available

Rev. B | Page 31 of 39

ADuCM3027/ADuCM3029

Data Sheet

Table 29. Signal Multiplexing for PORT 2

Availability

WLCSP LFCSP Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3

P2_00 No

P2_01 Yes

P2_02 No

P2_03 Yes

P2_04 Yes

P2_05 Yes

P2_06 Yes

P2_07 No

P2_08 No

P2_09 No

P2_10 No

P2_11 Yes

Yes

GPIO32

GPIO33/XINT0_WAKE3

GPIO34

GPIO35

GPIO36

GPIO37

GPIO38

GPIO39

GPIO40

SPT0_AFS

Not available

TMR2_OUT

SPI1_CS2

Not available

SPI2_CS3

SPI0_CS2

SPI0_CS3

SPI2_CS2

SYS_CLKOUT

Not available

SPT0_ACNV

ADC0_VIN0

ADC0_VIN1

ADC0_VIN2

ADC0_VIN3

ADC0_VIN4

ADC0_VIN5

ADC0_VIN6

ADC0_VIN7

SPI1_CS1

Not available

RTC1_SS1

GPIO41

GPIO42

GPIO43

Rev. B | Page 32 of 39

Data Sheet

ADuCM3027/ADuCM3029

APPLICATIONS INFORMATION

This section contains circuit diagrams that show the

recommended external components for proper operation of the

ADuCM3027/ADuCM3029 in example application scenarios.

VBAT

IO

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

SYS_LFXTAL_OUT

VDCDC_OUT

4

0.47µF

13

25

9

SYS_HWRST

ADuCM3027/ADuCM3029/

VLDO_OUT

12

0.1µF

ADuCM3029-1/ADuCM3029-2

6

VDCDC_CAP1N

VDCDC_CAP1P

VDCDC_CAP2N

P1_09

P1_08

P1_06

29

30

32

7

10

11 VDCDC_CAP2P

RTC1_SS1

P2_11 33

IO

16 P2_03

31

P1_07

P2_04

17

53

54

55

56

P1_05

P1_04

P1_03

P1_02

18 P2_05

19 P2_06

20 P2_07

21 P2_08

22 P2_09

23 P2_10

P0_12

P2_00

P1_15

P2_02

35

36

37

45

39 P0_09

P0_08

40

P1_00

P0_15

47

50

28 P0_06

P0_07

P1_01

P1_12

p1_13

27

38

42

43

P0_13 51

52

P2_01

P1_11

P0_14

41

46

P0_05

P0_04

24

26

P0_11 57

P0_14 58

P1_14

P1_10

P0_03

44

59

60

P0_01

62

63

P0_00

61 P0_02

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 26. Recommended External Components when Using the Internal Buck Converter

Rev. B | Page 33 of 39

ADuCM3027/ADuCM3029

Data Sheet

VBAT

HFCLK CRYSTAL

26.000MHz

IO

LFCLK CRYSTAL

32.7680kHz

LFXTAL_IN

8pF

LFXTAL_OUT

HFXTAL_IN

18pF

HFXTAL_OUT

18pF

8pF

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

SYS_LFXTAL_OUT

VDCDC_OUT

4

13

25

9

SYS_HWRST

ADuCM3027/ADuCM3029/

VLDO_OUT

12

ADuCM3029-1/ADuCM3029-2

0.47µF

6

7

VDCDC_CAP1N

VDCDC_CAP1P

P1_09

29

P1_08 30

P1_06 32

10 VDCDC_CAP2N

11 VDCDC_CAP2P

RTC1_SS1

33

31

P2_11

P1_07

IO

16

P2_03

17 P2_04

18 P2_05

53

54

55

56

P1_05

P1_04

P1_03

P1_02

19

20

P2_06

P2_07

21 P2_08

P0_12

P2_00

P1_15

22

23

P2_09

P2_10

35

36

37

39

P0_09

P2_02 45

40 P0_08

P1_00 47

28 P0_06

27 P0_07

P0_15

50

P0_13 51

P1_01

P1_12

p1_13

38

42

43

52

P2_01

P1_11

P0_14

41

46

P0_05

P0_04

24

26

57

58

P0_11

P0_14

44 P1_14

P1_10

P0_01

P0_00

59

60 P0_03

61

62

63

P0_02

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 27. Recommended External Components when Using LFXTAL and HFXTAL

Rev. B | Page 34 of 39

Data Sheet

ADuCM3027/ADuCM3029

VBAT

IO

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

4

VREF_ADC

IO

SYS_LFXTAL_OUT

VDCDC_OUT

13

25

9

SYS_HWRST

ADuCM3027/ADuCM3029/

VLDO_OUT

12

0.1µF

4.7µF

ADuCM3029-1/ADuCM3029-2

0.47µF

6

7

VDCDC_CAP1N

VDCDC_CAP1P

P1_09

29

P1_08 30

P1_06 32

10 VDCDC_CAP2N

11 VDCDC_CAP2P

RTC1_SS1

33

31

IO

P2_11

P1_07

ANALOG_IN

33Ω

IO

16

P2_03

0.0056µF

17 P2_04

18 P2_05

19 P2_06

53

54

55

56

P1_05

P1_04

P1_03

P1_02

20

P2_07

21 P2_08

22 P2_09

P0_12

P2_00

P1_15

P2_02

35

36

37

45

23

P2_10

39 P0_09

40 P0_08

P1_00 47

P0_15

28 P0_06

50

P0_13 51

P0_07

P1_01

P1_12

p1_13

27

38

42

43

52

P2_01

P1_11

P0_14

41

46

P0_05

P0_04

24

26

57

58

P0_11

P0_14

44 P1_14

P1_10

P0_03

P0_02

P0_01

P0_00

59

60

61

62

63

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 28. Recommended External Components on VREF_ADC Pin and ADC Input Channel (ADC0_VIN0 Used as Example) when Using the Internal ADC

Rev. B | Page 35 of 39

ADuCM3027/ADuCM3029

Data Sheet

ABOUT ADuCM3027/ADuCM3029 SILICON ANOMALIES

This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM3027/ADuCM3029. These anomalies represent

the currently known differences between revisions of the ADuCM3027/ADuCM3029 product(s) and the functionality specified in the

ADuCM3027/ADuCM3029 data sheet(s) and the Hardware Reference manual.

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries

to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended

workarounds outlined in this section.

ADuCM30297/ADuCM3029 FUNCTIONALITY ISSUES

Silicon Revision Identifier

Silicon Status

No. of Reported Anomalies

1.2

Released

4 (21000011, 21000015, 21000016, 21000017)

A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading

Bits[3:0] of the SYS_CHIPID register. SYS_CHIPID = 0x4 indicates Silicon Revision 1.2.

FUNCTIONALITY ISSUES

Table 30 through Table 33 detail all known silicon anomalies for the ADuCM3027/ADuCM3029 including a description, workaround,

and identification of applicable silicon revisions.

Table 30. 21000011—I²C Master Mode Fails to Generate Clock

When the I²C clock dividers are configured in master mode such that the sum of the LOW bit in the I2C_DIV register

Background

and the HIGH bit in the I2C_DIV register is less than 16, the I²C fails to generate a clock.

Issue

Workaround

Related Issues

The I²C master mode fails to generate clock when clock dividers are too small.

Program the I²C clock dividers such that I2C_DIV.LOW + I2C_DIV.HIGH ≥ 16.

None.

Table 31. 21000015—Pin P2_11 Not Retained

Background

The state of the P2_11 pin is not retained after waking up from shutdown mode.

Issue

Pin P2_11 is not retained after shutdown wake up.

Workaround

Related Issues

None. To retain the pin state through shutdown, use any other GPIO pin instead of P2_11.

None.

Table 32. 21000016—Data Loss with I²C Automatic Clock Stretching

When the I²C Rx FIFO is full and new I²C data is received, a data overflow occurs. When automatic clock stretching is

Background

enabled, the transaction is paused by holding the SCL line low. This pause function works as expected when the

next read happens after the clock is stretched (for example, after the overflow is detected). However, if the read

occurs after the last bit of the I²C data is received but before the clock is stretched, the received data is not written

to the Rx FIFO and is lost.

Issue

Possible receive data loss with I²C automatic clock stretching.

After I²C automatic clock stretching is enabled, read the FIFO only after the overflow flag is set in the status register

to ensure the Rx FIFO is never read at the same time the overflow is asserted.

Workaround

Related Issues

None.

Rev. B | Page 36 of 39

Data Sheet

ADuCM3027/ADuCM3029

Table 33. 21000017—SPI Read Command Mode Does Not Work

When the SPI master is enabled and uses the DMA mode with SPI_CNT = 1, the read command mode may not

function properly. Consider the following configurations: SPI_RD_CTL = 0x07, SPI_CNT = 1, and the Tx and Rx DMA

channels configured for one half-word. In this configuration, the read command sent in the first byte on the MOSI

output is repeated in the second byte (in the address slot); thus, the slave device responds on the MISO line with

whatever content is at the address equivalent to the read command value (for example, if the read command is 0xB,

the response is the data read from Slave Address 0xB).

Background

Issue

Workaround

SPI read command mode does not work properly when SPI_CNT is 1 and DMA is enabled.

Use the overlap mode to align the transmit/receive SPI operations and discard the junk bytes, as follows:

Set the OVERLAP bit in the SPI_RD_CTL register = 1 to enable overlap mode.

Set the TXBYTES bit in the SPI_RD_CTL register = 1 to configure a single transmit byte (8-bit address register).

Set SPI_CNT.VALUE = 3 to configure the transfer count: one byte for the address register, one byte for the command,

and one dummy byte to obtain the read value, and on the receive side, discard the first two bytes received during

the transfer of the address and command bytes before processing the actual read value in the third byte.

Do not use Tx DMA operation on the SPI transmit side, as follows: enable only the SPI Rx DMA requests, fill the SPI Tx

FIFO by using core accesses to write to the SPI_TX register, and perform a dummy read of the SPI_RX register to

start the SPI transfers.

Related Issues

None.

Rev. B | Page 37 of 39

ADuCM3027/ADuCM3029

OUTLINE DIMENSIONS

Data Sheet

DETAIL A

(JEDEC 95)

9.10

0.30

0.25

0.20

9.00 SQ

8.90

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

49

64

(SEE DETAIL A)

1

48

0.50

BSC

4.60

4.50 SQ

4.40

EXPOSED

PAD

16

33

32

17

0.50

TOP VIEW

END VIEW

BOTTOM VIEW

0.20 MIN

0.40

0.30

7.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WMMD

Figure 29. 64-Lead Frame Chip Scale Package [LFCSP]

9 mm × 9 mm Body and 0.75 mm Package Height

(CP-64-16)

Dimensions shown in millimeters

2.800

2.760 SQ

2.720

0.210

12 10

8

6

4

2

3

1

0.108

13 11

9

7

5

A

B

C

D

E

F

0.35

BSC

BALL A1

IDENTIFIER

0.303

BSC

G

H

0.350

BSC

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.103

0.320

0.290

0.260

0.530

0.470

0.410

END VIEW

COPLANARITY

0.05

0.280

0.240

0.200

SEATING

PLANE

0.210

0.180

0.150

Figure 30. 54-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-54-1)

Dimensions shown in millimeters

Rev. B | Page 38 of 39

Data Sheet

ADuCM3027/ADuCM3029

ORDERING GUIDE

Package

Option

Model¹

Description

Temperature²

−40°C to +85°C

Package Description

54-Ball WLCSP, 13" Reel

54-Ball WLCSP, 7” Reel

64-Lead LFCSP

64-Lead LFCSP, 13”Reel

64-Lead LFCSP, 7”Reel

54-Ball WLCSP, 13” Reel

54-Ball WLCSP, 7” Reel

64-Lead LFCSP

64-Lead LFCSP, 13”Reel

64-Lead LFCSP, 7”Reel

64-Lead LFCSP

64-Lead LFCSP, 7”Reel

64-Lead LFCSP

ADuCM3027BCBZ-RL

ADuCM3027BCBZ-R7

ADuCM3027BCPZ

ADuCM3027BCPZ-RL

ADuCM3027BCPZ-R7

ADuCM3029BCBZ-RL

ADuCM3029BCBZ-R7

ADuCM3029BCPZ

ADuCM3029BCPZ-RL

ADuCM3029BCPZ-R7

ADuCM3029-1BCPZ

ADuCM3029-1BCPZ-R7

ADuCM3029-2BCPZ

ADuCM3029-2BCPZ-R7

EV-COG-AD3029LZ

EV-COG-AD3029WZ

ULP ARM Cortex-M3 with 128 kB Embedded Flash

ULP ARM Cortex-M3 with 256 kB Embedded Flash

ADuCM3029 LFCSP Development Board

CB-54-1

CP-64-16

CB-54-1

CP-64-16

64-Lead LFCSP, 7”Reel

ADuCM3029 WLCSP Development Board

¹Z = RoHS Compliant Part.

²Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Absolute Maximum Ratings section for junction temperature

(T_J) specification which is the only temperature specification.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D14168-0-5/19(B)

Rev. B | Page 39 of 39


型号：	ADUCM3027BCBZ-R7
厂家：	ADI
描述：	Ultra Low Power Arm Cortex-M3 MCU with Integrated Power Management
文件：	总39页 (文件大小：688K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADUCM3027BCBZ-R7 [ADI]

相关型号：

ADUCM3027BCBZ-RL

ADUCM3027BCPZ

ADUCM3027BCPZ-R7

ADUCM3027BCPZ-RL

ADUCM3029

ADUCM3029-1BCPZ

ADUCM3029-1BCPZ-R7

ADUCM3029-2BCPZ

ADUCM3029-2BCPZ-R7

ADUCM3029BCBZ-R7

ADUCM3029BCBZ-RL

ADUCM3029BCPZ