ADUCM3027BCPZ-R7 [ADI]
ADUCM3027BCPZ-R7;
| 型号： | ADUCM3027BCPZ-R7 |
| 厂家： | 
ADI |
| 描述： | ADUCM3027BCPZ-R7 外围集成电路 |
| 文件： | 总37页 (文件大小：1255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power ARM Cortex-M3 MCU
with Integrated Power Management
ADuCM3027/ADuCM3029
Hardware cryptographic accelerator supporting AES-128,
AES-256, and SHA-256
FEATURES
EEMBC ULPBench™ score: 245.5
DIGITAL PERIPHERALS
Ultralow power active and hibernate modes
Active (full on mode) < 30 μA/MHz (typical)
Flexi™ (core in sleep, peripherals active) < 300 μA (typical)
Hibernate (with SRAM retention) < 750 nA (typical)
Shutdown (optional RTC active) < 60 nA (typical)
ARM® Cortex®-M3 processor with MPU
Up to 26 MHz with serial wire debug interface
Power management
Single-supply operation (VBAT): 1.74 V to 3.6 V
Optional buck converter for improved efficiency
Memory options
128 KB/256 KB of embedded flash memory with ECC
4 KB of cache memory to reduce active power
64 KB of configurable system SRAM with parity
Up to 32 KB of SRAM retained in hibernate mode
Safety
3 SPI interfaces to enable glueless interface to sensors,
radios, and converters
I2C and UART interfaces
SPORT for natively interfacing with converters and radios
Programmable GPIOs (44 in LFCSP and 36 in WLCSP)
3 general-purpose timers with PWM support
RTC and FLEX_RTC with SensorStrobe™ and time stamping
Programmable beeper
25-channel DMA controller
CLOCKING FEATURES
26 MHz clock: on-chip oscillator, external crystal oscillator
32 kHz clock: on-chip oscillator, low power crystal oscillator
Integrated PLL with programmable divider
ANALOG PERIPHERALS
Watchdog with dedicated on-chip oscillator
Hardware CRC with programmable polynomial
Multiparity bit protected SRAM
12-bit SAR ADC, 1.8 MSPS, 8 channels, digital comparator
APPLICATIONS
Internet of Things (IoT)
ECC protected embedded flash
Smart machine, smart metering, smart building,
smart city, smart agriculture
Wearables
Security
TRNG
User code protection
Fitness and clinical
26 MHz CORE RATE
SERIAL-WIRE
PLL
INSTRUCTION
RAM/CACHE
(32 KB)
HFXTAL
LFXTAL
POWER
MANAGEMENT
ARM
CORTEX-M3
MULTI-
LAYER
AMBA
BUS
FLASH
(256 KB)
HFOSC
LFOSC
BUCK
SRAM0
(16 KB)
NVIC
MPU
WIC
MATRIX
REF BUFFER
SRAM1
(16 KB)
TEMP
SENSOR
DMA
CRYPTO
(AES 128/256,
SHA 256)
ADC
SPORT
SPI
UART
TMR0
TMR2
TMR1
RTC0
RTC1
AHB
-APB
BRIDGE
2
I C
SPI
SPI
TRNG
WDT
BEEPER
GPIO
PROGRAMMABLE
CRC POLYNOMIAL
Figure 1. Functional Block Diagram
Rev. 0
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©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
ADuCM3027/ADuCM3029
TABLE OF CONTENTS
General Description ................................................. 3
Highlights ........................................................... 3
ARM Cortex-M3 Processor ..................................... 3
Memory Architecture ............................................ 4
System and Integration Features ............................... 5
On-Chip Peripheral Features ................................. 10
Development Support .......................................... 10
Additional Information ........................................ 11
Reference Designs ............................................... 11
Security Features Disclaimer .................................. 11
Specifications ........................................................ 12
Operating Conditions .......................................... 12
Electrical Characteristics ....................................... 12
System Clocks/Timers .......................................... 14
ADC Specifications .............................................. 15
Flash Specifications .............................................. 15
Absolute Maximum Ratings ................................... 16
ESD Sensitivity ................................................... 16
Package Information ............................................ 16
Timing Specifications ........................................... 17
MCU Test Conditions .......................................... 25
Driver Types ...................................................... 25
Environmental Conditions .................................... 28
Pin Configuration And Function Description ................ 29
Outline Dimensions ................................................ 36
Ordering Guide ..................................................... 37
REVISION HISTORY
3/2017—Revision 0: Initial Version
Rev. 0
| Page 2 of 37 | March 2017
ADuCM3027/ADuCM3029
GENERAL DESCRIPTION
The ADuCM3027/ADuCM3029 microcontroller units (MCUs)
are ultra low power microcontroller systems with integrated
power management for processing, control, and connectivity.
The MCU system is based on the ARM Cortex-M3 processor, a
collection of digital peripherals, embedded SRAM and flash
memory, and an analog subsystem which provides clocking,
reset, and power management capability in addition to an
analog-to-digital converter (ADC) subsystem. For a feature
comparison across the ADuCM3027/ADuCM3029 product
offerings, see Table 1.
HIGHLIGHTS
The following are the key features of the ADuCM3027/
ADuCM3029 MCUs:
• Industry leading ultralow power consumption.
• Robust operation.
• Full voltage monitoring in deep sleep modes.
• ECC support on flash.
• Parity error detection on SRAM memory.
• Leading edge security.
Table 1. Product Flash Memory Options
• Fast encryption provides read protection to customer
algorithms.
Device
Embedded Flash Memory Size
ADuCM3029
ADuCM3027
256 KB
128 KB
• Write protection prevents device reprogramming by
unauthorized code.
• Failure detection of 32 kHz LFXTAL via interrupt.
System features that are common across the ADuCM3027/
ADuCM3029 MCUs include the following:
• SensorStrobe for precise time synchronized sampling of
external sensors.
• Up to 26 MHz ARM Cortex-M3 processor
• Works in hibernate mode, resulting in drastic current
reduction in system solutions. Current consumption
reduces by 10 times when using, for example, the
ADXL363 accelerometer.
• Up to 256 KB of embedded flash memory with error cor-
rection code (ECC)
• Optional 4 KB cache for lower active power
• 64 KB system SRAM with parity
• Software intervention is not required after setup.
• No pulse drift due to software execution.
• Power management unit (PMU)
• Multilayer advanced microcontroller bus architecture
(AMBA) bus matrix
ARM CORTEX-M3 PROCESSOR
The ARM Cortex-M3 core is a 32-bit reduced instruction set
computer (RISC). The length of the data can be 8 bits, 16 bits, or
32 bits. The length of the instruction word is 16 bits or 32 bits.
• Central direct memory access (DMA) controller
• Beeper interface
• Serial port (SPORT), serial peripheral interface (SPI), inter-
integrated circuit (I2C), and universal asynchronous
receiver/transmitter (UART) peripheral interfaces
The processor has the following features:
• Cortex-M3 architecture
• Thumb-2 instruction set architecture (ISA)
technology
• Cryptographic hardware support with advanced encryp-
tion standard (AES) and secure hash algorithm (SHA) -256
• Three-stage pipeline with branch speculation
• Low latency interrupt processing with tail chaining
• Single-cycle multiply
• Real-time clock (RTC)
• General-purpose and watchdog timers
• Programmable general-purpose input/output (GPIO) pins
• Hardware divide instructions
• Hardware cyclic redundancy check (CRC) calculator with
programmable generator polynomial
• Nested vectored interrupt controller (NVIC) (64 inter-
rupts and 8 priorities)
• Power-on reset (POR) and power supply monitor (PSM)
• 12-bit successive approximation register (SAR) ADC
• True random number generator (TRNG)
• Two hardware breakpoints and one watchpoint
(unlimited software breakpoints using Segger JLink)
• Memory protection unit (MPU)
To support low dynamic and hibernate power management, the
ADuCM3027/ADuCM3029 MCUs provide a collection of
power modes and features, such as dynamic and software con-
trolled clock gating and power gating.
• Eight-region MPU with subregions and background
region
• Programmable clock generator unit
For full details on the ADuCM3027/ADuCM3029 MCUs, refer
to the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU
with Integrated Power Management Hardware Reference.
Rev. 0
| Page 3 of 37 | March 2017
ADuCM3027/ADuCM3029
• Configurable for ultralow power operation
• Deep sleep mode, dynamic power management
• Programmable clock generator unit
SRAM Region
This memory space contains the application instructions and
literal (constant) data that must be accessed in real-time. It sup-
ports read/write access by the ARM Cortex-M3 core and
read/write DMA access by system peripherals. Byte, half-word,
and word accesses are supported.
ARM Cortex-M3 Memory Subsystem
The memory map of the ADuCM3027/ADuCM3029 is based
on the Cortex-M3 model from ARM. By retaining the standard-
ized memory mapping, it is easier to port applications across
M3 platforms.
SRAM is divided into 32 KB data SRAM and 32 KB instruction
SRAM. If instruction SRAM is not enabled, then the associated
32 KB can be mapped as data SRAM, resulting in 64 KB of data
SRAM.
The ADuCM3027/ADuCM3029 application development is
based on memory blocks across code/SRAM regions. Internal
memory is available via internal SRAM and internal flash.
Parity bit error detection (optional) is available on all SRAM
memories. Two parity bits are associated with each 32-bit word.
Code Region
When the cache controller is enabled, 4 KB of the instruction
SRAM is reserved as cache memory.
Accesses in this region (0x0000 0000 to 0x0001 FC00 for the
ADuCM3027 and 0x0000 0000 to 0x0003 FFFF for the
ADuCM3029) are performed by the core and target the memory
and cache resources.
Users can select the SRAM configuration modes depending on
the instruction SRAM and cache needed.
In hibernate mode, 8 KB to 32 KB of the SRAM can be retained
in increments of 8 KB. 8 KB of data SRAM is always retained.
Users can additionally retain
SRAM Region
Accesses in this region (0x2000 0000 to 0x2004 7FFF) are per-
formed by the ARM Cortex-M3 core. The SRAM region of the
core can otherwise act as a data region for an application.
• 16 KB out of 32 KB of instruction SRAM
• 8 KB out of 32 KB of data SRAM
• Internal SRAM Data Region. This space can contain
read/write data. Internal SRAM can be partitioned between
code and data (SRAM region in M3 space) in 32 KB blocks.
Access to this region occurs at core clock speed with no
wait states.
It also supports read/write access by the Cortex-M3 core
and read/write DMA access by system devices. It supports
exclusive memory accesses via the global exclusive access
monitor within the Cortex-M3 platform.
MMRs (Peripheral Control and Status)
For the address space containing MMRs, refer to Figure 2.
These registers provide control and status for on-chip peripher-
als of the ADuCM3027/ADuCM3029. For more information
about the MMRs, refer to the ADuCM302x Ultra Low Power
ARM Cortex-M3 MCU with Integrated Power Management
Hardware Reference.
Flash Memory
• System MMRs. Various system memory mapped registers
(MMRs) reside in this region.
The ADuCM3027/ADuCM3029 MCUs include 128 KB to
256 KB of embedded flash memory, which is accessed using a
flash controller. For memory available on each product, see
Table 1. The flash controller is coupled with a cache controller.
A prefetch mechanism is implemented in the flash controller to
optimize code performance.
System Region
Accesses in this region (0xE000 0000 to 0xF7FF FFFF) are per-
formed by the ARM Cortex-M3 core and are handled within the
Cortex-M3 platform.
Flash writes are supported by a key hole mechanism via
advanced peripheral bus (APB) writes to MMRs. The flash con-
troller provides support for DMA-based key hole writes.
• CoreSight™ ROM. The read only memory (ROM) table
entries point to the debug components of the processor.
• ARM APB Peripheral. This space is defined by ARM and
occupies the bottom 256 KB/128 KB of the system (SYS)
region (0xE000 0000 to 0xE004 0000) depending on the
device used. The space supports read/write access by the
M3 core to the internal peripherals of the ARM core
(NVIC, system control space (SCS), wake-up interrupt
controller (WIC)) and CoreSight ROM. It is not accessible
by system DMA.
With respect to flash integrity, the devices support the
following:
• A fixed user key required for running protected com-
mands, including mass erase and page erase.
• An optional and user definable user failure analysis key
(FAA key). Analog Devices personnel need this key while
performing failure analysis.
MEMORY ARCHITECTURE
• An optional and user definable write protection for user
accessible memory.
The internal memory of the ADuCM3027/ADuCM3029 is
shown in Figure 2. It incorporates up to 256 KB of embedded
flash memory for program code and nonvolatile data storage, 32
KB of data SRAM, and 32 KB of SRAM (configured as instruc-
tion space or data space).
• An optional 8-bit ECC. It is enabled by default. It is recom-
mended not to disable ECC.
Rev. 0
| Page 4 of 37 | March 2017
ADuCM3027/ADuCM3029
RESERVED
REAL TIME CLOCK 0 (RTC0)
RESERVED
0x4000 1044
0x4000 1000
0x400F FFFF
0x4001 0FE0
0x4001 0000
DMA 0
RESERVED
RESERVED
0x4004 C80C
0x4004 C000
POWER MGT, EXT IRQ,
CLOCKING, & MISC MMR
RESERVED
0x4000 0824
0x4000 0800
GENERAL-PURPOSE TIMER 2
RESERVED
0x4000 5C0C
0x4000 5C00
BEEPER 0
0x4004 406C
0x4004 4000
RESERVED
0x4000 0424
0x4000 0400
CRYPTO
RESERVED
GENERAL-PURPOSE TIMER 1
RESERVED
0x4000 5030
0x4000 5000
UART 0
0x4004 0414
0x4004 0400
RESERVED
0x4000 0024
0x4000 0000
RANDOM NUMBER GENERATOR
RESERVED
GENERAL-PURPOSE TIMER 0
RESERVED
0x4000 4438
0x4000 4400
SPI 1 MASTER/SLAVE
RESERVED
0x4004 000C
0x4004 0000
0x2004 7FFF
0x2004 4000
0x2004 3FFF
0x2004 0000
0x2000 7FFF
0x2000 4000
0x2000 3FFF
PROGRAMMABLE CRC ENGINE
RESERVED
RAM BANK 1* (16K BYTES)
0x4000 4038
0x4000 4000
SPI 0 MASTER/SLAVE
RESERVED
RAM BANK 1 (16K BYTES)
RESERVED
0x4003 8078
0x4003 8000
SPORT 0
0x4000 3058
0x4000 3000
2
I C 0 MASTER/SLAVE
RESERVED
RAM BANK 0* (16K BYTES)
0x4002 4038
0x4002 4000
RESERVED
WATCHDOG TIMER
RESERVED
SPIH 0 MASTER/SLAVE
RESERVED
0x4000 2C18
0x4000 2C00
RAM BANK 0 (16K BYTES)
RESERVED
0x2000 0000
0x4002 00B4
0x4002 0000
GPIO
0x1000 7FFF
0x1000 0000
0x4000 2040
0x4000 2000
INSTRUCTION SRAM* (32K BYTES)
RESERVED
SYSTEM ID AND DEBUG ENABLE
RESERVED
RESERVED
0x4001 8088
0x4001 8000
FLASH CONTROLLER
RESERVED
0x4000 1444
0x4000 1400
0x0003 FFFC
0x0000 0000
256K BYTES FLASH MEMORY
REAL TIME CLOCK 1 (RTC1)
Figure 2. ADuCM3027/ADuCM3029 Memory Map
In this mode, an on-chip loader routine initiates in the kernel,
which configures the UART port and communicates with the
host to manage the firmware upgrade via a specific serial down-
load protocol.
Cache Controller
The ADuCM3027/ADuCM3029 MCUs have an optional 4 KB
instruction cache. In certain applications, enabling the cache
and executing the code can result in lower power consumption
than operating directly from flash. When the cache controller is
enabled, 4 KB of instruction SRAM is reserved as cache mem-
ory. In hibernate mode, the cache memory is not retained.
Table 2. Boot Modes
Boot Mode Description
0
1
UART download mode.
SYSTEM AND INTEGRATION FEATURES
Flash boot. Boot from integrated flash memory.
The ADuCM3027/ADuCM3029 MCUs provide several features
that ease system integration.
Power Management
Reset
The ADuCM3027/ADuCM3029 MCUs have an integrated
power management system that optimizes performance and
extends battery life of the devices.
There are four types of resets: external, power-on, watchdog
timeout, and software system reset. The software system reset is
provided as part of the Cortex-M3 core.
The power management system consists of the following:
The SYS_HWRST pin is toggled to perform a hardware reset.
• Integrated 1.2 V low dropout regulator (LDO) and optional
capacitive buck regulator
Booting
• Integrated power switches for low standby current in hiber-
nate and shutdown modes
The ADuCM3027/ADuCM3029 MCUs support two boot
modes: booting from internal flash and upgrading software
through UART download. If the SYS_BMODE0 pin (GPIO17)
is pulled low during power-up or a hard reset, the MCU enters
into serial download mode.
Rev. 0
| Page 5 of 37 | March 2017
ADuCM3027/ADuCM3029
Additional power management features include the following:
• Customized clock gating for active and Flexi modes
• Power gating to reduce leakage in hibernate and shutdown
modes
VBAT
VDCDC_CAP1P
VDCDC_CAP1N
VDCDC_OUT
0.1μF
0.1μF
BUCK
(ENABLED)
• Flexible sleep modes
0.47μF
VDCDC_CAP2P
VDCDC_CAP2N
• Shutdown mode with no retention
• Optional high efficiency buck converter to reduce power
• Integrated low power oscillators
Power Modes
The PMU provides control of the ADuCM3027/ADuCM3029
power modes and allows the ARM Cortex-M3 to control the
clocks and power gating to reduce the power consumption.
Several power modes are available. Each mode provides an
additional low power benefit with a corresponding reduction in
functionality.
VLDO_OUT
0.47μF
LDO
• Active mode. All peripherals can be enabled. Active power
is managed by optimized clock management. See Table 4
for details on active mode power.
Note: For designs in which the optional buck is not used, the
following pins must be left unconnected—VDCDC_CAP1P,
VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, and
VDCDC_CAP2N.
• Flexi mode. The ARM Cortex-M3 core is clock gated, but
the remainder of the system is active. No instructions can
be executed in this mode, but DMA transfers can continue
between peripherals and memory as well as memory to
memory. See Table 5 for details on Flexi mode power.
Figure 3. Buck Enabled Design
Security Features
• Hibernate mode. This mode provides state retention, con-
figurable SRAM and port pin retention, a limited number
of wake-up interrupts (XINT0_WAKEn and UART0_RX),
and, optionally, two RTCs—RTC0 and RTC1
(FLEX_RTC).
The ADuCM3027/ADuCM3029 MCUs provide a combination
of hardware and software protection mechanisms that lock out
access to the devices in secure mode, but grant access in open
mode. These mechanisms include password protected slave
boot mode (UART), as well as password protected serial wire
debug (SWD) interfaces.
• Shutdown mode. This mode is the deepest sleep mode, in
which all the digital and analog circuits are powered down
with an option to wake from four possible wake-up
sources: three external interrupts and RTC0. The RTC0 can
be optionally enabled in this mode and the device can be
periodically woken up by the RTC0 interrupt. See Table 6
for deep sleep (hibernate and shutdown) mode
specifications.
Mechanisms are provided to protect the device contents (flash,
SRAM, CPU registers, and peripheral registers) from being read
through an external interface by an unauthorized user. This is
referred to as read protection.
It is possible to protect the device from being reprogrammed in
circuit with unauthorized code. This is referred to as in circuit
write protection.
The following features are available for power management and
control:
CAUTION
• A voltage range of 1.74 V to 3.6 V, using a single supply
(such as the CR2032 coin cell battery).
This product includes security features that can be
used to protect embedded nonvolatile memory
contents and prevent execution of unauthorized
code. When security is enabled on this device
(either by the ordering party or the subsequent
receiving parties), the ability of Analog Devices to
conduct failure analysis on returned devices is
limited. Contact Analog Devices for details on the
failure analysis limitations for this device.
• GPIOs are driven directly from the battery. The pin state is
retained in hibernate and shutdown modes. The GPIO
configuration is only retained in hibernate mode.
• Wake-up from external interrupt (via GPIOs), UART0_RX
interrupt, and RTCs for hibernate mode.
• Wake-up from external interrupt (via GPIOs) and RTC0
for shutdown mode.
The devices can be configured with no protection, read protec-
tion, or read and in circuit write protection. It is not necessary
to provide in circuit write protection without read protection.
• Optional high power buck converter for 1.2 V full on sup-
port; for MCU usage only. See Figure 3 for the suggested
external circuitry.
Rev. 0
| Page 6 of 37 | March 2017
ADuCM3027/ADuCM3029
• Initial seed to be programmed by user.
Cryptographic Accelerator
• DMA controller (memory to memory transfer) used for
data transfer to offload the MCU.
The cryptographic accelerator is a 32-bit APB DMA capable
peripheral. There are two 32-bit buffers provided for data
input/output operations. These buffers read in or read out
128 bits in four data accesses. Big endian and little endian data
formats are supported, as are the following modes:
Programmable GPIOs
The ADuCM3027/ADuCM3029 MCUs have 44 and 36 GPIO
pins in the LFCSP and WLCSP packages, respectively, with
multiple, configurable functions defined by user code. They can
be configured as an input/output and have programmable pull-
up resistors. All GPIO pins are functional over the full supply
range.
• Electronic code book (ECB) mode—AES mode
• Counter (CTR) mode
• Cipher block chaining (CBC) mode
• Message authentication code (MAC) mode
In deep sleep mode, GPIO pins retain their state. On reset, they
tristate.
• Cipher block chaining-message authentication code
(CCM/CCM*) mode
Timers
• SHA-256 modes
The ADuCM3027/ADuCM3029 MCUs have three general-pur-
pose timers and a watchdog timer.
True Random Number Generator (TRNG)
The TRNG is used during operations where nondeterministic
values are required. This can include generating challenges for
secure communication or keys for an encrypted communication
channel. The generator can run multiple times to generate a suf-
ficient number of bits for the strength of the intended operation.
The TRNG can seed a deterministic random bit generator.
General-Purpose Timers
The ADuCM3027/ADuCM3029 MCUs have three identical
general-purpose timers, each with a 16-bit up and down
counter. The up and down counter can be clocked from one of
four user selectable clock sources. Any selected clock source can
be scaled down using a prescaler of 1, 16, 64, or 256.
Reliability and Robustness Features
Watchdog Timer (WDT)
The ADuCM3027/ADuCM3029 MCUs provide a number of
features that can enhance or help achieve certain levels of sys-
tem safety and reliability. While the level of safety is mainly
dominated by system considerations, the following features are
provided to enhance robustness:
The WDT is a 16-bit count down timer with a programmable
prescaler. The prescaler source is selectable and can be scaled by
a factor of 1, 16, or 256. The watchdog timer is clocked by the
32 kHz on-chip oscillator (LFOSC) and recovers from an illegal
software state. The WDT requires periodic servicing to prevent
it from forcing a reset or interrupt to the MCU.
• ECC enabled flash memory. The entire flash array can be
protected to either correct single-bit errors or detect two-
bit errors per 64-bit flash data (enabled by default).
Analog-to-Digital Converter (ADC) Subsystem
• Multiparity bit protected SRAM. Each word of the SRAM
and cache memory is protected by multiple parity bits to
allow detection of random soft errors.
The ADuCM3027/ADuCM3029 MCUs integrate a 12-bit SAR
ADC with up to eight external channels. Conversions can be
performed in single or autocycle mode. In single mode, the
ADC can be configured to convert on a particular channel by
selecting one of the channels. Autocycle mode is provided to
reduce MCU overhead of sampling and reading individual
channel registers. The ADC can also be used for temperature
sensing and measuring battery voltage using dedicated chan-
nels. Temperature sensing and battery monitoring cannot be
included with external channels in autocycle mode.
• Software watchdog. The on-chip watchdog timer can pro-
vide software-based supervision of the ADuCM3027/
ADuCM3029.
Cyclic Redundancy Check (CRC) Accelerator
The CRC accelerator computes the CRC for a block of memory
locations. The exact memory location can be in the SRAM,
flash, or any combination of MMRs. The CRC accelerator gen-
erates a checksum that can be compared with an expected
signature.
A digital comparator triggers an interrupt if ADC input is above
or below a programmable threshold. The ADC0_VIN0,
ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3 input channels
can be used with the digital comparator.
The main features of the CRC include the following:
• Generates a CRC signature for a block of data.
• Supports programmable polynomial length of up to 32 bits.
• Operates on 32 bits of data at a time.
Use the ADC in DMA mode to reduce MCU overhead by mov-
ing ADC results directly into SRAM with a single interrupt
asserted when the required number of ADC conversions has
been completely logged to memory.
• Supports MSB first and LSB first CRC implementations.
• Various data mirroring capabilities.
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ADuCM3027/ADuCM3029
The main features of the ADC subsystem include the following:
• 12-bit resolution.
Real-Time Clock (RTC)
The ADuCM3027/ADuCM3029 MCUs have two real-time
clock blocks—RTC0 and RTC1 (FLEX_RTC). The clock blocks
share a low power crystal oscillation circuit that operates in con-
junction with a 32,768 Hz external crystal.
• Programmable ADC update rate from 10 KSPS to
1.8 MSPS.
• Integrated input multiplexer that supports up to eight
channels.
The RTC has an alarm that interrupts the core when the pro-
grammed alarm value matches the RTC count. The software
enables and configures the RTC.
• Temperature sensing support.
• Battery monitoring support.
The RTC also has a digital trim capability to allow a positive or
negative adjustment to the RTC count at fixed intervals.
• Software selectable on-chip reference voltage
generation—1.25 V and 2.5 V.
The FLEX_RTC supports SensorStrobe mechanism. Using this
mechanism, the ADuCM3027/ADuCM3029 MCUs can be used
as a programmable clock generator in some power modes,
including hibernate mode. In this way, the external sensors can
have their timing domains mastered by the ADuCM3027/
ADuCM3029 MCUs, as SensorStrobe can output a programma-
ble divider from the FLEX_RTC, which can operate up to a
resolution of 30.7 μs. The sensors and MCU are in sync, which
removes the need for additional resampling of data to time align
it.
• Software selectable internal or external reference.
• Autocycle mode—ability to automatically select a sequence
of input channels for conversion.
• Averaging function—converted data on single or multiple
channels can be averaged up to 256 samples.
• Alert function—internal digital comparator for
ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and
ADC0_VIN3 channels. An interrupt is generated if the dig-
ital comparator detects an ADC result above or below a
user defined threshold.
In the absence of this mechanism,
• The external sensor uses an RC oscillator (~ 30ꢀ typical
variation). The MCU must sample the data and resample it
on the time domain of the MCU before using it.
• Dedicated DMA channel support.
• Each channel, including temperature sensor and battery
monitoring, has a data register for conversion result.
Or
• The MCU remains in a higher power state and drives each
data conversion on the sensor side.
Clocking
The ADuCM3027/ADuCM3029 MCUs have the following
clocking options:
This mechanism allows the ADuCM3027/ADuCM3029 MCUs
to be in a lower power state for a long duration and avoids
unnecessary data processing which extends the battery life of
the end product.
• 26 MHz
• Internal oscillator—HFOSC (26 MHz)
• External crystal oscillator—HFXTAL (26 MHz or
16 MHz)
• GPIO clock in—SYS_CLKIN
• 32 kHz
• Internal oscillator—LFOSC
• External crystal oscillator—LFXTAL
The clock options have software configurability with the follow-
ing exceptions:
• HFOSC cannot be disabled when using an internal buck
regulator.
• LFOSC cannot be disabled even if using LFXTAL.
Rev. 0
| Page 8 of 37 | March 2017
ADuCM3027/ADuCM3029
The key differences between RTC0 and RTC1 (FLEX_RTC) are
shown in Table 3.
Table 3. RTC Features
Features
RTC0
RTC1 (FLEX_RTC)
Resolution of Time Counts time at 1 Hz in units of seconds. Operationally, always Can prescale the clock by any power of two from 0 to 15.
Base (Prescaling) prescales to 1 Hz (for example, divide by 32,768) and always It can count time in units of any of these 16 possible
counts real time in units of seconds.
prescale settings. For example, the clock can be prescaled
by 1, 2, 4, 8, …, 16384, or 32768.
Source Clock
LFXTAL.
Depending on the low frequency multiplexer (LFMUX)
configuration, the RTC is clocked by the LFXTAL or the
LFOSC.
Wake-Up Timer
Wake-up time is specified in units of seconds.
Supports alarm times down to a resolution of 30.7 μs, that
is, where the time is specified down to a specific 32 kHz
clock cycle.
Number of Alarms One alarm only. Uses an absolute, nonrepeating alarm time, Two alarms. One absolute alarm time and one periodic
specified in units of 1 sec.
alarm, repeating every 60 prescaled time units.
SensorStrobe
Mechanism
Not available.
SensorStrobe is an alarm mechanism in the RTC that
causes an output pulse to be sent via GPIOs to an external
device to instruct the device to take a measurement or
perform some action at a specific time. SensorStrobe
events are scheduled at a specific target time relative to
the real-time count of the RTC. SensorStrobe can be
enabled in active, Flexi, and hibernate modes.
Input Capture
Not available.
Input capture takes a snapshot of the RTC when an
external device signals an event via a transition on one of
the GPIO inputs to the ADuCM3027/ ADuCM3029.
Typically, an input-capture event is triggered by an auton-
omous measurement or action on such a device, which
then signals to the ADuCM3027/ ADuCM3029 that the
RTC must take a snapshot of time corresponding to the
event.Taking the snapshot can wake up theADuCM3027/
ADuCM3029 and cause an interrupt to the CPU. The CPU
cansubsequently obtaininformation from the RTC on the
exact 32 kHz cycle on which the input capture event
occurred.
Rev. 0
| Page 9 of 37 | March 2017
ADuCM3027/ADuCM3029
Serial ports operate in two modes:
• Standard digital signal processor (DSP) serial mode
• Timer enable mode
Beeper Driver
The ADuCM3027/ADuCM3029 MCUs have an integrated
audio driver for a beeper.
The beeper driver module in the ADuCM3027/ADuCM3029
MCUs generate a differential square wave of programmable fre-
quency. It drives an external piezoelectric sound component
with two terminals that connect to the differential square wave
output.
Serial Peripheral Interface (SPI) Ports
The ADuCM3027/ADuCM3029 MCUs provide three SPIs. SPI
is an industry standard, full-duplex, synchronous serial inter-
face that allows eight bits of data to be synchronously
transmitted and simultaneously received. Each SPI incorporates
two DMA channels that interface with the DMA controller. One
DMA channel transmits and the other receives. The SPI on the
MCU eases interfacing to external serial flash devices.
The beeper driver consists of a module that can deliver frequen-
cies ranging from 8 kHz to ~0.25 kHz. It operates on a fixed
independent 32 kHz clock source that is unaffected by changes
in system clocks.
The SPI features include the following:
• Serial clock phase mode and serial clock polarity mode
• Loopback mode
It allows programmable tone durations from 4 ms to 1.02 sec in
4 ms increments. Pulse (single-tone) and sequence (multitone)
modes provide versatile playback options.
In sequence mode, the beeper can be programmed to play any
number of tone pairs from 1 to 254 (2 to 508 tones) or be pro-
grammed to play forever (until stopped by the user). Interrupts
are available to indicate the start or end of any beep, the end of a
sequence, or when the sequence is nearing completion.
• Continuous and repeated transfer mode
• Wired OR output mode
• Read command mode for half-duplex operation (transmit
followed by receive)
• Flow control support in read command mode
• Support for 3-pin SPI in read command mode
• Multiple CS line support
Debug Capability
The ADuCM3027/ADuCM3029 MCUs support SWD.
ON-CHIP PERIPHERAL FEATURES
• CS software override support
The ADuCM3027/ADuCM3029 MCUs have a rich set of
peripherals connected to the core via several concurrent high
bandwidth buses, providing flexibility in system configuration
as well as excellent overall system performance (see Figure 1).
UART Port
The ADuCM3027/ADuCM3029 MCUs provide a full-duplex
UART port, which is fully compatible with PC standard UARTs.
The UART port provides a simplified UART interface to other
peripherals or hosts, supporting full-duplex, DMA, and asyn-
chronous transfers of serial data. The UART port includes
support for five to eight data bits, and none, even, or odd parity.
A frame is terminated by one, one and a half, or two stop bits.
The ADuCM3027/ADuCM3029 MCUs contain high speed
serial ports, an interrupt controller for flexible management of
interrupts from the on-chip peripherals or external sources, and
power management control functions to tailor the performance
and power characteristics of the MCU and system to many
application scenarios.
I2C
Serial Ports (SPORT)
The ADuCM3027/ADuCM3029 MCUs provide an I2C bus
peripheral that has two pins for data transfer. SCL is a serial
clock pin and SDA is a serial data pin. The pins are configured
in a wired AND format that allows arbitration in a multimaster
system. A master device can be configured to generate the serial
clock. The frequency is programmed by the user in the serial
clock divisor register. The master channel can operate in fast
mode (400 kHz) or standard mode (100 kHz).
The ADuCM3027/ADuCM3029 MCUs provide two single
direction half SPORTs or one bidirectional full SPORT. The
synchronous serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices such
as Analog Devices audio codecs, ADCs, and DACs. The serial
ports contain two data lines, a clock, and a frame sync. The data
lines can be programmed to either transmit or receive, and each
data line has a dedicated DMA channel.
DEVELOPMENT SUPPORT
Serial port data can be automatically transferred to and from
on-chip memory or external memory via dedicated DMA chan-
nels. The frame sync and clock can be shared. Some of the ADCs
and DACs require two control signals for their conversion pro-
cess. To interface with such devices, the SPT0_ACNV and
SPT0_BCNV signals are provided. To use these signals, enable
the timer enable mode. In this mode, a PWM timer inside the
module generates the programmable SPT0_ACNV and
SPT0_BCNV signals.
Development support for the ADuCM3027/ADuCM3029
MCUs includes documentation, evaluation hardware, and
development software tools.
Documentation
The ADuCM302x Ultra Low Power ARM Cortex-M3 MCU
with Integrated Power Management Hardware Reference details
the functionality of each block on the ADuCM3027/
ADuCM3029 MCUs. It includes power management, clocking,
memories, and peripherals.
Rev. 0
| Page 10 of 37 | March 2017
ADuCM3027/ADuCM3029
Hardware
REFERENCE DESIGNS
The ADuCM3029 EZ-KIT® is available to prototype sensor con-
figurations with the ADuCM3027/ADuCM3029 MCUs.
The Circuits from the Lab® page provides the following:
• Graphical circuit block diagram presentation of signal
chains for a variety of circuit types and applications
Software
• Drill down links for components in each chain to selection
guides and application information
The ADuCM3029 EZ-KIT includes a complete development
and debug environment for the ADuCM3027/ADuCM3029
MCUs. The board support package (BSP) for the ADuCM3027/
ADuCM3029 is provided for the IAR Embedded Workbench
for ARM, Keil™, and CrossCore® embedded studio (CCES)
environments.
• Reference designs applying best practice design techniques
SECURITY FEATURES DISCLAIMER
To our knowledge, the Security Features, when used in accor-
dance with the data sheet and hardware reference manual
specifications, provide a secure method of implementing code
and data safeguards. However, Analog Devices does not guaran-
tee that this technology provides absolute security.
The BSP also includes operating system (OS) aware drivers and
example code for all the peripherals on the devices.
ADDITIONAL INFORMATION
ACCORDINGLY, ANALOG DEVICES HEREBY DISCLAIMS
ANY AND ALL EXPRESS AND IMPLIED WARRANTIES
THAT THE SECURITY FEATURES CANNOT BE
BREACHED, COMPROMISED, OR OTHERWISE CIRCUM-
VENTED AND IN NO EVENT SHALL ANALOG DEVICES
BE LIABLE FOR ANY LOSS, DAMAGE, DESTRUCTION, OR
RELEASE OF DATA, INFORMATION, PHYSICAL PROP-
ERTY, OR INTELLECTUAL PROPERTY.
The following publications that describe the ADuCM3027/
ADuCM3029 MCUs can be ordered from any Analog Devices
sales office or accessed electronically on the Analog Devices
website:
•
ADuCM302x Ultra Low Power ARM Cortex-M3 MCU
with Integrated Power Management Hardware Reference.
•
ADuCM3027/ADuCM3029 Anomaly List
This data sheet describes the ARM Cortex-M3 core and mem-
ory architecture used on the ADuCM3027/ADuCM3029
MCUs, but does not provide detailed programming information
for the ARM processor. For more information about program-
ming the ARM processor, visit the ARM Infocenter web page.
The applicable documentation for programming the ARM Cor-
tex-M3 processor include the following:
• ARM Cortex-M3 Devices Generic User Guide
• ARM Cortex-M3 Technical Reference Manual
Rev. 0
| Page 11 of 37 | March 2017
ADuCM3027/ADuCM3029
SPECIFICATIONS
For information about product specifications, contact your Analog Devices, Inc. representative.
OPERATING CONDITIONS
Parameter
Conditions
Min
1.74
2.5
Typ
Max
Unit
V
1, 2
VBAT
External Battery Supply Voltage
High Level Input Voltage
Low Level Input Voltage
ADC Supply Voltage
3.0
3.6
VIH
VIL
VBAT = 3.6 V
V
VBAT = 1.74 V
0.45
3.6
V
VBAT
1.74
−40
3.0
V
_
ADC
TJ
Junction Temperature
TAMBIENT = −40°C to +85°C
+85
°C
1 The voltage must remain powered even if the associated function is not used.
2 Value applies to the VBAT_ANA1,VBAT_ANA2,VBAT_DIG1, and VBAT_DIG2 pins.
ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Min
Typ
Max
Unit
V
1
VOH
High Level Output Voltage
VBAT = minimum V, IOH = −1.0 mA
VBAT = minimum V, IOL = 1.0 mA
VBAT =maximum V, VIN = maximum VBAT
VBAT =maximum V, VIN = 0 V
1.4
1
VOL
Low Level Output Voltage
0.4
1
V
2
IIHPU
High Level Input Current Pull-Up
Low Level Input Current Pull-Up
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pull-Up
Three-State Leakage Current Pull-Up
0.01
μA
μA
μA
μA
μA
μA
μA
μA
pF
2
IILPU
100
1
3
IOZH
VBAT = maximum V, VIN = maximum VBAT
VBAT = maximum V, VIN = 0 V
0.01
0.01
3
IOZL
1
4
IOZLPU
VBAT = maximum V, VIN = 0 V
100
1
4
IOZHPU
VBAT = maximum V, VIN = maximum VBAT
5
IOZLPD
Three-State Leakage Current Pull-Down VBAT = maximum V, VIN = 0 V
1
5
IOZHPD
Three-State Leakage Current Pull-Down VBAT = maximum V, VIN = maximum VBAT
100
CIN
Input Capacitance
TJ = 25°C
10
1 Applies to the output and bidirectional pins: P1_10, P0_10, P0_11, P1_02, P1_03, P1_04, P1_05, P2_01, P0_13, P0_15, P1_00, P1_01, P1_15, P2_00, P0_12, P2_11, P1_06,
P1_07, P1_08, P1_09, P0_00, P0_01, P0_02, P0_03, P0_06, P0_07, P2_03, P2_04, P2_05, P2_06, P2_07, P2_08, P2_09, P2_10, P0_04, P0_05, P0_14, P2_02, P1_14, P1_13,
P1_12, P1_11, P0_08, and P0_09.
2 Applies to the input pin with pull-up: SYS_HWRST.
3 Applies to the three-statable pins: P1_10, P0_10, P0_11, P1_02, P1_03, P1_04, P1_05, P2_01, P0_13, P0_15, P1_00, P1_15, P2_00, P0_12, P2_11, P1_06, P1_07, P1_08, P1_09,
P0_00, P0_01, P0_02, P0_03, P2_03, P2_04, P2_05, P2_06, P2_07, P2_08, P2_09, P2_10, P0_04, P0_05, P0_14, P2_02, P1_14, P1_13, P1_12, P1_11, P0_08, and P0_09.
4 Applies to the three-statable pins with pull-ups: P1_10, P0_10, P0_11, P1_02, P1_03, P1_04, P1_05, P2_01, P0_13, P0_15, P1_00, P1_15, P2_00, P0_12, P2_11, P1_06, P1_07,
P1_08, P1_09, P0_00, P0_01, P0_02, P0_03, P2_03, P2_04, P2_05, P2_06, P2_07, P2_08, P2_09, P2_10, P0_04, P0_05, P0_14, P2_02, P1_14, P1_13, P1_12, P1_11, P0_08,
P0_09, P0_07, and P1_01.
5 Applies to the three-statable pin with pull-down: P0_06.
Rev. 0
| Page 12 of 37 | March 2017
ADuCM3027/ADuCM3029
Power Supply Current
Table 4, Table 5, and Table 6 describe power supply current for VBAT
.
Table 4. Active Mode—Current Consumption When VBAT = 3.0 V
Conditions
Buck
Typ1
0.40
0.98
Max2
Unit
Code3 executing from flash, cache enabled, peripheral clocks off, HCLK = 6.5 MHz
Code3 executing from flash, cache enabled, peripheral clocks off, HCLK = 26 MHz
Enabled
Enabled
mA
1.29
2.38
1.64
3.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Disabled 1.75
Enabled 1.28
Disabled 2.34
Enabled 0.95
Disabled 1.78
Code3 executing from flash, cache enabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz Enabled
1.08
Disabled 1.99
Code3 executing from flash, cache disabled, peripheral clocks off, HCLK = 26 MHz
Code3 executing from SRAM, peripheral clocks off, HCLK = 26 MHz
1.36
2.48
1.43
2.67
1.78
3.29
1.49
2.74
Code3 executing from flash, cache disabled, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz Enabled
1.37
Disabled 2.55
Code3 executing from SRAM, peripheral clocks on, HCLK = 26 MHz, PCLK = 26 MHz
Enabled
Disabled 2.03
1.08
1 TJ = 25°C.
2 TJ = 85°C.
3 The code being executed is a prime number generation in a continuous loop, with HFOSC as the system clock source.
Table 5. Flexi™ Mode—Current Consumption When VBAT = 3.0 V
Conditions
Buck
Typ1
0.3
0.52
0.39
0.7
Max2
Unit
mA
mA
mA
mA
Peripheral clocks off
Enabled
Disabled
Enabled
Disabled
0.67
1.11
0.80
1.38
Peripheral clocks on, PCLK = 26 MHz
1 TJ = 25°C.
2 TJ = 85°C.
Table 6. Deep Sleep Modes1—Current Consumption When VBAT = 3.0 V
−40°C +25°C +85°C +85°C
Typ
0.66
0.67
0.68
0.69
0.69
0.74
0.83
290
40
Typ Max Unit
Typ
0.75
0.77
0.79
0.81
0.78
0.83
0.93
310
56
Mode
Conditions
Hibernate RTC1 and RTC0 disabled, 8 KB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 16 KB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 24 KB SRAM retained, LFXTAL off
RTC1 and RTC0 disabled, 32 KB SRAM retained, LFXTAL off
RTC1 enabled, 8 KB SRAM retained, LFOSC as source for RTC1
RTC1 enabled, 8 KB SRAM retained, LFXTAL as source for RTC1
2.0
2.4
2.6
3.0
6.05 μA
6.4 μA
6.75 μA
7.1
μA
μA
2.05 6.1
2.1
2.25 6.3
6.15 μA
μA
1180 nA
950 nA
RTC1 and RTC0 enabled, 8 KB SRAM retained, LFXTAL as source for RTC1 and RTC0
Shutdown RTC0 enabled, LFXTAL as source for RTC0
RTC0 disabled
490
260
1 Buck enable/disable selection does not affect power consumption.
Rev. 0
| Page 13 of 37 | March 2017
ADuCM3027/ADuCM3029
SYSTEM CLOCKS/TIMERS
Table 7 and Table 8 show the system clock specifications for the ADuCM3027/ADuCM3029 MCUs.
Platform External Crystal Oscillator
Table 7. Platform External Crystal Oscillator Specifications
Parameter
Min
Typ
Max
Unit Conditions
LOW FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (LFXTAL)
CEXT1 = CEXT2
6
10
pF
External capacitor, CEXT1 = CEXT2
(symmetrical load), for C L 5 pF
(maximum)andESR=30k(maximum).
CEXT1, CEXT2 must be selected considering
the printed circuit board (PCB) trace
capacitance due to routing.
Frequency
32,768
Hz
pF
HIGH FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (HFXTAL)
CEXT1 = CEXT2
20
External capacitor, CEXT1 = CEXT2
(symmetrical load), for C L= 10 pF
(maximum) and ESR = 50 (maximum).
CEXT1, CEXT2 must be selected considering
the PCB trace capacitance due to
routing.
Frequency
26
MHz
On-Chip RC Oscillator
Table 8. On-Chip RC Oscillator Specifications
Parameter
Min
Typ
Max
Unit
Conditions
HIGH FREQUENCY RC OSCILLATOR (HFOSC)
Frequency
25.09
30,800
26
26.728
MHz
Hz
LOW FREQUENCY RC OSCILLATOR (LFOSC)
Frequency
32,768
34,407
Rev. 0
|
Page 14 of 37 | March 2017
ADuCM3027/ADuCM3029
ADC SPECIFICATIONS
Table 9. ADC Specifications
Parameter1, 2
VBAT/VREF (V)
Package
Typ
Unit
Conditions
NO MISSING CODE
1.8/1.25 (internal/external) 64-lead LFCSP 12
1.8/1.25 (internal/external) 54-ball WLCSP 12
3.0/2.5 (internal/external) 64-lead LFCSP 12
Bits
Bits
Bits
Fin = 1068 Hz, Fs = 100 KSPS,
internalreferenceinlowpower
mode, 400,000 samples end
point method used
INTEGRAL NONLINEARITY ERROR
1.8/1.25 (internal/external) 64-lead LFCSP 1.6
1.8/1.25 (internal/external) 54-ball WLCSP 1.8
3.0/2.5 (internal/external) 64-lead LFCSP 1.4
LSB
LSB
LSB
DIFFERENTIAL NONLINEARITY ERROR 1.8/1.25 (internal/external) 64-lead LFCSP −0.7, +1.15 LSB
1.8/1.25 (internal/external) 54-ball WLCSP −0.75, +1.2 LSB
3.0/2.5 (internal/external) 64-lead LFCSP −0.7, +1.1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
μA
OFFSET ERROR
GAIN ERROR
1.8/1.25 (external)
1.8/1.25 (external)
3.0/2.5 (external)
1.8/1.25 (external)
1.8/1.25 (external)
3.0/2.5 (external)
1.8/1.25 (internal)
1.8/1.25 (internal)
3.0/2.5 (internal)
64-lead LFCSP 0.5
54-ball WLCSP 0.5
64-lead LFCSP 0.5
64-lead LFCSP 2.5
54-ball WLCSP 3.0
64-lead LFCSP 0.5
64-lead LFCSP 104
54-ball WLCSP 108
64-lead LFCSP 131
3
Fin = 1068 Hz, Fs = 100 KSPS,
internalreferenceinlowpower
mode
IVBAT_ADC
μA
μA
1 The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs.
2 The specifications are characterized after performing internal ADC offset calibration.
3 Current consumption from VBAT_ADC supply when ADC is performing the conversion.
FLASH SPECIFICATIONS
Table 10. Flash Specifications
Parameter
Min
Typ
Max
Unit
Conditions
FLASH
Endurance
Data Retention
10,000
Cycles
Years
10
Rev. 0
|
Page 15 of 37 | March 2017
ADuCM3027/ADuCM3029
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
Stresses at or above those listed in Table 11 may cause perma-
nent damage to the product. This is a stress rating only. The
functional operation of the product at these or any other condi-
tions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum
operating conditions for extended periods may affect product
reliability.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Table 11. Absolute Maximum Ratings
PACKAGE INFORMATION
Parameter
Rating
Unit
SUPPLY
Figure 4 and Table 12 provide details about package branding.
For a complete listing of product availability, see the Ordering
Guide section.
VBAT_ANA1
−0.3 to +3.6
V
VBAT_ANA2
VBAT_ADC
VBAT_DIG1
VBAT_DIG2
VREF_ADC
ANALOG
VDCDC_CAP1N
VDCDC_AP1P
VDCDC_OUT
VDCDC_CAP2N
VDCDC_CAP2P
−0.3 to +3.6
V
V
Figure 4. Product Information on Package1
1 Exact brand may differ, depending on package type.
VLDO_OUT
−0.3 to +1.32
SYS_HFXTAL_IN
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
SYS_LFXTAL_OUT
Table 12. Package Brand Information
Brand Key
Field Description
Product model
ADuCM3027/ADuCM3029
DIGITAL INPUT/OUTPUT
t
Temperature range
Package type
pp
P0.X
−0.3 to +3.6
V
P1.X
P2.X
SYS_HWRST
Z
RoHS compliant designation
See the Ordering Guide section
Assembly lot code
Silicon revision
ccc
vvvvvv.x
n.n
yyww
Date code
Rev. 0
|
Page 16 of 37
|
March 2017
ADuCM3027/ADuCM3029
TIMING SPECIFICATIONS
Specifications are subject to change without notice.
Reset Timing
Table 13 and Figure 5 describe reset timing.
Table 13. Reset Timing
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tWRST
SYS_HWRST Asserted Pulse Width Low1
4
μs
1 Applies after power-up sequence is complete.
tWRST
SYS_HWRST
Figure 5. Reset Timing
System Clock and PLL
Table 14 describes system clock and phase-locked loop (PLL) specifications.
Table 14. System Clock and PLL
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tCK
PLL Input CLKIN Period1
PLL Output Frequency 2, 3
38.5
16
62.5
60
ns
fPLL
MHz
ns
tPCLK
tHCLK
System Peripheral Clock Period
38.5
154
154
Advanced High Performance Bus (AHB) Subsystem Clock Period 38.5
ns
1 The input to the PLL can come either from the high frequency external crystal or from the high frequency internal RC oscillator. Refer to the ADuCM302x Ultra Low Power
ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference.
2 For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, and PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13,
PLL_NSEL = 26, and PLL_DIV2 = 1 for PLL input clock = 16 MHz.
3 For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, and PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8,
PLL_NSEL = 30, and PLL_DIV2 = 0 for PLL input clock= 16 MHz.
Rev. 0
| Page 17 of 37 | March 2017
ADuCM3027/ADuCM3029
Serial Ports
To determine whether communication is possible between two devices at a particular clock speed, confirm the following specifications:
• Frame sync delay and frame sync setup and hold
• Data delay and data setup and hold
• Serial clock (SPT_CLK) width
In Figure 6, use the rising edge or the falling edge of SPT_CLK (external or internal) as the active sampling edge.
When externally generated, the SPORT clock is called fSPTCLKEXT
.
1
t
= ------------------------------
SPTCLKEXT
f
SPTCLKEXT
When internally generated, the programmed SPORT clock (fSPTCLKPROG) frequency is set by the following equation:
f
PCLK
f
= ----------------------------------------------
SPTCLKPROG
2 CLKDIV + 1
where CLKDIV is a field in the SPORT_DIV register that can be set from 0 to 65535.
Table 15. Serial Ports—External Clock
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tSFSE
Frame Sync Setup Before SPT_CLK (Externally Generated Frame Sync inTransmit or Receive Mode)1 5
ns
ns
ns
ns
ns
ns
tHFSE
Frame Sync Hold After SPT_CLK (Externally Generated Frame Sync in Transmit or Receive Mode)1
5
tSDRE
tHDRE
tSCLKW
tSPTCLK
Receive Data Setup Before Receive SPT_CLK1
Receive Data Hold After SPT_CLK1
SPT_CLK Width2
5
8
38.5
77
SPT_CLK Period2
SWITCHING CHARACTERISTICS
tDFSE
tHOFSE
tDDTE
tHDTE
Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3
Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)3
Transmit Data Delay After Transmit SPT_CLK3
20
20
ns
ns
ns
ns
2
1
Transmit Data Hold After Transmit SPT_CLK3
1 This specification is referenced to the sample edge.
2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPT_CLK.
3 This specification is referenced to the drive edge.
Rev. 0
| Page 18 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 16. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tSDRI
tHDRI
SWITCHING CHARACTERISTICS
Receive Data Setup Before SPT_CLK1
Receive Data Hold After SPT_CLK1
25
0
ns
ns
tDFSI
Frame Sync Delay After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2
Frame Sync Hold After SPT_CLK (Internally Generated Frame Sync in Transmit or Receive Mode)2 –8
20
20
ns
ns
ns
ns
ns
ns
tHOFSI
tDDTI
Transmit Data Delay After SPT_CLK2
Transmit Data Hold After SPT_CLK2
SPT_CLK Width
tHDTI
–7
tSCLKIW
tSPTCLK
tPCLK – 1.5
2 × tPCLK – 1
SPT_CLK Period
1 This specification is referenced to the sample edge.
2 This specification is referenced to the drive edge.
DATA RECEIVE—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA RECEIVE—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tHOFSE
tSFSE
tHFSE
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
tSDRI
tHDRI
tSDRE
tHDRE
SPT0_AD0/SPTO_BD0
(DATA CHANNEL A/B)
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
DATA TRANSMIT—INTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
DRIVE EDGE SAMPLE EDGE
tSCLKIW
tSCLKW
SPT0_ACLK/BSPT0_CLK
(SPORT CLOCK)
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK)
tDFSI
tDFSE
tHOFSI
tHOFSE
tSFSE
tHFSE
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
SPT0_AFS/SPT0_BFS
(FRAME SYNC)
tDDTI
tDDTE
tHDTI
tHDTE
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 6. Serial Ports
Rev. 0
|
Page 19 of 37
|
March 2017
ADuCM3027/ADuCM3029
Table 17. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
SWITCHING CHARACTERISTICS
tDDTIN
tDDTTI
Data Enable From Internal Transmit SPT_CLK1
Data Disable From Internal Transmit SPT_CLK1
5
ns
ns
160
1 This specification is referenced to the drive edge.
DRIVE EDGE
DRIVE EDGE
SPT0_ACLK/SPT0_BCLK
(SPORT CLOCK INTERNAL)
tDDTIN
tDDTTI
SPT0_AD0/SPT0_BD0
(DATA CHANNEL A/B)
Figure 7. Serial Ports—Enable and Three-State
Rev. 0
| Page 20 of 37 | March 2017
ADuCM3027/ADuCM3029
SPI Timing
Table 18, Figure 8, and Figure 9 (for master mode) and Table 19, Figure 10, and Figure 11 (for slave mode) describe SPI timing specifica-
tions. High speed SPI (SPIH) can be used for high data rate peripherals.
Table 18. SPI Master Mode Timing1
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tCS
CS to SCLK Edge
0.5 × tPCLK – 3
tPCLK – 3.5
tPCLK – 3.5
5
ns
ns
ns
ns
ns
tSL
SCLK Low Pulse Width
tSH
SCLK High Pulse Width
tDSU
tDHD
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
20
SWITCHING CHARACTERISTICS
tDAV
tDOSU
tSFS
Data Output Valid After SCLK Edge
25
ns
ns
ns
Data Output Setup Before SCLK Edge
CS High After SCLK Edge
tPCLK – 2.2
0.5 × tPCLK – 3
1 This specification is characterized with respect to double drive strength.
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
MOSI
MISO
MSB
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
MSB IN
LSB IN
tDSU
tDHD
Figure 8. SPI Master Mode Timing (Phase Mode = 1)
Rev. 0
| Page 21 of 37 | March 2017
ADuCM3027/ADuCM3029
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
tDOSU
MOSI
MISO
MSB
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
MSB IN
LSB IN
tDSU
tDHD
Figure 9. SPI Master Mode Timing (Phase Mode = 0)
Table 19. SPI Slave Mode Timing
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tCS
CS to SCLK Edge
SCLK Low Pulse Width
38.5
ns
ns
ns
ns
ns
tSL
38.5
38.5
6
tSH
SCLK High Pulse Width
tDSU
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
tDHD
8
SWITCHING CHARACTERISTICS
tDAV
tDOCS
tSFS
Data Output Valid After SCLK Edge
Data Output Valid After CS Edge
CS High After SCLK Edge
25
ns
ns
ns
20
38.5
Rev. 0
| Page 22 of 37 | March 2017
ADuCM3027/ADuCM3029
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
MISO
MOSI
MSB
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
MSB IN
LSB IN
tDSU
tDHD
Figure 10. SPI Slave Mode Timing (Phase Mode = 1)
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
SCLK
(POLARITY = 1)
tDAV
tDOCS
MISO
MOSI
MSB
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
MSB IN
LSB IN
tDSU
tDHD
Figure 11. SPI Slave Mode Timing (Phase Mode = 0)
Rev. 0
| Page 23 of 37 | March 2017
ADuCM3027/ADuCM3029
General-Purpose Port Timing
Table 20 and Figure 12 describe general-purpose port timing.
Table 20. General-Purpose Port Timing
Parameter
Min
Max
Unit
TIMING REQUIREMENTS
tWFI
General-Purpose Port Pin Input Pulse Width
4 × tPCLK
ns
tWFI
GPIO INPUT
Figure 12. General-Purpose Port Timing
Timer PWM_OUT Cycle Timing
Table 21 and Figure 13 describe timer PWM_OUT cycle timing.
Table 21. Timer PWM_OUT Cycle Timing
Parameter
Min
Max
256 × (216 – 1)
Unit
SWITCHING CHARACTERISTICS
tPWMO
Timer Pulse Width Output
4 × tPCLK – 6
ns
PWM OUTPUTS
tPWM0
Figure 13. Timer PWM_OUT Cycle Timing
Rev. 0
| Page 24 of 37 | March 2017
ADuCM3027/ADuCM3029
MCU TEST CONDITIONS
DRIVER TYPES
The ac signal specifications (timing parameters) that appear in
this data sheet include output disable time, output enable time,
and others. Timing is measured on signals when they cross the
Table 22 shows driver types.
Table 22. Driver Types
V
MEAS level as described in Figure 14. All delays (in ns or μs) are
Driver Type1, 2, 3 Associated Pins
measured between the point that the first signal reaches VMEAS
and the point that the second signal reaches VMEAS. The value of
VMEAS is set to VBAT/2.
Type A
P0_00, P0_01, P0_02, P0_03, P0_07, P0_10,
P0_11, P0_12, P0_13, P0_15, P1_00, P1_01,
P1_02, P1_03, P1_04, P1_05, P1_06, P1_07,
P1_08, P1_09, P1_10, P1_15, P2_00, P2_01,
P2_04, P2_05, P2_06, P2_07, P2_08, P2_09,
P2_10, P2_11, SYS_HWRST
Input
or
Output
V
V
ME AS
ME AS
Type B
P0_08, P0_09, P0_14, P1_11, P1_12, P1_13,
P1_14, P2_02
Figure 14. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
Type C
Type D
P0_04, P0_05
P0_06
1 In single drive mode, the maximum source/sink capacity is 2 mA.
2 In double drive mode, the maximum source/sink capacity is 4 mA.
3 At maximum drive capacity, only 16 GPIOs are allowed to switch at any given
point of time.
Tester Pin Electronics
50 ꢀ:
V
Load
T1
DUT
Output
45 ꢀ:
70 ꢀ:
ZO = 50 :ꢀ(Impedance)
TD = 4.04 r 1.18 ns
50 ꢀ:
0.5 pF
4 pF
2 pF
400 ꢀ:
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 15. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Rev. 0
| Page 25 of 37 | March 2017
ADuCM3027/ADuCM3029
Figure 16 through Figure 21 show the typical current voltage
characteristics for the output drivers of the MCU.
The curves represent the current drive capability of the output
drivers as a function of output voltage.
VOH (V)
VOH (V)
2.7
2.75
2.8
2.85
2.9
2.95
3
1.2
1.3
1.4
1.5
1.6
1.7
1.8
5
4
5
4
Type B
Type A
Type A
3
3
,
-3.0V
,
-1.74V
2
2
Type B
1
1
0
0
Type C,D
Type C,D
-1
-2
-3
-1
-2
-3
-4
-5
Type A,C,D
Type A,C,D
,
-3.0V
,
-1.74V
Source/Sink VBAT Current (mA)
Type B
Type B
-4
-5
0.6
0
0.1
0.2
0.3
0.4
0.5
0
0.05
0.1
0.15
0.2
0.25
0.3
VOL (V)
VOL (V)
Figure 16. Output Double Drive Strength Characteristics (VBAT = 1.74 V)
Figure 18. Output Double Drive Strength Characteristics (VBAT = 3.0 V)
VOH (V)
VOH (V)
1.2
1.3
1.4
1.5
1.6
1.7
2.75
2.8
2.85
2.9
2.95
3
2.5
2
2.5
2
Type A
,
-1.74V
Type B
Type A
1.5
1
1.5
1
,
-3.0V
Type B
0.5
0
0.5
0
Type C,D
Type C,D
-0.5
-1
- 0.5
-1
Type A,C,D
Type D
,
-3.0V
,
-1.74V
-1.5
-2
-1.5
-2
Type B
Type B
Type A,C
-2.5
-2.5
0
0.1
0.2
0.4
0.5
0.6
VOL (V) 0.3
0
0.05
0.1
0.15
0.2
0.25
VOL (V)
Figure 17. Output Single Drive Strength Characteristics (VBAT = 1.74 V)
Figure 19. Output Single Drive Strength Characteristics (VBAT = 3.0 V)
Rev. 0
|
Page 26 of 37
|
March 2017
ADuCM3027/ADuCM3029
VOH (V)
VOH (V)
3.3
3.35
3.4
3.45
3.5
3.55
3.6
3.38
3.4
3.42
3.44
3.46
3.48
3.5
3.52
3.54
3.56
3.58
5
4
2.5
2
Type B
Type B
Type A
Type A
3
1.5
1
2
,
-3.6V
,
-3.6V
1
0.5
0
0
Type C,D
Type C,D
-1
-2
-3
-4
-5
-0.5
-1
Type A
Type B
,
-3.6V
,
-3.6V
Type B
-1.5
-2
Type C,D
Type A,C,D
-2.5
0
0.05
0.1
0.15
0.2
0.25
0
0.05
0.1
0.15
0.2
0.25
VOL (V)
VOL (V)
Figure 20. Output Double Drive Strength Characteristics (VBAT = 3.6 V)
Figure 21. Output Single Drive Strength Characteristics (VBAT = 3.6 V)
Rev. 0
|
Page 27 of 37
|
March 2017
ADuCM3027/ADuCM3029
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
mation of TJ by the equation:
ENVIRONMENTAL CONDITIONS
Table 23. Thermal Characteristics (64-Lead LFCSP)
TJ = TA + JA PD
Parameter
Typ
28.2
5.4
Unit
°C/W
°C/W
JA
JC
where:
TA is ambient temperature (°C).
TJ is junction temperature (°C).
PD is power dissipation (To calculate PD, see the Power Supply
Current section).
Values of JC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Rev. 0
| Page 28 of 37 | March 2017
ADuCM3027/ADuCM3029
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Figure 22 shows an overview of signal placement on the 64-Lead LFCSP_WQ.
VBAT_ANA1
SYS_HFXTAL_IN
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
SYS_LFXTAL_OUT
VDCDC_CAP1N
VDCDC_CAP1P
VBAT_ANA2
1
2
3
4
5
6
7
8
9
48 GND_DIG
47 XINT0_WAKE1/GPIO16
46 TRM0_OUT/SPI1_RDY/GPIO14
45 SPT0_ACNV/SPI1_CS2/GPIO34
44 SPI0_RDY/GPIO30
43 GPIO29
42 GPIO28
ADuCM3027/
ADuCM3029
41 TMR1_OUT/GPIO27
40 BPR0_TONE_N/GPIO08
39 BPR0_TONE_P/SPI2_CS1/GPIO09
38 GPIO17/SYS_BMODE0
37 SPT0_ACLK/GPIO31
36 SPT0_AFS/GPIO32
VDCDC_OUT
TOP VIEW
VDCDC_CAP2N 10
VDCDC_CAP2P 11
VLDO_OUT 12
VREF_ADC 13
VBAT_ADC 14
GND_VREFADC 15
ADC0_VIN0/GPIO35 16
35 SPT0_AD0/UART0_SOUT_EN/GPIO12
34 VBAT_DIG1
33
SPI1_CS1/SYS_CLKOUT/GPIO43/RTC1_SS1
Figure 22. 64-Lead LFCSP Configuration
Rev. 0
| Page 29 of 37 | March 2017
ADuCM3027/ADuCM3029
Figure 23 shows an overview of signal placement on the 54-Ball WLCSP.
12
10
VDCDC_CAP2N
8
6
4
2
13
VBAT_ADC
11
9
7
5
3
1
VBAT_ANA1
SYS_LFXTAL_IN
VLDO_OUT
VDCDC_CAP1P
SYS_HFXTAL_OUT
A
B
C
D
E
F
VDCDC_CAP2P
SYS_LFXTAL_OUT
P2_03
VREF_ADC
P0_00
P0_03
VDCDC_CAP1N
SYS_HFXTAL_IN
P2_05 GND_VREFADC VDCDC_OUT VBAT_ANA2
P0_02
P0_11
P0_01
P0_05
P0_06
P2_06
P0_07
P2_04
P0_04
GND_ANA
P1_10
P1_02
P0_10
P1_03
SYS_HWRST GND_DIG
P1_07
P1_08
P1_09
P1_04
P1_05
P2_01
VBAT_DIG1
P2_11
P1_06
P1_01
P0_13
P0_15
VBAT_DIG2
G
H
P0_12
P0_09
P0_08
P1_14
P0_14
P1_00
BOTTOM VIEW
(BALL SIDE UP)
Not to Scale
Figure 23. 54-Ball WLCSP Configuration
Rev. 0
| Page 30 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 24 lists the signal descriptions of the ADuCM3027/ADuCM3029 MCUs.
Table 24. Signal Functional Descriptions
GPIO Signal Name
SPIn_CLK
Description
SPI Clock. n = 0, 1, 2.
SPIn_MOSI
SPIn_MISO
SPIn_RDY
SPI Master Out Slave In. n = 0, 1, 2.
SPI Master In Slave Out. n = 0, 1, 2.
SPI Ready Signal. n = 0, 1, 2.
SPI Chip Select Signal. n = 0, 1, 2 and m = 0, 1, 2, 3.
SPORT A Clock Signal.
SPIn_CSm
SPT0_ACLK
SPT0_AFS
SPORT A Frame Sync.
SPT0_AD0
SPORT A Data Pin 0.
SPT0_ACNV
SPT0_BCLK
SPT0_BFS
SPORT A Converter Signal for Interface with ADC.
SPORT B Clock Signal.
SPORT B Frame Sync.
SPT0_BD0
SPORT B Data Pin 0.
SPT0_BCNV
I2C0_SCL
SPORT B Converter Signal for Interface with ADC.
I2C Clock.
I2C Data.
I2C0_SDA
SWD0_CLK
SWD0_DATA
BPR0_TONE_N
BPR0_TONE_P
UART0_TX
Serial Wire Debug Clock.
Serial Wire Debug Data.
Beeper Tone Negative Pin.
Beeper Tone Positive Pin.
UART Transmit Pin.
UART0_RX
UART Receive Pin.
UART0_SOUT_EN
XINT0_WAKEn
TMRn_OUT
SYS_BMODE0
SYS_CLKIN
SYS_CLKOUT
RTC1_SS1
UART Serial Data Out Pin.
System Wake-Up Pin. Wake Up from Flexi/Hibernate/Shutdown Modes1. n = 0, 1, 2, 3.
Timer Output Pin. n = 0, 1, 2.
Boot Mode Pin.
External Clock In Pin.
External Clock Out Pin.
RTC1 SensorStrobe Pin.
ADC0_VINn
ADC Voltage Input Pin. n = 0, 1, 2, 3, 4, 5, 6, 7.
1
For shutdown, XINT0_WAKE3 is not capable of waking the device from shutdown mode.
Rev. 0
| Page 31 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 25 lists the 64-Lead LFCSP_WQ package by pin number for the ADuCM3027/ADuCM3029 MCUs.
Table 25. Pin Function Descriptions, 64-Lead LFCSP_WQ
Pin No.
1
GPIO
Signal Name
Description
GPIO Pull
VBAT_ANA1
Analog 3 V Supply.
2
SYS_HFXTAL_IN
26 MHz High Frequency Crystal.
26 MHz High Frequency Crystal.
32 kHz Low Frequency Crystal.
32 kHz Low Frequency Crystal.
Buck Fly Capacitor.
3
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
4
5
SYS_LFXTAL_OUT
VDCDC_CAP1N
6
7
VDCDC_CAP1P
Buck Fly Capacitor.
8
VBAT_ANA2
Analog 3 V Supply.
9
VDCDC_OUT
Buck Output Capacitor.
Buck Fly Capacitor.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
VDCDC_CAP2N
VDCDC_CAP2P
Buck Fly Capacitor.
VLDO_OUT
LDO Output Capacitor.
Analog Reference Voltage for ADC.
Analog 3 V Supply for ADC.
Reference Ground for ADC.
VREF_ADC
VBAT_ADC
GND_VREFADC
P2_03
P2_04
P2_05
P2_06
P2_07
P2_08
P2_09
P2_10
P0_05
ADC0_VIN0/GPIO35
ADC0_VIN1/GPIO36
ADC0_VIN2/GPIO37
ADC0_VIN3/GPIO38
ADC0_VIN4/SPI2_CS3/GPIO39
ADC0_VIN5/SPI0_CS2/GPIO40
ADC0_VIN6/SPI0_CS3/GPIO41
ADC0_VIN7/SPI2_CS2/GPIO42
I2C0_SDA/GPIO05
SYS_HWRST
PU
PU
PU
PU
PU
PU
PU
PU
PU
System Hardware Reset.
P0_04
P0_07
P0_06
P1_09
P1_08
P1_07
P1_06
P2_11
I2C0_SCL/GPIO04
GPIO07/SWD0_DATA
GPIO06/SWD0_CLK
SPI1_CS0/GPIO25
SPI1_MISO/GPIO24
SPI1_MOSI/GPIO23
SPI1_CLK/GPIO22
SPI1_CS1/SYS_CLKOUT/GPIO43/RTC1_SS1
VBAT_DIG1
PU
PU
PD
PU
PU
PU
PU
PU
Digital 3 V Supply.
P0_12
P2_00
P1_15
P1_01
P0_09
P0_08
P1_11
P1_12
P1_13
P1_14
P2_02
SPT0_AD0/GPIO12
SPT0_AFS/GPIO32
SPT0_ACLK/GPIO31
GPIO17/SYS_BMODE0
BPR0_TONE_P/SPI2_CS1/GPIO09
BPR0_TONE_N/GPIO08
TMR1_OUT/GPIO27
GPIO28
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO29
SPI0_RDY/GPIO30
SPT0_ACNV/SPI1_CS2/GPIO34
Rev. 0
| Page 32 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 25. Pin Function Descriptions, 64-Lead LFCSP_WQ (Continued)
Pin No.
GPIO
P0_14
P1_00
Signal Name
Description
GPIO Pull
PU
46
TMR0_OUT/SPI1_RDY/GPIO14
XINT0_WAKE1/GPIO16
GND_DIG
47
PU
48
Digital Ground.
49
VBAT_DIG2
Digital 3 V Supply.
50
P0_15
P0_13
P2_01
P1_05
P1_04
P1_03
P1_02
P0_11
P0_10
P1_10
P0_03
P0_02
P0_01
P0_00
XINT0_WAKE0/GPIO15
XINT0_WAKE2/GPIO13
XINT0_WAKE3/TMR2_OUT/GPIO33
SPI2_CS0/GPIO21
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
51
52
53
54
SPI2_MISO/GPIO20
55
SPI2_MOSI/GPIO19
56
SPI2_CLK/GPIO18
57
UART0_RX/GPIO11
58
UART0_TX/GPIO10
59
SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26
SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03
SPI0_MISO/SPT0_BD0/GPIO02
SPI0_MOSI/SPT0_BFS/GPIO01
SPI0_CLK/SPT0_BCLK/GPIO00
GND_ANA
60
61
62
63
64
Analog Ground.
Ground.
Exposed Pad
GND
Rev. 0
| Page 33 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 26 lists the 54-Ball WLCSP package by ball number for the ADuCM3027/ADuCM3029 MCUs.
Table 26. Pin Function Descriptions, 54-Ball WLCSP
Ball No. GPIO
Pin Label
Description
GPIO Pull
A01
A03
A05
A07
A09
A11
A13
VBAT_ANA1
Analog 3 V Supply.
SYS_HFXTAL_OUT
SYS_LFXTAL_IN
26 MHz High Frequency Crystal.
32 kHz Low Frequency Crystal.
Buck Fly Capacitor.
VDCDC_CAP1P
VDCDC_CAP2N
Buck Fly Capacitor.
VLDO_OUT
LDO Output Capacitor
Analog 3 V Supply for ADC.
VBAT_ADC
B01
B03
B05
B07
B09
B11
B13
C01
C03
C05
C07
C09
C11
C13
D01
D03
D05
D07
D09
D11
D13
E01
E03
E05
E07
E09
E11
E13
F02
F04
F06
F08
F10
F12
G01
G03
P0_00
SPI0_CLK/SPT0_BCLK/GPIO00
SYS_HFXTAL_IN
PU
26 MHz High Frequency Crystal.
32 kHz Low Frequency Crystal.
Buck Fly Capacitor.
SYS_LFXTAL_OUT
VDCDC_CAP1N
VDCDC_CAP2P
Buck Fly Capacitor.
VREF_ADC
Analog Reference Voltage for ADC.
P2_03
P0_03
P0_01
P0_02
ADC0_VIN0/GPIO35
SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03
SPI0_MOSI/SPT0_BFS/GPIO01
SPI0_MISO/SPT0_BD0/GPIO02
VBAT_ANA2
PU
PU
PU
PU
Analog 3 V Supply.
VDCDC_OUT
Buck Output Capacitor.
Reference Ground for ADC.
GND_VREFADC
P2_05
P0_10
P1_10
P0_11
ADC0_VIN2/GPIO37
UART0_TX/GPIO10
SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26
UART0_RX/GPIO11
GND_ANA
PU
PU
PU
PU
Analog Ground.
P2_04
P2_06
P0_05
P1_03
P1_02
ADC0_VIN1/GPIO36
ADC0_VIN3/GPIO38
I2C0_SDA/GPIO05
SPI2_MOSI/GPIO19
SPI2_CLK/GPIO18
GND_DIG
PU
PU
PU
PU
PU
Digital Ground.
SYS_HWRST
System Hardware Reset.
P0_04
P0_07
P0_06
P2_01
P1_05
P1_04
P1_09
P1_08
P1_07
I2C0_SCL/GPIO04
GPIO07/SWD0_DATA
GPIO06/SWD0_CLK
XINT0_WAKE3/TMR2_OUT/GPIO33
SPI2_CS0/GPIO21
SPI2_MISO/GPIO20
SPI1_CS0/GPIO25
SPI1_MISO/GPIO24
SPI1_MOSI/GPIO23
VBAT_DIG2
PU
PU
PD
PU
PU
PU
PU
PU
PU
Digital 3 V Supply.
P0_15
XINT0_WAKE0/GPIO15
PU
Rev. 0
| Page 34 of 37 | March 2017
ADuCM3027/ADuCM3029
Table 26. Pin Function Descriptions, 54-Ball WLCSP (Continued)
Ball No. GPIO
Pin Label
Description
GPIO Pull
G05
G07
G09
G11
G13
H02
H04
H06
H08
H10
H12
P0_13
P1_01
P1_06
P2_11
XINT0_WAKE2/GPIO13
GPIO17/SYS_BMODE0
SPI1_CLK/GPIO22
PU
PU
PU
PU
SPI1_CS1/SYS_CLKOUT/GPIO43/RTC1_SS1
VBAT_DIG1
Digital 3 V Supply.
P1_00
P0_14
P1_14
P0_08
P0_09
P0_12
XINT0_WAKE1/GPIO16
TMR0_OUT/SPI1_RDY/GPIO14
SPI0_RDY/GPIO30
PU
PU
PU
PU
PU
PU
BPR0_TONE_N/GPIO08
BPR0_TONE_P/SPI2_CS1/GPIO09
SPT0_AD0/GPIO12/UART0_SOUT_EN
Rev. 0
| Page 35 of 37 | March 2017
ADuCM3027/ADuCM3029
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.20
PIN 1
PIN 1
INDICATOR
INDICATOR
49
64
1
48
0.50
BSC
EXPOSED
PAD
4.60
4.50 SQ
4.40
16
33
32
17
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
7.50 REF
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.203 REF
Figure 24. 64-Lead Frame Chip Scale Package [LFCSP]
9 mm x 9 mm Body and 0.75 mm Package Height
(CP-64-16)
Dimensions shown in mm
Note: Exposed pad must be grounded
2.800
2.760 SQ
2.720
0.210
13 11
12 10
8
6
4
2
3
1
0.108
9
7
5
A
B
C
D
E
F
0.35
BSC
BALL A1
IDENTIFIER
0.303
BSC
G
H
0.350
BSC
TOP VIEW
BOTTOM VIEW
(BALL SIDE UP)
0.103
(BALL SIDE DOWN)
0.320
0.290
0.260
0.530
0.470
0.410
END VIEW
COPLANARITY
0.05
0.280
0.240
0.200
SEATING
PLANE
0.210
0.180
0.150
Figure 25. 54-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-54-1)
Dimensions shown in mm
Rev. 0
| Page 36 of 37 | March 2017
ADuCM3027/ADuCM3029
ORDERING GUIDE
Model1
Description
Temperature2, 3 Package Description Package Option
54-Ball WLCSP, 13” Reel
ULP ARM Cortex-M3 with 128 KB Embedded Flash
ULP ARM Cortex-M3 with 128 KB Embedded Flash
ADUCM3027BCBZ-RL
ADUCM3027BCBZ-R7
ADUCM3027BCPZ
ADUCM3027BCPZ-RL
−40°C to +85°C
CB-54-1
−40°C to +85°C 54-Ball WLCSP, 7” Reel CB-54-1
ULP ARM Cortex-M3 with 128 KB Embedded Flash −40°C to +85°C 64-Lead LFCSP
ULP ARM Cortex-M3 with 128 KB Embedded Flash 64-Lead LFCSP, 13” Reel
CP-64-16
CP-64-16
−40°C to +85°C
ADUCM3027BCPZ-R7 ULP ARM Cortex-M3 with 128 KB Embedded Flash −40°C to +85°C 64-Lead LFCSP, 7”Reel CP-64-16
ADUCM3029BCBZ-RL ULP ARM Cortex-M3 with 256 KB Embedded Flash −40°C to +85°C 54-Ball WLCSP, 13” Reel CB-54-1
ADUCM3029BCBZ-R7 ULP ARM Cortex-M3 with 256 KB Embedded Flash −40°C to +85°C 54-Ball WLCSP, 7” Reel CB-54-1
ADUCM3029BCPZ
ULP ARM Cortex-M3 with 256 KB Embedded Flash −40°C to +85°C 64-Lead LFCSP
64-Lead LFCSP, 13” Reel
CP-64-16
CP-64-16
ADUCM3029BCPZ-RL ULP ARM Cortex-M3 with 256 KB Embedded Flash −40°C to +85°C
ADUCM3029BCPZ-R7 ULP ARM Cortex-M3 with 256 KB Embedded Flash −40°C to +85°C 64-Lead LFCSP, 7”Reel CP-64-16
ADZS-UCM3029EZLITE ADuCM3029 Evaluation Kit
−40°C to +85°C 64-Lead LFCSP
CP-64-16
1 Z = RoHS Compliant Part.
2 Referenced temperature is ambient temperature. The ambient temperature is not a specification. See the Absolute Maximum Ratings section for TJ (junction temperature)
specification which is the only temperature specification.
3 These are preproduction devices. See ENG-Grade agreement for details.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14168-0-3/17(0)
Rev. 0
| Page 37 of 37 | March 2017
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