ADUCM310BBCZ [ADI]
Precision Analog Microcontroller, Tunable Optical Control Microcontroller;
| 型号： | ADUCM310BBCZ |
| 厂家： | 
ADI |
| 描述： | Precision Analog Microcontroller, Tunable Optical Control Microcontroller 微控制器 外围集成电路 |
| 文件： | 总28页 (文件大小：542K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller, Tunable
Optical Control Microcontroller
ADuCM310
Data Sheet
External 16 MHz crystal option
External clock source
Memory
2× 128 kB Flash/EE memories, 32 kB SRAM
In-circuit download, SW-DP-based debugging
Software triggered in-circuit reprogrammability
On-chip peripherals
UART, 2× I2C and 2× SPI serial input/output
28-pin general-purpose input/output (GPIO) port
3 general-purpose timers
FEATURES
Analog input/output
22-channel, 14-bit, 800 kSPS analog-to-digital
converter (ADC)
10 external channels
1 on-chip die temperature monitor
6 current output digital-to-analog converter (IDAC)
monitor channels
3 power monitor channels
2 buffered reference output channels
Fully differential and single-ended modes
0 V to 2.5 V analog input range
Wake-up (W/U) timer
Watchdog timer (WDT)
32-element programmable logic array (PLA)
Vectored interrupt controller
Interrupt on edge or level external pin inputs
9× external interrupts
Power
Multiple supplies
6 low noise, 12-/14-bit IDAC outputs
1× 250 mA, 1× 200 mA, 2× 100 mA, and 2× 20 mA
Semiconductor optical amplifier (SOA) IDAC pull-down
to −3.0 V for fast current sink
Eight 12-bit voltage output DACs (VDACs)
Channel 0 and Channel 1: 0 V to 3 V, 75 Ω load
Channel 2 and Channel 3: −5 V to 0 V, 500 Ω load
Channel 4 and Channel 5: 0 V to 3 V, 300 Ω load
Channel 6: 0 V to 5 V, 500 Ω load
5 V for VDAC6 and VDAC7
3.3 V for digital and analog inputs/outputs
1.8 V to 2.7 V for IDACs
−5 V supply for IDAC3 and VDAC2/VDAC3
Package and temperature range
6 mm × 6 mm, 112-ball CSP_BGA package
Fully specified for −40°C to +85°C ambient operation
Tools
Channel 7: 0 V to 5 V, 100 Ω load
2.5 V, on-chip voltage reference
2 buffered 2.5 V outputs
Microcontroller
ARM Cortex-M3 processor, 32-bit RISC architecture
Serial wire port supports code download and debugging
Clocking options
QuickStart™ development system
Full third party support
APPLICATIONS
Optical modules—tunable laser modules
Trimmed on-chip oscillator ( 3%)
80 MHz phase-locked loop (PLL)
FUNCTIONAL BLOCK DIAGRAM
32.786kHz
16MHz OSC
80MHz PLL
AIN0
AIN9
RESET
POR
14-BIT
SAR
ADC
MUX
BUF
IOVDDx
PVDD_IDACx
AVDDx
ON-CHIP
1.8V LDO
INTERNAL CHANNELS,
IDACs, TEMPERATURE,
SUPPLIES
ARM
CORTEX-M3
PROCESSOR
DGNDx
PGND
GPIO PORTS
UART PORT
2 × SPI PORT
2.5V BAND
VREF_1.2
BUF_VREF2.5A
BUF_VREF2.5B
GAP V
REF
2
2 × I C PORT
MEMORY
256k FLASH
32k SRAM
EXT IRQs
GENERAL-
PURPOSE
I/O PORTS
VDAC
VDAC0
3 × GP TIMER
WD TIMER
W/U TIMER
PWM
DMA
NVIC
VDAC7
IDAC0
VDAC
IDAC
ADuCM310
PLA
32 × ELEMENTS
SWDIO
SWCLK
SERIAL
WIRE
IDAC5
IDAC
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADUCM310* PRODUCT PAGE QUICK LINKS
Last Content Update: 08/02/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• ADuCM310 Material Declaration
• PCN-PDN Information
EVALUATION KITS
• Quality And Reliability
• ADuCM310 Evaluation Board
• Symbols and Footprints
DOCUMENTATION
Application Notes
DISCUSSIONS
View all ADuCM310 EngineerZone Discussions.
• AN-1160: Cortex-M3 Based ADuCxxx Serial Download
Protocol
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-1322: ADuCM320 Code Execution Speed
Data Sheet
• ADuCM310: Precision Analog Microcontroller, Tunable
Optical Control Microcontroller Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
User Guides
• UG-549: How to Set Up and Use the ADuCM310
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• UG-829: ADuCM310 Development Systems Getting
Started Tutorial
TOOLS AND SIMULATIONS
• ADuCM310 CMSIS Pack
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
ADuCM310
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.................................................................... 17
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 22
Recommended Circuit and Component Values ........................ 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Timing Specifications ................................................................ 12
Absolute Maximum Ratings.......................................................... 17
REVISION HISTORY
7/2017—Rev. A to Rev. B
Change to Features ........................................................................... 1
Change to General Description...................................................... 3
Changes to Specifications Section and Table 1............................. 4
Added Endnote 1, Table 1; Renumbered Sequentially .............. 12
11/2015—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Changes to Specifications Section and Table 1............................. 4
Changes to Table 6 and Figure 5................................................... 15
Changes to Table 7 and Figure 6................................................... 16
Changes to Figure 7........................................................................ 18
5/2015—Revision 0: Initial Version
Rev. B Page 2 of 27
Data Sheet
ADuCM310
GENERAL DESCRIPTION
The ADuCM310 is a multidie stack, on-chip system designed
for diagnostic control of tunable laser optical module applications.
The ADuCM310 features a 16-bit (14-bit accurate) multichannel
successive approximation register (SAR) ADC, an ARM
Cortex™-M3 processor, eight voltage DACs (VDACs), six
current output DACs, and Flash/EE memory packaged in a
6 mm × 6 mm, 112-ball CSP_BGA package.
The ADuCM310 also provides 2× buffered reference outputs
capable of sourcing up to 1.2 mA. These outputs can be used
externally to the chip.
The ADuCM310 integrates an 80 MHz ARM Cortex-M3
processor. It is a 32-bit reduced instruction set computer (RISC)
machine, offering up to 100 DMIPS peak performance. The ARM
Cortex-M3 processor also has a flexible 14-channel direct
memory access (DMA) controller supporting serial peripheral
interface (SPI), UART, and I2C communication peripherals. The
ADuCM310 has 256 kB of nonvolatile Flash/EE memory and
32 kB of SRAM integrated on-chip.
The bottom die in the stack supports the bulk of the low voltage
analog circuitry and is the largest of the three die. It contains
the ADC, VDACs, main IDAC circuits, as well as other analog
support circuits, such as the low drift precision 2.5 V voltage
reference source.
A 16 MHz on-chip oscillator generates the 80 MHz system
clock. This clock internally divides to allow the processor to
operate at lower frequency, thus saving power. A low power
internal 32 kHz oscillator is available and can clock the timers.
The ADuCM310 includes three general-purpose timers, a
wake-up timer (which can be used as a general-purpose timer),
and a system watchdog timer.
The middle die in the stack supports the bulk of the digital
circuitry, including the ARM Cortex-M3 processor, the flash
and SRAM blocks, and all of the digital communication
peripherals. In addition, this die provides the clock sources for
the whole chip. A 16 MHz internal oscillator is the source of the
internal PLL that outputs an 80 MHz system clock.
The top die, which is the smallest die, was developed on a high
voltage process, and this die supports the −5 V and +5 V VDAC
outputs. It also implements the SOA IDAC current sink circuit
that allows the external SOA diode to pull to a −3.0 V level to
implement the fast shutdown of the laser output.
A range of communication peripherals can be configured as
required in a specific application. These peripherals include
UART, 2 × I2C, 2 × SPI, GPIO ports, and pulse-width
modulation (PWM).
On-chip factory firmware supports in-circuit serial download via
the UART, while nonintrusive emulation and program download
are supported via the serial wire debug port (SW-DP) interface.
These features are supported on the EVAL-ADuCM310QSPZ
development system.
Regarding the individual blocks, the ADC is capable of
operating at conversion rates up to 800 kSPS. There are
10 external inputs to the ADC, which can be single ended or
differential. Several internal channels are included, such as the
supply monitor channels, an on-chip temperature sensor, and
internal voltage reference monitors.
The ADuCM310 operates from 2.9 V to 3.6 V and is specified
over a temperature range of −40°C to +85°C.
The VDACs are 12-bit string DACs with output buffers capable
of sourcing between 10 mA and 50 mA, and these DACs are all
capable of driving 10 nF capacitive loads.
Note that, throughout this data sheet, multifunction pins, such
as P1.0/SIN/ECLKIN/PLAI[4], are referred to either by the
entire pin name or by a single function of the pin, for example,
P1.0, when only that function is relevant.
The low drift current DACs have 14-bit resolution and varied
full-scale output ranges from 0 mA to 20 mA to 0 mA to
250 mA on the SOA IDAC (IDAC3). The SOA IDAC also
comes with a 0 mA to −80 mA current sink capability.
For additional information on the ADuCM310, see the
ADuCM310 reference manual, How to Set Up and Use the
ADuCM310.
A precision 2.5 V on-chip reference source is available. The internal
ADC, IDACs, and VDAC circuits use this on-chip reference
source to ensure low drift performance for all of these peripherals
Rev. B Page 3 of 27
ADuCM310
Data Sheet
SPECIFICATIONS
AVDD = IOVDD = DVDD = 2.9 V to 3.6 V (the input supply voltages). The difference between AVDD, IOVDD, and DVDD must be ≤0.3 V.
AVNEG (the supply voltage) = −5.5 V to −4.65 V. VDACVDD (the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7),
and VDACVDD must be ≥ AVDD. PVDD (the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AVDD ≥ PVDD + 0.4V. VREF = 2.5 V
internal reference, fCORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted.
For power sequencing, connect the AGND, DGND, PGND, and IOGND pins to ground before applying power to the AVNEG or VDACVDD pins.
For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS
All measurements in single-ended
mode, unless otherwise stated
ADC Power-Up Time
DC Accuracy
5
µs
fSAMPLE ≥500 kSPS
Resolution
14
Bits
Integral Nonlinearity
Input Buffer
Disabled
2
LSB
LSB
LSB
LSB
LSB
LSB
2.5 V internal reference
2.5 V internal reference
1.51
Enabled
Disabled
2.5
2
1.51
External reference
External reference
2.5 V external reference;
no missing codes
2.5 V external reference;
no missing codes
ADC input voltage = 1.25 V dc
Differential Nonlinearity
−0.99
−0.99
0.7
+1.51
+2.0
0.7
LSB
LSB
DC Code Distribution
ENDPOINT ERRORS
3
5
Offset Error (All Channels Except
the Internal Channels)
ADC update rate up to 800 kSPS
Buffer On or Buffer Off
−0.8
0.2
0.2
+0.8
mV
mV
Buffer on, chop mode on and
automatic zero or buffer off
Buffer on, chop mode on and
automatic zero or buffer off
−0.61
+0.61
Offset Error Drift2
Buffer On or Buffer Off
3.2
µV/°C
µV/°C
Buffer on, chop mode on and
automatic zero or buffer off
Buffer on, chop mode on and
automatic zero or buffer off
2.51
Full-Scale Error
Buffer On or Buffer Off
ADC update rate up to 800 kSPS
Excluding internal channels
Excluding internal channels
−0.75
−0.71
0.2
0.2
0.2
+0.75
+0.61
+1
mV
mV
Internal Channels
% of full scale Input buffer on; AVDD/2, IOVDD/2,
PVDD voltage on PVDD_IDAC2 pin
0.2
0.61
2
% of full scale Input buffer on; AVDD/2, IOVDD/2,
PVDD voltage on PVDD_IDAC2 pin
% of full scale Input buffer on; IDAC0 to IDAC5;
measured with 1.5 V on the IDAC0
to IDAC5 pins
% of full scale Input buffer on; IDAC0 to IDAC5;
measured with 1.5 V on the IDAC0
to IDAC5 pins
0.75
0.75
2
1.51
Gain Error Drift2
µV/°C
Full-scale error drift minus offset
error drift; all modes; internal
reference
Rev. B Page 4 of 27
Data Sheet
ADuCM310
Parameter
DYNAMIC PERFORMANCE2
Min
Typ
Max
Unit
Test Conditions/Comments
fIN = 665.283 Hz sine wave; fSAMPLE
=
100 kSPS; internally unbuffered
channels; the filter on the analog
inputs is a 15 Ω resistor and a 2 nF
capacitor
Signal-to-Noise Ratio (SNR)
Input Buffer
Disabled
80
dB
Includes distortion and noise
components
Enabled
78
74
dB
dB
Chop mode on
Automatic zero
Total Harmonic Distortion (THD)
Input Buffer
Disabled
Enabled
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
−86
−86
−88
−95
dB
dB
dB
dB
Chop mode on and automatic zero
Buffer on and off
Measured on adjacent channels; fIN =
25 kHz sine wave; buffer on and off
ANALOG INPUT
Absolute Input Voltage Range
Unbuffered Mode
Buffered Mode
AGND
AGND + 0.15
AVDD
2.5
V
V
Voltage level on AINx pin
Voltage level on AINx pin
Input Voltage Ranges
Differential Mode
−VREF
+VREF
V
Voltage difference between AIN+
(positive input) and AIN− (negative
input)
Common-Mode Voltage Range
Single-Ended Mode
0.9
AGND
1.6
VREF
V
V
Voltage difference between AIN+
and AIN−
Input Current3
Buffered Mode
AIN0, AIN1, AIN2, and AIN3
VIN = 0.15 V to 2.5 V
−102
−40
−602
5
+132
+60
+902
nA
nA
nA
pA/°C
ADC sampling rate ≤ 100 kSPS
ADC sampling rate ≤ 500 kSPS
ADC sampling rate ≤ 800 kSPS
Input buffer on, ADC sampling rate ≤
500 kSPS
15
25
20
Input Current Drift
101
34
pA/°C
pA/°C
pA/°C
Input buffer on, ADC sampling rate ≤
500 kSPS
Input buffer on, ADC sampling rate ≤
800 kSPS
Input buffer on, ADC sampling rate ≤
800 kSPS
AIN4 to AIN9 ≤ 100 kSPS
ADC sampling rate ≤ 500 kSPS
ADC sampling rate ≤ 800 kSPS
VIN = 0 V to 2.5 V, all channels, all
sampling rates
201
AIN4 to AIN9
−502
20
50
−90
+750
+502
nA
nA
nA
nA
−2152
−3502
−11002
+1102
+902
Unbuffered Mode
Input Current Drift
+17002
1401
530
20
pA/°C
pA/°C
pF
VIN = 1 V
VIN = 1 V
Input Capacitance
Input Leakage Current
During ADC acquisition, buffer on
ADC off, buffer off or buffer on,
AINx connected 2.5 V
−1.62
+1
+3.52
nA
Rev. B Page 5 of 27
ADuCM310
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ON-CHIP VOLTAGE REFERENCE
Output Voltage
0.47 µF from VREF_1.2 to AGND
2.505
V
mV
ppm/°C
ppm/°C
dB
Accuracy4
5
301
44
TA = 25°C
Reference Temperature Coefficient2, 5
15
15
70
3
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time2
EXTERNAL REFERENCE INPUT2
Input Voltage Range2
Ω
ms
For ADC_CAPP, TA = 25°C
Turned on by default
38
50
1.8
2.5
V
ADC maximum reference voltage =
2.5 V
Switching Time
External to Internal Reference
Internal to External Reference
2.5
1
ms
ms
BUFFERED VREF OUTPUTS
(BUF_VREF2.5x PINS)
Output Voltage
Accuracy
Reference Temperature Coefficient2
2.5
15
V
mV
ppm/°C
5
301
TA = 25°C, load = 0.4 mA
100 nF capacitor required on both
outputs
15
2.5
3
50
ppm/°C
mV/mA
Ω
Load Regulation
Output Impedance
TA = 25°C
Load Current
1.2
mA
Power Supply Rejection Ratio
IDAC CHANNEL SPECIFICATIONS6, 7
Voltage Compliance Range2
70
dB
Output voltage compliance;
minimum compliance if IDACx set to
full scale, see Figure 15 to Figure 20
IDAC0, IDAC1, and IDAC2
IDAC4 and IDAC5
IDAC3
0.4
PVDD
200 mV
−
PVDD
–
V
V
V
V
275 mV
PVDD
200 mV
PVDD
450 mV
0.4
–
0.5
−
−3.7
−3.0
At −3.5 V, maximum sink current is
80 mA; pin voltage clamped to
−3.5 V, tolerance of clamping
voltage is 200 mV
Reference Current Generator
Reference Current
0.38
0.76
mA
mA
Using internal reference, 0.1%,
≤5 ppm, 3.16 kΩ external resistor
If the external resistor (REXT) value
drops below 1.580 kΩ, IDAC output
currents disable
IDAC Reference Current Shutdown
Threshold
Temperature Coefficient2, 5
Over Heat Shutdown
Resolution
7
135
25
ppm/°C
°C
Using internal reference;
Junction temperature
IDAC0, IDAC1, IDAC4,and IDAC5
14
14
14
Bits
Bits
Bits
11-bit MSBs and 5-bit LSBs are
guaranteed monotonic
11-bit MSBs and 5-bit LSBs are
guaranteed monotonic
0 V to 2 V compliant range, 11-bit
MSBs and 5-bit LSBs are guaranteed
monotonic
IDAC2
IDAC3
IDAC3
8
Bits
−4.5 V to 0 V compliant range
Rev. B Page 6 of 27
Data Sheet
ADuCM310
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Full-Scale Output
IDAC0 and IDAC1
IDAC4 and IDAC5
IDAC2
100
20
200
250
mA
mA
mA
mA
IDAC3
Current source
Current sink
Current sink
11-bit
−90
−801
−3
Integral Nonlinearity
Noise Current
1.5
1.5
+4
+4
LSB
LSB
−2.51
11-bit
RMS noise; maximum bandwidth
setting, IDACxCON[5:2] = 0000b
IDAC0 and IDAC1
IDAC4 and IDAC5
IDAC2
1.5
0.3
4
µA
µA
µA
µA
Measured driving 10 Ω
Measured driving 100 Ω
Measured driving 5 Ω
Measured driving 5 Ω
IDAC3
5
Full-Scale Error
IDAC0 and IDAC1
−2.31
−3.0
−0.71
−1
−1.751
−1.77
−21
0.25
+11
+1.3
0.7
+0.7
0.65
%
%
%
%
%
%
%
%
0.25
0.25
0.25
0.25
0.25
0.25
0.25
IDAC4 and IDAC 5
IDAC2
IDAC3
1.41
+1.6
−2.4
Full-Scale Error Drift vs. Temperature
IDAC4 and IDAC5
Including internal reference drift
and 5 ppm external resistor
−401
−58
−12
+301
+58
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
−12
+55
+40
+551
+90
+40
IDAC2 and IDAC3
IDAC2 and IDAC3
IDAC0 and IDAC1
Full temperature range
Reduced 25°C to 85°C range
−1451
−205
−100
+1451
+205
+100
Full temperature range
Reduced 25°C to 85°C range
Long-term stability
IDAC0 and IDAC1
Full-Scale Error Drift vs. Time8
IDAC0
200
450
500
2250
40
µA/
1000 hours
µA/
1000 hours
µA/
1000 hours
µA/
1000 hours
IDAC1
IDAC2
IDAC3
IDAC4 and IDAC5
µA/
1000 hours
Zero-Scale Error
IDAC0 and IDAC1
Pull-down current off
−1201
−180
−135
−251
−31
+751
+115
−100
+15
+15
−22
µA
µA
µA
µA
µA
µA
Pull-Down Current
IDAC4 and IDAC5
−115
−24
Increased −45°C to +85°C range
Pull-Down Current
−30
Rev. B Page 7 of 27
ADuCM310
Data Sheet
Parameter
Min
Typ
Max
Unit
µA
µA
Test Conditions/Comments
IDAC2 and IDAC3
−3501
−460
−300
+2801
+300
−160
Pull-Down Current for IDAC2
Zero-Scale Error Drift2
IDAC0 and IDAC1
−288
µA
−8501
−1400
−120
−120
300
300
50
50
1
+12001
+1400
+2051
+230
nA/°C
nA/°C
nA/°C
nA/°C
µA/°C
IDAC4 and IDAC5
IDAC2 and IDAC3
Settling Time
IDAC0, IDAC1, IDAC2, and IDAC3
1
ms
To 0.1%, IDACxCON[5:2] = 0101b,
1 mA change in output current
IDAC4 and IDAC5
2
ms
µs
IDAC0, IDAC1, IDAC2, and IDAC3
250
To 1%, IDACxCON[5:2] = 0101b,
1 mA change in output current
IDAC4 and IDAC5
IDAC0, IDAC1, IDAC2, and IDAC3
1.2
50
ms
µs
To 1%, IDACxCON[5:2] = 0000b,
1 mA change in output current
IDAC4 and IDAC5
IDAC3 Switching Time2
1.1
ms
µs
1
Time to switch from current source
to current sink
Transconductance
Analog input signal coupled on to
CDAMP_IDACx pin via 1 nF capacitor;
frequency range = 100 kHz to
1000 kHz; voltage is the peak to
peak voltage on the CDAMP_IDACx
pin of the associated IDAC; current
is peak-to-peak current change
IDAC0 and IDAC1
IDAC2
IDAC3
IDAC4 and IDAC5
IDAC Shutdown Temperature
7.99/100
12.6/100
18.6/100
1.16/100
125
mA/mV
mA/mV
mA/mV
mA/mV
°C
Die temperature; enabled via
IDACxCON[6]
VDAC CHANNEL SPECIFICATIONS6, 9, 10
DC Accuracy
Resolution
12
Bits
Relative Accuracy
VDAC0, VDAC1, and VDAC2
VDAC4 and VDAC5
VDAC3, VDAC6, and VDAC7
Differential Nonlinearity
Offset Error
−6.3
−7.3
−7
1
2
2
0.6
+10
+11
+8.5
+1
LSB
LSB
LSB
LSB
−0.99
Guaranteed monotonic
Calculated
5
4
mV
mV
2.5 V internal reference
Measured at Code 0
Actual
VDAC0, VDAC1, VDAC4, and
VDAC5
7
VDAC6 and VDAC7
VDAC2 and VDAC3
Full-Scale Error
15
−20
22
mV
mV
−30
0.71
0.9
% of full scale For VDAC2, VDAC3, VDAC4, VDAC5,
and VDAC6
% of full scale For VDAC2, VDAC3, VDAC4, VDAC5,
and VDAC6
%
%
VDAC0, VDAC1, and VDAC72
0.71
0.9
With 500 Ω load
With 500 Ω load
Rev. B Page 8 of 27
Data Sheet
ADuCM310
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VDAC0 and VDAC1
0.5
%
With 75 Ω load, over full
temperature range
VDAC7
0.5
%
With 100 Ω load, over full
temperature range
Gain Mismatch Error
0.1
0.2
0.1
0.35
%
%
%
%
VDAC0 relative to VDAC1
VDAC2 relative to VDAC3
VDAC4 relative to VDAC5
VDAC6 relative to VDAC7; both
driving a 500 Ω load
Offset Error Drift
Calculated
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
5
µV/°C
µV/°C
25
Actual
Measured at Code 0
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
13
75
µV/°C
µV/°C
Gain Error Drift
Excluding internal reference drift
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
5
ppm/°C
ppm/°C
10
Output Impedance
VDAC0, VDAC1, VDAC4,
VDAC5, VDAC6, and VDAC7
VDAC2 and VDAC3
1
Ω
Ω
1.5
Short-Circuit Current
Measured with VDAC shorted to
ground and to associated power
supply
VDAC0 and VDAC1
VDAC2 and VDAC3
VDAC4 and VDAC5
VDAC6 and VDAC7
VDAC Outputs
200
170
200
200
mA
mA
mA
mA
Capacitive load up to 0.01 µF
Output Impedance
VDAC0, VDAC1, and VDAC4
to VDAC7
VDAC2 and VDAC3
Output Range
1.8
1.2
Ω
Ω
Buffer on
VDAC0 and VDAC1
0 + Actual
Offset1
AVDD
600 mV
−0.15
–
V
V
V
V
V
RL = 75 Ω, 40 mA maximum, VOUT
maximum = 3 V
RL = 500 Ω, 10 mA maximum, VOUT
maximum = −5 V, gain = −2.25 V
RL = 300 Ω, 10 mA maximum, VOUT
maximum = 3 V
RL = 500 Ω, 10 mA maximum, VOUT
maximum = 5 V
VDAC2 and VDAC3
VDAC4 and VDAC5
VDAC6
AVNEG
+
250 mV
0 + Actual
Offset1
0 + Actual
Offset1
0 + Actual
Offset1
AVDD
300 mV
VDACVDD
250 mV
VDACVDD
700 mV
–
−
−
VDAC7
RL = 100 Ω, 50 mA maximum, VOUT
maximum = 5 V
Rev. B Page 9 of 27
ADuCM310
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DAC AC CHARACTERISTICS
Slew Rate
VDAC0, VDAC1, VDAC4, and
VDAC5
3
V/µs
VDAC2, VDAC3, and VDAC6
Voltage Output Settling Time
1.1
10
0.05
20
V/µs
µs
ms
Load =100 pF
Load = 0.01 µF
1 LSB change at major carry
(DACxDAT register change from
0x07FF0000 to 0x08000000)
Digital-to-Analog Glitch Energy
nV/sec
AC PSRR 100 Hz
VDAC0, VDAC1, VDAC4, and
VDAC5
72
dB
VDAC2 and VDAC3
VDAC6 and VDAC7
AC PSRR 1 kHz
67
64
dB
dB
VDAC0, VDAC1, VDAC4, and
VDAC5
56
dB
VDAC2 and VDAC3
VDAC6 and VDAC7
53
50
dB
dB
POWER-ON RESET (POR)
POR Trip Level
Refers to voltage at DVDD pin
Power-on level
Power-down level
2.80
2.74
2.85
2.79
65
2.9
2.83
V
V
mV
POR Hysteresis
EXTERNAL RESET
External Reset Minimum Pulse
Width2
1.5
µs
ns
Minimum pulse width required on
external RESET pin to trigger a
reset sequence
Maximum low pulse width on RESET
pin that does not generate a reset
Reset Pin Glitch Immunity2
50
TEMPERATURE SENSOR
Accuracy2
1.25
1.37
1.494
V
Indicates die temperature; ADC
measured voltage for temperature
sensor channel without calibration,
TA = 25°C
FLASH/EE MEMORY
Endurance
Data Retention
10,000
20
Cycles
Years
MHz
TJ = 85°C
INTERNAL HIGH POWER OSCILLATOR
16
Used as input to PLL to generate
80 MHz clock
Accuracy
−2.251
+2.251
+3
%
%
INTERNAL LOW POWER OSCILLATOR
Accuracy
32.768
8
8
kHz
%
−121
−22
+12
+12
LOGIC INPUTS
Input Low Voltage (VINL
)
0.2 × IOVDD
12
V
V
mA
Input High Voltage (VINH
Short-Circuit Current2
LOGIC OUTPUTS
Output High Voltage (VOH)11
Output Low Voltage (VOL)11
Short-Circuit Current2
)
0.7 × IOVDD
IOVDD − 0.4
V
V
mA
ISOURCE = 2 mA
ISINK = 2 mA
0.4
12
Rev. B Page 10 of 27
Data Sheet
ADuCM310
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT LEAKAGE CURRENT
Logic 1
Internal Pull-Up Disabled
Logic 0
Internal Pull-Up Disabled
Pull-Up
80
+6
80
+6
40
µA
nA
µA
nA
kΩ
VINH = 3.6 V
VINH = 0 V
−22
+22
−22
30
+22
72
If not disabled, disabled at reset;
pull-up can be described as an
80 µA (typical) current source
CRYSTAL INPUTS XCLKI AND XCLKO
(16 MHz)
Logic Inputs, XCLKI Only
Input Low Voltage (VINL
Input High Voltage (VINH
XCLKI Input Capacitance
XCLKO Output Capacitance
MICROCONTROLLER UNIT CLOCK RATE
Using PLL Output2
)
1.1
1.7
8
V
V
pF
pF
)
8
0.05
80
50
MHz
PROCESSOR START-UP TIME
At Power-On2
38
ms
ms
Includes kernel power-on
execution time
Includes kernel power-on
execution time
After Reset Event
1.44
After Processor Power Down
Mode 1, Mode 2, or Mode 3
POWER REQUIREMENTS
Power Supply Voltage Range
AVDD
3 to 5
fCLK
2.9
2.9
3.3
3.3
3.6
3.6
V
V
Measured between AVDDx and
AGND
Measured between IOVDDxand
AGND
IOVDD
Analog Power Supply Currents
AVDD Current
6.5
7.2
mA
ADC, VDACs, IDACs off
Digital Power Supply Current
Current in Normal Mode
DVDD
29
2.7
32
5.1
mA
mA
CLKCON1[2:0] = [000b]
All GPIO pull-ups enabled
IOVDD
Additional Power Supply Currents
ADC2
3.1
3.6
mA
ADC continuously converting at
100 kSPS
ADC Input Buffer2
IDAC2
DAC2
4.1
26.5
2.7
4.8
30
3.1
mA
mA
mA
Both buffers enabled
Total for all VDACs driving
maximum allowed load with
DACxDAT = 0
VDAC2 and VDAC32
VDAC6 and VDAC72
−1.7
1
mA
mA
IDD when VDAC2 and VDAC3 are
driving maximum allowed load
with DACxDAT set to 0
IDD sourced from the VDACVDD
supply when VDAC6 and VDAC7
are driving the maximum allowed
load with DACxDAT set to 0
1 Reduced temperature range of − 10°C to + 85°C.
2 These numbers are not production tested but are guaranteed by design or characterization data at production release.
3 The input current is the total input current including the input pad and mux leakage plus the charge current for the full input circuit. The input current relates to the
ADC sampling frequency.
Rev. B Page 11 of 27
ADuCM310
Data Sheet
4 The internal reference calibration and trimming are performed when the processor operates in normal mode with CD = 0, when ADC is enabled and converting, when
IDACs are all on, and when VDACs are on. VREF accuracy can vary under other operating conditions.
5 Measured using the following box method:
(
)
(
)
×16
VREF Maximum at Any Temperature −VREF Minimum at Any Temperature
2.5× Temperature Maximum−Temperature Minimum
6 VDAC linearity specifications are calculated with following ranges:
VDAC0 and VDAC1 = +150 mV to +2.699 V
VDAC2 and VDAC3: −150 mV to −4.22 V
VDAC4 and VDAC5: +150 mV to +2.98 V
VDAC6: +150 mV to +4.747 V
VDAC7: +150 mV to +4.297 V
7 Analog Devices, Inc., production IDAC full-scale trimming conditions include PVDD_IDACx pin voltage = 0.7 V, all IDACs on.
8 The long-term stability specifications is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
9 For all VDAC specifications for VDAC0, VDAC1, VDAC4, and VDAC5, DACxCON[10:9] = 11.
10 VDACx minimum and maximum limits apply to the internal reference only (DACxCON[1:0] = 00b). AVDDx supply valid only with typical specifications.
11 The average current from the GPIO pins must not exceed 3 mA per pin. See Figure 22.
TIMING SPECIFICATIONS
I2C Timing
Table 2. I2C Timing in Standard Mode (100 kHz)
Slave
Parameter
Description
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
Typ
Max
Unit
µs
ns
µs
ns
µs
µs
µs
µs
µs
ns
µs
µs
tL
tH
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally for 300 ns after falling edge of SCLx)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
3.45
1
15
300
3.45
3.45
Data valid acknowledge time
Table 3. I2C Timing in Fast Mode (400 kHz)
Slave
Typ
Parameter
Description
Min
1.3
0.6
0.3
100
0
0.6
0. 3
1.3
20
Max
Unit
µs
ns
µs
ns
µs
µs
µs
µs
ns
ns
µs
µs
tL
tH
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally for 300 ns after falling edge of SCLx)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
300
300
0.9
15
Data valid acknowledge time
0.9
Rev. B Page 12 of 27
Data Sheet
ADuCM310
tBUF
tR
MSB
tF
SDAx (I/O)
MSB
LSB
ACK
tDSU
tDSU
tDHD
tDHD
tRSU
tPSU
tVD;DAT
tR
tSHD
tH
tVD;ACK
1
2
TO 7
8
9
1
SCLx (I)
tL
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 2. I2C Compatible Interface Timing
SPI Timing
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
(SPIxDIV1 + 1) × tHCLK2/2
(SPIxDIV1 + 1) × tHCLK2/2
tDAV
tDSU
tDHD
tDF
tDR
tSR
0
3
½ SCLKx
SCLKx
SCLKx
25
Data output rise time
SCLKx rise time
25
tSF
SCLKx fall time
20
ns
1 For SPI0, x is 0, and for SPI1, x is 1.
2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
tDF
tDR
MOSIx
MISOx
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. B Page 13 of 27
ADuCM310
Data Sheet
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLKx low pulse width
(SPIxDIV1 + 1) × tHCLK2/2
SCLKx high pulse width
Data output valid after SCLKx edge
Data output setup before SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
(SPIxDIV1 + 1) × tHCLK2/2
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
0
3
½ SCLKx
SCLKx
SCLKx
25
25
20
20
1 For SPI0, x is 0, and for SPI1, x is 1.
2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
MOSIx
MISOx
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. B Page 14 of 27
Data Sheet
ADuCM310
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
Description
Min
10
Typ
Max
Unit
ns
tCS0/tCS1
CS0 CS1
/
to SCLKx edge
tCS
CS0 CS1
/
SCLKx
ns
M
high time between active periods
(SPIxDIV1 + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
tSL
tSH
SCLKx low pulse width
2
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
(SPIxDIV1 + 1) × tHCLK
tDAV
tDSU
tDHD
tDF
tDR
tSR
20
10
10
25
25
1
1
20
tSF
tSFS
CS0 CS1
/
high after SCLKx edge
1 For SPI0, x is 0, and for SPI1, x is 1.
2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
tCSM
CS0/CS1
tSFS
tCS0/tCS1
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
tDF
tDR
MISOx
MOSIx
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. B Page 15 of 27
ADuCM310
Data Sheet
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
Description
Min
10
Typ
Max
Unit
ns
tCS0/tCS1
CS0 CS1
/
to SCLKx edge
tCS
CS0 CS1
/
SCLKx
ns
M
high time between active periods
(SPIxDIV1 + 1) × tHCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLKx low pulse width
2
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
(SPIxDIV1 + 1) × tHCLK
20
10
10
25
25
1
1
20
10
CS0 CS1
/
Data output valid after
edge
CS0 CS1
/
high after SCLKx edge
1 For SPI0, x is 0, and for SPI1, x is 1
2 tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
tCSM
CS0/CS1
tCS0/tCS1
tSFS
SCLKx
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLKx
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISOx
MOSIx
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. B Page 16 of 27
Data Sheet
ADuCM310
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8.
Parameter
Rating
AVDD to AGNDx
AVNEG to AGNDx
VDACVDD to AGNDx
IOVDDx to DGNDx
−0.3 V to +3.96 V
−5.5 V to +0.3 V
−0.3 V to +5.5 V
−0.3 V to +3.96 V
−0.3 V to IOVDDx + 0.3 V
−0.3 V to IOVDDx + 0.3 V
−0.3 V to AVDD + 0.3 V
0 mA to 30 mA
−30 mA to 0 mA
AVNEG − 0.3 V
Table 9. Thermal Resistance
Package Type
θJA
θJC
Unit
112-Ball CSP_BGA
44.5
11
°C/W
Digital Input Voltage to DGNDx
Digital Output Voltage to DGNDx
Analog Inputs to AGNDx
Total Positive GPIO Pins Current
Total Negative GPIO Pins Current
IDAC3 Pull-Down Voltage
IDAC3 Pull-Down Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD Rating, All Pins
ESD CAUTION
−100 mA
−40°C to +85°C
−65°C to +150°C
150°C
Human Body Model (HBM)
1 kV
Field-Induced Charged Device
Model (FICDM)
1.25 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B Page 17 of 27
ADuCM310
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
RESERVED
IDAC0
PVDD_
IDAC0
IDAC2
PVDD_
IDAC2
IDAC3
PGND
PVDD_
IDAC3
PVDD_
IDAC1
IDAC1
RESERVED
A
B
C
D
E
F
IDAC4
CDAMP_
IDAC0
CDAMP_
IDAC2
IDAC2
PVDD_
IDAC2
IDAC3
PGND
PVDD_
IDAC3
CDAMP_
IDAC3
CDAMP_
IDAC1
IDAC5
P1.0/
SIN/
ECLKIN/
PLAI[4]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
P1.2/
PWM0/
PLAI[6]
P1.3/
PWM1/
PLAI[7]
PVDD_
IDAC4
CDAMP_
IDAC4
CDAMP_
IDAC5
PVDD_
IDAC5
P2.3/BM
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P2.4/IRQ5/
ADCCONV/
PWM6/
P1.7/IRQ1/
PWM5/CS1/
PLAO[13]
P1.1/SOUT/
PLACLK1/
PLAI[5]
P2.5/IRQ6/
PWM7/
PLAO[19]
P3.2/
PLAI[14]
RESERVED
IOVDD1
RESET
RESERVED
DGND2
SWCLK
IREF
IOVDD2
IOGND2
VREF_1.2
AVDD4
PLAO[18]
P2.2/IRQ4/
MRST/
CLKOUT/
PLAI[10]
P0.1/
MISO0/
PLAI[1]
P0.0/
SCLK0/
PLAI[0]
P2.1/IRQ3/
PWMSYNC/
PLAI[9]
SWDIO
ADuCM310
P0.3/
IRQ0/CS0/
PLAI[3]
P0.2/
MOSI0/
PLAI[2]
IOGND1
RESERVED
RESERVED
AIN4
VDACV
DD
AVDD_REG1
AVDD_REG2
VDAC7
TOP VIEW
(Not to Scale)
G
H
J
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P0.5/
SDA0/
PLAO[3]
P.04/
SCL0/
PLAO[2]
AGND2
VDAC6
VDAC2
VDAC3
AIN9
G
H
J
P2.6/
IRQ7/
PLAO[20]
P2.7/
IRQ8/
PLAO[21]
P3.0/
PLAI[12]
AGND5
VDAC4
VDAC1
VDAC5
DVDD
RESERVED
AIN0
AIN1
AIN2
AIN3
AIN5
P3.4/
PLAO[26]
XTALO
XTALI
P3.1/
PLAI[13]
AIN6
BUF_
VREF2.5A
AGND4
K
L
IOVDD3
DVDD_REG1
AGND1
AV
AIN7
ADC_CAPN
BUF_
VREF2.5B
K
L
NEG
IOGND3
1
DGND1
2
DVDD_REG2
3
VDAC0
4
AVDD3
5
AGND3
6
AGND6
7
AIN8
8
ADC_CAPN
10
ADC_CAPP
11
9
IDAC RELATED
DIGITAL PINS
ANALOG PINS
RESERVED
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type1 Description
D2
RESET
I
Reset Input (Active Low). An internal pull-up is included on this pin.
E3
P0.0/SCLK0/PLAI[0]
I/O
General-Purpose Input and Output Port 0.0/SPI0 Clock/Input to PLA
Element 0. This pin defaults as an input with the internal pull-up resistor
disabled.
E2
F3
F2
P0.1/MISO0/PLAI[1]
P0.2/MOSI0/PLAI[2]
P0.3/IRQ0/CS0/PLAI[3]
I/O
I/O
I/O
General-Purpose Input and Output Port 0.1/SPI0 Data Master Input-Slave
Output/Input to PLA Element 1. This pin defaults as an input with the
internal pull-up disabled.
General-Purpose Input and Output Port 0.2/SPI0 Data Master Output-
Slave Input/Input of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
General-Purpose Input and Output Port 0.3/External Interrupt Request 0/
SPI0 Chip Select Input/Input of PLA Element 3. This pin defaults as an
input with the internal pull-up disabled. If SPI0 is used, configure this pin
as CS0.
G4
P0.4/SCL0/PLAO[2]
I/O
General-Purpose Input and Output Port 0.4/I2C Interface Clock for
I2C0/Output of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
Rev. B Page 18 of 27
Data Sheet
ADuCM310
Pin No.
Mnemonic
Type1 Description
G3
P0.5/SDA0/PLAO[3]
I/O
I/O
I/O
I/O
I/O
General-Purpose Input and Output Port 0.5/I2C Interface Data for
I2C0/Output of PLA Element 3. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 0.6/I2C Interface Clock for
I2C1/Output of PLA Element 4. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 0.7/I2C Interface Data for
I2C1/Output of PLA Element 5. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 1.0/UART Input Pin/External
Input Clock/Input to PLA Element 4. The ECLKIN pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.1/UART Output Pin/PLA Input
Clock/Input to PLA Element 5. The PLACLK1 pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
G2
G1
C4
D5
P0.6/SCL1/PLAO[4]
P0.7/SDA1/PLAO[5]
P1.0/SIN/ECLKIN/PLAI[4]
P1.1/SOUT/PLACLK1/PLAI[5]
C5
C6
C7
P1.2/PWM0/PLAI[6]
I/O
I/O
I/O
General-Purpose Input and Output Port 1.2/PWM0 Output/Input to PLA
Element 6. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.3/PWM1 Output/Input to PLA
Element 7. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.4/PWM2 Output/SPI1
Clock/Output of PLA Element 10. This pin defaults as an input with
internal pull-up disabled.
P1.3/PWM1/PLAI[7]
P1.4/PWM2/SCLK1/PLAO[10]
C8
C9
D9
P1.5/PWM3/MISO1/PLAO[11]
P1.6/PWM4/MOSI1/PLAO[12]
P1.7/IRQ1/PWM5/CS1/PLAO[13]
I/O
I/O
I/O
General-Purpose Input and Output Port 1.5/PWM3 Output/SPI1 Data
Master Input-Slave Output/Output of PLA Element 11. This pin defaults as
an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.6/PWM4 Output/SPI1 Data
Master Output-Slave Input/Output of PLA Element 12. This pin defaults as
an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.7/External Interrupt Request 1/
PWM5 Output/SPI1 Chip Select Input/Output of PLA Element 13. This pin
defaults as an input with internal pull-up disabled. If SPI1 is used,
configure this pin as CS1.
D4
E8
E4
C3
D7
P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8]
P2.1/IRQ3/PWMSYNC/PLAI[9]
P2.2/IRQ4/MRST/CLKOUT/PLAI[10]
P2.3/BM
I/O
I/O
I/O
I/O
I/O
General-Purpose Input and Output Port 2.0/External Interrupt Request 2/
PWM Trip Input Source/PLA Input Clock/Input to PLA Element 8. This pin
defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 2.1/External Interrupt Request 3/
PWM Sync Input/Input to PLA Element 9. This pin defaults as an input
with the internal pull-up disabled.
General-Purpose Input and Output Port 2.2/External Interrupt Request 4/
Reset Out Pin/Clock Output/Input to PLA Element 10. This pin defaults as
an input with the internal pull-up disabled.
General-Purpose Input and Output Port 2.3/BM pin. If this pin is low, then
the device enters UART download after the next rest sequence. This pin
defaults as an input with the internal pull-up disabled.
P2.4/IRQ5/ADCCONV/PWM6/PLAO[18]
General-Purpose Input and Output Port 2.4/External Interrupt Request 5/
External Input to Start ADC Conversions/PWM6 Output/Output of
PLA Element 18. This pin defaults as an input with the internal pull-up
disabled.
D8
H1
H2
H3
P2.5/IRQ6/PWM7/PLAO[19]
P2.6/IRQ7/PLAO[20]
P2.7/IRQ8/PLAO[21]
P3.0/PLAI[12]
I/O
I/O
I/O
I/O
General-Purpose Input and Output Port 2.5/External Interrupt Request 6/
PWM7 Output/Output of PLA Element 19. This pin defaults as an input
with the internal pull-up disabled.
General-Purpose Input and Output Port 2.6/External Interrupt Request 7/
Output of PLA Element 20. This pin defaults as an input with the internal
pull-up disabled.
General-Purpose Input and Output Port 2.7/External Interrupt Request 8/
Output of PLA Element 21. This pin defaults as an input with the internal
pull-up disabled.
General-Purpose Input and Output Port 3.0/Input to PLA Element 12. This
pin defaults as an input with the internal pull-up disabled.
Rev. B Page 19 of 27
ADuCM310
Data Sheet
Pin No.
Mnemonic
Type1 Description
J3
P3.1/PLAI[13]
P3.2/PLAI[14]
P3.4/PLAO[26]
I/O
I/O
I/O
General-Purpose Input and Output Port 3.1/Input to PLA Element 13. This
pin defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 3.2/Input to PLA Element 14. This
pin defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 3.4/Output of PLA Element 26. This
pin defaults as an input with the internal pull-up disabled.
D3
J1
E10
E9
G11
SWCLK
SWDIO
VREF_1.2
I
Serial Wire Debug Clock Input Pin.
Serial Wire Debug Data Input/Output Input Pin.
1.2 V Reference Output. This pin cannot be used to source current
externally. Connect this pin to AGND via a 470 nF capacitor.
I/O
AO
D11
IREF
AI
This pin generates the reference current for the IDACs. Connect this pin to
analog ground via a 5 ppm, 3.16 kΩ external resistor (REXT).
J6
H7
J7
K7
G8
AIN0
AIN1
AIN2
AIN3
AIN4
AI
AI
AI
AI
AI
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2.
Single-Ended or Differential Analog Input 3.
Single-Ended or Differential Analog Input 4. This is also the input for the
digital comparator.
H8
J8
K8
L8
L9
L4
K4
J9
K9
J4
H5
H9
H10
A2
A3
B2
A10
A9
AIN5
AIN6
AIN7
AIN8
AIN9
VDAC0
VDAC1
VDAC2
VDAC3
VDAC4
VDAC5
VDAC6
VDAC7
IDAC0
PVDD_IDAC0
CDAMP_IDAC0
IDAC1
PVDD_IDAC1
CDAMP_IDAC1
IDAC5
PVDD_IDAC5
CDAMP_IDAC5
IDAC4
PVDD_IDAC4
CDAMP_IDAC4
IDAC2
PVDD_IDAC2
CDAMP_IDAC2
IDAC3
PVDD_IDAC3
CDAMP_IDAC3
PGND
AI
AI
AI
AI
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
12-Bit VDAC Output 0, 0 V to 3 V Range.
12-Bit VDAC Output 1, 0 V to 3 V Range.
12-Bit VDAC Output 2, −5 V to 0 V Range.
12-Bit VDAC Output 3, −5 V to 0 V Range.
12-Bit VDAC Output 4, 0 V to 3 V Range.
12-Bit VDAC Output 5, 0 V to 3 V Range.
12-Bit VDAC Output 6, 0 V to 5 V Range.
12-Bit VDAC Output 7, 0 V to 5 V Range.
IDAC0 (100 mA).
AI
AO
AO
AO
AO
AO
AO
AO
AO
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
S
Power for IDAC0.
Damping Capacitor Pin for IDAC0. Connect this pin to the PVDD supply.
IDAC1 (100 mA).
Power for IDAC1.
Damping capacitor pin for IDAC1. Connect this pin to the PVDD supply.
IDAC5 (20 mA).
Power for IDAC5.
Damping capacitor pin for IDAC5. Connect this pin to the PVDD supply.
IDAC4 (20 mA).
Power for IDAC4.
Damping capacitor pin for IDAC4. Connect this pin to the PVDD supply.
IDAC2 (200 mA).
Power for IDAC2.
Damping Capacitor for IDAC2. Connect this pin to the PVDD supply.
IDAC3 (250 mA).
Power for IDAC3.
Damping Capacitor Pin for IDAC3. Connect this pin to the PVDD supply.
Power Supply Ground of the IDACs.
Analog Ground Pins.
B10
B11
C11
C10
B1
C1
C2
A4, B4
A5, B5
B3
A6, B6
A8, B8
B9
A7, B7
K5, G9,
L6, J11,
H4, L7
AGND1, AGND2, AGND3, AGND4,
AGND5, AGND6
S
Rev. B Page 20 of 27
Data Sheet
ADuCM310
Pin No.
Mnemonic
Type1 Description
J5
DVDD
S
Digital Supply Pin. This pin is the supply for the 16 MHz oscillator, PLL,
POR, and digital core, including the flash that requires a regulated 1.8 V
supply and a 3 V supply.
F9
L5, H11
K3
VDACVDD
AVDD3, AVDD4
DVDD_REG1
S
S
S
5 V Analog Supply Pin.
Analog Supply Pin (3.3 V).
Output of 2.5 V on Chip Low Dropout (LDO) Regulator. Connect a 470 nF
capacitor to this pin and DGND. This regulator supplies the inter-die digital
interface.
L3
DVDD_REG2
AVDD_REG1
AVDD_REG2
S
S
S
Output of 1.8 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies flash and the Cortex-M3 processor.
Output of 2.5 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies the ADC.
Output of 2.5 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies the IDACs.
F10
G10
K6
E1
L2, D10
E11, K1
F1, F11,
L1
AVNEG
IOVDD1
DGND1, DGND2
IOVDD2, IOVDD3
IOGND1, IOGND2, IOGND3
S
S
S
S
S
−5 V Supply Pin.
3.3 V GPIO Supply Pin.
Digital Ground Pins.
3.3 V GPIO Supply Pins.
GPIO Ground Pins.
J2
XTALO
XTALI
DO
DI
Output from the Crystal Oscillator Inverter. If an external crystal is not
used, leave this pin unconnected.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. If an external crystal is not used, connect this pin to
the DGND system ground.
K2
J10
BUF_VREF2.5A
BUF_VREF2.5B
ADC_CAPN
AO
AO
S
Buffered 2.5 V Bias, Maximum Load = 1.2 mA. Connect this pin to AGND
via a 100 nF capacitor.
Buffered 2.5 V Bias, Maximum Load = 1.2 mA. Connect this pin to AGND
via a 100 nF capacitor.
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this
pin to AGND.
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this
pin to a 4.7 µF capacitor and connect the other side of the capacitor to
the AGND and the ADC_CAPN pins.
K11
K10, L10
L11
ADC_CAPP
S
A1, A11,
D1, F4,
F8, D6,
H6
RESERVED
Reserved. Do not connect to this pin.
1 I is input, I/O is input/output, AO is analog output, AI is analog input, S is supply, DO is digital output, and DI is digital input.
Rev. B Page 21 of 27
ADuCM310
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
600
450
400
350
300
250
200
150
100
50
500
400
300
HEADROOM 125°C
HEADROOM 125°C
200
HEADROOM 25°C
100
HEADROOM 25°C
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
Figure 11. Typical Headroom Voltage vs. Load Resistance for VDAC0,
AVDD = 3 V; Headroom = AVDD − VDAC Output Voltage
Figure 8. Typical Headroom Voltage vs. Load Resistance for VDAC7,
VDACVDD = 3 V; Headroom = VDACVDD − VDAC Output Voltage
600
500
400
300
700
600
500
400
300
HEADROOM 125°C
HEADROOM 125°C
200
200
100
HEADROOM 25°C
100
0
HEADROOM 25°C
0
0
200
400
600
800
1000
1200
0
100 200 300 400 500 600 700 800 900 1000
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
Figure 9. Typical Headroom Voltage vs. Load Resistance for VDAC7,
VDACVDD = 5 V; Headroom = VDACVDD − VDAC Output Voltage
Figure 12. Typical Headroom Voltage vs. Load Resistance for VDAC4,
AVDD = 3 V; Headroom = AVDD − VDAC Output Voltage
1000
900
0.8
0.6
0.4
800
HEADROOM 125°C
700
0.2
600
AIN0
500
0
–0.2
–0.4
–0.6
–0.8
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
HEADROOM 25°C
400
300
200
100
0
0
100 200 300 400 500 600 700 800 900 1000
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
LOAD RESISTANCE (Ω)
V
IN
Figure 10. Typical Headroom Voltage vs. Load Resistance for VDAC2,
AVNEG = −5 V; Headroom = AVNEG − VDAC Output Voltage
Figure 13. Input Current vs. VIN, VDD = 3.3 V, TA = 25°C, Unbuffered Mode, 100 kSPS
Rev. B Page 22 of 27
Data Sheet
ADuCM310
15
250
200
150
100
50
+115°C
10
5
+85°C
+25°C
0
–5
–10
–15
–20
–25
–30
–35
–40°C
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
75
100
125
150
175
200
225
V
IDAC OUTPUT CURRENT (mA)
IN
Figure 17. Typical IDAC2 PVDD_IDAC2 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Figure 14. Input Current vs. VIN, VDD = 3.3 V, TA = 25°C, Buffered Mode, 100 kSPS
250
600
+115°C
500
200
+115°C
+85°C
+85°C
400
150
+25°C
+25°C
300
–40°C
–40°C
100
200
100
0
50
0
37.5
50.0
62.5
75.0
87.5
100.0
112.5
100
125
150
175
200
225
250
275
IDAC OUTPUT CURRENT (mA)
IDAC OUTPUT CURRENT (mA)
Figure 15. Typical IDAC0 PVDD_IDAC0 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Figure 18. Typical IDAC3 PVDD_IDAC3 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
250
160
+115°C
+115°C
140
200
+85°C
120
+85°C
100
150
+25°C
+25°C
80
–40°C
–40°C
100
60
40
20
0
50
0
37.5
50.0
62.5
75.0
87.5
100.0
112.5
5
10
15
25
25
IDAC OUTPUT CURRENT (mA)
IDAC OUTPUT CURRENT (mA)
Figure 16. Typical IDAC1 PVDD_IDAC1 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Figure 19. Typical IDAC4 PVDD_IDAC4 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Rev. B Page 23 of 27
ADuCM310
Data Sheet
160
140
120
100
80
3.0
2.5
2.0
1.5
1.0
0.5
0
V
MAX
OL
V
MIN
OL
+115°C
V
MIN
OH
+85°C
+25°C
60
40
20
0
V
MAX
OH
–40°C
5
7
9
11
13
15
17
19
21
0
2
4
6
8
10
12
14
16
IDAC OUTPUT CURRENT (mA)
LOAD CURRENT (mA)
Figure 20. Typical IDAC5 PVDD_IDAC5 Pin Voltage Headroom vs.
Output Current for Different Temperatures, PVDD = 1.8 V
Figure 22. Typical Output Voltage vs. Load Current
90
3.60
80
78.2
77.6
80
70
60
50
40
30
20
10
0
77.2
61.9
AFTER 50ms DVDD MUST
STAY ABOVE 2.85V INCLUDING
NOISE EXCURSIONS
2.90
2.85
46.2
50ms min
20
DVDD MUST BE ABOVE 2.9V
FOR AT LEAST 50ms TO
COMPLETE POR
TIME (Not to Scale)
1.30
1.45
1.50
1.60
EXT V
1.80
2.00
2.50
(V)
REF
Figure 21. ADC SNR vs. External Reference Voltage (EXT VREF
)
Figure 23. DVDD Power-On Requirements
Rev. B Page 24 of 27
Data Sheet
ADuCM310
RECOMMENDED CIRCUIT AND COMPONENT VALUES
Figure 24 shows a typical connection diagram for the
ADuCM310.
The ADC reference requires a 4.7 µF capacitor between the
ADC_CAPN and ADC_CAPP balls. Directly connect
ADC_CAPN to the analog ground (AGND).
There are four digital supply balls: IOVDD1, IOVDD2,
IOVDD3, and DVDD. Decouple these balls with a 0.1 µF
capacitor placed as close as possible to each of the four balls and a
10 µF capacitor at the supply source. Similarly, the analog supply
pins, AVDD3 and AVDD4, each require a 0.1 µF capacitor
placed as close as possible to each ball with a 10 µF capacitor at
the supply source.
The ADuCM310 contains four internal regulators. These regulators
require external decoupling capacitors. The DVDD_REG1 and
DVDD_REG2 balls each requires a 0.47 µF capacitor to the
digital ground (DGND). The AVDD_REG1 and AVDD_REG2
balls each requires a decoupling capacitor to the AGND.
To generate an accurate and low drift reference current, connect the
IREF ball to the analog ground via a low parts per million
(ppm) 3.16 kΩ resistor.
The IDACs source their output currents from the PVDD supply
balls, PVDD_IDACx. Connect a 100 nF capacitor close to each
PVDD supply ball. Place at least one 10 µF capacitor at the
source of the PVDD supply (PVDD_IDACx balls).
Connect the VREF_1.2 ball to AGND via a 0.47 µF capacitor.
See Figure 24 for more details.
The IDAC output filters depend on a 10 nF capacitor placed
between the CDAMP_IDACx ball and the PVDD_IDACx ball.
Rev. B Page 25 of 27
ADuCM310
Data Sheet
IOVDD
DVDD
0.1µF
0.1µF
0.1µF 0.1µF
0.47µF
0.47µF
DGND
DGND
J5
F1
L1
E1
IOVDD1
E11
K1
L3
L2
D10
F11
K3
DVDD
PVDD
10KΩ
D2
RESET
+5V
–5V
100nF
XTALI
K2
J2
0.1µF
VDACVDD F9
XTALO
100nF
100nF
100nF
100nF
100nF
100nF
AGND
–0.1µF
AGND
AVNEG
K6
A3
PVDD_IDAC0
DVDD
10KΩ
A9 PVDD_IDAC1
PVDD_IDAC2
PVDD_IDAC2
PVDD_IDAC3
PVDD_IDAC3
A5
B5
A8
B8
ADuCM310
P2.3/BM
C3
C4
P1.0/SIN/ECLKIN/PLAI[4]
SWCLK
E10
C1 PVDD_IDAC4
PVDD_IDAC5
C11
D5
P1.1/SOUT/PLACLK1/PLAI[5
n
100
F
CDAMP_IDAC0
CDAMP_IDAC1
B2
B10
B3
SWDIO
PGND
PGND
E9
A7
10nF
10nF
10nF
10nF
10nF
10nF
CDAMP_IDAC2
CDAMP_IDAC3
CDAMP_IDAC4
CDAMP_IDAC5
B9
B7
C2
C10
G11
G10
L6 J11
L5
H11
D11 L11 L10 K10
F10
K5
G9
AVDD
0.47µF 0.47µF
0.47µF 3.16kΩ 4.7µF
0.1µF
0.1µF
AGND
RESET
GND
RESET
DGND
SWDIO
Tx
SWCLK
Rx
NO CONNECT
DVDD
DVDD
1.6Ω
10µF
0.1µF
0.1µF
DGND DGND1 AGND1
AVDD
V
IOVDD
IN
ADP7102ARDZ-3.3-R7
1.6Ω
VIN
VOUT
SENSE
EN
0.1µF
10µF
0.1µF
10kΩ
10µF
0.1µF
10µF
PG
DGND
GND
AGND AGND
+5V
–5V
ADP3605
+2.5V
PVDD
ADP1741ACPZ
V
V
IN
OUT
–
+
–
+
VOUT
VIN
0.1µF
0.1µF
AGND
0.1µF
0.1µF
31.6kΩ
0.1µF
VSENSE
+
30kΩ
10µF
PGND
10µF
C
P
+
EN
EP
ADJ
10µF
–
10kΩ
C
–
P
SD
GND
GND
SS
PGND
10µF
PGND
AGND
Figure 24. Typical Connection Diagram
Rev. B Page 26 of 27
Data Sheet
ADuCM310
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
A1 BALL
CORNER
A1 BALL
CORNER
11 10
7 4 2 1
9 8 6 5 3
A
B
C
D
E
F
5.00
REF SQ
G
H
J
0.50
BSC
K
L
BOTTOM VIEW
DETAIL A
0.50
TOP VIEW
REF
0.93
0.86
0.79
0.26
REF
DETAIL A
1.200
1.083
1.000
0.223 NOM
0.173 MIN
0.35
0.30
0.25
COPLANARITY
0.08
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-195-AC
WITH THE EXCEPTION TO BALL COUNT.
Figure 25. 112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-112-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
BC-112-4
BC-112-4
ADuCM310BBCZ
ADuCM310BBCZ-RL
EVAL-ADuCM310QSPZ
−10°C to +85°C
−10°C to +85°C
112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board with QuickStart Development System
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13040-0-7/17(B)
Rev. B Page 27 of 27
相关型号：
©2020 ICPDF网 联系我们和版权申明