ADUCM4050BCPZ_技术文档

Ultra Low Power ARM Cortex-M4F MCU

with Integrated Power Management

ADuCM4050

Data Sheet

Digital peripherals

FEATURES

3 SPI interfaces to enable glueless interface to sensors,

radios, and converters

EEMBC ULPMark™-CP score (3 V): 189

Ultra low power active and hibernate modes

Active mode dynamic current: 41 µA/MHz (typical)

Flexi mode: 400 µA (typical)

Hibernate mode: 0.65 µA (typical)

Shutdown mode: 50 nA (typical)

Shutdown mode (fast wake-up): 0.20 µA (typical)

ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM

with SWD interface

Power management

Single-supply operation (connected to VBAT pins): 1.74 V to

3.6 V

1 I²C and 2 UART peripheral interfaces

SPORT for natively interfacing with converters and radios

Programmable GPIOs (44 in LFCSP and 51 in WLCSP)

3 general-purpose timers with PWM support

RGB timer for driving RGB LED

RTC0 for time keeping

RTC1 with SensorStrobe and time stamping

Programmable beeper

27-channel DMA controller

Clocking features

26 MHz clock: on-chip oscillator, external crystal oscillator,

SYS_CLKIN for external clock, and integrated PLL

32 kHz clock: on-chip oscillator and low power crystal

oscillator

Clock fail detection for external crystals

Analog peripherals

Optional buck converter for improved efficiency

Memory options

512 kB of embedded flash memory with ECC

4 kB of cache memory to reduce active power

128 kB of configurable system SRAM with parity

Safety

Watchdog with dedicated on-chip oscillator

Hardware CRC with programmable polynomial

Multiparity bit protected SRAM

ECC protected embedded flash

Security

Hardware cryptographic accelerator supporting AES-128,

AES-256, and SHA-256

Protected key storage in flash, SHA-256-based keyed

HMAC and key wrap and unwrap

User code protection

12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital

comparator

APPLICATIONS

Internet of Things (IoT)

Smart agriculture, smart building, smart metering, smart

city, smart machine, and sensor network

Wearables

Fitness and clinical

Machine learning and neural networks

TRNG

FUNCTIONAL BLOCK DIAGRAM

52MHz CORE RATE

PLL

SERIAL WIRE

ITM TRACE

HFXTAL

LFXTAL

HFOSC

LFOSC

HP BUCK

PWR MGT

ARM

CORTEX–M4F

FLASH (512kB)

MULTI-

LAYER

AMBA

BUS

NVIC

MPU

WIC

FPU

CRYPTO

(AES-128, AES-256,

SHA 256)

DATA SRAM/

INSTRUCTION

SRAM/

MATRIX

REF BUFFER

TEMP SENSOR

ADC

DMA

KEYED HMAC

CACHE (128kB)

KEY WRAP–UNWRAP

PROTECTED

KEY STORAGE

TMR0

TMR1

RTC0

RTC1

ADC CONTROLLER

SPORT

SPIH

UART0

UART1

TRNG

AHB–APB

BRIDGE

2

PROGRAMMABLE

CRC POLYNOMIAL

SPI0

SPI1

I C

TMR2

RGB TMR

WDT

BEEPER

GPIO

Figure 1.

Rev. A

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Technical Support

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ADuCM4050

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 28

ARM Cortex-M4F Processor.................................................... 28

Memory Architecture ................................................................ 29

System Integration Features...................................................... 30

On-Chip Peripheral Features.................................................... 35

Development Support................................................................ 36

Reference Designs ...................................................................... 36

Security Features Disclaimer .................................................... 36

MCU Test Conditions................................................................ 36

Driver Types................................................................................ 36

EEMBC ULPMark™-CP Score.................................................. 37

GPIO Multiplexing......................................................................... 38

Applications Information.............................................................. 40

Silicon Anomaly ............................................................................. 43

ADuCM4050 Functionality Issues........................................... 43

Functionality Issues.................................................................... 43

Section 1. ADuCM4050 Functionality Issues......................... 44

Outline Dimensions....................................................................... 45

Ordering Guide .......................................................................... 46

Applications....................................................................................... 1

Functional Block Diagram................................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Product Highlights ........................................................................... 3

Specifications..................................................................................... 4

Operating Conditions and Electrical Characteristics.............. 4

Embedded Flash Specifications.................................................. 4

Power Supply Current Specifications......................................... 5

ADC Specifications .................................................................... 10

Temperature Sensor Specifications .......................................... 11

System Clocks ............................................................................. 12

Timing Specifications ................................................................ 13

Absolute Maximum Ratings.......................................................... 20

Thermal Resistance .................................................................... 20

ESD Caution................................................................................ 20

Pin Configuration and Function Descriptions........................... 21

Typical Performance Characteristics ........................................... 26

REVISION HISTORY

4/2019—Rev. 0 to Rev. A

6/2018—Revision 0: Initial Version

Change to Crystal Equivalent Series Resistance Parameter,

Table 10 ............................................................................................ 12

Updated Outline Dimensions....................................................... 45

Rev. A | Page 2 of 46

Data Sheet

ADuCM4050

GENERAL DESCRIPTION

The ADuCM4050 microcontroller unit (MCU) is an ultra low

power integrated microcontroller system with integrated power

management for processing, control, and connectivity. The MCU

system is based on the ARM® Cortex®-M4F processor. The

MCU also has a collection of digital peripherals, embedded

static random access memory (SRAM) and embedded flash

memory, and an analog subsystem that provides clocking, reset,

and power management capabilities in addition to an analog-

to-digital converter (ADC) subsystem.

The ADuCM4050 features a real-time clock (RTC), general-

purpose and watchdog timers, and programmable general-purpose

input/output (GPIO) pins. There is a hardware cyclic redundancy

check (CRC) calculator with programmable generator polynomial.

The device also features a power on reset (POR) and power supply

monitor (PSM), a 12-bit successive approximation register (SAR)

ADC, a red/green/blue (RGB) timer for driving RGB LED, and a

true random number generator (TRNG).

To support low dynamic and hibernate power management, the

ADuCM4050 MCU provides a collection of power modes and

features such as dynamic- and software-controlled clock gating

and power gating.

This data sheet describes the ARM Cortex-M4F core and

memory architecture used on the ADuCM4050 MCU. It does

not provide detailed programming information about the ARM

processor.

For full details on the ADuCM4050 MCU, refer to the

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with

Integrated Power Management Hardware Reference.

The system features include an up to 52 MHz ARM Cortex-

M4F processor, 512 kB of embedded flash memory with error

correction code (ECC), an optional 4 kB cache for lower active

power, and 128 kB system SRAM with parity. The ADuCM4050

features a power management unit (PMU), multilayer advanced

microcontroller bus architecture (AMBA) bus matrix, central

direct memory access (DMA) controller, and beeper interface.

PRODUCT HIGHLIGHTS

1. Ultra low power consumption.

2. Robust operation.

3. Full voltage monitoring in deep sleep modes.

4. ECC support on flash.

5. Parity error detection on SRAM memory.

6. Leading edge security.

7. Fast encryption provides read protection to user algorithms.

8. Write protection prevents device reprogramming by

unauthorized code.

9. Failure detection of 32 kHz low frequency external crystal

oscillator (LFXTAL) via interrupt.

10. SensorStrobe™ for precise time synchronized sampling of

external sensors. Works in hibernate mode, resulting in drastic

current reduction in system solutions. Current consumption

reduces by 10 times when using, for example, the ADXL363

accelerometer. Software intervention is not required after

setup. No pulse drift due to software execution.

The ADuCM4050 features cryptographic hardware supporting

advanced encryption standard (AES)-128 and AES-256 with

secure hash algorithm (SHA)-256 and the following modes:

electronic code book (ECB), cipher block chaining (CBC),

counter (CTR), and cipher block chaining-message

authentication code (CCM/CCM*) modes.

The ADuCM4050 has protected key storage with key wrap/

unwrap, and keyed hashed message authentication code (HMAC)

with key unwrap.

The ADuCM4050 supports serial port (SPORT), serial peripheral

interface (SPI), I²C, and universal asynchronous receiver/

transmitter (UART) peripheral interfaces.

Rev. A | Page 3 of 46

ADuCM4050

Data Sheet

SPECIFICATIONS

OPERATING CONDITIONS AND ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

EXTERNAL BATTERY SUPPLY VOLTAGE^{1, 2}

INPUT VOLTAGE

High Level

V_BAT

1.74

3.0

3.6

V

V_IH

V_IL

2.5

V

V_BAT= 3.6 V

V_BAT= 1.74 V

Low Level

0.45

3.6

ADC SUPPLY VOLTAGE

OUTPUT VOLTAGE³

High Level

V_{BAT_ADC}

1.74

1.4

3.0

V_OH

V_OL

V

V_BAT= 1.74 V, I_OH= −1.0 mA

V_BAT= 1.74 V, I_OL= 1.0 mA

Low Level

0.4

INPUT CURRENT PULL-UP⁴

High Level

Low Level

I_IHPU

I_ILPU

0.01

0.2

100

µA

V_BAT= 3.6 V, V_IN= 3.6 V

V_BAT= 3.6 V, V_IN= 0 V

THREE-STATE LEAKAGE CURRENT

High Level⁵

I_OZH

0.15

0.30

100

0.15

100

0.15

µA

pF

V

V_BAT= 3.6 V, V_IN= 3.6 V

V_BAT= 3.6 V, V_IN= 0 V

T_J= 25°C

Pull-Up⁶

I_OZHPU

I_OZHPD

I_OZL

I_OZLPU

I_OZLPD

C_IN

Pull-Down⁷

Low Level⁵

Pull-Up⁶

Pull-Down⁷

INPUT CAPACITANCE

V_BATPOWER-ON RESET

10

V_{VBAT_POR}

1.49

−40

1.59

1.64

+85

Power-on reset level on V_BAT; trip point

is detected when battery is decaying⁸

Junction Temperature

T_J

°C

T_AMBIENT= −40°C to +85°C

¹Value applies to VBAT_ANA1, VBAT_ANA2, VBAT_DIG1, and VBAT_DIG2 pins.

²Must remain powered (even if the associated function is not used).

³Applies to the output and bidirectional pins: P0_00 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03.

4

SYS_HWRST

Applies to the

input pin with pull-up.

⁵Applies to the three-state pins: P0_00 to P0_05, P0_08 to P0_15, P1_00 to P1_15, P2_00 to P2_15, P3_00 to P3_03.

⁶Applies to the three-state pins with pull-ups: P0_00 to P0_05, P0_07 to P0_15, P1_00 to P1_15, P2_00 to P2_15, and P3_00 to P3_03.

⁷Applies to the P0_06 three-state pin with pull-down.

⁸This specification is valid when the device is powered up; if the battery decays and falls below 1.71 V, power-on reset is detected. For safer operation of the device,

adhere to the V_BATspecification.

EMBEDDED FLASH SPECIFICATIONS

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

FLASH

Endurance

Data Retention

10,000

Cycles

Years

10

Rev. A | Page 4 of 46

Data Sheet

ADuCM4050

POWER SUPPLY CURRENT SPECIFICATIONS

Active Mode

Table 3.

Parameter

ACTIVE MODE³

Min Typ ¹Max²Unit

Test Conditions/Comments

Current consumption when V_BAT= 3.0 V

Buck Enabled

1.27 2.71

mA

Code executing from flash, cache enabled, system peripheral clock (PCLK) disabled,

advanced high performance clock (HCLK) = 26 MHz⁴

1.83 3.28

1.40 2.84

1.97 3.41

2.33 3.78

2.94 4.39

2.59 4.04

3.21 4.65

1.43 2.87

1.56 3.00

2.64 4.09

2.90 4.35

41

2.34 4.78

3.38 5.82

2.60 5.04

3.65 6.09

4.46 6.90

5.61 8.05

4.98 7.42

6.14 8.58

2.66 5.10

2.92 5.36

5.08 7.52

5.60 8.04

82

mA

Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz⁴

Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz⁵

Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz⁵

Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz⁵

Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz⁵

Code executing from SRAM, PCLK disabled, HCLK = 26 MHz⁴

Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from SRAM, PCLK disabled, HCLK = 52 MHz⁵

Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz⁵

Dynamic Current

Buck Disabled

µA/MHz Code executing from flash, cache enabled

mA

Code executing from flash, cache enabled, PCLK disabled, HCLK = 26 MHz⁴

Code executing from flash, cache disabled, PCLK disabled, HCLK = 26 MHz⁴

Code executing from flash, cache enabled, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from flash, cache disabled, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from flash, cache enabled, PCLK disabled, HCLK = 52 MHz⁵

Code executing from flash, cache disabled, PCLK disabled, HCLK = 52 MHz⁵

Code executing from flash, cache enabled, PCLK = 52 MHz, HCLK = 52 MHz⁵

Code executing from flash, cache disabled, PCLK = 52 MHz, HCLK = 52 MHz⁵

Code executing from SRAM, PCLK disabled, HCLK = 26 MHz⁴

Code executing from SRAM, PCLK = 26 MHz, HCLK = 26 MHz⁴

Code executing from SRAM, PCLK disabled, HCLK = 52 MHz⁵

Code executing from SRAM, PCLK = 52 MHz, HCLK = 52 MHz⁵

Dynamic Current

µA/MHz Code executing from flash, cache enabled

¹T_J= 25°C

²T_J= 85°C

³The code being executed is a prime number generation in a continuous loop, with high frequency RC oscillator (HFOSC) as the system clock source.

⁴Zero wait states and low buck load.

⁵One wait state and high buck load.

Rev. A | Page 5 of 46

ADuCM4050

Data Sheet

Flexi Mode

Table 4.

Parameter

FLEXI™ MODE

Buck Enabled

Min Typ ¹Max²Unit

Test Conditions/Comments

Current consumption when V_BAT= 3.0 V

PCLK disabled, HCLK = 26 MHz

PCLK = 26 MHz, HCLK = 26 MHz

PCLK disabled, HCLK = 52 MHz

PCLK = 52 MHz, HCLK = 52 MHz

PCLK disabled, HCLK = 26 MHz

PCLK = 26 MHz, HCLK = 26 MHz

PCLK disabled, HCLK = 52 MHz

PCLK = 52 MHz, HCLK = 52 MHz

0.40 1.85

0.54 1.98

0.62 2.06

0.88 2.33

0.62 3.06

0.88 3.32

1.04 3.48

1.57 4.01

mA

Buck Disabled

¹T_J= 25°C.

²T_J= 85°C.

Rev. A | Page 6 of 46

Data Sheet

ADuCM4050

Deep Sleep Modes—V_BAT= 1.8 V

Table 5.

Parameter

HIBERNATE MODE¹

Min Typ Max

Unit Test Conditions/Comments

V_BAT= 1.8 V

T_J= 25°C

0.78

µA

Real-Time Clock 1 (RTC1) and Real-Time Clock 0 (RTC0) disabled, 16 kB SRAM retained,

LFXTAL off

0.89

0.96

1.06

1.35

1.44

1.51

1.60

0.85

1.66

1.08

1.11

1.14

1.82

1.84

1.87

2.79 6.90

3.46 9.00

µA

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, low frequency RC oscillator (LFOSC) as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

V_BAT= 1.8 V

T_J= 85°C

4.73 12.50 µA

5.38 14.80 µA

6.26 16.70 µA

6.85 18.70 µA

8.12 22.30 µA

8.74 24.50 µA

2.95 7.30

8.92 25.50 µA

µA

3.16 7.77

3.16 7.78

3.22 7.92

9.07 25.70 µA

9.10 25.76 µA

9.15 25.91 µA

µA

SHUTDOWN MODE¹

T_J= 25°C

0.03

0.37

0.31 1.30

0.78 2.93

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

T_J= 85°C

FAST SHUTDOWN

MODE¹

V_BAT= 1.8 V

T_J= 25°C

0.17

0.51

0.47 1.50

0.94 3.53

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

T_J= 85°C

RTC0 enabled, LFXTAL as RTC0 source

¹Buck enable/disable does not affect power consumption.

Rev. A | Page 7 of 46

ADuCM4050

Data Sheet

Deep Sleep Modes—V_BAT= 3.0 V

Table 6.

Parameter

HIBERNATE MODE¹

Min Typ

Max

Unit

Test Conditions/Comments

V_BAT= 3.0 V

T_J= 25°C

0.65

0.72

0.77

0.83

1.09

1.13

1.17

1.22

0.68

1.26

0.87

0.95

0.97

1.38

1.46

1.48

2.00

2.38

2.98

3.29

4.04

4.41

4.94

5.20

2.11

5.32

2.53

2.61

2.64

6.03

6.10

6.12

µA

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

V_BAT= 3.0 V

T_J= 85°C

4.60

5.70

7.80

9.00

10.06

11.80

13.70

15.50

5.00

16.00

5.75

5.92

5.98

16.12

16.30

16.37

SHUTDOWN MODE¹

T_J= 25°C

0.05

0.68

0.45

1.26

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

T_J= 85°C

1.60

4.18

FAST SHUTDOWN

MODE¹

V_BAT= 3.0 V

T_J= 25°C

0.20

0.83

0.62

1.43

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

T_J= 85°C

1.80

4.74

RTC0 enabled, LFXTAL as RTC0 source

¹Buck enable/disable does not affect power consumption.

Rev. A | Page 8 of 46

Data Sheet

ADuCM4050

Deep Sleep Modes—V_BAT= 3.6 V

Table 7.

Parameter

HIBERNATE MODE¹

Min Typ

Max

Unit

Test Conditions/Comments

V_BAT= 3.6 V

T_J= 25°C

0.66

0.73

0.77

0.82

1.04

1.08

1.12

1.16

0.69

1.19

0.85

0.96

0.98

1.32

1.43

1.45

1.95

2.29

2.82

3.14

3.78

4.10

4.63

4.95

2.07

5.06

2.52

2.63

2.65

5.51

5.62

5.64

µA

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 and RTC0 disabled, 16 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 28 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 48 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 60 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 80 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 92 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 112 kB SRAM retained, LFXTAL off

RTC1 and RTC0 disabled, 124 kB SRAM retained, LFXTAL off

RTC1 enabled, 16 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 124 kB SRAM retained, LFOSC as RTC1 source

RTC1 enabled, 16 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 16 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

RTC1 enabled, 124 kB SRAM retained, LFXTAL as RTC1 source

RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC0 source

RTC1 and RTC0 enabled, 124 kB SRAM retained, LFXTAL as RTC1 and RTC0 source

V_BAT= 3.6 V

T_J= 85°C

5.00

6.00

7.20

8.20

10.00

11.00

12.30

14.90

5.30

15.20

6.19

6.48

6.53

15.34

15.64

15.71

SHUTDOWN MODE¹

T_J= 25°C

0.07

1.05

0.58

1.79

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

T_J= 85°C

1.90

5.57

FAST SHUTDOWN

MODE¹

V_BAT= 3.6 V

T_J= 25°C

0.22

1.21

0.75

1.97

µA

RTC0 disabled

RTC0 enabled, LFXTAL as RTC0 source

RTC0 disabled

T_J= 85°C

2.10

6.32

RTC0 enabled, LFXTAL as RTC0 source

¹Buck enable/disable does not affect power consumption.

Rev. A | Page 9 of 46

ADuCM4050

Data Sheet

ADC SPECIFICATIONS

Table 8.

Parameter^{1, 2}

Min Typ ³

Max

Unit

Test Conditions/Comments

1.8 V (V_BAT)/1.25 V (internal/external V_REF)

INTEGRAL NONLINEARITY ERROR

64-Lead LFCSP

4

1.6

LSB

4

64-Lead LFCSP

3.0 V (V_BAT)/2.5 V (internal/external V_REF)

−1.7 to +1.3

4

72-Ball WLCSP

1.4

LSB

1.8 V (V_BAT)/1.25 V (internal/external V_REF

)

DIFFERENTIAL NONLINEARITY ERROR

64-Lead LFCSP

4

LSB

1.8 V (V_BAT)/1.25 V (internal/external V_REF

)

−0.7 to +1.15

−0.7 to +1.1

−0.75 to +1.0

4

64-Lead LFCSP

72-Ball WLCSP

3.0 V (V_BAT)/2.5 V (internal/external V_REF)

4

1.8 V (V_BAT)/1.25 V (internal/external V_REF

)

OFFSET ERROR

64-Lead LFCSP

72-Ball WLCSP

GAIN ERROR

64-Lead LFCSP

72-Ball WLCSP

4

0.5

LSB

1.8 V (V_BAT)/1.25 V (external V_REF)

4

3.0 V (V_BAT)/2.5 V (external V_REF

)

4

1.8 V (V_BAT)/1.25 V (external V_REF

)

2.5

0.5

3.0

LSB

1.8 V (V_BAT)/1.25 V (external V_REF

)

4

3.0 V (V_BAT)/2.5 V (external V_REF

)

1.8 V (V_BAT)/1.25 V (external V_REF

)

5

I V_{BAT_ADC}

6

64-Lead LFCSP

72-Ball WLCSP

64-Lead LFCSP

129

157

124

47

51

46

µA

V

1.8 V (V_BAT)/1.25 V (internal V_REF)

6

3.0 V (V_BAT)/2.5 V (internal V_REF

)

6

1.8 V (V_BAT)/1.25 V (internal V_REF

)

7

1.8 V (V_BAT)/1.25 V (external V_REF)

7

3.0 V (V_BAT)/2.5 V (external V_REF

)

7

72-Ball WLCSP

1.8 V (V_BAT)/1.25 V (external V_REF)

INTERNAL REFERENCE VOLTAGE

1.25

2.50

Internal reference, 1.25 V selected

Internal reference, 2.5 V selected

V

ADC SAMPLING FREQUENCY (f_S)⁸

0.01

1.8

MSPS

¹The ADC is characterized in standalone mode without core activity and minimal or no switching on the adjacent ADC channels and digital inputs/outputs.

²The specifications are characterized after performing internal ADC offset calibration.

³T_J= 25°C.

⁴f_IN= 1068 Hz, f_S= 100 kSPS, internal reference in low power mode, 400,000 samples end point method used.

⁵Current consumption from VBAT_ADC supply when ADC is performing the conversion.

⁶f_IN= 1068 Hz, f_S= 100 kSPS, internal reference in low power mode.

⁷f_IN= 1068 Hz, f_S= 100 kSPS, sine wave with 1.25 V p-p applied at ADC0_VIN1 channel input.

⁸Effects of analog source impedance must be considered when selecting ADC sampling frequency.

Rev. A | Page 10 of 46

Data Sheet

ADuCM4050

TEMPERATURE SENSOR SPECIFICATIONS

Table 9.

Parameter

Min

Typ

Max Unit

Test Conditions/Comments

TEMPERATURE SENSOR

Internal reference = 1.25 V with C_LOAD= 0.1 μF and 4.7 μF

on the VREFP_ADC pin

Accuracy

2

3

°C

T_AMBIENT= 25°C to +5°C

T_AMBIENT= −40°C to +85°C

Rev. A | Page 11 of 46

ADuCM4050

Data Sheet

SYSTEM CLOCKS

External Crystal Oscillator Specifications

Table 10.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LOW FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (LFXTAL)

Frequency

External Capacitance from

f_LFXTAL

C_LFXTAL

32,768

Hz

pF

6

10

External capacitors on SYS_LFXTAL_IN

and SYS_LFXTAL_OUT pins must be

selected considering the printed circuit

board (PCB) trace capacitance due to

routing

SYS_LFXTAL_IN Pin to Ground and

from SYS_LFXTAL_OUT Pin to Ground

Crystal Equivalent Series Resistance

Crystal Drive Level¹

Oscillator Transconductance¹

ESR_LFXTAL

gm_LFXTAL

30

8

50

kΩ

nW

µS

HIGH FREQUENCY EXTERNAL CRYSTAL

OSCILLATOR (HFXTAL)

Frequency

External Capacitance from

SYS_HFXTAL_IN Pin to Ground and

from SYS_HFXTAL_OUT Pin to Ground

f_HFXTAL

C_HFXTAL

26

MHz

pF

20

50

External capacitors on SYS_HFXTAL_IN

and SYS_HFXTAL_OUT pins must be

selected considering the PCB trace

capacitance due to routing

Crystal Equivalent Series Resistance

¹Guaranteed by design.

ESR_HFXTAL

Ω

On-Chip Resistor-Capacitor (RC) Oscillator Specifications

Table 11.

Parameter

Symbol

f_LFOSC

f_HFOSC

Min

Typ

Max

Unit

Hz

LOW FREQUENCY RC OSCILLATOR (LFOSC)

Frequency

30,800

25.03

32,768

26

35,062

27.07

HIGH FREQUENCY RC OSCILLATOR (HFOSC)

Frequency

MHz

System Clocks and Phase-Locked Loop (PLL) Specifications

Table 12.

Parameter

Symbol

Min

Typ

Max

Unit

PLL SPECIFICATIONS

PLL Input Clock Frequency¹

f_PLLIN

f_PLLOUT

f_PCLK

16

0.8125

26

60

52

MHz

PLL Output Clock Frequency^{2, 3}

System Peripheral Clock (PCLK) Frequency

Advanced High Performance Bus Clock (HCLK) Frequency

f_HCLK

¹The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC).

²For the maximum value, the recommended settings are PLL MSEL = 13, PLL NSEL = 16, PLL DIV2 = 1 for PLL input clock = 26 MHz; and PLL MSEL = 13, PLL NSEL = 26,

PLL DIV2 = 1 for PLL input clock = 16 MHz; see the ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Hardware Reference for

more information on these configuration options.

³For the minimum value, the recommended settings are PLL MSEL = 13, PLL NSEL = 30, PLL DIV2 = 0 for PLL input clock = 26 MHz; and PLL MSEL = 8, PLL NSEL = 30,

PLL DIV2 = 0 for 16 MHz.

Rev. A | Page 12 of 46

Data Sheet

ADuCM4050

TIMING SPECIFICATIONS

Reset Timing

Table 13.

Parameter

Symbol

Min

Typ

Max

Unit

RESET TIMING REQUIREMENTS

SYS_HWRST Asserted Pulse Width Low¹

t_WRST

4

µs

¹Applies after power-up sequence is complete.

t_WRST

SYS_HWRST

Figure 2. Reset Timing

Serial Ports Timing

Table 14.

Parameter

Symbol Min

Typ Max Unit Test Conditions/Comments

EXTERNAL CLOCK SERIAL PORTS

Timing Requirements

Frame Sync Setup Before SPORT Clock¹

t_SFSE

t_HFSE

5

ns

Externally generated frame sync

in transmit or receive mode

Externally generated frame sync

in transmit or receive mode

Frame Sync Hold After SPORT Clock¹

Receive Data Setup Before Receive SPORT Clock¹

Receive Data Hold After SPORT Clock¹

SPORT Clock Width²

t_SDRE

t_HDRE

t_SCLKW

t_SPTCLK

5

8

38.5

77

ns

SPORT Clock Period²

Switching Characteristics³

Frame Sync Delay After SPORT Clock

t_DFSE

20

ns

Internally generated frame sync in

transmit or receive mode

Internally generated frame sync in

transmit or receive mode

Frame Sync Hold After SPORT Clock

t_HOFSE

2

1

Transmit Data Delay After Transmit SPORT Clock

Transmit Data Hold After Transmit SPORT Clock

INTERNAL CLOCK SERIAL PORTS

t_DDTE

t_HDTE

ns

Timing Requirements¹

Receive Data Setup Before SPORT Clock

Receive Data Hold After SPORT Clock

Switching Characteristics

t_SDRI

t_HDRI

25

0

ns

Frame Sync Delay After SPORT Clock³

t_DFSI

20

ns

Internally generated frame sync in

transmit or receive mode

Internally generated frame sync in

transmit or receive mode

Frame Sync Hold After SPORT Clock³

t_HOFSI

−8

Transmit Data Delay After SPORT Clock³

Transmit Data Hold After SPORT Clock³

SPORT Clock Width

t_DDTI

t_HDTI

t_SCLKIW

t_SPTCLK

ns

−7

t_PCLK− 1.5

(2 × t_PLCK) − 1

SPORT Clock Period

Rev. A | Page 13 of 46

ADuCM4050

Data Sheet

Parameter

Symbol Min

Typ Max Unit Test Conditions/Comments

ENABLE AND THREE-STATE SERIAL PORTS

Switching Characteristics

Data Enable from Internal Transmit SPORT Clock³t_DDTIN

Data Disable from Internal Transmit SPORT Clock³t_DDTTI

5

ns

160

¹This specification is referenced to the sample edge.

²This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external SPORT Clock.

³These specifications are referenced to the drive edge.

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSI

t_HOFSI

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

t_SDRI

t_HDRI

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 3. Serial Ports (Data Receive Mode through Internal Clock)

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

SPT0_A/SPT0_BCLK

(SPORT CLOCK)

t_DFSI

t_HOFSI

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

t_DDTI

t_HDTI

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 4. Serial Ports (Data Transmit Mode through Internal Clock)

DRIVE EDGE

SAMPLE EDGE

t_SCLKW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSE

t_HOFSE

t_SFSE

t_HFSE

SPT0_AFS/SPT0_BFS

(FRAME SYNC)

t_SDRE

t_HDRE

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 5. Serial Ports (Data Receive Mode through External Clock)

Rev. A | Page 14 of 46

Data Sheet

ADuCM4050

DRIVE EDGE

SAMPLE EDGE

t_SCLKIW

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK)

t_DFSI

t_HOFSI

t_SFSE

t_HFSE

SPT0__AFS/SPT0__BFS

(FRAME SYNC)

t_DDTE

t_HDTE

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 6. Serial Ports (Data Transmit Mode through External Clock)

DRIVE EDGE

SPT0_ACLK/SPT0_BCLK

(SPORT CLOCK INTERNAL)

t_DDTIN

t_DDTTI

SPT0_AD0/SPT0_BD0

(DATA CHANNEL A/B)

Figure 7. Enable and Three-State Serial Ports

Rev. A | Page 15 of 46

ADuCM4050

Data Sheet

SPI Timing

Table 15.

Parameter¹

Symbol

Min

Typ

Max

Unit

SPI MASTER MODE TIMING

Timing Requirements

Chip Select (CS) to Serial Clock (SCLK) Edge

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_CS

t_SL

t_SH

t_DSU

t_DHD

(2 × t_PCLK) − 6.5

t_PCLK− 3.5

5

ns

20

Data Output Valid After SCLK Edge

Data Output Setup Before SCLK Edge

CS High After SCLK Edge

t_DAV

t_DOSU

t_SFS

25

ns

t_PCLK− 2.2

t_PCLK+ 2

High Speed SPI (SPIH) MASTER MODE TIMING

Timing Requirements

CS to SCLK Edge

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_CS

t_SL

t_SH

t_DSU

t_DHD

(2 × t_PCLK) − 6.5

t_PCLK− 2

3.5

ns

12

Data Output Valid After SCLK Edge

Data Output Setup Before SCLK Edge

CS High After SCLK Edge

t_DAV

t_DOSU

t_SFS

12.5

ns

t_PCLK− 2.2

t_PCLK+ 2

SPI SLAVE MODE TIMING

Timing Requirements

CS to SCLK Edge

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_CS

t_SL

t_SH

t_DSU

t_DHD

38.5

6

ns

8

Data Output Valid After SCLK Edge

Data Output Valid After CS Edge

CS High After SCLK Edge

t_DAV

t_DOCS

t_SFS

20

ns

38.5

SPIH SLAVE MODE TIMING

Timing Requirements

CS to SCLK Edge

SCLK Low Pulse Width

SCLK High Pulse Width

Data Input Setup Time Before SCLK Edge

Data Input Hold Time After SCLK Edge

Switching Characteristics

t_CS

t_SL

t_SH

t_DSU

t_DHD

19.23

1

ns

1

Data Output Valid After SCLK Edge

Data Output Valid After CS Edge

CS High After SCLK Edge

t_DAV

t_DOCS

t_SFS

15

ns

19.23

¹These specifications are characterized with respect to double drive strength.

Rev. A | Page 16 of 46

Data Sheet

ADuCM4050

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

MSB

BIT 6 TO BIT 1

LSB

MOSI

MISO

LSB IN

MSB IN

t_DSU

t_DHD

Figure 8. SPI Master Mode Timing (Phase Mode = 1)

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

t_DOSU

MOSI

MISO

MSB

BIT 6 TO BIT 1

LSB

BIT 6 TO

BIT 1

LSB IN

MSB IN

t_DSU

t_DHD

Figure 9. SPI Master Mode Timing (Phase Mode = 0)

CS

t_SFS

t_CS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

MISO

MOSI

MSB

BIT 6 TO BIT 1

LSB

LSB IN

MSB IN

t_DSU

t_DHD

Figure 10. SPI Slave Mode Timing (Phase Mode = 1)

Rev. A | Page 17 of 46

ADuCM4050

Data Sheet

CS

t_CS

t_SFS

SCLK

(POLARITY = 0)

t_SH

t_SL

SCLK

(POLARITY = 1)

t_DAV

t_DOCS

MISO

MSB

BIT 6 TO BIT 1

LSB

MOSI

LSB IN

MSB IN

t_DSU

t_DHD

Figure 11. SPI Slave Mode Timing (Phase Mode = 0)

Rev. A | Page 18 of 46

Data Sheet

ADuCM4050

I²C Specifications

Table 16.

Parameter

Symbol

Min

Typ

Max

Unit

I²C SCLK FREQUENCY

Standard Mode

Fast Mode

100

400

kHz

General-Purpose Port Timing

Table 17.

Parameter

Symbol

Min

Typ

Unit

TIMING REQUIREMENTS

General-Purpose Port Pin Input Pulse Width

t_WFI

4 × t_PCLK

ns

t_WFI

GPIO INPUT

Figure 12. General-Purpose Timing

RTC1 (FLEX_RTC) Specifications

Table 18.

Parameter

Symbol

Min

Typ

Max

Unit

SensorStrobe

Minimum Output Frequency

Maximum Output Frequency

RTC1 ALARM

0.5

16.384

Hz

kHz

Minimum Time Resolution

30.52

µs

Timer Pulse-Width Modulation (PWM) Output Cycle Timing

Table 19.

Parameter

Symbol

Min

Typ

Max

256 × (216 − 1)

Unit

SWITCHING REQUIREMENTS

Timer Pulse Width Modulation Output

t_PWMO

(4 × t_PCLK) − 6

ns

t_PWMO

PWM OUTPUTS

Figure 13. Timer PWM Output Cycle Timing

Rev. A | Page 19 of 46

ADuCM4050

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 20.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required. θ_JAcan be used for a first-order

approximation of T_Jby the following equation:

Parameter

Rating

Supply

VBAT_ANA1, VBAT_ANA2, VBAT_ADC, −0.3 V to +3.6 V

VBAT_DIG1, VBAT_DIG2, and

VREFP_ADC

Analog

T_J= T_A+ (θ_JA× P_D)

where:

VDCDC_CAP1N, VDCDC_CAP1P,

VDCDC_OUT, VDCDC_CAP2N, and

VDCDC_CAP2P

VLDO_OUT, SYS_HFXTAL_IN,

SYS_HFXTAL_OUT, SYS_LFXTAL_IN,

and SYS_LFXTAL_OUT

−0.3 V to +3.6 V

−0.3 V to +1.32 V

T_Ais ambient temperature (°C).

T_Jis junction temperature (°C).

P_Dis power dissipation (to calculate power dissipation.

Table 21. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

Digital Input/Output

CP-64-17

26.3

1.0

°C/W

P0_xx, P1_xx, P2_xx, P3_xx, and

SYS_HWRST

−0.3 V to +3.6 V

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 20 of 46

Data Sheet

ADuCM4050

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

VBAT_DIG2

P0_13

P1_05

P1_02

P3_02

P0_10

P0_03

P0_00

VBAT_ANA1

A

B

C

D

E

F

P1_00

P0_14

P0_15

P2_01

P1_04

P1_03

P3_00

P3_01

P1_12

P3_03

P0_11

P0_04

P1_10

P0_02

P2_06

P0_01

GND_ANA

P2_05

SYS_HFXTAL_OUT SYS_HFXTAL_IN

SYS_LFXTAL_IN

VDCDC_CAP1N

SYS_LFXTAL_OUT

P1_13

P1_14

P2_02

VBAT_ANA2

P1_11

P1_01

P0_08

P1_15

P0_09

P1_06

P2_15

P1_09

GND_DIG

SYS_HWRST

VBAT_ADC

VDCDC_OUT

VDCDC_CAP1P

VDCDC_CAP2N

P2_14

P2_08

VREFP_ADC

VDCDC_CAP2P

P2_00

P0_12

P2_11

P1_07

P1_08

P0_06

P0_07

P2_13

P2_12

P2_09

P0_05

P2_04

P2_07

GND_ADC

VLDO_OUT

G

H

VBAT_DIG1

P2_03

GND_VREFADC

ADuCM4050

TOP VIEW

(BALL SIDE DOWN)

Not to Scale

Figure 14. 72-Ball WLCSP Pin Configuration

Table 22. 72-Ball WLCSP Pin Function Descriptions

Pin No. Mnemonic

Signal Names

Description

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section for more information.

A1

A2

A3

A4

A5

VBAT_DIG2

P0_13

P1_05

P1_02

P3_02

Not applicable

GPIO13/SYS_WAKE2

GPIO21, SPI2_CS0

GPIO18, SPI2_CLK

GPIO50, RGB_TMR0_3,

SPT0_AD0

A6

A7

P0_10

P0_03

GPIO10, UART0_TX

GPIO03, SPI0_CS0, SPT0_BCNV,

SPI2_RDY

GPIO. See the GPIO Multiplexing section for more information.

A8

A9

B1

B2

B3

B4

P0_00

VBAT_ANA1

P1_00

P0_15

P1_04

GPIO00, SPI0_CLK, SPT0_BCLK

Not applicable

GPIO16/SYS_WAKE1

GPIO15/SYS_WAKE0

GPIO20, SPI2_MISO

GPIO. See the GPIO Multiplexing section for more information.

External Supply for Analog Circuits in the MCU.

GPIO. See the GPIO Multiplexing section for more information.

P3_00

GPIO48, RGB_TMR0_1,

SPT0_ACLK

B5

P3_03

GPIO51, SPT0_ACNV

GPIO. See the GPIO Multiplexing section for more information.

Rev. A | Page 21 of 46

ADuCM4050

Data Sheet

Pin No. Mnemonic

Signal Names

Description

B6

P1_10

GPIO26, SPI0_CS1, SYS_CLKIN,

SPI1_CS3

GPIO. See the GPIO Multiplexing section for more information.

B7

B8

B9

C1

C2

C3

C4

P0_01

GPIO01, SPI0_MOSI, SPT0_BFS

GPIO. See the GPIO Multiplexing section for more information.

High Frequency Crystal Output.

High Frequency Crystal Input.

SYS_HFXTAL_OUT Not applicable

SYS_HFXTAL_IN

P0_14

P2_01

P1_03

Not applicable

GPIO14, TMR0_OUT, SPI1_RDY

GPIO33/SYS_WAKE3, TMR2_OUT GPIO. See the GPIO Multiplexing section for more information.

GPIO19, SPI2_MOSI

GPIO49, RGB_TMR0_2,

SPT0_AFS

GPIO. See the GPIO Multiplexing section for more information.

P3_01

C5

C6

C7

C8

C9

D1

D2

D3

D4

D5

D6

D7

D8

D9

E1

P0_11

P0_02

GPIO11, UART0_RX

GPIO02, SPI0_MISO, SPT0_BD0

Not applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Reference for Analog Circuits in the MCU.

Low Frequency Crystal Output.

Low Frequency Crystal Input.

GPIO. See the GPIO Multiplexing section for more information.

External Supply for Analog Circuits in the MCU.

GND_ANA

SYS_LFXTAL_OUT Not applicable

SYS_LFXTAL_IN

P1_13

P1_14

P2_02

P1_12

P0_04

P2_06

Not applicable

GPIO29, TMR2_OUT

GPIO30, SPI0_RDY

GPIO34, SPT0_ACNV, SPI1_CS2

GPIO28, RTC1_SS2

GPIO04, I2C0_SCL

GPIO38, ADC0_VIN3

GPIO37, ADC0_VIN2

Not applicable

GPIO27, TMR1_OUT

GPIO08, BPR0_TONE_N

GPIO09, BPR0_TONE_P,

SPI2_CS1

P2_05

VBAT_ANA2

VDCDC_CAP1N

P1_11

P0_08

P0_09

Buck Converter Capacitor 1 Negative Terminal.

GPIO. See the GPIO Multiplexing section for more information.

E2

E3

E4

P2_15

GPIO47, SPI2_CS2, SPI1_CS3,

SPI0_CS1

GPIO. See the GPIO Multiplexing section for more information.

E5

E6

E7

E8

GND_DIG

Not applicable

Ground Reference for Digital Circuits in the MCU.

Hardware Reset Pin.

SYS_HWRST

VBAT_ADC

VDCDC_OUT

External Supply for Internal ADC.

Buck Converter Output. This pin is only for connecting the decoupling

capacitor. Do not connect to external load.

E9

F1

F2

F3

F4

F5

F6

VDCDC_CAP1P

P1_01

P1_15

P1_06

P1_09

Not applicable

SYS_BMODE0, GPIO17

GPIO31, SPT0_ACLK, UART1_TX

GPIO22, SPI1_CLK, RGB_TMR0_1 GPIO. See the GPIO Multiplexing section for more information.

GPIO25, SPI1_CS0, SWV

GPIO46, SPI0_CS3

Buck Converter Capacitor 1 Positive Terminal.

GPIO. See the GPIO Multiplexing section for more information.

P2_14

P2_08

GPIO40, ADC0_VIN5, SPI0_CS2,

RTC1_SS3

F7

F8

F9

G1

G2

VREFP_ADC

VDCDC_CAP2P

VDCDC_CAP2N

P2_00

Not applicable

GPIO32, SPT0_AFS, UART1_RX

GPIO12, SPT0_AD0,

UART0_SOUT_EN

External Reference Voltage for Internal ADC.

Buck Converter Capacitor 2 Positive Terminal.

Buck Converter Capacitor 2 Negative Terminal.

GPIO. See the GPIO Multiplexing section for more information.

P0_12

G3

P1_07

GPIO23, SPI1_MOSI,

RGB_TMR0_2

GPIO. See the GPIO Multiplexing section for more information.

G4

G5

G6

P0_06

P2_13

P2_09

SWD0_CLK, GPIO06

GPIO45, UART1_RX, SPI0_CS2

GPIO41, ADC0_VIN6, SPI0_CS3

GPIO. See the GPIO Multiplexing section for more information.

Rev. A | Page 22 of 46

Data Sheet

ADuCM4050

Pin No. Mnemonic

Signal Names

Description

G7

G8

G9

P2_04

GND_ADC

VLDO_OUT

GPIO36, ADC0_VIN1

Not applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Pin for Internal ADC.

Low Drop Out Regulator Output. This pin is only for connecting the

decoupling capacitor. Do not connect to external load.

H1

H2

VBAT_DIG1

P2_11

Not applicable

External Supply for Digital Circuits in the MCU.

GPIO43, SPI1_CS1, SYS_CLKOUT, GPIO. See the GPIO Multiplexing section for more information.

RTC1_SS1

H3

P1_08

GPIO24, SPI1_MISO,

RGB_TMR0_3

GPIO. See the GPIO Multiplexing section for more information.

H4

H5

H6

H7

H8

H9

P0_07

P2_12

P0_05

P2_07

P2_03

GND_VREFADC

SWD0_DATA, GPIO07

GPIO44, UART1_TX, SPI2_CS3

GPIO05, I2C0_SDA

GPIO39, ADC0_VIN4, SPI2_CS3

GPIO35, ADC0_VIN0

GPIO. See the GPIO Multiplexing section for more information.

Ground for ADC Reference Supply.

Not applicable

Rev. A | Page 23 of 46

ADuCM4050

Data Sheet

48 GND_DIG

47 P1_00

46 P0_14

45 P2_02

44 P1_14

43 P1_13

42 P1_12

41 P1_11

40 P0_08

39 P0_09

38 P1_01

37 P1_15

36 P2_00

35 P0_12

34 VBAT_DIG1

33 P2_11

VBAT_ANA1

SYS_HFXTAL_IN

SYS_HFXTAL_OUT

SYS_LFXTAL_IN

SYS_LFXTAL_OUT

VDCDC_CAP1N

VDCDC_CAP1P

VBAT_ANA2

1

2

3

4

5

6

7

8

9

ADuCM4050

TOP VIEW

(Not to Scale)

VDCDC_OUT

VDCDC_CAP2N 10

VDCDC_CAP2P 11

VLDO_OUT 12

VREF_ADC 13

VBAT_ADC 14

GND_VREFDAC 15

P2_03 16

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE GROUNDED.

Figure 15. 64-Lead LFCSP Pin Configuration

Table 23. 64-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic

Signal Names

Not applicable

Description

1

2

3

4

5

6

7

8

9

VBAT_ANA1

SYS_HFXTAL_IN

External Supply for Analog Circuits in the MCU.

High Frequency Crystal Input.

High Frequency Crystal Output.

Low Frequency Crystal Input.

Low Frequency Crystal Output.

Buck Converter Capacitor 1 Negative Terminal.

Buck Converter Capacitor 1 Positive Terminal.

External Supply for Analog Circuits in the MCU.

Buck Converter Output. This pin is only for connecting the decoupling

capacitor. Do not connect to external load.

SYS_HFXTAL_OUT Not applicable

SYS_LFXTAL_IN Not applicable

SYS_LFXTAL_OUT Not applicable

VDCDC_CAP1N

VDCDC_CAP1P

VBAT_ANA2

Not applicable

VDCDC_OUT

10

11

12

VDCDC_CAP2N

VDCDC_CAP2P

VLDO_OUT

Not applicable

Buck Converter Capacitor 2 Negative Terminal.

Buck Converter Capacitor 2 Positive Terminal.

Low Dropout Regulator Output. This pin is only for connecting the

decoupling capacitor. Do not connect to external load.

13

14

15

16

17

18

19

20

21

VREF_ADC

VBAT_ADC

GND_VREFADC

P2_03

P2_04

P2_05

P2_06

P2_07

P2_08

Not applicable

GPIO35, ADC0_VIN0

GPIO36, ADC0_VIN1

GPIO37, ADC0_VIN2

GPIO38, ADC0_VIN3

GPIO39, ADC0_VIN4, SPI2_CS3

External Reference Voltage for Internal ADC.

External Supply for Internal ADC.

Ground for Internal ADC.

GPIO. See the GPIO Multiplexing section for more information.

GPIO40, ADC0_VIN5, SPI0_CS2,

RTC1_SS3

22

23

24

25

26

27

P2_09

P2_10

P0_05

SYS_HWRST

P0_04

GPIO41, ADC0_VIN6, SPI0_CS3

GPIO42, ADC0_VIN7, SPI2_CS2

GPIO05, I2C0_SDA

GPIO. See the GPIO Multiplexing section for more information.

GPIO.

GPIO. See the GPIO Multiplexing section for more information.

Hardware Reset Pin.

Not applicable

GPIO04, I2C0_SCL

SWD0_DATA, GPIO07

GPIO. See the GPIO Multiplexing section for more information.

P0_07

Rev. A | Page 24 of 46

Data Sheet

ADuCM4050

Pin No. Mnemonic

Signal Names

Description

28

29

30

P0_06

P1_09

P1_08

SWD0_CLK, GPIO06

GPIO25, SPI1_CS0, SWV

GPIO24, SPI1_MISO,

RGB_TMR0_3

GPIO. See the GPIO Multiplexing section for more information.

31

P1_07

GPIO23, SPI1_MOSI,

RGB_TMR0_2

GPIO. See the GPIO Multiplexing section for more information.

32

33

P1_06

P2_11

GPIO22, SPI1_CLK, RGB_TMR0_1 GPIO. See the GPIO Multiplexing section for more information.

GPIO43, SPI1_CS1, SYS_CLKOUT, GPIO. See the GPIO Multiplexing section for more information.

RTC1_SS1

34

35

VBAT_DIG1

P0_12

Not applicable

GPIO12, SPT0_AD0,

UART0_SOUT_EN

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section for more information.

36

37

38

39

P2_00

P1_15

P1_01

P0_09

GPIO32, SPT0_AFS, UART1_RX

GPIO31, SPT0_ACLK, UART1_TX

SYS_BMODE0, GPIO17

GPIO09, BPR0_TONE_P,

SPI2_CS1

GPIO. See the GPIO Multiplexing section for more information.

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

P0_08

P1_11

P1_12

P1_13

P1_14

P2_02

P0_14

P1_00

GND_DIG

VBAT_DIG2

P0_15

P0_13

P2_01

P1_05

P1_04

P1_03

P1_02

P0_11

P0_10

P1_10

GPIO08, BPR0_TONE_N

GPIO27, TMR1_OUT

GPIO28, RTC1_SS2

GPIO29, TMR2_OUT

GPIO30, SPI0_RDY

GPIO34, SPT0_ACNV, SPI1_CS2

GPIO14, TMR0_OUT, SPI1_RDY

GPIO16/SYS_WAKE1

Not applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Reference for Digital Circuits in the MCU.

Not applicable

GPIO15/SYS_WAKE0

GPIO13/SYS_WAKE2

External Supply for Digital Circuits in the MCU.

GPIO. See the GPIO Multiplexing section for more information.

GPIO33/SYS_WAKE3, TMR2_OUT GPIO. See the GPIO Multiplexing section for more information.

GPIO21, SPI2_CS0

GPIO20, SPI2_MISO

GPIO19, SPI2_MOSI

GPIO18, SPI2_CLK

GPIO11, UART0_RX

GPIO10, UART0_TX

GPIO. See the GPIO Multiplexing section for more information.

GPIO26, SPI0_CS1, SYS_CLKIN,

SPI1_CS3

60

P0_03

GPIO03, SPI0_CS0, SPT0_BCNV,

SPI2_RDY

GPIO. See the GPIO Multiplexing section for more information.

61

62

63

64

P0_02

P0_01

P0_00

GND_ANA

EPAD

GPIO02, SPI0_MISO, SPT0_BD0

GPIO01, SPI0_MOSI, SPT0_BFS

GPIO00, SPI0_CLK, SPT0_BCLK

Not applicable

GPIO. See the GPIO Multiplexing section for more information.

Ground Reference for Analog Circuits in the MCU.

Not applicable

Exposed Pad. The exposed pad must be grounded.

Rev. A | Page 25 of 46

ADuCM4050

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 16 through Figure 21 show the typical current voltage characteristics for the output drivers of the MCU. The curves represent the

current drive capability of the output drivers as a function of output voltage.

V

(V)

V

(V)

OH

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

2.5

2.6

2.7

2.8

2.9

3.0

5

4

5

4

V

, V

= 3.0V

V

, V

= 1.74V

OH BAT

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OH

3

2

1

0

–1

–2

–3

–4

–5

–1

–2

–3

–4

–5

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

, V

= 1.74V

0.2

V

, V

= 3.0V

OL BAT

0

0.1

0.3

(V)

0.4

0.5

0.6

0

0.05

0.10

0.15

V (V)

OL

0.20

0.25

0.30

V

OL

Figure 16. Output Double Drive Strength Characteristics (V_BAT= 1.74 V)

Figure 18. Output Double Drive Strength Characteristics (V_BAT= 3.0 V)

V

(V)

V

(V)

OH

1.1

1.2

1.3

1.4

1.5

1.6

1.7

= 1.74V

1.8

2.6

2.7

2.8

2.9

= 3.0V

3.0

2.5

2.0

2.5

2.0

1.5

1.0

0.5

0

V

, V

V

, V

OH BAT

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OH

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–0.5

–1.0

–1.5

–2.0

–2.5

V

TYPE A

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

TYPE B

TYPE C

TYPE D

V

, V

= 3.0V

V

, V

= 1.74V

0.2

OL BAT

0.05

OL BAT

0

0.1

0.3

(V)

0.4

0.5

0.6

0

0.10

0.15

V (V)

OL

0.20

0.25

0.30

V

OL

Figure 17. Output Single Drive Strength Characteristics (V_BAT= 1.74 V)

Figure 19. Output Single Drive Strength Characteristics (V_BAT= 3.0 V)

Rev. A | Page 26 of 46

Data Sheet

ADuCM4050

V

(V)

V

(V)

OH

3.20

5

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.2

3.3

3.4

3.5

, V

3.6

2.5

2.0

V

= 3.6V

V

, V

= 3.6V

OH BAT

4

3

V

TYPE A

V

TYPE A

OH

TYPE B

TYPE C

TYPE D

TYPE B

TYPE C

TYPE D

1.5

2

1.0

1

0.5

0

–1

–2

–3

–4

–5

–0.5

–1.0

–1.5

–2.0

–2.5

V

TYPE A

TYPE B

TYPE C

TYPE D

V

TYPE A

TYPE B

TYPE C

TYPE D

OL

V

, V

= 3.6V

V

, V

= 3.6V

OL BAT

0

0.05

0.10

0.15

0.20

0.25

0

0.05

0.10

0.15

0.20

0.25

V

(V)

V

(V)

OL

Figure 20. Output Double Drive Strength Characteristics (V_BAT= 3.6 V)

Figure 21. Output Single Drive Strength Characteristics (V_BAT= 3.6 V)

Rev. A | Page 27 of 46

ADuCM4050

Data Sheet

THEORY OF OPERATION

Code Region

ARM CORTEX-M4F PROCESSOR

The ARM Cortex-M4F core is a 32-bit reduced instruction set

computer (RISC). The length of the data can be 8 bits, 16 bits,

or 32 bits. The length of the instruction word is 16 bits or

32 bits. The processor has the following features:

Accesses in the code region (0x0000_0000 to 0x0007_FFFF

except 0x0007_F000 to 0x0007_FFFF, which is meant for

protected key storage) are performed by the core and target the

memory and cache resources.

SRAM Region

•

ARM Cortex-M4F architecture

Thumb-2 instruction set architecture (ISA) technology

Three-stage pipeline with branch speculation

Low latency interrupt processing with tail chaining

Single-cycle multiply

Hardware divide instructions

Nested vectored interrupt controller (NVIC) (72 interrupts

and 8 priorities)

Six hardware breakpoints and one watchpoint (unlimited

software breakpoints using the Segger JLink debug probe)

Bit banding support

Trace support—instruction trace macrocell (ITM), trace

port interface unit (TPIU), and data watchpoint and trace

(DWT) triggers and counters

Memory protection unit (MPU)

Eight-region MPU with subregions and background region

Programmable clock generator unit

Accesses in the SRAM region (see Figure 22) are performed by

the ARM Cortex-M4F core. The SRAM region of the core can

act as a data region for an application.

•

Internal SRAM data region. This space can contain

read/write data. Internal SRAM can be partitioned between

code and data (the SRAM region in the ARM Cortex-M4F

space) in 32 kB blocks. Access to this region occurs at core

clock speed with no wait states. The SRAM data region also

supports read/write access by the ARM Cortex-M4F core

and read/write DMA access by system devices.

•

System memory mapped registers (MMRs). Various system

MMRs reside in this region.

System Region

•

Accesses in this region (0xE000_0000 to 0xFFFF_FFFF) are

performed by the ARM Cortex-M4F core and handled within

the ARM Cortex-M4F platform. This system region includes

the following components:

Configurable for ultralow power operation

Deep sleep modes, dynamic power management

Programmable clock generator unit

•

CoreSight™ read only memory (ROM). The ROM table

entries (see the ARM Cortex-M4F Technical Reference

Manual) show the debug components of the processor.

ARM advanced peripheral bus (APB) peripheral. This

space is defined by ARM and occupies the bottom 256 kB

of the system region (0xE000_0000 to 0xE004_0000). The

space supports read/write access by the ARM Cortex-M4F

core to the internal peripherals of the ARM core (NVIC,

system control space (SCS), and wake-up interrupt controller

(WIC)) and CoreSight ROM. It is not accessible by system

DMA.

Floating point unit (FPU)

Supports single-precision add, subtract, multiply, divide,

multiply and accumulate, and square root operations

Provides conversions between fixed point and floating

point data formats, and floating point constant instructions

•

ARM Cortex-M4F Subsystem

The ADuCM4050 MCU memory map (see the ADuCM4050

Ultra Low Power ARM Cortex-M4F MCU with Integrated

Power Management Hardware Reference) is based on the ARM

Cortex-M4F memory model. By retaining the standardized

memory mapping, it is easier to port applications across ARM

Cortex-M4F platforms. The ADuCM4050 application

development is based on memory blocks across code and

SRAM regions. Sufficient internal memory is available via

internal SRAM and internal flash.

•

Platform control register. This space has registers within

the ARM Cortex-M4F platform component that control

the ARM core, its memory, and the code cache. It is

accessible by the ARM Cortex-M4F core (but not

accessible by system DMA).

Rev. A | Page 28 of 46

Data Sheet

ADuCM4050

For more information about the MMRs, refer to the

ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU with

Integrated Power Management Hardware Reference.

MEMORY ARCHITECTURE

The internal memory of the ADuCM4050 MCU is shown in

Figure 22. It incorporates 512 kB of embedded flash memory for

program code and nonvolatile data storage, 96 kB of data SRAM,

and 32 kB of SRAM (configured as instruction space or data space).

Flash Memory

The ADuCM4050 MCU includes 512 kB of embedded flash

memory, which is accessed using a flash controller. The flash

controller is coupled with a cache controller. A prefetch

mechanism is implemented in the flash controller to optimize

code performance.

SRAM Region

This memory space contains the application instructions and

variables data, which must be accessed in real time. It supports

read/write access by the ARM Cortex-M4F core and read/write

DMA access by system peripherals. Byte, half-word and word

accesses are supported.

Flash writes are supported by a keyhole mechanism via APB

writes to MMRs. The flash controller provides support for

DMA-based keyhole writes.

SRAM is divided into 96 kB data SRAM and 32 kB instruction

SRAM. If instruction SRAM is not enabled, then the associated

32 kB can be mapped as data SRAM, resulting in 128 kB of data

SRAM.

The device supports the following with consideration to flash

integrity:

•

A fixed user key required for running protected commands,

including mass erase and page erase.

An optional and user definable user failure analysis key

(FAA key).

An optional and user definable write protection for user-

accessible memory.

When the cache controller is enabled, 4 kB of the instruction

SRAM is reserved as cache memory. Optional parity bit error

detection is available on all SRAM memories. Multiple parity

bits are associated with each 32-bit word.

In hibernate mode, up to 124 kB of SRAM can be retained in

the following ways:

8-bit ECC.

•

124 kB of data SRAM

96 kB of data SRAM and 28 kB of instruction SRAM

Cache Controller

The ADuCM4050 MCU has an optional 4 kB instruction cache.

In certain applications, enabling the cache and executing the code

can result in lower power consumption rather than operating

directly from flash. When enabling the cache controller, 4 kB

of instruction SRAM is reserved as cache memory. In hibernate

mode, the cache memory is not retained.

MMRs (Peripheral Control and Status)

For the address space containing MMRs, refer to Figure 22.

These registers provide control and status for on-chip

peripherals of the ADuCM4050 MCU.

RESERVED

0x4000_70C4

RESERVED

0x4000_0C3C

ADC0

0x4004_C814

RGB TIMER

RESERVED

0x4000_7000

0x4000_5C0F

0x4000_5C00

0x4000_544C

RESERVED

BEEPER 0

RESERVED

0x4000_0C00

0x4000_082C

POWER MANAGEMENT, EXTERNAL

INTERRUPTS, CLOCKING,

MISCELLANEOUS REGISTERS

GENERAL-PURPOSE TIMER 2

RESERVED

0x4000_0800

0x4000_042C

UART 1

0x4004_C000

0x4004_40C8

RESERVED

CRYPTOGRAPHIC ACCELERATOR

RESERVED

0x4000_5400

0x4000_504C

RESERVED

GENERAL-PURPOSE TIMER 1

RESERVED

0x4000_0400

0x4000_002C

UART 0

RESERVED

0x4004_4000

0x4004_0418

0x4000_5000

0x4000_4438

GENERAL-PURPOSE TIMER 0

RESERVED

RANDOM NUMBER GENERATOR

RESERVED

0x4000_0000

0x2005_4000

SPI 1 MASTER/SLAVE

RESERVED

0x4004_0400

0x4004_0018

0x4000_4400

0x4000_4038

SYSTEM SRAM BANK 6 (16kB)

PROGRAMMABLE CRC ENGINE

RESERVED

0x2005_0000

0x2004_8000

0x2004_4000

SPI 0 MASTER/SLAVE

RESERVED

0x4004_0000

0x4003_806C

SYSTEM SRAM BANK 5 (32kB)

SYSTEM SRAM BANK 4 (16kB)

0x4000_4000

0x4000_305C

SPORT 0

2

I C 0 MASTER/SLAVE

0x4003_8000

0x4002_4038

RESERVED

0x4000_3000

0x4000_2C1C

SYSTEM SRAM BANK 3 (16kB)

RESERVED

WATCHDOG TIMER

RESERVED

0x2004_0000

0x2000_4000

SPIH 0 MASTER/SLAVE

RESERVED

0x4002_4000

0x4002_00F8

0x4000_2C00

0x4000_2040

SYSTEM SRAM BANK 0 (16kB)

RESERVED

GPIO

0x2000_0000

0x1000_8000

SYSTEM ID AND DEBUG ENABLE

RESERVED

0x4002_0000

0x4001_8064

RESERVED

0x4000_2000

0x4000_14E8

INSTRUCTION SRAM BANK 1,

INSTRUCTION SRAM BANK 2,

INSTRUCTION SRAM BANK 7

(32kB)

FLASH CONTROLLER

REAL TIME CLOCK 1 (RTC1)

RESERVED

0x4001_8000

0x4001_0FE4

0x4001_0000

0x4000_1400

0x4000_10E8

RESERVED

DMA 0

0x1000_0000

0x0008 0000

0x0000_0000

RESERVED

REAL TIME CLOCK 0 (RTC0)

0x4000_1000

512kB FLASH MEMORY

Figure 22. ADuCM4050 Memory Map—SRAM Mode 0

Rev. A | Page 29 of 46

ADuCM4050

Data Sheet

Flexi Mode

SYSTEM INTEGRATION FEATURES

The ADuCM4050 MCU provides several features for

development of ultra low power, secure, and robust systems.

In flexi mode, the ARM Cortex-M4F core is clock gated, but the

remainder of the system is active. No instructions can be executed

in this mode, but DMA transfers can continue between peripherals

as well as memory to memory. See Table 4 for details on flexi mode

current consumption.

Reset

There are four kinds of resets: external, power-on, watchdog

timeout, and software system reset. The software system reset is

provided as part of the ARM Cortex-M4F core. The

Hibernate Mode

pin is toggled to perform a hardware reset.

SYS_HWRST

Hibernate mode provides state retention, configurable SRAM

and port pin retention, a limited number of wake-up interrupts

(SYS_WAKEx, UART0_RX, and optionally, RTC0 and RTC1

(FLEX_RTC™)).

Booting

The ADuCM4050 MCU supports two boot modes: booting from

internal flash and upgrading software through UART download

(see Table 24). If SYS_BMODE0 (Pin P1_01) is pulled low

during power-up or a hard reset, the MCU enters into serial

download mode. In this mode, an on-chip loader routine

initiates in the kernel, which configures the UART port and

communicates with the host to manage the firmware upgrade

via a specific serial download protocol.

Shutdown Mode

Shutdown mode is the deepest sleep mode, in which all the digital

and analog circuits are powered down with an option to wake

from four possible wake-up sources. The RTC0 can be (optionally)

enabled in this mode, and the device can be periodically woken

up by the RTC0 interrupt.

Shutdown Mode—Fast Wake-Up

Table 24. Boot Modes

Boot Mode Description

This mode has a faster wake-up time than shutdown mode at

the expense of higher power consumption. See Table 25 for

wake-up time specifications.

0

1

UART download mode.

Flash boot. Boot from integrated flash memory.

Power Management and Control

Power Management and Modes

The following features are available for power management and

control:

The ADuCM4050 MCU has an integrated power management

system that optimizes performance and extends the battery life

of the device. The power management system consists of the

following:

•

Voltage range of 1.74 V to 3.6 V using a single supply (such

as the CR2032 coin cell battery).

•

GPIOs are driven directly from the battery. The pin state is

retained in hibernate and shutdown modes. The GPIO

configuration is only retained in hibernate mode.

Wake-up from external interrupts (via GPIOs),

UART0_RX interrupt, and RTCs for hibernate mode.

Wake-up from external interrupts (via GPIOs) and RTC0

for shutdown mode.

•

Integrated 1.2 V low dropout regulator (LDO) and optional

capacitive buck regulator

Integrated power switches for low standby current in

hibernate and shutdown modes

•

Additional power management features include the following:

•

Customized clock gating for active modes

Power gating to reduce leakage in hibernate and shutdown

modes

Optional high power buck converter for 1.2 V full on support

(MCU use only). See Figure 23 for suggested external circuitry.

•

Flexible sleep modes

VBAT

VDCDC_CAP1P

VDCDC_CAP1N

VDCDC_OUT

Shutdown mode with no retention

Optional high efficiency buck converter to reduce power

Integrated low power oscillators

0.1µF

BUCK

ENABLED

1µF

VDCDC_CAP2P

VDCDC_CAP2N

The PMU provides control of the ADuCM4050 MCU power

modes and allows the ARM Cortex-M4F to control the clocks

and power gating to reduce the power consumption. Several

power modes are available, offering options to balance power

consumption and functionality. The power modes available in the

ADuCM4050 are described in the following sections.

VLDO_OUT

0.47µF

LDO

Active Mode

NOTES

1. FOR DESIGNS IN WHICH THE OPTIONAL BUCK IS NOT USED,

THE FOLLOWING PINS MUST BE LEFT UNCONNECTED: VDCDC_CAP1P,

VDCDC_CAP1N, VDCDC_OUT, VDCDC_CAP2P, AND VDCDC_CAP2N.

In active mode, all peripherals can be enabled. Active power is

managed by optimized clock management. See Table 3 for

details on active mode current consumption.

Figure 23. Buck Enable Design

Rev. A | Page 30 of 46

Data Sheet

ADuCM4050

Table 25. Power Modes Wake-Up Times

Mode

VTOR¹

Flash

SRAM

Flash

Root Clock

HFOSC

HFXTAL

PLL_HFOSC

PLL_HFXTAL

PLL_HFOSC

PLL_HFXTAL

HFOSC

HCLK/PCLK

26 MHz

52 MHz

26 MHz

Wake-Up Time

Flexi

Hibernate

1.605 µs

10.356 µs

4.984 µs

686.452 µs

14.487 µs

742.668 µs

15.730 µs

726.101 µs

68.144 ms

1.220 ms

Shutdown

Shutdown (Fast Wake-Up)

HFOSC

¹VTOR means vector table offset register.

True Random Number Generator (TRNG)

Security Features

The TRNG is used during operations where nondeterministic

values are required. This can include generating challenges for

secure communication or keys used for an encrypted commu-

nication channel. The generator can run multiple times to

generate a sufficient number of bits for the strength of the

intended operation. The true random number generator can

seed a deterministic random bit generator.

The ADuCM4050 MCU provides a combination of hardware

and software protection mechanisms that lock out access to the

device in secure mode, but grant access in open mode. These

mechanisms include the password protected slave boot mode

(UART), as well as password protected serial wire debug (SWD)

interfaces. Mechanisms are provided to protect the device

contents (flash, SRAM, CPU registers, and peripheral registers)

from being read through an external interface by an

Reliability and Robustness Features

unauthorized user. This is referred to as read protection.

The ADuCM4050 MCU provides several features that can

enhance or help achieve certain levels of system safety and

reliability. Whereas the level of safety is mainly dominated by

system considerations, the following features are provided to

enhance robustness.

It is possible to protect the device from being reprogrammed in

circuit with unauthorized code. This is referred to as in circuit

write protection.

The device can be configured with no protection, read protection,

or read and in circuit write protection. It is not necessary to

provide in circuit write protection without read protection.

ECC Enabled Flash Memory

The entire flash array is protected to either correct single-bit

errors or detect two bit errors per 64-bit flash data.

This product includes security features that can be used to protect

embedded nonvolatile memory contents and prevent execution

of unauthorized code. When security is enabled on this device

(either by the ordering party or the subsequent receiving parties),

the ability of Analog Devices to conduct failure analysis on

returned devices is limited. Contact Analog Devices for details

on the failure analysis limitations for this device.

Multiparity Bit Protected SRAM

Each word of the SRAM and cache memory is protected by

multiple parity bits to allow detection of random soft errors.

Software Watchdog

The on-chip watchdog timer can provide software-based

supervision of the ADuCM4050 core.

Cryptographic Accelerator

The cryptographic accelerator is a 32-bit APB DMA capable

peripheral. There are two 128-bit buffers provided for data

input/output operations. These buffers read in or read out

128 bits in four data accesses. Big endian and little endian data

formats are supported, as are the following modes:

•

ECB mode—AES mode

CTR mode

CBC mode

Message authentication code (MAC) mode

CCM/CCM* mode

SHA-256 modes

Protected key storage with key wrap and unwrap—HMAC

signature generation

Rev. A | Page 31 of 46

ADuCM4050

Data Sheet

CRC Accelerator

ADC Subsystem

The CRC accelerator computes the CRC for a block of memory

locations, that can be in the SRAM, flash, or any combination of

MMRs. The CRC accelerator generates a checksum that can be

compared with an expected signature. The main features of the

CRC include the following:

The ADuCM4050 MCU integrates a 12-bit SAR ADC with up

to eight external channels. Conversions can be performed in

single or autocycle mode. In single mode, the ADC can be

configured to convert on a particular channel by selecting one

of the ADC channels. Autocycle mode is provided to convert

over multiple channels with reduced MCU overhead of

sampling and reading individual channel registers. The ADC

can also be used for temperature sensing and measuring battery

voltage using the ADC channels.

•

Generates a CRC signature for a block of data.

Supports programmable polynomial length of up to 32 bits.

Operates on 32 bits of data at a time, and generates CRC

for any data length.

Temperature sensing and battery monitoring cannot be

included in autocycle mode.

•

Supports MSB first and LSB first CRC implementations.

Various data mirroring capabilities.

Initial seed to be programmed by user.

DMA controller (memory to memory transfer) used for

data transfer to offload the MCU.

The digital comparator on the device allows an interrupt to be

triggered if ADC input is above or below a programmable

threshold. Use the following GPIO multiplexed channels with

the digital comparator (see the GPIO Multiplexing section):

ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and ADC0_VIN3.

Programmable GPIOs

The ADuCM4050 MCU has 44 and 51 GPIO pins in the LFCSP

and WLCSP packages, respectively, with multiple, configurable

functions defined by user code. They can be configured as

input/output pins and have programmable pull-up resistors. All

GPIO pins are functional over the full supply range. In deep

sleep modes, GPIO pins retain their state. On reset, they tristate.

Use the ADC in DMA mode to reduce MCU overhead by

moving ADC results directly into SRAM with a single interrupt

asserted when the required number of ADC conversions

completely logs to memory. The main features of the ADC

subsystem include the following:

•

12-bit resolution.

Programmable ADC update rate from 10 kSPS to

1.8 MSPS.

Timers

The ADuCM4050 MCU contains three general-purpose timers,

a watchdog timer, and an RGB timer. All timers support event

capture feature, where they can take 40 different interrupts.

•

Integrated input mux that supports up to eight channels.

Temperature sensing support.

Battery monitoring support.

Software selectable on-chip reference voltage generation—

1.25 V or 2.50 V.

General-Purpose Timers

The ADuCM4050 MCU has three identical general-purpose

timers, each with a 16-bit up or down counter. The up or down

counter can be clocked from one of four user-selectable clock

sources. Any selected clock source can be scaled down using a

prescaler of 1, 16, 64, or 256.

•

Software-selectable internal or external reference.

Autocycle mode provides the ability to automatically select

a sequence of input channels for conversion.

Multiple conversions over a single channel or multiple

channels can be performed without core interruption.

Averaging function—converted data on a single channel or

multiple channels can be averaged up to 256 samples.

Alert function that contains an internal digital comparator

for the ADC0_VIN0, ADC0_VIN1, ADC0_VIN2, and

ADC0_VIN3 channels. An interrupt is generated if the

digital comparator detects an ADC result above or below a

user defined threshold. In addition, up to eight cycles of

hysteresis are built in.

•

Watchdog Timer (WDT)

The watchdog timer (WDT) is a 16-bit count down timer with a

programmable prescaler. The prescaler source is selectable and

can be scaled by a factor of 1, 16, or 256. The WDT is clocked by

the 32 kHz on-chip oscillator (LFOSC) and helps recover from

an illegal software state. The WDT requires periodic servicing

to prevent it from forcing a reset or interrupt to the MCU.

RGB Timer

The ADuCM4050 MCU has an RGB timer that supports a

common anode RGB LED. It has a timer counter and three

compare registers. It can generate three distinct pulse width

modulation (PWM) waveforms on three GPIO pins

simultaneously so different colors can be realized using a

common anode RGB LED.

•

Dedicated DMA channel support.

Each channel, including temperature sensor and battery

monitoring, has a data register for conversion result.

When the RGB timer is in operation, the other three timers are

available for user software.

Rev. A | Page 32 of 46

Data Sheet

ADuCM4050

Clocking

Real-Time Clock (RTC)

The ADuCM4050 MCU has the following clocking options:

The ADuCM4050 MCU has two RTC blocks: RTC0 and RTC1,

also called flexible real-time clock (FLEX_RTC™). The RTC

blocks share a low power crystal oscillation circuit that operates

in conjunction with a 32,768 Hz external crystal.

•

High frequency clocks

•

Internal high frequency oscillator (HFOSC) at

26 MHz

The RTC has an alarm that interrupts the core when the

programmed alarm value matches the RTC count. The software

enables and configures the RTC.

•

High frequency external crystal oscillator (HFXTAL)

at 26 MHz or 16 MHz

GPIO clock in (SYS_CLKIN)

Phase-locked loop (PLL)

•

The RTC also has a digital trim capability to allow a positive or

negative adjustment to the RTC count at fixed intervals.

•

Low frequency clocks at 32 kHz

•

Internal low frequency oscillator (LFOSC)

Low frequency external crystal oscillator (LFXTAL)

The FLEX_RTC supports three SensorStrobe outputs:

RTC1_SS1, RTC1_SS2, and RTC1_SS3 (see the ADuCM4050

Ultra Low Power ARM Cortex-M4F MCU with Integrated

Power Management Hardware Reference). Using this

mechanism, the ADuCM4050 MCU can be used as a

programmable clock generator in all power modes except

shutdown mode. In this way, the external sensors can have their

timing domains mastered by the ADuCM4050 MCU, as the

SensorStrobe output is a programmable divider from the

FLEX_RTC, which can operate at 0.5 Hz to 16.384 kHz. The

sensors and MCU are in sync, which removes the need for

additional resampling of data to time align it.

The clock options have software configurability with the

following exceptions: the HFOSC cannot be disabled when

using an internal buck regulator, and the LFOSC cannot be

disabled even if using LFXTAL.

Clock sources with a frequency greater than 26 MHz can be

achieved by using a PLL. The maximum frequency sourced

from the PLL is 52 MHz.

When core frequency is greater than 26 MHz, program the flash

wait states to 1.

In the absence of the SensorStrobe mechanism, the external

sensor uses an RC oscillator (approximately 30% typical

variation). The MCU must sample the data and resample it on

the time domain of the MCU before using it.

As PLL is disabled and relock is transparent to user software,

hibernate mode can enter and exit seamlessly when the system

frequency is sourced from PLL.

Clock Fail Detection

Alternatively, the MCU remains in a higher power state and

drives each data conversion on the sensor side.

The LFOSC clock continuously monitors the LFXTAL in

hibernate, active, and flexi power modes. If the LFXTAL stops

running, there is an option to detect and generate an interrupt

and/or automatically switch to the LFOSC without software

intervention. The HFOSC clock monitors the HFXTAL clock,

GPIO clock, and the PLL clock. If using any of these clocks as

the system clock and it fails to toggle, the clock can be detected

through an interrupt. There is an option to automatically switch

to the HFOSC.

The SensorStrobe mechanism allows the ADuCM4050 MCU to

be in a lower power state for a long duration and avoids

unnecessary data processing, extending the battery life of the

end product. The key differences between RTC0 and RTC1 are

shown in Table 26.

Rev. A | Page 33 of 46

ADuCM4050

Data Sheet

Table 26. RTC Features

Features

RTC0

RTC1 (FLEX_RTC)

Resolution of

Time Base

(Prescaling)

Counts time at 1 Hz in units of seconds. Operationally, Can prescale the clock by any power of two from 0 to 15. It can

RTC0 always prescales to 1 Hz (for example, divide

by 32,768) and always counts real time in units of

seconds.

count time in units of any of these 16 possible prescale settings.

For example, the clock can be prescaled by 1, 2, 4, 8, …, 16,384, or

32,768.

Source Clock

LFXTAL.

Depending on the low frequency multiplexer configuration, the

RTC is clocked by the LFXTAL or the LFOSC.

Wake-Up Timer

Wake-up time is specified in units of seconds.

Supports alarm times down to a resolution of 30.52 µs, that is,

where the time is specified down to a specific 32 kHz clock cycle.

Number of

Alarms

One alarm only. Uses an absolute, nonrepeating

alarm time, specified in units of 1 sec.

Two alarms. One absolute alarm time and one periodic alarm,

repeating every 60 prescaled time units.

SensorStrobe

Mechanism

Not available.

Four independent channels with fine control on duty cycle and

frequency (0.5 Hz to 16.384 kHz).

SensorStrobe is an alarm function in the RTC that can send an

output pulse via GPIOs to an external device to instruct that

device to take a measurement or perform some action at a

specific time. SensorStrobe events are scheduled at a specific

target time relative to the real-time count of the RTC.

SensorStrobe can be enabled in active, flexi, and hibernate

modes.

Input Capture

Not available.

Input capture takes a snapshot of the RTC real-time count when

an external device signals an event via a transition on one of the

GPIO inputs to the ADuCM4050 MCU. Typically, an input capture

event is triggered by an autonomous measurement or action on

such a device, which then signals to the ADuCM4050 MCU that

the RTC must take a snapshot of time corresponding to the event.

Taking this snapshot can wake up the ADuCM4050 MCU and

cause an interrupt to the CPU. The CPU can subsequently obtain

information from the RTC on the exact 32 kHz cycle on which the

input capture event occurred.

Input Sampling

Not available.

Each SensorStrobe channel has up to three separate GPIO inputs

from an external device, which can be sampled based on the

output pulse sent to the external device. Each channel can be

configured to interrupt the ADuCM4050 MCU when any activity

happens on these GPIO inputs from the external device. These

inputs can broadcast sensor states such as first in, first out (FIFO)

buffer full, switch open, and threshold crossed. This feature allows

the ADuCM4050 MCU to remain in a low power state and wake

up to process the data only when a specific programmed

sequence from an external device is detected.

Rev. A | Page 34 of 46

Data Sheet

ADuCM4050

ADCs and DACs require two control signals for their

Beeper Driver

conversion processes. To interface with such devices,

SPT0_ACNV and SPT0_BCNV signals are provided. To use

these signals, enable the timer enable mode. In this mode, a

PWM timer inside the SPORT module generates the

programmable SPT0_ACNV and SPT0_BCNV signals.

The ADuCM4050 MCU has an integrated audio driver for a

beeper. The beeper driver module in the ADuCM4050 MCU

generates a differential square wave of programmable frequency.

It drives an external piezoelectric sound component with two

terminals that connect to the differential square wave output.

Serial ports operate in two modes: the standard digital signal

processor (DSP) serial mode and timer enable mode.

The beeper driver consists of a module that can deliver

frequencies ranging from 8 kHz to approximately 0.25 kHz; the

minimum frequency is determined by the maximum value of a

divide register that can be programmed to 127. This results in a

beeper frequency of,

SPI Ports

The ADuCM4050 MCU provides three SPIs. The SPI is an

industry-standard, full duplex, synchronous serial interface that

allows eight bits of data to be synchronously transmitted and

simultaneously received. Each SPI incorporates two DMA

channels that interface with the DMA controller. One DMA

channel transmits and the other receives. The SPI on the MCU

eases interfacing to external serial flash devices.

32.768 kHz/127 = 0.25802 kHz

The beeper driver allows programmable tone durations in 4 ms

increments. Pulse (single-tone) and sequence (multitone)

modes provide versatile playback options.

In sequence mode, the beeper can be programmed to play any

number of tone pairs from 1 to 254 (2 to 508 tones) or be

programmed to play forever (until stopped by the user).

Interrupts are available to indicate the start or end of any beep,

the end of a sequence, or when the sequence is nearing

completion.

The SPI features include the following:

•

Serial clock phase mode and serial clock polarity mode

Loopback mode

Continuous transfer mode

Wire-OR’d output mode

Read command mode for half-duplex operation (transmit

followed by receive)

Debug Capability

The ADuCM4050 MCU supports a 2-wire serial wire debug

(SWD) interface and trace feature via a single-wire viewer port.

The ADuCM4050 MCU also has a full flash patch and

breakpoint (FPB) unit with support for up to six hardware

breakpoints.

•

Flow control support

Multiple chip select (CS) line support

CS software override support

Support for 3-pin SPI

ON-CHIP PERIPHERAL FEATURES

UART Ports

The ADuCM4050 MCU contains a rich set of peripherals

connected to the core via several concurrent high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see Figure 1).

The ADuCM4050 MCU provides two full duplex UART ports

that are fully compatible with PC standard UARTs. The UART

port provides a simplified UART interface to other peripherals

or hosts, supporting full duplex, DMA supported, asynchronous

transfers of serial data. The UART port includes support for

five to eight data bits, and none, even, or odd parity. A frame

is terminated by one, one and a half, or two stop bits.

The ADuCM4050 MCU contains high speed serial ports, an

interrupt controller for flexible management of interrupts

from the on-chip peripherals or external sources, and power

management control functions to tailor the performance and

power characteristics of the MCU and system to many

application scenarios.

I²C

The ADuCM4050 MCU provides an I²C bus peripheral that has

two pins for data transfer. SCL (Pin P0_04) is a serial clock pin

and SDA (Pin P0_05) is a serial data pin. The pins are

Serial Ports (SPORT)

configured in a wire-AND’e d format that allows arbitration in a

multimaster system. A master device can be configured to

generate the serial clock. The frequency is programmed by the

user in the serial clock divisor register. The master channel can

operate in fast mode (400 kHz) or standard mode (100 kHz).

The ADuCM4050 MCU provides two single-direction half

SPORTs or one bidirectional full SPORT. The synchronous

serial ports provide an inexpensive interface to a wide variety of

digital and mixed-signal peripheral devices such as Analog

Devices audio codecs, ADCs, and DACs. The serial ports

contain two data lines, a clock, and a frame sync. The data lines

can be programmed to either transmit or receive, and each data

line has a dedicated DMA channel.

Serial port data can be automatically transferred to and from

on-chip memory or external memory via dedicated DMA

channels. The frame sync and clock can be shared. Some of the

Rev. A | Page 35 of 46

ADuCM4050

Data Sheet

DEVELOPMENT SUPPORT

MCU TEST CONDITIONS

Development support for the ADuCM4050 MCU includes

documentation, evaluation hardware, and development

software tools.

The ac signal specifications (timing parameters) appearing in

this data sheet include output disable time, output enable time,

and others. Timing is measured on signals when they cross the

voltage threshold (V_MEAS) level as described in Figure 24. All

delays (in nanoseconds or microseconds) are measured between

the point that the first signal reaches V_MEASand the point that

the second signal reaches V_MEAS. The value of V_MEASis set to

Documentation

The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU

with Integrated Power Management Hardware Reference details

the functionality of each block on the ADuCM4050 MCU. It

includes power management, clocking, memories, and peripherals.

V

_BAT/2. The tester pin electronics is shown in Figure 25.

The ADuCM4050 Ultra Low Power ARM Cortex-M4F MCU

with Integrated Power Management Hardware Reference can be

ordered from any Analog Devices sales office or accessed

electronically on the Analog Devices website at www.analog.com.

INPUT

V

MEAS

OR

MEAS

OUTPUT

Figure 24. Voltage Reference Levels for AC Measurements (Except Output

Enable/Disable)

50Ω

Hardware

V

LOAD

T1

DUT

OUTPUT

The EV-COG-AD4050LZ is available to prototype sensor

configuration with the ADuCM4050 MCU.

70Ω

45Ω

ZO = 50Ω (IMPEDANCE)

Software

50Ω

TD = 4.04ns ± 1.18ns

0.5pF

4pF

2pF

The EV-COG-AD4050LZ includes a complete development and

debug environment for the ADuCM4050 MCU. The device

family pack for the ADuCM4050 MCU is provided for the IAR

Embedded Workbench for ARM, Keil™, and CrossCore®

embedded studio (CCES) environments.

400Ω

NOTES

1. THE WORST-CASE TRANSMISSION LINE DELAY (TD) IS SHOWN AND

CAN BE USED FOR THE OUTPUT TIMINGANALYSIS TO REFLECT THE

TRANSMISSION LINE EFFECTAND MUST BE CONSIDERED.

TRANSMISSION LINE IS FOR LOAD ONLY AND DOES NOT AFFECT

THE DATA SHEET TIMING SPECIFICATIONS.

The device family pack also includes operating system (OS)

aware drivers and example code for peripherals on the device.

2. ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING

FORA GIVEN SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM

CAN INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR

ANY TIMING DIFFERENCES.

REFERENCE DESIGNS

The Circuits from the Lab® web page provides the following for

the ADuCM4050 reference design:

Figure 25. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

•

Graphical circuit block diagram presentation of signal

chains for a variety of circuit types and applications

Drill down links for components in each chain to selection

guides and application information

DRIVER TYPES

Table 27 shows the driver types.

Table 27. Driver Types

Driver Type^{1, 2, 3}Associated Pins

Reference designs applying best practice design techniques

SECURITY FEATURES DISCLAIMER

Type A

P0_00 to P0_03, P0_07, P0_10 to P0_13, P0_15,

To the knowledge of Analog Devices, the security features,

when used in accordance with the data sheet and hardware

reference manual specifications, provide a secure method of

implementing code and data safeguards. However, Analog

Devices does not guarantee that this technology provides

absolute security. Accordingly, analog devices hereby disclaims

any and all express and implied warranties that the security

features cannot be breached, compromised, or otherwise

circumvented and in no event is Analog Devices liable for any

loss, damage, destruction, or release of data, information,

physical property, or intellectual property.

P1_00 to P1_10, P1_15, P2_00, P2_01, P2_04 to

P2_14, P3_00 to P3_03, and SYS_HWRST

P0_08, P0_09, P0_14, P1_11 to P1_14, and P2_02

P0_04 and P0_05

P0_06

Type B

Type C

Type D

¹In single drive mode, the maximum source/sink capacity is 2 mA.

²In double drive mode, the maximum source/sink capacity is 4 mA.

³At maximum drive capacity, only 16 GPIOs are allowed to switch at any given

point in time.

Rev. A | Page 36 of 46

Data Sheet

ADuCM4050

Table 28. EEMBC ULPMark™-CP Profile Configuration

EEMBC ULPMARK™-CP SCORE

Profile Configuration

Value

Using the following software configuration and the profile

configuration shown in Table 28, the EEMBC ULPMark-CP

score is 189.

Wake-Up Timer Module

RTC1

Wake-Up Timer Clock Source

Wake-Up Timer Frequency

Wake-Up Timer Accuracy

Active Power Mode Name

Active Mode Clock Configuration

Active Mode Voltage Integrity

Inactive Power Mode Name

Inactive Clock Configuration

Inactive Mode Voltage Integrity

External crystal

32768 Hz

20 ppm

Active mode

52 MHz (CPU), 32 kHz (RTC)

1.74 V

Hibernate

Off (CPU), 32 kHz (RTC)

1.74 V

•

Compiler name and version: IAR EWARM 8.20.1

Compiler flags:

--no_size_constraints --cpu=Cortex-M4 -D

__ADUCM4050__ --no_code_motion -Ohs -e --

fpu=VFPv4_sp --endian=little

•

ULPBench Profile and Version: Core Profile v1.1

EnergyMonitor Software Version: V2.0

Rev. A | Page 37 of 46

ADuCM4050

Data Sheet

GPIO MULTIPLEXING

The following tables capture signal multiplexing options for the GPIO pins.

Table 29. Signal Multiplexing for Port 0¹

Multiplexed Function 0

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

SWD0_CLK

SWD0_DATA

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13/SYS_WAKE2

GPIO14

GPIO15/SYS_WAKE0

Multiplexed Function 1

SPI0_CLK

SPI0_MOSI

SPI0_MISO

SPI0_CS0

I2C0_SCL

I2C0_SDA

GPIO06

GPIO07

BPR0_TONE_N

BPR0_TONE_P

UART0_TX

UART0_RX

SPT0_AD0

Not applicable

TMR0_OUT

Not applicable

Multiplexed Function 2

SPT0_BCLK

SPT0_BFS

SPT0_BD0

SPT0_BCNV

Not applicable

SPI2_CS1

Not applicable

SPI1_RDY

Multiplexed Function 3

Not applicable

SPI2_RDY

Not applicable

UART0_SOUT_EN

Not applicable

P0_00

P0_01

P0_02

P0_03

P0_04

P0_05

P0_06

P0_07

P0_08

P0_09

P0_10

P0_11

P0_12

P0_13

P0_14

P0_15

Not applicable

¹Available in WLCSP and LFCSP.

Table 30. Signal Multiplexing for Port 1¹

Multiplexed Function 0

GPIO16/SYS_WAKE1

SYS_BMODE0

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23

GPIO24

GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

Multiplexed Function 1

Multiplexed Function 2

Multiplexed Function 3

Not applicable

RGB_TMR0_1

RGB_TMR0_2

RGB_TMR0_3

SWV

P1_00

P1_01

P1_02

P1_03

P1_04

P1_05

P1_06

P1_07

P1_08

P1_09

P1_10

P1_11

P1_12

P1_13

P1_14

P1_15

Not applicable

GPIO17

SPI2_CLK

SPI2_MOSI

SPI2_MISO

SPI2_CS0

Not applicable

SYS_CLKIN

TMR1_OUT

RTC1_SS2

Not applicable

SPI0_RDY

UART1_TX

SPI1_CLK

SPI1_MOSI

SPI1_MISO

SPI1_CS0

SPI0_CS1

SPI1_CS3

Not applicable

TMR2_OUT

Not applicable

SPT0_ACLK

Not applicable

¹Available in WLCSP and LFCSP.

Rev. A | Page 38 of 46

Data Sheet

ADuCM4050

Table 31. Signal Multiplexing for Port 2

Availability

WLCSP LFCSP Multiplexed Function 0 Multiplexed Function 1 Multiplexed Function 2 Multiplexed Function 3

P2_00 Yes

P2_01 Yes

P2_02 Yes

P2_03 Yes

P2_04 Yes

P2_05 Yes

P2_06 Yes

P2_07 Yes

P2_08 Yes

P2_09 Yes

P2_10 No

P2_11 Yes

P2_12 Yes

P2_13 Yes

P2_14 Yes

P2_15 Yes

Yes

No

GPIO32

GPIO33/SYS_WAKE3

GPIO34

GPIO35

GPIO36

GPIO37

GPIO38

GPIO39

GPIO40

GPIO41

GPIO42

GPIO43

GPIO44

GPIO45

GPIO46

GPIO47

SPT0_AFS

UART1_RX

TMR2_OUT

SPI1_CS2

Not applicable

SPI2_CS3

SPI0_CS2

SPI0_CS3

SPI2_CS2

SYS_CLKOUT

SPI2_CS3

Not applicable

SPT0_ACNV

ADC0_VIN0

ADC0_VIN1

ADC0_VIN2

ADC0_VIN3

ADC0_VIN4

ADC0_VIN5

ADC0_VIN6

ADC0_VIN7

SPI1_CS1

Not applicable

RTC1_SS3

Not applicable

RTC1_SS1

Not applicable

SPI0_CS1

UART1_TX

UART1_RX

SPI0_CS3

No

SPI0_CS2

Not applicable

SPI1_CS3

SPI2_CS2

Table 32. Signal Multiplexing for Port 3¹

Multiplexed Function 0

GPIO48

GPIO49

GPIO50

GPIO51

Multiplexed Function 1

Multiplexed Function 2

SPT0_ACLK

SPT0_AFS

SPT0_AD0

SPT0_ACNV

Multiplexed Function 3

Not applicable

P3_00

P3_01

P3_02

P3_03

RGB_TMR0_1

RGB_TMR0_2

RGB_TMR0_3

Not applicable

¹Only available in WLCSP.

Rev. A | Page 39 of 46

ADuCM4050

Data Sheet

APPLICATIONS INFORMATION

This section contains circuit diagrams that show the recommended

external components for proper operation of the ADuCM4050

in example application scenarios.

VBAT

IO

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

SYS_LFXTAL_OUT

VDCDC_OUT

4

1µF

13

25

9

SYS_HWRST_N

ADuCM4050BCPZ

VLDO_OUT

12

0.1µF

0.47µF

6

VDCDC_CAP1N

VDCDC_CAP1P

VDCDC_CAP2N

SPI1_CS0/GPIO25/SWV

SPI1_MISO/RGB_TMR0_3/GPIO24

SPI1_CLK/RGB_TMR0_1/GPIO22

29

30

32

7

10

11 VDCDC_CAP2P

RTC1_SS1

SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33

IO

16 ADC0_VIN0/GPIO35

ADC0_VIN1/GPIO36

31

SPI1_MOSI/RGB_TMR0_2GPIO23

17

53

54

55

56

SPI2_CS0/GPIO21

SPI2_MISO/GPIO20

SPI2_MOSI/GPIO19

SPI2_CLK/GPIO18

18 ADC0_VIN2/GPIO37

19 ADC0_VIN3/GPIO38

20 ADC0_VIN4/SPI2_CS3/GPIO39

21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40

22 ADC0_VIN6/SPI0_CS3/GPIO41

23 ADC0_VIN7/SPI2_CS2/GPIO42

SPT0_AD0/UART0_SOUT_EN/GPIO12

SPT0_AFS/UART1_RX/GPIO32

SPT0_ACLK/UART1_TX/GPIO31

SPT0_ACNV/SPI1_CS2/GPIO34

35

36

37

45

39 BPR0_TONE_P/SPI2_CS1/GPIO09

BPR0_TONE_N/GPIO08

40

SYS_WAKE1/GPIO16

SYS_WAKE0/GPIO15

47

50

28 GPIO06/SWD0_CLK

GPIO07/SWD0_DATA

GPIO17/SYS_BMODE0

RTC1_SS2/GPIO28

TMR2_OUT/GPIO29

27

38

42

43

SYS_WAKE2/GPIO13 51

52

SYS_WAKE3/TRM2_OUT/GPIO33

TMR1_OUT/GPIO27

41

46

TMR0_OUT/SPI1_RDY/GPIO14

I2C0_SDA/GPIO05

I2C0_SCL/GPIO04

24

26

UART0_RX/GPIO11 57

UART0_TX/GPIO10 58

SPI0_RDY/GPIO30

44

59

60

SPI0_MOSI/SPT0_BFS/GPIO1

62

SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26

SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03

63

SPI0_CLK/SPT0_BCLK/GPIO0

61 SPI0_MISO/SPT0_BD0/GPIO2

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 26. Recommended External Components when Using the Internal Buck Converter

Rev. A | Page 40 of 46

Data Sheet

ADuCM4050

VBAT

HFCLK CRYSTAL

26.000MHz

IO

LFCLK CRYSTAL

32.7680kHz

LFXTAL_IN

8pF

LFXTAL_OUT

HFXTAL_IN

18pF

HFXTAL_OUT

18pF

8pF

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

SYS_LFXTAL_OUT

VDCDC_OUT

4

13

25

9

SYS_HWRST_N

ADuCM4050BCPZ

VLDO_OUT

12

0.47µF

6

VDCDC_CAP1N

VDCDC_CAP1P

VDCDC_CAP2N

SPI1_CS0/GPIO25/SWV

SPI1_MISO/RGB_TMR0_3/GPIO24

SPI1_CLK/RGB_TMR0_1/GPIO22

29

30

32

7

10

11 VDCDC_CAP2P

RTC1_SS1

SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33

IO

16 ADC0_VIN0/GPIO35

ADC0_VIN1/GPIO36

31

SPI1_MOSI/RGB_TMR0_2GPIO23

17

53

54

55

56

SPI2_CS0/GPIO21

SPI2_MISO/GPIO20

SPI2_MOSI/GPIO19

SPI2_CLK/GPIO18

18 ADC0_VIN2/GPIO37

19 ADC0_VIN3/GPIO38

20 ADC0_VIN4/SPI2_CS3/GPIO39

21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40

22 ADC0_VIN6/SPI0_CS3/GPIO41

23 ADC0_VIN7/SPI2_CS2/GPIO42

SPT0_AD0/UART0_SOUT_EN/GPIO12

SPT0_AFS/UART1_RX/GPIO32

SPT0_ACLK/UART1_TX/GPIO31

SPT0_ACNV/SPI1_CS2/GPIO34

35

36

37

45

39 BPR0_TONE_P/SPI2_CS1/GPIO09

BPR0_TONE_N/GPIO08

40

SYS_WAKE1/GPIO16

SYS_WAKE0/GPIO15

47

50

28 GPIO06/SWD0_CLK

GPIO07/SWD0_DATA

GPIO17/SYS_BMODE0

RTC1_SS2/GPIO28

TMR2_OUT/GPIO29

27

38

42

43

SYS_WAKE2/GPIO13 51

52

SYS_WAKE3/TRM2_OUT/GPIO33

TMR1_OUT/GPIO27

41

46

TMR0_OUT/SPI1_RDY/GPIO14

I2C0_SDA/GPIO05

I2C0_SCL/GPIO04

24

26

UART0_RX/GPIO11 57

UART0_TX/GPIO10 58

SPI0_RDY/GPIO30

44

59

60

SPI0_MOSI/SPT0_BFS/GPIO1

62

SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26

SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03

63

SPI0_CLK/SPT0_BCLK/GPIO0

61 SPI0_MISO/SPT0_BD0/GPIO2

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 27. Recommended External Components when Using LFXTAL and HFXTAL

Rev. A | Page 41 of 46

ADuCM4050

Data Sheet

VBAT

IO

0.1µF

14

1

8

34

VBAT_DIG1

49

VBAT_DIG2

VBAT_ADC

VBAT_ANA1

VBAT_ANA2

2

SYS_HFXTAL_IN

SYS_LFXTAL_IN

VREF_ADC

3

5

SYS_HFXTAL_OUT

SYS_LFXTAL_OUT

VDCDC_OUT

4

VREF_ADC

IO

13

25

9

SYS_HWRST_N

ADuCM4050BCPZ

VLDO_OUT

12

0.1µF

4.7µF

0.47µF

6

VDCDC_CAP1N

VDCDC_CAP1P

VDCDC_CAP2N

SPI1_CS0/GPIO25/SWV

SPI1_MISO/RGB_TMR0_3/GPIO24

SPI1_CLK/RGB_TMR0_1/GPIO22

29

30

32

7

10

11 VDCDC_CAP2P

RTC1_SS1

SPI1_CS1/SYS_CLKOUT/RTC1_SS1/GPIO43 33

IO

ANALOG_IN

33Ω

IO

16 ADC0_VIN0/GPIO35

31

SPI1_MOSI/RGB_TMR0_2GPIO23

0.0056µF

ADC0_VIN1/GPIO36

17

53

54

55

56

SPI2_CS0/GPIO21

SPI2_MISO/GPIO20

SPI2_MOSI/GPIO19

SPI2_CLK/GPIO18

18 ADC0_VIN2/GPIO37

19 ADC0_VIN3/GPIO38

20 ADC0_VIN4/SPI2_CS3/GPIO39

21 ADC0_VIN5/SPI0_CS2/RTC1_SS3/GPIO40

22 ADC0_VIN6/SPI0_CS3/GPIO41

23 ADC0_VIN7/SPI2_CS2/GPIO42

SPT0_AD0/UART0_SOUT_EN/GPIO12

SPT0_AFS/UART1_RX/GPIO32

SPT0_ACLK/UART1_TX/GPIO31

SPT0_ACNV/SPI1_CS2/GPIO34

35

36

37

45

39 BPR0_TONE_P/SPI2_CS1/GPIO09

BPR0_TONE_N/GPIO08

40

SYS_WAKE1/GPIO16

SYS_WAKE0/GPIO15

47

50

28 GPIO06/SWD0_CLK

GPIO07/SWD0_DATA

GPIO17/SYS_BMODE0

RTC1_SS2/GPIO28

TMR2_OUT/GPIO29

27

38

42

43

SYS_WAKE2/GPIO13 51

52

SYS_WAKE3/TRM2_OUT/GPIO33

TMR1_OUT/GPIO27

41

46

TMR0_OUT/SPI1_RDY/GPIO14

I2C0_SDA/GPIO05

I2C0_SCL/GPIO04

24

26

UART0_RX/GPIO11 57

UART0_TX/GPIO10 58

SPI0_RDY/GPIO30

44

59

60

SPI0_MOSI/SPT0_BFS/GPIO1

62

SPI0_CS1/SYS_CLKIN/SPI1_CS3/GPIO26

SPI0_CS0/SPT0_BCNV/SPI2_RDY/GPIO03

63

SPI0_CLK/SPT0_BCLK/GPIO0

61 SPI0_MISO/SPT0_BD0/GPIO2

GND_ANA

64

GND_DIG

48

GND_VREFADC

15

PAD

Figure 28. Recommended External Components on VREF_ADC Pin and ADC Input Channel (ADC0_VIN0 Used as Example) when Using the Internal ADC

Rev. A | Page 42 of 46

Data Sheet

ADuCM4050

SILICON ANOMALY

This anomaly list describes the known bugs, anomalies, and workarounds for the ADuCM4050. These anomalies represent the currently

known differences between revisions of the ADuCM4050 product and the functionality specified in the ADuCM4050 data sheet and the

hardware reference manual.

Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries

to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended

workarounds outlined here.

ADuCM4050 FUNCTIONALITY ISSUES

Silicon Revision Identifier

Silicon Status

No. of Reported Anomalies

0.1

Released

3 (21000011, 21000016, 21000017)

A silicon revision number with the form x.y is branded on all devices. The silicon revision can be electronically determined by reading Bits[3:0]

of the SYS_CHIPID register. SYS_CHIPID = 0x1 indicates Silicon Revision 0.1, and SYS_CHIPID = 0x0 indicates Silicon Revision 0.0.

FUNCTIONALITY ISSUES

Table 33. 21000011—I²C Master Mode Fails to Generate Clock when Clock Dividers are Too Small

When the I²C clock dividers are configured in master mode such that the sum of the low and high bit fields in the

Issue

I2C_DIV register is less than 16, the I²C fails to generate a clock.

Program the I²C clock dividers such that I2C_DIV.LOW + I2C_DIV.HIGH ≥ 16.

0.1

Workaround

Revision

Table 34. 21000016—Possible Receive Data Loss with I²C Automatic Clock Stretching

When the I²C Rx FIFO is full and new I²C data is received, a data overflow occurs. When automatic clock stretching is

enabled, the transaction is paused by holding the SCL (Pin P0_04) line low. This function works as expected when the

next read happens after the clock is stretched (that is, after the overflow is detected). However, if the read occurs after

the last bit of the I²C data is received but before the clock is stretched, the received data is not written to the Rx FIFO and

is lost.

Issue

When I²C automatic clock stretching is enabled, read the FIFO should only after the overflow flag is set in the status

register to ensure that that Rx FIFO is never read at the same time that the overflow is asserted.

0.1

Workaround

Revision

Table 35. 21000017—SPI Read Command Mode Does Not Work Properly when SPI_CNT is 1 and DMA is Enabled

When SPI master is enabled and uses the DMA mode with SPI_CNT = 1, the read command mode may not function

properly. Consider the following configurations: SPI_RD_CTL = 0x07; SPI_CNT = 1; the transmit and receive DMA

channels are configured for 1 half-word.

Issue

In this configuration, the read command sent in the first byte on the MOSI output is repeated in the second byte (in the

address slot). Therefore, the slave device responds on the MISO line with whatever content is at the address equivalent to the

read command value (for example, if the read command is 0xB, the response is the data read from Slave Address 0xB).

The following workarounds can be used. Utilize the overlap mode to align the transmit/receive SPI operations and

discard the junk bytes, as follows:

Workaround

1. Set SPI_RD_CTL.OVERLAP = 1 to enable overlap mode.

2. Set SPI_RD_CTL.TXBYTES = 1 to configure a single transmit byte (8-bit address register).

3. Set SPI_CNT.VALUE = 3 to configure the transfer count: one byte for the address register, one byte for the command,

and one dummy byte to obtain the read value.

4. On the receive side, discard the first two junk bytes received during the transfer of the address and command bytes

before processing the actual read value in the third byte.

Alternatively, do not use Tx DMA operation on the SPI transmit side, by taking the following steps:

1. Enable only SPI RX DMA requests.

2. Fill the SPI Tx FIFO by using core accesses to write the SPI_TX register.

3. Perform a dummy read of the SPI_RX register to kick off the SPI transfers.

0.1

Revision

Rev. A | Page 43 of 46

ADuCM4050

Data Sheet

SECTION 1. ADuCM4050 FUNCTIONALITY ISSUES

Reference No.

Description

Status

21000011

21000016

21000017

I²C master mode fails to generate clock when clock dividers are too small

Possible receive data loss with I²C automatic clock stretching

SPI read command mode does not work properly when SPI_CNT is 1 and DMA is enabled

Identified

This completes the Silicon Anomaly section.

Rev. A | Page 44 of 46

Data Sheet

ADuCM4050

OUTLINE DIMENSIONS

3.61

3.57

3.53

9

8

7

6

5

4

3

2

1

0.355

A

B

C

D

E

F

BALL A1

IDENTIFIER

3.20

3.16

3.12

2.45 REF

G

H

0.35

BALL PITCH

BOTTOM VIEW

TOP VIEW

(

BALL SIDE UP)

(BALL SIDE DOWN)

0.385

2.80 REF

0.320

0.290

0.260

0.530

0.470

0.410

SIDE VIEW

COPLANARITY

0.05

SEATING

PLANE

0.280

0.240

0.200

0.210

0.180

0.150

Figure 29. 72-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-72-3)

Dimensions shown in millimeters

DETAIL A

(JEDEC 95)

9.10

9.00 SQ

8.90

0.30

0.25

0.18

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

(SEE DETAIL A)

49

48

64

1

0.50

BSC

6.30

6.20 SQ

6.10

EXPOSED

PAD

33

32

16

17

0.45

0.40

0.35

TOP VIEW

END VIEW

BOTTOM VIEW

0.20 MIN

7.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.08

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WMMD

Figure 30. 64-Lead Lead Frame Chip Scale Package [LFCSP]

9 mm × 9 mm Body and 0.75 mm Package Height

(CP-64-17)

Dimensions shown in millimeters

Rev. A | Page 45 of 46

ADuCM4050

Data Sheet

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

CB-72-3

CP-64-17

ADUCM4050BCBZ-RL

ADUCM4050BCBZ-R7

ADUCM4050BCPZ

ADUCM4050BCPZ-RL

ADUCM4050BCPZ-R7

EV-COG-AD4050LZ

EV-COG-AD4050WZ

72-Ball Wafer Level Chip Scale Package [WLCSP], 13” Reel

72-Ball Wafer Level Chip Scale Package [WLCSP], 7” Reel

64-Lead Lead Frame Chip Scale Package [LFCSP]

64-Lead Lead Frame Chip Scale Package [LFCSP], 13” Reel

64-Lead Lead Frame Chip Scale Package [LFCSP], 7” Reel

ADuCM4050 LFCSP Development Board

CP-64-17

ADuCM4050 WLCSP Development Board

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D14745-0-4/19(A)

Rev. A | Page 46 of 46


型号：	ADUCM4050BCPZ
厂家：	ADI
描述：	Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management
文件：	总46页 (文件大小：743K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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