ADUCM410BBCZ-RL7_技术文档

Precision Analog Microcontroller, 16-Bit Analog

Input/Output with MDIO Interface, Arm Cortex-M33

Data Sheet

ADuCM410

Fully specified for −40°C to +105°C operation

Tools

FEATURES

Analog input/output

Low cost quick start development system

Full third-party support

Multichannel, 16-bit, 2 MSPS ADC

Up to 16 external channels

On-chip die temperature monitor

4 power monitor channels

4 PGA/TIA channels supporting voltage and current

measurements

Fully differential and single-ended modes

0 V to VREF analog input range

12-bit voltage output DACs

8× 0 V to 2.5 V, 1 kΩ load

4× 0 V to 2.5 V, 2.5 kΩ load

On-chip low drift voltage reference, 1.25 V or 2.5 V

Buffered 1.25 V or 2.5 V output

4 voltage comparators

APPLICATIONS

Optical networking 100 Gbps/200 Gbps/400 Gbps and

higher frequency modules

Industrial control, automation, and instrumentation systems

GENERAL DESCRIPTION

The ADuCM410 is a fully integrated, single package device that

includes high performance analog peripherals together with

digital peripherals (controlled by a 160 MHz Arm® Cortex™-

M33 processor) and integrated flash for code and data.

The analog-to-digital converter (ADC) on the ADuCM410

provides 16-bit, 2 MSPS data acquisition using up to 16 input

pins that can be programmed for single-ended or differential

operation with a programmable gain amplifier (PGA) or

transimpedance amplifier (TIA) for voltage and current

measurements. Additionally, the die temperature and supply

voltages can be measured.

Microcontroller

32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU

Serial wire port supports code download and debug

Clocking options

16 MHz on-chip oscillator

160 MHz PLL output with programmable divider

External clock source

The ADC input voltage is 0 V to VREF. A sequencer is provided

that allows a user to select a set of ADC channels to be measured in

sequence without software involvement during the sequence.

The sequence can optionally repeat automatically at a user

selectable rate.

Memory

2× 512 kB independent Flash/EE memories

10,000 cycles Flash/EE endurance

10-year Flash/EE retention

128 kB SRAM with ECC

Software triggered, in circuit reprogrammability via MDIO or I²C

On-chip peripherals

Up to 12 channels of 12-bit voltage digital-to-analog converters

(VDACs) are provided with output buffers supported.

2× UART, 3× SPI, 3× I²C serial input/output

Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs

MDIO slave up to 10 MHz

5× general-purpose timers

Wake-up timer (WUTs)

The ADuCM410 can be configured so that the digital and analog

outputs retain their output voltages through a watchdog or

software reset sequence. Therefore, a product can remain

functional even while the ADuCM410 is resetting itself.

The ADuCM410 has a low power ARM Cortex-M33 processor

and a 32-bit reduced instruction set computer (RISC) machine

that offers up to 240 MIPS peak performance with a floating-

point unit (FPU). Also integrated are 2× 512 kB Flash/EE

memory and 128 kB static random access memory (SRAM)—

both with single-error correction (SEC) and double error

detection (DED) error checking and correction (ECC). The

flash comprises two separate 512 kB blocks supporting

execution from one flash block and simultaneous writing

and/or erasing of the other flash block.

Watchdog timers (WDTs)

32-element PLA

16-bit PWM

10 external Interrupts

Power

Multiple supplies: 3.3 V for voltage DACs and ADCs, and

3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs

Flexible operating modes for low power applications

Packages and temperature range

5 mm × 5 mm, 81-ball CSP_BGA and 3.46 mm × 3.46 mm

64-ball WLCSP

Continued on Page 3

BGA package uses ULA molding compounds

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADuCM410

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Performance Characteristics ........................................... 17

Pin Configurations and Function Descriptions......................... 18

Theory of Operation ...................................................................... 29

RMS Noise Resolution of ADC .................................................... 30

Applications Information.............................................................. 31

Power Supplies............................................................................ 31

Power-Up Requirements ........................................................... 31

Recommended Circuit and Component Values .................... 32

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 35

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Timing Specifications ................................................................ 11

Absolute Maximum Ratings.......................................................... 16

Thermal Resistance .................................................................... 16

Electrostatic Discharge (ESD) Ratings .................................... 16

ESD Caution................................................................................ 16

REVISION HISTORY

9/2020—Revision 0: Initial Version

Rev. 0 | Page 2 of 35

Data Sheet

ADuCM410

The ADuCM410 operates from an on-chip oscillator and has a

phase-locked loop (PLL) of 160 MHz. This clock can optionally

be divided down to reduce current consumption. Additional

low power modes can be set via the ADuCM410 software.

The GPIO pins (Px.x) power up in high impedance input mode.

In output mode, the software chooses between open-drain

mode and push/pull mode. The pull-up and pull-down resistors

can be disabled and enabled in the software. The GPIO pins can

be configured with different voltage levels according to the

IOVDDx pin, such as 3.3 V, 1.8 V, and 1.2 V. In GPIO output

mode, the inputs can remain enabled to monitor the GPIO pins.

The GPIO pins can also be programmed to handle digital or

analog peripheral signals, in which case, the pin characteristics

are matched to the specific requirement.

The device includes a management data input/output (MDIO)

interface capable of operating up to 10 MHz. User programming is

eased by incorporating physical address (PHYADR) and device

address (DEVAD) hardware comparators. The nonerasable

kernel code combined with flags in user flash allow user code to

reliably switch between the two hardware independent flash

blocks.

A large support ecosystem is available for the Arm Cortex-M33

processor to ease product development of the ADuCM410.

Access is via the Arm serial wire debug port. On-chip factory

firmware supports in-circuit serial download via MDIO or I²C.

These features are incorporated into a low cost, quick start

development system supporting this precision analog

microcontroller.

The ADuCM410 integrates a range of on-chip peripherals that

can be configured under software control, as required in the

application. These peripherals include 2× universal asynchronous

receiver transmitter (UART), 3× I²C, and 3× serial peripheral

interface (SPI) serial input/output communication controllers,

general-purpose inputs/outputs (GPIOs), 32-element

programmable logic arrays (PLAs), five general-purpose timers,

a wake-up timer (WUT), and a system watchdog timer (WDT).

A 16-bit pulse-width modulation (PWM) with eight output

channels is also provided.

Note that throughout this data sheet, multifunction pins, such

as VDAC7/P4.2, are referred to either by the entire pin name or

by a single function of the pin, for example, P4.2, when only

that function is relevant.

Rev. 0 | Page 3 of 35

ADuCM410

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

1

VDAC0

VDAC1

VDAC10 VDAC11

AIN0

AIN1

PGA0

AIN2/PADC0P

0.2V/

0.5V

PGA0OUT

1

PGA1

AIN4/PADC01N

AIN3/PADC1P

PGA2

AIN5/PADC2P

0.2V/

0.5V

PGA2OUT

ADuCM410

1

PGA3

AIN7/PADC23N

AIN6/PADC3P

PGA0

AIN8/COM0P

COMP

GP TIMER

WATCHDOG

TIMER

AIN9/COM0N/PGA2OUT

VDAC8

2

16-BIT

GPIO

PLA

GPIOs

SAR ADC

AT 2MSPS

WAKE-UP TIMER

BUF

PGA1

PLAOx

PLAIx

AIN0

2 × 512kB FLASH/EE

WITH ECC/MPU

2 × 64kB SRAM

WITH ECC/MPU

CACHE

CONTROLLER

AIN10/COM1P

COMP

AIN11/COM1N/PGA0OUT

VDAC9

4

MDIO

SPI

AIN15

5

PGA2

SPIs

AVDD/2

IOVDD/2

AGND

DMA

AIN12/COM2P

COMP

AIN13/COM2N

VDAC10

SDAx,

SCLx

16MHz

OSC

32kHz

6

7

WIC

NVIC

2

PLL

ALP

I C

OSC

POR

1.1V

TEMPERATURE

SENSOR

Arm Cortex-M33

WITH DSP

UP TO 160MHz

HP

REF

SOUTx,

SINx

PGA3

UART

PWM

8

9

REF

1

AIN14/COM3P

COMP

BUF

2.5V

ALDO

DLP

REF

1

AIN15/COM3N

10

11

12

SWD

DLDO

VDAC11

1

BUF0_VREF

BUF1_VREF

AVDD_REG

DVDD_REG

SERIAL WIRE

3

EMULATION

1

THIS IS A PARTIAL FUNCTION OF A MULTIFUNCTION PIN. FOR EXAMPLE, VDAC0 AND AIN4/PADC01N ARE SEPARATE FUNCTIONS

ON THE SAME PIN, AIN4/PADC01N/VDAC0.

GPIOs REFER TO Px.x.

SERIAL WIRE EMULATION REFERS TO SWDIO, SWCLK, AND SWO.

MDIO REFERS TO PRTADDRx, MDIO, AND MCK.

SPIs REFER TO SLKx, CSx, MOSIx, SRDYx, AND MISOx.

NVIC IS NESTED VECTORED INTERRUPT CONTROLLER.

WAKE-UP INTERRUPT CONTROLLER.

2

3

4

5

6

7

8

HP REF IS HIGH POWER REFERENCE.

9

ALP REF IS ANALOG LOW POWER REFERENCE.

ALDO IS ANALOG LOW DROPOUT REGULATOR.

10

11

DLP REF IS DIGITAL LOW POWER REFERENCE.

12

DLDO IS DIGITAL LOW DROPOUT REGULATOR.

Figure 1.

Rev. 0 | Page 4 of 35

Data Sheet

ADuCM410

SPECIFICATIONS

AVDD = IOVDD0 = 2.85 V to 3.6 V, IOVDD1 = 1.2 V or 1.8 V, DVDD = 1.8 V to 3.6 V, VREF = 2.5 V for the internal reference, the core

frequency (f_CORE) = 160 MHz, and T_A= −40°C to +105°C, unless otherwise noted. HCLK is the high speed system clock.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC CHANNEL SPECIFICATIONS

ADC Power-Up Time

5

μs

Data Rate (f_ADC

Resolution

Integral Nonlinearity

)

2

MSPS

Bits

LSB

16

−4

2.5 V internal reference

Voltage input to AINx, PGA off,

differential mode

Voltage input to AINx, PGA off, single-

ended mode

PGA voltage input to ADC, G = 2

G = 4

G = 6

G = 8

G = 10

1

+3

+6

+8

−9.5

LSB

5

4

5

8

LSB

TIA input channels

TIA resistance (R_TIA) = 250 Ω

R_TIA= 750 Ω, 2 kΩ

R_TIA= 5 kΩ

R_TIA= 10 kΩ, 20 kΩ,100 kΩ

Differential and single-ended

−8

−11.5

−15

−0.9

3

6

8

+12

+8

+11.5

+15

+1.5

LSB

Differential Nonlinearity

DC Code Distribution¹

0.9

Minimum and maximum range from

mean ADC codes for 1000 samples

9

5

LSB

ADC input = 2 V, single-ended mode,

f

_ADC= 2 MSPS, PGA off

ADC input = 1 V, differential mode, f_ADC

=

50 kSPS, PGA gain = 2, oversampling ratio

(OSR) = 8

5

LSB

ADC input = 200 mV, differential mode,

f

_ADC= 50 kSPS, PGA gain = 10, OSR = 8

TIA mode, gain resistor = 100 kΩ, f_ADC

=

25 kSPS, OSR = 4, input current = 10 µA

ENDPOINT ERRORS

Offset Error

Voltage inputs only

PGA off

PGA channels; voltage input to ADC; G =

2, 4, 6, 8, 10; TIA input channels; all gain

settings; current converted to a voltage;

not production calibrated; user calibration

can remove this error

−425

−770

150

200

+330

+830

µV

−250

−415

−610

−1460

150

250

200

250

4

+225

+365

+555

+1375

µV

µV/°C

Gain resistor = 250 Ω, 750 Ω

Gain resistor = 2 kΩ

Gain resistor = 5 kΩ

Gain resistor = 10 kΩ, 20 kΩ,100 kΩ

PGA off

Matching compared to AIN0; for voltage

input channels, PGA off only

Offset Error Drift

Offset Error Drift Matching

1

Rev. 0 | Page 5 of 35

ADuCM410

Data Sheet

Parameter

Min

Typ

250

0.2

Max

+370

+0.3

Unit

Test Conditions/Comments

Full-Scale Error

−900

−0.33

µV

% of FS²

PGA off, voltage input to AINx

PGA voltage input to ADC; G = 2, 4 (not

factory calibrated); user calibration can

remove this error

−0.5

−5

0.2

+0.4

+12

+1

% of FS²

G = 6, 8, 10 (not factory calibrated); user

calibration can remove this error

TIA input channels, all gain settings,

current converted to a voltage

+5

−1

0.5

5

0.5

% of FS²

ppm/°C

Internal channels only

Gain Error Drift

Gain Error Drift Matching

Matching compared to AIN0; for voltage

input channels, PGA off only

PGA Mismatch Error

−0.3

+0.2

4

+0.3

%

Error between adjacent gain settings of

PGA

PGA Mismatch Error Drift

DYNAMIC PERFORMANCE

ppm/°C

Input frequency (f_IN) = 500 Hz sine wave,

sampling frequency (f_SAMPLE) = 1 MSPS

internally

Signal-to-Noise Ratio (SNR)

84

dB

Includes distortion and noise

components, voltage input, PGA off,

single-ended mode

89

dB

Voltage input, PGA off, differential mode

Total Harmonic Distortion (THD)

Peak Harmonic or Spurious Noise

Channel to Channel Crosstalk

ANALOG INPUT (VOLTAGE CHANNELS)

Input Voltage Ranges

−100

−88

−96

Measured on adjacent channels

Differential Mode

V_CM

VREF/(2 ×

gain)

−

V

_CM+ VREF/(2

V

PGA gain = 2, 4, 6, 8, 10; V_CMis common-

mode voltage

× gain)

Single-Ended Mode

Leakage Current

0

2.5

V

nA

Gain = 1 and PGA = off

Input voltage to AINx = 0.15 V to 2.5 V

(except AIN4 and AIN7)

5

30

nA

AIN4 and AIN7 only

Input buffer enabled

At 100 kHz sample rate from 0.15 V to

2.5 V, AINx = 0.15 V to 2.5 V (except AIN4

and AIN7)

Input Current

−60

10

+60

−60

−230

50

30

+135

+530

nA

pF

AIN4 and AIN7 only

PGA off, 2 MSPS ADC sample rate

During ADC acquisition

Input Capacitance

ANALOG INPUT (PGA VOLTAGE

CHANNELS)

PGA Gain Options

Settling Time

Compliant Range

1

10

250

10

G = 1, 2, 4, 6, 8, or 10

μs

mV

Lower of

2500 or

AVDD − 800

ANALOG INPUT (TIA CURRENT

CHANNELS)

Source and Sink Current Range

TIA Bias Voltage Range

−5

250

+5

Lower of

2500 or

mA

mV

AVDD – 800

500

1800

mV

R_TIA= 250 Ω

Rev. 0 | Page 6 of 35

Data Sheet

ADuCM410

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Output Voltage Range

250

Lower of

2500 or

mV

Except R_TIA= 250 Ω

AVDD − 800

500

1800

mV

R_TIA= 250 Ω

Allowed External Load Capacitance¹

No external extra capacitors to AGND or

to supply on AINx when used as TIA

inputs

TIA Gain Resistors

250 Ω, 750 Ω

2 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 100 kΩ

Gain Accuracy

Gain Drift over Temperature

Gain Mismatch Error

120

30

+12

120

+0.9

pF

%

ppm/°C

%

−5

+5

60

0.3

TIA gain resistor and ADC gain error

−0.8

Error introduced when moving up or

down one R_TIAvalue

ON-CHIP VOLTAGE REFERENCE

4.7 μF decoupling capacitor between

ADCREFP and ADCREFN

Output Voltage

2.5

V

Accuracy

Reference Temperature Coefficient

5

30

20

mV

ppm/°C

T_A= 25°C

T_A= −40°C to +25°C range

T_A= 25°C to 105°C range

10

Power Supply Rejection Ratio (PSRR)

DC

AC

70

60

dB

AVDD change effects, 2.85 V to 3.6 V

Tested with AVDD noise of 1 kHz, 10 kHz,

100 kHz, and 1 MHz

Output Impedance

2

Ω

Do not use as external reference source,

T_A= 25°C

EXTERNAL REFERENCE INPUT

Input Voltage Range

2.5

5

V

Only supports 2.5 V external reference

input

External reference source must be

Input Impedance

kΩ

capable of sourcing 500 µA minimum

BUFFERED REFERENCE VOLTAGE

OUTPUTS (BUFx_VREF)

1 μF capacitor required on both outputs

Output Voltage

1.25 or

2.5

V

Accuracy

Reference Temperature Coefficient

6

30

20

mV

T_A= 25°C, load = 4 mA

T_A= −40°C to +25°C range

T_A= 25°C to 105°C range

10

2.5

ppm/°C

mV/mA

Ω

mA

dB

Load Regulation

Output Impedance

Load Current

PSRR

4

70

VOLTAGE DAC (VDAC) CHANNEL

SPECIFICATIONS

VDAC Channel 0 to Channel 7: buffer on;

load resistance (R_L) = 1 kΩ, load

capacitance (C_L) = 100 pF; DACCONx, Bit 9

= 0 (normal drive, unless otherwise

stated); VDAC Channel 8 to Channel 11:

buffer on, R_L= 2.5 kΩ, C_L= 100 pF

DC Accuracy

Resolution

12

−2

−0.9

−13.5

−10

Bits

LSB

mV

Relative Accuracy³

Differential Nonlinearity³

Calculated Offset Error

Actual Offset Error

1.5

0.5

5

+2

+3

+0.9

+15.5

+10

Guaranteed monotonic

2.5 V internal reference

Measured at Code 0

VDAC Channel 0 to Channel 7: DACCONx,

Bit 9 = 1; R_L= 250 Ω; C_L= 100 pF

Rev. 0 | Page 7 of 35

ADuCM410

Data Sheet

Parameter

Min

−0.7

Typ

0.2

Max

+0.5

Unit

% of FS²

Test Conditions/Comments

Gain Error

VDAC Channel 0 to Channel 7: DACCONx,

Bit 9 = 1; R_L= 250 Ω; C_L= 100 pF

Offset Error Drift

Gain Error Drift

Short-Circuit Current

10

15

32

μV/°C

ppm/°C

mA

VDAC Channel 0 to Channel 7

VDAC Channel 8 to Channel 11

15

mA

DAC OUTPUTS

Output Range¹

0

2.5

V

VDAC Channel 0 to Channel 7

VDAC Channel 8 to Channel 11

Lower of 2.5

or AVDD − 0.7

Output Impedance

DAC AC CHARACTERISTICS

Slew Rate

Voltage Output Settling Time

Digital to Analog Glitch Energy

1

Ω

2.5

10

20

V/µs

µs

nV-sec

1 LSB change at major carry (where

maximum number of bits simultaneously

changes in DACDATx register)

COMPARATOR INPUT

Offset Voltage

15

mV

The offset voltage is dependent on the

comparator being enabled with its input

pins connected to external biasing

circuits; if the comparator is left powered

down or if the inputs to the comparator

are left floating, over time the offset error

may increase

Noninverting (positive), input

Inverting (negative), input, hysteresis

disabled

Inverting (negative), input, hysteresis =

10 mV

Inverting (negative), input, hysteresis =

210 mV

Negative input range (reference node of

the comparator)

Bias Current

−30

3¹

10¹

+43

nA

50¹

nA

V

740

0.5

840

940

Voltage Range

AVDD − 1.2

AGND

0

AVDD

2.0

Positive input range to comparator

Differential input range; positive input −

negative input voltage

V

Capacitance

Hysteresis

Hysteresis Voltage Accuracy

7

50

10

pF

mV

% of target

hysteresis

10

210

35

16 configurable options⁴

10 mV to 35 mV settings

5

15

% of target

hysteresis

µs

50 mV to 210 mV settings

Response Time

POWER-ON RESET (POR)

POR Trip Level (DVDD)

Refers to voltage at DVDD pin

Power-on level, see Figure 18

Power-down level (brownout)

1.6

1.62

1.77

1.7

V

ms

1.66

32

Timeout from POR

FLASH MEMORY

2× 512 kB, 128 kB SRAM

Endurance

Data Retention

10,000

10

Cycles

Years

MHz

%

Junction temperature (T_J) = 125°C

INTERNAL HIGH POWER OSCILLATOR

Accuracy

16

3

Rev. 0 | Page 8 of 35

Data Sheet

ADuCM410

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TEMPERATURE SENSOR

Voltage Output at 25°C

Voltage Temperature Coefficient

Accuracy

Indicates die temperature

0.13625

0.4568

2

32

7

V

mV/°C

°C

−3

+4.4

+10

INTERNAL LOW POWER OSCILLATOR

Accuracy

kHz

%

−10

3.3 V GPIO

Logic Inputs

IOVDD0 = 3.3 V

IOVDD × 0.3

Input Low Voltage (V_INL

)

0.99

V

Input High Voltage (V_INH

)

2

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up/Pull-Down

Disabled

120

125

−32

160

163

+1

210

+65

µA

nA

V_IN= 0 V

V_IN= 3.3 V

IOVDD0 power source

Logic Outputs

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

2.4

V

Source current (I_SOURCE) = 12 mA

0.4

10

Sink current (I_SINK) = 12 mA; for I²C SCL0,

SCL2, SDA0, and SDA2, I_SINK= 20 mA; for

I²C SCL1 and SDA1, I_SINK= 12 mA

Input Capacitor

pF

Short-Circuit Current

13

mA

1.8 V GPIO

IOVDD1 = 1.8 V

Logic Inputs

V_INL

0.54

V

V_INH

1.26

155

170

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up/Pull-Down

Disabled

194

217

+25

240

270

+2000

µA

nA

Input voltage (V_IN) = 0 V

V_IN= 1.8 V

IOVDD1 power source

−500

Logic Outputs

V_OH

V_OL

Input Capacitor

Short-Circuit Current

1.2 V GPIO

Logic Inputs

V_INL

1.4

V

pF

mA

I_SOURCE= 12 mA

I_SINK= 12 mA

0.3

10

17

IOVDD1 = 1.2 V

0.36

V

V_INH

0.84

55

V

Pull-Up Current

Pull-Down Current

Internal Pull-Up/Pull-Down

Disabled

76

82

+20

100

110

+1510

µA

nA

V_IN= 0 V

V_IN= 1.2 V

IOVDD1 power source

−450

Logic Outputs

V_OH

V_OL

1.0

V

pF

mA

I_SOURCE= 6 mA

I_SINK= 6 mA

0.18

10

Input Capacitor

Short-Circuit Current

7

MDIO

Logic Inputs

V_INL

V_INH

Logic Output

V_OH

V_OL

0.36

0.2

V

0.84

1.0

V

I_SOURCE= 4 mA

I_SINK= 4 mA

Rev. 0 | Page 9 of 35

ADuCM410

Data Sheet

Parameter

Min

Typ

Max

Unit

pF

mA

Test Conditions/Comments

Input Capacitor

Short-Circuit Current

10

7

MICROCONTROLLER UNIT (MCU)

CLOCK RATE

Using PLL Output

EXTERNAL RESET

Minimum Pulse Duration

PROCESSOR START-UP TIME

At Power-On

160

163

MHz

µs

10

Pin voltage must stay low for this period

32

1

ms

Includes kernel power-on execution time

After Reset Event

After Processor Power-Down

Core Sleep (Mode 1)⁵

System Sleep (Mode 2), Hibernate

(Mode 3)⁵

30

85

HCLK cycles

µs

Fixed number of HCLK periods

HCLK = 160 MHz from PLL

3

µs

HCLK = 16 MHz from internal oscillator

POWER REQUIREMENTS

Power Supply Voltage Range

AVDD to AGND

2.85

1.8

3.3

1.8 or

3.3

3.6

V

DVDD to DGND

IOVDD0 to IOGND

IOVDD1 to IOGND

2.85

1.08

3.3

1.2 or

1.8

3.6

1.98

V

If unused, can be tied to DVDD_REG or to

DGND

Analog Power Supply Currents

AVDD Current

Digital Power Supply Current

Current in Normal Mode

IOVDD0

900

1050

µA

Analog peripherals in idle mode

On power-up, GPIOs unloaded

175

20

12

200

60

30

µA

mA

IOVDD1

DVDD Current

Active Mode

Executing typical code (current from all

supplies)

16

4.8

11

4.3

2.46

mA

HCLK = 160 MHz from PLL

HCLK = 16 MHz from internal oscillator

HCLK = 160 MHz from PLL

Core Sleep (Mode 1)⁵

HCLK = 16 MHz from internal oscillator

System Sleep (Mode 2)⁵

19

17

Hibernate (Mode 3)⁵

Additional Power Supply Currents

2.44

mA

Full clock, PLL = 160 MHz

ADC

PGA

2.8

0.375

3.4

0.465

mA

Continuously converting at 2 MSPS

Per powered up PGA, excluding load

current

DAC

330

350

µA

Per powered up DAC, excluding load

current

Total Supply Current

18.8

mA

Active mode with PLL clock of 160 MHz

and ADC enabled.

¹These numbers are not production tested but are guaranteed by design and/or characterization data at production release.

²FS is full scale.

³VDAC linearity specifications generated using reduced DAC code range of 82 to 4095. For VDAC Channel 8 to Channel 11, end code of 4095 only used when AVDD –

0.7 V > 2.5 V.

⁴These options include 10 mV, 25 mV, 35 mV, 50 mV, 60 mV, 75 mV, 100 mV, 110 mV, 125 mV, 135 mV, 150 mV, 160 mV, 175 mV, 185 mV, 200 mV, and 210 mV.

⁵In core sleep mode, the system gates the clock to the Cortex-M33 core after the Cortex-M33 enters sleep mode. In system sleep mode, the system gates the system

bus clock and the peripheral bus clock after the Cortex-M33 enters sleep mode. See the ADuCM410 hardware reference manual for more information about the

various power modes.

Rev. 0 | Page 10 of 35

Data Sheet

ADuCM410

TIMING SPECIFICATIONS

I²C Timing

Table 2. I²C Timing in Standard Mode (100 kHz)—Slave/Master

Parameter

Description

Min

4.7

4.0

250

0

Typ

Max

Unit

µs

ns

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via

TCTL register, THDATIN bits)

3.45

µs

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

4.7

4.0

4.7

µs

ns

µs

pF

1

t_F

15

300

3.45

400

t_{VD; DAT}

t_{VD; ACK}

C_B

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

Table 3. I²C Timing in Fast Mode (400 kHz)—Slave/Master

Parameter Description

Min Typ Max Unit

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via TCTL register,

THDATIN bits)

1.3

0.6

100

0

µs

ns

µs

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

0.6

1.3

20

µs

ns

µs

pF

300

0.9

400

t_F

15

t_{VD; DAT}

t_{VD; ACK}

C_B

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

I²C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.

Table 4. I²C Timing in Fast Mode Plus (1 MHz)—Slave/Master

Parameter

Description

Min

0.5

0.26

50

Typ

Max

Unit

µs

ns

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time.

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via

TCTL register, THDATIN bits)

0

µs

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Fall time for both SCLx and SDAx

Data valid time

Data valid acknowledge time

Capacitive load for each bus line (not shown in Figure 2)

Rev. 0 | Page 11 of 35

0.26

0.5

µs

ns

µs

pF

120

0.45

550

t_F

t_{VD; DAT}

t_{VD; ACK}

C_B

ADuCM410

Data Sheet

I²C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.

Table 5. I²C Timing in High Speed Mode (3.4 MHz)—Slave Only

Parameter

Description

Min

160

60

160

10

Typ

Max

Unit

ns

t_L

t_H

t_SHD

t_DSU

t_DHD

SCLx low pulse width

SCLx high pulse width

Start condition hold time.

Data setup time

Data hold time (SDAx held internally after falling edge of SCLx, duration set via

TCTL register, THDATIN bits)

0

ns

t_RSU

t_PSU

t_BUF

t_R

Setup time for repeated start

Stop condition setup time

Bus-free time between a stop condition and a start condition

Rise time for both SCLx and SDAx

Up to C_B= 100 pF

Up to C_B= 400 pF

Fall time for both SCLx and SDAx

Up to C_B= 400 pF

160

200

ns

10

40

80

40

80

400

ns

pF

t_F

C_B

Capacitive load for each bus line (not shown in Figure 2)

t_BUF

t_R

SDAx (I/O)

MSB

LSB

ACK

MSB

t_DSU

t_DHD

t_RSU

t_F

t_DHD

t_PSU

t_{VD; DAT}

t_R

t_H

t_SHD

t_{VD; ACK}

1

2–7

8

9

1

SCLx (I)

t_L

P

S

S(R)

t_F

STOP

START

REPEATED

START

CONDITION CONDITION

Figure 2. I²C-Compatible Interface Timing

SPI Timing Specifications: Slave Mode

SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4, and P2.7 to P2.4) drive strength set to 12 mA, IOVDD1 ≥ 1.2 V, and 40 MHz SPI clock.

See Figure 3 and Figure 4.

Table 6. SPI Slave Mode Timing

Parameter

Symbol

Min

Typ

Max

Unit

TIMING REQUIREMENTS

CSx to SCLKx Edge

t_CS

25

ns

Minimum valid CSx inactive period

t_CS

M

SCLKx Low Pulse Width

SCLKx High Pulse Width

t_SL

t_SH

t_DSU

t_DHD

10

ns

Data Input Setup Time Before SCLKx Edge

Data Input Hold Time After SCLKx Edge

SWITCHING CHARACTERISTICS

Data Output Valid After SCLKx Edge

Data Output Valid After CSx Edge

CSx High After SCLKx Edge

5

t_DAV

t_DOCS

t_SFS

10

15

ns

8.75

Rev. 0 | Page 12 of 35

Data Sheet

ADuCM410

t_CSM

CSx

t_CS

t_SFS

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

MSB

MISOx

MOSIx

Figure 3. SPI Slave Mode Timing (Serial Clock Phase Mode, CTL Register, Bit 2, CPHA = 0)

t_CSM

CSx

t_CSx

t_SFS

SCLKx

(POLARITY = 0)

t_SH

t_SL

SCLKx

(POLARITY = 1)

t_DAV

t_DOCS

t_DF

t_DR

MISOx

MSB

BIT 6 TO BIT 1

LSB

MOSIx

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 4. SPI Slave Mode Timing (CPHA = 1)

Rev. 0 | Page 13 of 35

ADuCM410

Data Sheet

SPI Timing: Master Mode

SCLKx = 40 MHz, SPI SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4, and P2.7 to P2.4) pin drive strength set to 12 mA. IOVDD1 ≥ 1.2 V. DIV is

the SPI clock divider in the SPI baud rate selection register (see the ADuCM410 hardware reference manual for more information). t_HCLK

is the time period of HCLK set up by the user.

Table 7. SPI Master Mode Timing (Phase Mode = 0 and 1)

Parameter

Description

Min

Typ

Max

Unit

ns

t_SL

t_SH

SCLKx low pulse width

SCLKx high pulse width

Data output valid after SCLKx edge

Data input setup time before SCLKx edge

Data input hold time after SCLKx edge

Data output fall time

Data output rise time

SCLKx rise time

SCLKx fall time

(DIV + 1) × t_HCLK/2

t_DAV

t_DSU

t_DHD

t_DF

t_DR

t_SR

0

5

t_SF

ns

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DF

t_DR

MOSIx

MISOx

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 5. SPI Master Mode Timing (CPHA = 1)

SCLKx

(POLARITY = 0)

t_SH

t_SL

t_SR

t_SF

SCLKx

(POLARITY = 1)

t_DAV

t_DF

t_DR

MOSIx

MISOx

MSB

BIT 6 TO BIT 1

LSB

MSB IN

BIT 6 TO BIT 1

LSB IN

t_DSU

t_DHD

Figure 6. SPI Master Mode Timing (CPHA = 0)

Rev. 0 | Page 14 of 35

Data Sheet

ADuCM410

Table 8. MDIO vs. MDC Timing

Parameter¹

Description

Min

Typ

Max

10

4

Unit

MHz

ns

Maximum MCK Clock Speed

Push/pull mode

Open-drain mode, pull-up resistance (R_PULLUP) = 312 Ω

MDIO setup before MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

MDIO valid after MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

Data output after MCK edge (push/pull mode)

Open-drain mode, R_PULLUP= 312 Ω

t_SETUP

t_HOLD

t_DELAY

5

10

7

10

ns

26

100

¹In Figure 7, CFP is C formfactor pluggable. V_IHis the voltage input high level, and V_ILis voltage input low level.

MCK

V

IH

IL

CFP

INPUT

MDIO

V

IH

IL

CFP

INPUT

MDIO

V

OH

OL

CFP

OUTPUT

t_SETUPt_HOLD

t_DELAY

Figure 7. MDIO Timing

Rev. 0 | Page 15 of 35

ADuCM410

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 9.

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

AVDD to AGND

IOVDD0 to IOGND

IOVDD1 to IOGND

DVDD to DGND

AVDD to IOVDD0

Analog Input Voltage to AGND

(AVDD Range = 2.85 V to 3.6 V)

Digital Input Voltage to IOGND

−0.3 V to +3.63 V

−0.3 V to +1.98 V

−0.3 V to +3.63 V

IOVDD0 0.3 V

−0.3 V to AVDD + 0.3 V,

must be ≤3.63 V

−0.3 V to IOVDD0 + 0.3 V,

must be ≤3.63 V

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

the junction to case thermal resistance.

Table 10. Thermal Resistance

Package Type

1

θ_JA

35

34

θ_JC

Unit

°C/W

BC-81-4

CB-64-2

0.12

0.16

Digital Input Voltage to IOGND (P1.0 −0.3 V to IOVDD1 + 0.3 V,

to P1.7 and P0.0 to P0.3 Only)¹

AGND to DGND

must be ≤1.98 V

−0.3 V to +0.3 V

0 mA to 40 mA

−40 mA to 0 mA

¹JEDEC 2S2P.

IOGND to DGND

ELECTROSTATIC DISCHARGE (ESD) RATINGS

Total Positive GPIO Pins Current

Total Negative GPIO Pins Current

Temperature Ranges

Storage

Operating

Reflow Profiles

The following ESD information is provided for handling of ESD

sensitive devices in an ESD protected area only.

−65°C to +150°C

−40°C to +105°C

Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.

Field induced charged device model (FICDM) per

ANSI/ESDA/JEDEC JS-002.

SnPb Assemblies (10 sec to 30 sec) 240°C

ESD Ratings for ADuCM410

Pb-Free Assemblies (20 sec to

40 sec)

Junction Temperature

260°C

Table 11. ADuCM410, 81-Ball CSP_BA and 64-Ball WLCSP

150°C

ESD Model

Withstand Threshold (kV)

Class

¹When IOVDD1 is the selected power rail.

HBM

3

2

FICDM

0.5

C2A

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

ESD CAUTION

Rev. 0 | Page 16 of 35

Data Sheet

ADuCM410

TYPICAL PERFORMANCE CHARACTERISTICS

2.510

16

14

12

10

8

DEVICE 1

DEVICE 2

DEVICE 3

2.508

2.506

2.504

2.502

2.500

2.498

2.496

2.494

2.492

2.490

6

4

DEVICE 5, AIN0

DEVICE 5, AIN1

DEVICE 5, AIN2

DEVICE 5, AIN3

DEVICE 5, AIN4

DEVICE 5, AIN5

DEVICE 5, AIN6

DEVICE 5, AIN7

DEVICE 5, AIN8

DEVICE 5, AIN9

DEVICE 5, AIN10

DEVICE 5, AIN11

DEVICE 5, AIN12

DEVICE 5, AIN13

DEVICE 5, AIN14

DEVICE 5, AIN15

2

DEVICE 6, AIN0

DEVICE 6, AIN1

DEVICE 6, AIN2

DEVICE 6, AIN3

DEVICE 6, AIN4

DEVICE 6, AIN5

DEVICE 6, AIN6

DEVICE 6, AIN7

DEVICE 6, AIN8

0

–2

0.1

0.5

0.9

1.3

1.7

2.1

2.5

2.9

3.3

3.7

4.0

0.30

0.60

0.90

1.20

1.35

1.65

1.95

2.25

2.50

VOLTAGE (V)

LOAD CURRENT (mA)

Figure 11. ADC Input Current vs. Voltage on AINx, f_SAMPLE= 100 kSPS

Figure 8. BUF0_VREF Load Regulation, 2.5 V Output Setting

3

1.258

DEVICE 1

DEVICE 2

DEVICE 3

1.256

1.254

1.252

1.250

1.248

1.246

1.244

1.242

1.240

2

1

0

–1

–2

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0.1

0.5

0.9

1.3

1.7

2.1

2.5

2.9

3.3

3.7

4.0

LOAD CURRENT (mA)

Figure 12. Temperature Sensor Accuracy, No Calibration, 240 Devices

Figure 9. BUF0_VREF Load Regulation, 1.25 V Output Setting

350

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

2.494

300

250

200

150

100

50

DEVICE 5, AIN0

DEVICE 5, AIN1

DEVICE 5, AIN2

DEVICE 5, AIN3

DEVICE 5, AIN4

DEVICE 5, AIN5

DEVICE 5, AIN6

DEVICE 5, AIN7

DEVICE 5, AIN8

DEVICE 5, AIN9

DEVICE 5, AIN10

DEVICE 5, AIN11

DEVICE 5, AIN12

DEVICE 5, AIN13

DEVICE 5, AIN14

DEVICE 5, AIN15

DEVICE 6, AIN0

DEVICE 6, AIN1

DEVICE 6, AIN2

DEVICE 6, AIN3

DEVICE 6, AIN4

DEVICE 6, AIN5

DEVICE 6, AIN6

DEVICE 6, AIN7

DEVICE 6, AIN8

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100

TEMPERATURE (°C)

0.30

0.60

0.90

1.20

1.35

1.65

1.95

2.25

2.50

VOLTAGE (V)

Figure 10. Input Current vs. Voltage on AINx, f_SAMPLE= 2 MSPS

Figure 13. Reference Voltage Drift vs. Temperature, 250 Devices

Rev. 0 | Page 17 of 35

ADuCM410

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

VDAC1

VDAC3/

P4.0/

VDAC7/

P4.2

RESET

P2.3/

BM/

P2.5/

P2.6/IRQ5/

SCLK2/

A

B

C

D

E

F

IOVDD0

IOGND

MISO2/

PLAO19

PLAI11

PLAI10

PLAO20

AIN15/

COM3N/

BUF1_VREF

VDAC6/

P4.1/

PLAO28

P2.4/

MOSI2/

PLAO18

P2.7/IRQ6/

CS2/

PLAO21

P0.4/SCL0/

SIN0/

PLAO2

P0.5/SDA0/

SOUT0/

PLAO3

VREF

AIN0

SWDIO

SWCLK

P2.1/DM/

IRQ2/

ECLKIN/

COMPDIN3/

PLAI9

P2.2/

POR/

CLKOUT/

SWO

P2.0/

P0.7/IRQ4/

SDA2/

COMPDIN1/

PLAO5

P0.6/IRQ3/

SCL2/

COMPDIN0/

PLAO4

AIN3/

PADC1P

AIN10/

COM1P

VDAC5/

P4.4

ADCCONV/

COMPDIN2/

PLAI8

AIN11/

COM1N/

PGA0OUT

P4.7/

IRQ7/

PLACLK2

AIN2/

PADC0P

VDAC8/

P5.0

VDAC11/

P5.3

AIN1

P5.6

P5.5

IOGND

IOVDD1

P1.2/

SCL1/

PWM0/

PLAI6

P1.1/SOUT1/

COMOUT3/

PLAI5

P1.0/SIN1/

COMOUT2/

PLAI4

DNC

P5.4

AIN5/

PADC2P

AIN12/

COM2P

VDAC9/

P5.1

ADCREFN

ADCREFP

P1.3/

SDA1/

PWM1/

PLAI7

AIN9/

COM0N/

PGA2OUT

P0.1/MISO0/

COMOUT1/

PLAI1

P0.0/SCLK0/

COMOUT0/

PLAI0

AIN6/

PADC3P

VDAC10/

P5.2

P4.5/PWM7

P4.3/PWM6

P3.2/

P3.3/

PRTADDR3/

SIN0/

P1.4/

P0.3/IRQ0/

AIN4/

PADC01N/

VDAC0

AIN14/

COM3P/

BUF0_VREF

P0.2/MOSI0/

PLACLK1/

PLAI2

AIN8/

COM0P

PRTADDR2/

PWMTRIP/

PLAI14

SCLK1/

PWM2/

PLAO10

CS0/

PLACLK0/

PLAI3

G

H

J

PLAI15

P3.4/

IRQ9/

PRTADDR4/

SOUT0/

PLAO26

P3.1/

P1.5/

AIN7/

PADC23N/

VDAC2

PRTADDR1/

PWMSYNC/

PLAI13

AIN13/

COM2N

P3.7/

PLAO29

MISO1/

PWM3/

PLAO11

AGND

AVDD

DGND

DVDD

P3.0/

IRQ8/

PRTADDR0/

SRDY0/

PLAI12

P3.5/

MCK/

SRDY1/

PLAO27

P3.6/

MDIO/

SRDY2/

PLAO30

P1.6/

P1.7/IRQ1/

MOSI1/

PWM4/

PLAO12

CS1/

PWM5/

PLAO13

VDAC4

AVDD_REG

DVDD_REG

DNC = DO NOT CONNECT. KEEP THIS PIN FLOATING.

Figure 14. 81-Ball CSP_BGA Pin Configuration

Table 12. 81-Ball CSP_BGA Pin Configuration Descriptions

Ball No. Mnemonic

Type¹

Description

A1

A2

VDAC1

VDAC3/P4.0/PLAI11

AO

Voltage DAC 1 Output.

AO/I/O Voltage DAC 3 Output (VDAC3).

Digital Input/Output Port 4.0 (P4.0).

Input to PLA Element 11 (PLAI11).

A3

VDAC7/P4.2

AO/I/O Voltage DAC 7 Output (VDAC7).

Digital Input/Output Port 4.2 (P4.2).

A4

A5

RESET

I

Reset Input (Active Low). An internal pull-up resistor is included with this pin.

P2.3/BM/PLAI10

I/O

Digital Input/Output Port 2.3 (P2.3). An internal pull-up resistor is enabled

at power-up on P2.3.

Boot Mode (BM). This pin determines the start-up sequence after every

reset.

Input to PLA Element 10 (PLAI10).

Rev. 0 | Page 18 of 35

Data Sheet

ADuCM410

Ball No. Mnemonic

Type¹

Description

A6

P2.5/MISO2/PLAO19

I/O

Digital Input/Output Port 2.5 (P2.5).

SPI Channel 2 (SPI2) Master Input, Slave Output (MISO2).

Output of PLA Element 19 (PLAO19).

Digital Input/Output Port 2.6 (P2.6).

External Interrupt 5 (IRQ5).

A7

P2.6/IRQ5/SCLK2/ PLAO20

I/O

SPI2 Clock (SCLK2).

Output of PLA Element 20 (PLAO20).

3.3 V GPIO Supply.

Ground for Digital Inputs/Outputs.

0.92 V Reference with a 100 nF Capacitor.

Analog Input 15 (AIN15).

A8

A9

B1

B2

IOVDD0

IOGND

VREF

S

AO/AI

AI/AO

AIN15/COM3N/BUF1_VREF

Comparator 3 Emitter Voltage (V_E) Negative (COM3N).

Buffered Reference Voltage Source (BUF1_VREF).

B3

VDAC6/P4.1/PLAO28

AO/I/O Voltage DAC 6 Output (VDAC6).

Digital Input/Output Port 4.1 (P4.1).

Output of PLA Element 2 (PLAO28).

B4

B5

B6

SWDIO

SWCLK

P2.4/MOSI2/PLAO18

I/O

I

I/O

Serial Wire Bidirectional Data.

Serial Wire Debug Clock.

Digital Input/Output Port 2.4 (P2.4).

SPI2 Master Output, Slave Input (MOSI2).

Output of PLA Element 18 (PLAO18).

Digital Input/Output Port 2.7 (P2.7).

External Interrupt 6 (IRQ6).

B7

P2.7/IRQ6/CS2/PLAO21

I/O

SPI2 Chip Select (CS2). Active low.

Output of PLA Element 21 (PLAO21).

Digital Input/Output Port 0.4 (P0.4).

I²C Channel 0 (I²C0) Serial Clock (SCL0).

UART Channel 0 (UART0) Input (SIN0).

Output of PLA Element 2 (PLAO2).

Digital Input/Output Port 0.5 (P0.5).

I²C0 Serial Data (SDA0).

B8

B9

P0.4/SCL0/SIN0/PLAO2

I/O

P0.5/SDA0/SOUT0/PLAO3

UART0 Output (SOUT0).

Output of PLA Element 3 (PLAO3).

Analog Input 0.

Analog Input 3 (AIN3).

C1

C2

AIN0

AIN3/PADC1P

AI

PGA Channel 1 Positive (PADC1P).

Analog Input 10 (AIN10).

Comparator 1 Positive input (COM1P).

Voltage DAC 5 Output (VDAC5).

Digital Input/Output Port 4.4 (P4.4).

Digital Input/Output Port 2.2 (P2.2).

C3

C4

C5

AIN10/COM1P

AI

VDAC5/P4.4

AO

I/O

P2.2/POR/CLKOUT/SWO

Reset Output (POR). This pin function is an output and it is the default.

Clock Output (CLKOUT).

Serial Wire Debug Output (SWO).

C6

P2.0/ADCCONV/COMPDIN2/PLAI8

I/O

Digital Input/Output Port 2.0 (P2.0).

External Input to Start ADC Conversions (ADCCONV).

Comparator 2 Digital Input for Three-State (COMPDIN2).

Input to PLA Element 8 (PLAI8).

Rev. 0 | Page 19 of 35

ADuCM410

Data Sheet

Ball No. Mnemonic

Type¹

Description

C7

P2.1/DM/IRQ2/ECLKIN/COMPDIN3/PLAI9

I/O

Digital Input/Output Port 2.1 (P2.1).

Download Mode Selection (DM).

External Interrupt 2 (IRQ2).

External Input Clock (ECLKIN).

Comparator 3 Digital Input for Three-State (COMPDIN3).

Input to PLA Element 9 (PLAI9).

Digital Input/Output Port 0.7 (P0.7).

External Interrupt 4 (IRQ4).

C8

C9

P0.7/IRQ4/SDA2/COMPDIN1/PLAO5

P0.6/IRQ3/SCL2/COMPDIN0/PLAO4

I/O

I²C Channel 2 (I²C2) Serial Data (SDA2).

Comparator 1 Digital Input for Three-State (COMPDIN1).

Output of PLA Element 5 (PLAO5).

Digital Input/Output Port 0.6 (P0.6).

External Interrupt 3 (IRQ3).

I²C2 Serial Clock (SCL2).

Comparator 0 Digital Input for Three-State (COMPDIN0).

Output of PLA Element 4 (PLAO4).

Analog Input 1.

D1

D2

AIN1

AIN2/PADC0P

AI

Analog Input 2 (AIN2).

PGA Channel 0 Positive (PADC0P).

Analog Input 11 (AIN11).

D3

AIN11/COM1N/PGA0OUT

AO/AI

Comparator 1 V_ENegative (COM1N).

PGA Channel 0 Output (PGA0OUT).

D4

D5

VDAC8/P5.0

AO/I/O Voltage DAC 8 Output (VDAC8).

Digital Input/Output Port 5.0 (P5.0).

AO/I/O Voltage DAC 11 Output (VDAC11).

Digital Input/Output Port 5.1 (P5.3).

VDAC11/P5.3

D6

D7

P5.6

I/O

Digital Input/Output Port 5.6.

Digital Input/Output Port 4.7 (P4.7).

External Interrupt 7 (IRQ7).

P4.7/IRQ7/PLACLK2

PLA Input Clock 2 (PLACLK2).

Ground for Digital Inputs/Outputs.

1.2 V/1.8 V GPIO Supply. If unused, IOVDD1 can be tied to DVDD_REG or

to DGND.

D8

D9

IOGND

IOVDD1

S

E1

E2

ADCREFN

AO/AI

AI

Decoupling Capacitor Connection for ADC Reference Buffer. Connect this

pin to AGND.

Analog Input 5 (AIN5).

AIN5/PADC2P

PGA Channel 2 Positive (PADC2P).

Analog Input 12 (AIN12).

Comparator 2 V_EPositive (COM2P).

E3

E4

AIN12/COM2P

VDAC9/P5.1

AI

AO/I/O Voltage DAC 9 Output (VDAC9).

Digital Input/Output Port 5.1 (P5.1).

Do Not Connect. Keep this pin floating.

E5

E6

E7

DNC

P5.5

I/O

Digital Input/Output Port 5.5.

Digital Input/Output Port 1.2 (P1.2).

I²C Channel 1 (I²C1) Serial Clock (SCL1).

PWM Output 0 (PWM0).

P1.2/SCL1/PWM0/PLAI6

Input to PLA Element 6 (PLAI6).

Ball E7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Rev. 0 | Page 20 of 35

Data Sheet

ADuCM410

Ball No. Mnemonic

Type¹

Description

E8

P1.1/SOUT1/COMOUT3/PLAI5

I/O

Digital Input/Output Port 1.1 (P1.1).

UART1 Output (SOUT1).

Comparator 3 Output (COMOUT3).

Input to PLA Element 5 (PLAI5).

Ball E8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

E9

P1.0/SIN1/COMOUT2/PLAI4

I/O

Digital Input/Output Port 1.0 (P1.0).

UART1 Input (SIN1).

Comparator 2 Output (COMOUT2).

Input to PLA Element 4 (PLAI4).

Ball E9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

F1

F2

ADCREFP

AO/AI

AI

Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 µF

Decoupling Capacitor.

Analog Input 6 (AIN6).

AIN6/PADC3P

PGA Channel 3 Positive (PADC3P).

Analog Input 9 (AIN9).

Comparator 0 V_ENegative (COM0N).

PGA Channel 2 Output (PGA2OUT).

F3

F4

AIN9/COM0N/PGA2OUT

VDAC10/P5.2

AO/AI

AO/I/O Voltage DAC 10 Output (VDAC10).

Digital Input/Output Port 5.2 (P5.2).

F5

F6

P5.4

P4.5/PWM7

I/O

Digital Input/Output Port 5.4.

Digital Input/Output Port 4.5 (P4.5).

PWM Output 7 (PWM7).

F7

F8

F9

P1.3/SDA1/PWM1/PLAI7

I/O

Digital Input/Output Port 1.3 (P1.3).

I²C1 Serial Data (SDA1).

PWM Output 1 (PWM1).

Input to PLA Element 7 (PLAI7).

Ball F7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 0.1 (P0.1).

SPI Channel 0 (SPI0) Master Input, Slave Output (MISO0).

Comparator 1 Output (COMOUT1).

Input to PLA Element 1 (PLAI1).

Ball F8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

P0.1/MISO0/COMOUT1/PLAI1

P0.0/SCLK0/COMOUT0/PLAI0

Digital Input/Output Port 0.0 (P0.0).

SPI0 Clock (SCLK0).

Comparator 0 Output (COMOUT0).

Input to PLA Element 0 (PLAI0).

Ball F9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

G1

G2

G3

AIN4/PADC01N/VDAC0

AIN14/COM3P/BUF0_VREF

AIN8/COM0P

AI

Analog Input 4 (AIN4).

PGA Channel 0/PGA Channel 1 Negative (PADC01N).

Voltage DAC 0 Output (VDAC0).

Analog Input 14 (AIN14).

Comparator 3 V_EPositive (COM3P).

Buffered Reference Voltage Source (BUF0_VREF).

Analog Input 8 (AIN8).

AI/AO

AI

Comparator 0 V_EPositive (COM0P).

Rev. 0 | Page 21 of 35

ADuCM410

Data Sheet

Ball No. Mnemonic

Type¹

Description

G4

P3.2/PRTADDR2/PWMTRIP/PLAI14

I/O

Digital Input/Output Port 3.2 (P3.2).

MDIO Port Address Bit 2 (PRTADDR2).

PWM Trip (PWMTRIP).

Input to PLA Element 14 (PLAI14).

Digital Input/Output Port 3.3 (P3.3).

MDIO Port Address Bit 3 (PRTADDR3).

UART0 Input (SIN0).

G5

P3.3/PRTADDR3/SIN0/PLAI15

I/O

Input of PLA Element 15 (PLAI15).

Digital Input/Output Port 4.3 (P4.3).

PWM Output 6 (PWM6).

Digital Input/Output Port 1.4 (P1.4).

SPI Channel 1 (SPI1) Clock (SCLK1).

PWM Output 2 (PWM2).

G6

G7

P4.3/PWM6

I/O

P1.4/SCLK1/PWM2/PLAO10

Output of PLA Element 10 (PLAO10).

Ball G7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

G8

G9

P0.3/IRQ0/CS0/PLACLK0/PLAI3

P0.2/MOSI0/PLACLK1/PLAI2

I/O

Digital Input/Output Port 0.3 (P0.3).

External Interrupt 0 (IRQ0).

SPI0 Chip Select (CS0). Active low.

PLA Clock 0 (PLACLK0).

Input to PLA Element 3 (PLAI3).

Ball G8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 0.2 (P0.2).

SPI0 Master Output, Slave Input (MOSI0).

PLA Clock 1 (PLACLK1).

Input to PLA Element 2 (PLAI2).

Ball G9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

H1

H2

AIN7/PADC23N/VDAC2

AIN13/COM2N

AI

Analog Input 7 (AIN7).

PGA Channel 2/PGA Channel 3 Negative (PADC23N).

Voltage DAC 2 Output (VDAC2).

Analog Input 13 (AIN13).

Comparator 2 V_ENegative (COM2N).

Analog Ground.

H3

H4

AGND

S

I/O

P3.1/PRTADDR1/PWMSYNC/PLAI13

Digital Input/Output Port 3.1 (P3.1).

MDIO Port Address Bit 1 (PRTADDR1).

PWM Synchronization (PWMSYNC).

Input to PLA Element 13 (PLAI13).

Digital Input/Output Port 3.4 (P3.4).

External Interrupt 9 (IRQ9).

H5

P3.4/IRQ9/PRTADDR4/SOUT0/PLAO26

I/O

MDIO Port Address Bit 4 (PRTADDR4).

UART0 Output (SOUT0).

Output of PLA Element 26 (PLAO26).

Digital Input/Output Port 3.7 (P3.7).

Output of PLA Element 29 (PLAO29).

Digital Input/Output Port 1.5 (P1.5).

SPI1 Master Input, Slave Output (MISO1).

PWM Output 3 (PWM3).

H6

H7

P3.7/PLAO29

I/O

P1.5/MISO1/PWM3/PLAO11

Output of PLA Element 11 (PLAO11).

Ball H7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

H8

H9

DGND

DVDD

S

Digital Ground.

1.8 V/3.3 V Digital Power Supply.

Rev. 0 | Page 22 of 35

Data Sheet

ADuCM410

Ball No. Mnemonic

Type¹

AO

Description

J1

J2

VDAC4

AVDD_REG

Voltage DAC 4 Output.

2.5 V Analog Regulator Supply with 0.47 µF Decoupling Capacitor. Do not

use AVDD_REG to power external circuits.

AO

J3

J4

AVDD

S

I/O

3.3 V Analog Power Supply.

Digital Input/Output Port 3.0 (P3.0).

External Interrupt 8 (IRQ8).

P3.0/IRQ8/PRTADDR0/SRDY0/PLAI12

MDIO Port Address Bit 0 (PRTADDR0).

SPI0 Ready (SRDY0).

Input to PLA Element 12 (PLAI12).

Digital Input/Output Port 3.5 (P3.5).

MDIO Slave Clock (MCK).

J5

J6

J7

P3.5/MCK/SRDY1/PLAO27

P3.6/MDIO/SRDY2/PLAO30

P1.6/MOSI1/PWM4/PLAO12

I/O

SPI1 Ready (SRDY1).

Output of PLA Element 27 (PLAO27).

Digital Input/Output Port 3.6 (P3.6).

MDIO Slave Data (MDIO).

SPI2 Ready (SRDY2).

Output of PLA Element 30 (PLAO30).

Digital Input/Output Port 1.6 (P1.6).

SPI1 Master Output, Slave Input (MOSI1).

PWM Output 4 (PWM4).

Output of PLA Element 12 (PLAO12).

Ball J7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

J8

P1.7/IRQ1/CS1/PWM5/PLAO13

I/O

Digital Input/Output Port 1.7 (P1.7).

External Interrupt 1 (IRQ1).

SPI1 Chip Select (CS1). Active low.

PWM Output 5 (PWM5).

Output of PLA Element 13 (PLAO13).

Ball J8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

J9

DVDD_REG

AO

1.1 V Digital Regulator Supply with 0.47 µF Decoupling Capacitor. Do not

use DVDD_REG to power external circuits.

¹AO is analog output, I/O is input/output, I is digital input, S is supply, and AI is analog input.

Rev. 0 | Page 23 of 35

ADuCM410

Data Sheet

1

2

3

4

5

6

7

8

P2.1/DM/

IRQ2/

ECLKIN/

COMPDIN3/

PLAI9

P2.0/

ADCCONV/

COMPDIN2/

PLAI8

IOGND

SWDIO

VDAC7

VDAC6

VDAC5

VDAC3

A

B

C

D

E

F

P0.3/IRQ0/

P0.2/MOSI0/

PLACLK1/

PLAI2

P2.3/

BM

PLAI10

CS0/

PLACLK0/

PLAI3

SWCLK

RESET

VDAC1

VREF

AVDD

P2.2/

POR/

CLKOUT/

SWO

P0.0/SCLK0/

COMOUT0/

PLAI0

P1.0/SIN1/

COMOUT2/

PLAI4

P0.1/MISO0/

COMOUT1/

PLAI1

AIN4/

PADC01N/

VDAC0

AIN14/

COM3P/

BUF0_VREF

AIN2/

PADC0P

IOVDD1

DVDD_REG

IOVDD0

P1.2/

SCL1/

PWM0/

PLAI6

P1.3/

SDA1/

PWM1/

PLAI7

P1.1/

SOUT1/

COMOUT3/

PLAI5

AIN3/

PADC1P

AIN10/

COM1P

AIN0

DGND

P1.4/

P1.7/

SCLK1/

PWM2/

PLAO10

AIN12/

COM2P

VDAC8/

P5.0

IRQ1/CS1/

PWM5/

PLAO13

AGND

AVDD_REG

ADCREFP

IOGND

P1.5/

P1.6/

P0.7/IRQ4/

SDA2/

COMPDIN1/

PLAO5

P3.2/

AIN8/

COM0P

VDAC9/

P5.1

MISO1/

PWM3/

PLAO11

MOSI1/

PWM4/

PLAO12

PRTADDR2/

PWMTRIP/

PLAI14

ADCREFN

P0.6/IRQ3/

SCL2/

P3.1/

P0.4/SCL0/

SIN0/

P0.5/SDA0/

SOUT0/

AIN7/

PADC23N/

VDAC2

PRTADDR1/

PWMSYNC/

PLAI13

VDAC11/

P5.3

AIN9/

G

H

AIN1

COMPDIN0/

PLAO4

COM0N

PLAO2

PLAO3

P3.5/

MCK/

SRDY1/

PLAO27

P3.0/

PRTADDR0/

SRDY0/

P3.6/

MDIO

VDAC10/

P5.2

AIN13/

COM2N

IOGND

DVDD

VDAC4

PLAI12

Figure 15. 64-Ball WLCSP Pin Configuration

Table 13. 64-Ball WLCSP Pin Function Descriptions

Pin No.

Mnemonic

Type¹

S

Description

A1

IOGND

Ground for Digital Inputs/Outputs.

Digital Input/Output Port 2.0 (P2.0).

A2

P2.0/ADCCONV/COMPDIN2/PLAI8

I/O

External Input to Start ADC Conversions (ADCCONV).

Comparator 2 Digital Input for Three-State (COMPDIN2).

Input to PLA Element 8 (PLAI8).

Ball A2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

A3

P2.1/DM/IRQ2/ECLKIN/COMPDIN3/PLAI9

I/O

Digital I/O Port 2.1 (P2.1).

Download Mode Selection (DM).

External Interrupt 2 (IRQ2).

External Input Clock (ECLKIN).

Comparator 3 Digital Input for Three-State (COMPDIN3).

Input to PLA Element 9 (PLAI9).

Ball A3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

A4

A5

A6

A7

A8

SWDIO

VDAC7

VDAC6

VDAC5

VDAC3

I/O

AO

Serial Wire Bidirectional Data.

Voltage DAC 7 Output.

Voltage DAC 6 Output.

Voltage DAC 5 Output.

Voltage DAC 3 Output.

Rev. 0 | Page 24 of 35

Data Sheet

ADuCM410

Pin No.

Mnemonic

Type¹

Description

B1

P0.3/IRQ0/CS0/PLACLK0/PLAI3

I/O

Digital Input/Output Port 0.3 (P0.3).

External Interrupt 0 (IRQ0).

SPI0 Chip Select (CS0).

PLA Clock 0 (PLACLK0).

Input to PLA Element 3 (PLAI3).

Ball B1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

B2

B3

P0.2/MOSI0/PLACLK1/PLAI2

I/O

Digital Input/Output Port 0.2 (P0.2).

SPI0 Master Out, Slave In (MOSI0).

PLA Clock 1 (PLACLK1).

Input to PLA Element 2 (PLAI2).

Ball B2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

P2.3/BM/PLAI10

Digital Input/Output Port 2.3 (P2.3). An internal pull-up resistor is enabled

at power-up on P2.3.

Boot Mode (BM). This pin determines the start-up sequence after every

reset.

Input to PLA Element 10 (PLAI10).

Serial Wire Debug Clock.

Reset Input (Active Low). An internal pull-up resistor is included with this pin.

Voltage DAC 1 Output.

0.92 V Reference with a 100 nF Capacitor.

3.3 V Analog Power Supply.

1.2 V/1.8 V GPIO Supply. If unused, IOVDD1 can be tied to DVDD_REG or

to DGND.

B4

B5

B6

B7

B8

C1

SWCLK

RESET

VDAC1

VREF

AVDD

IOVDD1

I

AO

AO/AI

S

C2

C3

C4

C5

P0.1/MISO0/COMOUT1/PLAI1

P0.0/SCLK0/COMOUT0/PLAI0

P1.0/SIN1/COMOUT2/PLAI4

P2.2/POR/CLKOUT/SWO

I/O

Digital Input/Output Port 0.1 (P0.1).

SPI 0 Master Input, Slave Output (MISO0).

Comparator 1 Output (COMOUT1)

Input to PLA Element 1 (PLAI1).

Ball C2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 0.0 (P0.0).

SPI 0 Clock (SCLK0).

Comparator 0 Output (COMOUT0).

Input to PLA Element 0 (PLAI0).

Ball C3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 1.0 (P1.0).

UART Input 1 (SIN1).

Comparator 2 Output (COMOUT2).

Input to PLA Element 4 (PLAI4).

Ball C4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 2.2 (P2.2).

Reset Output (POR). This pin function is an output, and it is the default.

Clock Output (CLKOUT).

Serial Wire Debug (SWD) Output (SWO).

Analog Input 14 (AIN14).

Comparator 3 Emitter Voltage (V_E) Positive (COM3P).

Buffered Reference Voltage source (BUF0_VREF).

Analog Input 2 (AIN2).

C6

C7

AIN14/COM3P/BUF0_VREF

AIN2/PADC0P

AI/AO

AI

PGA Channel 0 Positive (PADC0P).

Rev. 0 | Page 25 of 35

ADuCM410

Data Sheet

Pin No.

Mnemonic

Type¹

Description

C8

AIN4/PADC01N/VDAC0

AI

Analog Input 4 (AIN4).

PGA Channel 0/PGA Channel 1 Negative (PADC01N).

Voltage DAC 0 Output (VDAC0).

D1

DVDD_REG

AO

1.1 V Digital Regulator Supply with 0.47 µF Decoupling Capacitor. Do not

use DVDD_REG to power external circuits.

D2

D3

DGND

P1.2/SCL1/PWM0/PLAI6

S

I/O

Digital Ground.

Digital Input/Output Port 1.2 (P1.2).

I²C1 Serial Clock (SCL1).

PWM Output 0 (PWM0).

Input to PLA Element 6 (PLAI6).

Ball D3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

D4

D5

D6

P1.3/SDA1/PWM1/PLAI7

P1.1/SOUT1/COMOUT3/PLAI5

AIN3/PADC1P

I/O

AI

Digital Input/Output Port 1.3 (P1.3).

I²C1 Serial Data (SDA1).

PWM Output 1 (PWM1).

Input to PLA Element 7 (PLAI7).

Ball D4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Digital Input/Output Port 1.1 (P1.1).

UART Channel 1 (UART1) Output (SOUT1).

Comparator 3 Output (COMOUT3)

Input to PLA Element 5 (PLAI5).

Ball D5 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

Analog Input 3 (AIN3).

PGA Channel 1 Positive (PADC1P).

Analog Input 0.

Analog Input 10 (AIN10).

Comparator 1 V_EPositive (COM1P).

3.3 V GPIO Supply.

Ground for Digital Inputs/Outputs.

Digital Input/Output Port 1.4 (P1.4).

SPI1 Clock (SCLK1).

D7

D8

AIN0

AIN10/COM1P

AI

E1

E2

E3

IOVDD0

IOGND

P1.4/SCLK1/PWM2/PLAO10

S

I/O

PWM Output 2 (PWM2).

Output of PLA Element 10 (PLAO10).

Ball E3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

E4

P1.7/IRQ1/CS1/PWM5/PLAO13

I/O

Digital Input/Output Port 1.7 (P1.7).

External Interrupt 1 (IRQ1).

SPI1 Chip Select (CS1).

PWM Output 5 (PWM5).

Output of PLA Element 13 (PLAO13).

Ball E4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

E5

E6

VDAC8/P5.0

AO/I/O Voltage DAC 8 Output (VDAC8).

Digital Input/Output Port 5.0 (P5.0).

AIN12/COM2P

AI

Analog Input 12 (AIN12).

Comparator 2 V_EPositive (COM2P).

Analog Ground.

E7

E8

AGND

AVDD_REG

S

AO

2.5 V Analog Regulator Supply with 0.47 µF Decoupling Capacitor. Do not

use AVDD_REG to power external circuits.

Rev. 0 | Page 26 of 35

Data Sheet

ADuCM410

Pin No.

Mnemonic

Type¹

Description

F1

P1.5/MISO1/PWM3/PLAO11

I/O

Digital Input/Output Port 1.5 (P1.5).

SPI1 Master Input, Slave Output (MISO1).

PWM Output 3 (PWM3).

Output of PLA Element 11 (PLAO11).

Ball F1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

F2

P1.6/MOSI1/PWM4/PLAO12

I/O

Digital Input/Output Port 1.6 (P1.6).

SPI1 Master Out, Slave Input (MOSI1).

PWM Output 4 (PWM4).

Output of PLA Element 12 (PLAO12).

Ball F2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V

support. Note that 3.3 V is the default.

F3

F4

P0.7/IRQ4/SDA2/COMPDIN1/PLAO5

P3.2/PRTADDR2/PWMTRIP/PLAI14

I/O

Digital Input/Output Port 0.7 (P0.7).

External Interrupt 4 (IRQ4).

I²C2 Serial Data (SDA2).

Comparator 1 Digital Input for Three-State (COMPDIN1).

Output of PLA Element 5 (PLAO5).

Digital Input/Output Port 3.2 (P3.2).

MDIO Port Address Bit 2 (PRTADDR2).

PWM Trip (PWMTRIP).

Input to PLA Element 14 (PLAI14).

F5

F6

VDAC9/P5.1

AIN8/COM0P

AO/I/O Voltage DAC 9 Output (VDAC9).

Digital Input/Output Port 5.1 (P5.1).

AI

Analog Input 8 (AIN8).

Comparator 0 V_EPositive (COM0P).

F7

F8

ADCREFN

ADCREFP

AO/AI

Decoupling Capacitor Connection for ADC. Connect ADCREFN to AGND.

Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 µF

Decoupling Capacitor.

G1

G2

G3

P0.4/SCL0/SIN0/PLAO2

I/O

Digital Input/Output Port 0.4 (P0.4).

I²C0 Serial Clock (SCL0).

UART0 Input (SIN0).

Output of PLA Element 2 (PLAO2).

Digital Input/Output Port 0.5 (P0.5).

I²C0 Serial Data (SDA0).

P0.5/SDA0/SOUT0/PLAO3

P0.6/IRQ3/SCL2/COMPDIN0/PLAO4

UART0 Output (SOUT0).

Output of PLA Element 3 (PLAO3).

Digital Input/Output Port 0.6 (P0.6).

External Interrupt 3 (IRQ3).

I²C2 Serial Clock (SCL2).

Comparator 0 Digital Input for Three-State (COMPDIN0).

Output of PLA Element 4 (PLAO4).

Digital Input/Output Port 3.1 (P3.1).

MDIO Port Address Bit 1 (PRTADDR1).

PWM Synchronization (PWMSYNC).

Input to PLA Element 13 (PLAI13).

G4

P3.1/PRTADDR1/PWMSYNC/PLAI13

I/O

G5

G6

VDAC11/P5.3

AO/I/O Voltage DAC 11 Output (VDAC11).

Digital Input/Output Port 5.1 (P5.3).

AIN7/PADC23N/VDAC2

AI

Analog Input 7 (AIN7).

PGA Channel 2/PGA Channel 3 Negative (PADC23N).

Voltage DAC 2 Output (VDAC2).

Analog Input 1.

G7

G8

AIN1

AIN9/COM0N

AI

Analog Input 9 (AIN9).

Comparator 0 V_ENegative (COM0N).

Ground for Digital Inputs/Outputs.

H1

IOGND

S

Rev. 0 | Page 27 of 35

ADuCM410

Data Sheet

Pin No.

H2

H3

Mnemonic

Type¹

S

Description

DVDD

P3.6/MDIO

1.8 V/3.3 V Digital Power Supply.

Digital Input/Output Port 3.6 (P3.6).

MDIO Slave Data (MDIO).

I/O

H4

H5

H6

P3.5/MCK/SRDY1/PLAO27

P3.0/PRTADDR0/SRDY0/PLAI12

VDAC10/P5.2

I/O

Digital Input/Output Port 3.5 (P3.5).

MDIO Slave Clock (MCK).

SPI1 Ready (SRDY1).

Output of PLA Element 27 (PLAO27).

Digital Input/Output Port 3.0 (P3.0).

MDIO Port Address Bit 0 (PRTADDR0).

SPI 0 Ready (SRDY0).

Input to PLA Element 12 (PLAI12).

AO/I/O Voltage DAC 10 Output (VDAC10).

Digital Input/Output Port 5.2 (P5.2).

H7

H8

VDAC4

AIN13/COM2N

AO

AI

Voltage DAC 4 Output.

Analog Input 13 (AIN13).

Comparator 2 V_ENegative (COM2N).

¹S is supply, I/O is input/output, AO is analog output, I is digital input, and AI is analog input.

Rev. 0 | Page 28 of 35

Data Sheet

ADuCM410

THEORY OF OPERATION

The ADuCM410 is an on-chip system. The ADuCM410 is

mixed-signal microcontroller based on the Arm Cortex-M33

processor.

to, all register details and information about the various features

and operation of the power management unit, the Arm Cortex-

M33 processor, the ADC circuit, the flash controller, and the

SPI, I²C, and UART interfaces.

See the ADuCM410 hardware reference manual for full details

on the operation of the ADuCM410, including, but not limited

Rev. 0 | Page 29 of 35

ADuCM410

Data Sheet

RMS NOISE RESOLUTION OF ADC

The rms noise specifications for the ADC with different ADC

digital filter settings are described in Table 14.

settings. Peak-to-peak effective bit results are shown in

parentheses. RMS bits are calculated as follows:

The internal 2.5 V reference was used for all measurements.

For gain = 1, single-ended measurements with V_IN= 2 V was used.





Input Range

RMS Noise

log









For PGA gains ≥ 2, a differential input voltage was applied,

ensuring the PGA output to the ADC was always 2 V. For

example, for gain = 4, V_IN= 500 m V.

Peak-to-peak bits are calculated as follows:





Input Range

log



²







6.6 × RMS Noise

Table 15 shows the rms and peak-to-peak effective number of

bits based on the noise results in Table 14 for various PGA gain

Table 14. ADC RMS Noise

Update Rate Oversampling Ratio

RMS Noise (μV), PGA Output Voltage = 2 V for All Settings

Gain = 4 Gain = 6 Gain = 8 Gain = 10

Not applicable Not applicable Not applicable Not applicable Not applicable

30.8 17.4 11.9 7.5 5.2

Not applicable Not applicable Not applicable Not applicable Not applicable

(Hz)

(OSR)

Gain = 1

81.3

32.44

20.15

Gain = 2

2,000,000

50,000

20,000

5000

1

8

32

16

8

Not applicable 13.4

Not applicable 15.8

10.0

11.47

11.5

12.7

9.96

10.6

10.78

11.4

5000

Table 15. ADC Effective Bits, Based on RMS Noise (Peak-to-Peak Effective Bits in Parenthesis)

Update Rate (Hz) Sinc3 OSR Gain = 1 Gain = 2 Gain = 4 Gain = 6

14.9 (12.18 p-p) Not applicable Not applicable Not applicable

Gain = 8

Gain = 10

2,000,000

50,000

20,000

5000

1

Not applicable

15.5 (12.8 p-p)

Not applicable

14.5 (11.8 p-p)

8

16 (13.5 p-p)

15.3 (12.6 p-p) 15.1 (12.4 p-p) 15.1 (12.37 p-p) 15.3 (12.6 p-p)

Not applicable Not applicable Not applicable Not applicable

15.9 (13.2 p-p) 15.15 (12.4 p-p) 14.9 (12.2 p-p)

15.73 (13 p-p) 15 (12.27 p-p)

32

16

8

16 (14.19 p-p)

Not applicable

16 (13.78 p-p)

16 (13.54 p-p)

5000

14.85 (12.1 p-p) 14.4 (11.7 p-p)

Rev. 0 | Page 30 of 35

Data Sheet

ADuCM410

APPLICATIONS INFORMATION

In both Figure 16 and Figure 17, a large value (10 μF) reservoir

capacitor is connected to DVDD, and a separate 10 μF

capacitor is connected to AVDD. In addition, local small value

(0.1 μF) capacitors are located at each AVDD, IOVDD0,

IOVDD1, and DVDD pin of the chip. Include all

recommended capacitors shown, and ensure that the smaller

capacitors are close to each supply pin with trace lengths as

short as possible. Connect the ground terminal of each of these

capacitors directly to the underlying ground plane.

POWER SUPPLIES

The ADuCM410 operational power supply voltage range is

2.85 V to 3.6 V for AVDD and IOVDD0.

IOVDD1 can be 1.2 V, 1.8 V, or the same as IOVDD0. The

DVDD range is 1.8 V to 3.6 V.

Separate analog (AVDD) and digital power supply pins

(IOVDD1 and DVDD) allow AVDD to be kept relatively free

of noisy digital signals often present in the system DVDD line.

In this mode, the ADuCM410 can also operate with split

supplies. That is, the device can use different voltage levels for

each supply (see Table 1). A typical split supply configuration is

shown in Figure 16.

The analog and digital ground pins on the ADuCM410 must be

referenced to the same system ground reference point.

POWER-UP REQUIREMENTS

Figure 18 and Figure 19 show the power-up requirements for

DVDD and AVDD. Figure 20 shows the power-up requirement

for IOVDD0 if no external pull-up is applied to the

P2.3/BM/PLAI10 pin.

DIGITAL SUPPLY

ANALOG SUPPLY

3.3V

10µF

ADuCM410

AVDD

DVDD

0.1µF

10µF

0.1µF

3.6

IOVDD0

1

GND

REF

AGND

IOVDD1

DGND

1.8V

AFTER 50ms DVDD MUST

STAY ABOVE 1.7V INCLUDING

NOISE EXCURSIONS

1

1.8

1.7

GND

IS A COMMON GROUND BETWEEN AGND AND DGND.

REF

Figure 16. External Multiple Supply Connections

As an alternative to providing two separate power supplies, the

user can reduce noise on AVDD by placing a small series

resistor and/or ferrite bead between AVDD and DVDD, and

then decouple AVDD separately to ground. An example of this

configuration is shown in Figure 17. With this configuration,

other analog circuitry (such as op amps and voltage reference)

can be powered from the AVDD supply line as well.

50ms MIN

DVDD MUST BE ABOVE

1.8V FOR AT LEAST 50ms

TO COMPLETE POR

1.6

TIME (Not to Scale)

Figure 18. DVDD Power-Up Requirements

25ms

BEAD

DVDD

1.6V

3.3V

10µF

AVDD

ADuCM410

2.85V

1.6V

AVDD

DVDD

0.1µF

10µF

0.1µF

IOVDD0

0.1µF

1

GND

AFTER DVDD RISES

REF

LDO

1.8V

ABOVE 1.6V

AGND

(POR THRESHOLD),

AVDD MUST REACH

2.85V (min.) WITHIN 25ms.

OTHERWISE, RESET ADC

IOVDD1

DGND

1

AND VDACs IN SOFTWARE .

1

GND

IS A COMMON GROUND BETWEEN AGND AND DGND.

REF

Figure 17. External Single-Supply Connections

TIME

DETAILS IN HARDWARE REFERENCE MANUAL.

1

Figure 19. AVDD Power-Up Requirements

Rev. 0 | Page 31 of 35

ADuCM410

Data Sheet

25ms

There are three digital supply balls, IOVDD0, IOVDD1, and

DVDD. Decouple these balls with a 0.1 μF capacitor placed as

near as possible to each of the three balls and their associated

ground balls (DGND and AGND, respectively). In addition,

place a 10 ꢀF capacitor near these balls. For DVDD, to improve

noise reduction, place a ferrite bead in series with a 10 ꢀF

capacitor to DGND.

DVDD

IOVDD0

2.85V

1.6V

Similarly, the analog supply pin (AVDD) requires a 0.1 μF

capacitor placed as near as possible to each ball and its associated

AGND ball. Also place a 10 ꢀF capacitor near these balls.

The ADC reference requires a 4.7 ꢀF capacitor be placed

between ADCREFP and ADCREFN and located as near as

possible to each ball. ADCREFN must be connected directly to

AGND. The ADuCM410 contains two internal regulators.

These regulators require external decoupling capacitors. The

DVDD_REG and AVDD_REG balls each require a 0.47 μF

capacitor to DGND and AGND, respectively. Take care in the

layout to ensure that currents flowing from the ground end of

each decoupling capacitor to its associated ground ball share as

little track as possible with other ground currents on the PCB.

TIME

Figure 20. IOVDD0 Power-Up Requirement, No External Pull-Up

RECOMMENDED CIRCUIT AND COMPONENT

VALUES

Figure 21 shows a typical connection diagram for the ADuCM410.

Adequately decouple the supplies and regulators with

capacitors connected between the AVDD_REG, DVDD_REG,

and IOVDDx balls and their associated ground balls (AGND

and DGND). Table 12 and Table 13 indicate which ground

balls are paired with which supply balls.

Rev. 0 | Page 32 of 35

Data Sheet

ADuCM410

0.47µF

IOVDD0

10kΩ

RESET

IOVDD0

10kΩ

ADuCM410

P2.3/BM/PLAI10

P1.0/SIN1/COMOUT2/PLAI4

SWCLK

P1.1/SOUT1/COMOUT3/PLAI5

SWDIO

0.47µF

0.1µF

4.7µF

RESET

GND

RESET

SWDIO

Tx

SWCLK

Rx

NC

IOVDD0

AVDD

LT3022EMSE

VIN

IN

OUT

IOVDD1

0.1µF

10µF

10kΩ

0.1µF

10µF

0.1µF

10µF

PGND

AVDD

ADJ/SENSE

AGND

10µF

ADP7104ARDZ-3.3

AVDD

VIN

VOUT

PG

10kΩ

10µF

0.1µF

10µF

0.1µF

10µF

EN/UVLO

SENSE/ADJ

GND

Figure 21. Recommended Circuit and Component Values (ADuCM410, LT3022EMSE, and ADP7104ARDZ-3.3)

Rev. 0 | Page 33 of 35

ADuCM410

Data Sheet

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

A1 BALL

CORNER

A1 BALL

CORNER

9

8

7

6

5

3

1

4

2

A

B

C

D

E

F

4.00 REF

SQ

0.50

BSC

G

H

J

TOP VIEW

BOTTOM VIEW

DETAIL A

0.50

REF

0.69

0.64

0.59

DETAIL A

0.26

0.21

0.16

0.91

0.85

0.79

SIDE VIEW

0.35

0.30

0.25

SEATING

PLANE

COPLANARITY

0.08

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-195-AB

Figure 22. 81-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-81-6)

Dimensions shown in millimeters

3.50

3.46 SQ

3.42

8

7

6

5

4

3

2

1

A

BALL A1

IDENTIFIER

B

C

D

E

F

2.80

REF

G

H

0.40

BSC

TOP VIEW

BOTTOM VIEW

(BALL SIDE UP)

(BALL SIDE DOWN)

0.330

0.300

0.270

2.80 REF

0.560

0.500

0.440

END VIEW

COPLANARITY

0.05

0.300

0.260

0.220

SEATING

PLANE

0.230

0.200

0.170

Figure 23. 64-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-64-2)

Dimensions shown in millimeters

Rev. 0 | Page 34 of 35

Data Sheet

ADuCM410

ORDERING GUIDE

Model^{1, 2}

Temperature Range

−40°C to +105°C

Package Description

Package Option

BC-81-6

ADuCM410BBCZ

81-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

64-Ball Wafer Level Chip Scale Package [WLCSP]

BGA Evaluation Board and Quick Start Development System

WLCSP Evaluation Board and Quick Start Development System

ADuCM410BBCZ-RL7

ADuCM410BCBZ-RL7

EVAL-ADUCM410QSPZ

EVAL-ADUCM410QSP1Z

CB-64-2

¹Z = RoHS Compliant Part.

²CSP_BGA package uses ultralow alpha (ULA) molding compounds.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D20321-9/20(0)

Rev. 0 | Page 35 of 35


型号：	ADUCM410BBCZ-RL7
厂家：	ADI
描述：	Precision Analog Microcontroller, 16-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 微控制器
文件：	总35页 (文件大小：836K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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