ADUM1251 [ADI]
Hot Swappable Dual I2C Isolators; 可热插拔的双I2C隔离器
| 型号： | ADUM1251 |
| 厂家： | 
ADI |
| 描述： | Hot Swappable Dual I2C Isolators |
| 文件： | 总12页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Swappable Dual I2C Isolators
ADuM1250/ADuM1251
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Bidirectional I2C communication
Open-drain interfaces
Suitable for hot swap applications
30 mA current sink capability
1000 kHz operation
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
8
7
6
5
V
DD2
V
1
2
3
4
DD1
SDA
SCL
GND
SDA
SCL
1
1
1
2
2
3.0 V to 5.5 V supply/logic levels
8-lead SOIC lead-free package
GND
2
Figure 1. ADuM1250 Functional Block Diagram
High temperature operation: 105°C
Safety and regulatory approvals
UL recognition
DECODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
8
7
6
5
V
DD2
V
1
2
3
4
2500 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A (pending)
VDE Certificate of Conformity (pending)
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; DIN EN 60950: 2000
DD1
SDA
SDA
SCL
1
1
1
2
SCL
2
GND
GND
2
VIORM = 560 V peak
Figure 2. ADuM1251 Functional Block Diagram
APPLICATIONS
Isolated I2C, SMBus, or PMBus interfaces
Multilevel I2C interfaces
Power supplies
Networking
Power-over-Ethernet
Both the ADuM1250 and ADuM1251 contain hot swap
circuitry to prevent glitching data when an unpowered card is
inserted onto an active bus.
GENERAL DESCRIPTION
The ADuM1250/ADuM12511 are hot swappable digital
isolators with non latching bidirectional communication
channels compatible with I2C interfaces. This eliminates the
need for splitting I2C signals into separate transmit and receive
signals for use with standalone optocouplers.
These isolators are based on iCoupler® chip scale transformer
technology from Analog Devices, Inc. iCoupler is a magnetic
isolation technology with functional, performance, size, and
power consumption advantages as compared to optocouplers.
With the ADuM1250/ADuM1251, iCoupler channels can be
integrated with semiconductor circuitry, which enables a
complete isolated I2C interface to be provided in a small
form factor.
The ADuM1250 provides two bidirectional channels
supporting a complete isolated I2C interface. The ADuM1251
provides one bidirectional channel and one unidirectional
channel for those applications where a bidirectional clock is not
required.
1 Protected by U.S. Patents 5,952,849 and 6,873,065. Other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADuM1250/ADuM1251
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Test Conditions..................................................................................9
Application Notes........................................................................... 10
Functional Description.............................................................. 10
Startup.......................................................................................... 10
Typical Application Diagram.................................................... 11
Magnetic Field Immunity............................................................. 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Package Characteristics ............................................................... 5
Regulatory Information............................................................... 5
Insulation and Safety-Related Specifications............................ 5
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics .............................................................................. 6
Recommended Operating Conditions ...................................... 6
REVISION HISTORY
10/06—Revision 0: Initial Version 0
Rev. 0 | Page 2 of 12
ADuM1250/ADuM1251
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DC Specifications
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit Test Conditions
ADuM1250
Input Supply Current, Side 1, 5 V
Input Supply Current, Side 2, 5 V
Input Supply Current, Side 1, 3.3 V
Input Supply Current, Side 2, 3.3 V
ADuM1251
IDD1
IDD2
IDD1
IDD2
2.8
2.7
1.9
1.7
5.0
5.0
3.0
3.0
mA
mA
mA
mA
VDD1 = 5 V
VDD2 = 5 V
VDD1 = 3.3 V
VDD2 = 3.3 V
Input Supply Current, Side 1, 5 V
Input Supply Current, Side 2, 5 V
Input Supply Current, Side 1, 3.3 V
Input Supply Current, Side 2, 3.3V
LEAKAGE CURRENTS
IDD1
IDD2
IDD1
IDD2
2.8
2.5
1.8
1.6
0.01
6.0
4.7
3.0
2.8
10
mA
mA
mA
mA
μA
VDD1 = 5 V
VDD2 = 5 V
VDD1 = 3.3 V
VDD2 = 3.3 V
ISDA1, ISDA2, ISCL1
,
VSDA1 = VDD1, VSDA2 = VDD2
,
ISCL2
VSCL1 = VDD1, VSCL2 = VDD2
SIDE 1 LOGIC LEVELS
Logic Input Threshold1
Logic Low Output Voltages
VSDA1T, VSCL1T
VSDA1OL, VSCL1OL
500
600
600
50
700
900
850
mV
mV
mV
mV
ISDA1 = ISCL1 = 3.0 mA
ISDA1 = ISCL1 = 0.5 mA
Input/Output Logic Low Level
Difference2
ΔVSDA1, ΔVSCL1
SIDE 2 LOGIC LEVELS
Logic Low Input Voltage
Logic High Input Voltage
Logic Low Output Voltage
1 VIL < 0.5 V, VIH > 0.7 V.
VSDA2IL, VSCL2IL
VSDA2IH, VSCL2IH
VSDA2OL, VSCL2OL
0.3 VDD2
400
V
V
mV
0.7 VDD2
ISDA2 = ISCL2 = 30 mA
2 ΔVS1 = VS1OL – VS1T. This is the minimum difference between the output logic low level and the input logic threshold within a given component. This ensures that there
is no possibility of the part latching up the bus to which it is connected.
Rev. 0 | Page 3 of 12
ADuM1250/ADuM1251
AC Specifications
All voltages are relative to their respective ground. All min/max specifications apply over the entire recommended operating range, unless
otherwise noted. All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 5 V, unless otherwise noted. Refer to Figure 5.
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
MAXIMUM FREQUENCY
OUTPUT FALL TIME
5 V Operation
1000
kHz
4.5 V ≤ VDD1,VDD2 ≤ 5.5 V, CL1 = 40 pF, R1 = 1.6 kΩ,
CL2 = 400 pF, R2 = 180 Ω
Side 1 Output (0.9 VDD1 to 0.9 V)
Side 2 Output (0.9 VDD2 to 0.1 VDD2
tf1
tf2
13
32
26
52
120
120
ns
ns
)
3 V Operation
3.0 V ≤ VDD1,VDD2 ≤ 3.6 V, CL1 = 40 pF, R1 = 1.0 kΩ,
CL2 = 400 pF, R2 = 120 Ω
Side 1 Output (0.9 VDD1 to 0.9 V)
tf1
tf2
13
32
32
61
120
120
ns
ns
Side 2 Output (0.9 VDD2 to 0.1 VDD2
)
PROPAGATION DELAY
5 V Operation
4.5 ≤ VDD1, VDD2 ≤ 5.5 V,
CL1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, Rising Edge1
Side 1-to-Side 2, Falling Edge2
Side 2-to-Side 1, Rising Edge3
Side 2-to-Side 1, Falling Edge4
3 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
95
130
ns
ns
ns
ns
162 275
31
85
70
155
3.0 V ≤ VDD1,VDD2 ≤ 3.6 V,
CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, Rising Edge1
Side 1-to-Side 2, Falling Edge2
Side 2-to-Side 1, Rising Edge3
Side 2-to-Side 1, Falling Edge4
PULSE WIDTH DISTORTION
5 V Operation
tPLH12
tPHL12
tPLH21
tPHL21
82
125
ns
ns
ns
ns
196 340
32 75
110 210
4.5 V ≤ VDD1, VDD2 ≤ 5.5 V,
C
L1 = CL2 = 0, R1 = 1.6 kΩ, R2 = 180 Ω
Side 1-to-Side 2, |tPLH12 − tPHL12
Side 2-to-Side 1, |tPLH21 − tPHL21
3 V Operation
|
|
PWD12
PWD21
67
54
145
85
ns
ns
3.0 V ≤ VDD1,VDD2 ≤ 3.6 V,
CL1 = CL2 = 0, R1 = 1.0 kΩ, R2 = 120 Ω
Side 1-to-Side 2, |tPLH12 − tPHL12
Side 2-to-Side 1, |tPLH21 − tPHL21
|
|
PWD12
PWD21
114 215
ns
ns
77
35
135
COMMON-MODE TRANSIENT
IMMUNITY5
|CMH|,
|CML|
25
kV/μs
1 tPLH12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.7 VDD2
2 tPHL12 propagation delay is measured from the Side 1 input logic threshold to an output value of 0.4 V.
3 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.7 VDD1
4 tPLH21 propagation delay is measured from the Side 2 input logic threshold to an output value of 0.9 V.
.
.
5 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
Rev. 0 | Page 4 of 12
ADuM1250/ADuM1251
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Symbol Min Typ Max Unit
Test Conditions
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance
RI-O
CI-O
CI
1012
1.0
4.0
46
Ω
pF
pF
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
θJCI
°C/W
Thermocouple located at center of package
underside
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
41
°C/W
1 The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1250/ADuM1251 has been approved by the following organizations:
Table 4.
UL
CSA (Pending)
VDE (Pending)
Recognized under 1577 Component
Approved under CSA Component Acceptance
Notice #5A
Certified according to DIN EN 60747-5-2
Recognition Program1
(VDE 0884 Part 2):2003-012
Basic insulation, 2500 V rms isolation rating Basic insulation per CSA 60950-1-03 and IEC
60950-1, 400 V rms (560 V peak) maximum
Basic insulation,400 V rms (560 V peak)
maximum working voltage
working voltage
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL1577, each device is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(current leakage detection limit = 5 μA).
2 In accordance with DIN EN 60747-5-2, each device is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second
(partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter
Symbol Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
4.90 min
V rms 1 minute duration
L(I01)
L(I02)
mm
mm
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage)
4.01 min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
0.017 min mm
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
>175
IIIa
V
Rev. 0 | Page 5 of 12
ADuM1250/ADuM1251
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
The * marking on the package denotes DIN EN 60747-5-2 approval for a 560 V peak working voltage.
Table 6.
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
VIORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure (See also Figure 3)
Case Temperature
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
VPEAK
VPEAK
VPR
896
672
VPEAK
VTR
4000
VPEAK
TS
IS1
IS2
RS
150
160
170
>109
°C
Side 1 Current
Side 2 Current
Insulation Resistance at TS, VIO = 500 V
mA
mA
Ω
350
300
250
200
150
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN EN 60747-5-2
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter
Symbol
Min
−40
3.0
Max
Unit
°C
V
Operating Temperature
Supply Voltages1
TA
+105
5.5
5.5
40
400
3
VDD1, VDD2
VSDA1, VSCL1, VSDA2, VSCL2
CL1
CL2
ISDA1, ISCL1
ISDA2, ISCL2
Input/Output Signal Voltage
Capacitive Load, Side 1
Capacitive Load, Side 2
Static Output Loading, Side 1
Static Output Loading, Side 2
V
pF
pF
mA
mA
0.5
0.5
30
1 All voltages are relative to their respective ground. See the Application Notes section for data on immunity to external magnetic fields.
Rev. 0 | Page 6 of 12
ADuM1250/ADuM1251
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 8.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Symbol Min
Max
+150
+105
Unit
°C
°C
Storage Temperature
TST
TA
−55
−40
Ambient Operating
Temperature
Supply Voltages1
VDD1
,
−0.5
−0.5
−0.5
+7.0
V
VDD2
VSDA1
VSCL1
Input/Output Voltage1,
Side 1
,
,
VDD1 + 0.5
VDD2 + 0.5
V
ESD CAUTION
Input/Output Voltage1,
Side 2
VSDA2
VSCL2
V
Average Output
Current, per Pin2
Common-Mode
Transients3
IO
mA
kV/μs
−100 +100
1 All voltages are relative to their respective ground.
2 See Figure 3 for maximum rated current values for various temperatures.
3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating may cause latch-
up or permanent damage.
Rev. 0 | Page 7 of 12
ADuM1250/ADuM1251
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
V
DD2
DD1
ADuM1250/
ADuM1251
TOP VIEW
(Not to Scale)
SDA
SCL
GND
SDA
SCL
1
1
1
2
2
GND
2
Figure 4. ADuM1250/ADuM1251 Pin Configuration
Table 9. ADuM1250 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
VDD1
SDA1
SCL1
GND1
GND2
SCL2
SDA2
VDD2
Supply Voltage, 3.0 V to 5.5 V.
Data Input/Output, Side 1.
Clock Input/Output, Side 1.
Ground 1. Ground reference for isolator Side 1.
Ground 2. Isolated ground reference for isolator Side 2.
Clock Input/Output, Side 2.
Data Input/Output, Side 2.
Supply Voltage, 3.0 V to 5.5 V.
Table 10. ADuM1251 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
VDD1
SDA1
SCL1
GND1
GND2
SCL2
SDA2
VDD2
Supply Voltage, 3.0 V to 5.5 V.
Data Input/Output, Side 1.
Clock Input, Side 1.
Ground 1. Ground reference for isolator Side 1.
Ground 2. Isolated ground reference for isolator Side 2.
Clock Output, Side 2.
Data Input/Output, Side 2.
Supply Voltage, 3.0 V to 5.5 V.
Rev. 0 | Page 8 of 12
ADuM1250/ADuM1251
TEST CONDITIONS
V
DD2
V
DD1
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
8
7
6
5
1
2
3
4
R2
C
R2
R1
R1
L1
SDA
2
SDA
SCL
GND
1
1
1
SCL
2
C
L2
C
C
GND
L2
L1
2
Figure 5. Timing Test Diagram
Rev. 0 | Page 9 of 12
ADuM1250/ADuM1251
STARTUP
APPLICATION NOTES
Both the VDD1 and VDD2 supplies have an under voltage lockout
feature to prevent the signal channels from operating unless
certain criteria are met. This avoids the possibility of input logic
low signals from pulling down the I2C bus inadvertently during
power-up/power-down.
FUNCTIONAL DESCRIPTION
The ADuM1250/ADuM1251 interfaces on each side to a
bidirectional I2C signal. Internally, the I2C interface is split into
two unidirectional channels communicating in opposing
directions via a dedicated iCoupler isolation channel for each.
One channel (the bottom channel of each channel pair shown
in Figure 6) senses the voltage state of the Side 1 I2C pin and
transmits its state to its respective Side 2 I2C pin.
Both the Side 1 and the Side 2 I2C pins are designed to interface
to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low
on either causes the opposite pin to be pulled low enough to
comply with the logic low threshold requirements of other I2C
devices on the bus. Avoidance of I2C bus contention is ensured
by an input low threshold at SDA1 or SCL1 guaranteed to be at
least 50 mV less than the output low signal at the same pin. This
prevents an output logic low at Side 1 being transmitted back to
Side 2 and pulling down the I2C bus.
The two criteria that must be met in order for the signal
channels to be enabled are as follows:
•
•
Both supplies must be at least 2.5 V.
At least 40 μs must elapse after both supplies exceeded the
internal startup threshold of 2.0 V.
Until both of these criteria are met for both supplies, the
ADuM1250/ADuM1251 outputs are pulled high, ensuring a
startup that avoids any disturbances on the bus. Figure 7 and
Figure 8 illustrate the supply conditions for fast and slow input
supply slew rates.
Since the Side 2 logic levels/thresholds are standard I2C values,
multiple ADuM1250/ADuM1251 devices connected to a bus by
their Side 2 pins can communicate with each other and with
other devices having I2C compatibility1.
MINIMUM RECOMMENDED
OPERATING SUPPLY, 3.0V
SUPPLY VALID
MINIMUM VALID SUPPLY, 2.5V
INTERNAL STARTUP
THRESHOLD, 2.0V
However, since the Side 1 pin has a modified output level/input
threshold, this side of the ADuM1250/ADuM1251 can only
communicate with devices conforming to the I2C standard. In
other words, Side 2 of the ADuM1250/ADuM1251 is I2C-
compliant while Side 1 is only I2C-compatible.
40µs
Figure 7. Start-Up Condition, Supply Slew Rate >12.5 V/ms
The output logic low levels are independent of the VDD1 and
VDD2 voltages. The input logic low threshold at Side 1 is also
independent of VDD1. However, the input logic low threshold at
Side 2 is designed to be at 0.3 VDD2, consistent with I2C
requirements. The Side 1 and Side 2 pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
MIN. RECOMMENDED
OPERATING SUPPLY, 3.0V
MIN. VALID SUPPLY, 2.5V
SUPPLY VALID
INTERNAL STARTUP
THRESHOLD, 2.0V
V
DD2
V
DECODE
ENCODE
DECODE
ENCODE
ENCODE
DECODE
ENCODE
DECODE
8
7
6
5
1
2
3
4
DD1
R2
R2
SDA
2
40µs
SDA
SCL
GND
1
1
1
Figure 8. Start-Up Condition, Supply Slew Rate <12.5 V/ms
SCL
2
C
C
L
GND
L
2
Figure 6. ADuM1250 Block Diagram
1 Here a distinction is made between I2C compatibility and I2C compliance. I2C
compatibility refers to situations in which a component's logic levels do not
necessarily meet the requirements of the I2C specification but still allow the
component to communication with an I2C-compliant device. I2C compliance
refers to situations in which a component's logic levels meet the
requirements of the I2C specification.
Rev. 0 | Page 10 of 12
ADuM1250/ADuM1251
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
(with the worst-case polarity), it reduces the received pulse
from > 1.0 V to 0.75 V. Note that this is still well above the 0.5 V
sensing threshold of the decoder.
TYPICAL APPLICATION DIAGRAM
V
V
2
DD
8
7
6
5
ADuM1250
1
2
3
4
SDA
2
SDA
SCL
GND
2
2
I C BUS
1
1
1
SCL
GND
2
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances away from the
ADuM1250 transformers. Figure 11 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As shown in Figure 11, the ADuM1250 is extremely
immune and can be affected only by extremely large currents
operated at high frequency and very close to the component.
For the 1 MHz example, one would have to place a 0.5 kA
current 5 mm away from the ADuM1250 to affect the
component’s operation.
Figure 9. Typical Isolated I2C Interface using ADuM1250
MAGNETIC FIELD IMMUNITY
The ADuM1250 is extremely immune to external magnetic
fields. The limitation on the ADuM1250’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM1250 is examined because it represents
the most susceptible mode of operation.
1000
DISTANCE = 1m
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
100
10
DISTANCE = 100mm
V = (−dβ/dt) Πr2 ;n =1, 2, ...N
∑
n
1
where:
DISTANCE = 5mm
β is the magnetic flux density (gauss).
0.1
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
0.01
1k
10k
100k
1M
10M
100M
Given the geometry of the receiving coil in the ADuM1250 and
an imposed requirement that the induced voltage is at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 10.
MAGNETIC FIELD FREQUENCY (Hz)
Figure 11. Maximum Allowable Current for Various
Current-to-ADuM1250 Spacings
Note that at combinations of strong magnetic fields and high
frequencies, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
threshold of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
100
10
1
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 10. Maximum Allowable External Magnetic Flux Density
Rev. 0 | Page 11 of 12
ADuM1250/ADuM1251
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 12. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Number
of Inputs,
Number
of Inputs,
Maximum
Data Rate
(Mbps)
Maximum
Propagation
Delay (ns)
Temperature
Range
Package
Description
Package
Option
Model
V
2
2
2
2
DD1 Side
V
2
2
1
1
DD2 Side
ADuM1250ARZ1
ADuM1250ARZ-RL71
ADuM1251ARZ1
ADuM1251ARZ-RL71
1
1
1
1
150
150
150
150
−40°C to +105°C 8-Lead SOIC_N R-8
−40°C to +105°C 8-Lead SOIC_N R-8
−40°C to +105°C 8-Lead SOIC_N R-8
−40°C to +105°C 8-Lead SOIC_N R-8
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06113-0-10/06(0)
Rev. 0 | Page 12 of 12
相关型号：
©2020 ICPDF网 联系我们和版权申明