ADUM1301BRW [ADI]
Triple-Channel Digital Isolators; 三通道数字隔离器
| 型号： | ADUM1301BRW |
| 厂家： | 
ADI |
| 描述： | Triple-Channel Digital Isolators |
| 文件： | 总20页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Triple-Channel Digital Isolators
ADuM1300/ADuM1301
GENERAL DESCRIPTION
FEATURES
Low power operation
5 V operation
The ADuM130x are 3-channel digital isolators based on Analog
Devices’ iCoupler® technology. Combining high speed CMOS
and monolithic transformer technology, these isolation compo-
nents provide outstanding performance characteristics superior
to alternatives such as optocoupler devices.
1.2 mA per channel max @ 0 Mbps to 2 Mbps
3.5 mA per channel max @ 10 Mbps
32 mA per channel max @ 90 Mbps
3 V operation
0.8 mA per channel max @ 0 Mbps to 2 Mbps
2.2 mA per channel max @ 10 Mbps
20 mA per channel max @ 90 Mbps
Bidirectional communication
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with
optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discretes
is eliminated with these iCoupler products. Furthermore,
iCoupler devices consume one-tenth to one-sixth the power of
optocouplers at comparable signal data rates.
3 V/5 V level translation
High temperature operation: 105°C
High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics
2 ns max pulse-width distortion
2 ns max channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply
voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In
addition, the ADuM130x provides low pulse-width distortion
(<2 ns for CRW grade) and tight channel-to-channel matching
(<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that
ensures dc correctness in the absence of input logic transitions
and during power-up/power-down conditions.
Wide body 16-lead SOIC package, Pb-free models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000
VIORM = 560 V peak
APPLICATIONS
General-purpose multichannel isolation
SPI® interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
FUNCTIONAL BLOCK DIAGRAMS
V
1
2
3
4
5
6
7
8
16
V
V
1
16
V
DD2
DD1
DD2
DD1
GND
V
15 GND
GND
2
3
4
5
6
7
8
15 GND
1
2
1
IA
IB
2
ENCODE
ENCODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
V
V
14
13
12
V
V
V
14
13
12
V
V
V
OA
OB
IC
IA
IB
IC
OA
OB
OC
V
V
V
OC
NC
11 NC
NC
NC
11 NC
V
10
9
V
OR V
E2
10
9
V
E1
E2
GND
GND
2
GND
GND
1
1
2
Figure 2. ADuM1301 Functional Block Diagram
Figure 1. ADuM1300 Functional Block Diagram
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADuM1300/ADuM1301
TABLE OF CONTENTS
Specifications..................................................................................... 3
ESD Caution................................................................................ 12
Pin Configurations and Pin Function Descriptions.................. 13
Typical Performance Characteristics ........................................... 14
Application Information................................................................ 16
PC Board Layout ........................................................................ 16
Propagation Delay-Related Parameters................................... 16
DC Correctness and Magnetic Field Immunity........................... 16
Power Consumption .................................................................. 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 18
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation
Characteristics ............................................................................ 11
Recommended Operation Conditions .................................... 11
Absolute Maximum Ratings.......................................................... 12
REVISION HISTORY
6/04—Data Sheet Changed from Rev. B to Rev. C.
Changes to Format .............................................................Universal
Changes to Features.......................................................................... 1
Changes to Electrical Characteristics—5 V Operation ............... 3
Changes to Electrical Characteristics—3 V Operation ............... 5
Changes to Electrical Characteristics—Mixed 5 V/3 V or
3 V/5 V Operation ............................................................................ 7
Changes to Ordering Guide .......................................................... 18
5/04—Data Sheet Changed from Rev. A to Rev. B.
Changes to the Format.......................................................Universal
Changes to the Features................................................................... 1
Changes to Table 7 and Table 8..................................................... 14
Changes to Table 9.......................................................................... 15
Changes to the DC Correctness and Magnetic Field Immunity
Section.............................................................................................. 19
Changes to the Power Consumption Section ............................. 20
Changes to the Ordering Guide.................................................... 21
9/03—Data Sheet Changed from Rev. 0 to Rev. A.
Edits to Regulatory Information................................................... 13
Edits to Absolute Maximum Ratings ........................................... 15
Deleted the Package Branding Information................................ 16
Rev. C | Page 2 of 20
ADuM1300/ADuM1301
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION1
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-
wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V.
Table 1.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1300, Total Supply Current, Three Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.50 0.53 mA
0.19 0.21 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.6
0.7
2.5 mA
1.0 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
6.5
1.9
8.1 mA
2.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
57
16
77
18
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1301, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.3
1.0
2.1 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
5.0
3.4
6.2 mA
4.2 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
43
29
57
37
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH
–10
2.0
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC ≤ VDD1 or VDD2
0 ≤ VE1, VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.8
V
V
V
V
V
V
,
VDD1, VDD2 – 0.1 5.0
VDD1, VDD2 – 0.4 4.8
VOAL, VOBL, VOCL 0.0
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
65
5
Pulse-Width Distortion, |tPLH – tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. C | Page 3 of 20
ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
PWD
32
5
50
3
ns
ns
5
|
ps/°C
ns
ns
tPSK
tPSKCD
15
3
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM130xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
27
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
18
Propagation Delay5
tPHL, tPLH
PWD
32
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
10
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic High Output8
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
tR/tF
|CMH|
2.5
35
ns
kV/µs
25
25
Common-Mode Transient Immunity at
Logic Low Output8
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.2
0.19
0.05
Mbps
mA/Mbps
mA/Mbps
Input Dynamic Supply Current, per Channel9
IDDI (D)
Output Dynamic Supply Current, per Channel9 IDDO (D)
1 All voltages are relative to their respective ground.
2 The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 17. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9
through Figure 12 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel
supply current for a given data rate.
Rev. C | Page 4 of 20
ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—3 V OPERATION1
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-
wise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V.
Table 2.
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM1300, Total Supply Current, Three Channels2
DC to 2 Mbps
IDDI (Q)
IDDO (Q)
0.26 0.31 mA
0.11 0.14 mA
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
0.9
0.4
1.7
0.7
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.4
1.1
4.9
1.6
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
31
8
48
13
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1301, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
0.7
0.6
1.4
0.9
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
2.6
1.8
3.7
2.5
mA
mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (90)
IDD2 (90)
24
16
36
23
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC,
IE1, IE2
VIH, VEH
VIL, VEL
VOAH, VOBH
VOCH
–10
1.6
+0.01 +10 µA
V
0 ≤ VIA, VIB, VIC ≤ VDD1 or VDD2
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
0.4
V
V
V
V
V
V
,
VDD1, VDD2 – 0.1 3.0
VDD1, VDD2 – 0.4 2.8
VOAL, VOBL, VOCL 0.0
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
0.1
0.04 0.1
0.2
0.4
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
75
5
Pulse-Width Distortion, |tPLH – tPHL
|
40
50
50
ns
ns
ns
Propagation Delay Skew6
Channel-to-Channel Matching7
tPSKCD/OD
Rev. C | Page 5 of 20
ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ Max Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width3
Maximum Data Rate4
Propagation Delay5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
PW
100 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
tPHL, tPLH
PWD
38
5
50
3
ns
ns
5
|
ps/°C
ns
ns
tPSK
tPSKCD
26
3
Channel-to-Channel Matching,
Codirectional Channels7
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM130xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
34
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
45
2
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
16
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
tPHZ, tPLH
tPZH, tPZL
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
|CMH|
25
25
35
kV/µs
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
|CML|
35
kV/µs
transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current, per Channel9
Output Dynamic Supply Current, per Channel9
IDDI (D)
IDDO (D)
0.10
0.03
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on
Page 17. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9
through Figure 12 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel
supply current for a given data rate.
Rev. C | Page 6 of 20
ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all min/max
specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at
TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
5 V/3 V Operation
IDDI (Q)
0.50
0.26
0.53 mA
0.31 mA
3 V/5 V Operation
Output Supply Current, per Channel, Quiescent
5 V/3 V Operation
3 V/5 V Operation
ADuM1300, Total Supply Current, Three Channels2
IDDO (Q)
0.11
0.19
0.14 mA
0.21 mA
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.6
0.9
2.5 mA
1.7 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2(Q)
0.4
0.7
0.7 mA
1.0 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
6.5
3.4
8.1 mA
4.9 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.1
1.9
1.6 mA
2.5 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (90)
57
31
77
48
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (90)
8
16
13
18
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
ADuM1301, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD1 (Q)
1.3
0.7
2.1 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (Q)
0.6
1.0
0.9 mA
1.4 mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
5.0
2.6
6.2 mA
3.7 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.8
3.4
2.5 mA
4.2 mA
5 MHz logic signal freq.
5 MHz logic signal freq.
Rev. C | Page 7 of 20
ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
IDD1 (90)
43
24
57
36
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
IDD2 (90)
16
29
23
37
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
Input Currents
IIA, IIB, IIC,
IE1, IE2
–10
+0.01
+10 µA
0 ≤ VIA,VIB, VIC ≤ VDD1 or VDD2
0 ≤ VE1,VE2 ≤ VDD1 or VDD2
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH, VEH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL, VEL
0.8
0.4
V
V
V
Logic High Output Voltages
VOAH, VOBH
VOCH
,
VDD1, VDD2
0.1
–
V
DD1/VDD2
IOx = –20 µA, VIx = VIxH
IOx = –4 mA, VIx = VIxH
VDD1
,
VDD1
/
V
VDD2 – 0.4
VDD2 – 0.2
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
IOx = 20 µA, VIx = VIxL
IOx = 400 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width3
Maximum Data Rate4
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
50
Propagation Delay5
tPHL, tPLH
PWD
tPSK
70
5
Pulse-Width Distortion, |tPLH – tPHL
Propagation Delay Skew6
Channel-to-Channel Matching7
ADuM130xBRW
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width3
Maximum Data Rate4
PW
100 ns
Mbps
ns
CL = 15 pF,CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
15
Propagation Delay5
tPHL, tPLH
PWD
35
5
50
3
5
Pulse-Width Distortion, |tPLH – tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
6
3
Channel-to-Channel Matching,
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
ADuM130xCRW
Minimum Pulse Width3
Maximum Data Rate4
PW
8.3
120
30
0.5
3
11.1 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
90
20
Propagation Delay5
tPHL, tPLH
PWD
40
2
5
Pulse-Width Distortion, |tPLH-tPHL
Change vs. Temperature
Propagation Delay Skew6
Channel-to-Channel Matching,
Codirectional Channels7
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
14
2
Channel-to-Channel Matching,
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels7
Rev. C | Page 8 of 20
ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
Output Enable Propagation Delay
(High Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient Immunity at
Logic High Output8
Common-Mode Transient Immunity at
Logic Low Output8
Refresh Rate
tPHZ, tPLH
6
6
8
8
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPZH, tPZL
tR/tf
3.0
2.5
35
ns
ns
kV/µs
|CMH|
|CML|
fr
25
25
VIx = VDD1/VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
35
kV/µs
transient magnitude = 800 V
5 V/3 V Operation
3 V/5 V Operation
1.2
1.1
Mbps
Mbps
Input Dynamic Supply Current, per Channel9 IDDI (D)
5 V/3 V Operation
0.19
0.10
mA/Mbps
mA/Mbps
3 V/5 V Operation
Output Dynamic Supply Current, per Channel9
IDDI (D)
5 V/3 V Operation
3 V/5 V Operation
0.03
0.05
mA/Mbps
mA/Mbps
1 All voltages are relative to their respective ground.
2 Supply current values for all three channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The
supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 17. See Figure 6
through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total IDD1 and IDD2
supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured
from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the
recommended operating conditions.
7 Co-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation
barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing
sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be
sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the
range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-
channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 17 for guidance on calculating the per-channel supply current for a
given data rate.
Rev. C | Page 9 of 20
ADuM1300/ADuM1301
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol
RI-O
CI-O
CI
θJCI
Min
Typ
1012
1.7
4.0
33
Max
Unit
Ω
pF
pF
°C/W
°C/W
Test Conditions
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance2
f = 1 MHz
IC Junction-to-Case Thermal Resistance, Side 1
IC Junction-to-Case Thermal Resistance, Side 2
Thermocouple located
at center of package
underside
θJCO
28
1 Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM130x have been approved by the organizations listed in Table 5.
Table 5.
UL
CSA
VDE
Recognized under 1577
Approved under CSA Component
Acceptance Notice #5A
Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-012
component recognition program1
Double insulation, 2500 V rms
isolation voltage
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
400 V rms maximum working voltage
Basic insulation, 560 V peak
Complies with DIN EN 60747-5-2 (VDE 0884 Part 2):2003-01,
DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000
Reinforced insulation, 560 V peak
File 205078
File E214100
File 2471900-4880-0001
1 In accordance with UL1577, each ADuM130x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 µA).
2 In accordance with DIN EN 60747-5-2, each ADuM130x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection
limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
V rms
1 minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
L(I01)
L(I02)
8.40 min mm
8.10 min mm
0.017 min mm
>175
IIIa
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
V
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. C | Page 10 of 20
ADuM1300/ADuM1301
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110, Table 1)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b1
I–IV
I–III
I–II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
V
IORM × 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VPR
896
V peak
V peak
V peak
V
IORM × 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
IORM × 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC
672
V
Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec)
VTR
4000
Safety-Limiting Values (Maximum value allowed in the event of a failure; also see Thermal
Derating Curve, Figure 3)
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS, VIO = 500 V
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits.
The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.
350
300
250
RECOMMENDED OPERATION CONDITIONS
SIDE #2
200
Table 8.
150
Parameter
Symbol Min Max Unit
TA –40 +105 °C
SIDE #1
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
100
50
0
VDD1, VDD2 2.7 5.5
1.0
V
ms
0
50
100
CASE TEMPERATURE (°C)
150
200
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting
Values with Case Temperature per DIN EN 60747-5-2
1 All voltages are relative to their respective ground.
See the DC Correctness and Magnetic Field Immunity section on Page 16
for information on immunity to external magnetic fields.
Rev. C | Page 11 of 20
ADuM1300/ADuM1301
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 9.
Parameter
Symbol
TST
TA
VDD1, VDD2
VIA, VIB, VIC, VE1, VE2
VOA, VOB, VOC
Min
–65
–40
–0.5
–0.5
–0.5
Max
Unit
°C
°C
V
V
V
Storage Temperature
Ambient Operating Temperature
Supply Voltages1
Input Voltage1, 2
Output Voltage1, 2
Average Output Current, Per Pin3
Side 1
+150
+105
+7.0
VDDI + 0.5
VDDO + 0.5
IO1
IO2
–23
–30
–100
+23
+30
+100
mA
mA
kV/µs
Side 2
Common-Mode Transients4
1 All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See PC Board Layout section.
3 See Figure 3 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or
permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Table 10. Truth Table (Positive Logic)
VIX Input1
VEX Input2 VDDI State1 VDDO State1 VOX Output1 Notes
H
L
X
X
H or NC
H or NC
L
Powered
Powered
Powered
Powered
Powered
Powered
H
L
Z
H
H or NC
Unpowered Powered
Outputs return to the input state within 1 µs of VDDI power restora-
tion.
X
X
L
X
Unpowered Powered
Z
Powered
Unpowered Indeterminate Outputs return to the input state within 1 µs of VDDO power restora-
tion, if VEX state is H or NC. Outputs returns to high impedance state
within 8 ns of VDDO power restoration, if VEX state is L.
1 VIX and VOX refer to the input and output signals of a given channel (A, B, or C). VEX refers to the output enable signal on the same side as the VOX outputs. VDDI and VDDO
refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEX to an external logic high or low is recommended.
Rev. C | Page 12 of 20
ADuM1300/ADuM1301
PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS
V
V
V
V
DD2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD1
DD2
DD1
*GND
V
GND *
2
*GND
V
GND *
2
1
1
ADuM1300
TOP VIEW
(Not to Scale)
ADuM1301
TOP VIEW
(Not to Scale)
V
V
IA
IB
IC
OA
IA
IB
OA
V
V
V
V
V
OB
OB
V
V
V
IC
OC
OC
NC
NC
NC
NC
NC
V
V
V
E2
E1
*GND
E2
*GND
GND *
2
GND *
2
1
1
NC = NO CONNECT
NC = NO CONNECT
Figure 4. ADuM1300 Pin Configuration
Figure 5. ADuM1301 Pin Configuration
*
Pins 2 and 8 are internally connected. Connecting both to GND1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND2 is recommended.
Output enable Pin 10 on the ADuM1300 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1301 may be left
disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1301) and Pin 10 (for both models) to an external logic high or
low is recommended.
Table 11. ADuM1300 Pin Function Descriptions
Table 12. ADuM1301 Pin Function Descriptions
Pin
Pin
No. Mnemonic Function
No. Mnemonic Function
1
VDD1
Supply Voltage for Isolator Side 1, 2.7 V to
5.5 V.
1
VDD1
Supply Voltage for Isolator Side 1, 2.7 V to
5.5 V.
2
3
4
5
6
7
8
9
GND1
VIA
VIB
VIC
NC
NC
GND1
GND2
Ground 1. Ground reference for isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
No Connect.
No Connect.
Ground 1. Ground Reference for Isolator Side 1.
Ground 2. Ground Reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA, VOB,
and VOC outputs are enabled when VE2 ishigh or
disconnected. VOA, VOB, and VOC outputs are dis-
abled when VE2 is low. In noisy environments,
connecting VE2 to an external logic high or low is
recommended.
No Connect.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground Reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to
5.5 V.
2
3
4
5
6
7
GND1
VIA
VIB
VOC
NC
VE1
Ground 1. Ground Reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
No Connect.
Output Enable 1. Active high logic input. VOC out-
put is enabled when VE1 ishigh or disconnected.
VOC is disabled when VE1 is low. In noisy environ-
ments, connecting to VE1 to an external logic high
or low is recommended.
Ground 1. Ground Reference for Isolator Side 1.
Ground 2. Ground Reference for Isolator Side 2.
Output Enable 2. Active high logic input. VOA and
VOB outputs are enabled when VE2 ishigh or dis-
connected. VOA and VOB outputs are disabled
when VE2 is low. In noisy environments, connect-
ing VE2 to an external logic high or low is recom-
mended.
No Connect.
Logic Input C.
Logic Output B.
Logic Output A.
10 VE2
8
9
GND1
GND2
10 VE2
11 NC
12 VOC
13 VOB
14 VOA
15 GND2
16 VDD2
11 NC
12 VIC
13 VOB
14 VOA
15 GND2
16 VDD2
Ground 2. Ground Reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to
5.5 V.
Rev. C | Page 13 of 20
ADuM1300/ADuM1301
TYPICAL PERFORMANCE CHARACTERISTICS
20
18
16
14
60
50
40
30
20
10
0
12
5V
10
8
5V
6
3V
3V
4
2
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 6. Typical Input Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation
Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
6
5
4
3
16
14
12
10
8
5V
5V
6
4
2
3V
3V
1
2
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 7. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
10
9
50
45
40
35
30
8
7
6
5
25
5V
4
20
3V
15
5V
3
2
3V
10
5
1
0
0
0
20
40
60
80
100
0
20
40
60
80
100
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Output Supply Current per Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. C | Page 14 of 20
ADuM1300/ADuM1301
30
25
20
15
10
5
40
35
30
25
3V
5V
3V
5V
0
0
20
40
60
80
100
–50
–25
0
25
50
75
100
DATA RATE (Mbps)
TEMPERATURE (°C)
Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 13. Propagation Delay vs. Temperature, C Grade
Rev. C | Page 15 of 20
ADuM1300/ADuM1301
APPLICATION INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM130x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(Figure 14). Bypass capacitors are most conveniently connected
between Pins 1 and 2 for VDD1 and between Pins 15 and 16 for
VDD2. The capacitor value should be between 0.01 µF and 0.1 µF.
The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. Bypass-
ing between Pins 1 and 8 and between Pins 9 and 16 should also
be considered unless the ground pair on each package side is
connected close to the package.
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the trans-
former. The decoder is bistable and is therefore either set or
reset by the pulses, indicating input logic transitions. In the
absence of logic transitions of more than 2 µs at the input, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 10)
by the watchdog timer circuit.
V
GND
V
DD2
DD1
The ADuM130x is extremely immune to external magnetic
fields. The limitation on the ADuM130x’s magnetic field
immunity is set by the condition in which induced voltage in
the transformer’s receiving coil is sufficiently large to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this may occur. The 3 V operating
condition of the ADuM130x is examined because it represents
the most susceptible mode of operation.
GND
1
IA
IB
2
V
V
V
V
V
OA
OB
V
IC/OC
NC
OC/IC
NC
V
E2
GND
2
V
E1
GND
1
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally
affects all pins on a given component side. Failure to ensure this
could cause voltage differentials between pins exceeding the
device’s Absolute Maximum Ratings, thereby leading to latch-up
or permanent damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages
can be tolerated. The voltage induced across the receiving coil is
given by
2
V = (–dβ/dt)∑∏rn ; n = 1, 2,…, N
PROPAGATION DELAY-RELATED PARAMETERS
where:
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propaga-
tion delay to a logic low output may differ from the propagation
delay to a logic high.
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and
an imposed requirement that the induced voltage be at most
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
INPUT (V
)
50%
IX
tPLH
tPHL
OUTPUT (V
)
50%
OX
Figure 15. Propagation Delay Parameters
Pulse-width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM130x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM130x
components operating under the same conditions.
Rev. C | Page 16 of 20
ADuM1300/ADuM1301
100.000
10.000
1.000
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces
could induce sufficiently large error voltages to trigger the
thresholds of succeeding circuitry. Care should be taken in
the layout of such traces to avoid this possibility.
POWER CONSUMPTION
0.100
The supply current at a given channel of the ADuM130x isola-
tor is a function of the supply voltage, the channel’s data rate,
and the channel’s output load.
0.010
For each input channel, the supply current is given by
0.001
1k
10k
100k
1M
10M
100M
IDDI = IDDI (Q)
f ≤ 0.5fr
f > 0.5fr
MAGNETIC FIELD FREQUENCY (Hz)
Figure 16. Maximum Allowable External Magnetic Flux Density
IDDI = IDDI (D) × (2f – fr) + IDDI (Q)
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event were to occur during a transmitted
pulse (and was of the worst-case polarity), it would reduce the
received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V
sensing threshold of the decoder.
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
I
DDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f – fr) + IDDO (Q)
f > 0.5fr
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM130x transformers. Figure 17 expresses these allowable
current magnitudes as a function of frequency for selected
distances. As seen, the ADuM130x is extremely immune and
can be affected only by extremely large currents operated at
high frequency, very close to the component. For the 1 MHz
example, one would have to place a 0.5 kA current 5 mm away
from the ADuM130x to affect the component’s operation.
CL is output load capacitance (pF).
V
DDO is the output supply voltage (V).
f is the input logic signal frequency (MHz, half of the input data
rate, NRZ signaling).
fr is the input stage refresh rate (Mbps).
1000.00
IDDI (Q), IDDO (Q) are the specified input and output quiescent sup-
ply currents (mA).
DISTANCE = 1m
100.00
To calculate the total IDD1 and IDD2 supply current, the supply
currents for each input and output channel corresponding to
IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7
provide per-channel supply currents as a function of data rate
for an unloaded output condition. Figure 8 provides per-
channel supply current as a function of data rate for a 15 pF
output condition. Figure 9 through Figure 12 provide total
IDD1 and IDD2 supply current as a function of data rate for
ADuM1300/ADuM1301 channel configurations.
10.00
DISTANCE = 100mm
1.00
DISTANCE = 5mm
0.10
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 17. Maximum Allowable Current
for Various Current-to-ADuM130x Spacings
Rev. C | Page 17 of 20
ADuM1300/ADuM1301
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
× 45°
0.30 (0.0118)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 18. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (RW-16)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Number
Number
Maximum
Maximum
of Inputs, of Inputs, Data Rate Maximum Propagation
Pulse-Width
Distortion (ns)
Temperature Package
Model
VDD1 Side VDD2 Side (Mbps)
Delay, 5 V (ns)
Range (°C)
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
–40 to +105
Option1
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
ADuM1300ARW2
ADuM1300BRW2
ADuM1300CRW2
ADuM1300ARWZ2, 3
ADuM1300BRWZ2, 3
ADuM1300CRWZ2, 3
ADuM1301ARW2
ADuM1301BRW2
ADuM1301CRW2
ADuM1301ARWZ2, 3
ADuM1301BRWZ2, 3
ADuM1301CRWZ2, 3
3
3
3
3
3
3
2
2
2
3
3
3
0
0
0
0
0
0
1
1
1
0
0
0
1
100
50
32
100
50
32
40
3
2
40
3
2
10
90
1
10
90
1
10
90
1
10
90
100
50
32
100
50
32
40
3
2
40
3
2
1 RW-16 = 16-lead wide body SOIC.
2 Tape and reel are available. The addition of an “-RL” suffix designates a 13” (1,000 units) tape and reel option.
3 Z = Pb-free part.
Rev. C | Page 18 of 20
ADuM1300/ADuM1301
NOTES
Rev. C | Page 19 of 20
ADuM1300/ADuM1301
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.
C03787–0–6/04(C)
Rev. C | Page 20 of 20
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