ADUM1412ARW [ADI]
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| 型号： | ADUM1412ARW |
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ADI |
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Quad-Channel Digital Isolators
ADuM1410/ADuM1411/ADuM1412
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Low power operation
5 V operation
1
2
3
16
15
14
V
V
DD1
DD2
ADuM1410
GND
GND
1
2
1.3 mA per channel maximum @ 0 Mbps to 2 Mbps
4.0 mA per channel maximum @ 10 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps
1.8 mA per channel maximum @ 10 Mbps
Bidirectional communication
3 V/5 V level translation
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs
16-lead, RoHS-compliant, SOIC wide body package
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577
CSA component acceptance notice #5A
VDE certificate of conformity
V
V
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
V
V
V
V
IA
OA
OB
OC
OD
4
5
13
12
IB
V
IC
6
7
8
11
10
9
V
ID
DISABLE
GND
CTRL
2
GND
1
2
Figure 1. ADuM1410
1
16
V
V
DD1
DD2
ADuM1411
2
3
15
14
GND
GND
2
1
V
V
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
V
V
V
V
IA
OA
OB
OC
ID
4
5
13
12
IB
V
IC
6
7
8
11
10
9
V
OD
CTRL
GND
CTRL
2
1
GND
1
2
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Figure 2. ADuM1411
V
IORM = 560 V peak
TÜV approval: IEC/EN 60950-1
1
2
3
16
15
14
V
V
DD2
DD1
ADuM1412
GND
GND
1
2
APPLICATIONS
V
V
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
ENCODE
ENCODE
V
V
V
V
IA
OA
OB
IC
4
5
13
12
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers
Industrial field bus isolation
IB
V
V
OC
6
7
8
11
10
9
OD
ID
CTRL
GND
CTRL
2
1
GND
1
2
Figure 3. ADuM1412
devices consume one-tenth to one-sixth the power of optocou-
plers at comparable signal data rates.
GENERAL DESCRIPTION
The ADuM141x1 are four-channel digital isolators based on
Analog Devices, Inc. iCoupler® technology. Combining high
speed CMOS and monolithic air core transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives such as optocoupler devices.
The ADuM141x isolators provide four independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide) up to 10 Mbps. All models operate
with the supply voltage on either side ranging from 2.7 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. All products also have a default output control pin. This
allows the user to define the logic state the outputs are to adopt
in the absence of the input power. Unlike other optocoupler
alternatives, the ADuM141x isolators have a patented refresh
feature that ensures dc correctness in the absence of input logic
transitions and during power-up/power-down conditions.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with opto-
couplers. The usual concerns that arise with optocouplers, such
as uncertain current transfer ratios, nonlinear transfer functions,
and temperature and lifetime effects, are eliminated with the simple
iCoupler digital interfaces and stable performance characteristics.
The need for external drivers and other discrete components is
eliminated with these iCoupler products. Furthermore, iCoupler
1 Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2010 Analog Devices, Inc. All rights reserved.
ADuM1410/ADuM1411/ADuM1412
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 11
Absolute Maximum Ratings ......................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions......................... 13
Typical Performance Characteristics ........................................... 17
Applications Information.............................................................. 19
PC Board Layout ........................................................................ 19
Propagation Delay-Related Parameters................................... 19
DC Correctness and Magnetic Field Immunity........................... 19
Power Consumption .................................................................. 20
Insulation Lifetime..................................................................... 20
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3 V Operation................................ 5
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
Package Characteristics ............................................................. 10
Regulatory Information............................................................. 10
Insulation and Safety-Related Specifications.......................... 10
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics.......................................................... 11
REVISION HISTORY
11/10—Rev. G to Rev. H
2/07—Rev. E to Rev F
Added TÜV Approval to Features Section.................................... 1
Added TÜV Column, Table 5....................................................... 10
Added ADuM1410ARWZ ...............................................Universal
Updated Pin Name CTRL to CTRL2 Throughout ........................1
Changes to Ordering Guide.......................................................... 21
6/07—Rev. F to Rev. G
10/06—Rev. D to Rev. E
Updated VDE Certification Throughout ...................................... 1
Changes to Features and Applications........................................... 1
Changes to DC Specifications in Table 1....................................... 3
Changes to DC Specifications in Table 2....................................... 5
Changes to DC Specifications in Table 3....................................... 7
Changes to Regulatory Information Section .............................. 10
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 21
Added ADuM1411 and ADuM1412 ...............................Universal
Deleted ADuM1310...........................................................Universal
Changes to Features ..........................................................................1
Changes to Specifications Section...................................................3
Updated Outline Dimensions....................................................... 20
Changes to Ordering Guide.......................................................... 20
3/06—Rev. C to Rev. D
Added Note 1 and Changes to Figure 2..........................................1
Changes to Absolute Maximum Ratings..................................... 11
11/05—Rev. SpB to Rev. C: Initial Version
Rev. H | Page 2 of 24
ADuM1410/ADuM1411/ADuM1412
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground.
Table 1.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
IDDI (Q)
0.50
0.38
0.73
0.53
mA
mA
IDDO (Q)
ADuM1410, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
2.4
1.2
3.2
1.6
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
8.8
2.8
12
4.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1411, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
2.2
1.8
2.8
2.4
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
5.4
3.8
7.6
5.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1412, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current
IDD1 (Q), IDD2 (Q)
2.0
4.6
2.6
6.5
mA
DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Version Only)
VDD1 or VDD2 Supply Current
All Models
IDD1 (10), IDD2 (10)
mA
μA
5 MHz logic signal frequency
Input Currents
IIA, IIB, IIC,
IID, ICTRL1
−10
2.0
+0.01 +10
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2
0 V ≤ VDISABLE ≤ VDD1
,
,
ICTRL2, IDISABLE
VIH
VIL
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
V
V
V
V
V
V
V
0.8
VOAH, VOBH
,
(VDD1 or VDD2) − 0.1 5.0
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
VOCH, VODH
(VDD1 or VDD2)−0.4
4.8
0.0
Logic Low Output Voltages
VOAL, VOBL
,
0.1
0.1
0.4
VOCL, VODL
0.04
0.2
Rev. H | Page 3 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM141xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM141xBRWZ
PW
1000 ns
Mbps
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
20
tPHL, tPLH
PWD
tPSK
65
100
40
ns
ns
ns
ns
4
|
50
tPSKCD/OD
50
Minimum Pulse Width2
Maximum Data Rate3
PW
100
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
20
Propagation Delay4
tPHL, tPLH
PWD
30
5
50
5
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
tPSK
tPSKCD
30
5
ns
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity |CMH|
at Logic High Output7
Common-Mode Transient Immunity |CML|
at Logic Low Output7
tR/tF
2.5
35
ns
kV/μs
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
25
25
35
kV/μs
Refresh Rate
Input Enable Time8
Input Disable Time8
Input Dynamic Supply Current
per Channel9
Output Dynamic Supply Current
per Channel9
fr
1.2
Mbps
μs
μs
mA/
Mbps
tENABLE
tDISABLE
IDDI (D)
2.0
5.0
VIA, VIB, VIC, VID = 0 V or VDD1
VIA, VIB, VIC, VID = 0 V or VDD1
0.12
0.04
IDDO (D)
mA/
Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H | Page 4 of 24
ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter
Symbol
Min
Typ Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
IDDI (Q)
0.25 0.38
0.19 0.33
mA
mA
IDDO (Q)
ADuM1410, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
IDD2 (Q)
1.2
0.8
1.6
1.0
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
VDD2 Supply Current
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
4.5
1.4
6.5
1.8
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1411, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
IDD1 (Q)
IDD2 (Q)
1.0
0.9
1.9
1.7
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
VDD2 Supply Current
IDD1 (10)
IDD2 (10)
3.1
2.1
4.5
3.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1412, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 or VDD2 Supply Current
IDD1 (Q), IDD2 (Q)
1.0
2.6
1.8
3.8
mA
DC to 1 MHz logic signal
frequency
10 Mbps (BRWZ Version Only)
VDD1 or VDD2 Supply Current
All Models
IDD1 (10), IDD2 (10)
mA
μA
5 MHz logic signal frequency
Input Currents
IIA, IIB, IIC,
IID, ICTRL1
CTRL2, IDISABLE
−10
1.6
+0.01 +10
0 V ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2
0 V ≤ VDISABLE ≤ VDD1
,
,
I
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
VIL
V
V
V
V
V
V
V
0.4
VOAH, VOBH
,
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.4 2.8
0.0
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
V
OCH, VODH
Logic Low Output Voltages
VOAL, VOBL
,
0.1
0.04 0.1
0.2 0.4
V
OCL, VODL
Rev. H | Page 5 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter
Symbol
Min
Typ Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS
ADuM141xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM141xBRWZ
PW
1000
ns
CL = 15 pF, CMOS signal levels
1
20
Mbps CL = 15 pF, CMOS signal levels
tPHL, tPLH
PWD
tPSK
75
100
40
50
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
4
|
tPSKCD/OD
50
Minimum Pulse Width2
Maximum Data Rate3
PW
100
ns
CL = 15 pF, CMOS signal levels
10
20
Mbps CL = 15 pF, CMOS signal levels
ns
ns
ps/°C CL = 15 pF, CMOS signal levels
ns
ns
Propagation Delay4
tPHL, tPLH
PWD
40
5
60
5
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
|
tPSK
tPSKCD
30
5
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching,
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
Opposing-Directional Channels6
All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
tR/tF
|CMH|
2.5
35
ns
CL = 15 pF, CMOS signal levels
25
25
kV/μs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/μs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
|CML|
35
Refresh Rate
fr
1.1
Mbps
Input Enable Time8
Input Disable Time8
Input Dynamic Supply Current
per Channel9
tENABLE
tDISABLE
IDDI (D)
2.0
5.0
0.07
μs
μs
mA/
VIA, VIB, VIC, VID = 0 V or VDD1
VIA, VIB, VIC, VID = 0 V or VDD1
Mbps
Output Dynamic Supply Current
per Channel9
IDDO (D)
0.02
mA/
Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H | Page 6 of 24
ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 3.
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
IDDI (Q)
5 V/3 V Operation
3 V/5 V Operation
0.50
0.25
0.73 mA
0.38 mA
Output Supply Current per Channel,
Quiescent
IDDO (Q)
5 V/3 V Operation
3 V/5 V Operation
0.19
0.38
0.33 mA
0.53 mA
ADuM1410, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
IDD1 (Q)
2.4
1.2
3.2
1.6
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2 (Q)
0.8
1.2
1.0
1.6
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
8.6
3.4
11
6.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
IDD2 (10)
1.4
2.6
1.8
3.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1411, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
IDD1 (Q)
2.2
1.0
2.8
1.9
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2 (Q)
0.9
1.7
1.7
2.4
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
5 V/3 V Operation
IDD1 (10)
5.4
3.1
7.6
4.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
3 V/5 V Operation
Rev. H | Page 7 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter
VDD2 Supply Current
Symbol
Min
Typ
Max Unit
Test Conditions
IDD2 (10)
5 V/3 V Operation
3 V/5 V Operation
2.1
3.8
3.0
5.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
ADuM1412, Total Supply Current,
Four Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
IDD1 (Q)
2.0
1.0
2.6
1.8
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
IDD2 (Q)
1.0
2.0
1.8
2.6
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
3 V/5 V Operation
10 Mbps (BRWZ Version Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
All Models
IDD1 (10)
4.6
2.6
6.5
3.8
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD2 (10)
2.6
4.6
3.8
6.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
Input Currents
IIA, IIB, IIC, IID, −10
ICTRL1, ICTRL2
IDISABLE
+0.01
+10 μA
0 V ≤ VIA,VIB, VIC,VID ≤ VDD1 or VDD2
0 V ≤ VCTRL1,VCTRL2 ≤ VDD1 or VDD2
0 V ≤ VDISABLE ≤ VDD1
,
,
,
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIH
2.0
1.6
V
V
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
VIL
0.8
0.4
V
V
V
V
V
V
V
Logic High Output Voltages
VOAH, VOBH
VOCH, VODH
,
(VDD1 or VDD2) − 0.1 (VDD1 or VDD2)
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2
IOx = −20 μA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 μA, VIx = VIxL
IOx = 400 μA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.0
0.04
0.2
0.1
0.1
0.4
SWITCHING SPECIFICATIONS
ADuM141xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM141xBRWZ
PW
1000 ns
Mbps
100 ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
25
tPHL, tPLH
PWD
tPSK
70
4
|
40
50
50
ns
ns
ns
tPSKCD/OD
Minimum Pulse Width2
Maximum Data Rate3
PW
100 ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
10
25
Propagation Delay4
tPHL, tPLH
PWD
35
5
60
5
4
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew5
|
ns
ps/°C
ns
tPSK
30
Rev. H | Page 8 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter
Symbol
Min
Typ
Max Unit
Test Conditions
Channel-to-Channel Matching,
tPSKCD
5
ns
CL = 15 pF, CMOS signal levels
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
All Models
Output Rise/Fall Time (10% to 90%) tR/tF
5 V/3 V Operation
3 V/5 V Operation
CL = 15 pF, CMOS signal levels
2.5
2.5
35
ns
ns
kV/μs
Common-Mode Transient
|CMH|
25
25
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V, transient
magnitude = 800 V
Immunity at Logic High Output7
Common-Mode Transient
|CML|
fr
35
kV/μs
Immunity at Logic Low Output7
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Enable Time8
Input Disable Time8
Input Dynamic Supply Current
per Channel9
1.2
1.1
2.0
5.0
Mbps
Mbps
μs
tENABLE
tDISABLE
IDDI (D)
VIA, VIB, VIC, VID = 0 V or VDD1
VIA, VIB, VIC, VID = 0 V or VDD1
μs
5 V Operation
0.12
0.07
mA/
Mbps
mA/
3 V Operation
Mbps
Output Dynamic Supply Current
per Channel9
IDDO (D)
5 V Operation
0.04
0.02
mA/
Mbps
mA/
3 V Operation
Mbps
1 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14).
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H | Page 9 of 24
ADuM1410/ADuM1411/ADuM1412
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Symbol Min Typ Max Unit
Test Conditions
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
RI-O
CI-O
CI
1012
Ω
pF
pF
2.2
4.0
f = 1 MHz
IC Junction-to-Case Thermal Resistance
Side 1
Side 2
θJCI
θJCO
33
28
°C/W
°C/W
Thermocouple located at center of package underside
1 The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM141x have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for
recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
CSA
VDE
TÜV
Recognized Under 1577
Component Recognition
Program1
Approved under CSA
Component Acceptance
Notice #5A
Certified according to DIN V VDE V
Approved according to:
0884-10 (VDE V 0884-10): 2006-122 IEC 60950-1:2005 and
EN 60950-1:2006
Double/reinforced insulation,
2500 V rms isolation voltage
Basic insulation per CSA
60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak)
maximum working voltage.
Reinforced insulation, 560 V peak
3000 V rms reinforced isolation
at a 400 V rms working voltage.
3000 V rms basic isolation at a
600 V rms working voltage.
Reinforced insulation per
CSA 60950-1-03 and IEC
60950-1, 400 V rms (566 V
peak) maximum working
voltage.
File E214100
File 205078
File 2471900-4880-0001
Certificate B 10 03 56232 006
1 In accordance with UL 1577, each ADuM141x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM141x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection
limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Symbol Value
Unit
Conditions
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
2500
7.7
V rms
1-minute duration
L(I01)
L(I02)
mm min Measured from input terminals to output terminals,
shortest distance through air
mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum External Tracking (Creepage)
8.1
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017
>175
IIIa
mm min
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. H | Page 10 of 24
ADuM1410/ADuM1411/ADuM1412
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 7.
Description
Conditions
Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
I to IV
I to III
I to II
40/105/21
2
VIORM
VPR
560
1050
V peak
V peak
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2 VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
and Subgroup 3
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
896
672
V peak
V peak
Highest Allowable Overvoltage
Safety-Limiting Values
Transient overvoltage, tTR = 10 seconds
Maximum value allowed in the event of a failure;
see Figure 4
VTR
4000
V peak
Case Temperature
Side 1 Current
Side 2 Current
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
Insulation Resistance at TS
VIO = 500 V
RECOMMENDED OPERATING CONDITIONS
350
300
250
Table 8.
Parameter
Symbol
Min Max
Unit
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
TA
−40 +105 °C
V
DD1, VDD2 2.7
5.5
1.0
V
ms
SIDE #2
200
150
100
50
1 All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
SIDE #1
0
0
50
100
CASE TEMPERATURE (°C)
150
200
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. H | Page 11 of 24
ADuM1410/ADuM1411/ADuM1412
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 9.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Storage Temperature (TST) Range
Ambient Operating Temperature
−65°C to +150°C
−40°C to +105°C
(TA) Range
Supply Voltages (VDD1, VDD2
1
)
−0.5 V to +7.0 V
Input Voltages (VIA, VIB, VIC, VID, VCTRL1
,
−0.5 V to VDDI + 0.5 V
1, 2
ESD CAUTION
VCTRL2, VDISABLE
Output Voltages (VOA, VOB, VOC, VOD
Average Output Current per Pin3
)
1, 2
)
−0.5 V to VDDO + 0.5 V
Side 1 (IO1
Side 2 (IO2
Common-Mode Transients4
)
)
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/ꢀs to +100 kV/ꢀs
1
All voltages are relative to their respective ground.
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the PC Board Layout section.
3 See Figure 4 for maximum rated current values for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Table 10. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
565
V peak
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Basic Insulation
Reinforced Insulation
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. H | Page 12 of 24
ADuM1410/ADuM1411/ADuM1412
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
6
7
8
16
V
DD1
DD2
GND *
15 GND *
1
2
V
V
V
V
14
13
12
11
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
ADuM1410
TOP VIEW
(Not to Scale)
DISABLE
GND *
10 CTRL
2
9
GND *
2
1
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED. CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 5. ADuM1410 Pin Configuration
Table 11. ADuM1410 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VDD1
GND1
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
3
4
5
6
7
VIA
VIB
VIC
VID
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
DISABLE
Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state
determined by CTRL2.
8
GND1
GND2
CTRL2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and
VOD outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, VOC, and VOD outputs are low when
CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect.
9
10
11
12
13
14
15
VOD
VOC
VOB
VOA
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
GND2
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
16
VDD2
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
Rev. H | Page 13 of 24
ADuM1410/ADuM1411/ADuM1412
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
GND *
15 GND *
1
2
V
V
V
14
13
12
11
V
V
V
V
IA
IB
IC
OA
OB
OC
ID
ADuM1411
TOP VIEW
(Not to Scale)
V
OD
CTRL
10 CTRL
1
2
GND *
9
GND *
2
1
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED. CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 6. ADuM1411 Pin Configuration
Table 12. ADuM1411 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VDD1
GND1
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
3
4
5
6
7
VIA
VIB
VIC
VOD
CTRL1
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOD output is high
when CTRL1 is high or disconnected and VDD2 is off. VOD output is low when CTRL1 is low and VDD2 is off. When VDD2
power is on, this pin has no effect.
8
GND1
GND2
CTRL2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, and VOC
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL2 is
low and VDD1 is off. When VDD1 power is on, this pin has no effect.
9
10
11
12
13
14
15
VID
VOC
VOB
VOA
GND2
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
16
VDD2
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
Rev. H | Page 14 of 24
ADuM1410/ADuM1411/ADuM1412
V
1
2
3
4
5
6
7
8
16
V
DD2
DD1
GND *
15 GND *
1
2
V
V
14
13
12
11
V
V
V
V
IA
OA
OB
IC
ADuM1412
IB
TOP VIEW
(Not to Scale)
V
V
OC
OD
ID
CTRL
10 CTRL
2
1
GND *
9
GND *
2
1
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
1
CONNECTED. CONNECTING BOTH TO GND IS RECOMMENDED.
2
Figure 7. ADuM1412 Pin Configuration
Table 13. ADuM1412 Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VDD1
GND1
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
3
4
5
6
7
VIA
VIB
VOC
VOD
CTRL1
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOC and VOD
outputs are high when CTRL1 is high or disconnected and VDD2 is off. VOC and VOD outputs are low when CTRL1 is low
and VDD2 is off. When VDD2 power is on, this pin has no effect.
8
GND1
GND2
CTRL2
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA and VOB
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low
and VDD1 is off. When VDD1 power is on, this pin has no effect.
9
10
11
12
13
14
15
VID
VIC
VOB
VOA
GND2
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
16
VDD2
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
Rev. H | Page 15 of 24
ADuM1410/ADuM1411/ADuM1412
Table 14. Truth Table (Positive Logic)
VIx
CTRLX
VDISABLE VDDI
VDDO
VOx
Input1 Input2
State3
State4
State5
Output1 Description
H
L
X
X
X
L or NC Powered
L or NC Powered
Powered
Powered
Powered
H
L
H
Normal operation, data is high.
Normal operation, data is low.
Inputs disabled. Outputs are in the default state as determined
by CTRLX.
Inputs disabled. Outputs are in the default state as determined
by CTRLX.
H or NC
H
H
X
X
X
X
L
X
Powered
Powered
L
H or NC
Unpowered
H
Input unpowered. Outputs are in the default state as determined
by CTRLX.
Outputs return to input state within 1 μs of VDDI power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13)
for more details.
X
X
L
X
X
Unpowered
Powered
Powered
L
Input unpowered. Outputs are in the default state as determined
by CTRLX.
Outputs return to input state within 1 μs of VDDI power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13)
for more details.
Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 1 μs of VDDO power restoration.
See the pin function descriptions (Table 11, Table 12, and Table 13)
for more details.
X
Unpowered
Z
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
2 CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D).
3 Available only on ADuM1410.
4 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
5 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
Rev. H | Page 16 of 24
ADuM1410/ADuM1411/ADuM1412
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
10
8
1.5
6
5V
1.0
5V
3V
4
3V
0.5
2
0
0
0
2
4
6
8
10
0
2
4
6
8
10
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 8. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3 V Operation
Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
1.0
0.9
0.8
0.7
10
8
0.6
6
5V
0.5
0.4
0.3
4
5V
3V
0.2
2
0.1
0
3V
0
0
2
4
6
8
10
0
2
4
6
8
10
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 9. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
1.4
1.2
1.0
10
8
6
0.8
5V
0.6
0.4
4
5V
3V
2
0.2
3V
0
0
0
2
4
6
8
10
0
2
4
6
8
10
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 10. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. H | Page 17 of 24
ADuM1410/ADuM1411/ADuM1412
10
10
8
8
6
6
4
4
5V
3V
5V
2
2
3V
0
0
0
2
4
6
8
10
0
2
4
6
8
10
DATA RATE (Mbps)
DATA RATE (Mbps)
Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 15. Typical ADuM1412 VDD1 or VDD2 Supply Current vs.
Data Rate for 5 V and 3 V Operation
Rev. H | Page 18 of 24
ADuM1410/ADuM1411/ADuM1412
APPLICATIONS INFORMATION
PC BOARD LAYOUT
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
The ADuM141x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins
(see Figure 16). Bypass capacitors are most conveniently con-
nected between Pin 1 and Pin 2 for VDD1, and between Pin 15
and Pin 16 for VDD2. The capacitor value should be between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless both ground pins
on each package are connected together close to the package.
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 μs, the
input side is assumed to be unpowered or nonfunctional, in
which case the isolator output is forced to a default state (see
Table 14) by the watchdog timer circuit.
V
GND
V
DD1
DD2
GND
The magnetic field immunity of the ADuM141x is determined
by the changing magnetic field, which induces a voltage in the
transformer’s receiving coil large enough to either falsely set or
reset the decoder. The following analysis defines the conditions
under which this can occur. The 3 V operating condition of the
ADuM141x is examined because it represents the most suscep-
tible mode of operation.
1
IA
IB
IC
ID
2
V
V
V
V
V
V
V
V
OA
OB
OC
OD
ADuM1410
DISABLE
GND
CTRL
2
GND
1
2
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it
is important to minimize board coupling across the isolation
barrier. Furthermore, users should design the board layout
so that any coupling that does occur equally affects all pins
on a given component side. Failure to ensure this can cause
voltage differentials between pins exceeding the absolute
maximum ratings of the device, thereby leading to latch-up
or permanent damage.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
2
V = (−dβ / dt) ∑ π rn ; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high
transition.
Given the geometry of the receiving coil in the ADuM141x and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field at a given frequency can be calculated. The result
is shown in Figure 18.
INPUT (V
)
50%
Ix
100
tPLH
tPHL
OUTPUT (V
)
50%
Ox
10
Figure 17. Propagation Delay Parameters
1
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
0.1
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM141x component.
0.01
0.001
1k
10k
100k
1M
10M
100M
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM141x
components operating under the same conditions.
MAGNETIC FIELD FREQUENCY (Hz)
Figure 18. Maximum Allowable External Magnetic Flux Density
Rev. H | Page 19 of 24
ADuM1410/ADuM1411/ADuM1412
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and had the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
POWER CONSUMPTION
The supply current at a given channel of the ADuM141x
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q)
DDI = IDDI (D) × (2f − fr) + IDDI (Q)
f ≤ 0.5 fr
f > 0.5 fr
I
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM141x transformers. Figure 19 shows these allowable
current magnitudes as a function of frequency for selected
distances. As shown, the ADuM141x is extremely immune and
can be affected only by extremely large currents operated at
high frequency very close to the component. For the 1 MHz
example noted previously, a 0.5 kA current would have to be
placed 5 mm away from the ADuM141x to affect the operation
of the component.
For each output channel, the supply current is given by
I
I
DDO = IDDO (Q)
f ≤ 0.5 fr
DDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
where:
DDI (D), IDDO (D) are the input and output dynamic supply currents
I
per channel (mA/Mbps).
CL is the output load capacitance (pF).
V
DDO is the output supply voltage (V).
1000
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
DISTANCE = 1m
100
I
DDI (Q), IDDO (Q) are the specified input and output quiescent
10
supply currents (mA).
DISTANCE = 100mm
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
1
DISTANCE = 5mm
VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
0.1
show per-channel supply currents as a function of data rate for
an unloaded output condition. Figure 10 shows the per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 11 through Figure 15 show the total VDD1 and
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
VDD2 supply current as a function of data rate for ADuM1410/
Figure 19. Maximum Allowable Current for Various
Current-to-ADuM141x Spacings
ADuM1411/ADuM1412 channel configurations.
INSULATION LIFETIME
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficiently large enough to trigger the
thresholds of succeeding circuitry. Care should be taken in the
layout of such traces to avoid this possibility.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM141x.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in
Table 10 summarize the peak voltage for 50 years of service life
for a bipolar ac operating condition and the maximum
CSA/VDE approved working voltages. In many cases, the
approved working voltage is higher than 50-year service life
voltage. Operation at these high working voltages can lead to
shortened insulation life in some cases.
Rev. H | Page 20 of 24
ADuM1410/ADuM1411/ADuM1412
The insulation lifetime of the ADuM141x depends on the
voltage waveform type imposed across the isolation barrier. The
iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 20, Figure 21, and Figure 22 illustrate these
different isolation voltage waveforms.
Note that the voltage presented in Figure 21 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
RATED PEAK VOLTAGE
0V
Figure 20. Bipolar AC Waveform
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life. The
working voltages listed in Table 10 can be applied while
maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage case. Any cross-
insulation voltage waveform that does not conform to Figure 21
or Figure 22 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 10.
RATED PEAK VOLTAGE
0V
Figure 21. Unipolar AC Waveform
RATED PEAK VOLTAGE
0V
Figure 22. DC Waveform
Rev. H | Page 21 of 24
ADuM1410/ADuM1411/ADuM1412
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0
.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number Number
Maximum Maximum
of Inputs, of Inputs, Maximum Propagation Pulse Width Temperature
DD1 Side DD2 Side Data Rate Delay, 5 V Distortion Range
Package
Option
Model1
V
V
Package Description
ADuM1410ARWZ
4
0
1 Mbps
1 Mbps
10 Mbps
10 Mbps
1 Mbps
1 Mbps
10 Mbps
10 Mbps
1 Mbps
1 Mbps
10 Mbps
10 Mbps
100 ns
100 ns
50 ns
40 ns
40 ns
5 ns
−40°C to +105°C 16-Lead SOIC_W
RW-16
ADuM1410ARWZ-RL 4
ADuM1410BRWZ
ADuM1410BRWZ-RL 4
ADuM1411ARWZ
ADuM1411ARWZ-RL 3
ADuM1411BRWZ
ADuM1411BRWZ-RL 3
ADuM1412ARWZ
ADuM1412ARWZ-RL 2
ADuM1412BRWZ
0
0
0
1
1
1
1
2
2
2
2
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
−40°C to +105°C 16-Lead SOIC_W RW-16
−40°C to +105°C 16-Lead SOIC_W, 13” Tape and Reel RW-16
4
50 ns
5 ns
3
100 ns
100 ns
50 ns
40 ns
40 ns
5 ns
3
50 ns
5 ns
2
100 ns
100 ns
50 ns
40 ns
40 ns
5 ns
2
ADuM1412BRWZ-RL 2
50 ns
5 ns
1
Z = RoHS Compliant Part.
Rev. H | Page 22 of 24
ADuM1410/ADuM1411/ADuM1412
NOTES
Rev. H | Page 23 of 24
ADuM1410/ADuM1411/ADuM1412
NOTES
©2004–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06580-0-11/10(H)
Rev. H | Page 24 of 24
相关型号：
ADUM1412BRW
IC SPECIALTY INTERFACE CIRCUIT, PDSO16, LEAD FREE, MS-013AA, SOIC-16, Interface IC:Other
ADI
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