ADUM3201ARWZ [ADI]

ESD/Latch-Up Considerations with iCouplerÂ® Isolation Products; ESD /闩锁考虑与iCouplerÂ®隔离产品


型号：	ADUM3201ARWZ
厂家：	ADI
描述：	ESD/Latch-Up Considerations with iCouplerÂ® Isolation Products ESD /闩锁考虑与iCouplerÂ®隔离产品
文件：	总8页 (文件大小：253K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AN-793

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/461-3113 • www.analog.com

ESD/Latch-Up Considerations with iCoupler Isolation Products

by Rich Ghiorse

INTRODUCTION

Components vs. Systems

Analog Devices iCoupler products offer an alternative iso-

lation solution to optocouplers with superior integration,

performance, and power consumption characteristics. An

iCoupler isolation channel consists of CMOS input and

output circuits and a chip scale transformer (see Figure 1).

Because the iCoupler employs CMOS technology, it can

be more vulnerable to latch-up or electrostatic discharge

(ESD) damage than an optocoupler when subjected to

system-level ESD, surge voltage, fast transient, or other

overvoltage conditions.

Simply put, a component is a single integrated device

with interconnects while a system is a nonintegrated

device built from several interconnected components. In

almost all cases the distinction between a component

and a system is obvious. However, the differences

between component and system tests may not be

so obvious. Further, component specifications may

not directly indicate how a device will perform in

system-level testing. ESD testing is a good example

of this.

ESD, surge, burst, and fast transient events are facts of

life in electronic applications. These events generally

consist of high voltage, short duration spikes applied

directly or indirectly to a device. These events arise

from interaction of the device to real-world phenomena,

such as human contact, ac line perturbations, lightning

strikes, or common-mode voltage differences between

system grounds.

Component-level ESD testing is most useful in deter-

mining a device’s robustness to handling by humans

and automated assembly equipment prior and during

assembly into a system. Component-level ESD data is

less useful in determining a device’s robustness within

a system subjected to system-level ESD events. There

are two reasons for this.

Figure 1. ADuM140x Quad Isolator

This application note provides guidance for avoiding

these problems. Examples are presented for various

system-level test conﬁgurations showing mechanisms

that may impact performance. For each example recom-

mended solutions are given.

•

System- and component-level ESD testing have

different objectives. Component-level testing seeks

to address conditions typically endured during com-

ponent handling and assembly. System-level testing

seeks to address conditions typically endured during

system operation.

Later this year, Analog Devices is introducing hardened

versions of most iCoupler products that will have

improved immunity to latch-up and electrical overstress

(EOS). This new product family, the ADuM3xxx series,

will be pin-compatible with the existing ADuM1xxx

series products and will offer identical performance

speciﬁcations. Both product families will continue to

be made available.

•

The speciﬁc conditions a component is subjected

to during system-level testing can be a strong func-

tion of the board/module/system design in which it

resides. For example, long inductive traces between

a system and component ground can actually impose

a more severe voltage transient onto a component

than is imposed on the system at the test point.

REV.0

AN-793

Table I summarizes the ESD test results for the

ADuM140x quad isolator. One might conclude from

Table I that iCouplers can only be used in systems with

ESD ratings of < 4 kV. In reality it is quite common for

iCouplers to be used in systems that pass 15 kV ESD

levels per IEC 61000-4-2.

DD1

DD2

GND

The difference is in the test methods:

Figure 2. iCoupler Model Useful in Analyzing

System Designs

The component-level tests call for direct application

of ESD events to the pins or body of an unpowered

device, while system-level tests call for application ESD

events to various locations in the system accessible to

external ESD occurrences. Furthermore, the speciﬁc

waveforms used in component-level and system-level

testing differ.

Latch-Up in CMOS Devices

Inherent in a CMOS process are parasitic PNP and

NPN transistors conﬁgured as silicon control rectiﬁers

(SCR). Latch-up is a condition that comes about when

this parasitic SCR is triggered. This causes a low resis-

tance to appear from V_DDto ground, and a subsequent

large current to be drawn through the device. This

excessive current lays open the possibility of damage

due to EOS.

Table I. ADuM140x ESDTest Results

ESD

Model

First Pass

Voltage (V)

First Fail

Voltage (V)

Human

Body Model

Damage caused by latch-up can range from complete

destruction of the device to parametric degradation. More

insidious are latent failures that could affect operation

later in a system’s lifetime. An excellent treatise on

the subject of latch-up in general can be found in the

Analog Dialogue 35-05 (2001) article, “Winning the

Battle Against Latch-Up in CMOS Switches.” While

this article speciﬁcally addresses problems with CMOS

switches, it is generally applicable to all CMOS devices,

including iCouplers.

3,500

4,000

Field Induced Charge

Device Model

1,500

200

2,000

400

Machine Model

For complete information on Analog Devices ESD testing, refer to the

Analog Devices Reliability Handbook.

To accurately predict the performance of iCouplers in

a system, the designer needs to understand the nature

of the system tests and weigh how they impact the

iCoupler at the component level. Table II lists common

system-level tests used in iCoupler applications. Several

examples of these tests will be discussed later.

The use of ceramic bypass capacitors to minimize supply

noise between V_DDand ground is highly recommended

in all iCoupler applications. These should have a value

between 0.01 F and 0.1 F and be placed as close as

possible to the iCoupler device. Even with adequate

bypassing, latch-up problems may still occur in some

applications. Placing a 200  resistor in series with V_DDis

also helpful. This limits the supply current to 25 mA in 5 V

applications, which is below the latch-up trigger current.

However, depending on the supply current being drawn,

this series resistance can reduce the supply voltage at

the iCoupler to an unacceptable level. This is most likely

to be a concern when operating at high data rates that

involve high supply currents.

Table II. Common SystemTests Used

in iCoupler Applications

Test

Standard

Test

Purpose

Voltage (V rms)¹

IEC 61000-4-2

IEC 61000-4-4

IEC 61000-4-5

ESD

2,000 to 15,000

500 to 4,000

FastTransient/Burst

Surge

¹IEC 61000-4 tests include compliance levels; the test voltages shown

are the ranges for level 1 (lowest) through level 4 (highest) compliance.

iCoupler Model for Analyzing SystemTest Performance

Figure 2 shows a circuit model of an iCoupler which is

useful to understand the impact of system-level testing.

Inductors L1, L2, L3, and L4 are due largely to package

pins and bond wires, while capacitor C1 is due to the

stray capacitance across the isolation barrier. The induc-

tance values are approximately 0.2 nH. The capacitance

value is approximately 0.3 pF per iCoupler channel.

Usually the mechanism that causes latch-up is an over-

voltage condition beyond the part’s absolute maximum

rating (>7.0 V or <–0.5 V for most iCoupler products).

Once an iCoupler is integrated into a system the source

of the overvoltage is not always clear. However, it is

usually manageable once understood.

–2–

REV. 0

AN-793

IEC 61000-4-2 ESDTesting

instance the chassis impedance, Z_CHASSIS, gives rise

to an injected current during an ESD discharge. This

current ﬂows in the loop formed by L3, C2, L4, and

C_STRAY. C_STRAYis the capacitance from the shield of an

output cable to chassis ground. The larger the value of

C_STRAY, the larger the injected current and the consequent

internal noise voltage appearing across L4. If this voltage

forces GND₂beyond its absolute maximum rating, then

latch-up could occur.

A block diagram of the IEC 61000-4-2 ESD test is shown

in Figure 3. In this test, ESD contact or air discharges are

applied at various points on a system chassis. This gives

rise to several mechanisms that can cause latch-up

problems for an iCoupler. These include injected current

via one of the iCoupler grounds as well as inductive

coupling from ESD currents in the system chassis or in

printed wiring board traces.

SYSTEM CHASSIS

The following measures are recommended to avoid

current injection difﬁculties:

• Minimize the chassis impedance to ground.

CHASSIS

GROUND

• Minimize C_STRAY, the cross-isolation barrier capacitance.

• If possible place a 200  resistor in series with V_DD2to

limit latch-up trigger current.

• Place a 50  resistor between chassis ground and

GND₁. This reduces I_INJECTEDand ultimately V_NOISE

• Place a transient absorbing Zener diode from the

connection to chassis ground. This clamps the noise

voltage to within the Zener voltage.

ESD ZAP TO 15kV

ESD

SOURCE

AIR OR CONTACT

DISCHARGE

Inductive Coupling from ESD Current

One consideration is the possibility of inductive coupling

from ESD current present in the iCoupler printed wiring

board or system chassis. Inductive pickup on iCoupler

transformers from external magnetic fields is not a

problem in the vast majority of applications; however,

there have been rare instances in IEC 61000-4-2 ESD

testing where this phenomenon has been noted.

Solutions to this problem are straightforward.

Figure 3. IEC 61000-4-2 ESDTest

Injected ESD Current

The ﬁrst possible mechanism for latch-up is one in

which excessive ESD current is injected into an iCoupler

ground. Figure 4 shows a situation where an iCoupler

is used as a ﬂoating output (the same mechanism can

be present in a ﬂoating input conﬁguration). In this

200 RESISTOR TO LIMIT

LATCH-UP TRIGGER CURRENT

USE 50 RESISTOR TO

ESD ZAP

DECREASE I

INJECTED

200

DD2

DD1

LOGIC

OUT

50

GND

–

NOISE

INJECTED

CHASSIS

STRAY

ADDITION OF TRANSIENT

ABSORBER TO CLAMP

MINIMIZE SIZE OF C

STRAY

COUPLING FROM OUTPUT

CABLE SHIELD TO CHASSIS

GROUND

CHASSIS/EARTH

GROUND

NOISE VOLTAGE AT GND PIN

Figure 4. Injected ESD Current Mechanism and Recommended Solutions

REV. 0

–3–

AN-793

Figure 5 shows an ESD test setup and the paths of cur-

rents I_ESDand I₁caused by an ESD strike. These currents

can be very large, and induce large magnetic ﬁelds on

the application printed wiring board and chassis. The

placement and geometry of ground traces, ground

circuit connections, board location, and orientation

within the chassis are all critical in minimizing inductive

pickup from the radiated magnetic ﬁelds.

WORST ORIENTATION

iCoupler

PACKAGE

CHIP SCALE

TRANSFORMER

INDUCED

Figure 5a shows a poor layout which uses a thin ground

trace near the iCoupler. It also shows a ground loop that

allows some of I_ESDto ﬂow through the board ground

circuit as I₁. Close proximity and narrow trace widths

increase the magnitude of the induced magnetic ﬁeld.

If strong enough, this can cause iCoupler latch-up as

discussed above. Figure 5b shows an optimal design

using a wide ground plane further away from the

iCoupler and a single point ground which prevents

I_ESDfrom flowing in the board ground circuit. When

designing ground circuits, it is always helpful to think in

terms of current paths.

–

MAGNETIC FIELD ORIENTATION RIGHT

ANGLE TO TRANSFORMER WINDINGS

MAXIMIZES V

INDUCED

BEST ORIENTATION

PC BOARD

CHIP SCALE

TRANSFORMER

MAGNETIC FIELD ORIENTATION

PARALLEL TO TRANSFORMER

WINDINGS MINIMIZES V

INDUCED

When designing the chassis for the system, it is impor-

tant to minimize impedance of the chassis ground con-

nection. It is also helpful to mount printed circuit boards

as far away from the edge of the chassis as possible, and

to have the board oriented so that iCouplers are parallel

to any radiated magnetic ﬁelds as depicted in Figure 6.

iCoupler

PACKAGE

SYSTEM

CHASSIS

Figure 6. External Magnetic Field Interaction

APPLICATION BOARD

with iCouplerTranformers

If inductive coupling is a problem, recommended solu-

tions include the following:

iCoupler

FIGURE 5a

•

Properly design ground system to avoid ground

loops.

POOR

GROUND

LAYOUT

•

Use ground plane instead of single narrow traces.

POOR GROUND TECHNIQUE:

1. GROUND LOOP ALLOWS PART OF THE LESD

TO FLOW THROUGH BOARD GROUND

2. THIN GROUND CONDUCTOR WILL RADIATE

MAGNETIC FIELD AND CAUSE PICKUP IN

iCoupler TRANSFORMERS

ESD

Orient print wiring boards away from chassis

boundaries.

•

If possible, orient the iCoupler parallel to external

magnetic ﬁelds as depicted in Figure 6.

ESD ZAP POINT

IEC 61000-4-5 SurgeTesting

SYSTEM

CHASSIS

Surge testing per IEC 61000-4-5 is another common

system-level test in industrial and instrumentation

applications. Figure 7 depicts an iCoupler in a surge

test conﬁguration showing associated bypass and stray

capacitances. V_TESTis the surge test voltage appearing

between earth ground and the board’s local ground

GND₁. This test typically has test voltages up to 4 kV. As

shown in Figure 7, if excessive stray capacitance exists

across the isolation barrier, the voltage at V_DD1can be

driven above its absolute maximum rating and damage

the iCoupler.

APPLICATION BOARD

GROUND

PLANE

iCoupler

FIGURE 5b

ESD

GOOD

GROUND

LAYOUT

GOOD GROUND TECHNIQUE:

1. USE OF WIDE GROUND PLANE LOWERS

INDUCTANCE AND WILL LOWER NOISE

2. NO LOOP SO LESD FLOWS THROUGH THE

CHASSIS ONLY

ESD ZAP POINT

Figure 5. Contrasting Examples of Board

Ground Circuits

–4–

REV. 0

AN-793

ꢈꢐ

C_BP1should be increased to 0.1 F to reduce the coupled

voltage to 0.4 V—a much safer value. Do the following

for best results:

ꢁ

ꢂꢂꢀ

ꢂꢂꢆ

�ꢀ

�ꢋ

�ꢆ

�ꢌ

ꢁ

•

Minimize capacitances between iCoupler ﬂoating

ꢃꢄ

ꢇ

grounds and system grounds.

ꢈꢉꢊ

ꢆ

ꢀ

•

Provide adequate bypassing with good quality

ceramic bypass capacitors with values large enough

to minimize the induced voltage at iCoupler

supply pins.

ꢅꢄꢂ

ꢆ

ꢀ

ꢈꢌ

ꢈꢀ

ꢈꢋ

•

Ensure V_DD1and V_DD2are free from noise spikes.

ꢁ

ꢍꢎꢏꢍ

If possible add a 200  resistor in series with V_DD1to

limit parasitic SCR trigger current.

Figure 7. iCoupler in IEC 61000-4-5 SurgeTest Setup

•

Use a transient-absorbing Zener diode across V_DD1.

Figure 8 shows the model reduced for easier analysis

of circuit. The simpliﬁed schematic ignores negligible

effects of lead inductances and lumps C_STRAYas a com-

puted element (Equation 1).

IEC 61000-4-4 FastTransient and BurstTesting Example

Fast transient and burst testing per IEC 61000-4-4 is

another common system-level test that can cause

problems if good design practice is not followed. This

test couples high voltage fast edge signals onto system

ac mains.

�

ꢙ

ꢋꢗꢍꢍꢖꢊꢙꢒꢕꢚꢖꢌꢒꢍ

ꢎꢏꢐꢔꢍꢖꢒꢔꢎ

ꢐꢊꢍꢗꢏꢊꢒꢏ

ꢐꢔꢀꢕꢁꢛꢛ�

ꢁꢛꢛ�

iꢃꢄꢅꢆꢇꢈꢉ

COUPLED TRANSIENT NOISE

THROUGH C

�

ꢀꢀꢁ

STRAY

OR V

DD2

ꢀꢀꢂ

DD1

�

ꢌ

�

ꢕꢖꢍꢕꢃꢗꢘꢋꢙꢒꢀ

ꢌ

BOARD WITH

iCoupler

�ꢗꢙꢎꢐꢓꢒꢕꢗꢔꢕ�

ꢀꢘꢒꢕꢎꢗꢕꢃ

ꢃꢊꢋ

ꢃ

ꢍꢎꢏꢐꢑ

ꢀꢀꢂ

ꢍꢎꢏꢐꢑ

ꢂ

TRANSFORMER

WINDING

CAPACITANCE

EFT/BURST

GENERATOR

ꢓꢔꢀ

ꢁ

ꢂ

STRAY

COUPLING

NETWORK

�

ꢎꢒꢍꢎ

DD1

AC LINES

DD2

Figure 8. Simpliﬁed Equivalent Circuit of Figure 7

SYSTEM POWER

SUPPLIES

COUPLED TRANSIENT

NOISE ONTO AC LINE

Using Figure 8, and ignoring inductances, C_STRAYis given

ADUM3201ARWZ [ADI]

相关型号：

ADUM3201ARZ

ADUM3201ARZ-RL7

ADUM3201BRZ

ADUM3201BRZ-RL7

ADUM3201CRZ

ADUM3201CRZ-RL7

ADUM3201WARZ

ADUM3201WARZ-RL7

ADUM3201WBRZ

ADUM3201WBRZ-RL7

ADUM3201WCRZ

ADUM3201WCRZ-RL7