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ADUM6403CRWZ [ADI]

Quad-Channel Isolators with Integrated DC-to-DC Converter; 四通道隔离器，集成DC- DC转换器
ADUM6403CRWZ
型号： ADUM6403CRWZ
厂家： ADI    ADI
描述：

Quad-Channel Isolators with Integrated DC-to-DC Converter
四通道隔离器，集成DC- DC转换器

转换器
文件： 总24页 (文件大小：594K)
中文：  中文翻译
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Quad-Channel Isolators with  
Integrated DC-to-DC Converter  
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
FUNCTIONAL BLOCK DIAGRAMS  
FEATURES  
isoPower integrated, isolated dc-to-dc converter  
Regulated 3.3 V or 5 V output  
Up to 500 mW output power  
Quad dc-to-25 Mbps (NRZ) signal isolation channels  
Schmitt trigger inputs  
16-lead SOIC package with 7.6 mm creepage  
High temperature operation: 105°C  
High common-mode transient immunity: >25 kV/μs  
Safety and regulatory approvals (pending)  
UL recognition  
OSC  
RECT  
REG  
1
2
3
4
5
6
7
8
16  
V
V
DD1  
ISO  
GND  
15 GND  
1
ISO  
V
V
V
V
/V  
14  
13  
12  
11  
10  
9
V
V
V
V
V
/V  
IA OA  
IA OA  
4-CHANNEL iCOUPLER CORE  
/V  
/V  
IB OB  
IB OB  
ADuM6400/ADuM6401/  
ADuM6402/ADuM6403/  
ADuM6404  
/V  
/V  
IC OC  
IC OC  
/V  
ID OD  
/V  
ID OD  
V
DDL  
SEL  
GND  
GND  
ISO  
1
5000 V rms for 1 minute per UL1577  
CSA Component Acceptance Notice #5A  
IEC 60950-1: 600 V rms (reinforced)  
IEC 60601-1: 250 V rms (reinforced)  
VDE certificate of conformity  
Figure 1. ADuM640x Block Diagram  
V
V
IA  
OA  
3
4
5
6
14  
13  
12  
11  
V
V
V
V
V
V
IB  
IC  
ID  
OB  
OC  
OD  
ADuM6400  
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12  
V
IORM = 560 V peak  
Figure 2. ADuM6400  
V
V
IA  
OA  
APPLICATIONS  
3
4
5
6
14  
13  
12  
11  
V
V
V
V
V
IB  
IC  
OB  
OC  
ID  
RS-232/RS-422/RS-485 transceivers  
Medical isolation  
AC/dc power supply startup bias and gate drives  
Isolated sensor interface  
ADuM6401  
V
OD  
Figure 3. ADuM6401  
V
V
IA  
OA  
GENERAL DESCRIPTION  
3
4
5
6
14  
13  
12  
11  
V
V
V
V
IB  
OC  
OD  
OB  
IC  
The ADuM640x1 devices are quad-channel digital isolators with  
isoPower®, an integrated, isolated dc-to-dc converter. Based on  
the Analog Devices, Inc., iCoupler® technology, the dc-to-dc  
converter provides up to 500 mW of regulated, isolated power at  
either 5.0 V or 3.3 V from a 5.0 V input supply, or 3.3 V from a  
3.3 V supply at the power levels shown in Table 1. This eliminates  
the need for a separate, isolated dc-to-dc converter in low power,  
isolated designs. The iCoupler chip scale transformer technology  
is used to isolate the logic signals and for the magnetic components  
of the dc-to-dc converter. The result is a small form factor, total  
isolation solution.  
V
V
ADuM6402  
ID  
Figure 4. ADuM6402  
V
V
IA  
OA  
3
4
5
6
14  
13  
12  
11  
V
V
V
V
V
V
OB  
OC  
OD  
IB  
IC  
ID  
ADuM6403  
Figure 5. ADuM6403  
V
V
IA  
OA  
3
4
5
6
14  
13  
12  
11  
V
V
V
V
IB  
IC  
ID  
OB  
OC  
OD  
The ADuM640x isolators provide four independent isolation  
channels in a variety of channel configurations and data rates  
(see the Ordering Guide for more information).  
V
V
ADuM6404  
isoPower uses high frequency switching elements to transfer  
power through its transformer. Special care must be taken  
during printed circuit board (PCB) layout to meet emissions  
standards. Refer to the AN-0971 application note for board  
layout recommendations at www.analog.com.  
Figure 6. ADuM6404  
Table 1. Power Levels  
Input Voltage (V)  
Output Voltage (V)  
Output Power (mW)  
5
5
500  
330  
200  
5
3.3  
3.3  
3.3  
1
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2009 Analog Devices, Inc. All rights reserved.  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagrams............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Pin Configurations and Function Descriptions......................... 11  
Truth Table .................................................................................. 15  
Typical Performance Characteristics ........................................... 16  
Terminology.................................................................................... 18  
Applications Information.............................................................. 19  
Theory of Operation.................................................................. 19  
Printed Circuit Board (PCB) Layout ....................................... 19  
Thermal Analysis ....................................................................... 19  
Propagation Delay-Related Parameters................................... 20  
EMI Considerations................................................................... 20  
DC Correctness and Magnetic Field Immunity........................... 20  
Power Consumption .................................................................. 21  
Power Considerations................................................................ 21  
Insulation Lifetime..................................................................... 22  
Outline Dimensions....................................................................... 23  
Ordering Guide .......................................................................... 23  
Electrical Characteristics—5 V Primary Input Supply/5 V  
Secondary Isolated Supply .......................................................... 3  
Electrical Characteristics—3.3 V Primary Input Supply/3.3 V  
Secondary Isolated Supply .......................................................... 5  
Electrical Characteristics—5 V Primary Input Supply/3.3 V  
Secondary Isolated Supply .......................................................... 6  
Package Characteristics ............................................................... 8  
Regulatory Approvals................................................................... 8  
Insulation and Safety-Related Specifications............................ 8  
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation  
Characteristics .............................................................................. 9  
Recommended Operating Conditions ...................................... 9  
Absolute Maximum Ratings.......................................................... 10  
ESD Caution................................................................................ 10  
REVISION HISTORY  
5/09—Revision 0: Initial Version  
Rev. 0 | Page 2 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
SPECIFICATIONS  
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY  
All typical specifications are at TA = 25°C, VDD1 = VSEL = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended  
operation range which is 4.5 V ≤ VDD1, VSEL, VISO ≤ 5.5 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are  
tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.  
Table 2. DC-to-DC Converter Static Specifications  
Parameter  
Symbol  
Min Typ Max Unit  
Test Conditions  
DC-TO-DC CONVERTER SUPPLY  
Setpoint  
Line Regulation  
Load Regulation  
Output Ripple  
Output Noise  
Switching Frequency  
PW Modulation Frequency  
Output Supply  
VISO  
4.7  
5.0  
1
1
5.4  
5
V
IISO = 0 mA  
IISO = 50 mA, VDD1 = 4.5 V to 5.5 V  
IISO = 10 mA to 90 mA  
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA  
CBO = 0.1 μF||10 μF, IISO = 90 mA  
VISO (LINE)  
VISO (LOAD)  
VISO (RIP)  
VISO (NOISE)  
fOSC  
mV/V  
%
75  
mV p-p  
mV p-p  
MHz  
kHz  
mA  
200  
180  
625  
fPWM  
IISO (MAX)  
100  
VISO > 4.5 V  
Efficiency at IISO (MAX)  
IDD1, No VISO Load  
IDD1, Full VISO Load  
34  
19  
290  
%
mA  
mA  
IISO = 100 mA  
IDD1 (Q)  
IDD1 (MAX)  
30  
Table 3. DC-to-DC Converter Dynamic Specifications  
2 Mbps—A Grade, B Grade, C Grade  
25 Mbps—C Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
SUPPLY CURRENT  
ADuM6400  
IDD1  
19  
100  
19  
100  
19  
100  
19  
100  
19  
100  
64  
89  
68  
87  
71  
85  
75  
83  
78  
81  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
ADuM6401  
ADuM6402  
ADuM6403  
ADuM6404  
IISO (LOAD)  
Rev. 0 | Page 3 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
Table 4. Switching Specifications  
A Grade  
Typ  
C Grade  
Typ  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
1
100  
40  
25  
60  
6
Mbps  
ns  
ns  
ps/°C  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
55  
45  
5
PW  
tPSK  
1000  
40  
Within PWD limit  
Between any two units  
Propagation Delay Skew  
Channel Matching  
Codirectional1  
50  
15  
tPSKCD  
tPSKOD  
50  
50  
6
15  
ns  
ns  
Opposing Directional2  
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the  
isolation barrier.  
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the  
isolation barrier.  
Table 5. Input and Output Characteristics  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIH  
VIL  
VOH  
0.7 VISO or 0.7 VDD1  
V
V
V
V
V
V
0.3 VISO or 0.3 VDD1  
VDD1 − 0.3 or VISO − 0.3 5.0  
VDD1 − 0.5 or VISO − 0.5 4.8  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
VDD1, VDDL, VISO supply  
Logic Low Output Voltages  
VOL  
0.0  
0.2  
0.1  
0.4  
Undervoltage Lockout  
Positive Going Threshold  
Negative Going Threshold  
Hysterisis  
Input Currents per Channel  
AC SPECIFICATIONS  
Output Rise/Fall Time  
Common-Mode Transient  
Immunity1  
VUV+  
VUV−  
VUVH  
II  
2.7  
2.4  
0.3  
V
V
V
μA  
−20  
25  
+0.01 +20  
0 V ≤ VIx ≤ VDDX  
10% to 90%  
tR/tF  
|CM|  
2.5  
35  
ns  
kV/μs VIx= VDD1 or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.0  
Mbps  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a  
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.  
Rev. 0 | Page 4 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY  
All typical specifications are at TA = 25°C, VDD1 = VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the entire  
recommended operation range which is 3.0 V ≤ VDD1, VSEL, VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching  
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.  
Table 6. DC-to-DC Converter Static Specifications  
Parameter  
Symbol  
Min Typ Max Unit  
Test Conditions  
DC-TO-DC CONVERTER SUPPLY  
Setpoint  
Line Regulation  
Load Regulation  
Output Ripple  
Output Noise  
Switching Frequency  
PW Modulation Frequency  
Output Supply  
VISO  
3.0  
3.3  
1
1
3.6  
5
V
IISO = 0 mA  
IISO = 30 mA, VDD1 = 3.0 V to 3.6 V  
IISO = 6 mA to 54 mA  
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 54 mA  
CBO = 0.1 μF||10 μF, IISO = 54 mA  
VISO (LINE)  
VISO (LOAD)  
VISO (RIP)  
VISO (NOISE)  
fOSC  
mV/V  
%
50  
mV p-p  
mV p-p  
MHz  
kHz  
mA  
130  
180  
625  
fPWM  
IISO (MAX)  
60  
VISO > 3 V  
Efficiency at IISO (MAX)  
IDD1, No VISO Load  
IDD1, Full VISO Load  
33  
14  
175  
%
mA  
mA  
IISO = 60 mA  
IDD1 (Q)  
IDD1 (MAX)  
20  
Table 7. DC-to-DC Converter Dynamic Specifications  
2 Mbps—A Grade, B Grade, C Grade  
25 Mbps—C Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
SUPPLY CURRENT  
ADuM6400  
IDD1  
14  
60  
14  
60  
14  
60  
14  
60  
14  
60  
41  
43  
44  
42  
46  
41  
47  
39  
51  
38  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
ADuM6401  
ADuM6402  
ADuM6403  
ADuM6404  
IISO (LOAD)  
Table 8. Switching Specifications  
A Grade  
Typ  
C Grade  
Typ  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
1
100  
40  
25  
60  
6
Mbps  
ns  
ns  
ps/°C  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
60  
45  
5
PW  
tPSK  
1000  
40  
Within PWD limit  
Between any two units  
Propagation Delay Skew  
Channel Matching  
Codirectional1  
50  
45  
tPSKCD  
tPSKOD  
50  
50  
6
15  
ns  
ns  
Opposing Directional2  
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the  
isolation barrier.  
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the  
isolation barrier.  
Rev. 0 | Page 5 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
Table 9. Input and Output Characteristics  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIH  
VIL  
VOH  
0.7 VISO or 0.7 VDD1  
V
V
V
V
V
V
0.3 VISO or 0.3 VDD1  
VDD1 − 0.2 or VISO − 0.2  
VDD1 − 0.5 or VISO − 0.5  
3.3  
3.1  
0.0  
0.0  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
VDD1, VDDL, VISO supply  
Logic Low Output Voltages  
VOL  
0.1  
0.4  
Undervoltage Lockout  
Positive Going Threshold  
Negative Going Threshold  
Hysterisis  
Input Currents per Channel  
AC SPECIFICATIONS  
Output Rise/Fall Time  
Common-Mode Transient  
Immunity1  
VUV+  
VUV−  
VUVH  
II  
2.7  
2.4  
0.3  
V
V
V
μA  
−10  
25  
+0.01 +10  
0 V ≤ VIx ≤ VDDX  
10% to 90%  
VIx = VDD1 or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
tR/tF  
|CM|  
2.5  
35  
ns  
kV/μs  
Refresh Rate  
fr  
1.0  
Mbps  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for  
a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.  
ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY  
All typical specifications are at TA = 25°C, VDD1 = 5.0 V, VISO = 3.3 V, VSEL = GNDISO. Minimum/maximum specifications apply over the  
entire recommended operation range which is 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VISO ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise  
noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.  
Table 10. DC-to-DC Converter Static Specifications  
Parameter  
Symbol  
Min Typ Max Unit  
Test Conditions  
DC-TO-DC CONVERTER SUPPLY  
Setpoint  
Line Regulation  
Load Regulation  
Output Ripple  
Output Noise  
Switching Frequency  
PW Modulation Frequency  
Output Supply  
Efficiency at IISO (MAX)  
IDD1, No VISO Load  
IDD1, Full VISO Load  
VISO  
3.0  
3.3  
1
1
3.6  
5
V
IISO = 0 mA  
IISO = 50 mA, VDD1 = 3.0 V to 3.6 V  
IISO = 6 mA to 54 mA  
20 MHz bandwidth, CBO = 0.1 μF||10 μF, IISO = 90 mA  
CBO = 0.1 μF||10 μF, IISO = 90 mA  
VISO (LINE)  
VISO (LOAD)  
VISO (RIP)  
VISO (NOISE)  
fOSC  
mV/V  
%
50  
mV p-p  
mV p-p  
MHz  
kHz  
mA  
%
mA  
mA  
130  
180  
625  
fPWM  
IISO (MAX)  
100  
20  
VISO > 3 V  
IISO = 90 mA  
30  
14  
230  
IDD1 (Q)  
IDD1 (MAX)  
Rev. 0 | Page 6 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
Table 11. DC-to-DC Converter Dynamic Specifications  
2 Mbps—A Grade, B Grade, C Grade  
25 Mbps—C Grade  
Parameter  
Symbol  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Test Conditions  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
No VISO load  
SUPPLY CURRENT  
ADuM6400  
IDD1  
9
100  
9
100  
9
100  
9
100  
9
100  
43  
93  
44  
92  
45  
91  
46  
89  
47  
88  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
IISO (LOAD)  
IDD1  
ADuM6401  
ADuM6402  
ADuM6403  
ADuM6404  
IISO (LOAD)  
Table 12. Switching Specifications  
A Grade  
Typ  
C Grade  
Typ  
Parameter  
Symbol  
Min  
Max  
Min  
Max  
Unit  
Test Conditions  
SWITCHING SPECIFICATIONS  
Data Rate  
Propagation Delay  
Pulse Width Distortion  
Change vs. Temperature  
Pulse Width  
1
100  
40  
25  
60  
6
Mbps  
ns  
ns  
ps/°C  
ns  
ns  
Within PWD limit  
50% input to 50% output  
|tPLH − tPHL|  
tPHL, tPLH  
PWD  
60  
45  
5
PW  
tPSK  
1000  
40  
Within PWD limit  
Between any two units  
Propagation Delay Skew  
Channel Matching  
Codirectional1  
50  
15  
tPSKCD  
tPSKOD  
50  
50  
6
15  
ns  
ns  
Opposing Directional2  
1
7
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.  
2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.  
Table 13. Input and Output Characteristics  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
Test Conditions  
DC SPECIFICATIONS  
Logic High Input Threshold  
Logic Low Input Threshold  
Logic High Output Voltages  
VIH  
VIL  
VOH  
0.7 VISO or 0.7 VDD1  
V
V
V
V
0.3 VISO or 0.3 VDD1  
VDD1 − 0.2, VISO − 0.2  
VDD1 − 0.5 or  
VDD1 or VISO  
VDD1 − 0.2 or  
IOx = −20 μA, VIx = VIxH  
IOx = −4 mA, VIx = VIxH  
VISO − 0.5  
VISO − 0.2  
Logic Low Output Voltages  
VOL  
0.0  
0.0  
0.1  
0.4  
V
V
IOx = 20 μA, VIx = VIxL  
IOx = 4 mA, VIx = VIxL  
VDD1, VDDL, VISO supply  
Undervoltage Lockout  
Positive Going Threshold  
Negative Going Threshold  
Hysterisis  
Input Currents per Channel  
AC SPECIFICATIONS  
Output Rise/Fall Time  
Common-Mode Transient  
Immunity1  
VUV+  
VUV−  
VUVH  
II  
2.7  
2.4  
0.3  
+0.01  
V
V
V
μA  
−10  
25  
+10  
0 V ≤ VIx ≤ VDDx  
10% to 90%  
tR/tF  
|CM|  
2.5  
35  
ns  
kV/μs VIx = VDD1 or VISO, VCM = 1000 V,  
transient magnitude = 800 V  
Refresh Rate  
fr  
1.0  
Mbps  
1 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a  
low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.  
Rev. 0 | Page 7 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
PACKAGE CHARACTERISTICS  
Table 14. Thermal and Isolation Characteristics  
Parameter  
Symbol Min Typ Max Unit Test Conditions  
Resistance (Input to Output)1  
Capacitance (Input to Output)1  
Input Capacitance2  
RI-O  
CI-O  
CI  
1012  
2.2  
4.0  
45  
Ω
pF  
pF  
f = 1 MHz  
IC Junction to Ambient Thermal Resistance θJA  
°C/W Thermocouple located at center of package underside,  
test conducted on 4-layer board with thin traces3  
1 The device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together; and Pin 9 to Pin 16 are shorted together.  
2 Input capacitance is from any input data pin to ground.  
3 See the Thermal Analysis section for thermal model definitions.  
REGULATORY APPROVALS  
Table 15.  
UL (Pending)1  
CSA  
VDE (Pending)2  
Recognized under 1577 component  
recognition program1  
Approved under CSA Component  
Acceptance Notice #5A  
Certified according to DIN V VDE V 0884-10  
(VDE V 0884-10):2006-123  
5000 V rms isolation voltage double  
protection  
Reinforced insulation per CSA 60950-1-03  
and IEC 60950-1, 600 V rms (848 V peak)  
maximum working voltage  
Reinforced insulation, 846 V peak  
Reinforced insulation per IEC 60601-1  
250 V rms (353 V peak) maximum working  
voltage  
File E214100  
File 205078  
File 2471900-4880-0001  
1 In accordance with UL 1577, each ADuM640x is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).  
2 In accordance with DIN EN 60747-5-2, each ADuM640x is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection  
limit = 5 pC).  
3 In accordance with DIN V VDE V 0884-10, each ADuM640x is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial discharge detection  
limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.  
INSULATION AND SAFETY-RELATED SPECIFICATIONS  
Table 16. Critical Safety-Related Dimensions and Material Properties  
Parameter  
Symbol Value  
Unit Test Conditions/Comments  
Rated Dielectric Insulation Voltage  
Minimum External Air Gap (Clearance)  
5000  
7.6  
V rms 1-minute duration  
L(I01)  
L(I02)  
mm  
Measured from input terminals to output terminals,  
shortest distance through air  
Minimum External Tracking (Creepage)  
>8.0  
mm  
Measured from input terminals to output terminals,  
shortest distance path along body  
Minimum Internal Gap (Internal Clearance)  
Tracking Resistance (Comparative Tracking Index)  
Isolation Group  
0.017 min mm  
Distance through insulation  
IEC 60112  
Material group (DIN VDE 0110, 1/89, Table 1)  
CTI  
>400  
II  
V
Rev. 0 | Page 8 of 24  
 
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS  
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by  
the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval.  
Table 17. VDE Characteristics  
Description  
Conditions  
Symbol Characteristic Unit  
Installation Classification per DIN VDE 0110  
For Rated Mains Voltage ≤ 150 V rms  
For Rated Mains Voltage ≤ 300 V rms  
For Rated Mains Voltage ≤ 400 V rms  
Climatic Classification  
Pollution Degree per DIN VDE 0110, Table 1  
Maximum Working Insulation Voltage  
Input-to-Output Test Voltage, Method b1  
I to IV  
I to III  
I to II  
40/105/21  
2
VIORM  
VPR  
846  
1590  
V peak  
V peak  
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,  
partial discharge < 5 pC  
Input-to-Output Test Voltage, Method a  
After Environmental Tests Subgroup 1  
After Input and/or Safety Test Subgroup 2  
and Subgroup 3  
VPR  
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC  
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC  
1375  
1018  
V peak  
V peak  
Highest Allowable Overvoltage  
Safety Limiting Values  
Transient overvoltage, tTR = 10 sec  
Maximum value allowed in the event of a failure  
(see Figure 7)  
VTR  
6000  
V peak  
Case Temperature  
Side 1 IDD1 Current  
Insulation Resistance at TS  
TS  
IS1  
RS  
150  
555  
>109  
°C  
mA  
Ω
VIO = 500 V  
600  
500  
400  
300  
200  
100  
0
0
50  
100  
150  
200  
AMBIENT TEMPERATURE (°C)  
Figure 7. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2  
RECOMMENDED OPERATING CONDITIONS  
Table 18.  
Parameter  
Symbol  
Min  
Max  
Unit  
Operating Temperature1  
Supply Voltages2  
VDD1 @ VSEL = 0 V  
VDD1 @ VSEL = VISO  
Minimum Load  
TA  
−40  
+105  
°C  
VDD  
VDD  
IISO(MIN)  
3.0  
4.5  
10  
5.5  
5.5  
V
V
mA  
1 Operation at 105°C requires reduction of the maximum load current as specified in Table 19.  
2 Each voltage is relative to its respective ground.  
Rev. 0 | Page 9 of 24  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
ABSOLUTE MAXIMUM RATINGS  
Ambient temperature = 25°C, unless otherwise noted.  
Table 19.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
Rating  
Storage Temperature Range (TST)  
Ambient Operating Temperature  
Range (TA)  
Supply Voltages (VDD1, VISO  
Input Voltage  
(VIA, VIB, VIC, VID, VSEL  
−55°C to +150°C  
−40°C to +105°C  
1
)
−0.5 V to +7.0 V  
−0.5 V to VDDI + 0.5 V  
1, 2  
)
Output Voltage  
(VOA, VOB, VOC, VOD  
−0.5 V to VDDO + 0.5 V  
1, 2  
)
ESD CAUTION  
Average Output Current per Pin3  
Common-Mode Transients4  
−10 mA to +10 mA  
−100 kV/μs to +100 kV/μs  
1 Each voltage is relative to its respective ground.  
2 VDDI and VDDO refer to the supply voltages on the input and output sides of a  
given channel, respectively. See the Printed Circuit Board (PCB) Layout section.  
3 See Figure 7 for maximum rated current values for various temperatures.  
4. Common-mode transients exceeding the absolute maximum slew rate may  
cause latch-up or permanent damage.  
Table 20. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1  
Parameter  
Max  
Unit  
Applicable Certification  
AC Voltage, Bipolar Waveform  
AC Voltage, Unipolar Waveform  
Basic Insulation  
Reinforced Insulation  
DC Voltage  
424  
V peak  
All certifications, 50-year operation  
600  
560  
V peak  
V peak  
Working voltage per IEC 60950-1  
Working voltage per DIN V VDE V 0884-10  
Basic Insulation  
Reinforced Insulation  
600  
560  
V peak  
V peak  
Working voltage per IEC 60950-1  
Working voltage per DIN V VDE V 0884-10  
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information.  
Rev. 0 | Page 10 of 24  
 
 
 
 
 
 
 
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
V
1
2
3
4
5
6
7
8
16  
V
ISO  
DD1  
GND  
15 GND  
1
IA  
IB  
IC  
ID  
ISO  
V
V
V
V
14  
13  
12  
11  
10  
9
V
V
V
V
V
OA  
OB  
OC  
OD  
SEL  
ADuM6400  
TOP VIEW  
(Not to Scale)  
V
DDL  
GND  
GND  
ISO  
1
Figure 8. ADuM6400 Pin Configuration  
Table 21. ADuM6400 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
2, 8  
GND1  
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both  
pins be connected to a common ground.  
3
VIA  
Logic Input A.  
4
VIB  
Logic Input B.  
5
VIC  
Logic Input C.  
6
VID  
Logic Input D.  
7
9, 15  
VDDL  
GNDISO  
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be  
connected to a common ground.  
10  
11  
12  
13  
14  
16  
VSEL  
VOD  
VOC  
VOB  
VOA  
VISO  
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.  
Logic Output D.  
Logic Output C.  
Logic Output B.  
Logic Output A.  
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).  
Rev. 0 | Page 11 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
V
1
2
3
4
5
6
7
8
16  
V
ISO  
DD1  
GND  
15 GND  
1
IA  
IB  
IC  
ISO  
V
V
V
14  
13  
12  
11  
10  
9
V
V
V
V
V
OA  
OB  
OC  
ID  
ADuM6401  
TOP VIEW  
(Not to Scale)  
V
OD  
V
DDL  
SEL  
GND  
GND  
ISO  
1
Figure 9. ADuM6401 Pin Configuration  
Table 22. ADuM6401 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
2, 8  
GND1  
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both  
pins be connected to a common ground.  
3
VIA  
Logic Input A.  
4
VIB  
Logic Input B.  
5
VIC  
Logic Input C.  
6
7
9, 15  
VOD  
VDDL  
GNDISO  
Logic Output D.  
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be  
connected to a common ground.  
10  
11  
12  
13  
14  
16  
VSEL  
VID  
VOC  
VOB  
VOA  
VISO  
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.  
Logic Input D.  
Logic Output C.  
Logic Output B.  
Logic Output A.  
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).  
Rev. 0 | Page 12 of 24  
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
V
1
2
3
4
5
6
7
8
16  
V
ISO  
DD1  
GND  
15 GND  
1
IA  
IB  
ISO  
V
V
14  
13  
12  
11  
10  
9
V
V
V
V
V
OA  
OB  
IC  
ADuM6402  
TOP VIEW  
(Not to Scale)  
V
V
OC  
OD  
ID  
V
DDL  
SEL  
GND  
GND  
ISO  
1
Figure 10. ADuM6402 Pin Configuration  
Table 23. ADuM6402 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
2, 8  
GND1  
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both  
pins be connected to a common ground.  
3
VIA  
Logic Input A.  
4
VIB  
Logic Input B.  
5
VOC  
Logic Output C.  
6
VOD  
Logic Output D.  
7
9, 15  
VDDL  
GNDISO  
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be  
connected to a common ground.  
10  
11  
12  
13  
14  
16  
VSEL  
VID  
VIC  
VOB  
VOA  
VISO  
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.  
Logic Input D.  
Logic Input C.  
Logic Output B.  
Logic Output A.  
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).  
Rev. 0 | Page 13 of 24  
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
V
1
2
3
4
5
6
7
8
16  
V
ISO  
DD1  
GND  
15 GND  
1
ISO  
V
14  
13  
12  
11  
10  
9
V
V
V
V
V
IA  
OA  
IB  
ADuM6403  
V
V
V
OB  
OC  
OD  
TOP VIEW  
(Not to Scale)  
IC  
ID  
V
DDL  
SEL  
GND  
GND  
ISO  
1
Figure 11. ADuM6403 Pin Configuration  
Table 24. ADuM6403 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
2, 8  
GND1  
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both  
pins be connected to a common ground.  
3
VIA  
Logic Input A.  
4
VOB  
Logic Output B.  
5
VOC  
Logic Output C.  
6
VOD  
Logic Output D.  
7
9, 15  
VDDL  
GNDISO  
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be  
connected to a common ground.  
10  
11  
12  
13  
14  
16  
VSEL  
VID  
VIC  
VIB  
VOA  
VISO  
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.  
Logic Input D.  
Logic Input C.  
Logic Input B.  
Logic Output A.  
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).  
Rev. 0 | Page 14 of 24  
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
V
1
2
3
4
5
6
7
8
16  
V
ISO  
DD1  
GND  
15 GND  
1
OA  
OB  
OC  
OD  
ISO  
V
14  
13  
12  
11  
10  
9
V
V
V
V
V
IA  
ADuM6404  
V
V
V
IB  
TOP VIEW  
(Not to Scale)  
IC  
ID  
V
DDL  
SEL  
GND  
GND  
ISO  
1
Figure 12. ADuM6404 Pin Configuration  
Table 25. ADuM6404 Pin Function Descriptions  
Pin No. Mnemonic Description  
1
VDD1  
Primary Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
2, 8  
GND1  
Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both  
pins be connected to a common ground.  
3
VOA  
Logic Output A.  
4
VOB  
Logic Output B.  
5
VOC  
Logic Output C.  
6
VOD  
Logic Output D.  
7
9, 15  
VDDL  
GNDISO  
Data Channel Supply Voltage, 3.0 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source.  
Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be  
connected to a common ground.  
10  
11  
12  
13  
14  
16  
VSEL  
VID  
VIC  
VIB  
VIA  
Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V.  
Logic Input D.  
Logic Input C.  
Logic Input B.  
Logic Input A.  
VISO  
Secondary Supply Voltage Output for External Loads, 3.3 V (VSEL Low) or 5.0 V (VSEL High).  
TRUTH TABLE  
Table 26. Truth Table (Positive Logic)  
VIx Input1 VSEL Input VDD1 State VDD1 Input (V) VISO State VISO Output (V) VOx Output1 Notes  
High  
Low  
High  
Low  
High  
Low  
High  
Low  
High  
High  
Low  
Low  
Low  
Low  
High  
High  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
5.0  
5.0  
3.3  
3.3  
5.0  
5.0  
3.3  
3.3  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
Powered  
5.0  
5.0  
3.3  
3.3  
3.3  
3.3  
5.0  
5.0  
High  
Low  
High  
Low  
High  
Low  
High  
Low  
Normal operation, data is high  
Normal operation, data is low  
Normal operation, data is high  
Normal operation, data is low  
Normal operation, data is high  
Normal operation, data is low  
Configuration not recommended  
Configuration not recommended  
1 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).  
Rev. 0 | Page 15 of 24  
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
TYPICAL PERFORMANCE CHARACTERISTICS  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
POWER  
I
DD1  
3.3V INPUT/3.3V OUTPUT  
5V INPUT/3.3V OUTPUT  
5V INPUT/5V OUTPUT  
0
0.02  
0.04  
0.06  
0.08  
0.10  
0.12  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
6.5  
OUTPUT CURRENT (A)  
INPUT SUPPLY VOLTAGE (V)  
Figure 16. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage  
Figure 13. Typical Power Supply Efficiency at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
10% LOAD  
90% LOAD  
V
V
V
= 5V, V  
= 5V, V  
= 3.3V, V  
= 5V  
= 3V  
ISO  
DD1  
DD1  
DD1  
0.1  
0
ISO  
= 3.3V  
ISO  
(100µs/DIV)  
0
0.02  
0.04  
0.06  
(A)  
0.08  
0.10 0.12  
I
ISO  
Figure 14. Typical Total Power Dissipation vs. IISO with Data Channels Idle  
Figure 17. Typical VISO Transient Load Response, 5 V Output,  
10% to 90% Load Step  
0.12  
0.10  
0.08  
0.06  
0.04  
10% LOAD  
90% LOAD  
0.02  
3.3V INPUT/3.3V OUTPUT  
5V INPUT/3.3V OUTPUT  
5V INPUT/5V OUTPUT  
0.20 0.25 0.30  
INPUT CURRENT (A)  
0
(100µs/DIV)  
0
0.05  
0.10  
0.15  
0.35  
Figure 18. Typical Transient Load Response, 3 V Output,  
10% to 90% Load Step  
Figure 15. Typical Isolated Output Supply Current, IISO, as a Function of  
External Load, No Dynamic Current Draw at 5 V/5 V, 5 V/3.3 V, and 3.3 V/3.3 V  
Rev. 0 | Page 16 of 24  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
20  
5V INPUT/5V OUTPUT  
3.3V INPUT/3.3V OUTPUT  
5V INPUT/3.3V OUTPUT  
16  
12  
8
4
0
BW = 20MHz (400ns/DIV)  
0
5
10  
15  
20  
25  
DATA RATE (Mbps)  
Figure 19. Typical VISO = 5 V Output Voltage Ripple at 90% Load  
Figure 22. Typical ICHn Supply Current per Reverse Data Channel  
(15 pF Output Load)  
5
4
3
5V  
2
3.3V  
1
0
0
5
10  
15  
20  
25  
BW = 20MHz (400ns/DIV)  
DATA RATE (Mbps)  
Figure 20. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load  
Figure 23. Typical IISO (D) Dynamic Supply Current per Input  
20  
3.0  
5V INPUT/5V OUTPUT  
3.3V INPUT/3.3V OUTPUT  
5V INPUT/3.3V OUTPUT  
16  
2.5  
2.0  
1.5  
1.0  
0.5  
0
12  
8
5V  
3.3V  
4
0
0
5
10  
15  
20  
25  
0
5
10  
15  
20  
25  
DATA RATE (Mbps)  
DATA RATE (Mbps)  
Figure 24. Typical IISO (D) Dynamic Supply Current per Output  
(15 pF Output Load)  
Figure 21. Typical ICHn Supply Current per Forward Data Channel  
(15 pF Output Load)  
Rev. 0 | Page 17 of 24  
 
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
TERMINOLOGY  
t
PLH Propagation Delay  
IDD1 (Q)  
tPLH propagation delay is measured from the 50% level of the rising  
IDD1(Q) is the minimum operating current drawn at the VDD1 pin  
when there is no external load at VISO and the I/O pins are  
operating below 2 Mbps, requiring no additional dynamic supply  
current. IDD1(Q) reflects the minimum current operating condition.  
edge of the VIx signal to the 50% level of the rising edge of the  
V
Ox signal.  
tPSK Propagation Delay Skew  
PSK is the magnitude of the worst-case difference in tPHL and/or tPLH  
t
IDD1 (D)  
that is measured between units at the same operating temperature,  
supply voltages, and output load within the recommended  
operating conditions.  
I
DD1 (D) is the typical input supply current with all channels  
simultaneously driven at a maximum data rate of 25 Mbps  
with full capacitive load representing the maximum dynamic  
load conditions. Resistive loads on the outputs should be  
treated separately from the dynamic load.  
t
PSKCD/tPSKOD Channel-to-Channel Matching  
Channel-to-channel matching is the absolute value of the  
difference in propagation delays between the two channels  
when operated with identical loads.  
IDD1 (MAX)  
I
DD1 (MAX) is the input current under full dynamic and VISO load  
conditions.  
Minimum Pulse Width  
The minimum pulse width is the shortest pulse width at which  
the specified pulse width distortion is guaranteed.  
t
PHL Propagation Delay  
tPHL propagation delay is measured from the 50% level of the  
falling edge of the VIx signal to the 50% level of the falling edge  
of the VOx signal.  
Maximum Data Rate  
The maximum data rate is the fastest data rate at which the  
specified pulse width distortion is guaranteed.  
Rev. 0 | Page 18 of 24  
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
APPLICATIONS INFORMATION  
THEORY OF OPERATION  
BYPASS < 2mm  
V
V
DD1  
ISO  
GND  
GND  
The dc-to-dc converter section of the ADuM640x works on  
principles that are common to most modern power supplies.  
It is a secondary side controller architecture with isolated pulse-  
width modulation (PWM) feedback. VDD1 power is supplied to an  
oscillating circuit that switches current into a chip-scale air core  
transformer. Power transferred to the secondary side is rectified  
and regulated to either 3.3 V or 5 V. The secondary (VISO) side  
controller regulates the output by creating a PWM control signal  
that is sent to the primary (VDD1) side by a dedicated iCoupler  
data channel. The PWM modulates the oscillator circuit to control  
the power being sent to the secondary side. Feedback allows for  
significantly higher power and efficiency.  
1
ISO  
V
V
V
V
/V  
IA OA  
V
V
V
V
V
/V  
IA OA  
/V  
IB OB  
/V  
IB OB  
/V  
IC OC  
/V  
IC OC  
/V  
/V  
ID OD  
ID OD  
V
DDL  
SEL  
GND  
1
GND  
ISO  
Figure 25. Recommended Printed Circuit Board Layout  
In applications involving high common-mode transients, ensure  
that board coupling across the isolation barrier is minimized.  
Furthermore, design the board layout such that any coupling  
that does occur equally affects all pins on a given component side.  
Failure to ensure this can cause voltage differentials between pins,  
exceeding the absolute maximum ratings specified in Table 19,  
thereby leading to latch-up and/or permanent damage.  
The ADuM640x implement undervoltage lockout (UVLO) with  
hysteresis on the VDD1 power input. This feature ensures that the  
converter does not go into oscillation due to noisy input power or  
slow power-on ramp rates.  
The ADuM640x are power devices that dissipate about 1 W  
of power when fully loaded and running at maximum speed.  
Because it is not possible to apply a heat sink to an isolation  
device, the devices primarily depend on heat dissipation into  
the PCB through the GND pins. If the devices are used at high  
ambient temperatures, provide a thermal path from the GND  
pins to the PCB ground plane. The board layout in Figure 25  
shows enlarged pads for Pin 8 and Pin 9. Large diameter vias  
should be implemented from the pad to the ground, and power  
planes should be used to reduce inductance. Multiple vias in the  
thermal pads can significantly reduce temperatures inside the  
chip. The dimensions of the expanded pads are left to the  
discretion of the designer and the available board space.  
A minimum load current of 10 mA is recommended to ensure  
optimum load regulation. Smaller loads can generate excess noise  
on chip due to short or erratic PWM pulses. Excess noise gener-  
ated this way can cause data corruption, in some circumstances.  
PRINTED CIRCUIT BOARD (PCB) LAYOUT  
The ADuM640x digital isolators with 0.5 W isoPower integrated  
dc-to-dc converters require no external interface circuitry for  
the logic interfaces. Power supply bypassing is required at the  
input and output supply pins (see Figure 25). Note that a low  
ESR bypass capacitor is required between Pin 1 and Pin 2, as  
close to the chip pads as possible.  
The power supply section of the ADuM640x uses a 180 MHz  
oscillator frequency to efficiently pass power through its chip  
scale transformers. In addition, normal operation of the data  
section of the iCoupler introduces switching transients on the  
power supply pins. Bypass capacitors are required for several  
operating frequencies. Noise suppression requires a low  
inductance, high frequency capacitor; ripple suppression  
and proper regulation require a large value capacitor. These are  
most conveniently connected between Pin 1 and Pin 2 for VDD1  
and between Pin 15 and Pin 16 for VISO. To suppress noise and  
reduce ripple, a parallel combination of at least two capacitors  
is required. The recommended capacitor values are 0.1 μF and  
10 μF for VDD1. The smaller capacitor must have a low ESR; for  
example, use of a ceramic capacitor is advised.  
THERMAL ANALYSIS  
The ADuM640x parts consist of four internal die attached to a  
split lead frame with two die attach paddles. For the purposes of  
thermal analysis, the die is treated as a thermal unit, with the  
highest junction temperature reflected in the θJA from Table 14.  
The value of θJA is based on measurements taken with the parts  
mounted on a JEDEC standard, 4-layer board with fine width  
traces and still air. Under normal operating conditions, the  
ADuM640x devices operate at full load across the full temperature  
range without derating the output current. However, following  
the recommendations in the Printed Circuit Board (PCB) Layout  
section decreases thermal resistance to the PCB, allowing  
increased thermal margins in high ambient temperatures.  
Note that the total lead length between the ends of the low ESR  
capacitor and the input power supply pin must not exceed 2 mm.  
Installing the bypass capacitor with traces more than 2 mm in  
length may result in data corruption. A bypass between Pin 1 and  
Pin 8 and between Pin 9 and Pin 16 should also be considered  
unless both common ground pins are connected together  
close to the package.  
Rev. 0 | Page 19 of 24  
 
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
The limitation on the ADuM640x magnetic field immunity is  
PROPAGATION DELAY-RELATED PARAMETERS  
set by the condition in which induced voltage in the transformer  
receiving coil is sufficiently large to either falsely set or reset the  
decoder. The following analysis defines the conditions under  
which this can occur. The 3.3 V operating condition of the  
ADuM640x is examined because it represents the most susceptible  
mode of operation.  
Propagation delay is a parameter that describes the time it takes  
a logic signal to propagate through a component (see Figure 26).  
The propagation delay to a logic low output may differ from the  
propagation delay to a logic high.  
INPUT (V  
)
50%  
Ix  
tPLH  
tPHL  
The pulses at the transformer output have an amplitude of >1.0 V.  
The decoder has a sensing threshold of about 0.5 V, thus estab-  
lishing a 0.5 V margin in which induced voltages can be tolerated.  
The voltage induced across the receiving coil is given by  
OUTPUT (V  
)
50%  
Ox  
Figure 26. Propagation Delay Parameters  
2
Pulse width distortion is the maximum difference between these  
two propagation delay values and is an indication of how  
accurately the input signal timing is preserved.  
V = (−dβ/dt)∑πrn ; n = 1, 2, … , N  
where:  
β is the magnetic flux density (gauss).  
N is the number of turns in the receiving coil.  
rn is the radius of the nth turn in the receiving coil (cm).  
Channel-to-channel matching refers to the maximum amount  
the propagation delay differs between channels within a single  
ADuM640x component.  
Given the geometry of the receiving coil in the ADuM640x, and  
an imposed requirement that the induced voltage be, at most, 50%  
of the 0.5 V margin at the decoder, a maximum allowable  
magnetic field is calculated as shown in Figure 27.  
100  
Propagation delay skew refers to the maximum amount the  
propagation delay differs between multiple ADuM640x  
components operating under the same conditions.  
EMI CONSIDERATIONS  
The dc-to-dc converter section of the ADuM640x components  
must, of necessity, operate at a very high frequency to allow  
efficient power transfer through the small transformers.  
This creates high frequency currents that can propagate in  
circuit board ground and power planes, causing edge and  
dipole radiation. Grounded enclosures are recommended for  
applications that use these devices. If grounded enclosures are  
not possible, follow good RF design practices in layout of the  
PCB. See www.analog.com for the most current PCB layout  
recommendations specifically for the ADuM640x.  
10  
1
0.1  
0.01  
0.001  
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
Positive and negative logic transitions at the isolator input cause  
narrow (~1 ns) pulses to be sent to the decoder via the transformer.  
The decoder is bistable and is, therefore, either set or reset by  
the pulses, indicating input logic transitions. In the absence of  
logic transitions at the input for more than 1 μs, periodic sets of  
refresh pulses indicative of the correct input state are sent to  
ensure dc correctness at the output. If the decoder receives no  
internal pulses of more than approximately 5 μs, the input side  
is assumed to be unpowered or nonfunctional, in which case,  
the isolator output is forced to a default high state by the watchdog  
timer circuit. This situation should only occur in the ADuM640x  
devices during power-up and power-down operations.  
Figure 27. Maximum Allowable External Magnetic Flux Density  
For example, at a magnetic field frequency of 1 MHz, the  
maximum allowable magnetic field of 0.2 kgauss induces a  
voltage of 0.25 V at the receiving coil. This is about 50% of the  
sensing threshold and does not cause a faulty output transition.  
Similarly, if such an event occurs during a transmitted pulse  
(and is of the worst-case polarity), it reduces the received pulse  
from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing  
threshold of the decoder.  
Rev. 0 | Page 20 of 24  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
The preceding magnetic flux density values correspond  
Dynamic I/O current is consumed only when operating a channel  
at speeds higher than the refresh rate of fr. The dynamic current  
of each channel is determined by its data rate. Figure 21 shows the  
current for a channel in the forward direction, meaning that the  
input is on the VDD1 side of the part. Figure 22 shows the current  
for a channel in the reverse direction, meaning that the input is on  
the VISO side of the part. Both figures assume a typical 15 pF load.  
to specific current magnitudes at given distances from the  
ADuM640x transformers. Figure 28 expresses these allowable  
current magnitudes as a function of frequency for selected  
distances. As shown in Figure 28, the ADuM640x are extremely  
immune and can be affected only by extremely large currents  
operated at high frequency very close to the component. For  
the 1 MHz example, a 0.5 kA current placed 5 mm away from  
the ADuM640x is required to affect component operation.  
1k  
The following relationship allows the total IDD1 current to be  
calculated:  
I
DD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4  
(1)  
DISTANCE = 1m  
where:  
100  
I
I
DD1 is the total supply input current.  
CHn is the current drawn by a single channel determined from  
10  
Figure 21 or Figure 22, depending on channel direction.  
ISO is the current drawn by the secondary side external load.  
DISTANCE = 100mm  
I
E is the power supply efficiency at 100 mA load from Figure 13  
1
at the VISO and VDD1 condition of interest.  
DISTANCE = 5mm  
The maximum external load can be calculated by subtracting  
the dynamic output load from the maximum allowable load.  
0.1  
I
ISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4  
where:  
ISO (LOAD) is the current available to supply an external secondary  
side load.  
ISO (MAX) is the maximum external secondary side load current  
available at VISO  
ISO (D)n is the dynamic load current drawn from VISO by an input  
(2)  
0.01  
1k  
10k  
100k  
1M  
10M  
100M  
MAGNETIC FIELD FREQUENCY (Hz)  
I
Figure 28. Maximum Allowable Current for  
Various Current-to-ADuM640x Spacings  
I
Note that, in combinations of strong magnetic field and high  
frequency, any loops formed by PCB traces can induce error  
voltages sufficiently large to trigger the thresholds of succeeding  
circuitry. Exercise care in the layout of such traces to avoid this  
possibility.  
.
I
or output channel, as shown in Figure 23 and Figure 24.  
The preceding analysis assumes a 15 pF capacitive load on each  
data output. If the capacitive load is larger than 15 pF, the additional  
current must be included in the analysis of IDD1 and IISO (LOAD)  
POWER CONSUMPTION  
.
The VDD1 power supply input provides power to the iCoupler  
data channels, as well as to the power converter. For this reason,  
the quiescent currents drawn by the data converter and the  
primary and secondary I/O channels cannot be determined  
separately. All of these quiescent power demands have been  
combined into the IDD1 (Q) current, as shown in Figure 29. The  
total IDD1 supply current is equal to the sum of the quiescent  
operating current; the dynamic current, IDD1 (D), demanded by  
the I/O channels; and any external IISO load.  
POWER CONSIDERATIONS  
The ADuM640x power input, data input channels on the  
primary side, and data channels on the secondary side are all  
protected from premature operation by UVLO circuitry. Below  
the minimum operating voltage, the power converter holds its  
oscillator inactive and all input channel drivers and refresh  
circuits are idle. Outputs remain in a high impedance state to  
prevent transmission of undefined states during power-up and  
power-down operations.  
I
I
ISO  
DD1(Q)  
E
During application of power to VDD1, the primary side circuitry  
is held idle until the UVLO preset voltage is reached. At that  
time, the data channels initialize to their default low output  
state until they receive data pulses from the secondary side.  
CONVERTER  
PRIMARY  
CONVERTER  
SECONDARY  
I
DD1(D)  
I
I
ISO(D)  
DDP(D)  
PRIMARY  
DATA  
INPUT/OUTPUT  
4-CHANNEL  
SECONDARY  
DATA  
INPUT/OUTPUT  
4-CHANNEL  
Figure 29. Power Consumption Within the ADuM640x  
Rev. 0 | Page 21 of 24  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
When the primary side is above the UVLO threshold, the data  
input channels sample their inputs and begin sending encoded  
pulses to the inactive secondary output channels. The outputs  
on the primary side remain in their default low state because no  
data comes from the secondary side inputs until secondary power  
is established. The primary side oscillator also begins to operate,  
transferring power to the secondary power circuits. The secondary  
Accelerated life testing is performed using voltage levels higher  
than the rated continuous working voltage. Acceleration factors  
for several operating conditions are determined, allowing calcu-  
lation of the time to failure at the working voltage of interest.  
The values shown in Table 20 summarize the peak voltages for  
50 years of service life in several operating conditions. In many  
cases, the working voltage approved by agency testing is higher  
than the 50-year service life voltage. Operation at working  
voltages higher than the service life voltage listed leads to  
premature insulation failure.  
V
ISO voltage is below its UVLO limit at this point; the regulation  
control signal from the secondary is not being generated. The  
primary side power oscillator is allowed to free run in this  
circumstance, supplying the maximum amount of power to  
the secondary, until the secondary voltage rises to its regulation  
The insulation lifetime of the ADuM640x depends on the voltage  
waveform type imposed across the isolation barrier. The iCoupler  
insulation structure degrades at different rates, depending on  
whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30,  
Figure 31, and Figure 32 illustrate these different isolation  
voltage waveforms.  
setpoint. This creates a large inrush current transient at VDD1  
When the regulation point is reached, the regulation control  
.
circuit produces the regulation control signal that modulates  
the oscillator on the primary side. The VDD1 current is reduced  
and is then proportional to the load current. The inrush current  
is less than the short-circuit current shown in Figure 16. The  
duration of the inrush depends on the VISO loading conditions  
and the current available at the VDD1 pin.  
Bipolar ac voltage is the most stringent environment. A 50-year  
operating lifetime under the bipolar ac condition determines  
the Analog Devices recommended maximum working voltage.  
In the case of unipolar ac or dc voltage, the stress on the insulation  
is significantly lower. This allows operation at higher working  
voltages while still achieving a 50-year service life. The working  
voltages listed in Table 20 can be applied while maintaining the  
50-year minimum lifetime, provided the voltage conforms to  
either the unipolar ac or dc voltage cases. Any cross-insulation  
voltage waveform that does not conform to Figure 31 or Figure 32  
should be treated as a bipolar ac waveform, and its peak voltage  
should be limited to the 50-year lifetime voltage value listed  
in Table 20.  
As the secondary side converter begins to accept power from  
the primary, the VISO voltage starts to rise. When the secondary  
side UVLO is reached, the secondary side outputs are initialized to  
their default low state until data is received from the corresponding  
primary side input. It can take up to 1 μs after the secondary side is  
initialized for the state of the output to correlate with the primary  
side input.  
Secondary side inputs sample their state and transmit it to the  
primary side. Outputs are valid about 1 μs after the secondary  
side becomes active.  
RATED PEAK VOLTAGE  
Because the rate of charge of the secondary side power supply is  
dependent on loading conditions, the input voltage, and the output  
voltage level selected, take care with the design to allow the  
converter sufficient time to stabilize before valid data is required.  
0V  
Figure 30. Bipolar AC Waveform  
When power is removed from VDD1, the primary side converter  
and coupler shut down when the UVLO level is reached. The  
secondary side stops receiving power and starts to discharge.  
The outputs on the secondary side hold the last state that they  
received from the primary side. Either the UVLO level is reached  
and the outputs are placed in their high impedance state, or the  
outputs detect a lack of activity from the primary side inputs  
and the outputs are set to their default low value before the  
secondary power reaches UVLO.  
RATED PEAK VOLTAGE  
0V  
Figure 31. DC Waveform  
RATED PEAK VOLTAGE  
0V  
INSULATION LIFETIME  
NOTES  
1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION  
PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE  
WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE.  
THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE  
VOLTAGE CANNOT CROSS 0V.  
All insulation structures eventually break down when subjected  
to voltage stress over a sufficiently long period. The rate of insu-  
lation degradation is dependent on the characteristics of the  
voltage waveform applied across the insulation. Analog Devices  
conducts an extensive set of evaluations to determine the  
lifetime of the insulation structure within the ADuM640x.  
Figure 32. Unipolar AC Waveform  
Rev. 0 | Page 22 of 24  
 
 
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
OUTLINE DIMENSIONS  
10.50 (0.4134)  
10.10 (0.3976)  
16  
1
9
7.60 (0.2992)  
7.40 (0.2913)  
10.65 (0.4193)  
8
10.00 (0.3937)  
0.75 (0.0295)  
0.25 (0.  
0098)  
1.27 (0.0500)  
BSC  
45°  
2.65 (0.1043)  
2.35 (0.0925)  
0.30 (0.0118)  
0.10 (0.0039)  
8°  
0°  
COPLANARITY  
0.10  
SEATING  
PLANE  
0.51 (0.0201)  
0.31 (0.0122)  
1.27 (0.0500)  
0.40 (0.0157)  
0.33 (0.0130)  
0.20 (0.0079)  
COMPLIANT TO JEDEC STANDARDS MS-013-AA  
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS  
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR  
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.  
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]  
Wide Body (RW-16)  
Dimensions shown in millimeters and (inches)  
ORDERING GUIDE  
Number  
Number  
Maximum Maximum  
Maximum  
of Inputs, of Inputs, Data Rate Propagation  
Pulse Width  
Temperature Package  
Package  
Option  
Model  
VDD1 Side VISO Side  
(Mbps)  
Delay, 5 V (ns) Distortion (ns) Range (°C)  
Description  
ADuM6400ARWZ1, 2  
ADuM6400CRWZ1, 2  
ADuM6401ARWZ1, 2  
ADuM6401CRWZ1, 2  
ADuM6402ARWZ1, 2  
ADuM6402CRWZ1, 2  
ADuM6403ARWZ1, 2  
ADuM6403CRWZ1, 2  
ADuM6404ARWZ1, 2  
ADuM6404CRWZ1, 2  
4
4
3
3
2
2
1
1
0
0
0
0
1
1
2
2
3
3
4
4
1
25  
1
25  
1
25  
1
25  
1
25  
100  
60  
40  
6
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
−40 to +105  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
16-Lead SOIC_W RW-16  
100  
60  
40  
6
100  
60  
40  
6
100  
60  
40  
6
100  
60  
40  
6
1 Tape and reel are available. The addition of an RL suffix designates a 13-inch (1,000 units) tape and reel option.  
2 Z = RoHS Compliant Part.  
Rev. 0 | Page 23 of 24  
 
 
 
ADuM6400/ADuM6401/ADuM6402/ADuM6403/ADuM6404  
NOTES  
©2009 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D08141-0-5/09(0)  
Rev. 0 | Page 24 of 24  
 
 

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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