ADV212BBCZ-150 [ADI]
JPEG 2000 Video Codec; JPEG 2000视频编解码器
| 型号： | ADV212BBCZ-150 |
| 厂家： | 
ADI |
| 描述： | JPEG 2000 Video Codec |
| 文件： | 总44页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JPEG 2000 Video Codec
ADV212
FEATURES
GENERAL DESCRIPTION
Complete single-chip JPEG 2000 compression and
decompression solution for video and still images
Identical in pinout and footprint to the ADV202 and
supports all the functionality of the ADV202
Power reduction of at least 30% compared with ADV202
JTAG/boundary scan support
Patented SURF® (spatial ultraefficient recursive filtering)
technology enables low power, low cost wavelet-based
compression
The ADV212 is a single-chip JPEG 2000 codec targeted for
video and high bandwidth image compression applications that
can benefit from the enhanced quality and features provided by
the JPEG 2000 (J2K)—ISO/IEC15444-1 image compression
standard. The part implements the computationally intensive
operations of the JPEG 2000 image compression standard and
provides fully compliant code-stream generation for most
applications.
Supports both 9/7 and 5/3 wavelet transforms with up to
6 levels of transform
The dedicated video port of the ADV212 provides glueless con-
nection to common digital video standards such as ITU-R BT.656,
SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 (625p),
SMPTE 274M (1080i), or SMPTE 296M (720p). A variety of
other high speed, synchronous pixel and video formats can also
be supported by using the programmable framing and
validation signals.
Video interface directly supporting ITU-R BT.656,
SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M
(525p), and ITU-R BT.1358 (625p), or any video format with
a maximum input rate of 65 MSPS for irreversible mode or
40 MSPS for reversible mode
Programmable tile/image size with widths up to 4096 pixels
in single-component mode; maximum tile/image height:
4096 pixels
2 or more ADV212s can be combined to support full-frame
SMPTE 274M HDTV (1080i) or SMPTE 296M (720p)
Flexible, asynchronous SRAM-style host interface allows glue-
less connection to most 16-/32-bit microcontrollers and ASICs
2.5 V or 3.3 V input/output and 1.5 V core supply
12 mm × 12 mm, 121-ball CSPBGA with a speed grade of
115 MHz, or 13 mm × 13 mm, 144-ball CSPBGA with a
speed grade of 150 MHz
The ADV212 is an upgrade version of the ADV202 that is
identical in pinout and footprint. It supports all the functionality
of the ADV202 and has the following additional options:
•
•
JTAG/boundary scan support
Power reduction of at least 30% compared with the
ADV202
APPLICATIONS
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Digital cinema systems
Professional video editing and recording
Digital still cameras
Digital camcorders
FUNCTIONAL BLOCK DIAGRAM
WAVELET
PIXEL I/F
HOST I/F
EC1
EC2
EC3
PIXEL I/F
ENGINE
EXTERNAL
DMA CTRL
PIXEL FIFO
CODE FIFO
ATTR FIFO
INTERNAL BUS AND DMA ENGINE
EMBEDDED
RISC
PROCESSOR
SYSTEM
RAM
ROM
ADV212
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADV212
TABLE OF CONTENTS
Memory System.......................................................................... 25
Internal DMA Engine................................................................ 25
ADV212 Interface .......................................................................... 26
Video Interface (VDATA Bus).................................................. 26
Host Interface (HDATA Bus) ................................................... 26
Direct and Indirect Registers.................................................... 26
Control Access Registers ........................................................... 27
Pin Configuration and Bus Sizes/Modes ................................ 27
Stage Register.............................................................................. 27
JDATA Mode............................................................................... 27
External DMA Engine ............................................................... 27
Internal Registers............................................................................ 28
Direct Registers........................................................................... 28
Indirect Registers........................................................................ 29
PLL ............................................................................................... 30
Hardware Boot............................................................................ 31
Video Input Formats...................................................................... 32
Applications..................................................................................... 34
Encode—Multichip Mode......................................................... 34
Decode—Multichip Master/Slave ............................................ 35
Digital Still Camera/Camcorder .............................................. 36
Encode/Decode SDTV Video Application ............................. 37
32-Bit Host Application............................................................. 38
HIPI (Host Interface—Pixel Interface) ................................... 39
JDATA Interface ......................................................................... 40
Outline Dimensions....................................................................... 41
Ordering Guide .......................................................................... 42
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
JPEG 2000 Feature Support......................................................... 3
Specificatons...................................................................................... 4
Supply Voltages and Current ...................................................... 4
Input/Output Specifications........................................................ 4
RESET
Clock and
Specifications................................................ 5
Normal Host Mode—Write Operation ..................................... 6
Normal Host Mode—Read Operation ...................................... 7
DREQ DACK
/
DMA Mode—Single FIFO Write Operation .. 8
DMA Mode—Single FIFO Read Operation . 10
DREQ DACK
/
External DMA Mode—FIFO Write, Burst Mode .................. 12
External DMA Mode—FIFO Read, Burst Mode ................... 13
Streaming Mode (JDATA)—FIFO Read/Write...................... 14
VDATA Mode Timing............................................................... 15
Raw Pixel Mode Timing ............................................................ 17
JTAG Timing............................................................................... 18
Absolute Maximum Ratings.......................................................... 19
Thermal Resistance .................................................................... 19
ESD Caution................................................................................ 19
Pin Configurations and Function Descriptions ......................... 20
Theory of Operation ...................................................................... 25
Wavelet Engine ........................................................................... 25
Entropy Codecs........................................................................... 25
Embedded Processor System .................................................... 25
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
ADV212
The ADV212 can process images at a rate of 40 MSPS in reversible
mode and at higher rates when used in irreversible mode. The
ADV212 contains a dedicated wavelet transform engine, three
entropy codecs, an on-board memory system, and an embedded
reduced instruction set computer (RISC) processor that can
provide a complete JPEG 2000 compression/decompression
solution.
JPEG 2000 FEATURE SUPPORT
The ADV212 supports a broad set of features that are included
in Part 1 of the JPEG 2000 standard (ISO/IEC 15444). See
ADV212 User’s Guide for information on the JPEG 2000 features
that the ADV212 currently supports.
Depending on the particular application requirements, the
ADV212 can provide varying levels of JPEG 2000 compression
support. It can provide raw code block and attribute data output,
which allows the host software to have complete control over
the generation of the JPEG 2000 code stream and other aspects
of the compression process such as bit-rate control. Otherwise,
the ADV212 can create a complete, fully compliant JPEG 2000
code stream (J2C) and enhanced file formats such as JP2.
The wavelet processor supports the 9/7 irreversible wavelet
transform and the 5/3 wavelet transform in reversible and
irreversible modes. The entropy codecs support all features in
the JPEG 2000 Part 1 specification, except maximum shift
region of interest (ROI).
The ADV212 operates on a rectangular array of pixel samples
called a tile. A tile can contain a complete image, up to the
maximum supported size, or some portion of an image. The
maximum horizontal tile size supported depends on the wavelet
transform selected and the number of samples in the tile.
Images larger than the ADV212’s maximum tile size can be
broken into individual tiles and then sent sequentially to the
chip while maintaining a single, fully compliant JPEG 2000
code stream for the entire image.
Rev. 0 | Page 3 of 44
ADV212
SPECIFICATONS
Specifications apply to IOVDD = 2.5 V or 3.3 V over operating temperature range, unless otherwise specified.
SUPPLY VOLTAGES AND CURRENT
Table 1.
Parameter
Mnemonic
VDD
IOVDD
IOVDD
VIN
Min
Typ
1.5
2.5
3.3
Max
1.575
2.625
3.465
VDDI/O + 0.3
+85
30
440
320
290
Unit
V
V
V
V
DC Supply Voltage, Core
1.425
2.375
3.135
−0.3
−40
DC Supply Voltage, Input/Output
DC Supply Voltage, Input/Output
Input Range
Operating Ambient Temperature Range in Free Air
Static Current1
Dynamic Current, Core (JCLK Frequency = 150 MHz)2
Dynamic Current, Core (JCLK Frequency = 108 MHz)
Dynamic Current, Core (JCLK Frequency = 81 MHz)
Dynamic Current, Input/Output
T
IDD
+25
15
380
280
210
40
°C
mA
mA
mA
mA
mA
50
1 No clock or input/output activity.
2 ADV212-150 only.
INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
Mnemonic
Min
2.2
1.9
Typ
Max
Unit
V
V
V
V
Test Conditions
VDD = maximum
VDD = maximum
VDD = minimum
VDD = minimum, IOH = −0.5 mA
VDD = minimum, IOH = −0.5 mA
VDD = minimum, IOL = +2 mA
VDD = maximum, VIN = VDD
VDD = maximum, VIN = 0 V
VDD = maximum, VIN = VDD
VDD = maximum, VIN = 0V
High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
High Level Three-State Leakage Current
Low Level Three-State Leakage Current
Input Pin Capacitance
VIH (3.3 V)
VIH (2.5 V)
VIL (3.3 V, 2.5 V)
VOH (3.3 V)
VOH (2.5 V)
VOL (3.3 V, 2.5 V)
IIH
IIL
IOZH
IOZL
CI
0.6
2.4
2.0
V
V
0.4
1.0
1.0
1.0
1.0
8
μA
μA
μA
μA
pF
pF
Output Pin Capacitance
CO
8
Rev. 0 | Page 4 of 44
ADV212
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter
Mnemonic
Min
13.3
10
6
Typ
Max
100
75.18
Unit
MCLK Period
tMCLK
fMCLK
tMCLKL
tMCLKH
tVCLK
ns
MHz
ns
ns
ns
MHz
ns
ns
MCLK Frequency
MCLK Width Low
MCLK Width High
VCLK Period
VCLK Frequency
VCLK Width Low
VCLK Width High
RESET Width Low
6
13.4
20
5
5
5
50
74.60
fVCLK
tVCLKL
tVCLKH
tRESET
MCLK cycles1
1 For a definition of MCLK, see Figure 32.
tMCLK
tMCLKL
tMCLKH
MCLK
VCLK
tVCLK
tVCLKL
tVCLKH
Figure 2. Input Clock
Rev. 0 | Page 5 of 44
ADV212
NORMAL HOST MODE—WRITE OPERATION
Table 4.
Parameter
Mnemonic
Min
Typ
Max
Unit
WE to ACK, Direct Registers and FIFO Accesses
t
t
ACK (direct)
5
1.5 × JCLK + 7.0
ns
WE to ACK, Indirect Registers
ACK (indirect)
5
2.5 × JCLK + 7.0
ns
Data Setup
Data Hold
Address Setup
Address Hold
tSD
tHD
tSA
tHA
tSC
3.0
1.5
2
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS to WE Setup
0
CS Hold
tHC
tWH
tWL
tWCYC
0
Write Inactive Pulse Width (Minimum Time Until Next WE Pulse)
Write Active Pulse Width
Write Cycle Time
2.5 JCLK1
2.5 JCLK
5 JCLK
1 For a definition of JCLK, see Figure 32.
tSA
tHA
ADDR
tSC
tHC
CS
tWCYC
tWL
tWH
WE
tACK
ACK
tHD
tSD
VALID
HDATA
Figure 3. Normal Host Mode—Write Operation
Rev. 0 | Page 6 of 44
ADV212
NORMAL HOST MODE—READ OPERATION
Table 5.
Parameter
Mnemonic
Min
Typ
Max
Unit
RD to ACK, Direct Registers and FIFO Accesses
t
t
ACK (direct)1
5
1.5 × JCLK + 7.0
ns
RD to ACK, Indirect Registers
ACK (indirect)1
10.5 × JCLK
15.5 × JCLK + 7.0
ns
Read Access Time, Direct Registers
Read Access Time, Indirect Registers
Data Hold
tDRD (direct)
tDRD (indirect)
tHZRD
tSC
5
1.5 × JCLK + 7.0
15.5 × JCLK + 7.0
8.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10.5 × JCLK
2
0
CS to RD Setup
Address Setup
CS Hold
tSA
tHC
2
0
Address Hold
tHA
tRH
tRL
2
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
2.5 JCLK 2
2.5 JCLK
5.0 JCLK
tRCYC
1
ACK
RD
rising transition. A
Timing relationship between
falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to
ACK
RD
minimum of three JCLK cycles is recommended between
2 For a definition of JCLK, see Figure 32.
assert and
deassert.
tSA
tHA
ADDR
tSC
tHC
CS
tRCYC
tRL
tRH
RD
ACK
tACK
tDRD
tHZRD
VALID
HDATA
Figure 4. Normal Host Mode—Read Operation
Rev. 0 | Page 7 of 44
ADV212
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
Mnemonic
DREQPULSE
tDREQ
Min
Typ
Max
Unit
ns
DREQ Pulse Width
1 JCLK1
15 JCLK
DACK Assert to Subsequent DREQ Delay
2.5 JCLK
3.5 × JCLK + 8.5
ns
WE to DACK Setup
tWE
0
ns
SU
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
tSU
2
ns
ns
ns
ns
ns
tHD
2
DACKLO
DACKHI
2 JCLK
2 JCLK
0
DACK Deassert Pulse Width
WE Hold After DACK Deassert
tWE
HD
WE Assert to FSRQ Deassert (FIFO Full)
DACK to DREQ Deassert (DR × PULS = 0)
WFSRQ
1.5 JCLK
2.5 JCLK
2.5 × JCLK + 7.5
3.5 × JCLK + 9.0
ns
ns
tDREQ
RTN
1 For a definition of JCLK, see Figure 32.
DREQ
PULSE
tDREQ
DREQ
DACK
DACK
HI
DACK
LO
tWESU
tWEHD
WE
tHD
tSU
HDATA
0
1
2
3
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 5. Single Write for
/
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
tDREQRTN
DREQ
DACK
DACK
HI
DACK
LO
tWESU
tWEHD
WE
tHD
tSU
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 6. Single Write for
/
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
Rev. 0 | Page 8 of 44
ADV212
DREQ
PULSE
tDREQ
DREQ
DACK
HI
DACK
LO
DACK
WEFB
tWESU
tWEHD
tHD
tSU
0
1
2
HDATA
Figure 7. Single Write Cycle for Fly-By DMA Mode
DREQ
(
Pulse Width Is Programmable)
FCS0
RD
WFSRQ
FIFO NOT FULL
FSRQ0
HDATA
FIFO FULL
0
1
2
tSU
tHD
NOT WRITTEN TO FIFO
Figure 8. Single Write Access for DCS DMA Mode
Rev. 0 | Page 9 of 44
ADV212
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
Mnemonic
DREQPULSE
tDREQ
Min
Typ
Max
Unit
ns
1
DREQ Pulse Width
1 JCLK
15 JCLK
DACK Assert to Subsequent DREQ Delay
2.5 JCLK
3.5 × JCLK + 9.0
ns
RD to DACK Setup
DACK to Data Valid
tRD
0
ns
ns
SU
tRD
2.5
11
Data Hold
tHD
DACKLO
DACKHI
1.5
ns
ns
ns
ns
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold after DACK Deassert
2 JCLK
2 JCLK
0
tRD
HD
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
RDFSRQ
1.5 JCLK
2.5 JCLK
ns
ns
2.5 × JCLK + 9.0
3.5 × JCLK + 9.0
tDREQ
RTN
1 For a definition of JCLK, see Figure 32.
DREQ
PULSE
tDREQ
DREQ
DACK
HI
DACK
LO
DACK
RD
tRDSU
tRDHD
tRD
tHD
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 9. Single Read for
/
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
tDREQRTN
DREQ
DACK
HI
DACK
LO
DACK
RD
tRDSU
tRDHD
tRD
tHD
HDATA
0
1
2
DREQ DACK
DMA Mode for Assigned DMA Channel
Figure 10. Single Read for
/
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
Rev. 0 | Page 10 of 44
ADV212
DREQ
PULSE
tDREQ
DREQ
DACK
DACK
HI
DACK
LO
tRDSU
tRDHD
RDFB
tRD
tHD
HDATA
0
1
2
Figure 11. Single Read Cycle for Fly-By DMA Mode
DREQ
(
Pulse Width Is Programmable)
FCS0
RD
RDFSRQ
FIFO NOT EMPTY
FSRQ0
HDATA
FIFO EMPTY
tHD
tRD
0
1
Figure 12. Single Read Access for DCS DMA Mode
Rev. 0 | Page 11 of 44
ADV212
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
DREQ Pulse Width1
Mnemonic
Min
Typ
Max
Unit
ns
2
DREQPULSE
1 JCLK
15 JCLK
WE to DREQ Deassert (DR × PULS = 0)
tDREQ
2.5 JCLK
0
3.5 × JCLK + 7.5
ns
RTN
DACK to WE Setup
tDACK
ns
SU
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
WEDeassert to Next DREQ
tSU
tHD
WELO
WEHI
2.5
2
1.5 JCLK
1.5 JCLK
2.5 JCLK
ns
ns
ns
ns
ns
tDREQ
4.5 × JCLK + 9.0
WAIT
WE Deassert to DACK Deassert
tWE_DACK
0
ns
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2 For a definition of JCLK, see Figure 32.
DREQ
PULSE
tDREQWAIT
DREQ
DACK
tWE_DACK
tDACKSU
WE
HI
WE
LO
WE
tHD
tSU
HDATA
14
15
0
1
13
DREQ
Figure 13. Burst Write Cycle for
/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
tDREQRTN
tDREQWAIT
DREQ
DACK
tWE_DACK
tDACKSU
WE
LO
WE
HI
WE
tHD
tSU
0
1
13
14
15
HDATA
DREQ
/DMA Mode for Assigned DMA Channel
Figure 14. Burst Write Cycle for
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
tDREQRTN
tDREQWAIT
DREQ
DACK
tWE_DACK
tDACKSU
WE
LO
WE
HI
WEFB
tHD
tSU
0
1
13
14
15
HDATA
Figure 15. Burst Write Cycle for Fly-By DMA Mode
Rev. 0 | Page 12 of 44
ADV212
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
DREQ Pulse Width1
Mnemonic
Min
Typ
Max
Unit
ns
2
DREQPULSE
1 JCLK
15 JCLK
RD to DREQ Deassert (DR × PULS = 0)
tDREQ
2.5 JCLK
0
3.5 × JCLK + 7.5
ns
RTN
DACK to RD Setup
RD to Data Valid
tDACK
ns
ns
SU
tRD
2.5
9.7
Data Hold
tHD
RDLO
RDHI
2.5
ns
ns
ns
ns
RD Assert Pulse Width
RD Deassert Pulse Width
RD Deassert to Next DREQ
1.5 JCLK
1.5 JCLK
2.5 JCLK
tDREQ
3.5 × JCLK + 7.5
WAIT
RD Deassert to DACK Deassert
tRD_DACK
0
ns
1 Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2 For a definition of JCLK, see Figure 32.
tDREQPULSE
tDREQWAIT
DREQ
tRD_DACK
DACK
tDACKSU
RD
RD
HI
LO
RD
tHD
0
1
13
14
15
HDATA
tRD
Figure 16. Burst Read Cycle for
DREQ DACK
/
DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0
tDREQWAIT
DREQ
DACK
tRD_DACK
tDREQRTN
tDACKSU
RD
RD
HI
LO
RD
tHD
0
1
13
14
15
HDATA
tRD
Figure 17. Burst Read Cycle for
(EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
tDREQRTN
DREQ DACK
/
DMA Mode for Assigned DMA Channel
tDREQWAIT
DREQ
DACK
tRD_DACK
tDACKSU
RDFB
tHD
HDATA
0
1
13
14
15
tRD
Figure 18. Burst Read Cycle for Fly-By DMA Mode
RD
Rev. 0 | Page 13 of 44
ADV212
STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10.
Parameter
Mnemonic
JDATATD
VALIDTD
HOLDSU
HOLDHD
JDATASU
JDATAHD
Min
Typ
Max
Unit
ns
ns
ns
ns
MCLK to JDATA Valid
1.5 JCLK1
2.5 × JCLK + 9.5
2.5 × JCLK + 8.0
MCLK to VALID Assert/Deassert
HOLD Setup to Rising MCLK
HOLD Hold from Rising MCLK
JDATA Setup to Rising MCLK
JDATA Hold from Rising MCLK
1.5 JCLK
3
3
3
3
ns
ns
1 For a definition of JCLK, see Figure 32.
MCLK
JDATA
JDATA
HD
TD
JDATA
VALID
HOLD
JDATA
SU
VALID
TD
HOLD
HD
HOLD
SU
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
MCLK
JDATA
HD
JDATA
SU
JDATA
VALID
TD
VALID
HOLD
HOLD
HD
HOLD
SU
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
Rev. 0 | Page 14 of 44
ADV212
VDATA MODE TIMING
Table 11.
Parameter
Mnemonic
VDATATD
VDATASU
VDATAHD
HSYNCSU
HSYNCHD
HSYNCTD
VSYNCSU
VSYNCHD
VSYNCTD
FIELDSU
Min
Typ
Max
Unit
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
3
4
12
12
12
3
4
4
3
FIELDHD
FIELDTD
SYNC DELAY
Decode Slave Data Sync Delay
(HSYNC Low to First 0xFF of EAV/SAV Code)
Decode Slave Data Sync Delay
81
VCLK cycles
VCLK cycles
101
(HSYNC Low to First Data for HVF Mode)
1 The sync delay value varies according to the application. Refer to the ADV212 User Guide for more information.
VCLK
VDATA
SU
VDATA
HD
VDATA (IN)
Cr
Y
Cb
Y
FF
00
00
EAV
FF
00
00
SAV
Cb
Y
Cr
Figure 21. Encode Video Mode Timing—CCIR 656 Mode
VCLK
HSYNC
HSYNC
HSYNC
Cb
SU
HD
VDATA (IN)
Cb
Y
Cr
Y
Y
Cr
Y
Figure 22. Encode Video Mode Timing—HVF Mode (HSYNC Timing)
(HSYNC Programmed for Negative Polarity)
VCLK
VSYNC
HD
VSYNC
SU
VSYNC
FIELD
SU
FIELD
HD
FIELD
Figure 23. Encode Video Mode Timing—HVF Mode (VSYNC and FIELD Timing)
(VSYNC and FIELD Programmed for Negative Polarity)
Rev. 0 | Page 15 of 44
ADV212
VCLK
VDATA
TD
VDATA (OUT)
HSYNC (IN)
FF
00
00
EAV
Cb
Y
HSYNC
SU
HSYNC
HD
VSYNC
HD
SYNC DELAY
VSYNC
SU
VSYNC (IN)
FIELD (IN)
FIELD
SU
Figure 24. Decode Video Mode Timing—CCIR 656 Mode, Decode Slave
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
VCLK
VDATA
TD
Cb
Y
Cr
Y
Cb
Y
VDATA (OUT)
HSYNC (IN)
HSYNC
SU
HSYNC
HD
VSYNC
HD
SYNC DELAY
VSYNC
SU
VSYNC (IN)
FIELD (IN)
FIELD
SU
Figure 25. Decode Video Mode Timing—HVF Mode, Decode Slave
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
VCLK
VDATA
TD
VDATA (OUT)
HSYNC (OUT)
VSYNC (OUT)
FF
00
Cr
00
SAV
Cb
Cb
Y
HSYNC
TD
VSYNC
TD
FIELD
TD
FIELD (OUT)
Figure 26. Decode Video Mode Timing—CCIR 656 Mode, Decode Master
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
VCLK
VDATA
TD
Cb
Y
Cr
Y
Cb
Y
Cb
Y
Cr
VDATA (OUT)
HSYNC (OUT)
VSYNC (OUT)
FIELD (OUT)
VSYNC
TD
FIELD
TD
Figure 27. Decode Video Mode Timing—HVF Mode, Decode Master
(HSYNC, VSYNC, and FIELD Programmed to Negative Polarity)
Rev. 0 | Page 16 of 44
ADV212
RAW PIXEL MODE TIMING
Table 12.
Parameter
Mnemonic
VDATATD
VDATASU
VDATAHD
VRDYTD
VFRMSU
VFRMHD
VFRMTD
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
VCLK to PIXELDATA Valid Delay (PIXELDATA Output)
PIXELDATA Setup to Rising VCLK (PIXELDATA Input)
PIXELDATA Hold from Rising VCLK (PIXELDATA Input)
VCLK to VRDY Valid Delay
VFRM Setup to Rising VCLK (VFRAME Input)
VFRM Hold from Rising VCLK (VFRAME Input)
VCLK to VFRM Valid Delay (VFRAME Output)
VSTRB Setup to Rising VCLK
12
4
4
12
12
3
4
VSTRBSU
VSTRBHD
4
3
VSTRB Hold from Rising VCLK
ns
VCLK
VDATA
VDATA
SU
HD
PIXEL DATA (IN)
PIXEL 1
PIXEL 2
PIXEL 3
VFRM
TD
SU
VFRM
HD
VFRM (IN)
VRDY
VRDY (OUT)
VSTRB
HD
VSTRB
SU
VSTRB (IN)
RAW PIXEL MODE—ENCODE
VCLK
VDATA
TD
PIXELDATA (OUT)
PIXEL 1
PIXEL 2
PIXEL 3
VFRM
VRDY
TD
TD
VFRM (OUT)
VRDY (OUT)
VSTRB
HD
VSTRB
SU
VSTRB (IN)
RAW PIXEL MODE—DECODE
Figure 28. Raw Pixel Modes
Rev. 0 | Page 17 of 44
ADV212
JTAG TIMING
Table 13.
Parameter
Mnemonic
TCK
TDISU
Min
134
4.0
4.0
0.0
Typ
Max
Unit
TCK Period
ns
ns
ns
ns
ns
ns
ns
TDI or TMS Setup Time
TDI or TMS Hold Time
TDO Hold Time
TDO Valid
TRST Hold Time
TRST Setup Time
TRST Pulse Width Low
TDIHD
TDOHD
TDOVALID
TRSTHD
TRSTSU
TRSTLO
10.0
4.0
4.0
4
TCK cycles
TCK
TDO
VALID
TDO
HD
TDO
TDI
TDI
TDI
HD
SU
TMS
TRST
HD
TRST
SU
TRST
Figure 29. JTAG Timing
Rev. 0 | Page 18 of 44
ADV212
ABSOLUTE MAXIMUM RATINGS
Table 14.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VDD − Supply Voltage, Core
IOVDD − Supply Voltage,
Input/Output
−0.3 V to +1.65 V
−0.3 V to 3.63 V
Table 15. Thermal Resistance
Package Type
144-Ball ADV212BBCZ
121-Ball ADV212BBCZ
θJA
θJC
Unit
°C/W
°C/W
Storage Temperature [TS]
Reflow Soldering
−65°C to +150°C
22.5
32.8
3.8
7.92
Pb-Free, 121-Ball
Pb-Free, 144-Ball
260°C [20 sec to 40 sec]
260°C [20 sec to 40 sec]
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 19 of 44
ADV212
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12 10
8
6
4
2
1110 9
7 3
8 6 5 4 2 1
9
7
11
5
3
1
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
G
H
J
K
L
M
K
L
BOTTOM VIEW
(Not to Scale)
BOTTOM VIEW
(Not to Scale)
Figure 30.121-Ball Pin Configuration
Figure 31. 144-Ball Pin Configuration
Rev. 0 | Page 20 of 44
ADV212
Table 16. Pin Function Descriptions
121-Ball Package 144-Ball Package
Pins
Used Type
Pin No.
Location
Pin No.
132
131
Location
L12
L11
Mnemonic
MCLK
RESET
Description
119
117
L9
L7
1
1
I
I
System Input Clock. See the PLL section.
Reset. Causes the ADV212 to immediately reset.
CS, RD, WE, DACK0, DACK1, DREQ0, and DREQ1
must be held high when a RESET is applied.
37 to 34,
27 to 25,
16, 15, 24,
14 to 12,
2, 6, 5
D4 to D1,
C5 to C3,
B5, B4, C2,
B3 to B1,
A2, A6, A5
64, 49 to 51, F4, E1 to E3,
37 to 39, 25 D1 to D3,
HDATA
[15:0]
16
I/O
Host Data Bus. With HDATA [23:16],
HDATA [27:24], and HDATA [31:28], these pins
make up the 32-bit wide host data bus. The
async host interface is interfaced together
with ADDR[3:0], CS, WE, RD, and ACK.
Unused HDATA pins should be pulled down
via a 10 kΩ resistor.
to 27, 13 to
15, 2 to 4
C1 to C3,
B1 to B3,
A2 to A4
88, 107,
87, 97
96
H11, K8,
H10, J9
J8
108 to 106,
96
95
J12, J11,
J10, H12
H11
ADDR [3:0]
CS
4
1
I
I
Address Bus for the Host Interface.
Chip Select. This signal is used to qualify
addressed read and write access to the
ADV212 using the host interface.
95
J7
94
H10
WE1
RDFB2
1
1
1
I
Write Enable Used with the Host Interface.
Read Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of WE and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
86
85
H9
H8
84
83
G12
G11
RD1
WEFB3
I
Read Enable Used with the Host Interface.
Write Enable When Fly-By DMA Is Enabled.
Simultaneous assertion of RD and DACK low
activates the HDATA bus, even if the DMA
channels are disabled.
Acknowledge. Used for direct register accesses.
This signal indicates that the last register access
was successful. Due to synchronization issues,
control and status register accesses might incur
an additional delay; therefore, the host software
should wait for acknowledgment from the
ADV212 before attempting another register
access.
ACK
O
Accesses to the FIFOs (external DMA modes),
on the other hand, are guaranteed to occur
immediately, provided that space is available;
therefore, the host software does not need to
wait for ACK before attempting another register
access, provided that the timing constraints
are observed.
If ACK is shared with more than one device, ACK
should be connected to a pull-up resistor (10 kΩ)
and the PLL_HI register, Bit 4, must be set to 1.
76
G10
82
G10
IRQ
1
O
Interrupt. This pin indicates that the ADV212
requires the attention of the host processor.
This pin can be programmed to indicate the
status of the internal interrupt conditions
within the ADV212. The interrupt sources are
enabled via the bits in register EIRQIE.
Rev. 0 | Page 21 of 44
ADV212
121-Ball Package
144-Ball Package
Pins
Used Type
Pin No.
Location
Pin No.
72
Location
Mnemonic
Description
63
F8
F12
DREQ0
1
O
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 0.
FSRQ0
VALID
CFG1
O
O
I
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream.
Polarity of this pin is programmable in the
EDMOD0 register. VALID is always an output.
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
64
F9
71
F11
DACK0
1
I
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ0) has been
acknowledged and that the data transfer can
proceed. This pin must be held high at all
times if the DMA interface is not used, even if
the DMA channels are disabled.
HOLD
FCS0
I
External Hold Indication for JDATA Input/Output
Stream. Polarity is programmable in the
EDMOD0 register. This pin is always an input.
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 0
(asynchronous mode).
I
65
F10
70
F10
DREQ1
1
O
Data Request for External DMA Interface.
Indicates that the ADV212 is ready to
send/receive data to/from the FIFO assigned
to DMA Channel 1.
FSRQ1
CFG2
O
I
FIFO Service Request. Used in DCS-DMA
Mode. Service request from the FIFO assigned
to Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on
reset to determine the boot configuration of
the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
75
G9
69
F9
DACK1
1
I
Data Acknowledge for External DMA Interface.
Signal from the host CPU, which indicates that
the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed.
This pin must be held high at all times unless a
DMA or JDATA access is occurring. This pin
must be held high at all times if the DMA
interface is not used, even if the DMA channels
are disabled.
FCS1
I
FIFO Chip Select. Used in DCS-DMA Mode.
Chip select for the FIFO assigned to Channel 1
(asynchronous mode).
90 to 92, 78
79 to 81, 70
J2 to J4, H1
111,97 to 99 K3, J1 to J3
HDATA
[31:28]
JDATA [7:4]
HDATA
[27:24]
4
4
I/O
Host Expansion Bus.
I/O
I/O
JDATA Bus (JDATA Mode).
Host Expansion Bus.
H2 to H4, G4 100, 85 to 87 J4, H1 to H3
JDATA [3:0]
I/O
JDATA Bus (JDATA Mode).
Rev. 0 | Page 22 of 44
ADV212
121-Ball Package
144-Ball Package
Pins
Used Type
Pin No.
Location
Pin No.
88,73 to 75
Location
Mnemonic
Description
69, 68,
59, 58
57, 46 to 48 F2, E2, E3,
E4
G3, G2,
F4, F3
H4, G1 to G3 HDATA
[23:20]
4
I/O
I/O
I/O
Host Expansion Bus.
76, 61 to 63 G4, F1 to F3 HDATA
[19:16]
4
Host Expansion Bus.
VDATA
[15:12]
Video Data. Only used for raw pixel video
mode. Unused pins should be pulled down via
a 10 kΩ resistor.
112
113
114
L2
L3
L4
134
135
136
M2
M3
M4
SCOMM7
SCOMM6
SCOMM5
8
I/O
I/O
I/O
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. This pin must be used
in multiple chip mode to align the outputs of
two or more ADV212s. For details, see the
Applications section and the AN-796
Application Note. When not used, this pin
should be tied low via a 10 kΩ resistor.
100
K1
121
L1
SCOMM4
O
LCODE Output in Encode Mode. When LCODE
is enabled, the output on this pin indicates on
a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit
interface, such as JDATA, LCODE is asserted for
four consecutive bytes and is enabled
by default.
101
K2
122
L2
SCOMM3
SCOMM2
SCOMM1
SCOMM0
VCLK
I
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. For internal use only.
This pin should be tied low via a 10 kΩ resistor.
Serial Communication. This pin should be tied
low via a10 kΩ resistor.
115
L5
123
L3
O
I
103
K4
109
K1
K2
E12
102
K3
110
O
I
53
E9
60
1
Video Data Clock. This pin must be supplied if
video data is input/output on the VDATA bus.
44, 43, 29,
31, 32, 18 to C7, C9, C10, 34 to 36,
20, 22, 21, 7, B7, B8, B9,
10
D11, D10,
46 to 48,
D10 to D12, VDATA
12
I/O
Video Data. Unused pins should be pulled
down via a 10 kΩ resistor.
C10 to C12,
B10 to B12,
A9 to A11
[11:0]
22 to 24,
9 to 11
B11, B10,
A7, A10
41
D8
58
E10
VSYNC
VFRM
1
I/O
Vertical Sync for Video Mode.
Raw Pixel Mode Framing Signal. When this pin
is asserted high, it indicates the first sample of
a tile.
42
54
D9
59
57
E11
E9
HSYNC
VRDY
FIELD
VSTRB
TCK
1
1
I/O
O
I/O
I
Horizontal Sync for Video Mode.
Raw Pixel Mode Ready Signal.
Field Sync for Video Mode.
Raw Pixel Mode Transfer Strobe.
JTAG Clock. If not used, this pin should be
connected to ground via a pull-down resistor.
JTAG Reset. If the JTAG is used, this pin must
be toggled low to high. If JTAG is not used, this
pin must be held low.
E10
94
J6
120
119
K12
K11
1
1
I
108
K9
TRS
I
Rev. 0 | Page 23 of 44
ADV212
121-Ball Package
144-Ball Package
Pins
Used Type
Pin No.
Location
Pin No.
Location
Mnemonic
Description
98
J10
118
141
130
K10
TMS
1
1
1
I
JTAG Mode Select. If JTAG is used, connect
10 kΩ pull-up resistor to this pin. If not used,
this pin should be connected to ground via a
pull-down resistor.
JTAG Serial Data Input. If JTAG is used, connect
a 10 kΩ pull-up resistor to this pin. If JTAG is
not used, this pin should be connected to
ground via a pull-down resistor.
116
109
L6
M9
TDI
I
K10
L10
TDO
VDD
O
V
JTAG Serial Data Output. If this pin is not used,
do not connect it.
Positive Supply for Core.
3, 8, 40, 84,
120
A3, A8, D7,
H7, L10
18, 19, 30,
31, 42, 43,
102, 103,
114, 115,
126, 127,
142
B6, B7, C6,
C7, D6, D7,
J6, J7, K6,
K7, L6, L7,
M10
1, 4, 9,11,
23, 33, 39,
A1, A4, A9,
A11, C1,
1, 5 to 8, 12, A1, A5 to
DGND
GND
Ground.
17, 20, 29,
A8, A12, B5,
45, 49 to 51, C11, D6, E1, 32, 41, 44,
55, 56, 60 to E5 to E7,
62, 66, 67, E11, F1, F5
71 to 73, 77, to F7, F11,
B8, C5, C8,
52 to 56, 65 D5, D8, E4
to 68, 77 to to E8, F5 to
81, 89 to 93, F8, G5 to
83, 89,99,
110, 111,
118, 121
G1, G5 to
G7, G11, H6, 105, 113,
J1, J11, K11, 116, 125,
L1, L8, L11
101, 104,
G9, H5 to
H9, J5, J8,
J9, K5, K8,
L5, L8, M1,
M5 to M8,
M11, M12
128, 133,
137 to 140,
143, 144
17, 28, 30,
38, 52, 74,
82, 93, 104
to 106
B6, C6, C8,
D5, E8, G8,
H5, J5, K5 to 112, 117,
K7 124, 129
16, 21, 28,
33, 40, 45,
B4, B9, C4,
C9, D4, D9,
K4, K9, L4,
L9
IOVDD
V
Positive Supply for Input/Output.
1
RD
WE
signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212
In fly-by mode DMA, the function of the
with the use of a single strobe.
and
2
3
RDFB
WEFB
WE
signal (
In encode mode with fly-by DMA, the host can use the
In decode mode with fly-by DMA, the host can use the
pin) to simultaneously read from the ADV212 and write to an external device like memory.
RD
signal ( pin) to simultaneously read from the external device and write to the ADV212.
Rev. 0 | Page 24 of 44
ADV212
THEORY OF OPERATION
The input video or pixel data is passed on to the ADV212’s pixel
interface, and samples are deinterleaved and passed on to the
wavelet engine, which decomposes each tile or frame into
subbands using the 5/3 or 9/7 filters. The resultant wavelet
coefficients are then written to the internal memory. The
entropy codecs code the image data so that it conforms to the
JPEG 2000 standard. An internal DMA provides high
bandwidth memory-to-memory transfers, as well as high
performance transfers between functional blocks and memory.
ENTROPY CODECS
The entropy codec block performs context modeling and
arithmetic coding on a code block of the wavelet coefficients.
Additionally, this block also performs the distortion metric
calculations during compression that are required for optimal
rate and distortion performance. Because the entropy coding
process is the most computationally intensive operation in the
JPEG 2000 compression process, three dedicated hardware
entropy codecs are provided on the ADV212.
WAVELET ENGINE
EMBEDDED PROCESSOR SYSTEM
The ADV212 provides a dedicated wavelet transform processor
based on the Analog Devices proven and patented SURF
technology. This processor can perform up to six wavelet
decomposition levels on a tile. In encode mode, the wavelet
transform processor takes in uncompressed samples, performs
the wavelet transform and quantization, and writes the wavelet
coefficients in all frequency subbands to the internal memory.
Each of these subbands is further broken down into code
blocks. The code-block dimensions can be user defined and are
used by the wavelet transform processor to organize the wavelet
coefficients into code blocks when writing to the internal
memory. Each completed code block is then entropy coded by
one of the entropy codecs.
The ADV212 incorporates an embedded 32-bit RISC processor.
This processor is used for configuration, control, and manage-
ment of the dedicated hardware functions, as well as for parsing
and generation of the JPEG 2000 code stream. The processor
system includes memory for both the program and data
memory, the interrupt controller, the standard bus interfaces,
and other hardware functions such as timers and counters.
MEMORY SYSTEM
The main function of the memory system is to manage wavelet
coefficient data, interim code-block attribute data, and
temporary workspace for creating, parsing, and storing the
JPEG 2000 code stream. The memory system can also be used
for the program and data memory for the embedded processor.
In decode mode, wavelet coefficients are read from internal
memory and recomposed into uncompressed samples.
INTERNAL DMA ENGINE
The internal DMA engine provides high bandwidth memory-
to-memory transfers, as well as high performance transfers
between memory and functional blocks. This function is critical
for high speed generation and parsing of the code stream.
Rev. 0 | Page 25 of 44
ADV212
ADV212 INTERFACE
There are several possible modes to interface to the ADV212 using
the VDATA bus and the HDATA bus or the HDATA bus alone.
The control and data channel bus widths can be specified
independently, which allows the ADV212 to support
applications that require control and data buses of different
widths.
VIDEO INTERFACE (VDATA BUS)
The video interface can be used in applications in which
uncompressed pixel data is on a separate bus from compressed
data. For example, it is possible to use the VDATA bus to input
uncompressed video while using the HDATA bus to output the
compressed data. This interface is ideal for applications
requiring very high throughput, such as live video capture.
The host interface is used for configuration, control, and status
functions, as well as for transferring compressed data streams. It
can be used for uncompressed data transfers in certain modes.
The host interface can be shared by as many as three concurrent
data streams in addition to control and status communications.
The data streams are
Optionally, the ADV212 interlaces ITU-R BT.656 resolution
video on the fly prior to wavelet processing, which yields
significantly better compression performance for temporally
coherent frame-based video sources. Additionally, high
definition digital video such as SMPTE 274M (1080i) is
supported using two or more ADV212 devices.
•
•
Uncompressed tile data (for example, still image data)
Fully encoded JPEG 2000 code stream (or unpackaged
code blocks)
•
Code-block attributes
The ADV212 uses big endian byte alignment for 16- and 32-bit
transfers. All data is left-justified (MSB).
The video interface can support video data or still image data
input/output in 8-/10-/12-bit formats, in YCbCr format, or in
single input mode. YCbCr data must be in 4:2:2 format.
Pixel Input on the Host Interface
Pixel input on the host interface supports 8-/10-/12-/14-/16-bit
raw pixel data formats. It can be used for pixel (still image)
input/output or compressed video output. Because there are no
timing codes or sync signals associated with the input data on
the host interface, dimension registers and internal counters are
used and must be programmed to indicate the start and end of
the frame. Refer to the ADV202 in HIPI Mode technical note for
information about using the ADV212 in this mode.
Video data can be input/output in several different modes on
the VDATA bus, as described in Table 17. In all these modes,
the pixel clock must be input on the VCLK pin.
Table 17. Video Input/Output Modes
Mode
Description
EAV/SAV
Accepts video with embedded EAV/SAV codes, where
the YCbCr data is interleaved onto a single bus.
HVF
Accepts video data accompanied with separate H,
V, and F signals, where YCbCr data is interleaved
onto a single bus.
Host Bus Configuration
For maximum flexibility, the host interface provides several
configurations to meet particular system requirements. The
default bus mode uses the same pins to transfer control, status,
and data to and from the ADV212. In this mode, the ADV212
can support 16- and 32-bit control transfers and 8-/16-/32-bit
data transfers. The size of these buses can be selected
independently, allowing, for example, a 16-bit microcontroller
to configure and control the ADV212 while still providing
32-bit data transfers to an ASIC or external memory system.
Raw Video Used for still picture data and nonstandard video.
VFRM, VSTRB, and VRDY are used to program the
dimensions of the image.
HOST INTERFACE (HDATA BUS)
The ADV212 can connect directly to a wide variety of host
processors and ASICs using an asynchronous SRAM-style
interface, DMA accesses, or streaming mode (JDATA) interface.
The ADV212 supports 16- and 32-bit buses for control and
8-/16-/32-bit buses for data transfer.
DIRECT AND INDIRECT REGISTERS
To minimize pin count and cost, the number of address pins
is limited to four, which yields a total direct address space of
16 locations. These locations are most commonly used by the
external controller and are, therefore, accessible directly. All
other registers in the ADV212 can be accessed indirectly
through the IADDR and IDATA registers.
Rev. 0 | Page 26 of 44
ADV212
has been provided to allow 16-bit hosts to access these registers
and memory locations using the stage register (STAGE). STAGE
is accessed as a 16-bit register using HDATA [15:0]. Prior to
writing to the desired register, the stage register must be written
with the upper (most significant) half-word.
CONTROL ACCESS REGISTERS
With the exception of the indirect address and data registers
(IADDR and IDATA), all control/status registers in the
ADV212 are 16 bits wide and are half-word (16-bit) addressable
only. When 32-bit host mode is enabled, the upper 16 bits of the
HDATA bus are ignored on writes and return all zeros on reads
of 16-bit registers.
When the host subsequently writes the lower half-word to the
desired control register, HDATA is combined with the
previously staged value to create the required 32-bit value that is
written. When a register is read, the upper (most significant)
half-word is returned immediately on HDATA and the lower
half-word can be retrieved by reading the stage register on a
subsequent access. For details on using the stage register, see the
ADV212 User’s Guide.
PIN CONFIGURATION AND BUS SIZES/MODES
The ADV212 provides a wide variety of control and data
configurations, which allows it to be used in many applications
with little or no glue logic. The modes described in this section
are configured using the BUSMODE register. In this section,
host refers to normal addressed accesses (
and data refers to external DMA accesses (
CS RD WE
/
/
/ADDR)
Note that the stage register does not apply to the three data
channels (PIXEL, CODE, ATTR). These channels are always
accessed at the specified data width and do not require the use
of the stage register.
DREQ DACK
/
).
32-Bit Host/32-Bit Data
In this mode, the HDATA<31:0> pins provide full 32-bit wide
data access to PIXEL, CODE, ATTR FIFOs.
JDATA MODE
16-Bit Host/32-Bit Data
JDATA mode is typically used only when the dedicated video
interface (VDATA) is also enabled. This mode allows code
stream data (compressed data compliant with JPEG 2000) to be
input or output on a single dedicated 8-bit bus (JDATA<7:0>).
The bus is always an output during compression operations,
and is an input during decompression.
This mode allows a 16-bit host to configure and communicate
with the ADV212 while allowing 32-bit accesses to the PIXEL,
CODE, ATTR FIFOs using the external DMA capability.
All addressed host accesses are 16 bits and, therefore, use only
the HDATA<15:0> pins. The HDATA<31:16> pins provide the
additional 16 bits necessary to support the 32-bit external DMA
transfers to and from the FIFOs only.
A 2-pin handshake is used to transfer data over this
synchronous interface. VALID is used to indicate that the
ADV212 is ready to provide or accept data and is always an
output. HOLD is always an input and is asserted by the host if it
cannot accept/provide data. For example, JDATA mode allows
real-time applications, in which pixel data is input over the
VDATA bus while the compressed data stream is output over
the JDATA bus.
16-Bit Host/16-Bit Data
This mode uses 16-bit transfers if used for host or external
DMA data transfers.
16-Bit Host/8-Bit Data (JDATA Bus Mode)
This mode provides separate data input/output and host
control interface pins. Host control accesses are 16 bits and use
HDATA<15:0>, whereas the dedicated data bus uses JDATA<7:0>.
EXTERNAL DMA ENGINE
The external DMA interface is provided to enable high
bandwidth data input/output between an external DMA
controller and the ADV212 data FIFOs. Two independent DMA
channels can each be assigned to any one of the three data
stream FIFOs (PIXEL, CODE, ATTR).
JDATA uses a valid/hold synchronous transfer protocol. The
direction of the JDATA bus is determined by the mode of the
ADV212. If the ADV212 is encoding (compression),
JDATA<7:0> is an output. If the ADV212 is decoding
(decompression), JDATA<7:0> is an input. Host control
accesses remain asynchronous. See also JDATA section below.
The controller supports asynchronous DMA using a
DREQ DACK
data-request/data-acknowledge (
/
) protocol in
STAGE REGISTER
either single or burst access modes. Additional functionality is
provided for single address compatibility (fly-by) and dedicated
chip select (DCS) modes.
Because the ADV212 contains both 16-bit and 32-bit registers
and its internal memory is mapped as 32-bit data, a mechanism
Rev. 0 | Page 27 of 44
ADV212
INTERNAL REGISTERS
This section describes the internal registers of the ADV212.
The host must first initialize the direct registers before any
application-specific operation can be implemented.
DIRECT REGISTERS
For additional information on accessing and configuring these
registers, see the ADV212 User’s Guide.
The ADV212 has 16 direct registers, as listed in Table 18. The
direct registers are accessed over the ADDR [3:0], HDATA [31:0],
CS RD WE
ACK
,
,
, and
pins.
Table 18. Direct Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
Description
PIXEL
CODE
ATTR
Pixel FIFO access register
Compressed code stream access register
Attribute FIFO access register
Reserved
Reserved
CMDSTA
EIRQIE
EIRQFLG
SWFLAG
BUSMODE
MMODE
STAGE
IADDR
IDATA
BOOT
PLL_HI
PLL_LO
Command stack
External interrupt enabled
External interrupt flags
Software flag register
Bus mode configuration register
Miscellaneous mode register
Staging register
Indirect address register
Indirect data register
Boot mode register
PLL control register—high byte
PLL control register—low byte
Rev. 0 | Page 28 of 44
ADV212
INDIRECT REGISTERS
In certain modes, such as custom-specific input format or HIPI
mode, indirect registers must be accessed by the user through
the use of the IADDR and IDATA registers. The indirect
register address space starts at Internal Address 0xFFFF0000.
Both 32-bit and 16-bit hosts can access the indirect registers.
32-bit hosts use the IADDR and IDATA registers, and the 16-bit
hosts use the IADDR, the IDATA, and the stage register.
For additional information on accessing and configuring these
registers, see the ADV212 User’s Guide.
Table 19. Indirect Registers
Address
Name
Description
0xFFFF0400
0xFFFF0404
0xFFFF0408
0xFFFF040C
0xFFFF0410
0xFFFF0414
0xFFFF0418
0xFFFF041C
0xFFFF0420
0xFFFF0424
0xFFFF0428
0xFFFF042C
0xFFFF0430
0xFFFF0440
0xFFFF0444
0xFFFF0448
0xFFFF044C
0xFFFF1408
0xFFFF140C
0xFFFF1410
0xFFFF1414
0xFFFF1418
0xFFFF141C
0xFFFF1420
0xFFFF1424 to 0xFFFF14FC
PMODE1
COMP_CNT_STATUS
LINE_CNT_STATUS
XTOT
Pixel/video format
Horizontal count
Vertical count
Total samples per line
Total lines per frame
Start line of Field 0 [F0]
Start line of Field 1 [F1]
Start of active video Field 0 [F0]
Start of active video Field 1 [F1]
End of active video Field 0 [F0]
End of active video Field 1 [F1]
Horizontal start of active video
Horizontal end of active video
Master/slave delay
Reserved
Pixel Mode 2
Video mode
External DMA Mode Register 0
External DMA Mode Register 1
FIFO threshold for pixel FIFO
Reserved
YTOT
F0_START
F1_START
V0_START
V1_START
V0_END
V1_END
PIXEL_START
PIXEL_END
MS_CNT_DEL
Reserved
PMODE2
VMODE
EDMOD0
EDMOD1
FFTHRP
Reserved
Reserved
FFTHRC
FFTHRA
Reserved
Reserved
FIFO threshold for code FIFO
FIFO threshold for ATTR FIFO
Reserved
Rev. 0 | Page 29 of 44
ADV212
PLL
The ADV212 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 μs before reading from or writing
to another register. If this delay is not implemented, erratic
behavior might result.
•
For MCLK frequencies greater than 50 MHz, the input clock
divider must be enabled, that is, IPD must be set to 1.
IPD cannot be enabled for MCLK frequencies below 20 MHz.
Deinterlace modes require JCLK ≥ 4 × MCLK.
It is not recommended to use an LLC output from a video
decoder as a clock source for MCLK.
•
•
•
MCLK is the input clock to the ADV212 PLL and is used to
generate the internal JCLK (JPEG 2000 processor clock) and
HCLK (embedded CPU clock).
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR 656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.
The PLL can be programmed to have any possible final
multiplier value as long as
•
•
•
JCLK > 50 MHz and < 150 MHz (144-pin version).
JCLK > 50 MHz and < 115 MHz (121-pin version).
HCLK < 81 MHz (121-pin version), or HCLK < 108 MHz
(144-pin version).
JCLK ≥ 2 × VCLK for single-component input.
JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.
In JDATA mode (JDATA), JCLK must be 4 × MCLK
or higher.
BYPASS
IPD
MCLK
PHASE
DETECT
JCLK
HCLK
÷2
÷2
LPF
VCO
÷2
•
•
•
÷2
÷2
÷PLLMULT
HCLKD
LFB
Figure 32. PLL Architecture and Control Functions
•
The maximum burst frequency for external DMA modes is
≤ 0.36 JCLK.
Table 20. Recommended PLL Register Settings
IPD
LFB
PLLMULT
HCLKD
HCLK
JCLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
N
N
N
N
N
N
N
N
0
1
0
1
0
1
0
1
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
N × MCLK/2
N × MCLK
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
CLKIN Frequency on MCLK
PLL_HI
0x0008
0x0008
0x0008
0x0008
PLL_LO
0x0004
0x0004
0x0004
0x0084
SMPTE 125M or ITU-R BT.656 (NTSC or PAL)
SMPTE 293M (525p)
ITU-R BT.1358 (625p)
27 MHz
27 MHz
27 MHz
74.25 MHz
SMPTE 274M (1080i)
Rev. 0 | Page 30 of 44
ADV212
HARDWARE BOOT
The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins.
Table 22. Hardware Boot Modes
Boot Mode
Settings
Description
Hardware Boot Mode 2 CFG<1> tied high, CFG<2> tied low
No boot host mode. ADV212 does not boot, but all internal registers and
memory are accessible through normal host input/output operations.
Hardware Boot Mode 4 CFG<1> tied low, CFG<2> tied high
Hardware Boot Mode 6 CFG<1> and CFG<2> tied high
Reserved.
Reserved.
Rev. 0 | Page 31 of 44
ADV212
VIDEO INPUT FORMATS
The ADV212 supports a wide variety of formats for
uncompressed video and still image data. The actual interface
and bus modes selected for transferring uncompressed data
dictates the allowed size of the input data and the number of
samples transferred with each access.
YCbCr formats or single component format. See the ADV212
User’s Guide for details. All formats can support less precision
than provided by specifying the actual data width/precision in
the PMODE register.
The maximum allowable data input rate is limited by using
irreversible or reversible compression modes and the data width
(or precision) of the input samples. Refer to Table 23 and
Table 25 to determine the maximum data input rate.
The host interface can support 8-/10-/12-/14-/16-bit data
formats. The video interface can support video data or still
image data input/output. Supported formats are 8-/10-/12-bit
Table 23. Maximum Pixel Data Input Rates (144-Ball Package)
Input Rate Limit
Approx Min Output Rate,
Compressed Data2
(Mbps)
Approx Max Output Rate,
Compressed Data3
(Mbps)
Active Resolution
Interface
Compression Mode
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Input Format
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
(MSPS)1
HDATA
45
45
45
45
40
32
27
23
65
65
65
40
32
27
130
130
130
130
130
130
130
130
130
130
130
130
130
130
200
200
200
200
200
200
200
200
200
200
200
200
200
200
Reversible
Reversible
Reversible
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
VDATA
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
10-bit data
12-bit data
1 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.
2 Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate].
3 Maximum peak output rate; an output rate above this value is not possible.
Table 24. Maximum Pixel Data Input Rates (121-Ball Package)
Input Rate Limit
Active Resolution
(MSPS)1
Approx Min Output Rate,
Compressed Data2
(Mbps)
Approx Max Output Rate,
Compressed Data3
(Mbps)
Interface
Compression Mode
Irreversible
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
Reversible
Input Format
8-bit data
10-bit data
12-bit data
16-bit data
8-bit data
10-bit data
12-bit data
14-bit data
8-bit data
10-bit data
12-bit data
8-bit data
HDATA
34
34
34
34
30
24
20
17
48
48
48
30
24
20
98
98
98
98
98
98
98
98
98
98
98
98
98
98
150
150
150
150
150
150
150
150
150
150
150
150
150
150
VDATA
Irreversible
Irreversible
Irreversible
Reversible
Reversible
Reversible
10-bit data
12-bit data
1 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings.
2 Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate].
3 Maximum peak output rate; an output rate above this value is not possible.
Rev. 0 | Page 32 of 44
ADV212
Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses
Compression Mode
Input Format
Tile/Precinct Maximum Width
9/7i
9/7i
9/7i
5/3i
5/3i
5/3i
5/3r
5/3r
5/3r
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
Single-component
Two-component
Three-component
2048
1024 each
1024 (Y)
4096
2048 (each)
2048 (Y)
4096
2048
1024
Rev. 0 | Page 33 of 44
ADV212
APPLICATIONS
In decode mode, a master/slave configuration (as shown in
Figure 34) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV212s. See the AN-796
Application Note for details on how to configure the ADV212s
in a multichip application.
This section describes typical video applications for the
ADV212 JPEG 2000 video processor.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 23), an 1080i
application requires at least two ADV212s to encode or decode
full-resolution 1080i video. In encode mode, the ADV212
accepts Y and CbCr data on separate buses. An encode example
is shown in Figure 33.
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV212 outputs.
32-BIT HOST CPU
ADV212_1_SLAVE
ADV7402
74.25MHz
OSC
10-BIT SD/HD
VIDEO
DECODER
DATA[31:0]
ADDR[3:0]
CS
HDATA[31:0]
ADDR[3:0]
CS
1080i
VIDEO IN
RD
RD
VCLK
MCLK
LLC
ACK
ACK
WE
WR
Y
VDATA[11:2]
Y[9:0]
C[9:0]
IRQ
IRQ
DREQ
DACK
DREQ
DACK
FIELD
VSYNC
HSYNC
CbCr
G I/O
SCOMM[5]
ADV212_2_SLAVE
HDATA[31:0]
ADDR[3:0]
VCLK
MCLK
CS
RD
CS
RD
HSYNC
VSYNC
FIELD
WR
ACK
IRQ
WE
ACK
IRQ
CbCr
VDATA[11:2]
DREQ
DACK
DREQ
DACK
SCOMM[5]
Figure 33. Encode—Multichip Application
Rev. 0 | Page 34 of 44
ADV212
In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.
DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
74.25MHz
OSC
32-BIT HOST CPU
ADV212_1_MASTER
ADV7321A
10-BIT SD/HD
VIDEO
ENCODER
DATA[31:0]
ADDR[3:0]
CS
HDATA[31:0]
ADDR[3:0]
CS
RD
RD
1080i
VIDEO OUT
VCLK
MCLK
CLKIN
Y[9:0]
WR
WE
ACK
IRQ
ACK
Y
Y
VDATA[11:2]
IRQ
DREQ
DACK
DREQ
DACK
FIELD
VSYNC
HSYNC
CbCr
G I/O
SCOMM[5]
C[9:0]
ADV212_2_SLAVE
HDATA[31:0]
ADDR[3:0]
VCLK
MCLK
CS
RD
CS
RD
HSYNC
VSYNC
FIELD
WR
ACK
IRQ
WE
ACK
IRQ
CbCr
VDATA[11:2]
DREQ
DACK
DREQ
DACK
SCOMM[5]
Figure 34. Decode—Multichip Master/Slave Application
Rev. 0 | Page 35 of 44
ADV212
DIGITAL STILL CAMERA/CAMCORDER
Figure 35 is a typical configuration for a digital camera or camcorder.
FPGA
AD9843A
D[9:0]
ADV212
MCLK
10
DATA INPUTS[9:0]
VCLK
16-BIT
HOST CPU
VFRM
VRDY
SDATA
SCK
SL
SERIAL DATA
SERIAL CLK
SERIAL EN
VSTRB
HDATA[15:0]
ADDR[3:0]
CS
DATA[15:0]
ADDR[3:0]
CS
RD
RD
WE
WE
PIXEL OUT[9:0]
VDATA[15:6]
ACK
IRQ
ACK
IRQ
Figure 35. Digital Still Camera/Camcorder Encode Application for 10-Bit Pixel Data Using Raw Pixel Mode
Rev. 0 | Page 36 of 44
ADV212
ENCODE/DECODE SDTV VIDEO APPLICATION
Figure 36 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.
ENCODE MODE
ADV7189
10-BIT
VIDEO
DECODER
ADV212
VIDEO IN
VDATA[11:2]
P[19:10]
32-BIT
HOST CPU
VCLK
MCLK
LLC1
DATA[31:0]
INTR
HDATA[31:0]
IRQ
27MHz
OSC
ADDR[3:0]
CS
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
ADV7301A
10-BIT
VIDEO
ENCODER
DECODE MODE
ADV212
VIDEO OUT
VDATA[11:2]
VCLK
P[9:0]
CLKIN
32-BIT
HOST CPU
MCLK
DATA[31:0]
INTR
HDATA[31:0]
IRQ
27MHz
OSC
ADDR[3:0]
CS
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
Figure 36. Encode/Decode—SDTV Video Application
Rev. 0 | Page 37 of 44
ADV212
32-BIT HOST APPLICATION
Figure 37 shows two ADV212 chips using a 10-bit CCIR 656 in normal host mode.
FPGA
ADV7189
ADV212
10-BIT
VIDEO
VIDEO IN
DECODER
DREQ0
DACK0
DREQ0
DACK0
VDATA[11:2]
P[19:10]
DATA[31:0]
HDATA[31:0]
LLC1
VCLK
MCLK
27MHz
OSC
32-BIT
HOST CPU
DATA[31:0]
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
ENCODE MODE
FPGA
ADV730xA
ADV212
10-BIT
VIDEO
VIDEO OUT
ENCODER
DREQ0
DACK0
DREQ0
DACK0
VDATA[11:2]
VCLK
P[9:0]
CLKIN
DATA[31:0]
HDATA[31:0]
MCLK
31-BIT
HOST CPU
27MHz
OSC
DATA[31:0]
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
CS
RD
RD
WE
WE
ACK
ACK
DECODE MODE
Figure 37. Encode/Decode 32-Bit Host Application
Rev. 0 | Page 38 of 44
ADV212
HIPI (HOST INTERFACE—PIXEL INTERFACE)
Figure 38 is a typical configuration using HIPI mode.
ADV212
Y0/G0<MSB>
Y0/G0<6>
Y0/G0<5>
Y0/G0<4>
Y0/G0<3>
Y0/G0<2>
Y0/G0<1>
Y0/G0<0>
Cb0/G1<MSB>
Cb0/G1<6>
Cb0/G1<5>
Cb0/G1<4>
Cb0/G1<3>
Cb0/G1<2>
Cb0/G1<1>
Cb0/G1<0>
Y1/G2<MSB>
Y1/G2<6>
Y1/G2<5>
Y1/G2<4>
Y1/G2<3>
Y1/G2<2>
Y1/G2<1>
Y1/G2<0>
Cr0/G3<MSB>
Cr0/G3<6>
Cr0/G3<5>
Cr0/G3<4>
Cr0/G3<3>
Cr0/G3<2>
Cr0/G3<1>
Cr0/G3<0>
HDATA<31>
HDATA<30>
HDATA<29>
HDATA<28>
HDATA<27>
HDATA<26>
HDATA<25>
HDATA<24>
HDATA<23>
HDATA<22>
HDATA<21>
HDATA<20>
HDATA<19>
HDATA<18>
HDATA<17>
HDATA<16>
HDATA<15>
HDATA<14>
HDATA<13>
HDATA<12>
HDATA<11>
HDATA<10>
HDATA<9>
HDATA<8>
HDATA<7>
HDATA<6>
HDATA<5>
HDATA<4>
HDATA<3>
HDATA<2>
HDATA<1>
HDATA<0>
32-BIT HOST
DATA<31:0>
CS
RD
CS
RD
WR
ACK
IRQ
WE
ACK
IRQ
DREQ
DACK
DREQ0
DACK0
COMPRESSED
DATA PATH
DREQ
DACK
DREQ1
DACK1
RAW PIXEL
DATA PATH
74.25MHz
MCLK
Figure 38. Host Interface—Pixel Interface Mode
Rev. 0 | Page 39 of 44
ADV212
JDATA INTERFACE
Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656.
FPGA
ADV212
ADV7189
P[19:10]
YCrCb
JDATA[7:0] VDATA[11:2]
HOLD
VIDEO IN
FIELD
VALID
FIELD
VS
HS
VSYNC
HSYNC
16-BIT
HOST CPU
VCLK
LLC1
DATA[15:0]
HDATA[15:0]
IRQ
ADDR[3:0]
CS
IRQ
ADDR[3:0]
27MHz
OSC
MCLK
CS
RD
RD
WE
WE
ACK
ACK
Figure 39. JDATA Application
Rev. 0 | Page 40 of 44
ADV212
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
12.20
12.00 SQ
11.80
11 10
9
7
8 6 5 3
4 2 1
A
B
C
D
E
F
BALL A1
CORNER
10.00
BSC SQ
G
H
J
1.00
BSC
K
L
BOTTOM VIEW
DETAILA
TOP VIEW
DETAIL A
*
1.85
1.71
1.40
*
1.31
1.21
1.11
0.50 NOM
0.30 MIN
0.20
COPLANARITY
0.70
0.60
0.50
SEATING
PLANE
BALL DIAMETER
*COMPLIANT WITH JEDEC STANDARDS MO-192-ABD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-121-1)
Dimensions shown in millimeters
A1 CORNER
INDEX AREA
13 .00
BSC SQ
9
7
11
5
4
3
1
2
12
10
8
6
A
B
C
D
E
F
G
H
J
BALL A1
INDICATOR
11.00
BCS SQ
TOP VIEW
K
L
M
BOTTOM VIEW
DETAILA
1.00 BSC
DETAIL A
*
1.85
MAX
*
1.32
1.21
1.11
0.53
0.43
COPLANARITY
0.20 MAX
0.70
0.60
0.50
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-192-AAD-1 WITH
EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.
Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-3)
Dimensions shown in millimeters
Rev. 0 | Page 41 of 44
ADV212
ORDERING GUIDE
Temperature
Range
Speed
Grade
Package
Option
Model
ADV212BBCZ-1151
Operating Voltage Package Description
−40°C to +85°C 115 MHz 1.5 V Internal,
2.5 V or 3.3 V I/O
121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
BC-121-1
BC-121-1
BC-144-3
BC-144-3
ADV212BBCZRL-1151 −40°C to +85°C 115 MHz 1.5 V Internal,
2.5 V or 3.3 V I/O
ADV212BBCZ-1501
−40°C to +85°C 150 MHz 1.5 V Internal,
2.5 V or 3.3 V I/O
ADV212BBCZRL-1501 −40°C to +85°C 150 MHz 1.5 V Internal,
2.5 V or 3.3 V I/O
1 Z = Pb-free part.
Rev. 0 | Page 42 of 44
ADV212
NOTES
Rev. 0 | Page 43 of 44
ADV212
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06389-0-10/06(0)
Rev. 0 | Page 44 of 44
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