ADV3002BSTZ [ADI]
4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication; 4 ： 1 HDMI / DVI开关，具有均衡， DDC / CEC缓冲和EDID复制
| 型号： | ADV3002BSTZ |
| 厂家： | 
ADI |
| 描述： | 4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication |
| 文件： | 总28页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4:1 HDMI/DVI Switch with Equalization,
DDC/CEC Buffers and EDID Replication
ADV3002
FUNCTIONAL BLOCK DIAGRAM
FEATURES
4 inputs, 1 output HDMI/DVI links
8 kV ESD protection on input pins
SEL[1:0] TX_EN
RESETB
SERIAL
PARALLEL
ADV3002
AVCC
AVEE
I2C_SDA
I2C_SCL
I2C_ADDR[1:0]
CONFIG
INTERFACE
CONTROL
LOGIC
HDMI 1.3a receive and transmit compliant
Supports 250 Mbps to 2.25 Gbps data rates and beyond
Supports 25 MHz to 225 MHz pixel clocks and beyond
Fully buffered unidirectional inputs/outputs
Switchable 50 Ω on-chip input terminations with manual
or automatic control on channel switch
Equalized inputs with low added jitter compensate for
more than 20 meters of HDMI cable at 2.25 Gbps
Loss of signal (LOS) detect circuit on TMDS clock
Output disable feature for reduced power dissipation
Bidirectional DDC buffers (SDA and SCL)
2
AVCC
AVCC
LOS
+
–
+
–
4
4
+
–
+
–
IN_x_CLK+
IN_x_CLK–
OUT_CLK+
OUT_CLK–
IN_x_DATA2+
IN_x_DATA2–
IN_x_DATA1+
IN_x_DATA1–
IN_x_DATA0+
IN_x_DATA0–
OUT_DATA2+
OUT_DATA2–
OUT_DATA1+
OUT_DATA1–
OUT_DATA0+
OUT_DATA0–
4
SWITCH
CORE
+
–
+
–
+
–
+
–
4
4
EQ
4
4
TMDS
AVCC
AVCC
DDC_xxx_A
DDC_xxx_B
DDC_xxx_C
DDC_xxx_D
2
2
2
2
2
SWITCH
CORE
DDC_SCL_COM,
DDC_SDA_COM
EDID replication reduces component count, while enabling
simultaneous access to all HDMI sources
3.3V
3.3V
5 V combiner provides power to EDID replicator and CEC
buffer when local system power is off
Bidirectional buffered CEC line with integrated pull-up
resistors (26 kΩ)
Hot plug detect pulse low on channel switch with
programmable pulse width or direct manual control
Standards compatible: HDMI, DVI, HDCP, I2C
80-lead, 14 mm × 14 mm LQFP RoHS-compliant package
CEC_IN
CEC_OUT
DDC/CEC
BIDIRECTIONAL
EDID_ENABLE
REPLICATOR
CONTROL
2
EDID_SCL,
EDID_SDA
EDID
P5V_A
P5V_B
P5V_C
P5V_D
5V
AMUXVCC
COMBINER
EDID EEPROM INTERFACE
HPD_A
HPD_B
HPD_C
HPD_D
APPLICATIONS
Advanced television (HDTV) sets
Projectors
HPD
CONTROL
HOT PLUG DETECT
A/V receivers
Set-top boxes
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADV3002 is a complete HDMI™/DVI link switch featuring
equalized transition minimized differential signaling (TMDS)
inputs, ideal for systems with long cable runs. The ADV3002
includes bidirectional buffering for the DDC bus and CEC line,
with integrated pull-up resistors for the CEC line. Additionally,
the ADV3002 includes an EDID replication function that enables
one EDID EEPROM to be shared for all four HDMI ports.
1. Input cable equalizer enables use of long cables at the
input. For a 24 AWG cable, the ADV3002 compensates for
more than 20 m at data rates up to 2.25 Gbps.
2. Auxiliary multiplexer isolates and buffers the DDC bus and
the CEC line, increasing total system capacitance limit.
3. EDID replication eliminates the need for multiple EDID
EEPROMs. EDID can be loaded from a single external
EEPROM or from a system microcontroller.
The ADV3002 is provided in a space-saving, 80-lead LQFP
surface-mount Pb-free plastic package and is specified to
operate over the 0°C to 85°C temperature range.
4. 5 V power combiner powers the EDID replicator and CEC
buffer when local system power is off.
5. Integrated hot plug detect pulse low on channel switch
with programmable pulse width or direct manual control.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADV3002
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC Buffers................................................................................ 13
EDID Replication....................................................................... 13
5 V Combiner ............................................................................. 15
CEC Buffer .................................................................................. 15
Hot Plug Detect Control ........................................................... 15
Loss of Signal Detect.................................................................. 16
Serial Control Interface ................................................................. 17
Reset............................................................................................. 17
Write Procedure.......................................................................... 17
Read Procedure........................................................................... 18
ADV3002 Register Map................................................................. 19
Applications Information.............................................................. 21
HDMI Multiplexer for Advanced TV ..................................... 21
Cable Lengths and Equalization............................................... 24
PCB Layout Guidelines.............................................................. 24
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
TMDS Performance Specifications............................................ 3
Auxiliary Channel Performance Specifications........................ 3
Power Supply and Control Logic Specifications ...................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
TMDS Input Channels............................................................... 12
TMDS Output Channels ........................................................... 12
REVISION HISTORY
12/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADV3002
SPECIFICATIONS
TA = 27°C, AVCC = 3.3 V, A M U XVC C = 5 V, AVEE = 0 V, data rate = 2.25 Gbps, differential input swing = 1000 mV, TMDS outputs
terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
TMDS PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Data Rate (DR) per Channel
Maximum Clock Rate
Bit Error Rate (BER)
Added Data Jitter
Added Clock Jitter
Differential Intrapair Skew
Differential Interpair Skew
EQUALIZATION PERFORMANCE
High Frequency Gain
INPUT CHARACTERISTICS
Input Voltage Swing
NRZ
2.25
225
Gbps
MHz
PRBS 223 − 1
DR ≤ 2.25 Gbps, PRBS 27 − 1
10−9
40
1
1
ps p-p
ps rms
ps
At output
At output
35
ps
Boost frequency = 1.125 GHz
Differential
18
dB
150
AVCC − 800
1200
AVCC
mV
mV
Input Common-Mode Voltage (VICM
OUTPUT CHARACTERISTICS
High Voltage Level
)
Single-ended high speed channel
Single-ended high speed channel
DR = 2.25 Gbps
AVCC − 200
AVCC − 600
75
AVCC + 10
mV
Low Voltage Level
Rise/fall time (20% to 80%)
TERMINATION
AVCC − 400 mV
190
ps
Input Termination Resistance
Output Termination Resistance
LOSS OF SIGNAL (LOS) DETECT
Frequency Cutoff
Single-ended
Single-ended
50
50
Ω
Ω
LOS_FC (see Figure 27)
Clock rate = 225 MHz, LOS_THR = 00
(see Figure 27)
5
MHz
mV
Amplitude Threshold
35
AUXILIARY CHANNEL PERFORMANCE SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
DDC CHANNELS
Input Capacitance, CAUX
Input Low Voltage, VIL
Input High Voltage, VIH
Output Low Voltage, VOL
Rise Time
DC bias = 2.5 V, ac voltage = 3.5 V p-p, f = 100 kHz
5
15
0.5
pF
V
V
0.7 × AMUXVCC
IOL = 5 mA
0.25
1.45
20
0.4
V
10% to 90%, CLOAD = 50 pF, RPULL-UP = 2 kΩ
90% to 10%, CLOAD = 50 pF, RPULL-UP = 2 kΩ
VIN = 5.0 V
µs
ns
µA
Fall Time
Leakage
250
10
CEC CHANNEL
Input Capacitance, CAUX
Input Low Voltage, VIL
Input High Voltage, VIH
Output Low Voltage, VOL
Output High Voltage, VOH
DC bias = 1.65 V, ac voltage = 2.5 V p-p, f = 100 kHz
IOL = 3 mA
5
15
0.8
pF
V
V
V
V
2.0
2.5
0.1
0.6
Rev. 0 | Page 3 of 28
ADV3002
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
Rise Time
10% to 90%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
RPULL-UP = 3 kΩ
75
250
µs
Fall Time
90% to 10%, CLOAD = 1500 pF, RPULL-UP = 27 kΩ; or CLOAD = 7200 pF,
0.2
26
50
µs
R
PULL-UP = 3 kΩ
Pull-Up Resistance
Leakage
kΩ
µA
Off-leakage test conditions1
1.8
0.4
HOT PLUG DETECT
Output Low Voltage, VOL
RPU = 800 Ω
0.25
V
1 Off leakage test conditions are described in the HDMI Compliance Test Specification 1.3c Section 8, Test ID 8-14. To measure CEC leakage, connect the CEC line to
3.63 V via 26 kΩ 5 % resistor with an ammeter in series and with the power mains disabled.
POWER SUPPLY AND CONTROL LOGIC SPECIFICATIONS
Table 3.
Parameter
POWER SUPPLY
AVCC
Test Conditions/Comments
Operating range (3.3 V 10%)
Output voltage, total load1 = 50 mA
Min
Typ
Max
Unit
3.0
4.7
4.0
3.3
5
5
3.6
5.5
5.5
V
V
V
P5V_x
AMUXVCC
QUIESCENT CURRENT
AVCC
Outputs disabled
Outputs enabled
Main power on
Main power off
Main power on
Main power off
40
60
150
10
30
30
10
mA
mA
mA
mA
mA
mA
170
0.5
20
20
0.5
P5V_x
AMUXVCC
POWER DISSIPATION
Outputs disabled
Outputs enabled
232
661
381
885
mW
mW
I2C® AND LOGIC INPUTS2
Input High Voltage, VIH
Input Low Voltage, VIL
I2C AND LOGIC OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
2.4
V
V
1.0
0.4
IOH = −2 mA
IOL = +2 mA
AVCC
V
V
1 The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply.
2 The ADV3002 I2C control and logic input pins are listed as control in the Type column in Table 6. I2C pins are 5 V tolerant and based on the 3.3 V I2C bus specification.
Rev. 0 | Page 4 of 28
ADV3002
ABSOLUTE MAXIMUM RATINGS
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
AVCC to AVEE
P5V_x
Rating
3.7 V
5.8 V
AMUXVCC
AVCC − 0.3 V < AMUXVCC < 5.8 V
Internal Power Dissipation 1.2 W
TMDS Single-Ended Input
Voltage
AVCC − 1.4 V < VIN < AVCC + 0.3 V
THERMAL RESISTANCE
TMDS Differential Input
Voltage
2.0 V
θJA is specified for the worst-case conditions: a device soldered
in a 4-layer JEDEC circuit board for surface-mount packages.
θJC is specified for the exposed pad soldered to the circuit board
with no airflow.
Voltage at TMDS Output
DDC Input Voltage
CEC Input Voltage
I2C Logic Input Voltage
(EDID_SCL, EDID_SDA,
I2C_SCL, I2C_SDA)
VOUT < 3.7 V
AVEE − 0.3 V <VIN < AMUXVCC + 0.3 V
AVEE − 0.3 V < VIN < 4.0 V
AVEE − 0.3 V < VIN < 4.0 V
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
Parallel Input Voltage
(I2C_ADDR[1:0],
RESETB)
Parallel Input Voltage
(SEL[1:0], TX_EN)
AVEE − 0.3 V < VIN < AMUXVCC + 0.3 V
AVEE − 0.3V < VIN < AVCC + 0.3 V
80-Lead LQFP (ST-80-2)
51.3
15.3
°C/W
ESD CAUTION
Storage Temperature Range −65°C to +125°C
Operating Temperature
Range
0°C to +85°C
Junction Temperature
150°C
8 kV
ESD Protection (HBM) on
HDMI Input Pins
ESD Protection (HBM) on
All Other Pins
2.5 kV
Rev. 0 | Page 5 of 28
ADV3002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
77
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
IN_B_CLK–
IN_B_CLK+
HPD_B
IN_C_DATA2+
IN_C_DATA2–
HPD_C
PIN 1
2
3
4
IN_B_DATA0–
IN_B_DATA0+
HPD_A
IN_C_DATA1+
IN_C_DATA1–
HPD_D
5
6
7
IN_B_DATA1–
IN_B_DATA1+
AVCC
IN_C_DATA0+
IN_C_DATA0–
AVCC
ADV3002
TOP VIEW
(Not to Scale)
8
9
10
11
12
13
14
15
16
17
18
19
20
IN_B_DATA2–
IN_B_DATA2+
SEL0
IN_C_CLK+
IN_C_CLK–
I2C_ADDR0
IN_D_DATA2+
IN_D_DATA2–
AVEE
IN_A_CLK–
IN_A_CLK+
SEL1
IN_A_DATA0–
IN_A_DATA0+
AVCC
IN_D_DATA1+
IN_D_DATA1–
AVCC
IN_A_DATA1–
IN_A_DATA1+
IN_D_DATA0+
IN_D_DATA0–
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Figure 2. Pin Configuration
Rev. 0 | Page 6 of 28
ADV3002
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
2
3
IN_B_CLK−
IN_B_CLK+
HPD_B
TMDS
TMDS
HPD
High Speed TMDS Input B Clock Complement.
High Speed TMDS Input B Clock.
Hot Plug Detect Output B.
4
5
6
IN_B_DATA0−
IN_B_DATA0+
HPD_A
TMDS
TMDS
HPD
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Hot Plug Detect Output A.
7
8
IN_B_DATA1−
IN_B_DATA1+
AVCC
IN_B_DATA2−
IN_B_DATA2+
SEL0
IN_A_CLK−
IN_A_CLK+
SEL1
IN_A_DATA0−
IN_A_DATA0+
IN_A_DATA1−
IN_A_DATA1+
AVEE
IN_A_DATA2−
IN_A_DATA2+
TX_EN
OUT_DATA2+
OUT_DATA2−
I2C_SCL
OUT_DATA1+
OUT_DATA1−
OUT_DATA0+
OUT_DATA0−
OUT_CLK+
OUT_CLK−
RESETB
IN_D_CLK−
IN_D_CLK+
I2C_ADDR1
I2C_SDA
TMDS
TMDS
Power
TMDS
TMDS
Control
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
Power
TMDS
TMDS
Control
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Control
TMDS
TMDS
Control
Control
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Control
TMDS
TMDS
TMDS
TMDS
HPD
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Positive Analog Supply 3.3 V.
High Speed TMDS Input B Data Complement.
High Speed TMDS Input B Data.
Channel Select Parallel Control LSB.
High Speed TMDS Input A Clock Complement.
High Speed TMDS Input A Clock.
Channel Select Parallel Control MSB.
High Speed TMDS Input A Complement.
High Speed TMDS Input A Data.
High Speed TMDS Input A Data Complement.
High Speed TMDS Input A Data.
Negative Analog Supply 0.0 V.
High Speed TMDS Input A Data Complement.
High Speed TMDS Input A Data.
TMDS Output Enable Parallel Control.
High Speed TMDS Output.
High Speed TMDS Output Complement.
Serial Control Clock Input.
High Speed TMDS Output.
High Speed TMDS Output Complement.
High Speed TMDS Output.
High Speed TMDS Output Complement.
High Speed TMDS Output Clock.
High Speed TMDS Output Clock Complement.
Configuration Registers Reset. Active low.
High Speed TMDS Input D Clock Complement.
High Speed TMDS Input D Clock.
Serial Control External Address MSB.
Serial Control Data Input/Output.
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
9, 18, 33, 43, 52
10
11
12
13
14
15
16
17
19
20
21, 30, 46
22
23
24
25
26
27
28
29
31
32
34
35
36
37
38
39
40
41
42
44
45
47
48
49
50
51
53
54
55
56
57
58
IN_D_D ATA0−
IN_D_DATA0+
IN_D_DATA1−
IN_D_DATA1+
IN_D_DATA2−
IN_D_DATA2+
I2C_ADDR0
IN_C_CLK−
IN_C_CLK+
IN_C_DATA0−
IN_C_DATA0+
HPD_D
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
High Speed TMDS Input D Data Complement.
High Speed TMDS Input D Data.
Serial Control External Address LSB.
High Speed TMDS Input C Clock Complement.
High Speed TMDS Input C Clock.
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
Hot Plug Detect Output D.
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
IN_C_DATA1−
IN_C_DATA1+
HPD_C
TMDS
TMDS
HPD
Hot Plug Detect Output C.
Rev. 0 | Page 7 of 28
ADV3002
Pin No.
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Mnemonic
IN_C_DATA2−
IN_C_DATA2+
EDID_SCL
EDID_SDA
EDID_ENABLE
AMUXVCC
CEC_OUT
Type
Description
TMDS
TMDS
Control
Control
Control
Power
CEC
High Speed TMDS Input C Data Complement.
High Speed TMDS Input C Data.
External EDID EEPROM Serial Interface Clock.
External EDID EEPROM Serial Interface Data.
EDID Replication Enable.
Positive Power Supply 5.0 V.
Consumer Electronics Control Output.
Consumer Electronics Control Input.
Display Data Channel Serial Clock Common Input/Output.
Display Data Channel Serial Data Common Input/Output.
Display Data Channel Serial Clock Input/Output D.
Display Data Channel Serial Data Input/Output D.
Display Data Channel Serial Clock Input/Output C.
Display Data Channel Serial Data Input/Output C.
Display Data Channel Serial Clock Input/Output B.
Display Data Channel Serial Data Input/Output B.
Display Data Channel Serial Clock Input/Output B.
Display Data Channel Serial Data Input/Output A.
5 V HDMI Supply from Source D.
CEC_IN
DDC_SCL_COM DDC
DDC_SDA_COM DDC
CEC
DDC_SCL_D
DDC_SDA_D
DDC_SCL_C
DDC_SDA_C
DDC_SCL_B
DDC_SDA_B
DDC_SCL_A
DDC_SDA_A
P5V_D
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
Power
Power
Power
Power
P5V_C
P5V_B
P5V_A
5 V HDMI Supply from Source C.
5 V HDMI Supply from Source B.
5 V HDMI Supply from Source A.
Rev. 0 | Page 8 of 28
ADV3002
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 27°C, AVCC = 3.3 V, AMUXVCC = 5.0 V, AVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 27 − 1,
data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V, unless otherwise noted.
HDMI CABLE
ADV3002
EVALUATION
BOARD
DIGITAL
PATTERN
GENERATOR
SERIAL DATA
ANALYZER
SMA COAX CABLE
REFERENCE EYE DIAGRAM AT TP1
TP1
TP2
TP3
Figure 3. Test Circuit for Eye Diagrams
0.167UI/DIV AT 2.25Gbps
0.167UI/DIV AT 2.25Gbps
Figure 4. Eye Diagram at TP2 for 2 m Cable
Figure 6. Eye Diagram at TP3 for 2 m Cable
0.167UI/DIV AT 2.25Gbps
0.167UI/DIV AT 2.25Gbps
Figure 5. Eye Diagram at TP2 for 20 m 24 AWG Cable
Figure 7. Eye Diagram at TP3 for 20 m 24 AWG Cable
Rev. 0 | Page 9 of 28
ADV3002
1.0
100
90
80
70
60
50
40
30
20
10
0
ALL CABLES = 24 AWG
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1080p, 12-BIT
1080p, 10-BIT
1080p, 8-BIT
720p
DETERMINISTIC JITTER
RANDOM JITTER
0
10
20
30
3.5
3.6
0
10
20
30
40
50
60
70
80
INPUT CABLE LENGTH (m)
TEMPERATURE (°C)
Figure 8. Deterministic Jitter vs. Input Cable Length
Figure 11. Jitter vs. Temperature
100
90
80
70
60
50
40
30
20
10
0
1000
800
600
400
200
DETERMINISTIC JITTER
RANDOM JITTER
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
DATA RATE (Gbps)
DATA RATE (Gbps)
Figure 9. Jitter vs. Data Rate
Figure 12. Eye Height vs. Data Rate
100
90
80
70
60
50
40
30
20
10
0
1000
800
600
400
200
0
DETERMINISTIC JITTER
RANDOM JITTER
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 10. Jitter vs. Supply Voltage
Figure 13. Eye Height vs. Supply Voltage
Rev. 0 | Page 10 of 28
ADV3002
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
EQ = 18dB
DETERMINISTIC JITTER
RANDOM JITTER
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
DIFFERENTIAL INPUT SWING (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 14. Deterministic Jitter vs. Input Swing
Figure 17. Jitter vs. Input Common-Mode Voltage
250
200
0.6
0.5
0.4
0.3
150
100
50
DDC
CEC
HPD
0.2
0.1
0
DATA RISE TIME @ 2.25Gbps
DATA FALL TIME @ 2.25Gbps
CLOCK RISE TIME @ 225MHz
CLOCK FALL TIME @ 225MHz
0
0
10
20
30
40
50
60
70
80
0
2
4
6
8
10
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 15. Rise and Fall Time vs. Temperature
Figure 18. DDC, CEC, HPD Output Logic Low Voltage vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Figure 16. Termination Resistance vs. Temperature
Rev. 0 | Page 11 of 28
ADV3002
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 18 dB. The
equalizer (EQ) level defaults to 18 dB after reset. No specific cable
length is suggested for a particular equalization setting because
cable performance varies widely between manufacturers; however,
in general, the equalization of the ADV3002 can be set to 18 dB
without degrading the signal integrity, even for short input cables.
AVCC
THEORY OF OPERATION
The primary function of the ADV3002 is to switch up to four
HDMI/DVI sources to one HDMI/DVI sink. Each HDMI/DVI
link consists of four differential, high speed channels and four
auxiliary single-ended, low speed signals. The high speed channels
include a data-word clock and three transition minimized differential
signaling (TMDS) data channels running at 10× the data-word
clock frequency for data rates up to 2.25 Gbps. The four low speed
control signals are the display data channel (DDC) bus (SDA and
SCL), the consumer electronics control (CEC) line, and the hot
plug detect (HPD) signal.
50Ω
50Ω
IN+
IN–
CABLE
EQ
The ADV3002 also includes an integrated EDID SRAM, eliminating
the need for an external EDID EEPROM for each HDMI connector.
A typical HDMI multiplexer is shown in Figure 19. The simplified
implementation using the ADV3002 is shown in Figure 20.
AVEE
NOTES
1. IN+ REFERS TO IN_x_CLK+/IN_x_DATAx+ PINS.
2. IN– REFERS TO IN_x_CLK–/IN_x_DATAx– PINS.
DDC
2
Figure 21. High Speed Input Simplified Schematic
5V
TMDS OUTPUT CHANNELS
EDID A
EDID B
EDID C
EDID D
DDC
2
Each high speed output differential pair is terminated to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown
in Figure 22. This termination is user-selectable; it can be turned
on or off by programming the TX_OTO bit of the TMDS output
control register, as shown in Table 10.
4:1
HDMI
Rx
2
5V
HDMI
MUX
DDC
DDC
2
2
5V
AVCC
DDC
5V
50Ω
50Ω
Figure 19. Typical HDMI Multiplexer Implementation
ESD
PROT.
OUT+
OUT–
DDC
2
5V
DISABLE
I
OUT
DDC
2
AVEE
NOTES
1. OUT+ REFERS TO OUT_CLK+ AND OUT_DATAx+ PINS.
2. OUT– REFERS TO OUT_CLK– AND OUT_DATAx– PINS.
2
HDMI
Rx
5V
ADV3002
DDC
DDC
Figure 22. High Speed Output Simplified Schematic
2
2
The output termination resistors of the ADV3002 back terminate
the output TMDS transmission lines. These back terminations, as
recommended in the HDMI 1.3a specification, act to absorb
reflections from impedance discontinuities on the output traces,
improving the signal integrity of the output traces and adding
flexibility to how the output traces can be routed. For example,
interlayer vias can be used to route the ADV3002 TMDS outputs
on multiple layers of the printed circuit board (PCB) without
severely degrading the quality of the output signal.
5V
DDC
2
5V
AMUXVCC
EDID DDC
EXTERNAL
EDID EEPROM
OR SYSTEM
MICROCONTROLLER
Figure 20. Simplified Implementation Using the ADV3002
The output has a disable feature that places the outputs in tristate
mode. Bigger wire-OR’e d arrays can be constructed using the
ADV3002 in this mode.
TMDS INPUT CHANNELS
Each high speed input differential pair terminates to the 3.3 V
power supply through a pair of 50 Ω on-chip resistors, as shown in
Figure 21. The state of the input terminations can be configured
automatically or programmed manually by setting the appropriate
bits in the TMDS input termination control register, as shown in
Table 10.
The ADV3002 requires output termination resistors when the high
speed outputs are enabled. Termination can be internal and/or
external. The internal terminations of the ADV3002 are enabled
by default after reset. External terminations can be provided either
by on-board resistors or by the input termination resistors of an
Rev. 0 | Page 12 of 28
ADV3002
HDMI/DVI receiver. If both the internal terminations are enabled
and external terminations are present, set the output current level
to 20 mA by programming the TX_OCL bit of the TMDS output
control register, as shown in Table 10 (20 mA is the default upon
reset). If only external terminations are provided (if the internal
terminations are disabled), set the output current level to 10 mA
by programming the TX_OCL bit of the TMDS output control
register. The high speed outputs must be disabled if there are no
output termination resistors present in the system.
EDID REPLICATION
The ADV3002 EDID replication feature reduces the total system
cost by eliminating the need for an EDID EEPROM for each HDMI
port. With the ADV3002, only a single external EDID is necessary.
The ADV3002 stores the EDID information in an on-chip SRAM.
This enables the EDID information to be simultaneously accessible
to all four HDMI ports. The ADV3002 combines the 5 V power
from the four HDMI sources such that the EDID information can
be available even when the system power is off. A block diagram
of the ADV3002 DDC buffering and EDID replication scheme is
shown in Figure 23.
DDC BUFFERS
The DDC buffers are 5 V tolerant bidirectional lines that carry
extended display identification data (EDID) and high bandwidth
digital content protection (HDCP) encryption. The ADV3002
provides switching and buffering for the DDC buses. The DDC
buffers are bidirectional, and fully support arbitration, clock
synchronization, and other relevant features of a standard mode
I2C bus.
SRAM
EXTERNAL
2
EDID_[SCL/SDA]
I2C_[SCL/SDA]
2
2
I C
EDID
EEPROM
v1.3
MASTER
EDID
CONTROL
2
I C
READ/
WRITE
SLAVE
MCU
2
I C
READ/
WRITE
SLAVE
HDMI
PORT A
2
2
2
2
2
2
I C
READ
SLAVE
2
HDMI
PORT B
2
I C
DDC
MUX
HDMI
Rx
2
2
READ
SLAVE
2
HDMI
PORT C
2
I C
READ
SLAVE
2
HDMI
PORT D
Figure 23. EDID Replication Block Diagram
Rev. 0 | Page 13 of 28
ADV3002
HDMI
PORT A
Source Physical Address Assignment
SPA = W . X . Y . Z
A
A
A
A
B
C
D
In HDTV applications where the CEC function is available, the
EDID contains the source physical address (SPA); a unique value
for each HDMI port. Because the memory in the ADV3002 is
volatile, the SPA must be stored in the external EDID EEPROM.
Rather than require a larger external EEPROM to store the SPA,
because all 256 bytes of memory are needed for typical EDID
information, the ADV3002 takes advantage of EDID information
that is always a fixed value, such as the 24-bit IEEE registration
identifier (0x000C03). The 24 bits of the IEEE registration identifier
are replaced with the desired SPA values. When a source requests
the IEEE registration identifier, the ADV3002 responds with the
fixed value (0x000C03). The ADV3002 then automatically calcu-
lates the correct checksum for each port based on the SPA stored
for that port in the vendor specific data block (VSDB).
HDMI
PORT B
SPA = W . X . Y . Z
B
B
B
ADV3002
HDMI
PORT C
SPA = W . X . Y . Z
C
C
C
HDMI
PORT D
SPA = W . X . Y . Z
D
D
D
Figure 24. SPA Assignments
Table 7. Typical Vendor Specific Data Block (VSDB)
CEC enabled devices have a source physical address (SPA) that
allows the CEC controller to address the specific physical devices
and control switches. The SPA is comprised of four fields or
nibbles. Each field is a 4-bit number; therefore, each field can be
any one of 16 possible values (0x0 through 0xF). Each HDMI
input port is assigned a unique SPA as shown in Figure 24. In any
CEC enabled device, only one of the four fields is unique per port.
In HDMI sink applications, where the sink is the root device, only
the W field is unique per port, whereas the X, Y, and Z fields are
always set to zero.
Byte No.
7
6
5
4
3
2
1
0
0
Vendor specific tag code Length (= N)
(= 3)
1
24-bit IEEE registration identifier (0x000C03)
(least significant byte first)
2
3
4
SPA Field W
SPA Field Y
SPA Field X
SPA Field Z
5
6 to N
Remainder or VSDB is stored in Byte 6 through Byte N
SPA = W. X. Y. Z
Table 8. Vendor Specific Data Block with ADV3002
Byte No.
7
6
5
4
3
2
1
0
A typical vendor specific data block (VSDB) is shown in Table 7.
When using the ADV3002 EDID replicator, the VSDB should
be replaced with the one shown in Table 8, whereby the port
specific field can be assigned to any of the four fields (W, X, Y, or Z)
depending on the value set in the override select bits as shown in
Table 9.
0
Vendor specific
tag code (= 3)
Length (= N)
1
Port A SPA override field
Port C SPA override field
Not used
Port B SPA override field
Port D SPA override field
Override select (see Table 9)
Default X field
2
3
4
Default W field
When calculating the checksum for Block 1 of the EDID, the custom
values entered in place of the IEEE registration identifier should
not be used in the calculation; instead, the IEEE registration iden-
tifier values should be used (0x000C03). The values in Byte 4 and
Byte 5 of the VSDB should be included in the calculation.
5
Default Y field
Default Z field
6 to N
Remainder or VSDB is stored in Byte 6 through Byte N
Table 9. Override Select Assignment
Override Select
Bit 3 Bit 2 Bit 1 Bit 0 Field Replaced by Port Specific SPA
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
W
X
Y
Z
Rev. 0 | Page 14 of 28
ADV3002
Reset
EDID Replication with External EEPROM
Pullling the RESETB pin low initiates a restart of the EDID
replication procedure shown in Figure 25 when the local system
supply is on. If the local system supply is off, the RESETB pin has
no effect.
The ADV3002 has dedicated pins to interface to an external EDID
EEPROM: EDID_SDA and EDID_SCL. In the default configuration,
after the first hot plug event or system power-up, the internal I2C
master in the ADV3002 copies the contents of the external EDID
EEPROM into the on-chip SRAM. While the EDID is being copied,
the HPD signals for all four ports are held low by the ADV3002. A
flowchart of the start-up procedure is shown in Figure 25. The entire
start-up procedure takes less than 10 ms. The EDID replication
feature can be disabled using the EDID_ENABLE pin.
5 V COMBINER
The 5 V combiner circuit combines the four 5 V supplies from
the four HDMI sources and provides the necessary power to the
ADV3002 EDID replication circuit, the CEC buffer, as well as the
external EDID EEPROM, if applicable. The combiner circuit is
designed such that the current limits on each of the 5 V supplies
are not exceeded when the local system power is either on or off.
A simplified circuit diagram of the 5 V combiner is shown in
Figure 26. The combiner detects the presence of the voltage on
the 5 V pin (P5V_x) from the HDMI connectors and closes the
respective internal switch to connect the 5 V to AMUXVCC.
If the local system 3.3 V and 5 V supplies are available, then the
combiner opens all the switches.
POWER-UP, RESET,
OR FIRST HOT PLUG
WAIT
<100µs
FOR EDID POWER-UP
COPY EDID INFORMATION
HPD ALL PORTS = LOW
TO ADV3002 SRAM
<10ms
DETECT
DETERMINE SPA
AND CHECKSUM
P5V_A
DETECT
P5V_B
WAIT FOR EDID
REQUEST
HPD ALL PORTS = HIGH
AMUXVCC
DETECT
RESPOND TO EDID
REQUEST
P5V_C
Figure 25. EDID Replication Start-Up Flowchart with External EEPROM
Writing to the EDID EEPROM
DETECT
P5V_D
The EDID data can be written to the external EEPROM by writing
data via the I2C control interface or via the HDMI A DDC inputs.
In both cases, the EDID write procedure is as follows:
Figure 26. 5 V Combiner Simplified Circuit Diagram
1. Write Value 0x96 to the EDID EEPROM write protect
password register, 0x0F. The ADV3002 fixed part address is
required to write to this register.
2. Write the EDID data to the EEPROM fixed part address
(0xA0). Data must be written one byte at a time.
3. Write Value 0x00 to the EDID EEPROM write protect
password register, 0x0F.
CEC BUFFER
The CEC buffer is bidirectional and includes integrated on-chip
pull-up resistors. The CEC buffer isolates capacitance from the
PCB and local system microcontroller, which is particularly
advantageous in systems where the microcontroller is not placed
near the HDMI connectors. The integrated on-chip pull-up resistors
are connected to an internal 3.3 V supply that is generated from
the AMUXVCC supply; thus, the CEC buffer is fully compliant
with the CEC line degradation specifications, when the local system
power supply is either on or off.
EDID Replication with External Microcontroller
The on-chip SRAM can be preloaded using an external microcontrol-
ler. Prior to loading the SRAM, disable the I2C master by writing
0x01 to the EDID replication mode register. The microcontroller
can then write EDID information into the SRAM via the ADV3002
I2C control interface. The writes to the SRAM should be to the fixed
part address of 0xA0. When the EDID copy process is complete,
enable the EDID replication function by writing 0x00 to the EDID
replication mode register. The EDID_SDA and EDID_SCL pins
are unused when an external microcontroller is used to program
the SRAM. These pins can be tied either high or low through a
resistor, but should not be left floating.
HOT PLUG DETECT CONTROL
The HPD lines going into the ADV3002 are normally high imped-
ance but are pulled low for greater than 100 ms when a channel
switch occurs. This pull-down pulse width can be changed by
modifying the value in the hot plug detect pulse width control
register (0x05), as shown in Table 10. Also, the HPD pulse can be
manually controlled using the hot plug detect manual override
control register (0x06), as shown in Table 10.
Rev. 0 | Page 15 of 28
ADV3002
FD
LOSS OF SIGNAL DETECT
1
0
The TMDS clock line of each HDMI input has a loss of signal (LOS)
monitor attached to it. The purpose of the LOS monitor is to
determine if there is activity in the HDMI link. A simplified
circuit diagram of the LOS detector is shown in Figure 27. The
LOS monitors are disabled by default. The LOS monitors can be
enabled by programming the LOS_EN bit of the LOS detect control
register. When enabled, the status of each HDMI input can be
read in the LOS detect status register. A logic high LOS_STATUS
bit of a given HDMI input indicates an inactive input; a logic low
LOS_S TATUS bit indicates an active input. Three conditions need
to be fulfilled for an HDMI input to be considered active:
LOS_FC
FREQUENCY
DETECTOR
TMDS CLOCK
INPUT[x]
LOS_STATUS[3:0]
FREQUENCY
DETECTOR
AD
1
0
LOS_THR
Figure 27. Loss of Signal Detect Simplified Circuit Diagram
LOS Autosquelch
•
•
•
The TMDS input termination resistors must be enabled. By
default, the ADV3002 TMDS input termination resistors are
enabled only on the selected input.
The TMDS clock frequency exceeds the frequency cutoff
(LOS_FC). Refer to Table 1 for the value of the LOS fre-
quency cutoff.
TMDS clock differential amplitude exceeds the LOS threshold
set in the LOS detect control register. Refer to Table 1 for the
value of the LOS amplitude threshold.
The LOS detect circuit can be used to automatically disable the
TMDS signal path. Setting the LOS_RX_EN bit in the LOS
control register causes the selected TMDS input to be disabled
when an LOS event occurs on that input. In this case, the TMDS
signal path is enabled when the active signal conditions listed
previously are met.
Rev. 0 | Page 16 of 28
ADV3002
SERIAL CONTROL INTERFACE
6. Wait for the ADV3002 to acknowledge the request.
RESET
7. Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8. Wait for the ADV3002 to acknowledge the request.
9. Do one of the following:
On initial power-up, or at any point in operation, the ADV3002
register set can be restored to the default values by pulling the
RESETB pin low according to the specification in Table 3. During
normal operation, however, the RESETB pin must be pulled up
to 3.3 V.
a. Send a stop condition (while holding the I2C_SCL line
high, pull the I2C_SDA line high) and release control of
the bus to end the transaction (shown in Figure 28).
b. Send a repeated start condition (while holding the I2C_SCL
line high, pull the I2C_SDA line low) and continue from
Step 2 in this procedure to perform another write.
c. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue from Step 2 of the read procedure (in the Read
Procedure section) to perform a read from another
address.
d. Send a repeated start condition (while holding the
I2C_SCL line high, pull the I2C_SDA line low) and
continue from Step 8 of the read procedure (in the Read
Procedure section) to perform a read from the same
address set in Step 5 of the write procedure.
WRITE PROCEDURE
To write data to the ADV3002 register set, an I2C master (such as
a microcontroller) needs to send the appropriate control signals to
the ADV3002 slave device. The signals are controlled by the I2C
master unless otherwise specified. For a diagram of the procedure,
see Figure 28. The steps for a write procedure are as follows:
1. Send a start condition (while holding the I2C_SCL line high,
pull the I2C_SDA line low).
2. Send the ADV3002 part address (seven bits). The upper five
bits of the ADV3002 part address are the static value [10010]
and the two LSBs are set by Input Pins I2C_ADDR[1:0]. This
transfer should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADV3002 to acknowledge the request.
5. Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
*
I2C_SCL
R/W
GENERAL CASE
START
FIXED ADDR PART
REGISTER ADDR
DATA
STOP
I2C_SDA
ADDR
ACK
ACK
ACK
EXAMPLE
I2C_SDA
1
2
3
4
5
6
7
8
9
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE LAST DATA BIT;
FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
Figure 28. I2C Write Procedure
Rev. 0 | Page 17 of 28
ADV3002
I2C_SCL
R/W
R/W
GENERAL CASE
I2C_SDA
FIXED PART
ADDR
FIXED PART
ADDR
START
ADDR
REGISTER ADDR
SR
ADDR
DATA
STOP
ACK
ACK
6
ACK
NACK
12
EXAMPLE
I2C_SDA
1
2
3
4
5
7
8
9
10 11
13
Figure 29. I2C Read Procedure
12. Do one of the following:
READ PROCEDURE
a. Send a no acknowledge (NACK) followed by a stop
condition (while holding the I2C_SCL line high, pull the
SDA line high) and release control of the bus to end the
transaction (shown in Figure 29).
b. Send a no acknowledge (NACK) followed by a repeated
start condition (while holding the I2C_SCL line high,
pull the I2C_SDA line low) and continue from Step 2 of
the write procedure (see the previous Write Procedure
section) to perform a write.
c. Send a no acknowledge (NACK) followed by a repeated
start condition (while holding the I2C_SCL line high,
pull the I2C_SDA line low) and continue from Step 2 of
this procedure to perform a read from another address.
d. Send a no acknowledge (NACK) followed by a repeated
start condition (while holding the I2C_SCL line high,
pull the I2C_SDA line low) and continue from Step 8 of
this procedure to perform a read from the next byte.
e. Send an acknowledge (ACK) and read the next byte of
data. Continue from Step 11.
To read data from the ADV3002 register set, an I2C master (such
as a microcontroller) needs to send the appropriate control signals
to the ADV3002 slave device. The signals are controlled by the I2C
master unless otherwise specified. For a diagram of the procedure,
see Figure 29. The steps for a read procedure are as follows:
1. Send a start condition (while holding the I2C_SCL line high,
pull the I2C_SDA line low).
2. Send the ADV3002 part address (seven bits). The upper five
bits of the ADV3002 part address are the static value [10010]
and the two LSBs are set by Input Pins I2C_ADDR[1:0]. This
transfer should be MSB first.
3. Send the write indicator bit (0).
4. Wait for the ADV3002 to acknowledge the request.
5. Send the register address (eight bits) from which data is to be
read. This transfer should be MSB first.
6. Wait for the ADV3002 to acknowledge the request.
7. Send a repeated start condition (Sr) by holding the I2C_SCL
line high and pulling the I2C_SDA line low.
8. Resend the ADV3002 part address (seven bits) from Step 2.
The upper five bits of the ADV3002 part address compose
the static value [10010]. The two LSBs are set by Input Pins I2C_
ADDR[1:0]. This transfer should be MSB first.
13. Send a stop condition (while holding the I2C_SCL line high,
pull the I2C_SDA line high).
9. Send the read indicator bit (1).
10. Wait for the ADV3002 to acknowledge the request.
11. Read the data from the ADV3002. The ADV3002 serially
transfers the data (eight bits) held in the register indicated by
the address set in Step 5. This data is sent MSB first.
Rev. 0 | Page 18 of 28
ADV3002
REGISTER MAP
Table 10. Register Map
Register
Address Default Name
Bit
Channel select 7:3
Bit Name
Unused
Description
0x00
0x00
Unused
control
2
CH_SRC
0: input selected by SEL[1:0] parallel pins
1: input selected by channel select control register, CH[1:0] channel select
00: Input A selected if CH_SRC = 1
01: Input B selected if CH_SRC = 1
1:0
CH[1:0] channel
select
10: Input C selected if CH_SRC = 1
11: Input D selected if CH_SRC = 1
0x01
0x07
TMDS output
control
7:4
3
Unused
TX_EN_SRC
Unused
0: TMDS output enable controlled by the TX_EN parallel pin
1: TMDS output enable controlled by the TX_EN bit
0: TMDS output disabled if TX_EN_SRC = 1
1: TMDS output enabled if TX_EN_SRC = 1
0: TMDS output current = 10 mA
2
1
0
TX_EN
TX_OCL
TX_OTO
1: TMDS output current = 20 mA
0: TMDS output termination = off
1: TMDS output termination = on
0x02
0x03
0x02
0x0F
TMDS input
control
7:2
1
Unused
EQ_SEL
Unused
0: TMDS equalizer boost = 6 dB
1: TMDS equalizer boost = 18 dB
0: TMDS input polarity = standard
0
ISIGN
1: TMDS input polarity = inverse
TMDS input
termination
control
7:4
3:0
ITO_SRC[3:0]
ITO_CTL[3:0]
0000: input termination control is automatic
1111: input termination control is manual
0000: all input terminations off if input termination control is manual
0001: Input A termination on if input termination control is manual
0010: Input B termination on if input termination control is manual
0100: Input C termination on if input termination control is manual
1000: Input D termination on if input termination control is manual
1111: all input terminations on if input termination control is manual
Unused
0x04
0x07
Auxiliary
buffer enables
7:3
2
1
Unused
Reserved
DDC_EN
Reserved; set to 1
0: DDC buffer disabled
1: DDC buffer enabled
0
CEC_EN
0: CEC buffer disabled
1: CEC buffer enabled
0x05
0x06
0x05
0x00
Hot plug
detect pulse
width control
7:0
HPD_PW[7:0]
Pulse width = decimal (HPD_PW) × step size (24 ms typical)
Hot plug
detect manual
override
7:5
4
Unused
HPD_SRC
Unused
0: hot plug detect control is automatic; pulse width set by hot plug
detect pulse width control register
1: hot plug detect control is manual; hot plug detect state is set by
HPD_CTL[3:0]
control
3:0
HPD_CTL[3:0]
0000: HPD outputs are high impedance (pulled up to 5 V via external
resistor)
0001: HPD_A = low if HPD_SRC = 1
0010: HPD_B = low if HPD_SRC = 1
0100: HPD_C = low if HPD_SRC = 1
1000: HPD_D = low if HPD_SRC = 1
1111: all HPD outputs = low if HPD_SRC = 1
Rev. 0 | Page 19 of 28
ADV3002
Register
Address Default Name
Bit
7:6
5:4
Bit Name
Unused
LOS_THR[1:0]
Description
0x07
0x00
Loss of signal
detect control
Unused
00: LOS Threshold 0
01: LOS Threshold 1
10: LOS Threshold 2
11: LOS Threshold 3
Unused
0: TMDS autosquelch disabled
1: TMDS autosquelch enabled
Reserved; set to 0
3
2
Unused
LOS_RX_EN
1
0
Reserved
LOS_EN
0: LOS detect disabled
1: LOS detect enabled
Unused
0x0E
0x00
EDID
7:1
0
Unused
EDID_REPL_EN
(write only)
replication
mode
(write only)
0: EDID replicator enabled; for use with an external EEPROM
1: EDID replicator disabled; external microcontroller can write the
SRAM; write only
0x0F
0x10
0x00
0x00
EDID EEPROM
write protect
password
7:0
PASSWD[7:0]
(write only)
0x00: write protect enabled; EDID EEPROM writes not allowed
0x96: write protect disabled; EDID EEPROM writes from Port A or I2C
control are allowed; write only
(write only)
Loss of signal
detect status
7:4
3:0
Unused
Unused
LOS_STATUS[3:0] 0000: TMDS active on all inputs
(read only)
0001: loss of signal detected on Input A
0010: loss of signal detected on Input B
0100: loss of signal detected on Input C
1000: loss of signal detected on Input D
1111: loss of signal detected on all inputs
0x03: read only
0xFE
0xFF
0x03
0xC2
Revision
7:0
7:0
REV[7:0]
(read only)
Device ID
ID[7:0]
0xC2: read only
(read only)
Rev. 0 | Page 20 of 28
ADV3002
APPLICATIONS INFORMATION
HDMI MULTIPLEXER FOR ADVANCED TV
available when the system power is off, a Thevenin equivalent
2 kΩ pull-up resistor to 3.3 V is shown in Figure 31.
The ADV3002 is a complete HDMI/DVI link switch featuring
equalized TMDS inputs, ideal for systems with long cable runs.
The ADV3002 includes bidirectional buffering for the DDC bus
and CEC line, with integrated pull-up resistors for the CEC line.
Additionally, the ADV3002 includes an EDID replication function
that enables one EDID EEPROM to be shared for all four HDMI
ports. Alternatively, a system standby microcontroller can be
used instead of a dedicated EDID EEPROM to load the ADV3002
SRAM. Simplified application schematics are shown in Figure 33
and Figure 34 illustrating these two options.
5V_COMBINED
AMUXVCC
3kΩ
ADV3002
MCU
CEC_IN
CEC_OUT
6kΩ
Figure 31. CEC Circuit
5 V Power
HDTV SET
The individual 5 V power from each HDMI source can be routed
to the respective 5 V inputs of the ADV3002. The ADV3002
combines these four 5 V supplies into one labeled AMUXVCC
to support EDID replication and CEC functionality when the
local system power is off. An internal 5 V supply must be provided
so that power is not drawn from the HDMI sources when the
local system power is on. When the local supply is off, this internal
5 V should be high impedance. This can be assured by using a
Schottky diode, as shown in Figure 32.
ADV3002
MAIN PCB
HDMI
Rx
OR
SoC
P5V_A
5V INTERNAL
Figure 30. ADV3002 as an HDMI Multiplexer in an HDTV
P5V_B
TMDS Signals
TMDS signals can be routed from an HDMI connector directly
to the inputs of the ADV3002. Additional components are not
required for the TMDS signals.
AMUXVCC
P5V_C
DDC Signals
47 kΩ pull-up resistors to 5 V are recommended for the DDC
input signals.
P5V_D
CEC Signal
The CEC buffer in the ADV3002 provides a fully compliant
input in situations where a general-purpose microcontroller is
used to interpret CEC commands. The rise time of the CEC
buffer is set by the time constant of the pull-up resistance and
the capacitance on the node. A 2 kΩ pull-up resistor to 3.3 V is
recommended for optimal output rise times. If a 3.3 V is not
Figure 32. 5 V Power Connections
Rev. 0 | Page 21 of 28
ADV3002
5V
3.3V
OPTION 1
AMUXVCC
1µF
0.01µF
0.1µF
0.01µF
0.001µF
AMUXVCC
TMDS
D2+
D2–
IN_A_DATA2+
IN_A_DATA2–
AVCC
D1+
D1–
IN_A_DATA1+
IN_A_DATA1–
D0+
D0–
IN_A_DATA0+
IN_A_DATA0–
CLK+
CLK–
IN_A_CLK+
IN_A_CLK–
5V
P5V_A
1kΩ
1kΩ
1kΩ
1kΩ
47kΩ
47kΩ
47kΩ
47kΩ
47kΩ
TMDS
OUT_DATA2+
OUT_DATA2–
D2+
D2–
HPD
DDC_SCL
DDC_SDA
CEC
HPD_A
DDC_SCL_A
DDC_SDA_A
OUT_DATA1+
OUT_DATA1–
D1+
D1–
OUT_DATA0+
OUT_DATA0–
D0+
D0–
HDMI
Rx
TMDS
OUT_CLK+
OUT_CLK–
CLK+
CLK–
D2+
D2–
IN_B_DATA2+
IN_B_DATA2–
AMUXVCC
D1+
D1–
IN_B_DATA1+
IN_B_DATA1–
D0+
D0–
CLK+
CLK–
IN_B_DATA0+
IN_B_DATA0–
IN_B_CLK+
IN_B_CLK–
2kΩ
2kΩ
DDC_SCL_COM
DDC_SDA_COM
DDC_SCL
DDC_SDA
5V
P5V_B
AMUXVCC
ADV3002
47kΩ
3.3V STANDBY
10kΩ
HPD
DDC_SCL
DDC_SDA
CEC
HPD_B
DDC_SCL_B
DDC_SDA_B
CEC_IN
2kΩ
2kΩ
2kΩ
I2C_SCL
I2C_SDA
I2C_ADDR[1:0]
CEC_OUT
TMDS
D2+
D2–
IN_C_DATA2+
IN_C_DATA2–
STANDBY
MCU
D1+
D1–
IN_C_DATA1+
IN_C_DATA1–
10kΩ
OPTIONAL
D0+
D0–
CLK+
CLK–
IN_C_DATA0+
IN_C_DATA0–
IN_C_CLK+
IN_C_CLK–
AVCC
EDID_ENABLE
5V
P5V_C
10kΩ
10kΩ
47kΩ
EDID_SCL
EDID_SDA
HPD
DDC_SCL
DDC_SDA
CEC
HPD_C
DDC_SCL_C
DDC_SDA_C
AMUXVCC
10kΩ
TMDS
D2+
D2–
IN_D_DATA2+
IN_D_DATA2–
RESETB
1µF
D1+
D1–
IN_D_DATA1+
IN_D_DATA1–
TX_EN
D0+
D0–
CLK+
CLK–
IN_D_DATA0+
IN_D_DATA0–
IN_D_CLK+
IN_D_CLK–
SEL[1:0]
5V
P5V_D
47kΩ
HPD
DDC_SCL
DDC_SDA
CEC
HPD_D
DDC_SCL_D
DDC_SDA_D
AVEE
Figure 33. Simplified Application Circuit Diagram (Option 1—No External EEPROM)
Rev. 0 | Page 22 of 28
ADV3002
5V
3.3V
OPTION 2
AMUXVCC
1µF
0.01µF
0.1µF
0.01µF
0.001µF
AMUXVCC
TMDS
D2+
D2–
IN_A_DATA2+
IN_A_DATA2–
AVCC
D1+
D1–
IN_A_DATA1+
IN_A_DATA1–
D0+
D0–
IN_A_DATA0+
IN_A_DATA0–
CLK+
CLK–
IN_A_CLK+
IN_A_CLK–
5V
P5V_A
1kΩ
1kΩ
1kΩ
1kΩ
47kΩ
47kΩ
47kΩ
47kΩ
47kΩ
TMDS
OUT_DATA2+
OUT_DATA2–
D2+
D2–
HPD
DDC_SCL
DDC_SDA
CEC
HPD_A
DDC_SCL_A
DDC_SDA_A
OUT_DATA1+
OUT_DATA1–
D1+
D1–
OUT_DATA0+
OUT_DATA0–
D0+
D0–
HDMI
Rx
TMDS
OUT_CLK+
OUT_CLK–
CLK+
CLK–
D2+
D2–
IN_B_DATA2+
IN_B_DATA2–
AMUXVCC
D1+
D1–
IN_B_DATA1+
IN_B_DATA1–
D0+
D0–
CLK+
CLK–
IN_B_DATA0+
IN_B_DATA0–
IN_B_CLK+
IN_B_CLK–
2kΩ
2kΩ
DDC_SCL_COM
DDC_SDA_COM
DDC_SCL
DDC_SDA
5V
P5V_B
ADV3002
47kΩ
3.3V STANDBY
HPD
DDC_SCL
DDC_SDA
CEC
HPD_B
DDC_SCL_B
DDC_SDA_B
CEC_IN
2kΩ
2kΩ
2kΩ
I2C_SCL
I2C_SDA
I2C_ADDR[1:0]
CEC_OUT
TMDS
D2+
D2–
IN_C_DATA2+
IN_C_DATA2–
MCU
D1+
D1–
IN_C_DATA1+
IN_C_DATA1–
10kΩ
D0+
D0–
CLK+
CLK–
IN_C_DATA0+
IN_C_DATA0–
IN_C_CLK+
IN_C_CLK–
OPTIONAL
AMUXVCC
5V
P5V_C
3.3V STANDBY
10kΩ
47kΩ
3.3V STANDBY
EDID_ENABLE
HPD
DDC_SCL
DDC_SDA
CEC
HPD_C
DDC_SCL_C
DDC_SDA_C
2kΩ
2kΩ
EDID
EEPROM
EDID_SCL
EDID_SDA
TMDS
D2+
D2–
IN_D_DATA2+
IN_D_DATA2–
D1+
D1–
IN_D_DATA1+
IN_D_DATA1–
AMUXVCC
10kΩ
D0+
D0–
CLK+
CLK–
IN_D_DATA0+
IN_D_DATA0–
IN_D_CLK+
IN_D_CLK–
RESETB
TX_EN
5V
P5V_D
SEL[1:0]
1µF
47kΩ
HPD
DDC_SCL
DDC_SDA
CEC
HPD_D
DDC_SCL_D
DDC_SDA_D
AVEE
Figure 34. Simplified Application Diagram (Option 2—External EDID EEPROM)
Rev. 0 | Page 23 of 28
ADV3002
transmission line that does not need to have controlled impedance.
The primary concern with laying out the auxiliary lines is ensuring
that they conform to the I2C bus standard and do not have
excessive capacitive loading.
CABLE LENGTHS AND EQUALIZATION
The ADV3002 offers two levels of programmable equalization
for the high speed inputs: 6 dB and 18 dB. The equalizer of the
ADV3002 supports video data rates of up to 2.25 Gbps and
can equalize more than 20 meters of 24 AWG HDMI cable at
2.25 Gbps, which corresponds to the video format, 1080p with
12-bit Deep Color. The length of cable that can be used in a
typical HDMI/DVI application depends on a large number
of factors including
TMDS Signals
In the HDMI/DVI standard, four differential pairs carry the
TMDS signals. In DVI, three of these pairs are dedicated to
carrying RGB video and sync data. For HDMI, audio data
interleaves with the video data; the DVI standard does not incor-
porate audio information. The fourth high speed differential pair
is used for the A/V data-word clock, and runs at one-tenth the
speed of the TMDS data channels.
•
Cable quality: the quality of the cable in terms of conductor
wire gauge and shielding. Thicker conductors have lower
signal degradation per unit length.
•
•
Data rate: the data rate being sent over the cable. The signal
degradation of HDMI cables increases with data rate.
Edge rates: the edge rates of the source input. Slower input
edges result in more significant data eye closure at the end
of a cable.
The ADV3002 buffers the TMDS signals, and the input traces
can be considered electrically independent of the output traces.
In most applications, the quality of the signal on the input
TMDS traces are more sensitive to the PCB layout. Regardless
of the data being carried on a specific TMDS channel, or
whether the TMDS line is at the input or the output of the
ADV3002, all four high speed signals should be routed on a
PCB in accordance with the same RF layout guidelines.
•
Receiver sensitivity: the sensitivity of the terminating
receiver.
As such, no particular equalizer setting is recommended for
specific cable types or lengths. In nearly all applications, the
ADV3002 equalization level can be set to high, or 18 dB, for all
input cable configurations at all data rates, without degrading the
signal integrity.
Layout for the TMDS Signals
The TMDS differential pairs can be either microstrip traces
(routed on the outer layer of a board) or stripline traces (routed
on an internal layer of the board). If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PCB binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path; therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
PCB LAYOUT GUIDELINES
The ADV3002 switches two distinctly different types of signals,
both of which are required for HDMI and DVI video. These
signal groups require different treatment when laying out a PCB.
The first group of signals carries the A/V data. HDMI/DVI video
signals are differential, unidirectional, and high speed (up to
2.25 Gbps). The channels that carry the video data must be
controlled impedance, terminated at the receiver, and capable of
operating up to at least 2.25 Gbps. It is especially important to
note that the differential traces that carry the TMDS signals
should be designed with a controlled differential impedance of
100 Ω. The ADV3002 provides single-ended 50 Ω terminations
on-chip for both its inputs and outputs, and both the input and
output terminations can be enabled or disabled through the
serial interface. Output termination is recommended but not
required by the HDMI standard but its inclusion improves the
overall system signal integrity.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). Always route the p and n of a given differen-
tial pair together to establish the required 100 Ω differential
impedance. Leave enough space between the differential pairs
of a given group to prevent the n of one pair from coupling with
the p of another pair. For example, one technique is to make the
interpair distance four to 10 times wider than the intrapair spacing.
The A/V data carried on these high speed channels is encoded
by a technique called TMDS, and in the case of HDMI, is also
encrypted according to the HDCP standard.
The second group of signals consists of low speed auxiliary
control signals used for communication between a source and a
sink. Depending upon the application, these signals can include
the DDC bus (this is an I2C bus used to send EDID information
and HDCP encryption keys between the source and the sink),
the CEC line, and the HPD line. These auxiliary signals are
bidirectional, low speed, and transferred over a single-ended
Any one group of four TMDS traces (Input A, Input B, Input C,
Input D, or the output) should have closely matched trace
lengths to minimize interpair skew. Severe interpair skew can
Rev. 0 | Page 24 of 28
ADV3002
THROUGH-HOLE VIAS
cause the data on the four different channels of a group to arrive
out of alignment with one another. A good practice is to match
the trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
Minimizing intrapair and interpair skew becomes increasingly
important as data rates increase. Any introduced skew consti-
tutes a correspondingly larger fraction of a bit period at higher
data rates.
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR
Though the ADV3002 features input equalization and output
preemphasis, minimizing the length of the TMDS traces is needed
to reduce overall system signal degradation. Commonly used
PCB material, such as FR4, is lossy at high frequencies; therefore,
long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
(REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
KEEP REFERENCE PLANE
ADJACENT TO SIGNAL ON ALL
LAYERS TO PROVIDE CONTINUOUS
GROUND CURRENT RETURN PATH.
Controlling the Characteristic Impedance of a TMDS
Differential Pair
Figure 35. Example Routing of Reference Plane
The characteristic impedance of a differential pair depends on
a number of variables, including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. Generally, working with the PCB fabricator is
required to obtain a set of parameters to produce the desired
results.
TMDS Terminations
The ADV3002 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the ADV3002 back terminate
the output TMDS transmission lines. These back terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the ADV3002
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
One consideration is how to guarantee a differential pair with
a differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential pair
are close and strongly coupled, they should have a width that
produces a100 Ω differential impedance. When the traces split
apart to go into a connector, for example, and are no longer so
strongly coupled, the width of the traces need to be increased to
yield a differential impedance of 100 Ω in the new configuration.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
The DDC and CEC signals are buffered and switched through
the ADV3002, and the HPD signal is pulsed low by the ADV3002.
These signals do not need to be routed with the same strict
considerations as the high speed TMDS signals.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the ADV3002. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing dif-
ferential pairs on multiple layers, it is necessary to also reroute
the corresponding reference plane to provide one continuous
ground current return path for the differential signals. Standard
plated through-hole vias are acceptable for both the TMDS
traces and the reference plane. An example of this is illustrated
in Figure 35.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the ADV3002 is being used.
For example, the maximum speed of signals present on the aux-
iliary lines are 100 kHz I2C data on the DDC lines, therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
Rev. 0 | Page 25 of 28
ADV3002
bus should suffice. The HDMI 1.3a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the ADV3002, or an
equivalent receiver. There is a similar limit of 150 pF of input
capacitance for the CEC line. The benefit of the ADV3002 is
that it buffers these lines, isolating the output capacitance so
that only the capacitance at the input side contributes to the
specified limit.
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The trace routing
of this signal is not critical, but it should be routed as directly as
possible.
When the ADV3002 is powered up, the DDC/CEC inputs of the
selected channel are actively buffered and routed to the outputs,
and the unselected auxiliary inputs are high impedance. When
the ADV3002 is powered off, all DDC/CEC inputs are placed in
a high impedance state. This prevents contention on the DDC bus,
enabling a design to include an EDID in front of the ADV3002.
The parasitic capacitance of traces on a PCB increases with trace
length. To help ensure that a design satisfies the HDMI specifica-
tion, make the length of the CEC and DDC lines on the PCB
as short as possible. Additionally, if there is a reference plane
in the layer adjacent to the auxiliary traces in the PCB stackup,
relieving or clearing out this reference plane immediately under
the auxiliary traces significantly decreases the amount of parasitic
trace capacitance. An example of the board stackup is shown in
Figure 36.
Power Supplies
The ADV3002 has two separate power supplies. The supply/
ground pairs are
•
•
AVCC/AVEE
AMUXVCC/AVEE
The AVCC/AVEE (3.3 V) supply powers the core of the
ADV3002. The AMUXVCC/AVEE supply (5 V) powers the
auxiliary multiplexer and EDID replication core.
3W
W
3W
Power Supply Bypassing
The ADV3002 requires minimal supply bypassing. Generally,
place bypass capacitors near the power pins and connect them
directly to the relevant supplies (without long intervening
traces). For example, to improve the parasitic inductance of the
power supply decoupling capacitors, minimize the trace length
between capacitor landing pads and the vias. The capacitors
should via down directly to the supply planes and should be
placed within a few centimeters of the ADV3002.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
Figure 36. Example Board Stackup for Auxiliary Control Signals
Rev. 0 | Page 26 of 28
ADV3002
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
0.75
0.60
0.45
1.60
MAX
61
80
60
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
20
41
0.15
0.05
40
21
SEATING
PLANE
VIEW A
0.65
0.38
0.32
0.22
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 37. 80-Lead Low Profile Quad Flat Package [LQFP]
(ST-80-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV3002BSTZ1
Temperature Range Package Description
Package Option Ordering Quantity
0°C to +85°C
80-Lead Low Profile Quad Flat Package [LQFP]
ST-80-2
ADV3002BSTZ-RL1 0°C to +85°C
ADV3002-EVALZ1
80-Lead Low Profile Quad Flat Package [LQFP], Reel ST-80-2
Evaluation Board
1,000
1 Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
ADV3002
NOTES
Purchase of licensed I2C components of Analog Devices Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C
Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07905-0-12/08(0)
Rev. 0 | Page 28 of 28
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