ADV3205JSTZ [ADI]
60 MHz, G = +2, 16 × 16; 60兆赫，G = 2 ， 16×16
| 型号： | ADV3205JSTZ |
| 厂家： | 
ADI |
| 描述： | 60 MHz, G = +2, 16 × 16 |
| 文件： | 总20页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60 MHz, G = +2, 16 × 16
Buffered Analog Crosspoint Switch
ADV3205
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SER/PAR D0 D1 D2 D3 D4
16 × 16 high speed nonblocking switch array
Serial or parallel programming of switch array
Serial data out allows daisy-chaining control of multiple
16 × 16 devices to create larger switch arrays
Complete solution
A0
A1
A2
CLK
A3
80-BIT SHIFT REGISTER
WITH 5-BIT
PARALLEL LOADING
DATA
OUT
DATA IN
UPDATE
Buffered inputs
16 output amplifiers
80
SET
INDIVIDUAL
OR RESET
ALL OUTPUTS
TO “OFF”
Operates on ±± V supplies
Low supply current of ±0 mA
PARALLEL LATCH
CE
RESET
80
Excellent video performance, VS = ±± V
−3 dB bandwidth: 60 MHz
16
DECODE
16 × 5:16 DECODERS
0.1 dB gain flatness: 10 MHz
OUTPUT
BUFFER
G = +2
ADV3205
256
0.1% differential gain error (RL = 1 kΩ)
0.1° differential phase error (RL = 1 kΩ)
Low all hostile crosstalk: −67 dB at ± MHz
Output disable allows connection of multiple devices
without loading the output bus
SWITCH
MATRIX
RESET
pin allows disabling of all outputs
16
16 INPUTS
OUTPUTS
Power-on reset capability with capacitor to ground
100-lead LQFP (14 mm × 14 mm)
APPLICATIONS
CCTV surveillance
Video routers (NTSC, PAL, S-Video, SECAM)
Video conferencing
Figure 1.
GENERAL DESCRIPTION
The ADV3205 is a fully buffered crosspoint switch matrix that
operates on 5 V, making it ideal for video applications. It offers
a −3 dB signal bandwidth of 60 MHz and channel switch times of
less than 60 ns with 0.1% settling. The ADV3205 has excellent
crosstalk performance, and ground/power pins surround all inputs
and outputs to provide extra shielding required for the most
demanding applications. The differential gain and differential
phase of better than 0.1% and 0.1°, respectively, along with 0.1 dB
flatness out to 10 MHz, make the ADV3205 an excellent choice
for many video applications.
The ADV3205 includes 16 independent output buffers that can
be placed into a disabled state for paralleling crosspoint outputs.
The ADV3205 has a gain of +2 and operates on voltage supplies
of 5 V while consuming only 34 mA of current. Channel
switching is performed via a serial digital control (which can
accommodate daisy-chaining of several devices) or via a parallel
control, allowing updating of an individual output without
reprogramming the entire array.
The ADV3205 is packaged in a 100-lead LQFP and is available
over the commercial temperature range of 0°C to 70°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
ADV3205
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics (Serial Mode) ....................................... 4
Timing Characteristics (Parallel Mode).................................... 5
Absolute Maximum Ratings............................................................ 6
Power Dissipation......................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Truth Table and Logic Diagram ................................................. 9
Typical Performance Characteristics ........................................... 10
Circuit Diagrams ............................................................................ 13
Theory of Operation ...................................................................... 14
Short-Circuit Output Conditions............................................. 14
Applications Information.............................................................. 15
Serial Programming................................................................... 15
Parallel Programming................................................................ 15
Power-On Reset.......................................................................... 16
Managing Video Signals............................................................ 16
Creating Larger Crosspoint Arrays.......................................... 16
Multichannel Video ................................................................... 17
Crosstalk...................................................................................... 17
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
12/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
ADV3205
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 150 Ω, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VOUT = 200 mV p-p
VOUT = 2 V p-p
0.1 dB, VOUT = 200 mV p-p
VOUT = 2 V p-p
0.1%, 2 V output step
2 V output step
41
60
25
10
20
23
100
MHz
MHz
MHz
ns
ns
V/μs
Gain Flatness
Propagation Delay
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation
Input Voltage Noise
DC PERFORMANCE
Gain Error
NTSC, RL = 1 kΩ
NTSC, RL = 1 kΩ
f = 5 MHz
f = 5 MHz, one channel
0.1 MHz to 10 MHz
0.1
0.1
−67
−100
12
%
Degrees
dB
dB
nV/√Hz
0.5
0.7
20
%
%
Gain Matching
Channel-to-channel
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Resistance
ppm/°C
Enabled
0.3
4
5
3.5
3
Ω
Disabled
Disabled
No Load
3.4
kΩ
pF
V
Output Capacitance
Output Voltage Swing
3.2
2.7
IOUT = 20 mA
V
Short-Circuit Current
INPUT CHARACTERISTICS
Input Offset Voltage
55
mA
All configurations
Temperature coefficient
No load
Any switch configuration
Any number of connected outputs
Any number of enabled inputs
5
10
1.5
4
50
1
10
mV
μV/°C
V
pF
MΩ
μA
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
80
50
20
ns
ns
mV p-p
50% update to 1% settling
Supply Current
AVCC outputs enabled, no load
AVCC outputs disabled
AVEE outputs enabled, no load
AVEE outputs disabled
45
31
45
31
8
50
35
50
35
13
mA
mA
mA
mA
mA
DVCC outputs enabled, no load
DYNAMIC PERFORMANCE
Supply Voltage Range
AVCC
AVEE
DVCC
DC
f = 100 kHz
f = 1 MHz
4.5
−5.5
4.5
75
5.5
−4.5
5.5
V
V
V
dB
dB
dB
PSRR
80
60
40
Rev. 0 | Page 3 of 20
ADV3205
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Operating (still air)
Operating (still air)
0
70
°C
°C/W
40
TIMING CHARACTERISTICS (SERIAL MODE)
Table 2.
Limit
Typ
Parameter
Symbol
Min
20
100
20
100
0
Max
Unit
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation, Serial Mode
CLK-to-UPDATE Delay
t1
t2
t3
t4
t5
t6
t7
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
UPDATE Pulse Width
50
CLK-to-DATA OUT Valid, Serial Mode
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
CLK, UPDATE Rise and Fall Times
RESET Time
200
50
16
100
200
t2
t4
1
CLK
0
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
t1
t3
1
0
DATA IN
OUT07 (D3)
OUT00 (D0)
OUT07 (D4)
t5
t6
1 = LATCHED
UPDATE
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
0 = TRANSPARENT
t7
DATA OUT
Figure 2. Timing Diagram, Serial Mode
Table 3. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR
CLK, DATA IN, CE,
UPDATE
RESET, SER/PAR
CLK, DATA IN, CE,
UPDATE
RESET, SER/PAR
CLK, DATA IN, CE,
UPDATE
RESET, SER/PAR
CLK, DATA IN, CE,
UPDATE
DATA OUT
2.7 V min
DATA OUT
0.5 V max
DATA OUT
DATA OUT
2.0 V min
0.8 V max
20 μA max
−400 μA min
−400 μA max 3.0 mA min
Rev. 0 | Page 4 of 20
Data Sheet
ADV3205
TIMING CHARACTERISTICS (PARALLEL MODE)
Table 4.
Limit
Max
Parameter
Symbol
Min
20
20
100
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parallel Data Setup Time
Address Setup Time
CLK Enable Width
Parallel Data Hold Time
Address Hold Time
CLK Pulse Separation
CLK-to-UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
CLK, UPDATE Rise and Fall Times
RESET Time
t1d
t1a
t2
t3d
t3a
t4
100
0
t5
t6
50
50
100
200
t2
t4
1
CLK
0
t1a
t3a
1
A0 TO A3
0
t1d
t3d
1
D0 TO D4
0
t5
t6
1 = LATCHED
UPDATE
0 = TRANSPARENT
Figure 3. Timing Diagram, Parallel Mode
Table 5. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2, D3, D4, A0, A1, A2,
RESET, SER/PAR
CLK, D0, D1, D2,
RESET, SER/PAR
CLK, D0, D1, D2,
D3, D4, A0, A1, A2, D3, D4, A0, A1, A2,
RESET, SER/PAR
CLK, D0, D1, D2,
A3, CE, UPDATE
A3, CE, UPDATE
A3, CE, UPDATE
A3, CE, UPDATE
DATA OUT DATA OUT
2.7 V min 0.5 V max
DATA OUT
DATA OUT
2.0 V min
0.8 V max
20 μA max
−400 μA min
−400 μA max 3.0 mA min
Rev. 0 | Page 5 of 20
ADV3205
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
POWER DISSIPATION
Packaged in a 100-lead LQFP, the ADV3205 junction-to-ambient
thermal impedance (θJA) is 40°C/W. For long-term reliability,
the maximum allowed junction temperature of the plastic
encapsulated die should not exceed 150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of 175°C for an extended
period can result in device failure.
Parameter
Rating
12 V
6 V
Analog Supply Voltage (AVCC to AVEE)
Digital Supply Voltage (DVCC to DGND)
Ground Potential Difference (AGND to
DGND)
Internal Power Dissipation1
Analog Input Voltage2
Digital Input Voltage
0.5 V
3.1 W
Maintain linear output
DVCC
Output Voltage (Disabled Output)
(AVCC − 1.5 V) to
(AVEE + 1.5 V)
Momentary
−65°C to +125°C
300°C
The maximum ADV3205 power dissipation occurs when all
outputs are enabled and driving loads. Supply current increases
approximately linearly with the number of outputs that are enabled.
Refer to the Theory of Operation section for more details regarding
power dissipation calculations. Figure 4 indicates the maximum
ADV3205 power dissipation as a function of ambient temperature.
Output Short-Circuit Duration
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
1 Specification is for device in free air (TA = 25°C):
100-lead plastic LQFP: θJA = 40°C/W.
2 To avoid differential input breakdown, in no case should one-half the output
voltage (1/2 VOUT) and any input voltage be greater than 10 V potential
differential. See the output voltage swing parameter in Table 1 for the linear
output range.
4.0
T
= 150°C
J
3.5
3.0
2.5
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 6 of 20
Data Sheet
ADV3205
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DV
DV
CC
CC
PIN 1
2
DGND
DGND
AGND
IN07
3
4
AGND
IN08
5
AGND
IN09
AGND
IN06
6
7
AGND
IN10
AGND
IN05
8
9
AGND
IN11
AGND
IN04
ADV3205
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AGND
IN12
TOP VIEW
(Not to Scale)
AGND
IN03
AGND
IN13
AGND
IN02
AGND
IN14
AGND
IN01
AGND
IN15
AGND
IN00
AGND
AGND
AV
AV
AV
EE
CC
EE
CC
AV
AV 15
CC
AV 00
CC
OUT15
OUT00
AV 14/15
EE
AV 00/01
EE
OUT14
OUT01
NC = NO CONNECT
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin Number
Mnemonic Description
1, 75
DVCC
5 V for Digital Circuitry.
2, 74
DGND
AGND
Ground for Digital Circuitry.
Analog Ground for Inputs and Switch Matrix.
3, 5, 7, 9, 11, 13, 15, 17, 19, 57,
59, 61, 63, 65, 67, 69, 71, 73
4, 6, 8, 10, 12, 14, 16, 18, 58, 60, INxx
62, 64, 66, 68, 70, 72
Analog Inputs; xx = Channel Number 00 through Channel Number 15.
20, 56
AVEE
−5 V for Inputs and Switch Matrix.
21, 55
AVCC
5 V for Inputs and Switch Matrix.
22, 54
26, 30, 34, 38, 42, 46, 50
23, 25, 27, 29, 31, 33, 35, 37,
39, 41, 43, 45, 47, 49, 51, 53
AVCCxx
AVCCxx/yy
OUTyy
5 V for Output Amplifier that is used by Channel Number xx.
5 V for Output Amplifier that is shared by Channel Number xx and Channel Number yy.
Analog Outputs; yy = Channel Number 00 Through Channel Number 15.
24, 28, 32, 36, 40, 44, 48, 52
AVEExx/yy
D4
D3
D2
D1
−5 V for Output Amplifier that is shared by Channel Number xx and Channel Number yy.
Parallel Data Input, TTL Compatible (Output Enable).
Parallel Data Input, TTL Compatible (Input Select MSB).
Parallel Data Input, TTL Compatible (Input Select).
76
77
78
79
Parallel Data Input, TTL Compatible (Input Select).
Rev. 0 | Page 7 of 20
ADV3205
Data Sheet
Pin Number
Mnemonic Description
80
D0
Parallel Data Input, TTL Compatible (Input Select LSB).
81
82
83
84
85 to 93
94
A3
A2
A1
A0
NC
SER/PAR
UPDATE
Parallel Data Input, TTL Compatible (Output Select MSB).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select).
Parallel Data Input, TTL Compatible (Output Select LSB).
No Connect. Do not connect to this pin.
Selects Serial Data Mode, Low or Parallel Data Mode, High.
95
Enable (Transparent) Low. Allows serial register to connect directly to switch matrix.
Data latched when high.
96
97
98
99
100
DATA IN
CLK
DATA OUT
CE
Serial Data Input, TTL Compatible.
Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Chip Enable, Enable Low. Must be low to clock in and latch data.
Disable Outputs, Active Low.
RESET
Rev. 0 | Page 8 of 20
Data Sheet
ADV3205
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table1
CE UPDATE
RESET SER/PAR
CLK DATA IN
DATA OUT
X
Data i-80
Operation/Comment
1
0
X
1
X
X
X
1
X
0
No change in logic.
Data i
The data on the serial DATA IN line is loaded into the serial
register. The first bit clocked into the serial register appears at
DATA OUT 80 clocks later.
2
↓
0
1
D0 ... D4,
A0 ... A3
Not
1
1
The data on the parallel data lines, D0 to D4, are loaded into
the 80-bit serial shift register location addressed by A0 to A3.
3
↓
applicable
in parallel
mode
0
0
X
X
X
X
X
1
0
X
X
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
X
X
X
1 X = don’t care, 0 = logic low, 1 = logic high, and ↓ = falling edge triggered.
2 ↓ = falling edge triggered.
3 ↓ = low level triggered.
D0
PARALLEL D1
DATA
D2
D3
D4
(OUTPUT
ENABLE)
SER/PAR
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
S
D1
DATA
OUT
D Q
CLK
D
Q
D Q
CLK
D
Q
D
Q
D
Q
D
Q
D Q
CLK
D
Q
D
Q
D
Q
D
Q
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
DATA IN
(SERIAL)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CE
UPDATE
OUT00 EN
OUT01 EN
OUT02 EN
OUT03 EN
OUT04 EN
OUT05 EN
OUT06 EN
OUT07 EN
OUT08 EN
OUT09 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A0
A1
A2
A3
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
OUT00
B0
OUT00
B1
OUT00
B2
OUT00
B3
OUT00
EN
OUT01
B0
OUT14
EN
OUT15
B0
OUT15
B1
OUT15
B2
OUT15
B3
OUT15
EN
Q
Q
Q
Q
CLR
Q
Q
CLR
Q
Q
Q
Q
Q
CLR Q
RESET
(OUTPUT ENABLE)
DECODE
256
16
OUTPUT ENABLE
SWITCH MATRIX
Figure 6. Logic Diagram
Rev. 0 | Page 9 of 20
ADV3205
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VS = 5 V, RL = 150 Ω, unless otherwise noted.
3
3
0
0
–3
–6
–3
–6
0.01
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 7. Small Signal Bandwidth, VOUT = 200 mV p-p
Figure 10. Large Signal Bandwidth, VOUT = 2 V p-p
0.3
0.2
0.3
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
0.1
1
10
FREQUENCY (MHz)
100
0.1
1
10
FREQUENCY (MHz)
100
Figure 11. Large Signal Gain Flatness, VOUT = 2 V p-p
Figure 8. Small Signal Gain Flatness, VOUT = 200 mV p-p
–50
–60
–40
–50
–60
–70
–80
–90
–100
ALL HOSTILE
–70
ADJACENT
–80
SECOND HARMONIC
–90
THIRD HARMONIC
–100
–110
0.001
0.01
0.1
1
10
100
0.1
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 9. Crosstalk vs. Frequency, VOUT = 2 V p-p
Figure 12. Distortion vs. Frequency, VOUT = 2 V p-p
Rev. 0 | Page 10 of 20
Data Sheet
ADV3205
0
–10
–20
–30
–40
–50
–60
–70
–80
160
140
120
100
80
+PSRR
–PSRR
60
40
20
–90
0.01
0
10
0.1
FREQUENCY (MHz)
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency
Figure 16. Noise vs. Frequency
1k
100
10
10k
1k
100
10
1
1
0.1
0.1
1
10
100
1k
0.1
1
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. Enabled Output Impedance vs. Frequency
Figure 17. Disabled Output Impedance vs. Frequency
0
–20
INPUT
–40
–60
OUTPUT
OUTPUT
– INPUT
2
–80
–100
–120
0
5
10
5
20
25
30
35
40
45
50
0.1
1
10
FREQUENCY (MHz)
100
5ns/DIV
Figure 18. Settling Time to 0.1%, 2 V Output Step
Figure 15. Off Isolation vs. Frequency, VOUT = 2 V p-p
Rev. 0 | Page 11 of 20
ADV3205
Data Sheet
5ns/DIV
100ns/DIV
Figure 19. Small Signal Pulse Response
Figure 22. Large Signal Pulse Response
UPDATE
UPDATE
1V/DIV
INPUT 1
V
OUT
OUTPUT
20mV/DIV
INPUT 0
100ns/DIV
100ns/DIV
Figure 23. Switching Transient
Figure 20. Switching Time
300
250
200
150
100
50
0
0
5
10
15
20
25
30
35
SERIES RESISTANCE (Ω)
Figure 21. CLOAD vs. Series Resistance for Less than 30% Overshoot
Rev. 0 | Page 12 of 20
Data Sheet
ADV3205
CIRCUIT DIAGRAMS
AV
DV
CC
CC
ESD
ESD
ESD
INPUT
INPUT
ESD
AV
DGND
EE
Figure 27. Logic Input
Figure 24. Analog Input
DV
CC
AV
CC
2kΩ
ESD
ESD
ESD
OUTPUT
OUTPUT
ESD
DGND
AV
EE
Figure 28. Logic Output
Figure 25. Analog Output
DV
CC
20kΩ
ESD
RESET
ESD
DGND
Figure 26. Reset Input
Rev. 0 | Page 13 of 20
ADV3205
Data Sheet
THEORY OF OPERATION
The ADV3205 is a gain-of-two crosspoint array with 16 outputs,
each of which can be connected to any one of 16 inputs.
Organized by output row, 16 switchable transconductance
stages are connected to each output buffer in the form of a
16-to-1 multiplexer. Each of the 16 rows of transconductance
stages are wired in parallel to the 16 input pins, for a total array
of 256 transconductance stages. Decoding logic for each output
selects one (or none) of the transconductance stages to drive the
output stage. The transconductance stages are NPN input differential
pairs, sourcing current into the folded cascode output stage.
The compensation networks and emitter follower output buffers
are in the output stage. Voltage feedback sets the gain at +2.
The ADV3205 contains internal crosstalk isolation clamps that
have variable bias levels. These levels were chosen to allow the
necessary input range to accommodate the full output swing
with a gain of +2. Overdriving the inputs beyond the linear
range of the device eventually forward biases these clamps,
increasing the power dissipation. The valid input range is 1.5 V.
When outputs are disabled and being driven externally, the
voltage applied to them should not exceed the valid input swing
range for the ADV3205.
A flexible TTL-compatible logic interface simplifies the
programming of the matrix. Either parallel or serial loading
into a first rank of latches programs each output. A global latch
simultaneously updates all outputs. In serial mode, a serial data out
pin (DATA OUT) allows devices to be daisy chained together
for single pin programming of multiple ICs. A power-on reset
function can be implemented to avoid bus conflicts by disabling
all outputs.
The ADV3205 can drive reverse-terminated video loads,
swinging 3.0 V into 150 ꢀ. Disabling unused outputs
and transconductance stages minimizes on-chip power
consumption.
Features of the ADV3205 facilitate the construction of larger
switch matrices. The unused outputs can be disabled, leaving
only a feedback network resistance of 4 kΩ on the output. This
allows multiple ICs to be bused together, provided the output
load impedance is greater than the minimum allowed values.
Because no additional input buffering is necessary, high input
resistance and low input capacitance are easily achieved without
additional signal degradation.
The digital logic requires 5 V on the DVCC pin with respect to
DGND. Internal ESD protection diodes require that the DGND
and AGND pins be at the same potential.
SHORT-CIRCUIT OUTPUT CONDITIONS
Although there is short-circuit current protection on the ADV3205
outputs, the short-circuit output current can reach levels that
can result in device failure. Do not operate the ADV3205 with a
sustained short to ground on any of its outputs.
The ADV3205 inputs have a unique bias current compensation
scheme that overcomes a problem common to transconductance
input array architectures. Typically, input bias current increases
as more and more transconductance stages connected to the same
input are turned on. Anywhere from 0 to 16 transconductance
stages can be sharing one input pin, so there is a varying amount of
bias current supplied through the source impedance driving the
input. The ADV3205 samples and cancels the input bias current
contributions from each transconductance stage so that the
residual bias current is nominally zero, regardless of the number
of enabled inputs.
Rev. 0 | Page 14 of 20
Data Sheet
ADV3205
APPLICATIONS INFORMATION
The ADV3205 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 80 bits can
be provided that updates the entire matrix in one serial operation.
The second option allows for changing the programming of a
single output via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the
programming, whereas the parallel programming technique
requires more signals, but can change a single output at a time,
and requires fewer clock cycles to complete programming.
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows for the modification of a
single output at a time. Because this takes only one CLK/
cycle, significant time savings can be realized by using parallel
programming.
UPDATE
One important consideration in using parallel programming is
RESET
When taken low, the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
that the
signal does not reset all registers in the ADV3205.
RESET
SERIAL PROGRAMMING
signal only sets each output to the
CE
The serial programming mode uses the device pins: , CLK,
UPDATE
SER
SER
/PAR. The first step is to assert a
DATA IN,
low on
, and
/PAR to enable the serial programming mode.
CE
After initial power-up, the internal registers in the device generally
contain random data, even though the
for the chip must be low to allow data to be clocked into the
CE
RESET
signal has been
device. The
signal can be used to address an individual
asserted. If parallel programming is used to program one output,
that output is properly programmed but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output at a time.
device when devices are connected in parallel.
UPDATE
The
shifted into the serial port of the device. Although the data still
UPDATE
signal should be high during the time that data is
shifts in when
is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
CE
UPDATE
are taken low after
In similar fashion, if both
and
The data at DATA IN is clocked in at every down edge of CLK. A
total of 80 bits must be shifted into the shift register via the DATA
IN input to complete the programming. For each of the 16 outputs,
there are four bits (D0 to D3) that determine the source of its
input followed by one bit (D4) that determines the enabled state
of the output. If D4 is low (output disabled), the four associated
bits (D0 to D3) do not matter because no input is switched to
that output.
initial power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
CE
UPDATE
low logic levels to both
and
after power is initially
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial power-up,
eliminates the possibility of programming the matrix to an
unknown state.
The most significant output address data is shifted into the shift
register first, following in sequence until the least significant
To change the output’s programming via parallel programming,
UPDATE
SER
UPDATE
CE
output address data is shifted in. At this point
can be
take
/PAR and
high and take low. The CLK
taken low, which causes the programming of the device according
signal should be in the high state. Put the 4-bit address of the
output to be programmed on the A0 to A3 pins. The first four
data bits (D0 to D3) should contain the information that identifies
the input that is programmed to the output that is addressed.
The fifth data bit (D4) determines the enabled state of the output. If
D4 is low (output disabled), the data on D0 to D3 does not matter.
UPDATE
is low (and
to the data that was just shifted in. The
registers are
CE
is low), the
UPDATE
asynchronous, and when
registers are transparent.
When more than one ADV3205 device is serially programmed in a
system, the DATA OUT signal from one device can be connected
to the DATA IN of the next device to form a serial chain. Connect
After the desired address and data signals are established, they
can be latched into the shift register by a high-to-low transition
of the CLK signal. The matrix is not programmed, however, until
CE UPDATE SER
all of the CLK,
,
, and /PAR pins in parallel and
operate them as previously described. The serial data is input to
the DATA IN pin of the first device of the chain, and it ripples
through to the last. Therefore, the data for the last device in the
chain should come at the beginning of the programming sequence.
The length of the programming sequence is 80 bits times the
number of devices in the chain.
UPDATE
the
signal is taken low. It is thus possible to latch in
new data for several or all of the outputs first via successive
UPDATE
negative transitions of CLK while
is held high and then
UPDATE
have all of the new data take effect when
goes low.
Use this technique when programming the device for the first
time after power-up when using parallel programming.
Rev. 0 | Page 15 of 20
ADV3205
Data Sheet
The ADV3205 outputs are low impedance and do not properly
terminate the source end of a 75 Ω transmission line. In these
cases, insert a series 75 Ω resistor at an output that drives a video
signal. Then terminate the 75 Ω transmission line with 75 Ω at
its far end. This overall termination scheme divides the amplitude
of the ADV3205 output by two. An overall unity-gain channel is
produced because of the channel gain-of-two of the ADV3205.
POWER-ON RESET
When powering up the ADV3205, it is usually desirable to have
RESET
the outputs start up in the disabled state. The
taken low, causes all outputs to be in the disabled state. However,
RESET
pin, when
the
signal does not reset all registers in the ADV3205.
This is important when operating in parallel programming mode.
Refer to the Parallel Programming section for information
about programming internal registers after power-up. Serial
programming programs the entire matrix each time; therefore,
no special considerations apply.
CREATING LARGER CROSSPOINT ARRAYS
The ADV3205 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 16. Various
features, such as output disable and chip enable, are useful for
creating larger arrays.
Because the data in the shift register is random after power-up,
do not use it to program the matrix or the matrix can enter
unknown states. To prevent this, do not apply logic low signals
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required. The
16 × 16 architecture of the ADV3205 contains 256 points, which is
a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer). The
printed circuit board (PCB) area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.
CE
UPDATE
to both
and
initially after power-up. First, load the
UPDATE
shift register with the desired data, and then take
to program the device.
low
RESET
The
used to create a simple power-up reset circuit. A capacitor from
RESET RESET
pin has a 20 kꢀ pull-up resistor to DVCC that can be
to ground holds
low for some time while the rest
of the device stabilizes. The low condition causes all outputs to
be disabled. The capacitor then charges through the pull-up resistor
to the high state, thus allowing full programming capability of
the device.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.
MANAGING VIDEO SIGNALS
Some nonblocking crosspoint architectures require more than this
minimum as previously calculated. In addition, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical
basis that is determined when designing the overall system.
Video signals often use controlled impedance transmission lines
that are terminated in their characteristic impedance. Although this
is not always the case, there are some considerations when using
the ADV3205 to route video signals with controlled impedance
transmission lines. Figure 29 shows a schematic of an input
and output treatment of a typical video channel.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by looking at a
diagram. Figure 30 illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3205 devices. Note that the 75 ꢀ source
terminations are not shown on the outputs, but they are required
when driving the 75 ꢀ transmission lines.
+5V
75Ω
TRANSMISSION
TYPICAL
INPUT
TYPICAL
OUTPUT
LINE
ADV3205
G = 2
75Ω
75Ω
75Ω
75Ω
VIDEO
SOURCE
–5V
Figure 29. Video Signal Circuit
Video signals most often use 75 Ω transmission lines that need
to be terminated with this value of resistance at each end. When
such a source is delivered to one of the ADV3205 inputs, the
high input impedance does not properly terminate these signals.
Therefore, terminate the line with a 75 Ω shunt resistor to
ground. Because video signals are limited in their peak-to-peak
amplitude (typically no more than 1.5 V p-p), there is no need
to attenuate video signals before they pass through the ADV3205.
16
16
IN00 TO IN15
ADV3205
ADV3205
75Ω
16
8
16
16
IN16 TO IN31
ADV3205
ADV3205
75Ω
16
16
16
16
Figure 30. 32 × 32 Crosspoint Array Using Four ADV3205 Devices
Rev. 0 | Page 16 of 20
Data Sheet
ADV3205
The inputs are individually assigned to each of the 32 inputs of
the two devices, and the shunt 75 Ω terminations are placed at
the end of the transmission lines. The outputs are wire-OR’ed
together in pairs. Only enable one of the outputs from a wire-
ORed pair at any given time. The device programming software
must be properly written to achieve this.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
and blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R–Y, and B–Y format, sometimes called YUV
format. These three circuit video standards are referred to as
analog component video.
MULTICHANNEL VIDEO
The analog component video standards require three crosspoint
channels per video channel to handle the switching function. In
a fashion similar to the two circuit video formats, the inputs and
outputs are assigned in groups of three, and the appropriate logic
programming is performed to route the video signals.
The good video specifications of the ADV3205 make it an ideal
candidate for creating composite video crosspoint switches. These
switches can be made quite dense by taking advantage of the
high level of integration of the ADV3205 and the fact that
composite video requires only one crosspoint channel per system
video channel. There are, however, other video formats that can
be routed with the ADV3205, requiring more than one crosspoint
channel per video channel.
CROSSTALK
Many video systems have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals of
other nearby channels to a given channel.
Some systems use twisted pair wiring to carry video signals.
These systems use differential signals and can lower costs
because they use lower cost cables, connectors, and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments, or where common-mode
voltages are present between transmitting and receiving equipment.
When there are many signals in proximity in a system, as is the
case in a system that uses the ADV3205, the crosstalk issues can
be quite complex. A good understanding of the nature of crosstalk
and some definition of terms is required to specify a system that
uses one or more ADV3205 devices.
In such systems, the video signals are differential; there are positive
and negative (or inverted) versions of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field, and
sharing of common impedances. This section explains these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and couples
with the receiver and induces a voltage. This voltage is an unwanted
crosstalk signal in any channel that receives it.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single ADV3205, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
effectively forms an 8 × 8 differential crosspoint switch.
Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields then generate voltages
in any other conductors with whose paths they link. The undesired
induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual inductance
that couples signals from one channel to another.
Programming such a device requires that the inputs and outputs
be programmed in pairs. This information can be deduced through
inspection of the programming format of the ADV3205 and the
requirements of the system.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an input
crosstalk signal for other channels that share the common
impedance.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in video systems is S-Video or Y/C Video.
The Y/C Video format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
All these sources of crosstalk are vector quantities; therefore, the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Because S-Video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems are the same.
Rev. 0 | Page 17 of 20
ADV3205
Data Sheet
Each of these cases is legitimately different from the others and
may yield a unique value, depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if the
possible combinations and permutations for connecting inputs
to the other outputs (not used for measurement) are taken into
consideration, the numbers grow impractically large. If a larger
crosspoint array of multiple ADV3205 devices is constructed, the
numbers grow larger still.
Areas of Crosstalk
A practical ADV3205 circuit must be mounted to some sort of
circuit board to connect it to power supplies and measurement
equipment. This, however, raises the issue that the crosstalk of a
system is a combination of the intrinsic crosstalk of the devices
in addition to the circuit board to which they are mounted. It is
important to try to separate these two areas when attempting to
minimize the effect of crosstalk.
In addition, crosstalk can occur among the inputs to a cross-
point and among the outputs. It can also occur from input to
output. Techniques are presented in the following sections for
diagnosing which part of a system is contributing to crosstalk,
as well as minimizing crosstalk.
Clearly, some subset of all these cases must be selected to be used as
a guide for a practical measure of crosstalk. One common method
is to measure all hostile crosstalk; this means that the crosstalk to
the selected channel is measured while all other system channels
are driven in parallel. In general, this yields the worst crosstalk
number, but this is not always the case, due to the vector nature
of the crosstalk signal.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by
Other useful crosstalk measurements are those that are created by
one nearest neighbor or by the two nearest neighbors on either
side. These crosstalk measurements are generally higher than those
of more distant channels, so they can serve as a worst-case measure
for any other 1-channel or 2-channel crosstalk measurements.
|XT| = 20log10(Asel(s)/Atest(s))
where:
s = jw, the Laplace transform variable.
Asel(s) is the amplitude of the crosstalk induced signal in the
selected channel.
Input and Output Crosstalk
The flexible programming capability of the ADV3205 can be
used to diagnose whether crosstalk is occurring more on the
input side or the output side. Some examples are illustrative. A
given input channel (IN07 in the middle for this example) can
be programmed to drive OUT07 (also in the middle). The input
to IN07 is just terminated to ground (via 50 Ω or 75 Ω) and no
signal is applied.
Atest(s) is the amplitude of the test signal.
It can be seen that crosstalk is a function of frequency, but not a
function of the magnitude of the test signal (to the first order).
In addition, the crosstalk signal has a phase relative to the test
signal associated with it.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magnitude
and phase information about the crosstalk signal.
All the other inputs are driven in parallel with the same test signal
(provided by a distribution amplifier), with all other outputs
except OUT07 disabled. Because grounded IN07 is programmed
to drive OUT07, no signal should be present. Any signal that is
present can be attributed to the other 15 hostile input signals
because no other outputs are driven (they are all disabled).
Thus, this method measures the all-hostile input contribution
to crosstalk into IN07. Of course, the method can be used for
other input channels and combinations of hostile inputs.
As a crosspoint system or device grows larger, the number of
theoretical crosstalk combinations and permutations can become
extremely large. For example, in the case of the 16 × 16 matrix
of the ADV3205, note the number of crosstalk terms that can be
considered for a single channel, such as the IN00 input. IN00 is
programmed to connect to one of the ADV3205 outputs where
the measurement can be made.
For output crosstalk measurement, a single input channel is
driven (IN00, for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 (far away
from IN00), which is terminated to ground. Therefore, OUT07
should not have a signal present because it is listening to a quiet
input. Any signal measured at OUT07 can be attributed to the
output crosstalk of the other 16 hostile outputs. Again, this method
can be modified to measure the other channels and the other
crosspoint matrix combinations.
First, the crosstalk terms associated with driving a test signal into
each of the other 15 inputs can be measured one at a time, while
applying no signal to IN00. Then, the crosstalk terms associated
with driving a parallel test signal into all 15 other inputs can be
measured two at a time in all possible combinations, then three at
a time, and so on, until finally, there is only one way to drive a test
signal into all 15 other inputs in parallel.
Rev. 0 | Page 18 of 20
Data Sheet
ADV3205
This crosstalk mechanism can be minimized by keeping the
Effect of Impedances on Crosstalk
mutual inductance low and increasing RL. The mutual inductance
can be kept low by increasing the spacing of the conductors and
minimizing their parallel lengths.
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input side
is capacitive coupling. The high impedance inputs do not have
significant current flow to create magnetically induced cross-
talk. However, significant current can flow through the input
termination resistors and the loops that drive them. Thus, the
PCB on the input side can contribute to magnetically coupled
crosstalk.
PCB Layout
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing, and
supply bypassing.
The packaging of the ADV3205 is designed to keep the crosstalk
to a minimum. Each input is separated from every other input
by an analog ground pin. Directly connect all AGND pins to the
ground plane of the circuit board. These ground pins provide
shielding, low impedance return paths, and physical separation
for the inputs. All of these help to reduce crosstalk.
From a circuit standpoint, the input crosstalk mechanism is
similar to a capacitor coupling to a resistive load. For low
frequencies, the magnitude of the crosstalk is given by
|XT| = 20log10[(RSCM) × s]
where:
RS is the source resistance.
CM is the mutual capacitance between the test signal circuit and
the selected circuit.
Each output is separated from its two neighboring outputs by an
analog supply pin of one polarity or the other. Each of these analog
supply pins provides power to the output stages of only the two
nearest outputs. These supply pins provide shielding, physical
separation, and a low impedance supply for the outputs. Individual
bypassing of each of these supply pins with a 0.1 μF chip capacitor
directly to the ground plane minimizes high frequency output
crosstalk via the mechanism of shared common impedances.
s is the Laplace transform variable.
From the previous equation, it can be observed that this crosstalk
mechanism has a high-pass nature; it can also be minimized by
reducing the coupling capacitance of the input circuits and
lowering the output impedance of the drivers. If the input is driven
from a 75 Ω terminated cable, the input crosstalk can be reduced
by buffering this signal with a low output impedance buffer.
Each output also has an on-chip compensation capacitor that is
individually tied to the nearby analog ground pins. This technique
reduces crosstalk by preventing the currents that flow in these paths
from sharing a common impedance on the IC and in the package
pins. Directly connect these AGND pins to the ground plane.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the ADV3205 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk is higher than the minimum obtainable due
to the high output currents. These currents induce crosstalk via
the mutual inductance of the output pins and bond wires of the
ADV3205.
There are separate digital (logic) and analog supplies. DVCC
must be at 5 V to be compatible with the 5 V CMOS and TTL
logic. AVCC and AVEE can range from 5 V to 12 V, depending
on the application.
Locally decouple each power supply pin (or group of adjacent
power supply pins) with a 0.1 μF capacitor. Use a 10 μF capacitor to
decouple power supplies as they come onto the board.
From a circuit standpoint, this output crosstalk mechanism is
similar to a transformer with a mutual inductance between the
windings that drives a load resistor. For low frequencies, the
magnitude of the crosstalk is given by
|XT| = 20log10(Mxy × s/RL)
where:
Mxy is the mutual inductance of Output X to Output Y.
RL is the load resistance on the measured output.
Rev. 0 | Page 19 of 20
ADV3205
Data Sheet
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
51
50
0.15
0.05
26
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BED
Figure 31. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ST-100-1
ADV3205JSTZ
ADV3205-EVALZ
0°C to 70°C
100-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10342-0-12/11(0)
Rev. 0 | Page 20 of 20
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