ADV7120KPZ30 [ADI]

CMOS 80 MHz, Triple 8-Bit Video DAC;


型号：	ADV7120KPZ30
厂家：	ADI
描述：	CMOS 80 MHz, Triple 8-Bit Video DAC 转换器
文件：	总13页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CMOS

80 MHz, Triple 8-Bit Video DAC

ADV7120

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

80 MHz Pipelined Operation

Triple 8-Bit D/ A Converters

RS-343A/ RS-170 Com patible Outputs

TTL Com patible Inputs

+5 V CMOS Monolithic Construction

40-Pin DIP or 44-Pin PLCC and 48-Lead TQFP

ADJUST

V_AA

V_REF

REFERENCE

AMPLIFIER

ADV7120

COMP

IOR

CLOCK

APPLICATIONS

RED

High Resolution Color Graphics

CAE/ CAD/ CAM Applications

Im age Processing

Instrum entation

Video Signal Reconstruction

Desktop Publishing

DAC

PIXEL

INPUT

PORT

GREEN

IOG

IOB

BLUE

Direct Digital Synthesis (DDS) and I/ Q Modulation

SPEED GRADES*

80 MHz

50 MHz

REF WHITE

BLANK

CONTROL

SYNC

CONTROL

I_SYNC

SYNC

30 MHz

GND

P RO D UCT H IGH LIGH TS

1. Fast video refresh rate, 80 MHz.

GENERAL D ESCRIP TIO N

T he ADV7120 (ADV ) is a digital to analog video converter on

a single monolithic chip. T he part is specifically designed for

high resolution color graphics and video systems. It is also ideal

for any high speed communications type applications requiring

low cost, high speed DACs. It consists of three, high speed,

8-bit, video D/A converters (RGB); a standard T T L input inter-

face and high impedance, analog output, current sources.

2. Compatible with a wide variety of high resolution color

graphics video systems.

3. Guaranteed monotonic with a maximum differential non-

linearity of ±0.5 LSB. Integral nonlinearity is guaranteed to

be a maximum of ±1 LSB.

T he ADV7120 has three separate, 8-bit, pixel input ports, one

each for red, green and blue video data. Additional video input

controls on the part include composite sync, blank and refer-

ence white. A single +5 V supply, an external 1.23 V reference

and pixel clock input are all that are required to make the part

operational.

T he ADV7120 is capable of generating RGB video output sig-

nals, which are compatible with RS-343A and RS-170 video

standards, without requiring external buffering.

T he ADV7120 is fabricated in a +5 V CMOS process. Its

monolithic CMOS construction ensures greater functionality

with low power dissipation. T he part is packaged in both a 0.6",

40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip car-

rier, PLCC. T he ADV7120 is also available in a very small 48-

lead T hin Quad Flatpack (T QFP).

ADV is a registered trademark of Analog Devices, Inc.

*Speed gr ades up to 140 MH z ar e also available upon special r equest.

P lease contact Analog D evices or its r epr esentatives for fur ther details.

REV. B

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

ADV7120* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

DESIGN RESOURCES

• ADV7120 Material Declaration

• PCN-PDN Information

DOCUMENTATION

Application Notes

• Quality And Reliability

• Symbols and Footprints

• AN-205: Video Formats and Required Load Terminations

DISCUSSIONS

View all ADV7120 EngineerZone Discussions.

• AN-213: Low Cost, Two-Chip, Voltage -Controlled

Amplifier and Video Switch

• AN-280: Mixed Signal Circuit Technologies

• AN-311: How to Reliably Protect CMOS Circuits Against

Power Supply Overvoltaging

SAMPLE AND BUY

Visit the product page to see pricing options.

• AN-342: Analog Signal-Handling for High Speed and

Accuracy

TECHNICAL SUPPORT

Submit a technical question or find your regional support

number.

Data Sheet

• ADV7120: CMOS 80 MHz, Triple 8-Bit Video DAC Data

Sheet

DOCUMENT FEEDBACK

Submit feedback for this data sheet.

REFERENCE MATERIALS

Solutions Bulletins & Brochures

• Digital to Analog Converters ICs Solutions Bulletin

This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not

trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

ADV7120–SPECIFICATIONS ⁽^I_S^V_YNC⁼co⁺n⁵ne^Vc^؎ted^5%to^;I^V0G. A⁼ll⁺Sp¹e^.2c³if⁵ic^Va^;t^Rion⁼s T³_M⁷_I^._N⁵t^⍀o T^{, C}¹⁼un¹l⁰es^ps^F;o^Rtherw⁼is⁵e⁶⁰no^⍀te^.d.)

REF

SET

MAX

P aram eter

All Versions Units

Test Conditions/Com m ents

ST AT IC PERFORMANCE

Resolution (Each DAC)

Accuracy (Each DAC)

Bits

Integral Nonlinearity, INL

Differential Nonlinearity, DNL

Gray Scale Error

±1

±0.5

±5

LSB max

Guaranteed Monotonic

% Gray Scale max Max Gray Scale Current: IOG = (V_REF* 12,082/R_SET) mA

IOR, IOB = (V_REF* 8,627/R_SET) mA

Coding

Binary

DIGIT AL INPUT S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

V min

V max

µA max

0.8

±1

V_IN= 0.4 V or 2.4 V

Input Capacitance, C_IN

pF max

ANALOG OUT PUT S

Gray Scale Current Range

mA min

mA max

Output Current

White Level Relative to Blank

17.69

20.40

16.74

18.50

0.95

1.90

6.29

9.5

69.1

–1

mA min

mA max

mA min

mA max

mA min

mA max

µA min

µA max

mA min

mA max

µA min

µA max

µA typ

T ypically 19.05 mA

T ypically 17.62 mA

T ypically 1.44 mA

T ypically 5 µA

White Level Relative to Black

Black Level Relative to Blank

Blank Level on IOR, IOB

Blank Level on IOG

T ypically 7.62 mA

T ypically 5 µA

Sync Level on IOG

LSB Size

DAC to DAC Matching

Output Compliance, V_OC

% max

V min

T ypically 2%

+1.4

100

V max

kΩ typ

pF max

Output Impedance, R_OUT

Output Capacitance, C_OUT

I_OUT= 0 mA

VOLT AGE REFERENCE

Voltage Reference Range, V_REF

Input Current, I_VREF

1.14/1.26

–5

V min/V max

mA typ

V_REF= 1.235 V for Specified Performance

POWER REQUIREMENT S

V_AA

I_AA

V nom

125

100

0.5

625

500

mA max

%/% max

mW max

T ypically 80 mA: 80 MHz Parts

T ypically 70 mA: 50 MHz & 35 MHz Parts

T ypically 0.12%/%: f = 1 kHz, COMP = 0.1 µF

T ypically 400 mW: 80 MHz Parts

Power Supply Rejection Ratio

Power Dissipation

T ypically 350 mW: 50 MHz & 30 MHz Parts

DYNAMIC PERFORMANCE

Glitch Impulse^{2, 3}

200

pV secs typ

ns max

DAC Noise^{2, 3, 4}

Analog Output Skew

T ypically 1 ns

NOT ES

¹T emperature range (T _MINto T _MIN); 0°C to +70°C.

²Sample tested at +25°C to ensure compliance.

³T T L input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and

outputs. See timing notes in Figure 1.

⁴T his includes effects due to clock and data feedthrough as well as RGB analog crosstalk.

Specifications subject to change without notice.

–2–

REV. B

ADV7120

(V = +5 V ؎ 5%; V = +1.235 V; R = 37.5 ⍀, C = 10 pF; R_SET= 560 ⍀.

REF

I_SYNCconnected to IOG. All Specifications T_MINto T ²unless otherwise noted.)

TIMING CHARACTERISTICS

MAX

P aram eter 80 MH z Version 50 MH z Version 30 MH z Version

Units

Conditions/Com m ents

f_MAX

t_l

t₂

t₃

t₄

12.5

33.3

MHz max

ns min

ns max

ns typ

Clock Rate

Data & Control Setup T ime

Data & Control Hold T ime

Clock Cycle T ime

Clock Pulse Width High T ime

Clock Pulse Width Low T ime

Analog Output Delay

t₅

t₆

t₇

t₈

ns max

ns typ

Analog Output Rise/Fall T ime

Analog Output T ransition T ime

NOT ES

¹T T L input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs

and outputs. See timing notes in Figure 1.

²T emperature range (T _MINto T _MAX): 0°C to +70°C

³Sample tested at +25°C to ensure compliance.

Specifications subject to change without notice.

CLOCK

DIGITAL INPUTS

(R0-R7, G0-G7, B0-B7;

DATA

SYNC, BLANK,

REF WHITE)

ANALOG OUTPUTS

(IOR, IOG, IOB, I

)

SYNC

NOTES

1. OUTPUT DELAY (

CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.

) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF

2. TRANSITION TIME ( ) MEASURED FROM THE 50% POINT OF FULL-SCALE

TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.

3. OUTPUT RISE/FALL TIME (

OF FULL TRANSITION.

t ) MEASURED BETWEEN THE 10% AND 90% POINTS

Figure 1. Video Input/Output Tim ing

REV. B

–3–

ADV7120

RECO MMEND ED O P ERATING CO ND ITIO NS

O RD ERING GUID E

P aram eter

Sym bol Min

Typ

Max

Units

Tem perature

Range¹

P ackage

O ption²

Model

Speed

Power Supply

V_AA

4.75

5.00

5.25

Volts

ADV7120KN80

ADV7120KN50

ADV7120KN30

ADV7120KP80

ADV7120KP50

ADV7120KP30

80 MHz

50 MHz

30 MHz

80 MHz

50 MHz

30 MHz

0°C to +70°C

N-40A

P-44A

ST -48

Ambient Operating

T emperature

Output Load

T _A

+70

°C

Ω

R_L

37.5

Reference Voltage

V_REF

1.14

1.235

1.26

Volts

ABSO LUTE MAXIMUM RATINGS¹

V_AAto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Voltage on Any Digital Pin . . . . . GND –0.5 V to V_AA+0.5 V

Ambient Operating T emperature (T_A) . . . . . . . . 0°C to +70°C

Storage T emperature (T_S) . . . . . . . . . . . . . . –65°C to +150°C

Junction T emperature (T_J) . . . . . . . . . . . . . . . . . . . . +150°C

Soldering T emperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C

IOR, IOB, IOG, I_SYNCto GND². . . . . . . . . . . . . . 0 V to V_AA

ADV7120KST 50 50 MHz

ADV7120KST 30 30 MHz

NOT ES

¹Industrial temperature range (–40°C to +85°C) version available to special

request. Please consult your local Analog Device representative.

²N = Plastic DIP; P = Plastic Leaded Chip Carrier.

NOT ES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Analog Output Short Circuit to any Power Supply or Common can be of an

indefinite duration.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADV7120 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

P IN CO NFIGURATIO NS

P LCC

TQFP

D IP

40 R3

39 R2

44 43 42 41 40

48 47 46 45

39 38 37

38 R1

44 43 42 40

37 R0

GND

FS ADJUST

36 FS ADJUST

35 V_REF

34 COMP

33 IOR

39 IOR

IOG

SYNC

IOR

IOG

32 IOG

31 I_SYNC

30 V_AA

29 IOB

28 GND

ADV7120

TOP VIEW

(Not to Scale)

ADV7120

TOP VIEW

(Not to Scale)

ADV7120

TOP VIEW

(Not to Scale)

G5 10

G6 11

IOB

33 IOB

32 GND

31 GND

30 GND

29 GND

G7 12

GND

CLOCK

BLANK 13

SYNC 14

V_AA15

B0 16

BLANK

SYNC

27 GND

26 GND

SYNC 11

25 CLOCK

B1 17

24 REF WHITE

23 B7

18 19 20 21 22 23 24

13 14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

B2 18

22 B6

NC = NO CONNECT

B4 20

21 B5

NOT E

For the ADV7120 in T QFP package: T he REF WHIT E pin is not available.

T he I_SYNCpin is not available and is internally connected to the IOG pin.

–4–

REV. B

ADV7120

P IN FUNCTIO N D ESCRIP TIO N

P in

Mnem onic

Function

BLANK

Composite blank control input (T T L compatible). A logic zero on this control input drives the analog out-

puts, IOR, IOB and IOG, to the blanking level. T he BLANK signal is latched on the rising edge of CLOCK.

While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHIT E pixel and control inputs are

ignored.

SYNC

Composite sync control input (T T L compatible). A logical zero on the SYNC input switches off a 40 IRE

current source on the I_SYNCoutput. SYNC does not override any other control or data input; therefore, it

should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.

CLOCK

Clock input (T T L compatible). T he rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,

BLANK and REF WHIT E pixel and control inputs. It is typically the pixel clock rate of the video system.

CLOCK should be driven by a dedicated T T L buffer.

REF WHIT E

Reference white control input (T T L compatible). A logical one on this input forces the IOR, IOG and IOB

outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHIT E is

latched on the rising edge of clock.

R0–R7,

G0–G7,

B0–B7

Red, green and blue pixel data inputs (T T L compatible). Pixel data is latched on the rising edge of CLOCK.

R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the

regular PCB power or ground plane.

IOR, IOG, IOB

Red, green, and blue current outputs. T hese high impedance current sources are capable of directly driving

a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether

or not they are all being used.

I_SYNC

Sync current output. T his high impedance current source can be directly connected to the IOG output. T his

allows sync information to be encoded onto the green channel. I_SYNCdoes not output any current while

SYNC is at logical zero. T he amount of current output at I_SYNCwhile SYNC is at logical one is given by:

I_SYNC(mA) = 3,455 × V_REF(V)/ R_SET(Ω)

If sync information is not required on the green channel, I_SYNCshould be connected to AGND.

FS ADJUST

Full-scale adjust control. A resistor (R_SET) connected between this pin and GND, controls the magnitude of

the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output

current.

T he relationship between R_SETand the full-scale output current on IOG (assuming I_SYNCis connected to

IOG) is given by:

R_SET(Ω) = 12,082 × V_REF(V)/IOG (mA)

T he relationship between R_SETand the full-scale output current on IOR and IOB is given by:

IOR, IOB (mA) = 8,628 × V_REF(V)/ R_SET(Ω)

COMP

V_REF

Compensation pin. T his is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capaci-

tor must be connected between COMP and V_AA

Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. T he use of an ex-

ternal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be con-

nected between V_REFand V_AA

V_AA

Analog power supply (5 V ± 5%). All V_AApins on the ADV7120 must be connected.

GND

Ground. All GND pins must be connected.

REV. B

–5–

ADV7120

TERMINO LO GY

Raster Scan

Blanking Level

T he most basic method of sweeping a CRT one line at a time to

generate and display images.

T he level separating the SYNC portion from the video portion

of the waveform. Usually referred to as the front porch or back

porch. At 0 IRE units, it is the level which will shut off the pic-

ture tube, resulting in the blackest possible picture.

Refer ence Black Level

T he maximum negative polarity amplitude of the video signal.

Refer ence White Level

T he maximum positive polarity amplitude of the video signal.

Color Video (RGB)

T his usually refers to the technique of combining the three pri-

mary colors of red, green and blue to produce color pictures

within the usual spectrum. In RGB monitors, three DACs are

required, one for each color.

Sync Level

T he peak level of the SYNC signal.

Video Signal

T hat portion of the composite video signal which varies in gray

scale levels between reference white and reference black. Also

referred to as the picture signal, this is the portion which may be

visually observed.

Sync Signal (SYNC)

T he position of the composite video signal which synchronizes

the scanning process.

Gr ay Scale

T he discrete levels of video signal between reference black and

reference white levels. An 8-bit DAC contains 256 different lev-

els while a 6-bit DAC contains 64.

T he REF WHIT E control input drives the RGB video outputs

to the white level. T his function could be used to overlay a cur-

sor or crosshair onto the RGB video output.

CIRCUIT D ESCRIP TIO N AND O P ERATIO N

T he ADV7120 contains three 8-bit D/A converters, with three

input channels each containing an 8-bit register. Also inte-

grated on board the part is a reference amplifier and CRT con-

trol functions BLANK, SYNC and REF WHIT E.

T able I details the resultant effect on the analog outputs of

BLANK, SYNC and REF WHIT E.

D igital Inputs

All these digital inputs are specified to accept T T L logic levels.

24-bits of pixel data (color information) R0–R7, G0–G7 and

B0–B7 are latched into the device on the rising edge of each

clock cycle. T his data is presented to the three 8-bit DACs and

is then converted to three analog (RGB) output waveforms.

(See Figure 2.)

Clock Input

T he CLOCK input of the ADV7120 is typically the pixel clock

rate of the system. It is also known as the dot rate. T he dot rate,

and hence the required CLOCK frequency, will be determined

by the on-screen resolution, according to the following

equation:

T hree other digital control signals are latched to the analog

video outputs in a similar fashion. BLANK, SYNC and REF

WHIT E are each latched on the rising edge of CLOCK to

maintain synchronization with the pixel data stream.

Dot Rate = (Horiz: Res) × (Vert Res) × (Refresh Rate)/

(Retrace Factor)

Horiz Res

Vert Res

Number of pixels/line

Number of lines/frame

T he BLANK and SYNC functions allow for the encoding of

these video synchronization signals onto the RGB video output.

T his is done by adding appropriately weighted current sources

to the analog outputs, as determined by the logic levels on the

BLANK and SYNC digital inputs. Figure 3 shows the analog

output, RGB video waveform of the ADV7120. T he influence

of SYNC and BLANK on the analog video waveform is

illustrated.

Refresh Rate

Horizontal scan rate. T his is the rate at

which the screen must be refreshed, typi-

cally 60 Hz for a noninterlaced system or

30 Hz for an interlaced system.

Retrace Factor

T otal blank time factor. T his takes into ac-

count that the display is blanked for a cer-

tain fraction of the total duration of each

frame (e.g., 0.8).

CLOCK

DIGITAL INPUTS

(R0-R7, G0-G7, B0-B7;

DATA

SYNC, BLANK,

REF WHITE)

ANALOG OUTPUTS

(IOR, IOG, IOB, I

)

SYNC

Figure 2. Video Data Input/Output

–6–

REV. B

ADV7120

If we, therefore, have a graphics system with a 1024 × 1024

resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-

tor of 0.8, then:

T he required CLOCK frequency is thus 78.6 MHz.

All video data and control inputs are latched into the ADV7120

on the rising edge of CLOCK, as previously described in the

“Digital Inputs” section. It is recommended that the CLOCK

input to the ADV7120 be driven by a T T L buffer (e.g.,

74F244).

Dot Rate = 1024 × 1024 × 60/0.8

= 78.6 MHz

RED, BLUE

GREEN

WHITE LEVEL

19.05 0.714 26.67 1.000

92.5 IRE

BLACK LEVEL

BLANK LEVEL

1.44 0.054

9.05 0.340

7.62 0.286

7.5 IRE

40 IRE

SYNC LEVEL

NOTES

1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.

2. V = 1.235V, R = 560Ω, I CONNECTED TO IOG.

REF

SET

SYNC

3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.

Figure 3. RGB Video Output Waveform

Table I. Video O utput Truth Table

IO G

IO R, IO B

(m A)

REF

WH ITE SYNC

D AC

D escription

(m A)^l

BLANK Input D ata

WHIT E LEVEL

VIDEO

VIDEO to BLANK

BLACK LEVEL

BLACK to BLANK

BLANK LEVEL

SYNC LEVEL

26.67

video + 9.05

video + 1.44

9.05

1.44

7.62

19.05

video + 1.44

1.44

xxH

FFH

data

00H

xxH

NOT E

T ypical with full-scale IOG = 26.67 mA.

V_REF= 1.235 V, R_SET= 560 Ω, I_SYNCconnected to IOG.

Refer ence Input

Video Synchr onization and Contr ol

An external 1.23 V voltage reference is required to drive

the ADV7120. T he AD589 from Analog Devices is an

ideal choice of reference. It is a two-terminal, low cost,

temperature compensated bandgap voltage reference which

provides a fixed 1.23 V output voltage for input currents

between 50 µA and 5 mA. Figure 4 shows a typical refer-

ence circuit connection diagram. T he voltage reference gets

its current drive from the ADV7120’s V_AAthrough an on-

board 1 kΩ resistor to the V_REFpin. A 0.1 µF ceramic ca-

T he ADV7120 has a single composite video sync (SYNC) input

control. Many graphics processors and CRT controllers have

the ability of generating horizontal sync (HSYNC), vertical sync

(VSYNC) and composite SYNC.

In a graphics system which does not automatically generate a

composite SYNC signal, the inclusion of some additional logic

circuitry will enable the generation of a composite SYNC signal.

T he I_SYNCcurrent output is typically connected directly to the

IOG output, thus encoding video synchronization information

onto the green video channel. If it is not required to encode sync

information onto the ADV7120’s analog outputs, the SYNC in-

put should be tied to logic low and the I_SYNCshould be con-

nected to analog ground.

pacitor is required between the COMP pin and V_AA

T his is necessary so as to provide compensation for the

internal reference amplifier.

REV. B

–7–

ADV7120

A resistance R_SETconnected between FS ADJUST and GND

determines the amplitude of the output video level according to

the following equations:

as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the

required configuration for each of the three RGB outputs con-

nected into a doubly terminated 75 Ω load. T his arrangement

will develop RS-343A video output voltage levels across a 75 Ω

monitor.

IOG (mA) = 12,082 × V_REF(V)/R_SET(Ω)

(1)

(2)

IOR, IOB (mA) = 8,628 × V_REF(V)/R_SET(Ω)

IOR, IOG, IOB

= 75Ω

If SYNC is not being encoded onto the green channel, then

Equation 1 will be similar to Equation 2.

DACs

Using a variable value of R_SET, as shown in Figure 4, allows for

accurate adjustment of the analog output video levels. Use of a

fixed 560 Ω R_SETresistor yields the analog output levels as

quoted in the specification page. T hese values also correspond

to the RS-343A video waveform values as shown in Figure 3.

(CABLE)

= 75Ω

Z = 75Ω

(MONITOR)

(SOURCE

TERMINATION)

ANALOG POWER PLANE

TERMINATION REPEATED THREE TIMES

FOR RED, GREEN AND BLUE DACs

0.1µF

COMP

Figure 5a. Analog Output Term ination for RS-343A

One suggested method of driving RS-170 video levels into a 75 Ω

monitor is shown in Figure 5b. T he output current levels of the

DACs remain unchanged but the source termination resistance,

Z_S, on each of the three DACs is increased from 75 Ω to 150 Ω.

≈ 4mA

1kΩ

REF

TO DACs

FS ADJUST

AD589

(1.235V

IOR, IOG, IOB

= 75Ω

500Ω

100Ω

VOLTAGE

REFERENCE)

560Ω

DACs

SET

(CABLE)

= 75Ω

GND

= 150Ω

(MONITOR)

ADV7120*

(SOURCE

TERMINATION)

*ADDITIONAL CIRCUITRY, INCLUDING

DECOUPLING COMPONENTS,

EXCLUDED FOR CLARITY

TERMINATION REPEATED THREE TIMES

FOR RED, GREEN AND BLUE DACs

Figure 4. Reference Circuit

Figure 5b. Analog Output Term ination for RS-170

More detailed information regarding load terminations for vari-

ous output configurations, including RS-343A and RS-170, is

available in an application note entitled “Video Formats & Re-

quired Load T erminations” available from Analog Devices,

publication number E1228-15-1/89.

D /A Conver ter s

T he ADV7120 contains three matched 8-bit D/A converters.

T he DACs are designed using an advanced, high speed, seg-

mented architecture. T he bit currents corresponding to each

digital input are routed to either the analog output (bit = “1”)

or GND (bit = “0”) by a sophisticated decoding scheme. As all

this circuitry is on one monolithic device, matching between the

three DACs is optimized. As well as matching, the use of identi-

cal current sources in a monolithic design guarantees monoto-

nicity and low glitch. T he onboard operational amplifier

stabilizes the full-scale output current against temperature and

power supply variations.

Figure 3 shows the video waveforms associated with the three

RGB outputs driving the doubly terminated 75 Ω load of Figure

5a. As well as the gray scale levels, black level to white level, the

diagram also shows the contributions of SYNC and BLANK.

T hese control inputs add appropriately weighted currents to the

analog outputs, producing the specific output level requirements

for video applications. T able I details how the SYNC and

BLANK inputs modify the output levels.

Analog O utputs

The ADV7120 has three analog outputs, corresponding to the red,

green and blue video signals. A fourth analog output (I_SYNC) can be

used if it is required to encode video synchronization information

onto the green signal. In this case, I_SYNCis connected to IOG .

(See “Video Synchronization and Control” section.)

Gr ay Scale O per ation

T he ADV7120 can be used for stand-alone, gray scale (mono-

chrome) or composite video applications (i.e., only one channel

used for video information). Any one of the three channels, red,

green or blue, can be used to input the digital video data. T he

two unused video data channels should be tied to logical zero.

T he red, green and blue analog outputs of the ADV7102 are

high impedance current sources. Each one of these three RGB

current outputs is capable of directly driving a 37.5 Ω load, such

–8–

REV. B

ADV7120

T he unused analog outputs should be terminated with the same

load as that for the used channel. In other words, if the red

channel is used and IOR is terminated with a doubly terminated

75 Ω load (37.5 Ω), IOB and IOG should be terminated with

37.5 Ω resistors. (See Figure 6.)

Video O utput Buffer s

T he ADV7120 is specified to drive transmission line loads,

which is what most monitors are rated as. T he analog output

configurations to drive such loads are described in the Analog

Interface section and illustrated in Figure 5. However, in some

applications it may be required to drive long “transmission line”

cable lengths. Cable lengths greater than 10 meters can attenu-

ate and distort high frequency analog output pulses. T he inclu-

sion of output buffers will compensate for some cable distortion.

Buffers with large full power bandwidths and gains between 2

and 4 will be required.

DOUBLY

IOR

IOG

TERMINATED

75Ω LOAD

VIDEO

INPUT

37.5Ω

T hese buffers will also need to be able to supply sufficient cur-

rent over the complete output voltage swing. Analog Devices

produces a range of suitable op amps for such applications.

T hese include the AD84X series of monolithic op amps. In very

high frequency applications (80 MHz), the AD9617 is recom-

mended. More information on line driver buffering circuits is

given in the relevant op amp data sheets.

IOB

ADV7120

Use of buffer amplifiers also allows implementation of other

video standards besides RS-343A and RS-170. Altering the gain

components of the buffer circuit will result in any desired

video level.

GND

Figure 6. Input and Output Connections for Stand-Alone

Gray Scale or Com posite Video

0.1µF

= 75Ω

75Ω

IOR, IOG, IOB

DACs

AD848

(CABLE)

0.1µF

= 75Ω

(MONITOR)

= 75Ω

(SOURCE

TERMINATION)

–V

GAIN (G) = 1 +

Figure 7. AD848 As an Output Buffer

REV. B

–9–

ADV7120

P C BO ARD LAYO UT CO NSID ERATIO NS

Gr ound P lanes

T he ADV7120 is optimally designed for lowest noise perfor-

mance, both radiated and conducted noise. T o complement the

excellent noise performance of the ADV7120, it is imperative

that great care be given to the PC board layout. Figure 8 shows

a recommended connection diagram for the ADV7120.

T he ADV7120 and associated analog circuitry, should have a

separate ground plane referred to as the analog ground plane.

T his ground plane should connect to the regular PCB ground

plane at a single point through a ferrite bead, as illustrated in

Figure 8. T his bead should be located as close as possible

(within 3 inches) to the ADV7120.

T he layout should be optimized for lowest noise on the

ADV7120 power and ground lines. T his can be achieved by

shielding the digital inputs and providing good decoupling. T he

lead length between groups of V_AAand GND pins should by

minimized so as to minimize inductive ringing.

T he analog ground plane should encompass all ADV7120

ground pins, voltage reference circuitry, power supply bypass

circuitry, the analog output traces and any output amplifiers.

T he regular PCB ground plane area should encompass all the

digital signal traces, excluding the ground pins, leading up to

the ADV7120.

COMP

0.1µF

ANALOG POWER PLANE

VIDEO

DATA

INPUTS

L1 (FERRITE BEAD)

0.1µF

+5V (V )

10µF

33µF

REF

Z1 (AD589)

ADV7120

ANALOG GROUND PLANE

GROUND

GND

L2 (FERRITE BEAD)

560Ω

75Ω

SET

FS ADJUST

IOR

CLOCK

REF WHITE

VIDEO

RGB

VIDEO

OUTPUT

CONTROL

INPUTS

IOG

SYNC

IOB

BLANK

COMPONENT

DESCRIPTION

VENDOR PART NUMBER

33µF TANTALUM CAPACITOR

10µF TANTALUM CAPACITOR

0.1µF CERAMIC CAPACITOR

FERRITE BEAD

C3, C4, C5, C6

L1, L2

FAIR-RITE 274300111 OR MURATA BL01/02/03

DALE CMF-55C

R1, R2, R3

75Ω 1% METAL FILM RESISTOR

560Ω 1% METAL FILM RESISTOR

1.235V VOLTAGE REFERENCE

Rset

SET

DALE CMF-55C

ANALOG DEVICES AD589JH

Figure 8. ADV7120 Typical Connection Diagram and Com ponent List

–10–

REV. B

ADV7120

P ower P lanes

the main PCB. Alternatively, consideration could be given to

using a three terminal voltage regulator.

T he PC board layout should have two distinct power planes,

one for analog circuitry and one for digital circuitry. T he analog

power plane should encompass the ADV7120 (V_AA) and all as-

sociated analog circuitry. T his power plane should be connected

to the regular PCB power plane (V_CC) at a single point through

a ferrite bead, as illustrated in Figure 8. T his bead should be lo-

cated within three inches of the ADV7120.

D igital Signal Inter connect

T he digital signal lines to the ADV7120 should be isolated as

much as possible from the analog outputs and other analog cir-

cuitry. Digital signal lines should not overlay the analog power

plane.

Due to the high clock rates used, long clock lines to the

ADV7120 should be avoided so as to minimize noise pickup.

T he PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7120 power pins, voltage reference circuitry

and any output amplifiers.

Any active pull-up termination resistors for the digital inputs

should be connected to the regular PCB power plane (V_CC), and

not the analog power plane.

T he PCB power and ground planes should not overlay portions

of the analog power plane. Keeping the PCB power and ground

planes from overlaying the analog power plane will contribute to

a reduction in plane-to-plane noise coupling.

Analog Signal Inter connect

T he ADV7120 should be located as close as possible to the out-

put connectors thus minimizing noise pickup and reflections

due to impedance mismatch.

Supply D ecoupling

Noise on the analog power plane can be further reduced by the

use of multiple decoupling capacitors. (See Figure 8.)

T he video output signals should overlay the ground plane, and

not the analog power plane, thereby maximizing the high fre-

quency power supply rejection.

Optimum performance is achieved by the use of 0.1 µF ceramic

capacitors. Each of the two groups of V_AAshould be individually

decoupled to ground. T his should be done by placing the ca-

pacitors as close as possible to the device with the capacitor

leads as short as possible, thus minimizing lead inductance.

For optimum performance, the analog outputs should each have

a source termination resistance to ground of 75 Ω (doubly ter-

minated 75 Ω configuration). T his termination resistance should

be as close as possible to the ADV7120 so as to minimize

reflections.

It is important to note that while the ADV7120 contains cir-

cuitry to reject power supply noise, this rejection decreases with

frequency. If a high frequency switching power supply is used,

the designer should pay close attention to reducing power sup-

ply noise. A dc power supply filter (Murata BNX002) will pro-

vide EMI suppression between the switching power supply and

Additional information on PCB design is available in an applica-

tion note entitled “Design and Layout of a Video Graphics Sys-

tem for Reduced EMI.” T his application note is available from

Analog Devices, publication number E1309-15-10/89.

REV. B

–11–

ADV7120

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

44-Ter m inal P lastic Leaded Chip Car r ier

(P -44A)

0.045 TYP

0.045

TYP

0.050 ± 0.005

(1.27 ± 0.13)

PIN 1

IDENTIFIER

0.045

TYP

0.630 (16.00)

0.590 (14.99)

0.021 (0.533)

0.013 (0.331)

TOP VIEW

(PINS DOWN)

0.032 (0.812)

0.026 (0.661)

0.020 MIN

0.656 (16.662)

0.650 (16.510)

0.120 (3.04)

0.090 (2.29)

0.180 (4.57)

0.165 (4.20)

0.695 (17.65)

0.685 (17.40)

R.020 MAX

3 PLCS

40-P in P lastic D IP

(N-40A)

0.545 (13.843)

0.535 (13.589)

0.155 (3.937)

0.145 (3.683)

0.630 (16.0)

0.590 (15.0)

2.090 (53.0)

2.008 (51.0)

0.17

(4.32)

MAX

0.012 (0.305)

0.008 (0.203)

0.021 (0.533)

0.015 (0.381)

0.052 (1.32)

0.048 (1.219)

0.105 (2.67)

0.095 (2.42)

0°

0.175 (4.45)

0.125 (3.18)

LEAD NO. 1 IDENTIFIED BY DOT, NOTCH OR "1."

LEADS ARE SOLDER PLATED KOVAR OR ALLOY 42.

48-Lead TQ FP

(ST-48)

0.354 ± 0.008

(9.00 ± 0.2)

0.059 +0.008 –0.004

(1.50 +0.2 –0.1)

0.276 ± 0.004

(7.0 ± 0.1)

0.055 ± 0.002

(1.40 ± 0.05)

0.02 ± 0.008

(0.5 ± 0.02)

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.004 ± 0.002

(0.1 ± 0.05)

0° MIN

(3.5° ± 3.5°)

0.02 ± 0.003 0.007 ± 0.003 –0.001

(0.50 ± 0.08) (0.18 ± 0.08 –0.03)

0.005 +0.002 –0.0008

(0.127 +0.05 –0.02)

–12–

REV. B

ADV7120KPZ30 [ADI]

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