ADV7122KST30 [ADI]
CMOS 80 MHz, Triple 10-Bit Video DACs; CMOS 80兆赫，三路10位视频DAC
| 型号： | ADV7122KST30 |
| 厂家： | 
ADI |
| 描述： | CMOS 80 MHz, Triple 10-Bit Video DACs |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS
a
80 MHz, Triple 10-Bit Video DACs
ADV7121/ADV7122
AD V7121 FUNCTIO NAL BLO CK D IAGRAM
FEATURES
80 MHz Pipelined Operation
Triple 10-Bit D/ A Converters
RS-343A/ RS-170 Com patible Outputs
TTL Com patible Inputs
FS
ADJUST
VAA
VREF
REFERENCE
AMPLIFIER
ADV7121
+5 V CMOS Monolithic Construction
40-Pin DIP Package (ADV7121)
44-Pin PLCC Package (ADV7122)
48-Lead TQFP (ADV7122)
COMP
IOR
CLOCK
RED
REGISTER
10
10
10
R0
R9
DAC
DAC
DAC
10
10
10
APPLICATIONS
PIXEL
INPUT
PORT
GREEN
REGISTER
High Definition Television (HDTV)
High Resolution Color Graphics
CAE/ CAD/ CAM Applications
Im age Processing
G0
G9
IOG
IOB
BLUE
REGISTER
B0
B9
Instrum entation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)
I/ Q Modulation
GND
AD V7122 FUNCTIO NAL BLO CK D IAGRAM
SPEED GRADES
80 MHz
FS
ADJUST
V
V
REF
AA
50 MHz
30 MHz
REFERENCE
AMPLIFIER
ADV7122
COMP
IOR
CLOCK
GENERAL D ESCRIP TIO N
T he ADV7121/ADV7122 (ADV®) is a video speed, digital-to-
analog converter on a single monolithic chip. T he part is specifi-
cally designed for high resolution color graphics and video
systems including high definition television (HDT V). It is also
ideal for any application requiring a low cost, high speed DAC
function especially in communications. It consists of three, high
speed, 10-bit, video D/A converters (RGB), a standard TTL input
interface and high impedance, analog output, current sources.
RED
REGISTER
10
10
10
R0
R9
DAC
DAC
DAC
10
10
10
PIXEL
INPUT
PORT
GREEN
REGISTER
G0
G9
IOG
IOB
BLUE
REGISTER
B0
B9
T he ADV7121/ADV7122 has three separate, 10-bit, pixel input
ports, one each for red, green and blue video data. A single +5 V
power supply, an external 1.23 V reference and pixel clock input is
all that is required to make the part operational. T he ADV7122
has additional video control signals, composite SYNC and BLANK.
SYNC
CONTROL
CONTROL
REGISTER
BLANK
SYNC
T he ADV7121/ADV7122 is capable of generating RGB video
output signals which are compatible with RS-343A, RS-170 and
most proposed production system HDT V video standards, in-
cluding SMPT E 240M.
GND
aged in a 44-pin plastic leaded (J-lead) chip carrier, PLCC,
and 48-lead thin quad flatpack (T QFP).
T he ADV7121/ADV7122 is fabricated in a +5 V CMOS pro-
cess. Its monolithic CMOS construction ensures greater func-
tionality with low power dissipation. T he ADV7121 is packaged
in a 0.6", 40-pin plastic DIP package. T he ADV7122 is pack-
P RO D UCT H IGH LIGH TS
1. Fast video refresh rate, 80 MHz.
2. Guaranteed monotonic to 10 bits. T en bits of resolution al-
lows for implementation of linearization functions such as
gamma correction and contrast enhancement.
ADV is a registered trademark of Analog Devices, Inc.
*Speed grades up to 140 MHz are also available on special request.
Please contact Analog Devices or its representatives for details.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A/RS-170 and the pro-
posed SMPT E 240M standard for HDT V.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +5 V ؎ 5%; V = +1.235 V; R = 3.75 ⍀, C = 10 pF; RSET = 560 ⍀. All
AA
REF
L
L
MIN to T 1 unless otherwise noted.)
ADV7121–SPECIFICATIONS Specifications T
MAX
P aram eter
K Version
Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
10
Bits
Integral Nonlinearity, INL
Differential Nonlinearity, DNL ±1
±2
LSB max
LSB max
Guaranteed Monotonic
Gray Scale Error
Coding
±5
% Gray Scale max
Binary
Max Gray Scale Current = (VREF * 7,969/RSET) mA
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
V min
0.8
±1
10
V max
µA max
pF max
VIN = 0.4 V or 2.4 V
2
Input Capacitance, CIN
ANALOG OUT PUT S
Gray Scale Current Range
15
22
mA min
mA max
Output Current
White Level
16.74
18.50
0
50
17.28
5
mA min
mA max
µA min
µA max
µA typ
T ypically 17.62 mA
Black Level
T ypically 5 µA
LSB Size
DAC to DAC Matching
Output Compliance, VOC
% max
V min
T ypically 2%
–1
+1.4
100
30
V max
kΩ typ
pF max
2
Output Impedance, ROUT
2
Output Capacitance, COUT
IOUT = 0 mA
VOLT AGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
1.14/1.26
–5
V min/V max
mA typ
VREF = 1.235 V for Specified Performance
POWER REQUIREMENT S
VAA
IAA
5
V nom
125
100
0.5
625
500
mA max
mA max
%/% max
mW max
mW max
T ypically 80 mA: 80 MHz Parts
T ypically 70 mA: 50 MHz & 35 MHz Parts
T ypically 0.12 %/%: f = 1 kHz, COMP = 0.1 µF
T ypically 400 mW: 80 MHz Parts
Power Supply Rejection Ratio2
Power Dissipation
T ypically 350 mW: 50 MHz & 35 MHz Parts
DYNAMIC PERFORMANCE
Glitch Impulse2, 3
50
200
2
pV secs typ
pV secs typ
ns max
DAC Noise2, 3, 4
Analog Output Skew
T ypically 1 ns
NOT ES
1T emperature range (T MIN to T MAX): 0°C to +70°C.
2Sample tested at +25°C to ensure compliance.
3T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4T his includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.
–2–
REV. B
ADV7121/ADV7122
ADV7122–SPECIFICATIONS(V = +5 V ؎ 5%; V = +1.235 V; R = 37.5 ⍀, C = 10 pF; R = 560 ⍀. All
Specifications TMIN to T 1 unless otherwise noted.)
AA
REF
L
L
SET
MAX
P aram eter
K Version Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
10
Bits
Integral Nonlinearity, INL
Differential Nonlinearity, DNL ±1
±2
LSB max
LSB max
Guaranteed Monotonic
Gray Scale Error
Coding
±5
% Gray Scale max Max Gray Scale Current: IOG = (VREF*12.082/RSET) mA
Max Gray Scale Current: IOR, IOB = (VREF*8,627/RSET) mA
Binary
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
V min
V max
µA max
0.8
±1
10
VIN = 0.4 V or 2.4 V
2
Input Capacitance, CIN
pF max
ANALOG OUT PUT S
Gray Scale Current Range
15
22
mA min
mA max
Output Current
White Level Relative to Blank
17.69
20.40
16.74
18.50
0 95
1.90
0
50
6.29
9.5
0
50
17.28
5
–1
mA min
mA max
mA min
mA max
mA min
mA max
µA min
µA max
mA min
mA max
µA min
µA max
µA typ
T ypically 19.05 mA
T ypically 17.62 mA
T ypically 1.44 mA
T ypically 5 µA
White Level Relative to Black
Black Level Relative to Blank
Black Level on IOR, IOB
Black Level on IOG
T ypically 7.62 mA
T ypically 5 µA
Sync Level on IOG
LSB Size
DAC to DAC Matching
Output Compliance, VOC
% max
V min
T ypically 2%
+1.4
100
30
V max
kΩ typ
pF max
2
Output Impedance, ROUT
2
Output Capacitance, COUT
IOUT = 0 mA
VOLT AGE REFERENCE
Voltage Reference Range, VREF
Input Current, IVREF
1.14/1.26
–5
V min/V max
mA typ
VREF = 1.235 V for Specified Performance
POWER REQUIREMENT S
VAA
IAA
5
V nom
125
100
0.5
625
500
mA max
mA max
%/% max
mW max
mW max
T ypically 80 mA: 80 MHz Parts
T ypically 70 mA: 50 MHz & 35 MHz Parts
T ypically 0.12%/%: f = 1 kHz, COMP = 0.01 µF
T ypically 400 mW: 80 MHz Parts
Power Supply Rejection Ratio2
Power Dissipation
T ypically 350 mW: 50 MHz & 35 MHz Parts
DYNAMIC PERFORMANCE
Glitch Impulse2, 3
50
200
2
pV secs typ
pV secs typ
ns max
DAC Noise2, 3, 4
Analog Output Skew
T ypically 1 ns
NOT ES
1T emperature range (T MIN to T MAX) 0°C to +70°C.
2Sample tested at +25°C to ensure compliance.
3T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4T his includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice
REV. B
–3–
ADV7121/ADV7122
TIMING CHARACTERISTICS
(V = +5 V ؎ 5%; V = +1.235 V; R = 37.5 ⍀, C = 10 pF; RSET = 560 ⍀.
All Specifications TMIN to TMAX unless otherwise noted.)
AA
REF
L
L
1
2
P aram eter
80 MH z Version
50 MH z Version
30 MH z Version
Units
Conditions/Com m ents
fmax
t1
t2
t3
t4
80
3
2
12.5
4
4
30
20
3
50
6
2
20
7
7
30
20
3
30
8
2
33.3
9
9
30
20
3
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
Clock Rate
Data & Control Setup T ime
Data & Control Hold T ime
Clock Cycle T ime
Clock Pulse Width High T ime
Clock Pulse Width Low T ime
Analog Output Delay
t5
t6
t73
t8
ns max
ns typ
Analog Output Rise/Fall T ime
Analog Output T ransition T ime
12
15
15
NOT ES
1T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
2T emperature range (T MIN to T MAX): 0°C to +70°C.
3Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
t
3
t
4
t
5
CLOCK
t
t
1
2
DIGITAL INPUTS
(R0–R9, G0–G9, B0–B9;
SYNC, BLANK)
DATA
t
8
t
6
ANALOG OUTPUTS
(IOR, IOG, IOB)
t
7
NOTES
1. OUTPUT DELAY (t ) MEASURED FROM THE 50% POINT OF THE
6
RISING EDGE OF THE CLOCK TO THE 50% POINT OF
FULL-SCALE TRANSITION.
2. TRANSITION TIME (t ) MEASURED FROM THE 50% POINT OF
8
FULL-SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT
VALUE.
3. OUTPUT RISE/FALL TIME (t ) MEASURED BETWEEN THE 10%
7
AND 90% POINTS OF FULL-SCALE TRANSITION.
Figure 1. Video Input/Output Tim ing
RECO MMEND ED O P ERATING CO ND ITIO NS
P aram eter
Sym bol
Min
Typ
Max
Units
Power Supply
VAA
4.75
5.00
5.25
Volts
Ambient Operating
T emperature
TA
0
+70
°C
Output Load
RL
37.5
Ω
Reference Voltage
VREF
1.14
1.235
1.26
Volts
REV. B
–4–
ADV7121/ADV7122
ABSO LUTE MAXIMUM RATINGS1
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Analog output short circuit to any power supply or common can be of an indefinite
duration.
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . . GND –0.5 V to VAA + 0.5 V
Ambient Operating T emperature (T A) . . . . . . . . 0°C to +70°C
Storage T emperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Soldering T emperature (5 secs) . . . . . . . . . . . . . . . . . . . 220°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C
IOR, IOB, IOG to GND2 . . . . . . . . . . . . . . . . . . . 0 V to VAA
P IN CO NFIGURATIO NS
D IP (N-40A) P ackage
P LCC (P -44A) P ackage
1
2
40
39
38
37
36
35
R6
R7
R8
R9
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
R5
R4
R3
R2
R1
R0
6
5
4
3
2
1
44 43 42 41 40
3
G1
G2
G3
7
8
9
39
38
FS ADJUST
4
V
5
REF
6
37 COMP
7
34 FS ADJUST
G4 10
G5 11
G6 12
G7 13
G8 14
36
35
34
33
32
31
30
29
IOR
IOG
V
8
33
32
ADV7121 DIP
REF
ADV7122 PLCC
COMP
9
TOP VIEW
(Not to Scale)
V
AA
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
31 IOR
V
AA
30
29
28
27
26
25
IOG
IOB
V
AA
15
16
17
G9
BLANK
SYNC
IOB
GND
GND
CLOCK
B9
GND
V
AA
CLOCK
B0
24 B8
23 B7
22 B6
B1
B2
B3
B4
18 19 20 21 22 23 24 25 26 27 28
21
B5
O RD ERING GUID E
Tem perature
Range*
P ackage
D escription
P ackage
O ption
Model
Speed
ADV7121KN80 80 MHz 0°C to +70°C
ADV7121KN50 50 MHz 0°C to +70°C
ADV7121KN30 30 MHz 0°C to +70°C
40-Pin Plastic DIP
40-Pin Plastic DIP
40-Pin Plastic DIP
N-40A
N-40A
N-40A
ADV7122KP80 80 MHz 0°C to +70°C
ADV7122KP50 50 MHz 0°C to +70°C
ADV7122KP30 30 MHz 0°C to +70°C
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
44-Lead Plastic Leaded Chip Carrier (PLCC) P-44A
ADV7122KST 50 50 MHz 0°C to +70°C
ADV7122KST 30 30 MHz 0°C to +70°C
48-Lead T hin Quad Flatpack (T QFP)
48-Lead T hin Quad Flatpack (T QFP)
ST -48
ST -48
*Industrial T emperature range (–40°C to +85°C) parts are also available to special ranges. Please contact your local Analog Devices
representative.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7121/ADV7122 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore, p roper
ESD precautions are recommended to avoid performance degradation or loss of fu nctionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
ADV7121/ADV7122
P IN FUNCTIO N D ESCRIP TIO N
P in
Mnem onic
Function
BLANK*
Composite blank control input (T T L compatible). A logic zero on this control input drives the analog outputs,
IOR, IOB and IOG, to the blanking level. T he BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a logical zero, the R0–R9, G0–G9 and R0–R9 pixel inputs are ignored.
SYNC*
Composite sync control input (T T L compatible). A logical zero on the SYNC input switches off a 40 IRE
current source. T his is internally connected to the IOG analog output. SYNC does not override any other
control or data input, therefore, it should only be asserted during the blanking interval. SYNC is latched on the
rising edge of CLOCK.
If sync information is not required on the green channel, the SYNC input should be tied to logical zero.
CLOCK
Clock input (T T L compatible). T he rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be
driven by a dedicated T T L buffer.
R0–R9,
G0–G9,
B0–B9
Red, green and blue pixel data inputs (T T L compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
IOR, IOG, IOB Red, green, and blue current outputs. T hese high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or not
they are all being used.
FS ADJUST
Full-scale adjust control. A resistor (RSET ) connected between this pin and GND, controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
T he relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG)
is given by:
RSET (Ω)
= 12,082 × VREF (V)/IOG (mA)
T he relationship between RSET and the full-scale output current on IOR, IOG and IOB is given by:
IOG* (mA)
IOR, IOB (mA)
= 12,082 × VREF (V)/RSET (Ω) (SYNC being asserted)
= 8,628 × VREF (V)/RSET (Ω)
T he equation for IOG will be the same as that for IOR and IOB when SYNC is not being used, i.e., SYNC
tied permanently low. For the ADV7121, all three analog output currents are as described by:
IOR, IOG, IOB (mA)
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and VAA
= 7,969 × VREF (V)/RSET (Ω)
COMP
VREF
.
Voltage reference input. An external 1.23 V voltage reference must be connected to this pin. T he use of an
external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be
connected between VREF and VAA
.
VAA
Analog power supply (5 V ± 5%). All VAA pins on the ADV7121/ADV7122 must be connected.
GND
Ground. All GND pins must be connected.
*SYNC and BLANK functions are not provided on the ADV7121.
REV. B
–6–
ADV7121/ADV7122
TERMINO LO GY
D igital Inputs
Blanking Level
T hirty bits of pixel data (color information) R0–R9, G0–G9 and
B0–B9 are latched into the device on the rising edge of each
clock cycle. T his data is presented to the three 10-bit DACs and
is then converted to three analog (RGB) output waveforms. See
Figure 2.
T he level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
Color Video (RGB)
T he ADV7122 has two additional control signals, which are
latched to the analog video outputs in a similar fashion. BLANK
and SYNC are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
T his usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
T he BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
T his is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7121/ADV7122. T he
influence of SYNC and BLANK on the analog video waveform
is illustrated.
Sync Signal (SYNC)
T he position of the composite video signal which synchronizes
the scanning process.
Gr ay Scale
T he discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
T able I details the resultant effect on the analog outputs of
BLANK and SYNC.
Raster Scan
T he most basic method of sweeping a CRT one line at a time to
generate and display images.
All these digital inputs are specified to accept T T L logic levels.
Refer ence Black Level
Clock Input
T he maximum negative polarity amplitude of the video signal.
T he CLOCK input of the ADV7121/ADV7122 is typically the
pixel clock rate of the system. It is also known as the dot rate.
T he dot rate, and hence the required CLOCK frequency, will be
determined by the on-screen resolution, according to the follow-
ing equation:
Refer ence White Level
T he maximum positive polarity amplitude of the video signal.
Sync Level
T he peak level of the SYNC signal.
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
Video Signal
T hat portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
Horiz Res
Vert Res
=
=
=
Number of Pixels/Line.
Number of Lines/Frame.
Refresh Rate
Horizontal Scan Rate. T his is the rate at
which the screen must be refreshed, typ-
ically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
CIRCUIT D ESCRIP TIO N & O P ERATIO N
T he ADV7121/ADV7122 contains three 10-bit D/A converters,
with three input channels, each containing a 10-bit register.
Also integrated on board the part is a reference amplifier. CRT
control functions BLANK and SYNC are integrated on board
the ADV7122.
Retrace Factor
=
T otal Blank T ime Factor. T his takes into
account that the display is blanked for a
certain fraction of the total duration of
each frame (e.g., 0.8).
CLOCK
DIGITAL INPUTS
(R0–R9, G0–G9, B0–B9;
SYNC, BLANK)
DATA
ANALOG OUTPUTS
(IOR, IOG, IOB)
Figure 2. Video Data Input/Output
REV. B
–7–
ADV7121/ADV7122
If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace fac-
tor of 0.8, then:
T he required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7121/
ADV7122 on the rising edge of CLOCK, as previously de-
scribed in the “Digital Inputs” section. It is recommended that
the CLOCK input to the ADV7121/ADV7122 be driven by a
T T L buffer (e.g., 74F244).
Dot Rate = 1024 × 1024 × 60/0.8
=
78.6 MHz
RED, BLUE
mA
19.05 0.714 26.67 1.000
GREEN
WHITE LEVEL
V
mA
V
92.5 IRE
BLACK LEVEL
BLANK LEVEL
1.44 0.054 9.05 0.340
7.5 IRE
40 IRE
0
0
7.62 0.286
0
0
SYNC LEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω
LOAD.
2. VREF = 1.235V, RSET = 560Ω.
3. RS–343A LEVELS AND TOLERANCES ASSUMED ON ALL
LEVELS.
Figure 3. RGB Video Output Waveform
Table Ia. Video O utput Truth Table for the AD V7122
IO G
(m A)*
IO R, IO B
(m A)
D AC
Input D ata
D escription
SYNC
BLANK
WHIT E LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
19.05
video + 1.44
video + 1.44
1.44
1.44
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
3FFH
data
data
00H
00H
xxH
video + 9.05
video + 1.44
9.05
1.44
7.62
0
0
xxH
*T ypical with full-scale IOG = 26.67 mA. VREF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG.
Table Ib. Video O utput Truth Table for the AD V7121
IO R, IO G, IO B
D AC
D escription
(m A)*
Input D ata
WHIT E LEVEL
VIDEO
VIDEO to BLACK
BLACK LEVEL
17.62
video
video
0
3FF
data
data
00H
*T ypical with full scale = 17.62 mA. VREF = 1.235 V, RSET = 560 Ω.
REV. B
–8–
ADV7121/ADV7122
Using a variable value of RSET , as shown in Figure 4, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560 Ω RSET resistor yields the analog output levels as quoted
in the specification page. T hese values typically correspond to
the RS-343A video waveform values as shown in Figure 3.
Video Synchr onization & Contr ol
T he ADV7122 has a single composite sync (SYNC) input con-
trol. Many graphics processors and CRT controllers have the
ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
D /A Conver ter s
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
T he ADV7121/ADV7122 contains three matched 10-bit D/A
converters. T he DACs are designed using an advanced, high
speed, segmented architecture. T he bit currents corresponding
to each digital input are routed to either the analog output (bit
= “1”) or GND (bit = “0”) by a sophisticated decoding scheme.
As all this circuitry is on one monolithic device, matching be-
tween the three DACs is optimized. As well as matching, the
use of identical current sources in a monolithic design guaran-
tees monotonicity and low glitch. T he onboard operational am-
plifier stabilizes the full-scale output current against temperature
and power supply variations.
T he sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync in-
formation onto the ADV7122, the SYNC input should be tied
to logic low.
Refer ence Input
An external 1.23 V voltage reference is required to drive the
ADV7121/ADV7122. T he AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost, tempera-
ture compensated bandgap voltage reference which provides a
fixed 1.23 V output voltage for input currents between 50 µA
and 5 mA. Figure 4 shows a typical reference circuit connection
diagram. T he voltage reference gets its current drive from the
ADV7121/ADV7122’s VAA through an onboard 1 kΩ resistor to
the VREF pin. A 0.1 µF ceramic capacitor is required between
the COMP pin and VAA. T his is necessary so as to provide com-
pensation for the internal reference amplifier.
Analog O utputs
T he ADV7121/ADV7122 has three analog outputs, correspond-
ing to the red, green and blue video signals.
T he red, green and blue analog outputs of the ADV7121/
ADV7122 are high impedance current sources. Each one of
these three RGB current outputs is capable of directly driving a
37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable.
Figure 5a shows the required configuration for each of the three
RGB outputs connected into a doubly terminated 75 Ω load.
T his arrangement will develop RS-343A video output voltage
levels across a 75 Ω monitor.
A resistance RSET connected between FS ADJUST and GND
determines the amplitude of the output video level according to
Equations 1 and 2 for the ADV7122 and Equation 3 for the
ADV7121:
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 5b. T he output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
IOG* (mA) = 12,082 × VREF (V)/RSET (Ω)
(1)
(2)
(3)
IOR, IOB (mA) = 8,628 × VREF (V)/RSET (Ω)
IOR, IOG, IOB (mA) = 7,969 × VREF (V)/RSET (Ω)
IOR, IOG, IOB
ZO = 75Ω
*Only applies to the ADV7122 when SYNC is being used. If SYNC is not being
encoded onto the green channel, then Equation 1 will be similar to Equation 2.
DACs
(CABLE)
ZL = 75Ω
ZS = 75Ω
(SOURCE
TERMINATION)
ANALOG POWER PLANE
(MONITOR)
+
5V
0.01µF
COMP
V
V
AA
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
1kΩ
I
≈ 5mA
REF
REF
Figure 5a. Analog Output Term ination for RS-343A
TO DACs
FS ADJUST
IOR, IOG, IOB
ZO = 75Ω
DACs
AD589
(1.235V
VOLTAGE
REFERENCE)
500Ω
100Ω
(CABLE)
ZL = 75Ω
R
ZS = 150Ω
(SOURCE
SET
(MONITOR)
560Ω
TERMINATION)
GND
ADV7121/ADV7122*
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARIITY
Figure 5b. Analog Output Term ination for RS-170
Figure 4. Reference Circuit
REV. B
–9–
ADV7121/ADV7122
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an Application Note entitled “Video Formats &
Required Load T erminations” available from Analog Devices,
publication no. E1228–15–1/89.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired video
level.
Z
Z
1
2
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Fig-
ure 5a. As well as the gray scale levels, Black Level to White
Level, the diagram also shows the contributions of SYNC and
BLANK for the ADV7122. T hese control inputs add appropri-
ately weighted currents to the analog outputs, producing the
specific output level requirements for video applications.
T able Ia. details how the SYNC and BLANK inputs modify
the output levels.
0.1µF
+V
S
Z
= 75Ω
O
IOR, IOG, IOB
DACs
2
7
75Ω
6
AD848
3
4
0.1µF
Z
= 75Ω
L
(CABLE)
(MONITOR)
Z
= 75Ω
S
–V
S
Z
1
(SOURCE
TERMINATION)
GAIN (G) = 1+ ––
Z
2
Figure 7. AD848 As an Output Buffer
P C Boar d Layout Consider ations
Gr ay Scale O per ation
T he ADV7121/ADV7122 can be used for stand-alone, gray
scale (monochrome) or composite video applications (i.e., only
one channel used for video information). Any one of the three
channels, RED, GREEN or BLUE can be used to input the
digital video data. T he two unused video data channels should
be tied to logical zero. T he unused analog outputs should be
terminated with the same load as that for the used channel. In
other words, if the red channel is used and IOR is terminated
with a doubly terminated 75 Ω load (37.5 Ω), IOB and IOG
should be terminated with 37.5 Ω resistors. See Figure 6.
T he ADV7121/ADV7122 is optimally designed for lowest noise
performance, both radiated and conducted noise. T o comple-
ment the excellent noise performance of the ADV7121/ADV7122
it is imperative that great care be given to the PC board layout.
Figure 8 shows a recommended connection diagram for the
ADV7121/ADV7122.
T he layout should be optimized for lowest noise on the
ADV7121/ADV7122 power and ground lines. T his can be
achieved by shielding the digital inputs and providing good de-
coupling. T he lead length between groups of VAA and GND
pins should by minimized so as to minimize inductive ringing.
DOUBLY
TERMINATED
75Ω LOAD
IOR
IOG
R0
R9
VIDEO
INPUT
Gr ound P lanes
T he ADV7121/ADV7122 and associated analog circuitry,
should have a separate ground plane referred to as the analog
ground plane. T his ground plane should connect to the regular
PCB ground plane at a single point through a ferrite bead, as il-
lustrated in Figure 8. T his bead should be located as close as
possible (within 3 inches) to the ADV7121/ADV7122.
G0
G9
37.5Ω
37.5Ω
B0
B9
IOB
T he analog ground plane should encompass all ADV7121/
ADV7122 ground pins, voltage reference circuitry, power sup-
ply bypass circuitry, the analog output traces and any output
amplifiers.
ADV7121/ADV7122
GND
T he regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7121/ADV7122.
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Com posite Video
Video O utput Buffer s
P ower P lanes
T he ADV7121/ADV7122 is specified to drive transmission line
loads, which is what most monitors are rated as. T he analog
output configurations to drive such loads are described in the
Analog Interface section and illustrated in Figure 5. However,
in some applications it may be required to drive long “transmis-
sion line” cable lengths. Cable lengths greater than 10 meters
can attenuate and distort high frequency analog output pulses.
T he inclusion of output buffers will compensate for some cable
distortion. Buffers with large full power bandwidths and gains
between 2 and 4 will be required. T hese buffers will also need
to be able to supply sufficient current over the complete output
voltage swing. Analog Devices produces a range of suitable op
amps for such applications. T hese include the AD84x series of
monolithic op amps. In very high frequency applications (80 MHz),
the AD9617 is recommended. More information on line driver
buffering circuits is given in the relevant op amp data sheets.
T he PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. T he analog
power plane should encompass the ADV7121/ADV7122 (VAA
)
and all associated analog circuitry. T his power plane should be
connected to the regular PCB power plane (VCC) at a single
point through a ferrite bead, as illustrated in Figure 8. T his bead
should be located within three inches of the ADV7121/ADV7122.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7121/ADV7122 power pins, voltage reference
circuitry and any output amplifiers.
T he PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
REV. B
–10–
ADV7121/ADV7122
COMP
C6
0.1µF
R0
R9
ANALOG POWER PLANE
VAA
VIDEO
DATA
INPUTS
G0
G9
L1 (FERRITE BEAD)
C3
0.1µF
C4
0.1µF
C5
0.1µF
+5V (VCC
)
B0
B9
VREF
C2
10µF
C1
33µF
Z1 (AD589)
ADV7121/ADV7122
GND
ANALOG GROUND PLANE
GROUND
L2 (FERRITE BEAD)
RSET
560Ω
R1
75Ω
R2
75Ω
R3
75Ω
FS ADJUST
IOR
CLOCK
RGB
VIDEO
CONTROL
INPUTS
VIDEO
OUTPUT
IOG
SYNC*
IOB
BLANK*
*SYNC and BLANK FUNCTIONS ARE NOT PROVIDED ON THE ADV7121.
DESCRIPTION
VENDOR PART NUMBER
COMPONENT
33µF TANTALUM CAPACITOR
10µF TANTALUM
C1
C2
0.1µF CERAMIC CAPACITOR
FERRITE BEAD
C3, C4, C5, C6
L1, L2
FAIR-RITE 274300111 OR MURATA BL01/02/03
DALE CMF-55C
75Ω 1% METAL FILM RESISTOR
560Ω 1% METAL FILM RESISTOR
1.235V VOLTAGE REFERENCE
R1, R2, R3
RSET
DALE CMF-55C
ANALOG DEVICES AD589JH
Z1
Figure 8. ADV7121/ADV7122 Typical Connection Diagram and Com ponent List
Supply D ecoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 8).
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC),
and not the analog power plane.
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individually
decoupled to ground. T his should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
Analog Signal Inter connect
T he ADV7121/ADV7122 should be located as close as possible
to the output connectors thus minimizing noise pickup and re-
flections due to impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
It is important to note that while the ADV7121/ADV7122 con-
tains circuitry to reject power supply noise, this rejection de-
creases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduce
ing power supply noise. A dc power supply filter (Murata
BNX002) will provide EMI suppression between the switching
power supply and the main PCB. Alternatively, consideration
could be given to using a three terminal voltage regulator.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). T his termination resistance
should be as close as possible to the ADV7121/ADV7122 so as
to minimize reflections.
Additional information on PCB design is available in an appli-
cation note entitled “Design and Layout of a Video Graphics
System for Reduced EMI.” T his application note is available
from Analog Devices, publication no. E1309–15–10/89.
D igital Signal Inter connect
T he digital signal lines to the ADV7121/ADV7122 should be
isolated as much as possible from the analog outputs and other
analog circuitry. Digital signal lines should not overlay the ana-
log power plane.
Due to the high clock rates used, long clock lines to the
ADV7121/ADV7122 should be avoided so as to minimize noise
pickup.
REV. B
–11–
ADV7121/ADV7122
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
44-Term inal P lastic Leaded Chip Carrier
(P -44A)
40-P in P lastic D IP
(N-40A)
REV. B
–12–
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