ADV7125JST330 [ADI]
CMOS, 330 MHz Triple 8-Bit High Speed Video DAC; CMOS ， 330 MHz三通道，8位高速视频DAC
| 型号： | ADV7125JST330 |
| 厂家： | 
ADI |
| 描述： | CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| 文件： | 总12页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, 330 MHz
a
Triple 8-Bit High Speed Video DAC
ADV7125
FEATURES
FUNCTIONAL BLOCK DIAGRAM
330 MSPS Throughput Rate
Triple 8-Bit DACs
V
AA
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40°C to +85°C)
BLANK
SYNC
BLANK AND
SYNC LOGIC
IOR
DATA
8
R7–R0
8
8
8
DAC
DAC
DAC
REGISTER
IOR
IOG
DATA
REGISTER
G7–G0
B7–B0
8
8
IOG
IOB
DATA
REGISTER
IOB
APPLICATIONS
VOLTAGE
REFERENCE
CIRCUIT
POWER-DOWN
MODE
PSAVE
Digital Video Systems
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
V
REF
CLOCK
ADV7125
GND
R
COMP
SET
Instrumentation
Video Signal Reconstruction
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
1. 330 MSPS (3.3 V only) throughput
2. Guaranteed monotonic to eight bits
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170
The ADV®7125 is a triple high speed, digital-to-analog converter
on a single monolithic chip. It consists of three high speed, 8-bit
video DACs with complementary outputs, a standard TTL input
interface, and a high impedance, analog output current source.
The ADV7125 has three separate 8-bit-wide input ports. A single
5 V/3.3 V power supply and clock are all that are required to make
the part functional. The ADV7125 has additional video control
signals, composite SYNC and BLANK, as well as a power-
save mode.
The ADV7125 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7125 is available in a 48-lead
LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADV7125–SPECIFICATIONS
(VAA = 5 V 5%, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to
5 V ELECTRICAL CHARACTERISTICS TMAX1, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
8
–1
–1
Bits
LSB
LSB
0.4
0.25
+1
+1
Guaranteed Monotonic
VIN = 0.0 V or VDD
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2
V
V
µA
µA
pF
0.8
+1
–1
20
10
ANALOG OUTPUTS
Output Current
Output Current
2.0
2.0
26.5
18.5
5
mA
mA
%
V
kΩ
pF
Green DAC, Sync = High
R/G/B DAC, Sync = Low
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.0
0
1.4
100
10
IOUT = 0 mA
Tested with DAC Output = 0 V
FSR = 18.62 mA
–0.025
–5.0
+0.025
+5.0
% FSR
% FSR
Gain Error2
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current3
Digital Supply Current3
Digital Supply Current3
Analog Supply Current
Analog Supply Current
Standby Supply Current4
3.4
10.5
18
67
8
9
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 530 Ω
RSET = 4933 Ω
15
25
72
2.1
5.0
0.5
PSAVE = Low, Digital, and Control
Inputs at VDD
Power Supply Rejection Ratio
0.1
%/%
NOTES
1Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
2Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF/RSET × K × (FFH) × 4 and K = 7.9896.
3Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
4These max/min specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
.
Specifications subject to change without notice.
–2–
REV. 0
ADV7125
(VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications
3.3 V ELECTRICAL CHARACTERISTICS1 TMIN to TMAX2, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Test Conditions2
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
8
+1
+1
Bits
LSB
LSB
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
–1
–1
0.5
0.25
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2.0
–1
V
V
µA
µA
pF
0.8
+1
VIN = 0.0 V or VDD
20
10
ANALOG OUTPUTS
Output Current
Output Current
2.0
2.0
26.5
18.5
mA
mA
%
V
kΩ
pF
Green DAC, Sync = High
R/G/B DAC, Sync = Low
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.0
0
1.4
0
70
10
0
% FSR
% FSR
Tested with DAC Output = 0 V
FSR = 18.62 mA
Gain Error3
0
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
1.12
1.235
1.235
1.35
V
V
VOLTAGE REFERENCE (Int.)
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current4
Digital Supply Current4
Digital Supply Current4
Digital Supply Current4
Analog Supply Current
Analog Supply Current
Standby Supply Current
2.2
6.5
11
16
67
8
5.0
12.0
15
mA
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
fCLK = 330 MHz
RSET = 560 Ω
RSET = 4933 Ω
72
2.1
5.0
0.5
PSAVE = Low, Digital, and Control
Inputs at VDD
Power Supply Rejection Ratio
0.1
%/%
NOTES
1These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF/RSET × K × (FFH) × 4 and K = 7.9896.
4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
.
Specifications subject to change without notice.
REV. 0
–3–
ADV7125
3
(VAA = 5 V 5%2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX
,
5 V TIMING SPECIFICATIONS1 unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
5.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
fCLK
fCLK
0.5
0.5
0.5
0.5
50
140
240
MHz
MHz
MHz
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
7
7
6
Data and Control Setup, t1
Data and Control Hold, t2
6
1.5
ns
Clock Period, t3
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Clock Pulsewidth High, t4
4.17
1.875
1.875
2.85
2.85
8.0
ns
ns
ns
ns
ns
ns
6
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
6
6
6
Clock Pulsewidth Low, t5
8.0
1.0
ns
6
Pipeline Delay, tPD
1.0
2
1.0
10
Clock Cycles
ns
6
PSAVE Up Time, t10
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
–4–
REV. 0
ADV7125
(VAA = 3.0 V to 3.6 V2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN
3.3 V TIMING SPECIFICATIONS1 to TMAX3, unless otherwise noted, TJ MAX = 110؇C.)
Parameter
Min
Typ
Max
Unit
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
7.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
fCLK
fCLK
fCLK
50
MHz
MHz
MHz
MHz
ns
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
330 MHz Grade
7
140
240
330
7
7
6
Data and Control Setup, t1
Data and Control Hold, t2
0.2
1.5
6
Clock Period, t3
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
Clock Pulsewidth High, t4
Clock Pulsewidth Low, t5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
6
fCLK_MAX = 330 MHz
fCLK_MAX = 330 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
6
6
6
6
6
ns
6
Pipeline Delay, tPD
PSAVE Up Time, t10
1.0
4
1.0
10
Clock Cycles
ns
6
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
Specifications subject to change without notice.
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
(R7–R0, G7–G0, B7–B0,
SYNC, BLANK)
DATA
t1
t8
t6
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t7
NOTES
1. OUTPUT DELAY (t6) MEASURED FROMTHE 50% POINT OFTHE RISING EDGE OF CLOCKTOTHE 50% POINT
OF FULL-SCALETRANSITION.
2. OUTPUT RISE/FALLTIME (t7) MEASURED BETWEENTHE 10% AND 90% POINTS OF FULL-SCALETRANSITION.
3. TRANSITIONTIME (t8) MEASURED FROMTHE 50% POINT OF FULL-SCALETRANSITIONTOWITHIN 2% OFTHE
FINAL OUTPUTVALUE.
Figure 1. Timing Diagram
REV. 0
–5–
ADV7125
ABSOLUTE MAXIMUM RATINGS1
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Analog output short circuit to any power supply or common can be of an indefinite
duration.
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on any Digital Pin . . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
ORDERING GUIDE
Speed Options
Package
50 MHz1
140 MHz1
240 MHz2
330 MHz2, 3
Plastic LQFP (ST-48)
ADV7125KST50
ADV7125KST140
ADV7125JST240
ADV7125JST330
NOTES
1Specified for –40°C to +85°C operation.
2Specified for 0°C to +70°C operation.
3Available in 3.3 V version only.
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
GND
GND
G0
36
35
34
33
32
31
30
29
28
27
26
25
V
REF
PIN 1
IDENTIFIER
COMP
IOR
G1
IOR
G2
IOG
ADV7125
TOP VIEW
(Not to Scale)
G3
IOG
G4
V
AA
G5
V
AA
G6
IOB
G7 10
IOB
11
12
BLANK
SYNC
GND
GND
13 14 15 16 17 18 19 20 21 22 23 24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7125 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–6–
REV. 0
ADV7125
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Function
Ground. All GND pins must be connected.
1, 2, 14, 15, 25, GND
26, 39, 40
3–10,
16–23,
41–48
G0–G7,
B0–B7,
R0–R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge
of CLOCK. R0, G0, and B0 are the least significant data bits. Unused pixel data inputs should
be connected to either the regular PCB power or ground plane.
11
12
BLANK
SYNC
Composite Blank Control Input (TTL Compatible). A logic zero on this control input drives the
analog outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the
rising edge of CLOCK. While BLANK is a logical zero, the R0–R7, G0–G7, and B0–B7 pixel
inputs are ignored.
Composite Sync Control Input (TTL Compatible). A logical zero on the SYNC input switches
off a 40 IRE current source. This is internally connected to the IOG analog output. SYNC does
not override any other control or data input; therefore, it should only be asserted during the
blanking interval. SYNC is latched on the rising edge of CLOCK. If sync information is not
required on the green channel, the SYNC input should be tied to logical zero.
13, 29, 30
24
VAA
Analog Power Supply (5 V 5%). All VAA pins on the ADV7125 must be connected.
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7,
SYNC, and BLANK pixel and control inputs. It is typically the pixel clock rate of the video
system. CLOCK should be driven by a dedicated TTL buffer.
27, 31, 33
IOR, IOG, IOB Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These
RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly
terminated 75 Ω load. If the complementary outputs are not required, these outputs should be
tied to ground.
28, 32, 34
35
IOR, IOG, IOB Red, Green, and Blue Current Outputs. These high impedance current sources are capable of
directly driving a doubly terminated 75 Ω coaxial cable. All three current outputs should have
similar output loads whether or not they are all being used.
COMP
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF
ceramic capacitor must be connected between COMP and VAA
.
36
37
VREF
RSET
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V)
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale
video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC
is connected to IOG) is given by:
RSET Ω = 11,445 ×V
V / IOG mA
( )
( )
(
)
REF
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG mA = 11,444.8 ×V
V / R
Ω SYNC being asserted
(
)
( ) SET ( )(
)
REF
IOR, IOB mA = 7,989.6 ×V
V / R
Ω
(
)
( )
( )
REF
SET
The equation for IOG will be the same as that for IOR and IOB when SYNC is not being used,
i.e., SYNC tied permanently low.
38
PSAVE
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this
pin is active.
REV. 0
–7–
ADV7125
TERMINOLOGY
Raster Scan
Blanking Level
The most basic method of sweeping a CRT one line at a time to
generate and display images.
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that will shut off the picture
tube, resulting in the blackest possible picture.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Color Video (RGB)
This usually refers to the technique of combining the three
primary colors of red, green, and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Level
The peak level of the SYNC signal.
Video Signal
The portion of the composite video signal that varies in grayscale
levels between reference white and reference black. Also referred
to as the picture signal, this is the portion that may be visually
observed.
Sync Signal (SYNC)
The position of the composite video signal that synchronizes the
scanning process.
Grayscale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.
–8–
REV. 0
ADV7125
CIRCUIT DESCRIPTION AND OPERATION
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7125. The influence of
SYNC and BLANK on the analog video waveform is illustrated.
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated on
board the part is a reference amplifier. CRT control functions
BLANK and SYNC are integrated on board the ADV7125.
Digital Inputs
Twenty-four bits of pixel data (color information) R0–R7, G0–G7,
and B0–B7 are latched into the device on the rising edge of
each clock cycle. This data is presented to the three 8-bit DACs
and then converted to three analog (RGB) output waveforms
(See Figure 2).
Table I details the resultant effect on the analog outputs of
BLANK and SYNC.
All these digital inputs are specified to accept TTL logic levels.
Clock Input
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, will be determined by
the on-screen resolution, according to the following equation:
CLOCK
DIGITAL INPUTS
(R7–R0, G7–G0, B7–B0,
DATA
SYNC, BLANK)
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/(Retrace Factor)
Horiz Res = Number of Pixels/Line
ANALOG OUTPUTS
(IOR, IOR, IOB
IOR, IOG, IOB)
Vert Res = Number of Lines/Frame
Figure 2. Video Data Input/Output
Refresh Rate = Horizontal Scan Rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system or 30 Hz for an interlaced system.
The ADV7125 has two additional control signals that are latched
to the analog video outputs in a similar fashion. BLANK and
SYNC are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
Retrace Factor = Total Blank Time Factor. This takes into account
that the display is blanked for a certain fraction of the total
duration of each frame (e.g., 0.8).
RED, BLUE
GREEN
mA
mA
V
V
18.62
0.7
26.67
1.000
WHITE LEVEL
100 IRE
BLANK LEVEL
SYNC LEVEL
0
0
8.62
0.3
43 IRE
0
0
NOTES
1. OUTPUTS CONNECTEDTO A DOUBLYTERMINATED 75⍀ LOAD.
2.V = 1.235V, R = 530⍀.
REF
SET
3. RS-343A LEVELS ANDTOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Table I. Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
Description
IOG (mA)
IOG (mA)
IOR/IOB
IOR/IOB
SYNC
BLANK
DAC Input Data
WHITE LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
Video + 8.05
Video
8.05
0
8.05
0
0
18.62
Video
Video
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
0
FFH
Data
Data
00H
00H
xxH
xxH
18.62 – Video
18.62 – Video
18.62
18.62
18.62
18.62 – Video
18.62 – Video
18.62
18.62
18.62
18.62
18.62
REV. 0
–9–
ADV7125
Therefore, if we have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate, and a retrace
factor of 0.8, then:
Analog Outputs
The ADV7125 has three analog outputs, corresponding to the
red, green, and blue video signals.
The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load,
such as a doubly terminated 75 Ω coaxial cable. Figure 4a
shows the required configuration for each of the three RGB
outputs connected into a doubly terminated 75 Ω load. This
arrangement develops RS-343A video output voltage levels
across a 75 Ω monitor.
Dot Rate = 1024 ×1024 × 60 / 0.8
= 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7125
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7125 be driven by a TTL buffer (e.g., 74F244).
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 4b. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
Video Synchronization and Control
The ADV7125 has a single composite sync (SYNC) input con-
trol. Many graphics processors and CRT controllers have the
ability to generate horizontal sync (HSYNC), vertical sync
(VSYNC), and composite SYNC.
IOR, IOG, IOB
Z
= 75⍀
O
In a graphics system that does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry enables the generation of a composite SYNC signal.
DACs
(CABLE)
Z
= 75⍀
S
Z
= 75⍀
L
(SOURCE
(MONITOR)
TERMINATION)
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7125, the SYNC input should be tied
to logic low.
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
Figure 4a. Analog Output Termination for RS-343A
Reference Input
The ADV7125 contains an on-board voltage reference. The
IOR, IOG, IOB
Z
= 75⍀
O
DACs
V
REF pin is normally terminated to VAA through a 0.1 µF capaci-
(CABLE)
Z
= 150⍀
(SOURCE
TERMINATION)
S
tor. Alternatively, the part could, if required, be overdriven by
Z = 75⍀
L
(MONITOR)
an external 1.23 V reference (AD1580).
A resistance, RSET, connected between the RSET pin and GND
determines the amplitude of the output video level according to
Equations 1 and 2 for the ADV7125:
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
Figure 4b. Analog Output Termination for RS-170
IOG * mA = 11,444.8 ×V
V / R
( )
Ω
( )
(1)
(
)
REF
SET
More detailed information regarding load terminations for various
output configurations, including RS-343A and RS-170, is avail-
able in an application note entitled, Video Formats and Required
Load Terminations available from Analog Devices,
IOR, IOB mA = 7,989.6 ×V
V / R
Ω
(2)
(
)
( )
( )
REF
SET
*Applies to the ADV7125 only when SYNC is being used. If SYNC is not being
encoded onto the green channel, Equation 1 will be similar to Equation 2.
(www.analog.com/library/applicationNotes/video/AN205.pdf).
Using a variable value of RSET allows for accurate adjustment of
the analog output video levels. Use of a fixed 560 Ω RSET resistor
yields the analog output levels quoted in the specification page.
These values typically correspond to the RS-343A video wave-
form values as shown in Figure 3.
Figure 3 shows the video waveforms associated with the three RGB
outputs driving the doubly terminated 75 Ω load of Figure 4a. As
well as the gray scale levels (black level to white level), the diagram
also shows the contributions of SYNC and BLANK for the
ADV7125. These control inputs add appropriately weighted cur-
rents to the analog outputs, producing the specific output level
requirements for video applications. Table I details how the SYNC
and BLANK inputs modify the output levels.
DACs
The ADV7125 contains three matched 8-bit DACs. The DACs
are designed using an advanced, high speed, segmented archi-
tecture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = “1”) or GND (bit = “0”)
by a sophisticated decoding scheme. As all this circuitry is on
one monolithic device, matching between the three DACs is
optimized. As well as matching, the use of identical current sources
in a monolithic design guarantees monotonicity and low glitch.
The on-board operational amplifier stabilizes the full-scale
output current against temperature and power supply variations.
Grayscale Operation
The ADV7125 can be used for standalone, grayscale (mono-
chrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.
The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
–10–
REV. 0
ADV7125
channel is used and IOR is terminated with a doubly terminated
75 Ω load (37.5 Ω), IOB and IOG should be terminated with
37.5 Ω resistors (See Figure 5).
Ground Planes
The ADV7125 and associated analog circuitry should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 7. This bead should be located as close as possible
(within three inches) to the ADV7125.
DOUBLY
VIDEO
INPUT
R0
R7
TERMINATED
IOR
IOG
75⍀ LOAD
ADV7125
37.5⍀
37.5⍀
The analog ground plane should encompass all ADV7125
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces, and any output amplifiers.
G0
G7
IOB
B0
B7
The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7125.
GND
Figure 5. Input and Output Connections for
Standalone Grayscale or Composite Video
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7125 (VAA) and all
associated analog circuitry. This power plane should be con-
nected to the regular PCB power plane (VCC) at a single point
through a ferrite bead, as illustrated in Figure 6. This bead
should be located within three inches of the ADV7125.
Video Output Buffers
The ADV7125 is specified to drive transmission line loads, as
are most monitors rated. The analog output configurations to
drive such loads are described in the Analog Outputs section
and are illustrated in Figure 6. However, in some applications,
it may be required to drive long transmission line cable lengths.
Cable lengths greater than 10 meters can attenuate and distort
high frequency analog output pulses. The inclusion of output
buffers will compensate for some cable distortion. Buffers with
large full power bandwidths and gains between two and four will
be required. These buffers will also need to be able to supply
sufficient current over the complete output voltage swing. Analog
Devices produces a range of suitable op amps for such applica-
tions. These include the AD84x series of monolithic op amps.
In very high frequency applications (80 MHz), the AD8061 is
recommended. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7125 power pins, voltage reference circuitry,
and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 7).
Use of buffer amplifiers also allows implementation of other video
standards besides RS-343A and RS-170. Altering the gain com-
ponents of the buffer circuit will result in any desired video level.
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individually
decoupled to ground. This should be done by placing the capaci-
tors as close as possible to the device with the capacitor leads as
short as possible, thus minimizing lead inductance.
Z
Z
1
2
0.1F
0.1F
+V
S
It is important to note that while the ADV7125 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three-terminal voltage regulator.
Z
= 75⍀
O
IOR, IOG, IOB
DACs
75⍀
AD848
Z
= 75⍀
L
(CABLE)
(MONITOR)
Z
= 75⍀
S
–V
S
Z
Z
(SOURCE
1
GAIN (G) = 1 +
TERMINATION)
2
Figure 6. AD848 As an Output Buffer
PC Board Layout Considerations
Digital Signal Interconnect
The ADV7125 is optimally designed for lowest noise performance,
both radiated and conducted noise. To complement the excel-
lent noise performance of the ADV7125, it is imperative that
great care be given to the PC board layout. Figure 7 shows a
recommended connection diagram for the ADV7125.
The digital signal lines to the ADV7125 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
Due to the high clock rates used, long clock lines to the ADV7125
should be avoided to minimize noise pickup.
The layout should be optimized for lowest noise on the ADV7125
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should by minimized to
minimize inductive ringing.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC) and
not the analog power plane.
REV. 0
–11–
ADV7125
Analog Signal Interconnect
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly termi-
nated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7125 to minimize reflections.
The ADV7125 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
Additional information on PCB design is available in an application
note entitled Design and Layout of a Video Graphics System for
Reduced EMI. This application note is available from Analog
Devices, publication no. E1309–15–10/89 (www.analog.com/
library/applicationNotes/designTech/AN333.pdf).
POWER SUPPLY DECOUPLING (0.1F AND 0.01F
CAPACITOR FOR EACH V GROUP)
AA
L1
0.1F
0.01F
13, 29,
30
(FERRITE BEAD)
V
V
0.1F
AA
CC
V
AA
5V (V
)
COMP
R7–R0
AA
ANALOG GROUND PLANE
0.1F
10F
33F
41–48
5V (V
)
V
AA
REF
R
SET
3–10
R
SET
530⍀
MONITOR
(CRT)
VIDEO
COAXIAL CABLE
G7–G0
B7–B0
DATA
75⍀
INPUTS
IOR
IOG
IOB
16–23
75⍀
75⍀
75⍀
75⍀
75⍀ 75⍀
ADV7125
BNC
CONNECTORS
SYNC
IOR
BLANK
COMPLEMENTARY
OUTPUTS
IOG
IOB
CLOCK
PSAVE
GND
1, 2, 14, 15,
25, 26, 39, 40
Figure 7. Typical Connection Diagram
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7؇
3.5؇
0؇
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–12–
REV. 0
相关型号：
©2020 ICPDF网 联系我们和版权申明