ADV7125KSTZ140 [ADI]
CMOS, 330 MHz Triple 8-Bit High Speed Video DAC; CMOS ， 330 MHz三通道，8位高速视频DAC
| 型号： | ADV7125KSTZ140 |
| 厂家： | 
ADI |
| 描述： | CMOS, 330 MHz Triple 8-Bit High Speed Video DAC |
| 文件： | 总16页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, 330 MHz
Triple 8-Bit High Speed Video DAC
ADV7125
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
AA
330 MSPS throughput rate
Triple 8-bit DACs
RS-343A-/RS-170-compatible output
Complementary outputs
BLANK
SYNC
BLANK AND
SYNC LOGIC
DAC output current range: 2.0 mA to 26.5 mA
TTL-compatible inputs
Internal Reference (1.235 V)
Single-supply +5 V/+3.3 V operation
48-lead LQFP and LFCSP packages
Low power dissipation (30 mW minimum @ 3 V)
Low power standby mode (6 mW typical @ 3 V)
Industrial temperature range (−40°C to +85°C)
Pb-free (lead-free) packages
IOR
IOR
DATA
8
8
8
8
DAC
DAC
DAC
R7 TO R0
G7 TO G0
B7 TO B0
REGISTER
IOG
IOG
DATA
REGISTER
IOB
IOB
DATA
REGISTER
8
8
VOLTAGE
REFERENCE
CIRCUIT
POWER-DOWN
MODE
PSAVE
CLOCK
V
REF
Qualified for automotive applications
ADV7125
APPLICATIONS
GND
R
COMP
SET
Digital video systems
Figure 1.
High resolution color graphics
Digital radio modulation
Image processing
Instrumentation
Video signal reconstruction
Automotive infotainment units
GENERAL DESCRIPTION
The ADV7125 (ADV®) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three high
speed, 8-bit video DACs with complementary outputs, a
standard TTL input interface, and a high impedance, analog
output current source.
The ADV7125 is fabricated in a 5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV7125 is available in
48-lead LQFP and 48-lead LFCSP packages.
PRODUCT HIGHLIGHTS
The ADV7125 has three separate 8-bit-wide input ports. A
single +5 V/+3.3 V power supply and clock are all that are
required to make the part functional. The ADV7125 has
1. 330 MSPS (3.3 V only) throughput.
2. Guaranteed monotonic to eight bits.
3. Compatible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170.
SYNC
BLANK
additional video control signals, composite
as well as a power save mode.
and
,
ADV is a registered trademark of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved.
ADV7125
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description and Operation.............................................. 11
Digital Inputs .............................................................................. 11
Clock Input.................................................................................. 11
Video Synchronization and Control........................................ 12
Reference Input........................................................................... 12
DACs............................................................................................ 12
Analog Outputs .......................................................................... 12
Gray Scale Operation................................................................. 13
Video Output Buffers................................................................. 13
PCB Layout Considerations...................................................... 13
Digital Signal Interconnect ....................................................... 13
Analog Signal Interconnect....................................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Products................................................................. 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Electrical Characteristics...................................................... 3
3.3 V Electrical Characteristics................................................... 4
5 V Timing Specifications ........................................................... 5
3.3 V Timing Specifications ........................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
REVISION HISTORY
2/11—Rev. B to Rev. C
Change to Table 6 ............................................................................. 8
Changes to Figure 3 and Table 6......................................................8
Deleted Ground Planes Section, Power Planes Section, and
Supply Decoupling Section ........................................................... 11
Changes to Figure 5........................................................................ 11
Changes to Table 7, Analog Outputs Section, Figure 6, and
Figure 7 ............................................................................................ 12
Changes to Video Output Buffers Section, PCB Layout
Considerations Section, and Figure 9.......................................... 13
Changes to Analog Signal Interconnect Section and
Figure 10 .......................................................................................... 14
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide.......................................................... 16
7/10—Rev. A to Rev. B
Change to Features Section ............................................................. 1
Changes to Clock Frequency Parameter, Table 4 ......................... 6
Changes to Figure 2.......................................................................... 6
Changes to Figure 4 and Figure 5................................................. 11
Changes to Table 7.......................................................................... 12
Changes to Endnotes to Ordering Guide.................................... 15
Added Automotive Products Section .......................................... 15
3/09—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Changes to Features Section, Applications Section, and General
Description Section.......................................................................... 1
10/02—Revision 0: Initial Version
Rev. C | Page 2 of 16
ADV7125
SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V 5ꢀ, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions1
Guaranteed Monotonic
VIN = ±.± V or VDD
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
8
−1
−1
Bits
LSB
LSB
±±.ꢀ
±±.2ꢁ
+1
+1
2
V
V
μA
μA
pF
±.8
+1
−1
PSAVE Pull-Up Current
2±
1±
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current
Green DAC, SYNC = high
RGB DAC, SYNC = low
2.±
2.±
26.ꢁ
18.ꢁ
ꢁ
mA
mA
%
V
kΩ
pF
% FSR
% FSR
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.±
±
1.ꢀ
1±±
1±
IOUT = ± mA
Tested with DAC output = ± V
FSR = 18.62 mA
−±.±2ꢁ
−ꢁ.±
+±.±2ꢁ
+ꢁ.±
Gain Error2
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current3
1.12
1.23ꢁ
1.3ꢁ
V
3.ꢀ
1±.ꢁ
18
67
8
9
mA
mA
mA
mA
mA
mA
%/%
fCLK = ꢁ± MHz
fCLK = 1ꢀ± MHz
fCLK = 2ꢀ± MHz
RSET = ꢁ3± Ω
RSET = ꢀ933 Ω
PSAVE = low, digital, and control inputs at VDD
1ꢁ
2ꢁ
72
Analog Supply Current
Standby Supply Currentꢀ
2.1
±.1
ꢁ.±
±.ꢁ
Power Supply Rejection Ratio
1 Temperature range TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz and 33± MHz.
2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 1±±), where Ideal = VREF/RSET × K × (±xFFH) × ꢀ and K = 7.9896.
3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at ± V and VDD
ꢀ These maximum/minimum specifications are guaranteed by characterization in the ꢀ.7ꢁ V to ꢁ.2ꢁ V range.
.
Rev. C | Page 3 of 16
ADV7125
3.3 V ELECTRICAL CHARACTERISTICS
VAA = 3.0 V to 3.6 V, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 2.
Parameter2
Min
Typ
Max
Unit
Test Conditions1
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
8
+1
+1
Bits
LSB
LSB
RSET = 68± Ω
RSET = 68± Ω
RSET = 68± Ω
−1
−1
±±.ꢁ
±±.2ꢁ
2.±
−1
V
V
μA
μA
pF
±.8
+1
VIN = ±.± V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
2±
1±
Green DAC, SYNC = high
RGB DAC, SYNC = low
Output Current
2.±
2.±
26.ꢁ
18.ꢁ
mA
mA
%
V
kΩ
pF
% FSR
% FSR
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
1.±
±
1.ꢀ
±
7±
1±
±
Tested with DAC output = ± V
FSR = 18.62 mA
Gain Error3
±
VOLTAGE REFERENCE, EXTERNAL
Reference Range, VREF
VOLTAGE REFERENCE, INTERNAL
Voltage Reference, VREF
POWER DISSIPATION
1.12
1.23ꢁ
1.23ꢁ
1.3ꢁ
V
V
Digital Supply Currentꢀ
2.2
6.ꢁ
11
16
67
8
ꢁ.±
12.±
1ꢁ
mA
mA
mA
mA
mA
mA
mA
%/%
fCLK = ꢁ± MHz
fCLK = 1ꢀ± MHz
fCLK = 2ꢀ± MHz
fCLK = 33± MHz
RSET = ꢁ6± Ω
RSET = ꢀ933 Ω
PSAVE = low, digital, and control inputs at VDD
Analog Supply Current
72
Standby Supply Current
2.1
±.1
ꢁ.±
±.ꢁ
Power Supply Rejection Ratio
1 Temperature range TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz and 33± MHz.
2 These max/min specifications are guaranteed by characterization in the 3.± V to 3.6 V range.
3 Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 1±±), where Ideal = VREF/RSET × K × (±xFFH) × ꢀ and K = 7.9896.
ꢀ Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at ± V and VDD
.
Rev. C | Page ꢀ of 16
ADV7125
5 V TIMING SPECIFICATIONS
VAA = 5 V 5ꢀ,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 3.
Parameter3
Symbol Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Timeꢀ
Analog Output Transition Timeꢁ
Analog Output Skew6
CLOCK CONTROL
t6
t7
t8
t9
ꢁ.ꢁ
1.±
1ꢁ
1
ns
ns
ns
ns
2
CLOCK Frequency7
fCLK
±.ꢁ
ꢁ±
MHz
ꢁ± MHz grade
1ꢀ± MHz grade
2ꢀ± MHz grade
±.ꢁ
±.ꢁ
±.ꢁ
1.ꢁ
ꢀ.17
1.87ꢁ
1.87ꢁ
2.8ꢁ
2.8ꢁ
8.±
1ꢀ±
2ꢀ±
MHz
MHz
ns
ns
ns
ns
ns
ns
Data and Control Setup6
Data and Control Hold6
CLOCK Period
t1
t2
t3
tꢀ
tꢁ
tꢀ
tꢁ
tꢀ
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = ꢁ± MHz
fCLK_MAX = ꢁ± MHz
ns
ns
ns
tꢁ
tPD
t1±
8.±
1.±
1.±
2
1.±
1±
Clock cycles
ns
PSAVE Up Time6
1 The maximum and minimum specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz.
3 Timing specifications are measured with input levels of 3.± V (VIH) and ± V (VIL) for both ꢁ V and 3.3 V supplies.
ꢀ Rise time was measured from the 1±% to 9±% point of zero to full-scale transition, fall time from the 9±% to 1±% point of a full-scale transition.
ꢁ Measured from ꢁ±% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 12ꢁ MHz and ꢁ V. Limits specified here are guaranteed by characterization.
Rev. C | Page ꢁ of 16
ADV7125
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V to 3.6 V,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 4.
Parameter3
Symbol
Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay,
Analog Output Rise/Fall Timeꢀ
Analog Output Transition Timeꢁ
Analog Output Skew6
CLOCK CONTROL
t6
t7
t8
t9
7.ꢁ
1.±
1ꢁ
1
ns
ns
ns
ns
2
CLOCK Frequency7
fCLK
ꢁ±
MHz
ꢁ± MHz grade
1ꢀ± MHz grade
2ꢀ± MHz grade
33± MHz grade
1ꢀ±
2ꢀ±
33±
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data and Control Setup6
Data and Control Hold6
CLOCK Period
t1
t2
t3
tꢀ
tꢁ
tꢀ
tꢁ
tꢀ
tꢁ
tꢀ
tꢁ
tPD
t1±
±.2
1.ꢁ
3
1.ꢀ
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
fCLK_MAX = 33± MHz
fCLK_MAX = 33± MHz
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = ꢁ± MHz
fCLK_MAX = ꢁ± MHz
1.ꢀ
1.87ꢁ
1.87ꢁ
2.8ꢁ
2.8ꢁ
8.±
8.±
1.±
1.±
ꢀ
1.±
1±
Clock cycles
ns
PSAVE Up Time6
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz and 33± MHz.
3 Timing specifications are measured with input levels of 3.± V (VIH) and ± V (VIL) for 3.3 V supplies.
ꢀ Rise time was measured from the 1±% to 9±% point of zero to full-scale transition, fall time from the 9±% to 1±% point of a full-scale transition.
ꢁ Measured from ꢁ±% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 12ꢁ MHz and ꢁ V. Limits specified here are guaranteed by characterization.
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
(R7 TO R0, G7 TO G0, B7 TO B0,
SYNC, BLANK)
t1
t6
t8
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t7
NOTES
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
Figure 2. Timing Diagram
Rev. C | Page 6 of 16
ADV7125
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VAA to GND
7 V
Voltage on Any Digital Pin
GND − ±.ꢁ V toVAA + ±.ꢁ V
Ambient Operating Temperature (TA) −ꢀ±°C to +8ꢁ°C
Storage Temperature (TS)
Junction Temperature (TJ)
−6ꢁ°C to +1ꢁ±°C
1ꢁ±°C
Lead Temperature (Soldering, 1± sec) 3±±°C
ESD CAUTION
Vapor Phase Soldering (1 Minute)
IOUT to GND1
22±°C
± V to VAA
1 Analog output short circuit to any power supply or common GND can be of
an indefinite duration.
Rev. C | Page 7 of 16
ADV7125
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GND
G0
1
2
3
4
5
6
7
8
9
36 V
REF
35 COMP
PIN 1
INDICATOR
IOR
IOR
34
33
G1
G2
32 IOG
31 IOG
G3
ADV7125
TOP VIEW
G4
30 V
29 V
AA
AA
(Not to Scale)
G5
G6
28 IOB
27 IOB
26 GND
25 GND
G7 10
BLANK 11
SYNC 12
NOTES
1. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE
CONNECTED TO GND.
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin Number
Mnemonic
Description
1, 2, 1ꢀ, 1ꢁ, 2ꢁ,
26, 39, ꢀ±
GND
Ground. All GND pins must be connected.
3 to 1±, 16 to
23, ꢀ1 to ꢀ8
G± to G7,
B± to B7,
R± to R7
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of
CLOCK. R±, G±, and B± are the least significant data bits. Unused pixel data inputs should be
connected to either the regular printed circuit board (PCB) power or ground plane.
11
BLANK
Composite Blank Control Input (TTL Compatible). A Logic ± on this control input drives the analog
outputs, IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of
CLOCK. While BLANK is a Logic ±, the R± to R7, G± to G7, and B± to B7 pixel inputs are ignored.
12
SYNC
Composite Sync Control Input (TTL Compatible). A Logic ± on the SYNC input switches off a
ꢀ± IRE current source. This is internally connected to the IOG analog output. SYNC does not override
any other control or data input; therefore, it should only be asserted during the blanking interval.
SYNC is latched on the rising edge of CLOCK. If sync information is not required on the green channel,
the SYNC input should be tied to Logic ±.
13, 29, 3±
2ꢀ
VAA
CLOCK
Analog Power Supply (ꢁ V ± ꢁ%). All VAA pins on the ADV712ꢁ must be connected.
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R± to R7, G± to G7, B± to B7, SYNC,
and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK
should be driven by a dedicated TTL buffer.
33, 31, 27
3ꢀ, 32, 28
IOR, IOG, IOB
IOR, IOG, IOB
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-3ꢀ3A and RS-17± video levels into a doubly terminated 7ꢁ Ω
load. If the complementary outputs are not required, these outputs should be tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly
driving a doubly terminated 7ꢁ Ω coaxial cable. All three current outputs should have similar output
loads whether or not they are all being used.
3ꢁ
36
COMP
VREF
Compensation Pin. This is a compensation pin for the internal reference amplifier. A ±.1 μF ceramic
capacitor must be connected between COMP and VAA
.
Voltage Reference Input for DACs or Voltage Reference Output (1.23ꢁ V).
Rev. C | Page 8 of 16
ADV7125
Pin Number
Mnemonic
Description
37
RSET
A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG)
is given by:
RSET (Ω) = 11,ꢀꢀꢁ × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by:
IOG (mA) = 11,ꢀꢀꢀ.8 × VREF (V)/RSET (Ω) (SYNC being asserted)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC
tied permanently low.
38
PSAVE
Power Save Control Pin. Reduced power consumption is available on the ADV712ꢁ when this pin is
active.
ꢀ9 (EPAD)
EP (EPAD)
The LFCSP_VQ has an exposed paddle that must be connected to GND.
Rev. C | Page 9 of 16
ADV7125
TERMINOLOGY
Raster Scan
Blanking Level
The most basic method of sweeping a CRT one line at a time to
generate and display images.
SYNC
The level separating the
portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level that shuts off the picture
tube, resulting in the blackest possible picture.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
Color Video (RGB)
The maximum positive polarity amplitude of the video signal.
This refers to the technique of combining the three primary
colors of red, green, and blue to produce color pictures within
the usual spectrum. In RGB monitors, three DACs are required,
one for each color.
Sync Level
SYNC
The peak level of the
signal.
Video Signal
SYNC
Sync Signal (
)
The portion of the composite video signal that varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that can be
visually observed.
The position of the composite video signal that synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels.
Rev. C | Page 1± of 16
ADV7125
CIRCUIT DESCRIPTION AND OPERATION
The ADV7125 contains three 8-bit DACs, with three input
channels, each containing an 8-bit register. Also integrated
on board the part is a reference amplifier. The CRT control
Table 7 details the resultant effect on the analog outputs of
BLANK SYNC
and
.
All these digital inputs are specified to accept TTL logic levels.
BLANK
functions,
ADV7125.
SYNC
and
, are integrated on board the
CLOCK INPUT
The CLOCK input of the ADV7125 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and thus the required CLOCK frequency, is determined by the
on-screen resolution, according to the following equation:
DIGITAL INPUTS
There are 24 bits of pixel data (color information), R0 to R7,
G0 to G7, and B0 to B7, latched into the device on the rising
edge of each clock cycle. This data is presented to the three 8-bit
DACs and then converted to three analog (RGB) output wave-
forms (see Figure 4).
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh
Rate)/(Retrace Factor)
where:
CLOCK
Horiz Res is the number of pixels per line.
Vert Res is the number of lines per frame.
DIGITAL INPUTS
(R7 TO R0, G7 TO G0,
DATA
Refresh Rate is the horizontal scan rate. This is the rate at which
the screen must be refreshed, typically 60 Hz for a noninterlaced
system, or 30 Hz for an interlaced system.
Retrace Factor is the total blank time factor. This takes into
account that the display is blanked for a certain fraction of the
total duration of each frame (for example, 0.8).
B7 TO B0,
SYNC, BLANK)
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG,
IOB, IOB)
Figure 4. Video Data Input/Output
The ADV7125 has two additional control signals that are latched
Therefore, for a graphics system with a 1024 × 1024 resolution,
a noninterlaced 60 Hz refresh rate, and a retrace factor of 0.8,
BLANK
to the analog video outputs in a similar fashion.
and
are each latched on the rising edge of CLOCK to maintain
synchronization with the pixel data stream.
BLANK SYNC
SYNC
Dot Rate = 1024 × 1024 × 60/0.8 = 78.6 MHz
The required CLOCK frequency is thus 78.6 MHz. All video
data and control inputs are latched into the ADV7125 on the
rising edge of CLOCK, as previously described in the Digital
Inputs section. It is recommended that the CLOCK input to the
ADV7125 be driven by a TTL buffer (for example, the 74F244).
The
and
functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK
SYNC
and
digital inputs.
Figure 5 shows the analog output, RGB video waveform of the
SYNC
BLANK
on the analog
ADV7125. The influence of
and
video waveform is illustrated.
RED AND BLUE
GREEN
mA
V
mA
V
18.67
0.7
26.0
0.975
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
0
0
7.2
0.271
0
0
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. V = 1.235V, R = 530Ω.
REF SET
3. RS-343 LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 5. Typical RGB Video Output Waveform
Rev. C | Page 11 of 16
ADV7125
Table 7. Typical Video Output Truth Table (RSET = 530 Ω, RLOAD = 37.5 Ω)
IOG (mA)
IOR/IOB (mA)
SYNC
BLANK
Video Output Level
White Level
Video
Video to BLANK
Black Level
Black to BLANK
BLANK Level
SYNC Level
IOG (mA)
IOR/IOB (mA)
DAC Input Data
±xFFH
Data
26.±
Video + 7.2
±
18.67
Video
±
1
1
±
1
±
1
±
1
1
1
1
1
±
±
18.67 − Video
18.67 − Video
18.67
18.67 − Video
18.67 − Video
18.67
Video
7.2
±
Video
Data
±
±
±
±
±x±±H
18.67
18.67
±x±±H
7.2
±
18.67
18.67
±xXXH (don’t care)
±xXXH (don’t care)
18.67
18.67
low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
VIDEO SYNCHRONIZATION AND CONTROL
SYNC
The ADV7125 has a single composite sync (
) input
control. Many graphics processors and CRT controllers have the
ability to generate horizontal sync (HSYNC), vertical sync
ANALOG OUTPUTS
SYNC
(VSYNC), and composite
In a graphics system that does not automatically generate a
SYNC
.
The ADV7125 has three analog outputs, corresponding to the
red, green, and blue video signals.
composite
signal, the inclusion of some additional logic
SYNC
The red, green, and blue analog outputs of the ADV7125 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 ꢁ load, such
as a doubly terminated 75 ꢁ coaxial cable. Figure 6 shows the
required configuration for each of the three RGB outputs
connected into a doubly terminated 75 ꢁ load. This arrangement
develops RS-343A video output voltage levels across a 75 ꢁ
monitor.
circuitry enables the generation of a composite
signal.
The sync current is internally connected directly to the IOG
output, thus encoding video synchronization information onto
the green video channel. If it is not required to encode sync
information onto the ADV7125, the
to logic low.
SYNC
input should be tied
REFERENCE INPUT
A suggested method of driving RS-170 video levels into a 75 ꢁ
monitor is shown in Figure 7. The output current levels of the
DACs remain unchanged, but the source termination resistance,
ZS, on each of the three DACs is increased from 75 ꢁ to 150 ꢁ.
IOR, IOG, IOB
The ADV7125 contains an on-board voltage reference. The VREF
pin should be connected as shown in Figure 10.
A resistance, RSET, connected between the RSET pin and GND,
determines the amplitude of the output video level according to
Equation 1 and Equation 2 for the ADV7125.
Z
= 75Ω
0
DACs
(CABLE)
IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω)
IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω)
(1)
(2)
Z
= 75Ω
S
Z
= 75Ω
L
(SOURCE
TERMINATION)
(MONITOR)
SYNC
Equation 1 applies to the ADV7125 only, when
is being
is not being encoded onto the green channel,
Equation 1 is similar to Equation 2.
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
SYNC
used. If
Figure 6. Analog Output Termination for RS-343A
Using a variable value of RSET allows for accurate adjustment of
the analog output video levels. Use of a fixed 560 ꢁ RSET resistor
yields the analog output levels quoted in the Specifications section.
These values typically correspond to the RS-343A video wave-
form values, as shown in Figure 5.
IOR, IOG, IOB
Z
= 75Ω
0
DACs
Z
(CABLE)
= 150Ω
(SOURCE
TERMINATION)
S
Z
= 75Ω
L
(MONITOR)
DACS
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN, AND BLUE DACs
The ADV7125 contains three matched 8-bit DACs. The DACs
are designed using an advanced, high speed, segmented architec-
ture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = 1) or GND (bit = 0)
by a sophisticated decoding scheme. Because all this circuitry
is on one monolithic device, matching between the three DACs
is optimized. As well as matching, the use of identical current
sources in a monolithic design guarantees monotonicity and
Figure 7. Analog Output Termination for RS-170
More detailed information regarding load terminations for
various output configurations, including RS-343A and RS-170,
is available in the AN-205 Application Note, Video Formats and
Required Load Terminations, available from Analog Devices at
www.analog.com.
Rev. C | Page 12 of 16
ADV7125
Z
Z
1
2
Figure 5 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 ꢁ load of
Figure 6. As well as the gray scale levels (black level to white
+V
4
0.1µF
S
2
3
Z
= 75Ω
0
75Ω
IOR, IOG, IOB
DACs
SYNC
level), Figure 5 also shows the contributions of
and
AD848
7
BLANK
for the ADV7125. These control inputs add appro-
(CABLE)
Z
= 75Ω
0.1µF
6
L
(MONITOR)
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
Z
= 75Ω
S
–V
S
(SOURCE
TERMINATION)
Z
1
GAIN (G) = 1 +
SYNC
BLANK
Table 7 details how the
output levels.
and
inputs modify the
Z
2
Figure 9. AD848 As an Output Buffer
GRAY SCALE OPERATION
PCB LAYOUT CONSIDERATIONS
The ADV7125 can be used for standalone, gray scale (mono-
chrome) or composite video applications (that is, only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to Logic 0. The
unused analog outputs should be terminated with the same load
as that for the used channel, that is, if the red channel is used
and IOR is terminated with a doubly terminated 75 ꢁ load
(37.5 ꢁ), IOB and IOG should be terminated with 37.5 ꢁ
resistors (see Figure 8).
The ADV7125 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7125, it is imperative
that great care be given to the PCB layout. Figure 10 shows a
recommended connection diagram for the ADV7125.
The layout should be optimized for lowest noise on the
ADV7125 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
to minimize inductive ringing.
DOUBLY
R0
R7
IOR
IOG
TERMINATED
VIDEO
OUTPUT
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 10). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each VAA pin to ground by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7125
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3-
terminal voltage regulator.
75Ω LOAD
37.5Ω
37.5Ω
ADV7125
G0
G7
IOB
B0
B7
GND
Figure 8. Input and Output Connections for Standalone Gray Scale or
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7125 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in the
Analog Outputs section and illustrated in Figure 9. However,
in some applications, it may be required to drive long transmis-
sion line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD843, AD844, AD847,
and AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7125 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7125 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (VCC) and not to the
analog power plane.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Rev. C | Page 13 of 16
ADV7125
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 ꢁ (doubly
terminated 75 ꢁ configuration). This termination resistance
should be as close as possible to the ADV7125 to minimize
reflections.
ANALOG SIGNAL INTERCONNECT
Place the ADV7125 as close as possible to the output connectors,
thus minimizing noise pickup and reflections due to impedance
mismatch.
The video output signals should overlay the ground plane and
not the analog power plane, thereby maximizing the high
frequency power supply rejection.
Additional information on PCB design is available in the
AN-333 Application Note, Design and Layout of a Video
Graphics System for Reduced EMI, which is available from
Analog Devices at www.analog.com.
POWER SUPPLY DECOUPLING
(0.1µF AND 0.01µF CAPACITOR
FOR EACH V GROUP
)
AA
0.1µF
0.01µF
13, 29,
30
0.1µF
COMP
V
AA
35
V
V
AA
AA
V
AA
41 TO 48
3 TO 10
1kΩ
1µF
36
37
V
REF
R7 TO R0
1
AD1580
2
R
SET
R
VIDEO
DATA
INPUTS
SET
530Ω
MONITOR (CRT)
COAXIAL CABLE
G7 TO G0
75Ω
34
32
28
IOR
IOG
16 TO 23
75Ω
75Ω
75Ω
B7 TO B0
ADV7125
IOB
75Ω
75Ω
75Ω
BNC
CONNECTORS
SYNC
12
11
24
38
33
31
IOR
IOG
BLANK
CLOCK
PSAVE
COMPLEMENTARY
OUTPUTS
IOB 27
GND
1, 2, 14, 15,
25, 26, 39, 40
Figure 10. Typical Connection Diagram
Rev. C | Page 1ꢀ of 16
ADV7125
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
25
12
0.15
0.05
13
24
SEATING
PLANE
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 11. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
EXPOSED
5.25
5.10 SQ
4.95
TOP
VIEW
6.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
SECTION OF THIS DATA SHEET.
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 12. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
Rev. C | Page 1ꢁ of 16
ADV7125
ORDERING GUIDE
Model1, 2, 3
ADV712ꢁKSTZꢁ±
ADV712ꢁKSTZꢁ±-REEL
ADV712ꢁKSTZ1ꢀ±
ADV712ꢁJSTZ2ꢀ±
Temperature Range
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
±°C to +7±°C
Package Description
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LQFP
ꢀ8-Lead LFCSP_VQ
ꢀ8-Lead LFCSP_VQ
ꢀ8-Lead LFCSP_VQ
ꢀ8-Lead LFCSP_VQ
Speed Option
ꢁ± MHz
ꢁ± MHz
Package Option
ST-ꢀ8
ST-ꢀ8
ST-ꢀ8
ST-ꢀ8
ST-ꢀ8
ST-ꢀ8
ST-ꢀ8
CP-ꢀ8-1
CP-ꢀ8-1
CP-ꢀ8-1
CP-ꢀ8-1
1ꢀ± MHz
2ꢀ± MHz
33± MHz
17± MHz
17± MHz
17± MHz
17± MHz
17± MHz
17± MHz
ADV712ꢁJSTZ33±
±°C to +7±°C
ADV712ꢁWBSTZ17±
ADV712ꢁWBSTZ17±-RL
ADV712ꢁBCPZ17±
ADV712ꢁBCPZ17±-RL
ADV712ꢁWBCPZ17±
ADV712ꢁWBCPZ17±-RL
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
−ꢀ±°C to +8ꢁ°C
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 ADV712ꢁJSTZ33± is available in a 3.3 V option only.
AUTOMOTIVE PRODUCTS
The ADV7125W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03097-0-2/11(C)
Rev. C | Page 16 of 16
相关型号：
ADV7127JR240-REEL
IC PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28, Digital to Analog Converter
ADI
©2020 ICPDF网 联系我们和版权申明