ADV7127JR240-REEL [ADI]
IC PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28, Digital to Analog Converter;
| 型号： | ADV7127JR240-REEL |
| 厂家： | 
ADI |
| 描述： | IC PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PDSO28, SOIC-28, Digital to Analog Converter 输入元件 光电二极管 转换器 |
| 文件： | 总16页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS, 240 MHz
a
10-Bit High Speed Video DAC
ADV7127
FEATURES
FUNCTIONAL BLOCK DIAGRAM
240 MSPS Throughput Rate
10-Bit D/A Converters
V
AA
SFDR
–70 dB typ: fCLK = 50 MHz; fOUT = 1 MHz
–53 dB typ: fCLK = 140 MHz; fOUT = 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
10
I
OUT
DATA
REGISTER
10
D9–D0
DAC
I
OUT
DAC Output Current Range: 2 mA to 26 mA
TTL Compatible Inputs
PDOWN*
PSAVE
CLOCK
POWER–
DOWN
MODE
VOLTAGE*
REFERENCE
CIRCUIT
V
REF
Internal Voltage Reference (1.23 V) on TSSOP Package
Single Supply +5 V/+3.3 V Operation
28-Lead SOIC Package and 24-Lead TSSOP Package
Low Power Dissipation (30 mW min @ 3 V)
Low Power Standby Mode (10 mW min @ 3 V)
Power-Down Mode (60 mW min @ 3 V)
Power-Down Mode Available on TSSOP Package
Industrial Temperature Range (–40؇C to +85؇C)
ADV7127
GND
R
SET
COMP
*ON TSSOP VERSION ONLY
APPLICATIONS
Digital Video Systems (1600
؋
1200 @ 100 Hz) High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
Direct Digital Synthesis (DDS)
Wireless LAN
The ADV7127 TSSOP package also has a power-down mode.
Both ADV7127 packages have a power standby mode.
GENERAL DESCRIPTION
The ADV7127 (ADV®) is a high speed, digital-to-analog con-
vertor on a single monolithic chip. It consists of a 10-bit,
video D/A converter with on-board voltage reference, comple-
mentary outputs, a standard TTL input interface and high
impedance analog output current sources.
The ADV7127 TSSOP package has an on-board voltage refer-
ence circuit. The ADV7127 SOIC package requires an external
reference.
PRODUCT HIGHLIGHTS
1. 240 MSPS Throughput.
The ADV7127 has a 10-bit wide input port. A single +5 V/
+3.3 V power supply and clock are all that are required to make
the part functional.
2. Guaranteed monotonic to 10 bits.
The ADV7127 is fabricated in a CMOS process. Its monolithic
CMOS construction ensures greater functionality with lower
power dissipation. The ADV7127 is available in a small outline
28-lead SOIC or 24-lead TSSOP package.
3. Compatible with a wide variety of high resolution color
graphics systems including RS-343A and RS-170A.
ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADV7127–SPECIFICATIONS
1
(VAA = +5 V ؎ 5%, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX unless
otherwise noted, TJ MAX = 110؇C)
5 V SOIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1
–1
Bits
LSB
LSB
0.4
0.25
+1
+1
Guaranteed Monotonic
VIN = 0.0 V or VAA
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2
V
V
µA
µA
pF
0.8
+1
–1
20
10
ANALOG OUTPUTS
Output Current
2.0
0
18.5
+1.4
mA
V
kΩ
pF
% FSR
% FSR
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
100
10
IOUT = 0 mA
Tested with DAC Output = 0 V
FSR = 17.62 mA
–0.025
–5.0
+0.025
+5.0
Gain Error2
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current3
Digital Supply Current3
Digital Supply Current3
Analog Supply Current
Analog Supply Current
Standby Supply Current4
3.4
10.5
18
33
5
9
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
15
25
37
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital and Control
Inputs at VAA
2.1
5.0
0.5
Power Supply Rejection Ratio
0.1
%/%
NOTES
1Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
2Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
3Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
4These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range.
.
Specifications subject to change without notice.
–2–
REV. 0
ADV7127
1
REF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX unless
5 V TSSOP SPECIFICATIONS(oVthe=rw+is5eVno؎te5d%, T,J VMAX = 110؇C)
AA
Parameter
Min
Typ
Max
Units
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
–1
–1
Bits
LSB
LSB
0.4
0.25
+1
+1
Guaranteed Monotonic
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
2
V
V
V
V
µA
µA
µA
pF
Input Low Voltage, VIL
0.8
+1
PDOWN Input High Voltage2
PDOWN Input Low Voltage2
Input Current, IIN
3
1
–1
VIN = 0.0 V or VAA
PSAVE Pull-Up Current
PDOWN Pull-Up Current
Input Capacitance, CIN
20
20
10
ANALOG OUTPUTS
Output Current
2.0
0
18.5
+1.4
mA
V
kΩ
pF
% FSR
% FSR
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
100
10
IOUT = 0 mA
Tested with DAC Output = 0 V
FSR = 17.62 mA
–0.025
–5.0
+0.025
+5.0
Gain Error3
VOLTAGE REFERENCE (Ext. and Int.)4
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current5
Digital Supply Current5
Digital Supply Current5
Analog Supply Current
Analog Supply Current
Standby Supply Current6
1.5
4
6.5
23
5
3
6
10
27
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital and Control
Inputs at VAA
3.8
6
PDOWN Supply Current2
1
mA
Power Supply Rejection Ratio
0.1
0.5
%/%
NOTES
1Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
2This power-down feature is only available on the ADV7127 in the TSSOP package.
3Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH ) and K = 7.9896.
4Internal voltage reference is available only on the ADV7127 TSSOP package.
5Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
6These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range.
.
Specifications subject to change without notice.
REV. 0
–3–
ADV7127–SPECIFICATIONS
2
(VAA = +3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX
3.3 V SOIC SPECIFICATIONS1 unless otherwise noted, TJ MAX = 110؇C)
Parameter
Min
Typ
Max
Units
Test Conditions
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
+1
+1
Bits
LSB
LSB
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
–1
–1
0.5
0.25
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
2.0
–1
V
V
µA
µA
pF
0.8
+1
VIN = 0.0 V or VDD
20
10
ANALOG OUTPUTS
Output Current
2.0
0
18.5
+1.4
mA
V
kΩ
pF
% FSR
% FSR
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
70
10
0
0
Tested with DAC Output = 0 V
FSR = 17.62 mA
Gain Error3
0
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
1.12
1.235
1.35
V
POWER DISSIPATION
Digital Supply Current4
Digital Supply Current4
Digital Supply Current4
Analog Supply Current
Analog Supply Current
Standby Supply Current
2.2
6.5
11
32
5
5.0
12.0
15
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital and Control
Inputs at VDD
35
2.4
5.0
0.5
Power Supply Rejection Ratio
0.1
%/%
NOTES
1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100) , where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
Specifications subject to change without notice.
.
–4–
REV. 0
ADV7127
2
(VAA = +3.0 V–3.6 V, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX
unless otherwise noted, TJ MAX = 110؇C)
3.3 V TSSOP SPECIFICATIONS1
Parameter
Min
Typ
Max
Units
Test Conditions
RSET = 680 Ω
RSET = 680 Ω
RSET = 680 Ω
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
10
+1
+1
Bits
LSB
LSB
–1
–1
0.5
0.25
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
2.0
V
V
V
V
µA
µA
pF
Input Low Voltage, VIL
0.8
2.1
0.6
PDOWN Input High Voltage3
PDOWN Input Low Voltage3
Input Current, IIN
–1
+1
VIN = 0.0 V or VDD
PSAVE Pull-Up Current
Input Capacitance, CIN
20
10
ANALOG OUTPUTS
Output Current
2.0
0
18.5
+1.4
mA
V
kΩ
pF
% FSR
% FSR
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
70
10
0
0
Tested with DAC Output = 0 V
FSR = 17.62 mA
Gain Error4
0
VOLTAGE REFERENCE (Ext.)
Reference Range, VREF
VOLTAGE REFERENCE (Int.)5
Reference Range, VREF
1.12
1.235
1.235
1.35
V
V
POWER DISSIPATION
Digital Supply Current6
Digital Supply Current6
Digital Supply Current6
Analog Supply Current
Analog Supply Current
Standby Supply Current
1
2.5
4
22
5
2
4.5
6
25
mA
mA
mA
mA
mA
mA
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = Low, Digital and Control
Inputs at VDD
2.6
3
PDOWN Supply Current
Power Supply Rejection Ratio
20
0.1
µA
%/%
0.5
NOTES
1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
3This power-down feature is only available on the ADV7127 in the TSSOP package.
4Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = VREF /RSET × K × (3FFH) and K = 7.9896.
5Internal voltage reference is available only on the ADV7127 TSSOP package.
6Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD
Specifications subject to change without notice.
.
REV. 0
–5–
ADV7127–SPECIFICATIONS
(VAA = (3 V–5.25 V)1, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications
are for T = +25؇C unless otherwise noted, TJ MAX = 110؇C)
5 V/3.3 V DYNAMIC SPECIFICATIONS
A
Parameter
Min
Typ
Max
Units
DAC PERFORMANCE
Glitch Impulse2, 3
10
22
33
pVs
dB
dB
Data Feedthrough2, 3
Clock Feedthrough2, 3
NOTES
1These max/min specifications are guaranteed by characterization.
2TTL input values are for 0 V and 3 V with input rise/fall times ≤3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
3Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
Specifications subject to change without notice.
3
(VAA = +5 V ؎ 5%2, VREF = 1.235 V, RSET = 560 ⍀, CL = 10 pF. All specifications TMIN to TMAX
5 V TIMING SPECIFICATIONS1 unless otherwise noted, TJ MAX = 110؇C)
Parameter
Min
Typ
Max
Units
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
5.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
0.5
0.5
0.5
50
140
240
MHz
MHz
MHz
50 MHz Grade
140 MHz Grade
240 MHz Grade
7
fCLK
7
fCLK
Data and Control Setup, t1
Data and Control Hold, t2
Clock Pulsewidth High, t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
Clock Pulsewidth High t4
Clock Pulsewidth Low t5
1.5
2.5
1.875
1.875
2.85
2.85
8.0
ns
ns
ns
ns
ns
ns
ns
ns
1.1
1.25
fMAX = 240 MHz
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 140 MHz
fMAX = 50 MHz
fMAX = 50 MHz
8.0
1.0
6
Pipeline Delay, tPD
PSAVE Up Time, t10
1.0
2
320
1.0
10
Clock Cycles
ns
ns
6
8
PDOWN Up Time, t11
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
8This power-down feature is only available on the ADV7127 in the TSSOP package.
Specifications subject to change without notice.
–6–
REV. 0
ADV7127
(VAA = +3.0 V–3.6 V2, VREF = 1.235 V, RSET = 560 ⍀. All specifications TMIN to TMAX3 unless
3.3 V TIMING SPECIFICATIONS1 otherwise noted, TJ MAX = 110؇C)
Parameter
Min
Typ
Max
Units
Condition
ANALOG OUTPUTS
Analog Output Delay, t6
Analog Output Rise/Fall Time, t7
7.5
1.0
15
1
ns
ns
ns
ns
4
5
Analog Output Transition Time, t8
6
Analog Output Skew, t9
2
CLOCK CONTROL
7
fCLK
50
140
240
MHz
MHz
MHz
ns
50 MHz Grade
140 MHz Grade
240 MHz Grade
7
fCLK
7
fCLK
Data and Control Setup, t26
1.5
2.5
6
Data and Control Hold, t2
ns
Clock Pulsewidth High, t4
1.1
1.4
ns
ns
ns
ns
ns
ns
fMAX = 240 MHz
fMAX = 240 MHz
fMAX = 140 MHz
fMAX = 140 MHz
fMAX = 50 MHz
fMAX = 50 MHz
6
Clock Pulsewidth Low t5
6
Clock Pulsewidth High t4
2.85
2.85
8.0
8.0
1.0
6
Clock Pulsewidth Low t5
6
Clock Pulsewidth High t4
6
Clock Pulsewidth Low t5
6
Pipeline Delay, tPD
PSAVE Up Time, t10
1.0
4
320
1.0
10
Clock Cycles
ns
ns
6
8
PDOWN Up Time, t11
NOTES
1Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
2These maximum and minimum specifications are guaranteed over this range.
3Temperature range: TMIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz.
4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5Measured from 50% point of full-scale transition to 2% of final value.
6Guaranteed by characterization.
7fCLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization.
8This power-down feature is only available on the ADV7127 in the TSSOP package.
Specifications subject to change without notice.
t3
t4
t5
CLOCK
t2
DIGITAL INPUTS
DATA
(D9–D0)
t1
t8
t6
ANALOG OUTPUTS
(I
, I )
OUT
OUT
t7
NOTES:
1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL
SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
Figure 1. Timing Diagram
REV. 0
–7–
ADV7127
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATIONS
24-Lead TSSOP 28-Lead SOIC
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on any Digital Pin . . . . . GND – 0.5 V to VAA + 0.5 V
Ambient Operating Temperature (TA) . . . . . –40°C to +85°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Vapor Phase Soldering (1 Minute) . . . . . . . . . . . . . . . . 220°C
IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
V
V
V
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
AA
AA
D0
1
2
3
4
5
6
7
8
9
24
23
22
21
D0
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
D8
D9
AA
PSAVE
PSAVE
R
R
SET
SET
V
V
REF
REF
20 COMP
COMP
NOTES
ADV7127
ADV7127
TOP VIEW
(Not to Scale)
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
19
18
17
V
I
I
AA
OUT
TOP VIEW
(Not to Scale)
I
OUT
OUT
V
V
AA
AA
16 GND
15 GND
14
D8 10
GND
V
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
D9
AA 10
11
12
13
14
18 GND
17 CLOCK
V
11
V
V
V
CLOCK
PDOWN
AA
AA
AA
NC
12
13 NC
16
15
AA
AA
V
NC = NO CONNECT
ORDERING GUIDE1
Speed Options
Package
50 MHz
140 MHz
240 MHz
R-282
ADV7127KR50
ADV7127KRU50
ADV7127KR140
ADV7127KRU140
ADV7127JR240
ADV7127JRU240
RU-243
NOTES
150 MHz and 140 MHz devices are specified for –40°C to +85°C operation; 240 MHz devices are specified for 0°C to +70°C.
2SOIC Package.
3TSSOP Package.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7127 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–8–
REV. 0
ADV7127
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
CLOCK
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
D0–D9
IOUT
Data Inputs (TTL Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs should be connected to either the regular PCB power or ground plane.
Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω
coaxial cable.
RSET
Full-Scale Adjust Control. A resistor (RSET) connected between this pin and GND controls the magnitude of the
full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current.
The relationship between RSET and the full-scale output current on IOUT is given by:
I
OUT (mA) = 7968 × VREF(V)/RSET(Ω)
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor
must be connected between COMP and VAA
COMP
VREF
.
Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an exter-
nal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected
between VREF and VAA
.
VAA
Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7127 must be connected.
GND
IOUT
Ground. All GND pins must be connected.
Differential Current Output. Capable of directly driving a doubly terminated 75 Ω load. If not required, this out-
put should be tied to ground.
PSAVE
Power Save Control Pin. The part is put into standby mode when PSAVE is low. The internal voltage reference
circuit is still active on the TSSOP in this case.
PDOWN
Power-Down Control Pin (24-Lead TSSOP Only). The ADV7127 completely powers down, including the voltage
reference circuit, when PDOWN is low.
Reference Black Level
TERMINOLOGY
The maximum negative polarity amplitude of the video signal.
Color Video (RGB)
This usually refers to the technique of combining the three
primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Reference White Level
The maximum positive polarity amplitude of the video signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion that may be
visually observed.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. A 10-bit DAC contains 1024 different
levels, while an 8-bit DAC contains 256.
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
REV. 0
–9–
ADV7127
5 V–Typical Performance Characteristics
(VAA = +5 V, VREF = 1.235 V, IOUT = 17.62 A, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = +25؇C)
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
72.2
72.0
71.8
71.6
71.4
71.2
71.0
70.8
SFDR (DE)
SFDR (DE)
SFDR (SE)
SFDR (SE)
70.6
70.4
0.1
1.0
2.51
5.04 20.2 40.4
100
0.1
1.0
2.51
5.04
20.2
40.4 100
–10
+25
+85
FREQUENCY – MHz
FREQUENCY – MHz
TEMPERATURE – ؇C
Figure 3. SFDR vs. fOUT @ fCLOCK
50 MHz (Single-Ended and
Differential)
=
Figure 4. SFDR vs. Temperature @
Figure 2. SFDR vs. fOUT @ fCLOCK
140 MHz (Single-Ended and
Differential)
=
f
CLOCK = 50 MHz (fOUT = 1 MHz)
1.00
0.50
0.00
76
1.0
0.9
0.8
0.7
74
0.75
2nd HARMONIC
72
3rd HARMONIC
70
68
66
64
62
60
58
4th HARMONIC
0.6
LINEARITY vs. I
ERROR
OUT
1023
0.5
0.4
0.3
0.2
0.1
0.0
–0.16
–0.50
–1.00
0
50
f
100
– MHz
140
160
CODE – INL
0
2
17.62
20
I
/mA
OUT
CLOCK
Figure 6. Linearity vs. IOUT
Figure 7. Typical Linearity
Figure 5. THD vs. fCLOCK @ fOUT
=
2 MHz (2nd, 3rd and 4th Harmonics)
–5.0
–5.0
–5.0
2
2
2
V
= 5V
AA
V
= 5V
V
= 5V
CLK = 140MHz
DUAL TONE
DIFF O/P
CLK = 140MHz
= 20MHz
SING O/P
AA
AA
CLK = 140MHz
= 2.5MHz
SING O/P
f
OUT
f
OUT
–45.0
–85.0
–45.0
–85.0
–45.0
–85.0
1
1
1
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 8. SFDR (Single-Tone) @
CLOCK = 140 MHz (fOUT1 = 2 MHz)
Figure 9. Single-Tone SFDR @ fCLOCK
= 140 MHz (fOUT1 = 20 MHz)
Figure 10. Dual-Tone SFDR @ fCLOCK
f
= 140 MHz (fOUT1 = 13.5 MHz, fOUT2
14.5 MHz)
=
–10–
REV. 0
ADV7127
3 V–Typical Performance Characteristics
(VAA = +3 V, VREF = 1.235 V, IOUT =17.62 A, 50 ⍀ Doubly Terminated Load, Differential Output Loading, TA = +25؇C)
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
72.0
71.8
71.6
71.4
71.2
71.0
70.8
70.6
70.4
SFDR (DE)
SFDR (SE)
SFDR (DE)
SFDR (f
= 1MHz)
OUT
SFDR (SE)
0.1
2.51
5.04
20.2 40.4
100
0
20
85
145
165
0.1
1.0
2.51 5.04
20.2
40.4
100
FREQUENCY – MHz
FREQUENCY – MHz
TEMPERATURE – ؇C
Figure 11. SFDR vs. fOUT @ fCLOCK
140 MHz (Single-Ended and
Differential)
=
Figure 12. SFDR vs. fOUT @ fCLOCK
50 MHz (Single-Ended and
Differential)
=
Figure 13. SFDR vs. Temperature @
f
CLOCK = 50 MHz, (fOUT = 1 MHz)
76
1.00
0.50
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2nd HARMONIC
74
0.75
4th HARMONIC
72
70
3rd HARMONIC
68
1023
0.00
66
64
62
60
58
56
–0.42
–0.50
–1.00
0
50
100
140
160
0
2
17.62
– mA
20
CODE– INL
I
FREQUENCY – MHz
OUT
Figure 14. THD vs. fCLOCK @ fOUT
2 MHz (2nd, 3rd and 4th Harmonics)
=
Figure 16. Typical Linearity
Figure 15. Linearity vs. IOUT
–5.0
–5.0
–5.0
2
2
2
V
= 3.3V
V
= 3.3V
V
= 3.3V
CLK = 140MHz
= 20MHz
SING O/P
AA
AA
CLK = 140MHz
AA
CLK = 140MHz
= 2.5MHz
SING O/P
f
DUAL TONE
SING O/P
OUT
f
OUT
–45.0
–85.0
–45.0
–85.0
–45.0
–85.0
1
1
1
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
0kHz
START
35.0MHz
70.0MHz
STOP
Figure 17. Single-Tone SFDR @
CLOCK = 140 MHz (fOUT1 = 2 MHz)
Figure 18. Single-Tone SFDR @
CLOCK = 140 MHz (fOUT1 = 20 MHz)
Figure 19. Dual-Tone SFDR @ fCLOCK
f
f
= 140 MHz (fOUT1 = 13.5 MHz, fOUT2
14.5 MHz)
=
REV. 0
–11–
ADV7127
CIRCUIT DESCRIPTION AND OPERATION
The ADV7127 contains one 10-bit D/A converter, with one
input channel containing a 10-bit register. A reference amplifier
is also integrated on board the part.
All video data and control inputs are latched into the ADV7127
on the rising edge of CLOCK, as previously described in the
Digital Inputs section. It is recommended that the CLOCK
input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).
Digital Inputs
I
OUT
Ten bits of data (color information) D0–D9 are latched into the
device on the rising edge of each clock cycle. This data is pre-
sented to the 10-bit DAC and is then converted to an analog
output waveform. See Figure 20.
mA
V
WHITE
LEVEL
17.61
0.66
CLOCK
100 IRE
DIGITAL INPUTS
DATA
BLACK
LEVEL
D0–D9
0
0
Figure 21. IOUT Video Output Waveform
ANALOG OUTPUTS
I
, I
OUT
OUT
Table I. Video Output Truth Table (RSET = 560 ⍀,
LOAD = 37.5 ⍀)
R
Figure 20. Video Data Input/Output
Description
Data
DAC
Input
All these digital inputs are specified to accept TTL logic levels.
IOUT
IOUT
Clock Input
The CLOCK input of the ADV7127 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following equation:
WHITE LEVEL
VIDEO
BLACK LEVEL
17.62
Video
0
0
3FF
17.62 – Video Data
17.62 000H
Power Management
Dot Rate = (Horiz Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
The PSAVE input of the ADV7127 puts the part into standby
mode. It is used to reduce power consumption. When PSAVE
is low, the power may be reduced to approximately 10 mW at
3 V. The ADV7127 in TSSOP package also has a power-down
feature where the entire part, including the voltage reference
circuit, is powered down. In this case, power on the ADV7127
can be reduced to 60 µW at 3 V.
Horiz Res
Vert Res
= Number of Pixels/Line.
= Number of Lines/Frame.
Refresh Rate
= Horizontal Scan Rate. This is the rate at
which the screen must be refreshed, typically
60 Hz for a noninterlaced system or 30 Hz
for an interlaced system.
Table II. Power Management
Retrace Factor = Total Blank Time Factor. This takes into
account that the display is blanked for a
certain fraction of the total duration of each
frame (e.g., 0.8).
Mode
ADV7127 TSSOP
ADV7127 SOIC
Power-Save 10 mW Typically at 3 V 10 mW Typically at 3 V
Power-Down Power 60 µW at 3 V
Not Available
Therefore, if we have a graphics system with
a 1024 × 1024 resolution, a noninterlaced
60 Hz refresh rate and a retrace factor of 0.8,
then:
Reference Input
The ADV7127 has an on-board voltage reference. The VREF
pin is normally terminated to VAA through a 0.1 µF capacitor.
Alternatively, the part could, if required, be overdriven by an
external 1.23 V reference (AD1580).
Dot Rate
= 1024 × 1024 × 60/0.8
= 78.6 MHz
A resistance RSET connected between the RSET pin and GND
determines the amplitude of the output video level according to
the following equation:
The required CLOCK frequency is thus 78.6 MHz.
IOUT (mA) = 7,968 × VREF(V)/RSET(Ω)
(1)
Using a variable value of RSET, as shown in Figure 22, allows
for accurate adjustment of the analog output video levels. Use
of a fixed 560 Ω RSET resistor yields the analog output levels
as quoted in the specification page. These values typically
correspond to the RS-343A video waveform values as shown in
Figure 21.
–12–
REV. 0
ADV7127
D/A Converter
Video Output Buffer
The ADV7127 contains a 10-bit D/A converter. The DAC is
designed using an advanced, high speed, segmented architec-
ture. The bit currents corresponding to each digital input are
routed to either the analog output (bit = “1”) or GND (bit =
“0”) by a sophisticated decoding scheme. The use of identical
current sources in a monolithic design guarantees monotonicity
and low glitch. The on-board operational amplifier stabilizes the
full-scale output current against temperature and power supply
variations.
The ADV7127 is specified to drive transmission line loads,
which is what most monitors are rated as. The analog output
configurations to drive such loads are described in the Analog
Interface section and illustrated in Figure 23. However, in some
applications it may be required to drive long “transmission line”
cable lengths. Cable lengths greater than 10 meters can attenu-
ate and distort high frequency analog output pulses. The inclu-
sion of output buffers will compensate for some cable distortion.
Buffers with large full power bandwidths and gains between two
and four will be required. These buffers will also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD84x series of monolithic
op amps. In very high frequency applications (80 MHz), the
AD9617 is recommended. More information on line driver
buffering circuits is given in the relevant op amp data sheets.
Analog Output
The analog output of the ADV7127 is a high impedance current
source. The current output is capable of directly driving a
37.5 Ω load, such as a doubly terminated 75 Ω coaxial cable.
Figure 22 shows the required configuration for the output con-
nected into a doubly terminated 75 Ω load. This arrangement
will develop RS-343A video output voltage levels across a 75 Ω
monitor.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired
video level.
I
OUT
Z
= 75⍀
O
DAC
Z
(SOURCE
TERMINATION)
(CABLE)
= 75⍀
S
Z
= 75⍀
Z
Z
1
L
2
(MONITOR)
+V
0.1F
S
Z
= 75⍀
O
I
75⍀
OUT
AD848
Figure 22. Analog Output Termination for RS-343A
(CABLE)
DAC
= 75⍀
(SOURCE
TERMINATION)
Z = 75⍀
L
(MONITOR)
0.1F
A suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 23. The output current level of the
DAC remains unchanged, but the source termination resistance,
ZS, on the DAC is increased from 75 Ω to 150 Ω.
Z
S
–V
S
Z
Z
1
2
GAIN (G) = 1 +
Figure 24. AD848 As an Output Buffer
PC Board Layout Considerations
I
OUT
Z
= 75⍀
O
The ADV7127 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7127 it is imperative
that great care be given to the PC board layout. Figure 25 shows
a recommended connection diagram for the ADV7127.
DAC
(CABLE)
Z
= 150⍀
S
Z
= 75⍀
L
(SOURCE
TERMINATION)
(MONITOR)
The layout should be optimized for lowest noise on the ADV7127
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should be minimized to
inductive ringing.
Figure 23. Analog Output Termination for RS-170
More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an Application Note entitled “Video Formats &
Required Load Terminations” available from Analog Devices,
publication no. E1228-15-1/89.
Ground Planes
The ADV7127 and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 25. This bead should be located as close as possible
(within 3 inches) to the ADV7127.
Figure 21 shows the video waveforms associated with the current
output driving the doubly terminated 75 Ω load of Figure 22.
Gray Scale Operation
The ADV7127 can be used for stand-alone, gray scale (mono-
chrome) or composite video applications (i.e., only one channel
used for video information).
The analog ground plane should encompass all ADV7127
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces and any output amplifiers.
The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7127.
REV. 0
–13–
ADV7127
Power Planes
Supply Decoupling
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7127 (VAA) and all
associated analog circuitry. This power plane should be con-
nected to the regular PCB power plane (VCC) at a single point
through a ferrite bead, as illustrated in Figure 25. This bead
should be located within three inches of the ADV7127.
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors (see Figure 25).
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individually
decoupled to ground. This should be done by placing the ca-
pacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV7127 contains cir-
cuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power sup-
ply noise. A dc power supply filter (Murata BNX002) will pro-
vide EMI suppression between the switching power supply and
the main PCB. Alternatively, consideration could be given to
using a three terminal voltage regulator.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7127 power pins, voltage reference circuitry
and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
COMP
C6
0.1F
ANALOG POWER PLANE
V
AA
ADV7127
C4
0.1F
C5
0.1F
L1 (FERRITE BEAD)
C3
0.1F
+5V (V
)
CC
V
REF
VIDEO
DATA
INPUTS
C2
10F
C1
33F
D0
D9
ANALOG GROUND PLANE
GROUND
GND
L2 (FERRITE BEAD)
R
SET
R1
75⍀
PDOWN
PSAVE
CLOCK
560⍀
R
SET
VIDEO
OUTPUT
I
OUT
COMPONENT
DESCRIPTION
VENDOR PART NUMBER
C1
33F TANTALUM CAPACITOR
10F TANTALUM
C2
C3, C4, C5, C6
L1, L2
0.1F CERAMIC CAPACITOR
FERRITE BEAD
FAIR-RITE 274300111 OR MURATA BL01/02/03
R1
75⍀ 1% METAL FILM RESISTOR DALE CMF-55C
560⍀ 1% METAL FILM RESISTOR DALE CMF-55C
R
SET
Figure 25. Typical Connection Diagram and Component List
–14–
REV. 0
ADV7127
Digital Signal Interconnect
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.
The digital signal lines to the ADV7127 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.
For optimum performance, the analog outputs should each
have a source termination resistance to ground of 75 Ω (doubly
terminated 75 Ω configuration). This termination resistance
should be as close as possible to the ADV7127 so as to mini-
mize reflections.
Due to the high clock rates used, long clock lines to the ADV7127
should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC), and
not the analog power plane.
Additional information on PCB design is available in an applica-
tion note entitled “Design and Layout of a Video Graphics
System for Reduced EMI.” This application note is available
from Analog Devices, publication number E1309-15-10/89.
Analog Signal Interconnect
The ADV7127 should be located as close as possible to the
output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
REV. 0
–15–
ADV7127
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
14
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
24-Lead TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
12
1
0.006 (0.15)
0.002 (0.05)
PIN 1
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
0.0075 (0.19)
REV. 0
–16–
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