ADV7171KSZ-REEL_技术文档

Digital PAL/NTSC Video Encoder with 10-Bit

SSAF™ and Advanced Power Management

ADV7170/ADV7171

Programmable LUMA delay

Individual on/off control of each DAC

CCIR and square pixel operation

FEATURES

ITU-R¹BT601/656 YCrCb to PAL/NTSC video encoder

High quality 10-bit video DACs

Integrated subcarrier locking to external video source

Color signal control/burst signal control

Interlaced/noninterlaced operation

Complete on-chip video timing generator

Programmable multimode master/slave operation

Macrovision® AntiTaping Rev. 7.1 (ADV7170 only)³

Closed captioning support

Teletext insertion port (PAL-WST)

On-board color bar generation

On-board voltage reference

2-wire serial MPU interface (I²C®-compatible and Fast I²C)

Single supply 5 V or 3.3 V operation

SSAF (super sub-alias filter)

Advanced power management features

CGMS (copy generation management system)

WSS (wide screen signalling)

Simultaneous Y, U, V, C output format

NTSC M, PAL M/N², PAL B/D/G/H/I, PAL60

Single 27 MHz clock required (×2 oversampling)

80 dB video SNR

32-bit direct digital synthesizer for color subcarrier

Multistandard video output support

Composite (CVBS)

Components S-Video (Y/C), YUV, and RGB

EuroSCART output (RGB + CVBS/LUMA)

Component YUV + CHROMA

Small 44-lead MQFP/TQFP packages

Industrial temperature grade = −40°C to +85°C⁴

APPLICATIONS

Video input data port supports

CCIR-656 4:2:2 8-bit parallel input format

4:2:2 16-bit parallel input format

Programmable simultaneous composite and S-Video or RGB

(SCART)/YUV video outputs

High performance DVD playback systems, portable video

equipment including digital still cameras and laptop PCs,

video games, PC video/multimedia and digital

satellite/cable systems (set-top boxes/IRD)

¹ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced

CCIR recommendations).

Programmable luma filters (low-pass [PAL/NTSC]) notch,

extended (SSAF, CIF, and QCIF)

Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,

1.2 MHz and 2.0 MHz], CIF and QCIF)

²Throughout the document N is referenced to PAL- Combination -N.

³Protected by U.S. Patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual

property rights. The Macrovision anticopy process is licensed for noncommercial

home use only, which is its sole intended use in the device. Please contact sales

office for latest Macrovision version available.

Programmable VBI (vertical blanking interval)

⁴Refer to Table 8 for complete operating details.

Programmable subcarrier frequency and phase

TTXREQ

TTX

M

POWER

10

U

L

T

I

10-BIT

DAC

MANAGEMENT

CONTROL

CGMS AND WSS

INSERTION

BLOCK

DAC D (PIN 27)

DAC C (PIN 26)

DAC B (PIN 31)

TELETEXT

INSERTION

BLOCK

YUV TO

RGB

V

AA

(SLEEP MODE)

P

L

E

X

E

R

10-BIT

DAC

MATRIX

RESET

10-BIT

DAC

8

Y 8

9

COLOR

DATA

P7–P0

PROGRAMMABLE

LUMINANCE

FILTER

ADD

SYNC

INTER-

POLATOR

10

4:2:2 TO

YCrCb

8

4:4:4

INTER-

TO

YUV

U

10

U 8

V 8

8

10

PROGRAMMABLE

CHROMINANCE

FILTER

INTER-

POLATOR

ADD

BURST

POLATOR

MATRIX

P15–P8

10-BIT

DAC

DAC A (PIN 32)

10

V

ADV7170/ADV7171

HSYNC

FIELD/VSYNC

BLANK

10

SIN/COS

10

REAL-TIME

CONTROL

CIRCUIT

VIDEO TIMING

GENERATOR

2

V

REF

I C MPU PORT

VOLTAGE

REFERENCE

CIRCUIT

R

DDS BLOCK

SET

COMP

CLOCK

SCLOCK SDATA

ALSB

SCRESET/RTC

GND

Figure 1. Functional Block Diagram

Protected by U.S. Patents 5,343,196; 5,442,355; and other intellectual property rights.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

ADV7170/ADV7171

TABLE OF CONTENTS

Specifications..................................................................................... 4

Mode Register 1 MR1 (MR17 to MR10)................................. 30

MR1 Bit Description.................................................................. 30

Mode Register 2 MR2 (MR27 to MR20)................................. 30

MR2 Bit Description.................................................................. 30

Mode Register 3 MR3 (MR37 to MR30).................................... 32

MR3 Bit Description.................................................................... 32

Mode Register 4 MR4 (MR47 to MR40)................................. 33

MR4 Bit Description.................................................................. 33

Dynamic Specifications ............................................................... 6

Timing Specifications .................................................................. 7

Timing Diagrams.......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Package Thermal Performance................................................. 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

General Description....................................................................... 13

Data Path Description................................................................ 13

Internal Filter Response............................................................. 14

Typical Performance Characteristics ........................................... 15

Features ............................................................................................ 18

Color Bar Generation ................................................................ 18

Square Pixel Mode...................................................................... 18

Color Signal Control.................................................................. 18

Burst Signal Control................................................................... 18

NTSC Pedestal Control ............................................................. 18

Pixel Timing Description .......................................................... 18

Subcarrier Reset.......................................................................... 18

Real-Time Control ..................................................................... 18

Video Timing Description ........................................................ 18

Power-On Reset.......................................................................... 26

SCH Phase Mode........................................................................ 26

MPU Port Description............................................................... 26

Register Accesses ........................................................................ 27

Register Programming................................................................... 28

Subaddress Register (SR7 to SR0) ............................................ 28

Register Select (SR5 to SR0)...................................................... 28

Mode Register 0 MR0 (MR07 to MR00)................................. 28

MR0 Bit Description.................................................................. 28

VSYNC

_3H (MR43).................................................................. 33

Timing Mode Register 0 (TR07 to TR00)............................... 33

TR0 Bit Description ................................................................... 34

Timing Mode Register 1 (TR17 to TR10)............................... 34

TR1 Bit Description ................................................................... 34

Subcarrier Frequency Registers 0 to 3 (FSC3 to FSC0)......... 35

Subcarrier Phase Registers (FP7 to FP0)................................. 35

Closed Captioning Even Field Data Register 1 to 0 (CED15 to

CED0) .......................................................................................... 35

Closed Captioning Odd Field Data Registers 1 to 0 (CCD15

to CCD0) ..................................................................................... 35

NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15

to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to

TXO0).......................................................................................... 36

Teletext Request Control Register TC07 (TC07 to TC00).... 36

CGMS_WSS Register 0 C/W0 (C/W07 to C/W00) .............. 36

C/W0 Bit Description................................................................ 36

CGMS_WSS Register 1 C/W1 (C/W17 to C/W10) .............. 37

C/W1 Bit Description................................................................ 37

CGMS Data Bits (C/W17 to C/W16)...................................... 37

CGMS_WSS Register 2 C/W1 (C/W27 to C/W20) .............. 37

C/W2 Bit Description................................................................ 37

Appendices ...................................................................................... 38

Appendix 1—Board Design and Layout Considerations...... 38

Rev. C | Page 2 of 64

ADV7170/ADV7171

Appendix 2—Closed Captioning..............................................40

Appendix 7—Optional Output Filter.......................................48

Appendix 8—Optional DAC Buffering ...................................48

Appendix 9—Recommended Register Values ........................49

Appendix 10—Output Waveforms...........................................51

Outline Dimensions........................................................................61

Ordering Guide ...........................................................................62

Appendix 3—Copy Generation Management System

(CGMS) ........................................................................................41

Appendix 4—Wide Screen Signaling .......................................42

Appendix 5—Teletext Insertion................................................43

Appendix 6—Waveforms...........................................................44

REVISION HISTORY

3/09—Rev. B to Rev. C

Changes to Table 8 ..........................................................................10

Updated Outline Dimensions........................................................61

Added Figure 103, Renumbered Figures Sequentially...............61

Changes to Ordering Guide...........................................................61

6/05—Rev. A to Rev. B

Updated Format.................................................................. Universal

Changes to Features Section ............................................................1

Changes to Table 8 ..........................................................................10

Changes to Square Pixel Mode Section........................................18

Changes to Figure 37 ......................................................................29

Changes to Figure 42 ......................................................................33

Changes to Subcarrier Frequency Registers 3 to 0 Section .......35

Changes to Figure 45 ......................................................................35

Changes to Figure 82 ......................................................................48

Changes to Ordering Guide...........................................................62

6/02—Starting Rev. A to Rev. B

Changes to Specifications.................................................................3

Changes to Package Thermal Performance section...9

Rev. C | Page 3 of 64

ADV7170/ADV7171

SPECIFICATIONS

V_AA= 5 V 5ꢀ¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 1.

Parameter

Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS

10

Bits

R_SET= 300 Ω

Guaranteed monotonic

0.6

LSB

1

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

Input Capacitance, C_IN

DIGITAL OUTPUTS

2

V

μA

pF

0.8

1

V_IN= 0.4 V or 2.4 V

10

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

ANALOG OUTPUTS

Output Current³

I_SOURCE= 400 μA

I_SINK= 3.2 mA

2.4

V

μA

pF

0.4

10

R_SET= 150 Ω, R_L= 37.5 Ω

R_SET= 1041 Ω, R_L= 262.5 Ω

3

0

34.7

5

1.5

37

mA

%

V

kΩ

pF

Output Current⁴

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

VOLTAGE REFERENCE

Reference Range, V_REF

POWER REQUIREMENTS⁵

V_AA

+1.4

30

I_OUT= 0 mA

I_VREFOUT= 20 μA

1.142

4.75

1.235

5.0

1.327

5.25

155

95

V

Normal Power Mode

I_DAC(max)⁶

R_SET= 150 Ω, R_L= 37.5 Ω

R_SET= 1041 Ω, R_L= 262.5 Ω

150

20

75

mA

I_DAC(min)⁶

7

I_CCT

Low Power Mode

I_DAC(max)⁶

80

20

75

mA

I_DAC(min)⁶

7

I_CCT

95

Sleep Mode

8

I_DAC

I_CCT

0.1

0.001

0.01

μA

%/%

9

Power Supply Rejection Ratio

COMP = 0.1 μF

0.5

¹The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³Full drive into 37.5 Ω doubly terminated load.

⁴Minimum drive current (used with buffered/scaled output load).

⁵Power measurements are taken with clock frequency = 27 MHz. Max T_J= 110°C.

⁶I_DACis the total current (min corresponds to 5 mA output per DAC; max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual DACs

reduces I_DACcorrespondingly.

⁷I_CCT(circuit current) is the continuous current required to drive the device.

⁸Total DAC current in sleep mode.

⁹Total continuous current during sleep mode.

Rev. C | Page 4 of 64

ADV7170/ADV7171

V_AA= 3.0 V to 3.6 V¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 2.

Parameter

Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE³

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

Differential Nonlinearity

DIGITAL INPUTS³

10

Bits

R_SET= 300 Ω

Guaranteed monotonic

0.6

LSB

1

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

Input Capacitance, C_IN

DIGITAL OUTPUTS³

2

V

μA

pF

0.8

1

3, 4

V_IN= 0.4 V or 2.4 V

10

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

ANALOG OUTPUTS³

Output Current^{4, 5}

I_SOURCE= 400 μA

I_SINK= 3.2 mA

2.4

V

μA

pF

0.4

10

R_SET= 150 Ω, R_L= 37.5 Ω

R_SET= 1041 Ω, R_L= 262.5 Ω

33

0

34.7

5

2.0

37

mA

%

V

kΩ

pF

Output Current⁶

DAC-to-DAC Matching

Output Compliance, V_OC

Output Impedance, R_OUT

Output Capacitance, C_OUT

POWER REQUIREMENTS^{3, 7}

V_AA

1.4

30

I_OUT= 0 mA

3.0

3.3

3.6

155

V

Normal Power Mode

I_DAC(max)⁸

R_SET= 150 Ω, R_L= 37.5 Ω

R_SET= 1041 Ω, R_L= 262.5 Ω

150

20

35

mA

I_DAC(min)⁸

9

I_CCT

Low Power Mode

I_DAC(max)⁸

80

20

35

mA

I_DAC(min)⁸

9

I_CCT

Sleep Mode

10

I_DAC

I_CCT

0.1

0.001

0.01

μA

%/%

11

Power Supply Rejection Ratio

COMP = 0.1 μF

0.5

¹The min/max specifications are guaranteed over this range. The min/max values are typical over 3.0 V to 3.6 V.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³Guaranteed by characterization.

⁴Full drive into 37.5 Ω load.

⁵DACs can output 35 mA typically at 3.3 V (R_SET= 150 Ω and R_L= 37.5 Ω); optimum performance obtained at 18 mA DAC current (R_SET= 300 Ω and R_L= 75 Ω).

⁶Minimum drive current (used with buffered/scaled output load).

⁷Power measurements are taken with clock frequency = 27 MHz. Max T_J= 110°C.

⁸I_DACis the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual DACs

reduces I_DACcorrespondingly.

⁹I_CCT(circuit current) is the continuous current required to drive the device.

¹⁰Total DAC current in sleep mode.

¹¹Total continuous current during sleep mode.

Rev. C | Page 5 of 64

ADV7170/ADV7171

DYNAMIC SPECIFICATIONS

V_AA= 5 V 5ꢀ¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 3.

Parameter

Differential Gain^{3, 4}

Differential Phase^{3, 4}

Differential Gain^{3, 4}

Conditions¹

Min

Typ

0.3

0.4

1.0

80

70

60

58

0.7

0.9

0.6

0.3

0.2

1.0

0.5

0.8

85

Max

0.7

2.0

Unit

%

Degrees

%

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

Normal power mode

Lower power mode

RMS

Peak periodic

RMS

Peak periodic

Differential Phase^{3, 4}

SNR^{3, 4}(Pedestal)

SNR^{3, 4}(Ramp)

Hue Accuracy^{3, 4}

1.2

1.4

Color Saturation Accuracy^{3, 4}

Chroma Nonlinear Gain^{3, 4}

Chroma Nonlinear Phase^{3 4}

Chroma/Luma Intermod^{3, 4}

Chroma/Luma Gain Inequality^{3, 4}

Chroma/Luma Delay Inequality^{3, 4}

Luminance Nonlinearity^{3, 4}

Chroma AM Noise^{3, 4}

Chroma PM Noise^{3, 4}

Referenced to 40 IRE

%

0.5

0.4

1.4

2.0

1.4

Degrees

%

ns

%

82

79

dB

81

¹The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³Guaranteed by characterization.

⁴These specifications are for the low-pass filter only and are guaranteed by design.

V_AA= 3.0 V to 3.6 V¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 4.

Parameter

Differential Gain³

Differential Phase³

Differential Gain³

Differential Phase³

SNR3 (Pedestal)

Conditions¹

Min

Typ

1.0

0.5

0.6

0.5

78

70

60

58

1.0

1.4

80

Max

Unit

%

Degrees

%

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

Normal power mode

Lower power mode

RMS

SNR3 (Pedestal)

SNR3 (Ramp)

Peak periodic

RMS

SNR3 (Ramp)

Hue Accuracy³

Peak periodic

Color Saturation Accuracy³

Luminance Nonlinearity^{3, 4}

Chroma AM Noise^{3, 4}

Chroma PM Noise^{3, 4}

Chroma Nonlinear Gain^{3, 4}

Chroma Nonlinear Phase^{3, 4}

Chroma/Luma Intermod^{3, 4}

%

dB

79

dB

%

Degrees

%

Referenced to 40 IRE

0.6

0.3

0.2

0.5

0.4

¹The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³Guaranteed by characterization.

⁴These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 10.

Rev. C | Page 6 of 64

ADV7170/ADV7171

TIMING SPECIFICATIONS

V_AA= 4.75 V to 5.25 V¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 5.

Parameter

MPU PORT^{3, 4}

Conditions

Min

Typ

Max

Unit

SCLOCK Frequency

0

400

kHz

μs

ns

μs

SCLOCK High Pulse Width, t₁

SCLOCK Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

CLOCK CONTROLAND PIXEL PORT^{5, 6}

f_CLOCK

0.6

1.3

0.6

100

After this period the first clock is generated

Relevant for repeated start condition

300

0.6

7

0

ns

27

MHz

Clock High Time, t₉

8

ns

Clock Low Time, t₁₀

8

ns

Data Setup Time, t₁₁

Data Hold Time, t₁₂

3.5

4

ns

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

4

3

ns

11

8

48

16

4

Digital Output Hold Time, t₁₄

4

Pipeline Delay, t₁₅

Clock cycles

TELETEXT^{3, 4, 7}

Digital Output Access Time, t₁₆

Data Setup Time, t₁₇

Data Hold Time, t₁₈

RESET CONTROL^{3, 4}

20

2

6

ns

RESET

6

ns

Low Time

¹The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Analog output load ≤ 10 pF.

⁴Guaranteed by characterization

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

⁶Pixel port consists of the following:

Pixel inputs:

Pixel controls:

Clock input:

P15–P0

HSYNC

VSYNC BLANK

, FIELD/

,

CLOCK

⁷Teletext port consists of the following:

Teletext output: TTXREQ

Teletext input: TTX

Rev. C | Page 7 of 64

ADV7170/ADV7171

V_AA= 3.0 V to 3.6 V¹, V_REF= 1.235 V, R_SET= 150 Ω. All specifications T_MINto T_MAX², unless otherwise noted.

Table 6.

Parameter

MPU PORT^{3, 4}

Conditions

Min Typ Max Unit

SCLOCK Frequency

0

400

kHz

μs

ns

μs

SCLOCK High Pulse Width, t₁

SCLOCK Low Pulse Width, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

CLOCK CONTROLAND PIXEL PORT^{4, 5, 6}

f_CLOCK

0.6

1.3

0.6

100

After this period the first clock is generated

Relevant for repeated start condition

300

0.6

7

0

ns

27

MHz

Clock High Time, t₉

8

ns

Clock Low Time, t₁₀

8

ns

Data Setup Time, t₁₁

Data Hold Time, t₁₂

3.5

4

ns

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

Digital Output Hold Time, t₁₄

Pipeline Delay, t₁₅

4

3

ns

12

8

48

Clock cycles

TELETEXT^{3, 4, 7}

Digital Output Access Time, t₁₆

Data Setup Time, t₁₇

Data Hold Time, t₁₈

23

2

6

ns

RESET CONTROL^{3, 4}

Low Time

6

ns

RESET

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.

²Ambient temperature range T_MINto T_MAX: −40°C to +85°C. The die temperature, T_J, must always be kept below 110°C.

³TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.

Analog output load ≤10 pF.

⁴Guaranteed by characterization

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition

⁶Pixel Port consists of the following:

Pixel inputs:

Pixel controls:

Clock input:

P15–P0

HSYNC

VSYNC BLANK

, FIELD/

,

CLOCK

⁷Teletext port consists of the following:

Teletext output: TTXREQ

Teletext input: TTX

Rev. C | Page 8 of 64

ADV7170/ADV7171

TIMING DIAGRAMS

t₃

t₅

t₃

SDATA

t₁

t₆

SCLOCK

t₄

t₂

t₇

t₈

Figure 2. MPU Port Timing Diagram

CLOCK

HSYNC,

t₁₂

t₉

t₁₀

CONTROL

I/PS

FIELD/VSYNC,

BLANK

PIXEL INPUT

DATA

Cb

Y

Cr

Y

Cb

t₁₃

Y

t₁₁

HSYNC,

FIELD/VSYNC,

BLANK

CONTROL

O/PS

t₁₄

Figure 3. Pixel and Control Data Timing Diagram

TTXREQ

CLOCK

t₁₆

t₁₇

t₁₈

TTX

4 CLOCK

CYCLES

4 CLOCK

CYCLES

4 CLOCK

CYCLES

3 CLOCK

CYCLES

4 CLOCK

CYCLES

Figure 4. Teletext Timing Diagram

Rev. C | Page 9 of 64

ADV7170/ADV7171

ABSOLUTE MAXIMUM RATINGS

Table 7.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may

affect device reliability. Only one absolute maximum rating may

be applied at any one time.

Parameter

Rating

V_AAto GND

7 V

Voltage on Any Digital Input Pin

Storage Temperature (T_S)

Junction Temperature (T_J)

GND − 0.5 V to V_AA+ 0.5 V

−65°C to +150°C

150°C

Lead Temperature (Soldering, 10 sec) 260°C

Analog Outputs to GND¹

GND − 0.5 V to V_AA

¹Analog output short circuit to any power supply or GND can be of an

indefinite duration.

PACKAGE THERMAL PERFORMANCE

Table 8. Allowable Operating Conditions for KS and KSU

Package Options

The 44-MQFP package used for this device takes advantage of

an ADI patented thermal coastline lead frame construction.

This maximizes heat transfer into the leads and reduces the

package thermal resistance.

KS, WBS

3 V 5 V

4 DAC ON Double 75R¹Yes +70°C max +70°C max No

KSU

Conditions

3 V

5 V

4 DAC ON Low Power²

4 DAC ON Buffering³

3 DAC ON Double 75R

3 DAC ON Low Power

3 DAC ON Buffering

Yes

Yes Yes

Yes

No

Yes

No

Yes

For the MQFP package, the junction-to-ambient (θ_JA) thermal

resistance in still air on a four-layer PCB is 35.5°C/W. The

junction-to-case thermal resistance (θ_JC) is 13.75°C/W. For the

TQFP package, θ_JAin still air on a four-layer PCB is 53.2°C/W.

θ_JCis 11.1°C/W. Junction Temperature = T_J= [V_AA(Σ DAC

Output Current + I_CCT) × θ_JA] + Ambient Temperature.

Yes

4 DAC ON Buffering

¹DAC ON Double 75R refers to a condition where the DACs are terminated

in a double 75R load and low power mode is disabled.

²DAC ON Low Power refers to a condition where the DACs are terminated

in a double 75R load and low power mode is enabled.

³DAC ON Buffering refers to a condition where the DAC current is reduced

to 5 mA and external buffers are used to drive the video load.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. C | Page 10 of 64

ADV7170/ADV7171

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

44 43 42 41 40 39 38 37 36 35 34

1

33

32

31

30

29

28

27

26

25

24

23

V

REF

AA

PIN 1

2

3

P5

DAC A

DAC B

P6

P7

P8

P9

4

ADV7170/ADV7171

V

AA

MQFP/TQFP

5

GND

6

V

TOP VIEW

(Not to Scale)

AA

7

P10

P11

DAC D

DAC C

COMP

8

9

P12

10

11

GND

SDATA

SCLOCK

V

AA

12 13 14 15 16 17 18 19 20 21 22

Figure 5. Pin Configuration

Table 9. Pin Function Descriptions

Input/

Output Description

Pin No.

1, 11, 20, 28, 30

2 to 9, 12 to 14,

38 to 42

Mnemonic

V_AA

P15 to P0

P

I

Power Supply (3 V to 5 V).

8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7 to P0) or 16-Bit YCrCb Pixel Port (P15 to P0).

P0 represents the LSB.

10, 19, 21, 29, 43

15

GND

HSYNC

G

I/O

Ground Pin.

HSYNC

(Mode 1 and Mode 2) Control Signal. This pin may be configured to output (master

mode) or accept (slave mode) sync signals.

VSYNC

16

17

VSYNC I/O

I/O

FIELD/

Dual Function FIELD (Mode 1) and

(Mode 2) Control Signal. This pin may be

configured to output (master mode) or accept (slave mode) these control signals.

Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level 0. This

signal is optional.

BLANK

18

22

ALSB

RESET

I

TTLAddress Input. This signal sets up the LSB of the MPU address.

The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default

mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite and

S-Video out, and DAC B powered on and DAC D powered off.

23

24

25

SCLOCK

SDATA

COMP

I

MPU Port Serial Interface Clock Input.

MPU Port Serial Data Input/Output.

Compensation Pin. Connect a 0.1 μF capacitor from COMP to V_AA. For optimum dynamic

performance in low power mode, the value of the COMP capacitor can be lowered to as low

as 2.2 nF.

I/O

O

26

27

31

32

DAC C

DAC D

DAC B

DAC A

O

RED/S-Video C/V Analog Output.

GREEN/S-Video Y/Y Analog Output.

BLUE/Composite/U Analog Output.

PAL/NTSC Composite Video Output. Full-scale output is 180 IRE (1286 mV) for NTSC and

1300 mV for PAL.

33

34

V_REF

R_SET

I/O

I

Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes

of the video signals.

Rev. C | Page 11 of 64

ADV7170/ADV7171

Input/

Output Description

Pin No.

Mnemonic

35

SCRESET/RTC

I

This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2.

It can be configured as a subcarrier reset pin, in which case a low-to-high transition on this

pin resets the subcarrier to Field 0. Alternatively, it may be configured as a real-time control

(RTC) input.

36

37

44

TTXREQ

TTX

O

I

Teletext Data Request Signal. Defaults to GND when teletext not selected. Enables

backward compatibility to ADV7175/ADV7176.

Teletext Data. Defaults to V_AAwhen teletext not selected. Enables backward compatibility

to ADV7175/ADV7176.

TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation.

Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel

operation.

CLOCK

I

Rev. C | Page 12 of 64

ADV7170/ADV7171

GENERAL DESCRIPTION

DATA PATH DESCRIPTION

The ADV7170/ADV7171 are integrated digital video encoders

that convert digital CCIR-601 4:2:2 8- or 16-bit component

video data into a standard analog baseband television signal

compatible with worldwide standards.

For PAL B/D/G/H/I/M/N, and NTSC M and N modes, YcrCb

4:2:2 data is input via the CCIR-656 compatible pixel port at a

27 MHz data rate. The pixel data is demultiplexed to form three

data paths. Y typically has a range of 16 to 235; Cr and Cb

typically have a range of 128 112. However, it is possible to

input data from 1 to 254 on Y, Cb, and Cr. The ADV7170/

ADV7171 support PAL (B, D, G, H, I, M, N) and NTSC (with

and without pedestal) standards. The appropriate SYNC,

The on-board SSAF (super sub-alias filter) with extended

luminance frequency response and sharp stop band attenuation

enables studio-quality video playback on modern TVs, giving

optimal horizontal line resolution.

BLANK

, and burst levels are added to the YCrCb data.

An advanced power management circuit enables optimal

control of power consumption in both normal operating modes

and power-down or sleep modes.

Macrovision antitaping (ADV7170 only), closed-captioning,

and teletext levels are also added to Y, and the resultant data

is interpolated to a rate of 27 MHz. The interpolated data is

filtered and scaled by three digital FIR filters.

The ADV7170/ADV7171 support both PAL and NTSC square

pixel operation. The parts also incorporate WSS and CGMS-A

data control generation.

The U and V signals are modulated by the appropriate sub-

carrier sine/cosine phases and added together to make up the

chrominance signal. The luma (Y) signal can be delayed 1 to

3 luma cycles (each cycle is 74 ns) with respect to the chroma

signal. The luma and chroma signals are then added together to

make up the composite video signal. All edges are slew rate

limited.

The output video frames are synchronized with the incoming

data timing reference codes. Optionally, the encoder accepts

HSYNC VSYNC

and can generate

,

, and FIELD timing signals.

These timing signals can be adjusted to change pulse width and

position while the part is in the master mode. The encoder

requires a single, two-times pixel rate (27 MHz) clock for

standard operation. Alternatively, the encoder requires a

24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL

square pixel mode operation. All internal timing is generated

on-chip.

The YCrCb data is also used to generate RGB data with

appropriate SYNC and

synchronization with the composite video output. Alternatively,

analog YUV data can be generated instead of RGB.

BLANK

levels. The RGB data is in

The four 10-bit DACs can be used to output the following:

Composite video + RGB video.

A separate teletext port enables the user to directly input teletext

data during the vertical blanking interval.

The ADV7170/ADV7171 modes are set up over a 2-wire, serial

bidirectional port (I²C-compatible) with two slave addresses.

Composite video + YUV video.

Two composite video signals + LUMA

and CHROMA (Y/C) signals.

Functionally, the ADV7170 and ADV7171 are the same with the

exception that the ADV7170 can output the Macrovision

anticopy algorithm.

Alternatively, each DAC can be individually powered off if not

required.

The ADV7170/ADV7171 are packaged in a 44-lead MQFP

package and a 44-lead TQFP package.

Video output levels are illustrated in Appendix 6—Waveforms.

Rev. C | Page 13 of 64

ADV7170/ADV7171

INTERNAL FILTER RESPONSE

The Y filter supports several different frequency responses, including two low-pass responses, two notch responses, an extended (SSAF)

response, a CIF response, and a QCIF response. The UV filter supports several different frequency responses, including four low-pass

responses, a CIF response, and a QCIF response that are shown in Table 10 and Table 11 and Figure 6 to Figure 18.

Table 10. Luminance Internal Filter Specifications

Filter Selection

MR04 MR03 MR02

Pass-Band Ripple

(dB)

3 dB Bandwidth

(MHz)

Stop-Band

Cutoff (MHz)

Stop-Band Attenuation

(dB)

Filter Type

Low Pass (NTSC)

Low Pass (PAL)

Notch (NTSC)

Notch (PAL)

Extended (SSAF)

CIF

0

1

0

1

0

1

0

1

0

1

0

1

0

0.091

0.15

0.015

0.095

0.051

0.018

Monotonic

4.157

4.74

6.54

6.24

6.217

3.0

7.37

7.96

8.3

8.0

−56

−64

−68

−66

−61

−50

7.06

7.15

QCIF

1.5

Table 11. Chrominance Internal Filter Specifications

Filter Selection

MR07 MR06 MR05

Pass-Band Ripple 3 dB Bandwidth

(dB) (MHz)

Stop-Band

Cutoff (MHz)

3.01

3.64

3.73

5.0

Stop-Band Attenuation

(dB)

−45

−58.5

−49

−40

Filter Type

1.3 MHz Low Pass

.65 MHz Low Pass

1.0 MHz Low Pass

2.0 MHz Low Pass

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

0.084

1.395

0.65

1.0

Monotonic

0.0645

2.2

CIF

QCIF

0.084

Monotonic

0.7

0.5

3.01

4.08

−45

−50

Rev. C | Page 14 of 64

ADV7170/ADV7171

TYPICAL PERFORMANCE CHARACTERISTICS

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 9. PAL Notch Luma Filter

Figure 6. NTSC Low-Pass Luma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

2

4

6

8

10

2

4

6

8

10

FREQUENCY (MHz)

Figure 10. Extended Mode (SSAF) Luma Filter

Figure 7. PAL Low-Pass Luma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

2

4

6

8

10

2

4

6

8

10

FREQUENCY (MHz)

Figure 11. CIF Luma Filter

Figure 8. NTSC Notch Luma Filter

Rev. C | Page 15 of 64

ADV7170/ADV7171

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 12. QCIF Luma Filter

Figure 15. 1.0 MHz Low-Pass Chroma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

2

4

6

8

10

2

4

6

8

10

FREQUENCY (MHz)

Figure 13. 1.3 MHz Low-Pass Chroma Filter

Figure 16. 2.0 MHz Low-Pass Chroma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

2

4

6

8

10

2

4

6

8

10

FREQUENCY (MHz)

Figure 14. 0.65 MHz Low-Pass Chroma Filter

Figure 17. CIF Chroma Filter

Rev. C | Page 16 of 64

ADV7170/ADV7171

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

FREQUENCY (MHz)

Figure 18. QCIF Chroma Filter

Rev. C | Page 17 of 64

ADV7170/ADV7171

FEATURES

COLOR BAR GENERATION

SUBCARRIER RESET

Together with the SCRESET/RTC pin and Bit MR22 and

Bit MR21 of Mode Register 2, the ADV7170/ADV7171

can be used in subcarrier reset mode. The subcarrier resets

to Field 0 at the start of the following field when a low-to-high

transition occurs on this input pin.

The ADV7170/ADV7171 can be configured to generate

100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars

for PAL. These are enabled by setting MR17 of Mode Register 1

to Logic Level 1.

SQUARE PIXEL MODE

REAL-TIME CONTROL

The ADV7170/ADV7171 can be used to operate in square pixel

mode. For NTSC operation, an input clock of 24.5454 MHz is

required. Alternatively, for PAL operation, an input clock of 29.5

MHz is required. The internal timing logic adjusts accordingly

for square pixel mode operation. When the ADV7171 is

configured for PAL square pixel mode, it supports 768 active

pixels per line. NTSC square pixel mode supports 640 active

pixels per line.

Together with the SCRESET/RTC pin and Bit MR22 and

Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be

used to lock to an external video source. The real-time control

mode allows the ADV7170/ADV7171 to automatically alter the

subcarrier frequency to compensate for line length variation.

When the part is connected to a device that outputs a digital

data stream in the RTC format (such as a ADV7185 video

decoder, shown in Figure 19), the part automatically changes to

the compensated subcarrier frequency on a line-by-line basis.

This digital data stream is 67 bits wide, and the subcarrier is

contained in Bit 0 to Bit 21. Each bit is 2 clock cycles long.

00Hex should be written into all four subcarrier frequency

registers when using this mode.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video

output using Bit MR24 of Mode Register 2.

BURST SIGNAL CONTROL

The burst information can be switched on and off the video

output using Bit MR25 of Mode Register 2.

VIDEO TIMING DESCRIPTION

The ADV7170/ADV7171 are intended to interface to off-the-

shelf MPEG1 and MPEG2 decoders. Consequently, the

ADV7170/ADV7171 accept 4:2:2 YCrCb pixel data via a

CCIR-656 pixel port, and they have several video timing modes

of operation that allow them to be configured as either system

master video timing generators or as slaves to the system video

timing generator. The ADV7170/ADV7171 generate all of the

required horizontal and vertical timing periods and levels for

the analog video outputs.

NTSC PEDESTAL CONTROL

The pedestal on both odd and even fields can be controlled on a

line-by-line basis using the NTSC pedestal control registers.

This allows the pedestals to be controlled during the vertical

blanking interval.

PIXEL TIMING DESCRIPTION

The ADV7170/ADV7171 operate in either 8-bit or 16-bit

YCrCb mode.

The ADV7170/ADV7171 calculate the width and placement of

analog sync pulses, blanking levels, and color burst envelopes.

Color bursts are disabled on appropriate lines, and serration

and equalization pulses are inserted where required.

8-Bit YCrCb Mode

This default mode accepts multiplexed YCrCb inputs through

the P7 to P0 pixel inputs. The inputs follow the sequence Cb0,

Y0 Cr0, Y1 Cb1, Y2, and so on. The Y, Cb, and Cr data are input

on a rising clock edge.

In addition, the ADV7170/ADV7171 support a PAL or NTSC

square pixel operation in slave mode. The part requires an input

pixel clock of 24.5454 MHz for NTSC and an input pixel clock of

29.5 MHz for PAL. The internal horizontal line counters place the

various video waveform sections in the correct location for the new

clock frequencies.

16-Bit YCrCb Mode

This mode accepts Y inputs through the P7 to P0 pixel inputs

and multiplexed CrCb inputs through the P15 to P8 pixel

inputs. The data is loaded on every second rising edge of

CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1,

Y2, and so on.

The ADV7170/ADV7171 have four distinct master and four

distinct slave timing configurations. Timing Control is established

SYNC BLANK

VSYNC

, and FIELD/ pins.

with the bidirectional

,

Timing Mode Register 1 can also be used to vary the timing pulse

widths where they occur in relation to each other.

Rev. C | Page 18 of 64

ADV7170/ADV7171

CLOCK

SCRESET/RTC

COMPOSITE VIDEO

(FOR EXAMPLE,

VCR OR CABLE)

VIDEO

DECODER

(FOR EXAMPLE,

ADV7185)

GREEN/LUMA/Y

RED/CHROMA/V

P7–P0

BLUE/COMPOSITE/U

COMPOSITE

HSYNC

FIELD/VSYNC

ADV7170/ADV7171

SEQUENCE

RESERVED

2

BIT

H/LTRANSITION

COUNT START

RESET

5 BITS

4 BITS

RESERVED

3

BIT

RESERVED

LOW

14 BITS

RESERVED

128

1

F

PLL INCREMENT

SC

0

13

21

RTC

TIME SLOT: 01

67 68

14

19

NOT USED IN

ADV7170/ADV7171

VALID

INVALID

8/LLC

SAMPLE SAMPLE

NOTES:

1

2

3

F

PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7170/ADV7171 FSC DDS REGISTER IS

PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD

SC

BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

RESET BIT

RESET ADV7170/ADV7171 DDS

Figure 19. RTC Timing and Connections

Vertical Blanking Data Insertion

Mode 0 (CCIR-656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

It is possible to allow encoding of incoming YCbCr data on

those lines of VBI that do not bear line sync or pre-/post-

equalization pulses (see Figure 21 to Figure 32). This mode of

operation is called “partial blanking” and is selected by setting

MR32 to 1. It allows the insertion of any VBI data (opened VBI)

into the encoded output waveform. This data is present in the

digitized incoming YcbCr data stream (for example, WSS data,

CGMS, VPS, and so on). Alternatively, the entire VBI may be

blanked (no VBI data inserted) on these lines by setting MR32

to 0.

The ADV7170/ADV7171 are controlled by the SAV (start active

video) and EAV (end active video) time codes in the pixel data.

All timing information is transmitted using a 4-byte synchroni-

zation pattern. A synchronization pattern is sent immediately

before and after each line during active picture and retrace.

HSYNC

VSYNC

Mode 0 is shown in Figure 20. The

, FIELD/

,

BLANK

and

(if not used) pins should be tied high during this

mode.

ANALOG

VIDEO

EAV CODE

SAV CODE

C

b

C

r

C

b

8

0

F

F A A

F B B

A

B

8

0

C

r

F

0

X

Y

1

0

8

0

1

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

r

Y

INPUT PIXELS

ANCILLARY DATA

(HANC)

4 CLOCK

1440 CLOCK

268 CLOCK

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

280 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

START OF ACTIVE

VIDEO LINE

END OF ACTIVE

VIDEO LINE

Figure 20. Timing Mode 0 (Slave Mode)

Rev. C | Page 19 of 64

ADV7170/ADV7171

Mode 0 (CCIR-656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7170/ADV7171 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes

HSYNC

BLANK

in the CCIR656 standard. The H bit is output on the

pin, the V bit is output on the

pin, and the F bit is output on the

VSYNC

FIELD/

pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V, and F transitions relative to the video

waveform are illustrated in Figure 23.

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

10

11

20

21

22

5

9

8

H

V

F

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

V

ODD FIELD

EVEN FIELD

F

Figure 21. Timing Mode 0 (NTSC Master Mode)

Rev. C | Page 20 of 64

ADV7170/ADV7171

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

22

23

5

21

H

V

EVEN FIELD

ODD FIELD

F

DISPLAY

VERTICAL BLANK

318

334

335

336

309

310

311

312

313

314

315

316

317

319

320

H

V

F

ODD FIELD

EVEN FIELD

Figure 22. Timing Mode 0 (PAL Master Mode)

ANALOG

VIDEO

H

F

V

Figure 23. Timing Mode 0 Data Transitions (Master Mode)

Rev. C | Page 21 of 64

ADV7170/ADV7171

Mode 1: Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7170/ADV7171 accept horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when

HSYNC

BLANK

is low indicates a new frame, that is, vertical retrace. The

signal is optional. When the input is disabled,

the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC)

and Figure 25 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 24. Timing Mode 1 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

317

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 25. Timing Mode 1 (PAL)

Rev. C | Page 22 of 64

ADV7170/ADV7171

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7170/ADV7171 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when

HSYNC BLANK BLANK

is low indicates a new frame, that is, vertical retrace. The

signal is optional. When the

input is disabled, the

ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following

HSYNC BLANK

, and

the timing signal transitions. Mode 1 is shown in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illustrates the

FIELD for an odd or even field transition relative to the pixel data.

,

HSYNC

FIELD

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

Cr

Y

Cb

Y

DATA

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0)

HSYNC

In this mode the ADV7170/ADV7171 accept horizontal and vertical SYNC signals. A coincident low transition of both

and

is high indicates the start of an even field. The

input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as

VSYNC

BLANK

VSYNC

HSYNC

low transition when

inputs indicates the start of an odd field. A

BLANK

signal is optional. When the

per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

Figure 27. Timing Mode 2 (NTSC)

Rev. C | Page 23 of 64

ADV7170/ADV7171

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

318

319

320

335

336

317

334

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

Figure 28. Timing Mode 2 (PAL)

Mode 2: Master Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

HSYNC

In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both

and

is high indicates the start of an even field. The

input is disabled, the ADV7170/ADV7171 automatically blank all normally blank lines as

HSYNC BLANK VSYNC

VSYNC

BLANK

VSYNC

HSYNC

low transition when

inputs indicates the start of an odd field. A

BLANK

signal is optional. When the

per CCIR-624. Mode 2 is shown in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 shows the

,

, and

VSYNC

for an odd-to-even field

for an

HSYNC BLANK

, and

even-to-odd field transition relative to the pixel data. Figure 30 shows the

transition relative to the pixel data.

,

HSYNC

VSYNC

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

PAL = 12 × CLOCK/2

NTSC = 16 × CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

Cb

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

Rev. C | Page 24 of 64

ADV7170/ADV7171

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode the ADV7170/ADV7171 accept or generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input

HSYNC BLANK BLANK

when

is high indicates a new frame, that is, vertical retrace. The

signal is optional. When the

input is disabled,

the ADV7170/ADV7171 automatically blank all normally blank lines as per CCIR-624. Mode 3 is shown in Figure 31 (NTSC) and Figure

32 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

10

11

20

21

22

5

9

8

HSYNC

BLANK

FIELD

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 31. Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

22

23

5

21

HSYNC

BLANK

FIELD

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

318

334

335

336

309

310

311

312

313

314

315

316

317

319

320

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 32. Timing Mode 3 (PAL)

Rev. C | Page 25 of 64

ADV7170/ADV7171

1

0

1

0

1

A1

X

POWER-ON RESET

After power-up, it is necessary to execute a reset operation.

A reset occurs on the falling edge of a high-to-low transition

ADDRESS

CONTROL

SET UP BY

ALSB

RESET

on the

pin. This initializes the pixel port so that the pixel

READ/WRITE

CONTROL

inputs, P7 to P0, are selected. After reset, the ADV7170/

ADV7171 is automatically set up to operate in NTSC mode.

Subcarrier frequency code 21F07C16HEX is loaded into the

subcarrier frequency registers. All other registers, with the

exception of Mode Register 0, are set to 00H. All bits in

Mode Register 0 are set to Logic Level 0, except Bit MR44.

Bit MR44 of Mode Register 4 is set to Logic Level 1. This

enables the 7.5 IRE pedestal.

0

1

WRITE

READ

Figure 33. ADV7170 Slave Address

0

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB

SCH PHASE MODE

READ/WRITE

CONTROL

The SCH phase is configured in default mode to reset every

four (NTSC) or eight (PAL) fields to avoid an accumulation of

SCH phase error over time. In an ideal system, zero SCH phase

error would be maintained forever, but in reality, this is

impossible to achieve due to clock frequency variations. This

effect is reduced by the use of a 32-bit DDS, which generates

this SCH.

0

1

WRITE

READ

Figure 34. ADV7171 Slave Address

To control the various devices on the bus, the following

protocol must be followed: first, the master initiates a data

transfer by establishing a start condition, defined by a high-to-

low transition on SDATA while SCLOCK remains high. This

indicates that an address/data stream follows. All peripherals

respond to the start condition and shift the next eight bits

Resetting the SCH phase every four or eight fields avoids the

accumulation of SCH phase error and results in very minor

SCH phase jumps at the start of the four or eight field sequence.

Resetting the SCH phase should not be done if the video source

does not have stable timing or the ADV7170/ADV7171 are

configured in RTC mode (MR21 = 1 and MR22 = 1). Under

these conditions (unstable video), the subcarrier phase reset

should be enabled (MR22 = 0 and MR21 = 1) but no reset

applied. In this configuration the SCH phase is never reset,

which means the output video tracks the unstable input video.

The subcarrier phase reset, when applied, resets the SCH phase

to Field 0 at the start of the next field (for example, subcarrier

phase reset applied in Field 5 [PAL] on the start of the next field

SCH phase resets to Field 0).

RW

(7-bit address + R/

bit). The bits transfer from MSB down to

LSB. The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth clock

pulse. This is known as an acknowledge bit. All other devices

withdraw from the bus at this point and maintain an idle

condition. The idle condition is where the device monitors the

SDATA and SCLOCK lines waiting for the start condition and

RW

the correct transmitted address. The R/

bit determines the

direction of the data. A Logic Level 0 on the LSB of the first byte

means that the master writes information to the peripheral. A

Logic Level 1 on the LSB of the first byte means the master

reads information from the peripheral.

MPU PORT DESCRIPTION

The ADV7170/ADV7171 support a 2-wire, serial (I²C-

compatible) microprocessor bus driving multiple peripherals.

Two inputs, serial data (SDATA), and serial clock (SCLOCK),

carry information between any devices connected to the bus.

Each slave device is recognized by a unique address. The

ADV7170/ADV7171 each have four possible slave addresses for

both read and write operations. These are unique addresses for

each device and are shown in Figure 33 and Figure 34.

The LSB sets either a read or write operation. Logic Level 1

corresponds to a read operation, while Logic Level 0 corre-

sponds to a write operation. A 1 is set by setting the ALSB pin of

the ADV7170/ADV7171 to Logic Level 0 or Logic Level 1.

Rev. C | Page 26 of 64

ADV7170/ADV7171

REGISTER ACCESSES

The ADV7170/ADV7171 act as standard slave devices on the

bus. The data on the SDATA pin is eight bits long, supporting

The MPU can write to or read from all of the ADV7170/

ADV7171 registers except the subaddress register, which is a

write-only register. The subaddress register determines which

register the next read or write operation accesses. All commu-

nications with the part through the bus start with an access to

the subaddress register. A read/write operation is performed

from/to the target address, which then increments to the next

address until a stop command on the bus is performed.

RW

the 7-bit addresses plus the R/

bit. The ADV7170 has 48

subaddresses, and the ADV7171 has 26 subaddresses to enable

access to the internal registers. It therefore interprets the first

byte as the device address and the second byte as the starting

subaddress. The subaddresses’ auto-increment allows data to be

written to or read from the starting subaddress. A data transfer

is always terminated by a stop condition. The user can also

access any unique subaddress register on a one-by-one basis

without having to update all the registers. There is one

exception. The subcarrier frequency registers should be updated

in sequence, starting with Subcarrier Frequency Register 0. The

auto-increment function should then be used to increment and

access Subcarrier Frequency Register 1, Subcarrier Frequency

Register 2, and Subcarrier Frequency Register 3. The subcarrier

frequency registers should not be accessed independently.

Stop and start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of

sequence with normal read and write operations, they cause an

immediate jump to the idle condition. During a given SCLOCK

high period, the user should issue only one start condition, one

stop condition, or a single stop condition followed by a single

start condition. If an invalid subaddress is issued by the user,

the ADV7170/ADV7171 do not issue an acknowledge, and they

return to the idle condition. If in auto-increment mode the user

exceeds the highest subaddress, the following action is taken:

In read mode, the highest subaddress register contents

continue to be output until the master device issues a no-

acknowledge. This indicates the end of a read. A no-

acknowledge condition is where the SDATA line is not pulled

low on the ninth pulse.

In write mode, the data for the invalid byte is not loaded into

any subaddress register, a no-acknowledge is issued by the

ADV7170/ADV7171, and the part returns to the idle

condition.

Figure 35 illustrates an example of data transfer for a read

sequence and the start and stop conditions.

Figure 36 shows bus write and read sequences.

SDATA

SCLOCK

S

P

9

1–7

9

1–7

8

1–7

8

START ADDR R/W ACK SUBADDRESS ACK

DATA

ACK

STOP

Figure 35. Bus Data Transfer

Rev. C | Page 27 of 64

ADV7170/ADV7171

REGISTER PROGRAMMING

This section describes each register, including subaddress

register, mode registers, subcarrier frequency registers,

subcarrier phase register, timing registers, closed captioning

extended data registers, closed captioning data registers, and

NTSC pedestal control registers, in terms of its configuration.

MODE REGISTER 0 MR0 (MR07 TO MR00)

(Address [SR4 to SR0] = 00H)

Figure 38 shows the various operations under the control of

Mode Register 0. This register can be read from as well as

written to.

SUBADDRESS REGISTER (SR7 TO SR0)

MR0 BIT DESCRIPTION

Output Video Standard Selection (MR01 to MR00)

The communications register is an 8-bit, write-only register.

After the part has been accessed over the bus and a read/write

operation is selected, the subaddress is set up. The subaddress

register determines to/from which register the operation takes

place.

These bits are used to set up the encode mode. The ADV7170/

ADV7171 can be set up to output NTSC, PAL B/D/G/H/I, and

PAL M/N standard video.

Luminance Filter Control (MR02 to MR04)

Figure 37 shows the various operations under the control of the

subaddress register. Zero should always be written to SR7 to SR6.

These bits specify which luma filter is to be selected. The filter

selection is made independent of whether PAL or NTSC is

selected.

REGISTER SELECT (SR5 TO SR0)

These bits are set up to point to the required starting address.

Chrominance Filter Control (MR05 to MR07)

These bits select the chrominance filter. A low-pass filter can be

selected with a choice of cutoff frequencies, 0.65 MHz,

1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF

or QCIF filters.

WRITE

S

SLAVE ADDR A(S)

LSB = 0

SUBADDR

A(S)

DATA

A(S)

DATA

A(S) P

SEQUENCE

LSB = 1

READ

SEQUENCE

SLAVE ADDR A(S)

S

SLAVE ADDR A(S)

DATA

A(M)

DATA

A(M) P

S = START BIT

P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A (S) = NO-ACKNOWLEDGE BY SLAVE

A (M) = NO-ACKNOWLEDGE BY MASTER

Figure 36. Write and Read Sequences

Rev. C | Page 28 of 64

ADV7170/ADV7171

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

SR7–SR5 (000)

ZERO SHOULD BE WRITTEN

TO THESE BITS

ADV7171 SUBADDRESS REGISTER

ADV7170 SUBADDRESS REGISTER

POWER-UP/

RESET VALUE

(HEX)

POWER-UP/

RESET VALUE

(HEX)

SR5

SR4

SR3

SR2

SR1

SR0

SR5

SR4

SR3

SR2

SR1

SR0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE REGISTER 0

MODE REGISTER 1

MODE REGISTER 2

MODE REGISTER 3

MODE REGISTER 4

RESERVED

00

58

00

10

00

16*

7C

F0

21

00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MODE REGISTER 0

00

58

00

10

00

16*

7C

F0

21

00

MODE REGISTER 1

MODE REGISTER 2

MODE REGISTER 3

MODE REGISTER 4

RESERVED

TIMING MODE REGISTER 0

TIMING MODE REGISTER 1

SUBCARRIER FREQUENCY REGISTER 0

SUBCARRIER FREQUENCY REGISTER 1

SUBCARRIER FREQUENCY REGISTER 2

SUBCARRIER FREQUENCY REGISTER 3

SUBCARRIER PHASE REGISTER

CLOSED CAPTIONING EXTENDED DATA BYTE 0

CLOSED CAPTIONING EXTENDED DATA BYTE 1

CLOSED CAPTIONING DATA BYTE 0

CLOSED CAPTIONING DATA BYTE 1

SUBCARRIER FREQUENCY REGISTER 0

SUBCARRIER FREQUENCY REGISTER 1

SUBCARRIER FREQUENCY REGISTER 2

SUBCARRIER FREQUENCY REGISTER 3

SUBCARRIER PHASE REGISTER

CLOSED CAPTIONING EXTENDED DATA BYTE 0

CLOSED CAPTIONING EXTENDED DATA BYTE 1

CLOSED CAPTIONING DATA BYTE 0

CLOSED CAPTIONING DATA BYTE 1

NTSC PEDESTAL CONTROL REG 0/

PAL TTX CONTROL REG 0

NTSC PEDESTAL CONTROL REG 0/

PAL TTX CONTROL REG 0

00

0

1

0

1

0

1

0

1

00

0

1

0

1

0

1

0

1

NTSC PEDESTAL CONTROL REG 1/

PAL TTX CONTROL REG 1

NTSC PEDESTAL CONTROL REG 1/

PAL TTX CONTROL REG 1

NTSC PEDESTAL CONTROL REG 2/

PAL TTX CONTROL REG 2

NTSC PEDESTAL CONTROL REG 2/

PAL TTX CONTROL REG 2

NTSC PEDESTAL CONTROL REG 3/

PAL TTX CONTROL REG 3

NTSC PEDESTAL CONTROL REG 3/

PAL TTX CONTROL REG 3

00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CGMS_WSS_0

0

1

0

1

0

1

0

1

0

1

CGMS_WSS_0

00

CGMS_WSS_1

00

CGMS_WSS_2

TELETEXT REQUEST CONTROL REGISTER

RESERVED

TELETEXT REQUEST CONTROL REGISTER

00

RESERVED

MACROVISION REGISTERS

*SUBCARRIER FREQUENCY REGISTER 0 = 16 IS

INCORRECT ON POWER-UP FOR NTSC. THIS REGISTER

SHOULD BE PROGRAMMED TO 1F FOR ACCURATE FSC.

Figure 37. Subaddress Register Map

Rev. C | Page 29 of 64

ADV7170/ADV7171

MR07

MR06

MR05

MR04

MR03

MR02

MR01

MR00

CHROMA FILTER SELECT

MR05

OUTPUT VIDEO

STANDARD SELECTION

MR07

MR06

MR01

MR00

1.3MHz LOW PASS FILTER

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

NTSC

0.65MHz LOW PASS FILTER

1.0MHz LOW PASS FILTER

2.0MHz LOW PASS FILTER

RESERVED

PAL (B, D, G, H, I)

PAL (M)

RESERVED

CIF

LUMA FILTER SELECT

MR02

Q CIF

MR04

MR03

RESERVED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOW PASS FILTER (NTSC)

LOW PASS FILTER (PAL)

NOTCH FILTER (NTSC)

NOTCH FILTER (PAL)

EXTENDED MODE

CIF

Q CIF

RESERVED

Figure 38. Mode Register 0

Color Bar Control (MR17)

MODE REGISTER 1 MR1 (MR17 TO MR10)

This bit can be used to generate and output an internal color bar

test pattern. The color bar configuration is 100/7.5/75/7.5 for

NTSC and 100/0/75/0 for PAL. It is important to note that when

color bars are enabled, the ADV7170/ADV7171 are configured

in a master timing mode.

(Address (SR4 to SR0) = 01H)

Figure 39 shows the various operations under the control of

Mode Register 1. This register can be read from as well as

written to.

MR1 BIT DESCRIPTION

Interlace Control (MR10)

MODE REGISTER 2 MR2 (MR27 TO MR20)

(Address [SR4 to SR0] = 02H)

This bit is used to set up the output to interlaced or noninter-

laced mode. This mode is only relevant when the part is in

composite video mode.

Mode Register 2 is an 8-bit-wide register.

Figure 40 shows the various operations under the control of

Mode Register 2. This register can be read from as well as

written to.

Closed Captioning Field Selection (MR12 to MR11)

These bits control the fields on which closed captioning data is

displayed. Closed captioning information can be displayed on

an odd field, even field, or both odd and even fields.

MR2 BIT DESCRIPTION

Square Pixel Control (MR20)

This bit is used to set up square pixel mode. This is available in

slave mode only. For NTSC, a 24.5454 MHz clock must be

supplied. For PAL, a 29.5 MHz clock must be supplied.

DAC Control (MR16 to MR13)

These bits can be used to power down the DACs. This can be

used to reduce the power consumption of the ADV7170/

ADV7171 if any of the DACs are not required in the

application.

Rev. C | Page 30 of 64

ADV7170/ADV7171

MR17

MR16

MR15

MR14

MR13

MR12

MR11

MR10

DAC A

CONTROL

DAC D

CONTROL

CLOSED CAPTIONING

FIELD SELECTION

MR16

MR14

MR12 MR11

0

1

NORMAL

POWER-DOWN

0

1

NORMAL

POWER-DOWN

0

1

0

1

0

1

NO DATA OUT

ODD FIELD ONLY

EVEN FIELD ONLY

DATA OUT

(BOTH FIELDS)

COLOR BAR

CONTROL

DAC B

CONTROL

DAC C

CONTROL

INTERLACE

CONTROL

MR17

MR15

MR13

MR10

0

1

NORMAL

POWER-DOWN

0

1

NORMAL

POWER-DOWN

0

1

INTERLACED

NONINTERLACED

0

1

DISABLE

ENABLE

Figure 39. Mode Register 1

MR27

MR26

MR25

MR24

MR23

MR22

MR21

MR20

CHROMINANCE

CONTROL

GENLOCK CONTROL

MR22 MR21

LOW POWER MODE

MR26

MR24

x

0

1

DISABLE GENLOCK

ENABLE SUBCARRIER

RESET PIN

0

1

DISABLE

ENABLE

0

1

ENABLE COLOR

DISABLE COLOR

1

ENABLE RTC PIN

MR27

RESERVED

BURST

CONTROL

ACTIVE VIDEO LINE

DURATION

SQUARE PIXEL

CONTROL

MR25

MR23

MR20

0

1

ENABLE BURST

DISABLE BURST

0

1

DISABLE

ENABLE

0

1

720 PIXELS

710 PIXELS/702 PIXELS

Figure 40. Mode Register 2

MR37

MR36

MR35

MR34

MR33

MR32

MR31

MR30

VBI_OPEN

TTXRQ BIT

CHROMA OUTPUT

SELECT

MR30

MR31

MODE CONTROL

MR32

MR36

MR34

0

1

DISABLE

ENABLE

RESERVED

0

1

NORMAL

BIT REQUEST

0

1

DISABLE

ENABLE

INPUT DEFAULT

COLOR

TELETEXT

ENABLE

DAC OUTPUT

DAC B

MR37

MR35

MR33

DAC A

DAC C

DAC D

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

COMPOSITE

BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y

GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE

Figure 41. Mode Register 3

a 1 selects ITU-R.BT470 standard for active video duration

(710 pixels NTSC; 702 pixels PAL).

Genlock Control (MR22 to MR21)

These bits control the genlock feature of the ADV7170/

ADV7171. Setting MR21 to a Logic Level 1 configures the

SCRESET/RTC pin as an input. Setting MR22 to Logic Level 0

configures the SCRESET/RTC pin as a subcarrier reset input.

Therefore, the subcarrier resets to Field 0 following a low-to-

high transition on the SCRESET/RTC pin. Setting MR22 to

Logic Level 1 configures the SCRESET/RTC pin as a real-time

control input.

Chrominance Control (MR24)

This bit enables the color information to be switched on and off

the video output.

Burst Control (MR25)

This bit enables the burst information to be switched on and off the

video output.

Low Power Mode (MR26)

Active Video Line Duration (MR23)

This bit enables the lower power mode of the ADV7170/

ADV7171, reducing the DAC current by 45ꢀ.

This bit switches between two active video line durations.

A 0 selects CCIR REC601 (720 pixels PAL/NTSC), and

Rev. C | Page 31 of 64

ADV7170/ADV7171

Reserved (MR27)

DAC Output (MR33)

This bit is used to switch the DAC outputs from SCART to a

EUROSCART configuration. A complete table of all DAC output

configurations is shown in Table 12.

A Logic Level 0 must be written to this bit.

MODE REGISTER 3 MR3 (MR37 TO MR30)

(Address [SR4 to SR0] = 03H)

Chroma Output Select (MR34)

Mode Register 3 is an 8-bit-wide register. Figure 41 shows the

various operations under the control of Mode Register 3.

With this active high bit it is possible to output YUV data with a

composite output on the fourth DAC or a chroma output on the

fourth DAC (0 = CVBS; 1 = CHROMA).

MR3 BIT DESCRIPTION

Revision Code (MR30 to MR31)

Teletext Enable (MR35)

These bits are read-only and indicate the revision of the device.

This bit must be set to 1 to enable teletext data insertion on the

TTX pin.

VBI Open (MR32)

This bit determines whether or not data in the vertical blanking

interval (VBI) is output to the analog outputs or blanked. VBI

data insertion is not available in Slave Mode 0. Also, when both

TTXREQ Bit Mode Control (MR36)

This bit enables switching of the teletext request signal from a

continuous high signal (MR36 = 0) to a bit wise request signal

(MR36 = 1).

BLANK

input control and VBI-open are enabled,

input

control has priority; that is, VBI data insertion does not work.

Input Default Color (MR37)

This bit determines the default output color from the DACs for

zero input pixel data (or disconnected). A Logic Level 0 means that

the color corresponding to 00000000 is displayed. A Logic Level 1

forces the output color to black for 00000000 pixel input video data.

Table 12. DAC Output Configuration Matrix

MR34

MR40

MR41

MR33

DAC A

CVBS

Y

CVBS

Y

CVBS

G

CVBS

Y

C

Y

C

Y

C

G

C

DAC B

CVBS

B

U

CVBS

B

U

DAC C

DAC D

Y

CVBS

Y

CVBS

G

CVBS

Y

Simultaneous Output

2 composite and Y/C

RGB and composite

YUV and composite

1 composite, Y and 2C

RGB and C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C

R

V

C

R

V

CVBS

Y

C

Y

C

G

C

Y

C

RGB and C

YUV and C

Y

CVBS: Composite video baseband signal

Y:

C:

U:

V:

R:

G:

B:

Luminance component signal (for YUV or Y/C mode)

Chrominance signal (for Y/C mode)

Chrominance component signal (for YUV mode)

RED Component video (for RGB mode)

GREEN Component video (for RGB mode)

BLUE Component video (for RGB mode)

Each DAC can be powered on or off individually with the following control bits (0 = ON; 1 = OFF):

MR13-DAC C

MR14-DAC D

MR15-DAC B

MR16-DAC A

Rev. C | Page 32 of 64

ADV7170/ADV7171

MR47

MR46

MR45

MR44

MR43

MR42

MR41

MR40

RGB SYNC

OUTPUT SELECT

MR40

SLEEP MODE

CONTROL

PEDESTAL

CONTROL

MR42

MR46

MR44

0

1

DISABLE

ENABLE

0

1

YC OUTPUT

RGB/YUV OUTPUT

0

1

DISABLE

ENABLE

0

1

PEDESTAL OFF

PEDESTAL ON

MR47

(0)

VSYNC_3H

ACTIVE VIDEO

RGB/YUV

CONTROL

FILTER CONTROL

MR43

MR45

MR41

ZERO SHOULD

BE WRITTEN TO

THIS BIT

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

RGB OUTPUT

YUV OUTPUT

Figure 42. Mode Register 4

Active Video Filter Control (MR45)

MODE REGISTER 4 MR4 (MR47 TO MR40)

This bit controls the filter mode applied outside the active video

portion of the line. This filter ensures that the sync rise and fall

times are always on spec regardless of which luma filter is

selected. This mode is enabled by a Logic Level 1.

(Address (SR4 to SR0) = 04H)

Mode Register 4 is an 8-bit-wide register. Figure 42 shows the

various operations under the control of Mode Register 4.

MR4 BIT DESCRIPTION

Output Select (MR40)

Sleep Mode Control (MR46)

When this bit is set to 1, sleep mode is enabled. With this mode

enabled, power consumption of the ADV7170/ADV7171 is

reduced to typically 200 nA. The I²C registers can be written to

and read from when the ADV7170/ADV7171 are in sleep

mode. If MR46 is set to a 0 when the device is in sleep mode,

the ADV7170/ADV7171 come out of sleep mode and resume

This bit specifies if the part is in composite video mode or

RGB/YUV mode. Note that in RGB/YUV mode the composite

signal is still available.

RGB/YUV Control (MR41)

This bit enables the output from the RGB DACs to be set to

YUV output video standard.

RESET

normal operation. Also, if the

signal is applied during

sleep mode, the ADV7170/ADV7171 come out of sleep mode

and resume normal operation.

RGB Sync (MR42)

This bit is used to set up the RGB outputs with the sync

information encoded on all RGB outputs.

Reserved (MR47)

A Logic Level 0 should be written to this bit.

_3H (MR43)

VSYNC

TIMING MODE REGISTER 0 (TR07 TO TR00)

(Address [SR4 to SR0] = 07H)

When this bit is enabled (1) in slave mode, it is possible to

VSYNC

drive the

active low input for 2.5 lines in PAL mode and

3 lines in NTSC mode. When this bit is enabled in master

Figure 43 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to.

VSYNC

mode, the ADV7170/ADV7171 output an active low

signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.

Pedestal Control (MR44)

This bit specifies whether a pedestal is to be generated on the

NTSC composite video signal. This bit is invalid if the

ADV7170/ADV7171 are configured in PAL mode.

Rev. C | Page 33 of 64

ADV7170/ADV7171

TR07

TR06

TR05

TR04

TR03

TR02

TR01

TR00

TIMING

REGISTER RESET

MASTER/SLAVE

CONTROL

BLANK INPUT

CONTROL

TR03

TR00

TR07

0

1

ENABLE

DISABLE

0

1

SLAVE TIMING

MASTER TIMING

PIXEL PORT

CONTROL

TIMING MODE

SELECTION

LUMA DELAY

TR05 TR04

TR06

TR02 TR01

0

1

0

1

0

1

0ns DELAY

0

1

8 BIT

16 BIT

0

1

0

1

0

1

MODE 0

74ns DELAY

148ns DELAY

222ns DELAY

MODE 1

MODE 2

MODE 3

Figure 43. Timing Register 0

TIMING MODE REGISTER 1 (TR17 TO TR10)

(Address (SR4 to SR0) = 08H)

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

Timing Register 1 is an 8-bit-wide register.

This bit controls whether the ADV7170/ADV7171 is in

Master or Slave Mode.

Figure 44 shows the various operations under the control of

Timing Register 1. This register can be read from as well written

to. This register can be used to adjust the width and position of

the master mode timing signals.

Timing Mode Selection (TR02 to TR01)

These bits control the timing mode of the ADV7170/ ADV7171.

These modes are described in more detail in

the Timing and Control section.

TR1 BIT DESCRIPTION

HSYNC Width (TR11 to TR10)

BLANK Control (TR03)

HSYNC

These bits adjust the

HSYNC to FIELD/VSYNC Delay (TR13 to TR12)

HSYNC

pulse width.

BLANK

This bit controls whether the

part is in slave mode.

input is used when the

Luma Delay (TR05 to TR04)

These bits adjust the position of the

VSYNC

output relative to

These bits control the addition of a luminance delay. Each bit

represents a delay of 74 ns.

the FIELD/

output.

HSYNC to FIELD Rising Edge Delay (TR15 to TR14)

Pixel Port Control (TR06)

When the ADV7170/ADV7171 are in Timing Mode 1, these

bits adjust the position of the

FIELD output rising edge.

This bit is used to set the pixel port to accept 8-bit or 16-bit

data. If an 8-bit input is selected, the data will be set up on

Pin P7 to Pin P0.

HSYNC

output relative to the

VSYNC Width (TR15 to TR14)

When the ADV7170/ADV7171 are configured in Timing

VSYNC

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the

internal timing counters. This bit should be toggled after

power-up, reset or changing to a new timing mode.

Mode 2, these bits adjust the

pulse width.

HSYNC

to Pixel Data Adjust (TR17 to TR16)

HSYNC

This enables the

to be adjusted with respect to the pixel

data. This allows the Cr and Cb components to be swapped.

This adjustment is available in both master timing mode and

slave timing mode.

Rev. C | Page 34 of 64

ADV7170/ADV7171

TR17

TR16

TR15

TR14

TR13

TR12

TR11

TR10

HSYNC WIDTH

HSYNC TO PIXEL

DATA ADJUST

HSYNC TO

FIELD/VSYNC DELAY

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

T

TR11 TR10

A

TR17 TR16

T

TR13 TR12

B

0

1

0

1

0

1

1 × T

4 × T

PCLK

T

TR15 TR14

C

0

1

0

1

0

1

0 × T

1 × T

2 × T

3 × T

0

1

0

1

0

1

0 × T

4 × T

8 × T

PCLK

x

0

1

T

B

16 × T

PCLK

+ 32μs

B

128 × T

PCLK

16 × T

PCLK

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0

1

0

1

0

1

1 × T

4 × T

PCLK

16 × T

PCLK

128 × T

PCLK

TIMING MODE 1 (MASTER/PAL)

LINE 1

LINE 313

LINE 314

T

HSYNC

A

T

C

T

B

FIELD/VSYNC

Figure 44. Timing Register 1

SUBCARRIER FREQUENCY REGISTERS 0 TO 3

(FSC3 TO FSC0)

SUBCARRIER PHASE REGISTERS (FP7 TO FP0)

(Address [SR4 to SR0] = 0DH)

(Address [SR4 to SR00] = 09H to 0CH)

This 8-bit-wide register is used to set up the subcarrier phase.

Each bit represents 1.41°. For normal operation this register is

set to 00Hex.

These 8-bit-wide registers are used to set up the subcarrier

frequency. The value of these registers is calculated by using

the following equation, rounded to the nearest integer:

CLOSED CAPTIONING EVEN FIELD DATA

REGISTER 1 TO 0 (CED15 TO CED0)

(Address [SR4–SR0] = 0E to 0FH)

No.of Subcarrier Frequency ValuesinOne Lineof Video Line

No.of 27MHzClock Cyclesin OneVideoLine

× 2³²

These 8-bit-wide registers are used to set up the closed

captioning extended data bytes on even fields. Figure 46

shows how the high and low bytes are set up in the registers.

For example, in NTSC mode,

227.5

Subcarrier FrequencyValue =

× 2³²= 569408542d = 21F07C1Fh

1716

CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8

BYTE 1

Note that on power-up, F_SCRegister 0 is set to 16h. A value of 1F

as derived above is recommended.

CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0

BYTE 0

Figure 46. Closed Captioning Extended Data Register

Program as follows:

FSC Register 0: 1FH

FSC Register 2: 7CH

FSC Register 3: F0H

FSC Register 4: 21H

CLOSED CAPTIONING ODD FIELD DATA

REGISTERS 1 TO 0 (CCD15 TO CCD0)

(Subaddress [SR4 to SR0] = 10H to 11H)

These 8-bit-wide registers are used to set up the closed

captioning data bytes on odd fields. Figure 47 shows how the

high and low bytes are set up in the registers.

Figure 45 shows how the frequency is set up by the four registers.

SUBCARRIER

FREQUENCY FSC7 FSC6 FSC5

REG 0

FSC4

FSC3 FSC2 FSC1 FSC0

CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

BYTE 1

SUBCARRIER

FREQUENCY

REG 1

FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8

CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

BYTE 0

SUBCARRIER

FREQUENCY FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

REG 2

Figure 47. Closed Captioning Data Register

SUBCARRIER

FREQUENCY FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24

REG 3

Figure 45. Subcarrier Frequency Register

Rev. C | Page 35 of 64

ADV7170/ADV7171

TTXREQ Rising Edge Control (TC07 to TC04)

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS 3 TO 0 (PCE15 TO PCE0, PCO15

TO PCO0)/(TXE15 TO TXE0, TXO15 TO TXO0)

These bits control the position of the rising edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a maximum

of 15 CLOCK cycles. See Figure 59.

(Subaddress [SR4–SR0] = 12H to 15H)

TTXREQ Falling Edge Control (TC03 to TC00)

These 8-bit-wide registers are used to enable the NTSC

pedestal/PAL teletext on a line-by-line basis in the vertical

blanking interval for both odd and even fields. Figure 48 and

Figure 49 show the four control registers. A Logic Level 1 in any

of the bits of these registers has the effect of turning the pedestal

off on the equivalent line when used in NTSC. A Logic Level 1

in any of the bits of these registers has the effect of turning on

teletext on the equivalent line when used in PAL.

These bits control the position of the falling edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a max of

15 CLOCK cycles. This controls the active window for teletext

data. Increasing this value reduces the amount of teletext bits

below the default of 360. If Bit TC03 to Bit TC00 are 00Hex

when bits TC07 to TC04 are changed, the falling edge of

TTXREQ tracks that of the rising edge (that is, the time

between the falling and rising edge remains constant).

See Figure 59.

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCO7

PCO6 PCO5

PCO4 PCO3

PCO2

PCO1

PCO0

FIELD 1/3

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8

CGMS_WSS REGISTER 0 C/W0 (C/W07 TO C/W00)

(Address [SR4 to SR0] = 16H)

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

FIELD 2/4 PCE7

PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0

CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51

shows the operations under the control of this register.

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

C/W0 BIT DESCRIPTION

FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9

PCE8

CGMS Data Bits (C/W03 to C/W00)

Figure 48. Pedestal Control Registers

These four data bits are the final four bits of the CGMS data

output stream. Note it is CGMS data ONLY in these bit

positions; that is, WSS data does not share this location.

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0

FIELD 1/3

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8

CGMS CRC Check Control (C/W04)

When this bit is enabled (1), the last six bits of the CGMS data

(that is, the CRC check sequence) are calculated internally by

the ADV7170/ADV7171. If this bit is disabled (0), the CRC

values in the register are output to the CGMS data stream.

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0

FIELD 2/4

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

FIELD 2/4 TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9

TXE8

CGMS Odd Field Control (C/W05)

Figure 49. Teletext Control Registers

When this bit is set (1), CGMS is enabled for odd fields. Note

this is valid only in NTSC mode.

TELETEXT REQUEST CONTROL REGISTER TC07

(TC07 TO TC00)

CGMS Even Field Control (C/W06)

(Address [SR4 to SR0] = 19H)

When this bit is set (1), CGMS is enabled for even fields. Note

this is valid only in NTSC mode.

Teletext control register is an 8-bit-wide register. See Figure 50.

WSS Control (C/W07)

When this bit is set (1), wide screen signaling is enabled. Note

this is valid only in PAL mode.

Rev. C | Page 36 of 64

ADV7170/ADV7171

TC07

TC06

TC05

TC04

TC03

TC02

TC01

TC00

TTXREQ RISING EDGE CONTROL

TC07 TC06 TC05 TC04

TTXREQ FALLING EDGE CONTROL

TC03 TC02 TC01 TC00

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

Figure 50. Teletext Control Register

C/W07

C/W06

C/W05

C/W04

C/W03

C/W02

C/W01

C/W00

WIDE SCREEN

SIGNAL CONTROL

CGMS ODD FIELD

CONTROL

C/W03 – C/W00

C/W07

C/W05

CGMS DATA BITS

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

CGMS EVEN FIELD

CONTROL

CGMS CRC CHECK

CONTROL

C/W06

C/W04

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

Figure 51. CGMS_WSS Register 0

CGMS_WSS REGISTER 2 C/W1 (C/W27 TO C/W20)

(Address [SR4 to SR0] = 18H)

CGMS_WSS REGISTER 1 C/W1 (C/W17 TO C/W10)

(Address [SR4 to SR0] = 17H)

CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53

shows the operations under the control of this register.

CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52

shows the operations under the control of this register.

C/W2 BIT DESCRIPTION

CGMS/WSS Data Bits (C/W27 to C/W20)

C/W1 BIT DESCRIPTION

CGMS/WSS Data Bits (C/W15 to C/W10)

These bit locations are shared by CGMS data and WSS data. In

NTSC mode, these bits are CGMS data. In PAL mode, these bits

are WSS data.

These bit locations are shared by CGMS data and WSS data. In

NTSC mode, these bits are CGMS data. In PAL mode, these bits

are WSS data.

CGMS DATA BITS (C/W17 TO C/W16)

These bits are CGMS data bits only.

C/W17

C/W16

C/W15

C/W14

C/W13

C/W12

C/W11

C/W10

C/W17 – C/W16

CGMS DATA BITS

C/W15 – C/W10

CGMS/WSS DATA BITS

Figure 52. CGMS_WSS Register 1

C/W27

C/W26

C/W25

C/W24

C/W23

C/W22

C/W21

C/W20

C/W27 – C/W20

CGMS/WSS DATA BITS

Figure 53. CGMS_ WSS Register 2

Rev. C | Page 37 of 64

ADV7170/ADV7171

APPENDICES

Supply Decoupling

APPENDIX 1—BOARD DESIGN

AND LAYOUT CONSIDERATIONS

For optimum performance, bypass capacitors should be

installed using the shortest leads possible, consistent with

reliable operation, to reduce the lead inductance. Best

performance is obtained with 0.1 μF ceramic capacitor

decoupling. Each group of V_AApins on the ADV7170/

ADV7171 must have at least one 0.1 μF decoupling capacitor

to GND. These capacitors should be placed as close as possible

to the device.

The ADV7170/ADV7171 are highly integrated circuits

containing both precision analog and high speed digital

circuitry. They have been designed to minimize interference

effects of the high speed digital circuitry on the integrity of the

analog circuitry. It is imperative that these same design and

layout techniques be applied to the system level design so that

high speed, accurate performance is achieved. Figure 54 shows

the analog interface between the device and monitor.

It is important to note that while the ADV7170/ADV7171

contain circuitry to reject power supply noise, this rejection

decreases with frequency. If a high frequency switching power

supply is used, the designer should pay close attention to

reducing power supply noise and consider using a three-

terminal voltage regulator for supplying power to the analog

power plane.

The layout should be optimized for lowest noise on the

ADV7170/ADV7171 power and ground lines by shielding the

digital inputs and providing good decoupling. The lead length

between groups of V_AAand GND pins should be minimized to

minimize inductive ringing.

Ground Planes

Digital Signal Interconnect

The ground plane should encompass all ADV7170/ADV7171

ground pins, voltage reference circuitry, power supply bypass

circuitry for the ADV7170/ADV7171, the analog output traces,

and all the digital signal traces leading up to the ADV7170/

ADV7171. The ground plane is the board’s common ground

plane.

The digital inputs to the ADV7170/ADV7171 should be isolated

as much as possible from the analog outputs and other analog

circuitry. Also, these input signals should not overlay the analog

power plane.

Due to the high clock rates involved, long clock lines to the

ADV7170/ADV7171 should be avoided to reduce noise pickup.

Power Planes

The ADV7170, the ADV7171, and any associated analog

circuitry should each have its own power plane, referred to

as the analog power plane (V_AA). This power plane should be

connected to the regular PCB power plane (V_CC) at a single

point through a ferrite bead. This bead should be located within

three inches of the ADV7170/ADV7171.

Any active termination resistors for the digital inputs should be

connected to the regular PCB power plane (V_CC) and not to the

analog power plane.

Analog Signal Interconnect

The ADV7170/ADV7171 should be located as close as possible

to the output connectors to minimize noise pickup and

reflections due to impedance mismatch.

The metallization gap separating device power plane and board

power plane should be as narrow as possible to minimize the

obstruction to the flow of heat from the device into the general

board.

The video output signals should overlay the ground plane, not

the analog power plane, to maximize the high frequency power

supply rejection.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7170/ADV7171 power pins and voltage

reference circuitry.

Digital inputs, especially pixel data inputs and clocking signals,

should never overlay any of the analog signal circuitry and

should be kept as far away as possible.

For best performance, the outputs should each have a 75 Ω load

resistor connected to GND. These resistors should be placed as

close as possible to the ADV7170/ADV7171 to minimize

reflections.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane unless they can be

arranged so that the plane-to-plane noise is common-mode.

The ADV7170/ADV7171 should have no inputs left floating.

Any inputs that are not required should be tied to ground.

Rev. C | Page 38 of 64

ADV7170/ADV7171

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

0.1μF

0.01μF

L1

(FERRITE BEAD)

5V (V

)

AA

5V

V

5V (V

)

5V (V

)

AA

10μF

33μF

1, 11, 20, 28, 30

CC

GND

0.1μF

V

AA

25

33

COMP

27

DAC D

DAC C

V

REF

75Ω

ADV7170/

ADV7171

38–42,

2–9, 12–14

26

31

32

5V (V

)

P15–P0

S-VIDEO

AA

4kΩ

RESET

DAC B

DAC A

35

15

SCRESET/RTC

HSYNC

100nF

UNUSED

INPUTS

SHOULD BE

GROUNDED

16

17

22

37

FIELD/VSYNC

BLANK

5V (V

)

CC

5V (V

)

5V (V

)

CC

RESET

100kΩ

5kΩ

TTX

TTXREQ

100Ω

TTX

23

24

34

SCLOCK

SDATA

MPU BUS

36

44

TTXREQ

CLOCK

100kΩ

R

SET

5V (V

)

AA

ALSB

18

GND

150Ω

TELETEXT PULL-UP AND

PULL-DOWN RESISTORS

SHOULD ONLY BE USED

IF THESE PINS ARE NOT

CONNECTED

10kΩ

10, 19, 21,

29, 43

27MHz CLOCK

(SAME CLOCK AS USED BY

MPEG2 DECODER)

Figure 54. Recommended Analog Circuit Layout

HSYNC

The circuit in Figure 55 can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the

pulse. This waveform is

guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if a 13.5 MHz

clock is required by the MPEG decoder. This guarantees that the Cr and Cb pixel information is input to the ADV7170/ADV7171 in the

correct sequence.

D

Q

13.5MHz

D

Q

CLOCK

HSYNC

CK

Figure 55. Circuit to Generate 13.5 MHz

Rev. C | Page 39 of 64

ADV7170/ADV7171

FCC Code of Federal Regulations (CFR) 47 Section 15.119 and

EIA608 describe the closed captioning information for Line 21

and Line 284.

APPENDIX 2—CLOSED CAPTIONING

The ADV7170/ADV7171 support closed captioning, conform-

ing to the standard television synchronizing waveform for color

transmission. Closed captioning is transmitted during the

blanked active line time of the odd fields Line 21 and the even

fields Line 284.

The ADV7170/ADV7171 use a single buffering method. This

means that the closed captioning buffer is only one byte deep;

therefore, there is no frame delay in outputting the closed

captioning data, unlike other 2-byte deep buffering systems.

The data must be loaded at least one line before (Line 20 or

Line 283) it is outputted on Line 21 and Line 284. A typical

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency- and phase-locked to the caption data. After the clock

run-in signal, the blanking level is held for two data bits and is

followed by a Logic Level 1 start bit. 16 bits of data follow the

start bit. These consist of two 8-bit bytes, seven data bits and

one odd parity bit. The data for these bytes is stored in Closed

Captioning Data Register 0 and Closed Captioning Data

Register 1.

VSYNC

implementation of this method is to use

to interrupt a

microprocessor, which in turn loads the new data (two bytes) in

every field. If no new data is required for transmission, you

must insert zeros in both the data registers; this is called

nulling. It is also important to load control codes, all of which

are double bytes, on Line 21, or a TV does not recognize them.

If you have a message like “Hello World,” which has an odd

number of characters, it is important to pad it out to an even

number to get end-of-caption, 2-byte control code to land in

the same field.

The ADV7170/ADV7171 also support the extended closed

captioning operation, which is active during even fields and is

encoded on scan Line 284. The data for this operation is stored

in Closed Captioning Extended Data Register 0 and Closed

Captioning Extended Data Register 1.

All clock run-in signals and timing to support closed captioning

on Line 21 and Line 284 are automatically generated by the

ADV7170/ADV7171. All pixel inputs are ignored during

Line 21 and Line 284.

10.5 ± 0.25μs

12.91μs

7 CYCLES

OF 0.5035MHz

(CLOCK RUN-IN)

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

R

I

T

Y

S

T

A

R

T

P

A

R

I

T

Y

D0–D6

50 IRE

40 IRE

BYTE 1

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003μs

27.382μs

33.764μs

Figure 56. Closed Captioning Waveform (NTSC)

Rev. C | Page 40 of 64

ADV7170/ADV7171

APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)

The ADV7170/ADV7171 support copy generation management systems (CGMS) conforming to the standard. CGMS data is transmitted

on Line 20 of the odd fields and Line 283 of even fields. Bit C/W05 and Bit C/W06 control whether or not CGMS data is output on odd

and even fields. CGMS data can only be transmitted when the ADV7170/ADV7171 are configured in NTSC mode.

The CGMS data is 20 bits long; the function of each of these bits is shown below. The CGMS data is preceded by a reference pulse of the

same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers in the following order:

C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12,

C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5,

C/W26 = C6, C/W27 = C7.

If the Bit C/W04 is set to a Logic Level 1, the last six bits, C19 to C14, which comprise the 6-bit CRC check sequence, are calculated

automatically on the ADV7170/ADV7171 based on the lower 14 bits (C0 to C13) of the data in the data registers and output with the

remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial

X⁶+ X + 1 with a preset value of 111111. If C/W04 is set to a Logic Level 0, all 20 bits (C0 to C19) are directly output from the CGMS

registers (no CRC is calculated; it must be calculated by the user).

Function of CGMS Bits

Word 0

Word 1

Word 2

CRC

–

6 Bits

4 Bits

6 Bits

CRC Polynomial = X⁶+ X + 1 (Preset to 111111)

0

Word 0

B1

1

Aspect Ratio

Display Format

Undefined

16:94:3

B2

Letterbox

Normal

B3

Word 0

B4, B5, B6

Word 1

Identification information about video and other signals (for example, audio)

Identification signal incidental to Word 0

B7, B8, B9, B10

Word 2

B11, B12, B13, B14

Identification signal and information incidental to Word 0

+100 IRE

+70 IRE

CRC SEQUENCE

REF

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

0 IRE

49.1μs ± 0.5μs

–40 IRE

11.2μs

2.235μs ± 20ns

Figure 57. CGMS Waveform Diagram

Rev. C | Page 41 of 64

ADV7170/ADV7171

APPENDIX 4—WIDE SCREEN SIGNALING

The ADV7170/ADV7171 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23.

WSS data can only be transmitted when the ADV7170/ADV7171 are configured in PAL mode. The WSS data is 14 bits long; the function

of each of these bits is as shown below.

The WSS data is preceded by a run-in sequence and a start code (see Figure 58). The bits are output from the configuration registers in

the following order:

C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8,

C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13.

If Bit C/W07 is set to a Logic Level 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 μs from the

HSYNC

falling edge of

) is available for the insertion of video.

Function of CGMS Bits

Bit 0 to Bit 2

Aspect Ratio/Format/Position

Bit 3 is odd parity check of Bit 0 to Bit 2

B0

0

B1

0

B2

0

B3

1

Aspect Ratio

4:3

Format

Position

Nonapplicable

Center

Full format

Letterbox

Full format

Nonapplicable

1

0

14:9

0

1

0

14:9

Top

1

0

1

16:9

Center

0

1

0

16:9

Top

1

0

1

>16:9

14:9

Center

0

1

Center

1

0

16:9

Nonapplicable

B4

0

1

B5

0

B9

0

1

0

1

B10

Camera Mode

Film Mode

0

1

No open subtitles

Subtitles in active image area

Subtitles out of active image area

Reserved

Standard Coding

1

B6

0

Motion Adaptive Color Plus

B11

0

1

No surround sound information

Surround sound mode

RESERVED

No Helper

1

B7

Modulated Helper

RESERVED

B12

B13

RESERVED

500mV

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

11.0μs

38.4μs

42.5μs

Figure 58. WSS Waveform Diagram

Rev. C | Page 42 of 64

ADV7170/ADV7171

Teletext Protocol

APPENDIX 5—TELETEXT INSERTION

The relationship between the TTX bit clock (6.9375 MHz) and

the system CLOCK (27 MHz) for 50 Hz is as follows:

The t_PDis the time needed by the ADV7170/ADV7171 to

interpolate input data on TTX and insert it onto the CVBS

or Y outputs, such that it appears t_SYNTTXOUT= 10.2 μs after the

leading edge of the horizontal signal. Time TTX_DELis the

pipeline delay time by the source that is gated by the TTXREQ

signal in order to deliver TTX data.

(27 MHz/4) = 6.75 MHz

(6.9375 × 10⁶/6.75 × 10⁶) = 1.027777

Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and

each bit has a width of nearly four clock cycles. The ADV7170/

ADV7171 use an internal sequencer and variable phase

interpolation filter to minimize the phase jitter and thus

generate a bandlimited signal that can be output on the CVBS

and Y outputs.

With the programmability offered with the TTXREQ signal on

the rising/falling edges, the TTX data is always inserted at the

correct position of 10.2 μs after the leading edge of horizontal

sync pulse, thus enabling a source interface with variable

pipeline delays.

The width of the TTXREQ signal must always be maintained to

allow the insertion of 360 (to comply with the Teletext Standard

of PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/sec;

this is achieved by setting TC03 to TC00 to 0. The insertion

window is not open if the teletext enable bit (MR35) is set to 0.

At the TTX input, the bit duration scheme repeats after every 37

TTX bits or 144 clock cycles. The protocol requires that TTX

Bit 10, Bit 19, Bit 28, and Bit 37 are carried by three clock cycles;

all other bits are carried by four clock cycles. After 37 TTX bits,

the next bits with three clock cycles are Bit 47, Bit 56, Bit 65,

and Bit 74. This scheme holds for all following cycles of 37 TTX

bits, until all 360 TTX bits are completed. All teletext lines are

implemented in the same way. Individual control of teletext

lines is controlled by teletext setup registers.

45 BYTES (360 BITS) – PAL

ADDRESS AND DATA

TELETEXT VBI LINE

RUN-IN CLOCK

Figure 59. Teletext VBI Line

t_SYNTTXOUT

CVBS/Y

HSYNC

t_PD

10.2μs

TTX

DATA

TTX

DEL

TTXREQ

PROGRAMMABLE PULSE EDGES

TTX

ST

t_SYNTTXOUT= 10.2μs

t_PD= PIPELINE DELAY THROUGH ADV7170/ADV7171

TTX

= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

DEL

Figure 60. Teletext Functionality Diagram

Rev. C | Page 43 of 64

ADV7170/ADV7171

APPENDIX 6—WAVEFORMS

NTSC Waveforms (with Pedestal)

+130.8 IRE

+100 IRE

1268.1mV

1048.4mV

PEAK COMPOSITE

REF WHITE

714.2mV

+7.5 IRE

0 IRE

387.6mV

334.2mV

BLACK LEVEL

BLANK LEVEL

48.3mV

SYNC LEVEL

–40 IRE

Figure 61. NTSC Composite Video Levels

+100 IRE

1048.4mV

REF WHITE

714.2mV

+7.5 IRE

0 IRE

387.6mV

334.2mV

BLACK LEVEL

BLANK LEVEL

48.3mV

SYNC LEVEL

–40 IRE

Figure 62. NTSC Luma Video Levels

PEAK CHROMA

963.8mV

629.7mV p-p

286mV p-p

BLANK/BLACK LEVEL

PEAK CHROMA

650mV

335.2mV

0mV

Figure 63. NTSC Chroma Video Levels

+100 IRE

1052.2mV

REF WHITE

720.8mV

+7.5 IRE

0 IRE

387.5mV

331.4mV

BLACK LEVEL

BLANK LEVEL

45.9mV

SYNC LEVEL

–40 IRE

Figure 64. NTSC RGB Video Levels

Rev. C | Page 44 of 64

ADV7170/ADV7171

NTSC Waveforms (without Pedestal)

+130.8 IRE

+100 IRE

1289.8mV

1052.2mV

PEAK COMPOSITE

REF WHITE

714.2mV

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

0 IRE

–40 IRE

Figure 65. NTSC Composite Video Levels

+100 IRE

REF WHITE

1052.2mV

714.2mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

–40 IRE

Figure 66. NTSC Luma Video Levels

978mV

PEAK CHROMA

694.9mV p-p

286mV p-p

650mV

BLANK/BLACK LEVEL

PEAK CHROMA

299.3mV

0mV

Figure 67. NTSC Chroma Video Levels

+100 IRE

1052.2mV

REF WHITE

715.7mV

BLANK/BLACK LEVEL

SYNC LEVEL

336.5mV

51mV

0 IRE

–40 IRE

Figure 68. NTSC RGB Video Levels

Rev. C | Page 45 of 64

ADV7170/ADV7171

PAL Waveforms

PEAK COMPOSITE

REF WHITE

1284.2mV

1047.1mV

696.4mV

350.7mV

50.8mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 69. PAL Composite Video Levels

1047mV

REF WHITE

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

350.7mV

50.8mV

Figure 70. PAL Luma Video Levels

989.7mV

650mV

PEAK CHROMA

672mV p-p

300mV p-p

BLANK/BLACK LEVEL

PEAK CHROMA

317.7mV

0mV

Figure 71. PAL Chroma Video Levels

1050.2mV

REF WHITE

698.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

351.8mV

51mV

Figure 72. PAL RGB Video Levels

Rev. C | Page 46 of 64

ADV7170/ADV7171

UV Waveforms

+505mV

+423mV

+334mV

BETACAM LEVEL

0mV

+171mV

+82mV

BETACAM LEVEL

0mV

–82mV

0mV

–171mV

–334mV

–423mV

–505mV

Figure 76. NTSC 100% Color Bars, No Pedestal V Levels

Figure 73. NTST 100% Color Bars, No Pedestal U Levels

+467mV

+391mV

+309mV

BETACAM LEVEL

+158mV

+76mV

BETACAM LEVEL

0mV

–76mV

0mV

–158mV

–391mV

–309mV

–467mV

Figure 74. NTSC 100% Color Bars with Pedestal U Levels

Figure 77. NTSC 100% Color Bars with Pedestal V Levels

+350mV

+293mV

+232mV

SMPTE LEVEL

+57mV

+118mV

0mV

SMPTE LEVEL

–57mV

0mV

–118mV

–293mV

–232mV

–350mV

Figure 75. PAL 100% Color Bars, U Levels

Figure 78. PAL 100% Color Bars, V Levels

Rev. C | Page 47 of 64

ADV7170/ADV7171

APPENDIX 7—OPTIONAL OUTPUT FILTER

APPENDIX 8—OPTIONAL DAC BUFFERING

If an output filter is required for the CVBS, Y, UV, Chroma, and

RGB outputs of the ADV7170/ADV7171, the filter shown in

Figure 79 can be used. Plots of the filter characteristics are

shown in Figure 80. An output filter is not required if the

outputs of the ADV7170/ADV7171 are connected to most

analog monitors or analog TVs. However, if the output signals

are applied to a system where sampling is used (for example,

digital TVs), then a filter is required to prevent aliasing.

When external buffering of the ADV7170/ADV7171 DAC

outputs is needed, the configuration in Figure 81 is recom-

mended. This configuration shows the DAC outputs running

at half (18 mA) their full current (36 mA) capability. This allows

the ADV7170/ADV7171 to dissipate less power; the analog

current is reduced by 50ꢀ with a R_SETof 300 Ω and a R_LOADof

75 Ω. This mode is recommended for 3.3 V operation, because

optimum performance is obtained from the DAC outputs at

18 mA with a V_AAof 3.3 V. This buffer also adds extra isolation

on the video outputs (see the buffer circuit in Figure 82).

22pF

When calculating absolute output full-scale current and voltage,

use the following equations:

1.8μH

FILTER I/P

FILTER O/P

270pF

330pF

75R

V_OUT= I_OUT× R_LOAD

(

V_REF× K

R_SET

)

I_OUT

=

Figure 79. Output Filter

K = 4.2146 constant,V_REF=1.235V

0

10

20

30

40

50

60

70

V

AA

ADV7170/ADV7171

OUTPUT

BUFFER

V

REF

DAC A

DAC B

DAC C

DAC D

CVBS

OUTPUT

BUFFER

CVBS

PIXEL

PORT

DIGITAL

CORE

OUTPUT

BUFFER

LUMA

R

SET

OUTPUT

BUFFER

300Ω

CHROMA

80

100k

1M

10M

FREQUENCY (Hz)

100M

Figure 80. Output Filter Plot

Figure 81. Output DAC Buffering Configuration

V

+

CC

5

4

3

OUTPUT TO

TV MONITOR

1

AD8061

INPUT/

OPTIONAL

FILTER O/P

2

V

–

CC

Figure 82. Recommended Output DAC Buffer

Rev. C | Page 48 of 64

ADV7170/ADV7171

output and the internal color bar generator is switched off. In

the examples shown, the timing mode is set to Mode 0 in slave

format. TR02 to TR00 of the Timing Register 0 control the

timing modes. For a detailed explanation of each bit in the

command registers, please see the Register Programming

section. TR07 should be toggled after setting up a new timing

mode. Timing Register 1 provides additional control over the

position and duration of the timing signals. In the examples,

this register is programmed in default mode.

APPENDIX 9—RECOMMENDED REGISTER VALUES

The ADV7170/ADV7171 registers can be set depending on the

user standard required.

The following examples give the various register formats for

several video standards.

In each case, the output is set to composite o/p with all DACs

BLANK

powered up and with the

input control disabled.

Additionally, the burst and color information are enabled on the

Table 13. PAL B/D/G/H/I (F_SC= 4.43361875 MHz)

Table 14. PAL M (F_SC= 3.57561149 MHz)

Address

00Hex

01Hex

02Hex

03Hex

04Hex

07Hex

08Hex

09Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Data

Address

00Hex

01Hex

02Hex

03Hex

04Hex

07Hex

08Hex

09Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Data

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Register 0

05Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Register 0

02Hex

00Hex

A3Hex

EFHex

E6Hex

21Hex

00Hex

CGMS_WSS Register 1

CGMS_WSS Register 2

Teletext Request Control Register

CGMS_WSS Register 1

CGMS_WSS Register 2

Teletext Request Control Register

Rev. C | Page 49 of 64

ADV7170/ADV7171

Table 15. PAL N (F_SC= 4.43361875 MHz)

Table 17. Power-Up Reset Values NTSC (F_SC= 3.5795454 MHz)

Address

Data

Address

00Hex

01Hex

02Hex

03Hex

04Hex

07Hex

08Hex

09Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Data

00Hex

01Hex

02Hex

03Hex

04Hex

07Hex

08Hex

09Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Register 0

05Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Register 0

00Hex

58Hex

00Hex

10Hex

00Hex

16Hex

7CHex

F0Hex

21Hex

00Hex

CGMS_WSS Register 1

CGMS_WSS Register 2

Teletext Request Control Register

CGMS_WSS Register 1

CGMS_WSS Register 2

Teletext Request Control Register

Table 16. PAL60 (F_SC= 4.43361875 MHz)

Address

Data

00Hex

01Hex

02Hex

03Hex

04Hex

07Hex

08Hex

09Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Register 0

04Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

CGMS_WSS Register 1

CGMS_WSS Register 2

Teletext Request Control Register

Rev. C | Page 50 of 64

ADV7170/ADV7171

APPENDIX 10—OUTPUT WAVEFORMS

0.6

0.4

0.2

0.0

–0.2

L608

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 0.00dB

APL = 39.1%

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = SOURCE

625 LINE PAL

NO FILTERING

SLOW CLAMP TO 0.00V AT 6.72

μs

FRAMES SELECTED: 1 2 3 4

Figure 83. 100/0/75/0 PAL Color Bars

0.5

0.0

L575

0.0

10.0

20.0

30.0

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

40.0

50.0

60.0

70.0

APL NEEDS SYNC = SOURCE!

SOUND-IN-SYNC OFF

SYNC = A

625 LINE PAL

NO FILTERING

SLOW CLAMP TO 0.00V AT 6.72μs

FRAMES SELECTED: 1

Figure 84. 100/0/75/0 PAL Color Bars Luminance

Rev. C | Page 51 of 64

ADV7170/ADV7171

0.5

0.0

–0.5

L575

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NO BRUCH SIGNAL

APL NEEDS SYNC = SOURCE!

625 LINE PAL NO FILTERING

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = A

SLOW CLAMP TO 0.00V AT 6.72μs

FRAMES SELECTED: 1

Figure 85. 100/0/75/0 Pal Color Bars Chrominance

100.0

0.5

50.0

0.0

F1

L76

–50.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

APL = 44.6%

PRECISION MODE OFF

SYNCHRONOUS

525 LINE NTSC

NO FILTERING

SYNC = A

SLOW CLAMP TO 0.00V AT 6.72

μ

s

FRAMES SELECTED: 1 2

Figure 86. 100/7.5/75/7.5 NTSC Color Bars

Rev. C | Page 52 of 64

ADV7170/ADV7171

0.6

0.4

0.2

50.0

0.0

–0.2

F2

L238

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL = 44.7%

PRECISION MODE OFF

525 LINE NTSC

NO FILTERING

SYNCHRONOUS

SYNC = SOURCE

SLOW CLAMP TO 0.00V AT 6.72μs

FRAMES SELECTED: 1 2

Figure 87. 100/7.5/75/7.5 NTSC Color Bars Luminance

0.4

50.0

0.2

0.0

–0.2

–50.0

–0.4

F1

L76

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC = SOURCE!

PRECISION MODE OFF

SYNCHRONOUS

525 LINE NTSC

NO FILTERING

SYNC = B

SLOW CLAMP TO 0.00V AT 6.72μs

FRAMES SELECTED: 1 2

Figure 88. 100/7.5/75/7.5 NTSC Color Bars Chrominance

Rev. C | Page 53 of 64

ADV7170/ADV7171

V

APL = 39.6%

SYSTEM LINE L608

ANGLE (DEG) 0.0

GAIN × 1.000 0.000dB

625 LINE PAL

BURST FROM SOURCE

DISPLAY +V AND –V

cy

R

g

M

g

75%

100%

YI

b

U

yl

B

G

Cy

m

g

r

SOUND IN SYNC OFF

Figure 89. PAL Vector Plot

R–Y

APL = 45.1%

SYSTEM LINE L76F1

ANGLE (DEG) 0.0

GAIN × 1.000 0.000dB

525 LINE NTSC

BURST FROM SOURCE

cy

I

R

M

g

Q

YI

b

100%

B–Y

75%

B

G

Cy

–Q

–I

SETUP 7.5%

Figure 90. NTSC Vector Plot

Rev. C | Page 54 of 64

ADV7170/ADV7171

COLOR BAR (NTSC)

FIELD = 2 LINE = 28

LUMINANCE LEVEL (IRE)

WFM

→

FCC COLOR BAR

0.4

0.2

0.0

0.2

0.1

0.2

0.1

30.0

20.0

10.0

0.0

–10.0

CHROMINANCE LEVEL (IRE)

0.0 –0.2

1.0

–0.2

–0.3

–0.2

–0.3

0.0

–1.0

CHROMINANCE PHASE (DEG)

. . . . .

–0.1

–0.2

–0.1

–0.3

–0.2

- - - - -

0.0

–1.0

–2.0

GRAY

YELLOW

32

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

AVERAGE: 32

→

REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD

Figure 91. NTSC Color Bar Measurement

WFM →

DGDP (NTSC)

MOD 5 STEP

BLOCK MODE START F2 L64, STEP = 32, END = 192

DIFFERENTIAL GAIN (%)

MIN = –0.00 MAX = 0.11 p-p/MAX = 0.11

0.11 0.07

0.00

0.08

0.07

0.05

0.3

0.2

0.1

0.0

–0.1

DIFFERENTIAL PHASE (DEG)

0.00 0.03

MIN = 0.02 MAX = 0.14 p-p = 0.16

0.14 0.10

–0.02

0.10

0.20

0.15

0.10

0.05

–0.00

–0.05

–0.10

1ST

2ND

3RD

4TH

5TH

6TH

Figure 92. NTSC Differential Gain and Phase Measurement

Rev. C | Page 55 of 64

ADV7170/ADV7171

LUMINANCE NONLINEARITY (NTSC)

WFM →

5 STEP

FIELD = 2 LINE = 21

LUMINANCE NONLINEARITY (%)

p-p = 0.2

99.9

100.0

99.9

99.8

100.4

100.3

100.2

100.1

100.0

99.9

99.8

99.7

99.6

99.5

99.4

99.3

99.2

99.1

99.0

98.9

98.8

98.7

98.6

1ST

2ND

3RD

4TH

5TH

Figure 93. NTSC Luminance Nonlinearity Measurement

CHROMINANCE AM PM (NTSC)

FULL FIELD (BOTH FIELDS)

BANDWIDTH 100Hz TO 500kHz

WFM →

APPROPRIATE

AM NOISE

–68.4dB RMS

–75.0

–70.0

–65.0

–60.0

–55.0

–50.0

–45.0

–40.0

dB RMS

PM NOISE

–64.4dB RMS

–75.0

–70.0

–65.0

–60.0

–55.0

–50.0

–45.0

–40.0

dB RMS

(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)

Figure 94. NTSC AMPM Noise Measurement

Rev. C | Page 56 of 64

ADV7170/ADV7171

NOISE SPECTRUM (NTSC)

FIELD = 2 LINE = 64

AMPLITUDE (0dB = 714mV p-p)

BANDWIDTH 100kHz TO FULL

WFM →

PEDESTAL

NOISE LEVEL = –80.1dB RMS

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

–100.0

1.0

2.0

3.0

(MHz)

4.0

5.0

6.0

Figure 95. NTSC SNR Pedestal Measurement

NOISE SPECTRUM (NTSC)

FIELD = 2 LINE = 64

WFM →

RAMP SIGNAL

AMPLITUDE (0dB = 714mV p-p)

NOISE LEVEL = –61.7dB RMS

BANDWIDTH 10kHz TO FULL (TILT NULL)

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

–100.0

1.0

2.0

3.0

(MHz)

4.0

5.0

Figure 96. NTSC SNR Ramp Measurement

Rev. C | Page 57 of 64

ADV7170/ADV7171

PARADE SMPTE/EBU PAL

mV Y(A)

mV

250

Pb(B)

mV

Pr(C)

250

700

600

500

400

300

200

100

0

200

150

100

50

200

150

100

50

0

–50

–100

–150

–200

–250

–100

–200

–300

–150

–200

–250

Figure 97. PAL YUV Parade Plot

LIGHTNING

L183

COLORBARS: 75% SMPTE/EBU (50Hz)

Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR p-p 525.0mV

AVERAGE 32 → 32

YI

–274.82

0.93%

G

R

CY

88.31

0.28%

M

B

–173.24

0.19%

–88.36

0.19%

174.35

–0.65%

260.51

–0.14%

B–Y

W

YI

462.80

–0.50%

CY

864.78

–0.88%

YI

G

307.54

–0.21%

CY

M

216.12

–0.33%

R

M

R

156.63

–0.22%

B

61.00

1.92%

B

R

G

M

CY

YI

W

R–Y

CY

–262.17

–0.13%

G

B

YI

M

R

–218.70

–0.51%

–42.54

0.69%

41.32

212.28

–3.43%

252.74

–3.72%

–0.76%

COLOR Pk-Pk: B–Y 532.33mV

1.40%

R–Y 514.90mV

–1.92%

Pk-WHITE: 700.4mV (100%) SETUP –0.01%

DELAY: B–Y –6ns R–Y –6ns

Figure 98. PAL YUV Lighting Plot

Rev. C | Page 58 of 64

ADV7170/ADV7171

COMPONENT NOISE

LINE = 202

AMPLITUDE (0dB = 700mV p-p)

BANDWIDTH 10kHz TO 5.0MHz

NOISE dB RMS

0.0

–5.0

–10.0

–15.0

–20.0

–25.0

–30.0

–35.0

–40.0

–45.0

–50.0

–55.0

–60.0

–65.0

–70.0

–75.0

–80.0

–85.0

–90.0

–95.0

→

Y 82.1

Pb 82.3

Pr 83.3

–100.0

1.0

2.0

3.0

4.0

5.0

6.0

(MHz)

Figure 99. PAL YUV SNR Plot

COMPONENT MULTIBURST

LINE = 202

AMPLITUDE (0dB = 100% OF 688.1mV 683.4mV

668.9mV)

–0.68

(dB)

0.04

–0.02

–0.05

–2.58

–8.05

5.79

0.0

–5.0

Y

–10.0

0.49

0.99

2.00

3.99

4.79

–2.59

0.21

0.23

–0.78

–7.15

0.0

–5.0

Pb

–10.0

0.49

0.25

0.99

0.25

1.99

2.39

2.89

–0.77

–2.59

–7.13

0.0

–5.0

Pr

–10.0

0.49

0.99

1.99

2.39

2.89

(MHz)

Figure 100. PAL YUV Multiburst Response

Rev. C | Page 59 of 64

ADV7170/ADV7171

COMPONENT VECTOR SMPTE/EBU, 75%

R

M

g

YI

BK

B

G

CY

Figure 101. PAL YUV Vector Plot

mV

GREEN (A)

mV

BLUE (B)

mV

RED (C)

700

600

500

400

300

200

100

0

700

600

500

400

300

200

100

0

600

500

400

300

200

100

0

–100

–200

–300

–100

–200

–300

–100

–200

–300

Figure 102. PAL RGB Waveforms

Rev. C | Page 60 of 64

ADV7170/ADV7171

OUTLINE DIMENSIONS

14.15

13.90 SQ

13.65

1.03

0.88

0.73

2.45

MAX

34

44

1.95 REF

1

33

PIN 1

SEATING

PLANE

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

2.20

2.00

1.80

0.23

0.11

23

11

7°

0°

22

12

0.25 MIN

0.10

0.45

0.30

LEAD WIDTH

COPLANARITY

VIEW A

0.80 BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MO-112-AA-1

Figure 103. 44-Lead Thin Plastic Quad Flat Package [MQFP]

(S-44-2)

Dimensions shown in millimeters

1.20

MAX

12.00 BSC SQ

PIN 1

34

44

0.75

0.60

0.45

1

33

TOP VIEW

(PINS DOWN)

10.00

BSC SQ

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

11

23

3.5°

0°

0.08 MAX

COPLANARITY

0.15

0.05

12

VIEW A

22

SEATING

PLANE

0.80

BSC

LEAD PITCH

0.45

0.37

0.30

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ACB

Figure 104. 44-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-44)

Dimensions shown in millimeters

Rev. C | Page 61 of 64

ADV7170/ADV7171

13.45

1.03

0.88

0.73

13.20 SQ

12.95

2.45

MAX

34

44

1.60 REF

1

33

PIN 1

SEATING

PLANE

10.20

10.00 SQ

9.80

TOP VIEW

(PINS DOWN)

2.20

0.23

0.11

2.00

1.80

23

11

0.25

0.10

7°

0°

22

12

0.10

0.45

0.29

LEAD WIDTH

COPLANARITY

VIEW A

0.80 BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-022-AB-1

Figure 105. 44-Lead Metric Quad Flat Package [MQFP]

(S-44-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Descriptions

Package Options

S-44-2

SU-44

S-44-2

SU-44

ADV7170KSZ¹

44-Lead Metric Quad Flat Package [MQFP]

44-Lead Thin Plastic Quad Flat Package [TQFP]

44-Lead Metric Quad Flat Package [MQFP]

44-Lead Thin Plastic Quad Flat Package [TQFP]

44-Lead Metric Quad Flat Package [MQFP]

Evaluation Board

ADV7170KSZ-REEL¹

ADV7170KSUZ¹

ADV7170KSUZ-REEL¹

ADV7171KSZ¹

ADV7171KSZ-REEL¹

ADV7171KSUZ¹

ADV7171KSUZ-REEL¹

ADV7171WBSZ-REEL¹

EVAL-ADV7170EBM

EVAL-ADV7171EBM

S-44-1

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. C | Page 62 of 64

ADV7170/ADV7171

NOTES

Rev. C | Page 63 of 64

ADV7170/ADV7171

NOTES

Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent

Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips.

registered trademarks are the property of their respective owners.

Printed in the U.S.A.

D00221-0-3/09(C)

Rev. C | Page 64 of 64


型号：	ADV7171KSZ-REEL
厂家：	ADI
描述：	Digital PAL/NTSC Video Encoder 数字PAL / NTSC视频编码器转换器色度信号转换器消费电路商用集成电路编码器
文件：	总64页 (文件大小：865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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