ADV7171SU [ADI]
Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management; 数字PAL / NTSC视频编码器与10位SSAF⑩和高级电源管理
| 型号： | ADV7171SU |
| 厂家： | 
ADI |
| 描述： | Digital PAL/NTSC Video Encoder with 10-Bit SSAF⑩ and Advanced Power Management |
| 文件： | 总55页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Digital PAL/NTSC Video Encoder with 10-Bit
SSAF™ and Advanced Power Management
a
ADV7170/ADV7171*
Programmable Chroma Filters (Low-Pass [0.65 MHz,
FEATURES
1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)
Programmable VBI (Vertical Blanking Interval)
Programmable Subcarrier Frequency and Phase
Programmable LUMA Delay
Individual ON/OFF Control of Each DAC
CCIR and Square Pixel Operation
ITU-R BT601/656 YCrCb to PAL/NTSC Video Encoder
High Quality 10-Bit Video DACs
SSAF (Super Sub-Alias Filter)
Advanced Power Management Features
CGMS (Copy Generation Management System)
WSS (Wide Screen Signalling)
Integrated Subcarrier Locking to External Video Source
Color Signal Control/Burst Signal Control
Interlaced/Noninterlaced Operation
Complete On-Chip Video Timing Generator
Programmable Multimode Master/Slave Operation
Macrovision AntiTaping Rev 7.01 (ADV7170 Only)**
Closed Captioning Support
Simultaneous Y, U, V, C Output Format
NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60
Single 27 MHz Clock Required (
؋
2 Oversampling) 80 dB Video SNR
32-Bit Direct Digital Synthesizer for Color Subcarrier
Multistandard Video Output Support:
Composite (CVBS)
Component S-Video (Y/C)
Component YUV and RGB
EuroSCART Output (RGB + CVBS/LUMA)
Component YUV + CHROMA
Video Input Data Port Supports:
Teletext Insertion Port (PAL-WST)
On-Board Color Bar Generation
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C® Compatible and Fast I2C)
Single Supply +5 V or +3.3 V Operation
Small 44-Lead PQFP/TQFP Packages
CCIR-656 4:2:2 8-Bit Parallel Input Format
4:2:2 16-Bit Parallel Input Format
APPLICATIONS
SMPTE 170M NTSC-Compatible Composite Video
ITU-R BT.470 PAL-Compatible Composite Video
Programmable Simultaneous Composite
and S-Video or RGB (SCART)/YUV Video Outputs
Programmable Luma Filters (Low-Pass [PAL/NTSC])
Notch, Extended (SSAF, CIF and QCIF)
High Performance DVD Playback Systems, Portable
Video Equipment Including Digital Still Cameras and
Laptop PCs, Video Games, PC Video/Multimedia and
Digital Satellite/Cable Systems (Set-Top Boxes/IRD)
FUNCTIONAL BLOCK DIAGRAM
TTXREQ
TTX
M
10
U
POWER
MANAGEMENT
CONTROL
10
10-BIT
L
CGMS & WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
DACD(PIN 27)
DAC
T
YUV TO
RBG
MATRIX
V
AA
10
I
(SLEEP MODE)
10
10
10-BIT
DAC
P
L
E
X
E
R
DACC(PIN 26)
DACB(PIN 31)
10
RESET
10-BIT
DAC
10
8
PROGRAMMABLE
LUMINANCE
FILTER
9
8
Y
9
COLOR
DATA
P7–P0
INTER-
ADD
POLATOR
SYNC
4:2:2 TO
YCrCb
TO
YUV
4:4:4
INTER-
POLATOR
8
8
10
10
U
V
U
V
8
8
8
8
PROGRAMMABLE
CHROMINANCE
FILTER
P15–P8
10
INTER-
POLATOR
ADD
MATRIX
10-BIT
DAC
DACA(PIN 32)
BURST
8
8
ADV7170/ADV7171
10
10
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
REAL-TIME
CONTROL
CIRCUIT
V
REF
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
2
I C MPU PORT
R
SET
COMP
CLOCK
SCLOCK SDATA
ALSB
SCRESET/RTC
GND
*Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
**This device is protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available.
NOTE: ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
SSAF is a trademark of Analog Devices, Inc.
I2C is a registered trademark of Philips Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
ADV7170/ADV7171–SPECIFICATIONS
(VAA = +5 V ؎ 5%1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
5 V SPECIFICATIONS
Parameter
Conditions1
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
10
Bits
RSET = 300 Ω
Guaranteed Monotonic
±0.6
LSB
LSB
Differential Nonlinearity
±1
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
V
V
µA
pF
0.8
±1
VIN = 0.4 V or 2.4 V
Input Capacitance, CIN
10
10
DIGITAL OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
ANALOG OUTPUTS
Output Current3
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
33
0
34.7
5
1.5
37
mA
mA
%
V
kΩ
pF
Output Current4
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
+1.4
30
30
IOUT = 0 mA
VOLTAGE REFERENCE
Reference Range, VREF
IVREFOUT = 20 µA
1.142
4.75
1.235
5.0
1.327
V
V
POWER REQUIREMENTS5
VAA
5.25
155
90
Normal Power Mode
IDAC (max)6
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
150
20
75
mA
mA
mA
IDAC (min)6
7
ICCT
Low Power Mode
IDAC (max)6
80
20
75
mA
mA
mA
IDAC (min)6
7
ICCT
90
Sleep Mode
8
IDAC
ICCT
0.1
0.001
0.01
µA
µA
%/%
9
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3Full drive into 37.5 Ω doubly terminated load.
4Minimum drive current (used with buffered/scaled output load).
5Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
6IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual
DACs reduces IDAC correspondingly.
7ICCT (Circuit Current) is the continuous current required to drive the device.
8Total DAC current in Sleep Mode.
9Total continuous current during Sleep Mode.
Specifications subject to change without notice.
–2–
REV. 0
ADV7170/ADV7171
(V = +3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless otherwise noted.)
3.3 V SPECIFICATIONS
AA
Parameter
Conditions1
Min
Typ
Max
Units
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
10
Bits
RSET = 300 Ω
Guaranteed Monotonic
±0.6
LSB
LSB
Differential Nonlinearity
±1
DIGITAL INPUTS3
Input High Voltage, VINH
Input Low Voltage, VINL
2
V
V
µA
pF
0.8
±1
3, 4
Input Current, IIN
VIN = 0.4 V or 2.4 V
Input Capacitance, CIN
10
10
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
ANALOG OUTPUTS3
Output Current4, 5
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
33
0
34.7
5
2.0
37
mA
mA
%
V
kΩ
pF
Output Current6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
+1.4
30
30
IOUT = 0 mA
POWER REQUIREMENTS3, 7
VAA
3.0
3.3
3.6
V
Normal Power Mode
IDAC (max)8
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
150
20
35
155
mA
mA
mA
IDAC (min)8
9
ICCT
Low Power Mode
IDAC (max)8
80
20
35
mA
mA
mA
IDAC (min)8
9
ICCT
Sleep Mode
10
IDAC
ICCT
0.1
0.001
0.01
µA
µA
%/%
11
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
NOTES
11The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
12Temperature range TMIN to TMAX: 0°C to +70°C.
13Guaranteed by characterization.
14Full drive into 37.5 Ω load.
15DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω).
16Minimum drive current (used with buffered/scaled output load).
17Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 110°C.
18
I
is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual
DAC
DACs reduces IDAC correspondingly.
19
I
(Circuit Current) is the continuous current required to drive the device.
CCT
10Total DAC current in Sleep Mode.
11Total continuous current during Sleep Mode.
Specifications subject to change without notice.
REV. 0
–3–
ADV7170/ADV7171–SPECIFICATIONS
(VAA = +5 V ؎ 5%1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
5 V DYNAMIC SPECIFICATIONS
Parameter
Conditions1
Min
Typ
Max
Units
Differential Gain3, 4
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
0.3
0.4
1.0
1.0
80
70
60
0.7
0.7
2.0
2.0
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
±Degrees
±%
±%
ns
Differential Phase3, 4
Differential Gain3, 4
Differential Phase3, 4
SNR3, 4 (Pedestal)
SNR3, 4 (Pedestal)
SNR3, 4 (Ramp)
SNR3, 4 (Ramp)
Peak Periodic
58
Hue Accuracy3, 4
0.7
0.9
0.6
0.3
0.2
1.0
0.5
0.8
85
1.2
1.4
Color Saturation Accuracy3, 4
Chroma Nonlinear Gain3, 4
Chroma Nonlinear Phase3, 4
Chroma/Luma Intermod3, 4
Chroma/Luma Gain Inequality3, 4
Chroma/Luma Delay Inequality3, 4
Luminance Nonlinearity3, 4
Chroma AM Noise3, 4
Chroma PM Noise3, 4
Referenced to 40 IRE
0.5
0.4
1.4
2.0
1.4
±%
dB
dB
82
79
81
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3Guaranteed by characterization.
4The low pass filter only and guaranteed by design.
Specifications subject to change without notice.
(VAA = +3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
3.3 V DYNAMIC SPECIFICATIONS
Parameter
Conditions1
Min
Typ
Max
Units
Differential Gain3
Normal Power Mode
Normal Power Mode
Lower Power Mode
Lower Power Mode
RMS
Peak Periodic
RMS
1.0
0.5
0.6
0.5
78
70
60
%
Degrees
%
Degrees
dB rms
dB p-p
dB rms
dB p-p
Degrees
%
±%
dB
dB
±%
Differential Phase3
Differential Gain3
Differential Phase3
SNR3 (Pedestal)
SNR3 (Pedestal)
SNR3 (Ramp)
SNR3 (Ramp)
Peak Periodic
58
Hue Accuracy3
1.0
1.0
1.4
80
Color Saturation Accuracy3
Luminance Nonlinearity3, 4
Chroma AM Noise3, 4
Chroma PM Noise3, 4
Chroma Nonlinear Gain3, 4
Chroma Nonlinear Phase3, 4
Chroma/Luma Intermod3, 4
79
Referenced to 40 IRE
0.6
0.3
0.2
0.5
0.4
±Degrees
±%
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.
2Temperature range TMIN to TMAX: 0°C to +70°C.
3Guaranteed by characterization.
4These specifications are for the low-pass filter only and guaranteed by design. For other internal filters, see Figure 4.
Specifications subject to change without notice.
–4–
REV. 0
ADV7170/ADV7171
(VAA = 4.75 V – 5.25 V1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
5 V TIMING SPECIFICATIONS otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
0
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
0.6
1.3
0.6
0.6
100
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
7
0
ns
ns
CLOCK CONTROL AND
PIXEL PORT5, 6
fCLOCK
27
MHz
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
8
8
3.5
4
4
ns
ns
ns
ns
ns
ns
ns
ns
3
11
8
48
16
4
Digital Output Hold Time, t14
4
Pipeline Delay, t15
Clock Cycles
TELETEXT3, 4, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
20
2
6
ns
ns
ns
RESET CONTROL3, 4
RESET Low Time
6
ns
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
2Temperature range TMIN to TMAX: 0oC to +70oC.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
7Teletext Port consists of the following:
Teletext Output:
Teletext Input:
TTXREQ
TTX
Specifications subject to change without notice.
REV. 0
–5–
ADV7170/ADV7171–SPECIFICATIONS
(VAA = 3.0 V – 3.6 V1, VREF = 1.235 V, RSET = 150 ⍀. All specifications TMIN to TMAX2 unless
otherwise noted.)
3.3 V TIMING SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
MPU PORT3, 4
SCLOCK Frequency
0
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
0.6
1.3
0.6
0.6
100
After This Period the First Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
7
0
ns
ns
CLOCK CONTROL AND
PIXEL PORT4, 5, 6
fCLOCK
27
MHz
ns
ns
ns
ns
ns
ns
ns
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
Pipeline Delay, t15
8
8
3.5
4
4
3
12
8
48
ns
Clock Cycles
TELETEXT3, 4, 7
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
23
2
6
ns
ns
ns
RESET CONTROL3, 4
RESET Low Time
6
ns
NOTES
1The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.
2Temperature range TMIN to TMAX: 0oC to +70oC.
3TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. Analog output load ≤ 10 pF.
4Guaranteed by characterization.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
7Teletext Port consists of the following:
Teletext Output:
Teletext Input:
TTXREQ
TTX
Specifications subject to change without notice.
–6–
REV. 0
ADV7170/ADV7171
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t12
t9
t10
HSYNC,
FIELD/VSYNC,
CONTROL
I/PS
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
Y
t11
t13
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O/PS
t14
Figure 2. Pixel and Control Data Timing Diagram
TXTREQ
CLOCK
t16
t17
t18
TXT
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 3. Teletext Timing Diagram
REV. 0
–7–
ADV7170/ADV7171
ABSOLUTE MAXIMUM RATINGS1
Table I. Allowable Operating Conditions for KS and SU
Package Options
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . GND – 0.5 V to VAA
KS
SU
Conditions
3 V
5 V
3 V
5 V
4 DAC ON Double 75R1
4 DAC ON Low Power2
4 DAC ON Buffering3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
3 DAC ON Double 75R
3 DAC ON Low Power
3 DAC ON Buffering
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
2Analog output short circuit to any power supply or common can be of an indefinite
duration.
2 DAC ON Double 75R
2 DAC ON Low Power
4 DAC ON Buffering
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PACKAGE THERMAL PERFORMANCE
NOTES
The 44-PQFP package used for this device takes advantage of
an ADI patented thermal coastline lead frame construction. This
maximizes heat transfer into the leads and reduces the package
thermal resistance.
1DAC ON Double 75R refers to a condition where the DACs are terminated in
a double 75R load and low power mode is disabled.
2DAC ON Low Power refers to a condition where the DACs are terminated in a
double 75R load and low power mode is enabled.
3DAC ON Buffering refers to a condition where the DAC current is reduced to
5 mA and external buffers are used to drive the video load.
The junction-to-ambient (θJA) thermal resistance in still air on a
four-layer PCB is 35.5°C/W. The junction-to-case thermal resis-
tance (θJC) is 13.75°C/W.
ORDERING GUIDE
Temperature
Range
Package
Descriptions
Package
Options
Model
ADV7170KS
ADV7170SU
ADV7171KS
ADV7171SU
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Plastic Quad Flatpack
Thin Plastic Quad Flatpack
Plastic Quad Flatpack
Thin Plastic Quad Flatpack
S-44
SU-44
S-44
SU-44
PIN CONFIGURATIONS
42
44 43
PIN 1
41 40 39 38 37 36 35 34
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
V
V
REF
AA
IDENTIFIER
P5
P6
DAC A
DAC B
P7
V
AA
P8
GND
ADV7170/ADV7171
PQFP/TQFP
P9
V
AA
TOP VIEW
(Not to Scale)
P10
P11
P12
DAC D
26 DAC C
25 COMP
24 SDATA
GND 10
11
23
V
SCLOCK
AA
13
20
21 22
12
14 15 16 17 18 19
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7170/ADV7171 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–8–
REV. 0
ADV7170/ADV7171
PIN FUNCTION DESCRIPTIONS
Input/
Output
Mnemonic
Function
P15–P0
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0).
P0 represents the LSB.
CLOCK
I
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alter-
natively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
I/O
I/O
I/O
I
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level “0.”
This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It
can be configured as a subcarrier reset pin, in which case a high-to-low transition on this pin
will reset the subcarrier to Field 0. Alternatively, it may be configured as a Real-Time
Control (RTC) input.
FIELD/VSYNC
BLANK
SCRESET/RTC
VREF
RSET
I/O
I
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of
the video signals.
COMP
DAC A
O
O
Compensation Pin. Connect a 0.1 µF Capacitor from COMP to VAA. For Optimum Dynamic
Performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.
PAL/NTSC Composite Video Output. Full-Scale Output is 180 IRE (1286 mV) for NTSC
and 1300 mV for PAL.
DAC C
DAC D
DAC B
SCLOCK
SDATA
ALSB
O
O
O
I
I/O
I
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output
BLUE/Composite/U Analog Output.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal set up the LSB of the MPU address.
RESET
I
The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default
mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 × Composite and
S Video out and DAC B powered ON and DAC D powered OFF.
TTX/VAA
I
Teletext Data/Defaults to VAA when Teletext not Selected (enables backward compatibility to
ADV7175/ADV7176).
TTXREQ/GND
O
Teletext Data Request Signal/ Defaults to GND when Teletext not Selected (enables back-
ward compatibility to ADV7175/ADV7176).
VAA
GND
P
G
Power Supply (+3 V to +5 V).
Ground Pin.
REV. 0
–9–
ADV7170/ADV7171
three data paths. Y typically has a range of 16 to 235, Cr and
Cb typically have a range of 128 ± 112; however, it is possible
to input data from 1 to 254 on both Y, Cb and Cr. The ADV7170/
ADV7171 supports PAL (B, D, G, H, I, M, N) and NTSC
(with and without pedestal) standards. The appropriate
SYNC, BLANK and Burst levels are added to the YCrCb
data. Macrovision antitaping (ADV7170 only), closed-captioning
and Teletext levels are also added to Y and the resultant data is
interpolated to a rate of 27 MHz. The interpolated data is
filtered and scaled by three digital FIR filters.
GENERAL DESCRIPTION
The ADV7170/ADV7171 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 8 or 16-bit component
video data into a standard analog baseband television signal
compatible with worldwide standards.
The on-board SSAF (Super Sub-Alias Filter) with extended
luminance frequency response and sharp stopband attenuation,
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal control
of power consumption in both normal operating modes and
power-down or sleep modes.
The U and V signals are modulated by the appropriate sub-
carrier sine/cosine phases and added together to make up the
chrominance signal. The luma (Y) signal can be delayed 1–3
luma cycles (each cycle is 74 ns) with respect to the chroma
signal. The luma and chroma signals are then added together to
make up the composite video signal. All edges are slew rate
limited.
The ADV7170/ADV7171 also supports both PAL and NTSC
square pixel operation. The parts also incorporate WSS and
CGMS-A data control generation.
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
(and can generate) HSYNC, VSYNC and FIELD timing sig-
nals. These timing signals can be adjusted to change pulsewidth
and position while the part is in the master mode. The encoder
requires a single two times pixel rate (27 MHz) clock for stan-
dard operation. Alternatively, the encoder requires a 24.54 MHz
clock for NTSC or 29.5 MHz clock for PAL square pixel mode
operation. All internal timing is generated on-chip.
The YCrCb data is also used to generate RGB data with ap-
propriate SYNC and BLANK levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YUV data can be generated instead of RGB.
The four l0-bit DACs can be used to output:
1. Composite Video + RGB Video.
2. Composite Video + YUV Video.
3. Two Composite Video Signals + LUMA and CHROMA
(Y/C) Signals.
A separate teletext port enables the user to directly input tele-
text data during the vertical blanking interval.
Alternatively, each DAC can be individually powered off if not
required.
The ADV7170/ADV7171 modes are set up over a two-wire
serial bidirectional port (I2C Compatible) with two slave addresses.
Video output levels are illustrated in Appendix 6.
Functionally, the ADV7171 and ADV7170 are the same with
the exception that the ADV7170 can output the Macrovision
anticopy algorithm.
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response and a QCIF re-
sponse. The UV filter supports several different frequency re-
sponses, including four low-pass responses, a CIF response and
a QCIF response, these can be seen in the following Figures 4
to 18.
The ADV7170/ADV7171 is packaged in a 44-lead PQFP pack-
age and a 44-lead TQFP package.
DATA PATH DESCRIPTION
For PAL B, D, G, H, I, M, N and NTSC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 Compatible Pixel Port at a
27 MHz data rate. The pixel data is demultiplexed to form
STOPBAND
CUTOFF (MHz) ATTENUATION (dB)
STOPBAND
PASSBAND RIPPLE 3 dB BANDWIDTH
FILTER TYPE
FILTER SELECTION
MR04 MR03 MR02
(dB)
(MHz)
4.157
4.74
6.54
6.24
6.217
3.0
LOW PASS (NTSC)
LOW PASS (PAL)
NOTCH (NTSC)
NOTCH (PAL)
EXTENDED (SSAF)
CIF
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.091
0.15
0.015
0.095
0.051
0.018
MONOTONIC
7.37
7.96
8.3
8.0
8.0
7.06
7.15
–56
–64
–68
–66
–61
–61
–50
1.5
QCIF
Figure 4. Luminance Internal Filter Specifications
STOPBAND
CUTOFF (MHz) ATTENUATION (dB)
STOPBAND
PASSBAND RIPPLE 3 dB BANDWIDTH
FILTER TYPE
FILTER SELECTION
MR07 MR06 MR05
(dB)
(MHz)
1.395
0.65
1.0
1.3 MHz LOW PASS
0.65 MHz LOW PASS
1.0 MHZ LOW PASS
2.0 MHz LOW PASS
RESERVED
CIF
QCIF
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0.084
3.01
3.64
3.73
5.0
–45
–58.5
–49
MONOTONIC
MONOTONIC
0.0645
2.2
–40
0.7
0.5
0.084
MONOTONIC
3.01
4.08
–45
–50
Figure 5. Chrominance Internal Filter Specifications
–10–
REV. 0
ADV7170/ADV7171
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
0
2
4
6
8
10
12
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 6. NTSC Low-Pass Luma Filter
Figure 9. PAL Notch Luma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 7. PAL Low-Pass Luma Filter
Figure 10. Extended Mode (SSAF) Luma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 8. NTSC Notch Luma Filter
Figure 11. CIF Luma Filter
REV. 0
–11–
ADV7170/ADV7171
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 12. QCIF Luma Filter
Figure 15. 1.0 MHz Low-Pass Chroma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 13. 1.3 MHz Low-Pass Chroma Filter
Figure 16. 2.0 MHz Low-Pass Chroma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 14. 0.65 MHz Low-Pass Chroma Filter
Figure 17. CIF Chroma Filter
–12–
REV. 0
ADV7170/ADV7171
0
–10
–20
–30
–40
–50
–60
–70
SUBCARRIER RESET
Together with the SCRESET/RTC pin, and bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used in subcarrier reset mode. The subcarrier will reset to Field
0 at the start of the following field when a low-to-high transition
occurs on this input pin.
REAL-TIME CONTROL
Together with the SCRESET/RTC pin, and Bits MR22 and
MR21 of Mode Register 2, the ADV7170/ADV7171 can be
used to lock to an external video source. The real-time control
mode allows the ADV7170/ADV7171 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
datastream in the RTC format (such as a ADV7185 video de-
coder, see Figure 19), the part will automatically change to the
compensated subcarrier frequency on a line-by-line basis. This
digital datastream is 67 bits wide and the subcarrier is contained
in Bits 0 to 21. Each bit is 2 clock cycles long. 00Hex should be
written into all four subcarrier frequency registers when using
this mode.
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 18. QCIF Chroma Filter
COLOR BAR GENERATION
The ADV7170/ADV7171 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NTSC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
These are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
VIDEO TIMING DESCRIPTION
The ADV7170/ADV7171 is intended to interface to off-
the-shelf MPEG1 and MPEG2 Decoders. Consequently, the
ADV7170/ADV7171 accepts 4:2:2 YCrCb Pixel Data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing
generator. The ADV7170/ADV7171 generates all of the re-
quired horizontal and vertical timing periods and levels for the
analog video outputs.
SQUARE PIXEL MODE
The ADV7170/ADV7171 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accord-
ingly for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
The ADV7170/ADV7171 calculates the width and placement of
analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
In addition, the ADV7170/ADV7171 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections in the correct location
for the new clock frequencies.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC Pedestal Control Registers.
This allows the pedestals to be controlled during the vertical
blanking interval (Lines 10 to 25 and Lines 273 to 288).
The ADV7170/ADV7171 has four distinct master and four
distinct slave timing configurations. Timing Control is estab-
lished with the bidirectional SYNC, BLANK and FIELD/
VSYNC pins. Timing Mode Register 1 can also be used to vary
the timing pulsewidths and where they occur in relation to each
other.
PIXEL TIMING DESCRIPTION
The ADV7170/ADV7171 can operate in either 8-bit or
16-bit YCrCb Mode.
8-Bit YCrCb Mode
This default mode accepts multiplexed YCrCb inputs through
the P7-P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1 Cb1, Y2, etc. The Y, Cb and Cr data are input on a
rising clock edge.
16-Bit YCrCb Mode
This mode accepts Y inputs through the P7–P0 pixel inputs and
multiplexed CrCb inputs through the P15–P8 pixel inputs. The
data is loaded on every second rising edge of CLOCK. The inputs
follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
REV. 0
–13–
ADV7170/ADV7171
CLOCK
COMPOSITE
VIDEO
e.g., VCR
OR CABLE
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7185)
GREEN/LUMA/Y
RED/CHROMA/V
M
U
X
P7–P0
BLUE/COMPOSITE/U
COMPOSITE
MPEG
DECODER
HSYNC
FIELD/VSYNC
ADV7170/ADV7171
SEQUENCE
RESERVED
2
BIT
H/LTRANSITION
COUNT START
RESET
4 BITS
RESERVED
5 BITS
RESERVED
3
BIT
LOW
14 BITS
128
1
RESERVED
FSCPLL INCREMENT
0
0
13
21
RTC
TIME SLOT: 01
6768
14
19
NOT USED IN
ADV7175A/ADV7176A
VALID
SAMPLE SAMPLE
INVALID
8/LLC
NOTES:
1
F
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7175A/ADV7176A FSC DDS REGISTER IS
PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
SC
F
SC
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3
RESET BIT
RESET ADV7175A/ADV7176A’s DDS
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not bear line sync or pre-/post-equalization
pulses (see Figures 21 to 32). This mode of operation is called “Partial Blanking” and is selected by setting MR31 to 1. It allows the
insertion of any VBI data (Opened VBI) into the encoded output waveform. This data is present in digitized incoming YCbCr data
stream (e.g., WSS data, CGMS, VPS, etc.). Alternatively, the entire VBI may be blanked (no VBI data inserted) on these lines by
setting MR31 to 0.
The complete VBI is comprised of the following lines:
525/60 Systems, Lines 525 to 21 for Field 1 and Lines 262 to Line 284 for Field 2.
625/50 Systems, Lines 624 to Line 22 and Lines 311 to 335.
The “Opened VBI” consists of:
525/60 Systems, Lines 10 to 21 for Field 1 and second half of Line 273 to Line 284 for Field 2.
625/50 Systems, Line 7 to Line 22 and Lines 319 to 335.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7170/ADV7171 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high during this mode.
–14–
REV. 0
ADV7170/ADV7171
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
C
b
8
0
0
0
F
F
F A
F B
A
B
A
B
8
0
0
0
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
INPUT PIXELS
Y
Y
Y
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
268 CLOCK
1440 CLOCK
1440 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
280 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 20. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7170/ADV7171 generates H, V and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time
Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 23.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
V
F
ODD FIELD
EVEN FIELD
Figure 21. Timing Mode 0 (NTSC Master Mode)
REV. 0
–15–
ADV7170/ADV7171
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
335
336
318
334
309
310
311
312
313
314
315
316
317
319
320
H
V
F
ODD FIELD EVEN FIELD
Figure 22. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 23. Timing Mode 0 Data Transitions (Master Mode)
–16–
REV. 0
ADV7170/ADV7171
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode the ADV7170/ADV7171 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is dis-
abled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure
24 (NTSC) and Figure 25 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 24. Timing Mode 1 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 25. Timing Mode 1 (PAL)
REV. 0
–17–
ADV7170/ADV7171
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode the ADV7170/ADV7171 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is
disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). Figure 26 illus-
trates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode the ADV7170/ADV7171 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks all normally
blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 27. Timing Mode 2 (NTSC)
–18–
REV. 0
ADV7170/ADV7171
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode the ADV7170/ADV7171 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7170/ADV7171 automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 30 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 * CLOCK/2
BLANK
NTSC = 16 * CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
–19–
REV. 0
ADV7170/ADV7171
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7170/ADV7171 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7170/ADV7171 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 31 (NTSC) and Figure 32 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 31. Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 32. Timing Mode 3 (PAL)
–20–
REV. 0
ADV7170/ADV7171
OUTPUT VIDEO TIMING
this configuration the SCH phase will never be reset, which
means that the output video will now track the unstable input
video. The subcarrier phase reset, when applied, will reset the
SCH phase to Field 0 at the start of the next field (e.g., subcarrier
phase reset applied in Field 5 [PAL] on the start of the next
field SCH phase will be reset to Field 0).
The video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. These sequences are summarized below. In slave
modes, the following sequences are synchronized with the input
timing control signals. In master modes, the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
MPU PORT DESCRIPTION
The ADV7170 and ADV7171 support a two-wire serial (I2C
Compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7170 and ADV7171 each have four possible slave ad-
dresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 33 and
Figure 34. The LSB sets either a read or write operation. Logic
Level “1” corresponds to a read operation, while Logic Level
“0” corresponds to a write operation. A “1” is set by setting the
ALSB pin of the ADV7170/ADV7171 to Logic Level “0” or
Logic Level “1.”
NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan Lines 10–
21, 525, and 262, 263, 273–284 are also blanked and can be
used for closed captioning data. Burst is disabled on lines 1–6,
261–269 and 523–525.
NTSC–Noninterlaced: Scan Lines 1–9 are always blanked,
and vertical sync pulses are included. Scan Lines 10–21 are also
blanked and can be used for closed captioning data. Burst is
disabled on Lines 1–6, 261–262.
PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are
always blanked, and vertical sync pulses are included in Fields
1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are al-
ways blanked, and vertical sync pulses are included in Fields 3,
4, 7 and 8. The remaining scan lines in the vertical blanking
interval are also blanked and can be used for teletext data.
Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields
1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and
623–625 in Fields 3, 4, 7 and 8.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always
blanked, and vertical sync pulses are included. The remaining
scan lines in the vertical blanking interval are also blanked and
can be used for teletext data. Burst is disabled on Lines 1–5,
310–312.
0
1
WRITE
READ
Figure 33. ADV7170 Slave Address
1
1
0
0
1
A1
X
0
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
the RESET pin. This initializes the pixel port so that the
pixel inputs, P7–P0 are selected. After reset, the ADV7170/
ADV7171 is automatically set up to operate in NTSC mode.
Subcarrier frequency code 21F07C16HEX is loaded into the
subcarrier frequency registers. All other registers, with the
exception of Mode Register 0, are set to 00H. All bits in Mode
Register 0 are set to Logic Level “0” except Bit MR44. Bit
MR44 of Mode Register 4 is set to Logic “1.” This enables the
7.5 IRE pedestal.
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 34. ADV7171 Slave Address
To control the various devices on the bus, the following proto-
col must be followed: first, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits transfer from MSB down to LSB. The pe-
ripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
SCH Phase Mode
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, zero SCH phase
error would be maintained forever, but in reality, this is impos-
sible to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error, and results in very minor
SCH phase jumps at the start of the four or eight field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7170/ADV7171 is con-
figured in RTC mode (MR21 = 1 and MR22 = 1). Under these
conditions (unstable video) the subcarrier phase reset should be
enabled (MR22 = 0 and MR21 = 1) but no reset applied. In
REV. 0
–21–
ADV7170/ADV7171
REGISTER ACCESSES
The ADV7170/ADV7171 acts as a standard slave device on the
bus. The data on the SDATA pin is 8 bits long, supporting
the 7-bit addresses, plus the R/W bit. The ADV7170 has 48
subaddresses and the ADV7171 has 26 subaddresses to enable
access to the internal registers. It therefore interprets the first
byte as the device address and the second byte as the starting
subaddress. The subaddresses auto increment allows data to
be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one basis
without having to update all the registers. There is one excep-
tion. The subcarrier frequency registers should be updated in
sequence, starting with Subcarrier Frequency Register 0. The
auto increment function should then be used to increment and
access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier
frequency registers should not be accessed independently.
The MPU can write to or read from all of the ADV7170/
ADV7171 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. A read/write operation is performed from/to
the target address, which then increments to the next address
until a stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes each register, including subaddress
register, mode registers, subcarrier frequency registers, subcarrier
phase register, timing registers, closed captioning extended data
registers, closed captioning data registers and NTSC pedestal
control registers, in terms of its configuration.
Subaddress Register (SR7–SR0)
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high pe-
riod, the user should issue only one start condition, one stop
condition or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7170/ADV7171 will not issue an acknowledge and will
return to the idle condition. If, in auto-increment mode the user
exceeds the highest subaddress, the following action will be
taken:
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus, and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
Figure 37 shows the various operations under the control of
the subaddress register. Zero should always be written to
SR7–SR6.
Register Select (SR5–SR0)
These bits are set up to point to the required starting address.
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDATA line is not
pulled low on the ninth pulse.
MODE REGISTER 0 MR0 (MR07–MR00)
(Address [SR4–SR0] = 00H)
Figure 38 shows the various operations under the control of Mode
Register 0. This register can be read from as well as written to.
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7170/ADV7171 and the part will re-
turn to the idle condition.
MR0 BIT DESCRIPTION
Encode Mode Control (MR01–MR00)
These bits are used to set up the encode mode. The ADV7170/
ADV7171 can be set up to output NTSC, PAL (B, D, G, H, I)
and PAL (M, N) standard video.
SDATA
Luminance Filter Control (MR02–MR04)
These bits specify which luma filter is to be selected. The filter
selection is made independent of whether PAL or NTSC is
selected.
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
DATA
8
9
P
START ADDR
ACK SUBADDRESS ACK
ACK
STOP
R/W
Figure 35. Bus Data Transfer
Chrominance Filter Control (MR05–MR07)
These bits select the chrominance filter. A low-pass filter can be
selected with a choice of cutoff frequencies, 0.65 MHz, 1.0 MHz,
1.3 MHz or 2 MHz, along with a choice of CIF or QCIF filters.
Figure 35 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
DATA
A(M)
A(S) P
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(M)
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 36. Write and Read Sequences
–22–
REV. 0
ADV7170/ADV7171
SR1
SR7
SR6
SR5
SR4
SR3
SR2
SR0
SR7–SR5 (000)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7170 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MODE REGISTER 0
ADV7171 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
MODE REGISTER 1
MODE REGISTER 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
RESERVED
MODE REGISTER 3
MODE REGISTER 4
RESERVED
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA-BYTE 0
CLOSED CAPTIONING EXTENDED DATA-BYTE 1
CLOSED CAPTIONING DATA-BYTE 0
CLOSED CAPTIONING DATA-BYTE 1
NTSC PEDESTAL CONTROL REG 0
NTSC PEDESTAL CONTROL REG 1
NTSC PEDESTAL CONTROL REG 2
NTSC PEDESTAL CONTROL REG 3
CGMS_WSS_0
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA-BYTE 0
CLOSED CAPTIONING EXTENDED DATA-BYTE 1
CLOSED CAPTIONING DATA-BYTE 0
CLOSED CAPTIONING DATA-BYTE 1
NTSC PEDESTAL CONTROL REG 0
NTSC PEDESTAL CONTROL REG 1
NTSC PEDESTAL CONTROL REG 2
NTSC PEDESTAL CONTROL REG 3
CGMS_WSS_0
CGMS_WSS_1
CGMS_WSS_2
TELETEXT REQUEST POSITION
RESERVED
CGMS_WSS_1
CGMS_WSS_2
RESERVED
TELETEXT REQUEST POSITION
RESERVED
RESERVED
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
Figure 37. Subaddress Register Map
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
OUTPUT VIDEO
STANDARD SELECTION
CHROMA FILTER SELECT
MR06 MR05
MR07
MR01 MR00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.3 MHz LOW PASS FILTER
0
0
NTSC
PAL (B, D, G, H, I)
PAL (M)
0.65 MHz LOW PASS FILTER
1.0 MHz LOW PASS FILTER
2.0 MHz LOW PASS FILTER
RESERVED
CIF
Q CIF
0
1
1
1
0
1
RESERVED
LUMA FILTER SELECT
MR03 MR02
RESERVED
MR04
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
LOW PASS FILTER (NTSC)
LOW PASS FILTER (PAL)
NOTCH FILTER (NTSC)
NOTCH FILTER (PAL)
EXTENDED MODE
CIF
1
0
1
0
1
0
1
Q CIF
RESERVED
Figure 38. Mode Register 0
–23–
REV. 0
ADV7170/ADV7171
MODE REGISTER 1 MR1 (MR17–MR10)
Color Bar Control (MR17)
(Address (SR4–SR0) = 01H)
Figure 39 shows the various operations under the control of Mode
Register 1. This register can be read from as well as written to.
This bit can be used to generate and output an internal color
bar test pattern. The color bar configuration is 75/7.5/75/7.5
for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled the ADV7170/ADV7171 is config-
ured in a master timing mode.
MR1 BIT DESCRIPTION
Interlaced Mode Control (MR10)
This bit is used to set up the output to interlaced or noninter-
laced mode. This mode is only relevant when the part is in
composite video mode.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4-SR0] = 02H)
Mode Register 2 is an 8-bit-wide register.
Closed Captioning Field Control (MR12–MR11)
These bits control the fields on which closed captioning data is
displayed; closed captioning information can be displayed on an
odd field, even field or both fields.
Figure 40 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Mode Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
DAC Control (MR16–MR13)
These bits can be used to power down the DACs. This can
be used to reduce the power consumption of the ADV7170/
ADV7171 if any of the DACs are not required in the application.
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
DAC A
CONTROL
DAC D
CONTROL
CLOSED CAPTIONING
FIELD SELECTION
MR16
MR14
MR12
MR11
0
1
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
DAC B
CONTROL
DAC C
CONTROL
INTERLACE
CONTROL
MR15
MR13
MR10
MR17
0
1
INTERLACED
NONINTERLACED
0
1
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
1
DISABLE
ENABLE
Figure 39. Mode Register 1
MR21
MR27
MR26
MR25
MR24
MR23
MR22
MR20
CHROMINANCE
CONTROL
LOW POWER MODE
SELECT
GENLOCK SELECTION
MR22 MR21
MR24
MR26
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
0
1
ENABLE COLOR
DISABLE COLOR
0
1
DISABLE
ENABLE
1
1
ENABLE RTC PIN
MR27
RESERVED
BURST
CONTROL
ACTIVE VIDEO LINE WIDTH
CONTROL
SQUARE PIXEL
CONTROL
MR25
MR23
MR20
0
1
ENABLE BURST
DISABLE BURST
0
1
DISABLE
ENABLE
0
1
CCI R624 OUTPUT
CCI R601 OUTPUT
Figure 40. Mode Register 2
MR31
MR36
MR35
MR34
MR33
MR32
MR30
MR37
VBI_OPEN
TTX BIT REQUEST
MODE CONTROL
CHROMA OUTPUT
SELECT
MR30
MR31
MR32
MR36
MR34
0
1
DISABLE
ENABLE
RESERVED
0
1
NORMAL
BIT REQUEST
0
1
DISABLE
ENABLE
DAC OUTPUT
SWITCHING
ALL ZEROS INVALID
CONTROL
TELETEXT
CONTROL
MR37
MR35
MR33
DAC A
DAC B
DAC C
DAC D
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
0
1
COMPOSITE
GREEN/LUMA/Y
BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y
BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure 41. Mode Register 3
–24–
REV. 0
ADV7170/ADV7171
Genlock Control (MR22–MR21)
MR3 BIT DESCRIPTION
These bits control the genlock feature of the ADV7170/ADV7171.
Setting MR21 to a Logic “1” configures the SCRESET/RTC
pin as an input. Setting MR22 to Logic Level “0” configures
the SCRESET/RTC pin as a subcarrier reset input. Therefore,
the subcarrier will reset to Field 0 following a high-to-low tran-
sition on the SCRESET/RTC pin. Setting MR22 to Logic Level
“1” configures the SCRESET/RTC pin as a real-time control
input.
Revision Code (MR30–MR31)
This bit is read only and indicates the revision of the device.
VBI Pass-Through Control (MR32)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or BLANKed.
DAC Switching Control (MR33)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC
output configurations is shown below.
Active Video Line Control (MR23)
This bit switches between two active video line durations. A
zero selects ITU-R BT.470 (720 pixels PAL/NTSC) and a one
selects ITU-R/SMPTE “analog” standard for active video dura-
tion (710 pixels NTSC 702 pixels PAL).
Chroma Output Select (MR34)
With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA)
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Teletext Enable (MR35)
This bit must be set to “1” to enable teletext data insertion on
the TTX pin.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
Teletext Mode Control (MR36)
This bit enables switching of the teletext request signal from a
continuous high signal (“MR36 = 0”) to a bit wise request sig-
nal (“MR36 = 1”).
Low Power Control (MR26)
This bit enables the lower power mode of the ADV7170/ADV7171.
This will reduce the DAC current by 45%.
Input Default Color (MR37)
This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logical “0” means
that the color corresponding to 00000000 will be displayed. A
Logical “1” forces the output color to black for 00000000 pixel
input video data.
Reserved (MR27)
A Logical 0 must be written to this bit.
MODE REGISTER 3 MR3 (MR37–MR30)
(Address [SR4–SR0] = 03H)
Mode Register 3 is an 8-bit-wide register.
Figure 41 shows the various operations under the control of
Mode Register 3.
Table II. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
DAC A
DAC B
DAC C
DAC D
Simultaneous Output
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
CVBS
CVBS
CVBS
CVBS
B
B
U
U
CVBS
CVBS
CVBS
CVBS
B
B
U
U
C
C
C
C
R
R
V
V
C
C
C
C
R
R
V
V
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
Y
C
Y
C
G
C
Y
C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
2 Composite and Y/C
RGB and Composite
RGB and Composite
YUV and Composite
YUV and Composite
1 Composite, Y and 2C
1 Composite, Y and 2C
1 Composite, Y and 2C
1 Composite, Y and 2C
RGB and C
RGB and C
YUV and C
YUV and C
CVBS: Composite Video Baseband Signal
NOTE
Y:
C:
U:
V:
R:
G:
B:
Luminance Component Signal (For YUV or Y/C Mode)
Chrominance Signal (For Y/C Mode)
Chrominance Component Signal (For YUV Mode)
Chrominance Component Signal (For YUV Mode)
RED Component Video (For RGB Mode)
Each DAC can be powered ON or OFF individually with the following control
bits (“0” = ON, “1” = OFF).
MR13-DAC C
MR14-DAC D
MR15-DAC B
GREEN Component Video (For RGB Mode)
BLUE Component Video (For RGB Mode)
MR16-DAC A
REV. 0
–25–
ADV7170/ADV7171
MR41
MR46
MR45
MR44
MR43
MR42
MR40
MR47
SLEEP MODE
CONTROL
PEDESTAL
CONTROL
RGB SYNC
OUTPUT SELECT
MR42
MR40
MR44
MR46
0
1
DISABLE
ENABLE
0
1
YC OUTPUT
RGB/YUV OUTPUT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
MR47
(0)
ACTIVE VIDEO
FILTER CONTROL
RGB/YUV
CONTROL
VSYNC_3H
MR43
MR45
MR41
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
ENABLE
DISABLE
0
1
RGB OUTPUT
YUV OUTPUT
Figure 42. Mode Register 4
Pedestal Control (MR44)
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 is configured in PAL mode.
Mode Register 4 is a 8-bit-wide register.
Figure 42 shows the various operations under the control of
Mode Register 4.
Active Video Filter Switching (MR45)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the Sync rise and fall
times are always on spec regardless of which Luma filter is se-
lected. A Logic “1” enables this mode.
MR4 BIT DESCRIPTION
Output Select (MR40)
This bit specifies if the part is in composite video or RGB/YUV
mode. Note that in RGB/YUV mode the composite signal is
still available.
Sleep Mode Control (MR46)
When this bit is set (“1”) Sleep Mode is enabled. With this
mode enabled, the ADV7170/ADV7171 power consumption is
reduced to typically 200 nA. The I2C registers can be written to
and read from when the ADV7170/ADV7171 is in Sleep
Mode. If MR46 is set to a (“0”) when the device is in Sleep
Mode, the ADV7170/ADV7171 will come out of Sleep Mode
and resume normal operation. Also, if the RESET signal is
applied during Sleep Mode the ADV7170/ADV7171 will come
out of Sleep Mode and resume normal operation.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
VSYNC_3H Control (MR43)
When this bit is enabled (“1”) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in mas-
ter mode, the ADV7170/ADV7171 outputs an active low
VSYNC signal for 3 lines in NTSC mode and 2.5 lines in PAL
mode.
Reserved (MR47)
A Logical 0 should be written to this bit.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
TR01
TR07
TR06
TR05
TR04
TR03
TR02
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02 TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
8 BIT
0
0
1
1
0
1
0
1
MODE 0
74ns DELAY
148ns DELAY
222ns DELAY
1
16 BIT
MODE 1
MODE 2
MODE 3
Figure 43. Timing Register 0
–26–
REV. 0
ADV7170/ADV7171
TR0 BIT DESCRIPTION
TIMING REGISTER 1 (TR17–TR10)
Master/Slave Control (TR00)
(Address (SR4–SR0) = 08H)
This bit controls whether the ADV7170/ADV7171 is in master
or slave mode.
Timing Register 1 is a 8-bit-wide register.
Figure 44 shows the various operations under the control of
Timing Register 1. This register can be read from as well writ-
ten to. This register can be used to adjust the width and position
of the master mode timing signals.
Timing Mode Control (TR02–TR01)
These bits control the timing mode of the ADV7170/ADV7171.
These modes are described in more detail in the Timing and
Control section of the data sheet.
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
BLANK Control (TR03)
This bit controls whether the BLANK input is used when the
part is in slave mode.
HSYNC to VSYNC/FIELD Delay Control (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
Luma Delay Control (TR05–TR04)
These bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
HSYNC to FIELD Delay Control (TR15–TR14)
When the ADV7170/ADV7171 is in timing mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
Pixel Port Select (TR06)
This bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on Pins
P7–P0.
VSYNC Width (TR15–TR14)
When the ADV7170/ADV7171 is configured in Timing Mode
2, these bits adjust the VSYNC pulsewidth.
Timing Register Reset (TR07)
Toggling TR07 from low to high and low again resets the inter-
nal timing counters. This bit should be toggled after power-up,
reset or changing to a new timing mode.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC TO PIXEL
DATA ADJUSTMENT
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
HSYNC WIDTH
HSYNC TO
FIELD/VSYNC DELAY
T
TR11 TR10
A
TR17 TR16
T
TR13 TR12
0
0
1
1
0
1
0
1
1
؋
T 4
؋
T B
PCLK
T
TR15 TR14
C
0
0
1
1
0
1
0
1
0
؋
T 1
؋
T 2
؋
T 3
؋
T 0
0
1
1
0
1
0
1
0
؋
T 4
؋
T 8
؋
T PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
x
x
0
1
T
T
B
16
؋
T PCLK
+ 32s
B
128
؋
T PCLK
16
؋
T PCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1
؋
T 4
؋
T PCLK
PCLK
16
؋
T PCLK
128
؋
T PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
TA
TB
HSYNC
TC
FIELD/VSYNC
Figure 44. Timing Register 1
REV. 0
–27–
ADV7170/ADV7171
SUBCARRIER FREQUENCY REGISTER 3–0
(FSC3–FSC0)
(Address [SR4–SR0] = 09H–02H)
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 12–15H)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using the
following equation:
These 8-bit-wide registers are used to enable the NTSC pedes-
tal/PAL Teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 48 and 49 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the Pedestal OFF on the
equivalent line when used in NTSC. A Logic “1” in any of the
bits of these registers has the effect of turning Teletext ON on
the equivalent line when used in PAL.
232 –1
FCLK
× FSCF
Subcarrier Frequency Register =
i.e.: NTSC Mode,
FCLK = 27 MHz,
FSCF = 3.5795454 MHz
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
232 –1
27 ×106
PCO7
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
FIELD 1/3
FIELD 1/3
× 3.5795454 ×106
Subcarrier Frequency Value =
= 21F07C16HEX
Figure 45 shows how the frequency is set up by the four registers.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
FIELD 2/4
FIELD 2/4
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41°. For normal operation this register is
set to 00Hex.
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Figure 48. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
SUBCARRIER
FREQUENCY
REG 3
FSC30
FSC31
FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FIELD 1/3
FIELD 1/3
SUBCARRIER
FREQUENCY
REG 2
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC14
FSC6
FSC15
FSC7
FSC13 FSC12 FSC11 FSC10 FSC9
FSC8
FSC0
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
SUBCARRIER
FREQUENCY
REG 0
FIELD 2/4
FIELD 2/4
FSC5
FSC4
FSC3 FSC2 FSC1
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9 TXE8
Figure 45. Subcarrier Frequency Register
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 0E–0FH)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 46 shows how the
high and low bytes are set up in the registers.
Figure 49. Teletext Control Registers
TELETEXT CONTROL REGISTER TC07 (TC07–TC00)
(Address [SR4–SR0] = 19H)
Teletext Control Register is an 8-bit-wide register. See Figure 50.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. See Figure 59.
CED15 CED14 CED13 CED12 CED11 CED10
CED9
CED8
BYTE 1
CED7
CED6
CED5
CED4
CED3
CED2
CED1
CED0
BYTE 0
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext bits
below the default of 360. If Bits TC03-TC00 are 00Hex when
bits TC07–TC04 are changed, the falling edge of TTREQ will
track that of the rising edge (i.e., the time between the falling
and rising edge remains constant). See Figure 59.
Figure 46. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 10–11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address [SR4–SR0] = 16H)
CCD15
CCD14 CCD13 CCD12 CCD11 CCD10
CCD9
CCD8
BYTE 1
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
BYTE 0
Figure 47. Closed Captioning Data Register
–28–
REV. 0
ADV7170/ADV7171
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TC07
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Figure 50. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
C/W03–C/W00
WIDE SCREEN SIGNAL
CONTROL
CGMS ODD FIELD
CONTROL
CGMS DATA BITS
C/W07
C/W05
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
CGMS EVEN FIELD
CONTROL
CGMS CRC CHECK
CONTROL
C/W06
C/W04
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
Figure 51. CGMS_WSS Register 0
CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)
C/W0 BIT DESCRIPTION
CGMS Data Bits (C/W03–C/W00)
(Address [SR4–SR0] = 17H)
CGMS_WSS register 1 is an 8-bit-wide register. Figure 52
shows the operations under the control of this register.
These four data bits are the final four bits of CGMS data output
stream. Note it is CGMS data ONLY in these bit positions, i.e.,
WSS data does not share this location.
C/W1 BIT DESCRIPTION
CGMS/WSS Data Bits (C/W15–C/W10)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, is calculated internally by
the ADV7170/ADV7171. If this bit is disabled (“0”) the CRC
values in the register are output to the CGMS data stream.
CGMS Data Bits (C/W17–C/W16)
These bits are CGMS data bits only.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note this is only valid in NTSC mode.
CGMS_WSS REGISTER 2 C/W1 (C/W27–C/W20)
(Address [SR4–SR0] = 18H)
CGMS_WSS register 2 is an 8-bit-wide register. Figure 53
shows the operations under the control of this register.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note this is only valid in NTSC mode.
C/W2 BIT DESCRIPTION
WSS Control (C/W07)
When this bit is set (“1”), wide screen signaling is enabled. Note
this is only valid in PAL mode.
CGMS/WSS Data Bits (C/W27–C/W20)
These bit locations are shared by CGMS data and WSS data. In
NTSC mode these bits are CGMS data. In PAL mode these
bits are WSS data.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17 C/W16
CGMS DATA ONLY
C/W15–C/W10
CGMS/WSS DATA
Figure 52. CGMS_WSS Register 1
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27–C/W20
CGMS/WSS DATA
Figure 53. CGMS_WSS Register 2
–29–
REV. 0
ADV7170/ADV7171
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
Supply Decoupling
The ADV7170/ADV7171 is a highly integrated circuit containing
both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system level design so that high speed, accurate
performance is achieved. Figure 54, Recommended Analog
Circuit Layout, shows the analog interface between the device
and monitor.
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7170/ADV7171 must have at least one
0.1 µF decoupling capacitor to GND. These capacitors should
be placed as close to the device as possible.
It is important to note that while the ADV7170/ADV7171 con-
tains circuitry to reject power supply noise, this rejection de-
creases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three-terminal voltage
regulator for supplying power to the analog power plane.
The layout should be optimized for lowest noise on the ADV7170/
ADV7171 power and ground lines by shielding the digital inputs
and providing good decoupling. The lead length between groups
of VAA and GND pins should by minimized to minimize induc-
tive ringing.
Digital Signal Interconnect
Ground Planes
The digital inputs to the ADV7170/ADV7171 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay the
analog power plane.
The ground plane should encompass all ADV7170/ADV7171
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7170/ADV7171, the analog output traces,
and all the digital signal traces leading up to the ADV7170/
ADV7171. The ground plane is the board’s common ground
plane.
Due to the high clock rates involved, long clock lines to the
ADV7170/ADV7171 should be avoided to reduce noise pickup.
This should be as substantial as possible to maximize heat
spreading and power dissipation on the board.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not the
analog power plane.
Power Planes
The ADV7170/ADV7171 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within three inches of
the ADV7170/ADV7171.
Analog Signal Interconnect
The ADV7170/ADV7171 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
The metallization gap separating device power plane and board
power plane should be as narrow as possible to minimize the
obstruction to the flow of heat from the device into the general
board.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7170/ADV7171 power pins and voltage refer-
ence circuitry.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed
as close as possible to the ADV7170/ADV7171 to minimize
reflections.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common-mode.
The ADV7170/ADV7171 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
–30–
REV. 0
ADV7170/ADV7171
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1F
0.01F
L1
(FERRITE BEAD)
+5V (V
)
AA
+5V (V
)
+5V (V
)
+5V
AA
AA
(V
)
1, 11, 20, 28, 30
33F
10F
CC
0.1F
GND
0.1F
V
AA
COMP
25
33
27
DAC D
DAC C
V
REF
75⍀
75⍀
75⍀
75⍀
ADV7170/
ADV7171
38–42,
2–9, 12–14
26
+5V (V
)
P15–P0
AA
S VIDEO
4k⍀
35
DAC B 31
SCRESET/RTC
RESET
100nF
15 HSYNC
“UNUSED
INPUTS
SHOULD BE
GROUNDED”
FIELD/VSYNC
16
17
22
+5V (V
)
32
DAC A
AA
+5V (V
)
+5V (V
)
CC
CC
BLANK
RESET
TTX
100k⍀
5k⍀
5k⍀
TTX
TTXREQ
100⍀
100⍀
37
36
44
SCLOCK 23
SDATA 24
MPU BUS
TTXREQ
CLOCK
100k⍀
34
R
SET
+5V (V
)
AA
ALSB
18
GND
150⍀
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
10k⍀
10, 19, 21
29, 43
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 54. Recommended Analog Circuit Layout
The circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. This waveform
is guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. This 13.5 MHz clock can be used if
13.5 MHz clock is required by the MPEG decoder. This will guarantee that the Cr and Cb pixel information is input to the
ADV7170/ADV7171 in the correct sequence.
D
Q
13.5MHz
D
Q
CLOCK
CK
CK
HSYNC
Figure 55. Circuit to Generate 13.5 MHz
REV. 0
–31–
ADV7170/ADV7171
APPENDIX 2
CLOSED CAPTIONING
The ADV7170/ADV7171 supports closed captioning, conform-
ing to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
FCC Code of Federal Regulations (CFR) 47 Section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
The ADV7170/ADV7171 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line
283) it is outputted on Line 21 and Line 284. A typical imple-
mentation of this method is to use VSYNC to interrupt a micro-
processor, which will in turn load the new data (two bytes) every
field. If no new data is required for transmission, you must
insert zeros in both the data registers; this is called NULLING.
It is also important to load “control codes,” all of which are
double bytes, on Line 21, or a TV will not recognize them. If
you have a message like “Hello World,” which has an odd num-
ber of characters, it is important to pad it out to an even number
to get “end of caption” 2-byte control code to land in the same
field.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level “1” start bit. 16 bits of data follow
the start bit. These consist of two 8-bit bytes, seven data bits
and one odd parity bit. The data for these bytes is stored in
closed captioning Data Registers 0 and 1.
The ADV7170/ADV7171 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed caption-
ing on Lines 21 and 284 are automatically generated by the
ADV7170/ADV7171. All pixels inputs are ignored during
Lines 21 and 284.
10.5 ؎ 0.25s
12.91s
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
D0–D6
D0–D6
50 IRE
40 IRE
BYTE 1
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003s
33.764s
27.382s
Figure 56. Closed Captioning Waveform (NTSC)
–32–
REV. 0
ADV7170/ADV7171
APPENDIX 3
COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7170/ADV7171 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is
transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data
is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7170/ADV7171 is configured in NTSC
mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a refer-
ence pulse of the same amplitude and duration as a CGMS bit (see Figure 57). The bits are output from the configuration registers
in the following order; C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10,
C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3,
C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the Bit C/W04 is set to a Logic “1,” the last six bits, C19–C14, which
comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7170/ADV7171 based on the lower 14 bits
(C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data.
The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a
Logic “0,” all 20 bits (C0–C19) are directly output from the CGMS registers (no CRC calculated, must be calculated by the user).
Function of CGMS Bits
Word 0 – 6 Bits
Word 1 – 4 Bits
Word 2 – 6 Bits
CRC
– 6 Bits
CRC Polynomial = X6 + X + 1 (Preset to 111111)
0
Word 0
B1
B2
1
Aspect Ratio
Display Format
Undefined
16:94:3
Letterbox
Normal
B3
Word 0
B4, B5, B6
Identification information about video and other signals (e.g., audio)
Identification signal incidental to Word 0
Word 1
B7, B8, B9, B10
Word 2
B11, B12, B13, B14 Identification signal and information incidental to Word 0
100 IRE
CRC SEQUENCE
REF
70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
49.1s ؎0.5s
–40 IRE
11.2s
2.235s ؎20s
Figure 57. CGMS Waveform Diagram
REV. 0
–33–
ADV7170/ADV7171
APPENDIX 4
WIDE SCREEN SIGNALING
The ADV7170/ADV7171 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23.
WSS data can only be transmitted when the ADV7170/ADV7171 is configured in PAL mode. The WSS data is 14 bits long, the
function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 58).
The bits are output from the configuration registers in the following order; C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3,
C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12,
C/W15 = W13. If the bit C/W07 is set to a Logic “1” it enables the WSS data to transmitted on Line 23. The latter portion of Line
23 (42.5 µs from the falling edge of HSYNC) is available for the insertion of video.
Function of CGMS Bits
Bit 0–Bit 2
Aspect Ratio/Format/Position
Bit 3 is odd parity check of Bit 0–Bit 2
B0 B1 B2 B3 Aspect Ratio Format
Position
Nonapplicable
Center
Top
Center
Top
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
4:3
Full Format
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full Format
14:9
14:9
16:9
16:9
>16:9
14:9
16:9
Center
Center
Nonapplicable Nonapplicable
B4
0
1
B9 B10
Camera Mode
Film Mode
0
1
0
1
0
0
1
1
No Open Subtitles
Subtitles In Active Image Area
Subtitles Out of Active Image Area
Reserved
B5
0
Standard Coding
1
Motion Adaptive Color Plus
B11
0
1
No Surround Sound Information
Surround Sound Mode
B6
0
No Helper
1
Modulated Helper
B12
B13
RESERVED
RESERVED
B7
RESERVED
500mV
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0s
38.4s
42.5s
Figure 58. WSS Waveform Diagram
–34–
REV. 0
ADV7170/ADV7171
APPENDIX 5
TELETEXT INSERTION
tPD is the time needed by the ADV7170/ADV7171 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such
that it appears tSYNTXTOUT = 10.2 µs after the leading edge of the horizontal signal. Time TXTDEL is the pipeline delay time by the
source that is gated by the TTREQ signal in order to deliver TTX data.
With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct
position of 10.2 µs after the leading edge of Horizontal Sync pulse, thus enabling a source interface with variable pipeline delays.
The width of the TTXREQ signal must always be maintained to allow the insertion of 360 (to comply with the Teletext Standard
“PAL-WST”) teletext bits at a text data rate of 6.9375 Mbits/s, this is achieved by setting TC03–TC00 to zero. The insertion win-
dow is not open if the Teletex Enable bit (MR34) is set to zero.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
(27 MHz/4) = 6.75 MHz
(6.9375 × 106/6.75 × 106) = 1.027777
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7170/ADV7171
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
that can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the say way. Individual control of teletext lines is controlled by Teletext Setup Registers.
45 BYTES (360 BITS) – PAL
ADDRESS & DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 59. Teletext VBI Line
tSYNTXTOUT
CVBS/Y
tPD
tPD
HSYNC
10.2s
TXT
DATA
TXT
DEL
TXTREQ
TXT
ST
PROGRAMMABLE PULSE EDGES
tSYNTXTOUT = 10.2s
tPD = PIPELINE DELAY THROUGH ADV7170/ADV7171
TXT = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
DEL
Figure 60. Teletext Functionality Diagram
REV. 0
–35–
ADV7170/ADV7171
APPENDIX 6
NTSC WAVEFORMS (WITH PEDESTAL)
1268.1mV
1048.4mV
130.8 IRE
100 IRE
PEAK COMPOSITE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 61. NTSC Composite Video Levels
1048.4mV
100 IRE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 62. NTSC Luma Video Levels
PEAK CHROMA
1067.7mV
650mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
232.2mV
0mV
Figure 63. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
SYNC LEVEL
–40 IRE
45.9mV
Figure 64. NTSC RGB Video Levels
–36–
REV. 0
ADV7170/ADV7171
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
100 IRE
1289.8mV
1052.2mV
PEAK COMPOSITE
REF WHITE
714.2mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
338mV
52.1mV
–40 IRE
Figure 65. NTSC Composite Video Levels
1052.2mV
100 IRE
REF WHITE
714.2mV
338mV
52.1mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 66. NTSC Luma Video Levels
PEAK CHROMA
1101.6mV
650mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
198.4mV
0mV
Figure 67. NTSC Chroma Video Levels
100 IRE
1052.2mV
REF WHITE
715.7mV
BLANK/BLACK LEVEL 336.5mV
51mV
0 IRE
SYNC LEVEL
–40 IRE
Figure 68. NTSC RGB Video Levels
REV. 0
–37–
ADV7170/ADV7171
PAL WAVEFORMS
PEAK COMPOSITE
REF WHITE
1284.2mV
1047.1mV
696.4mV
350.7mV
50.8mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 69. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
350.7mV
50.8mV
Figure 70. PAL Luma Video Levels
PEAK CHROMA
1092.5mV
650mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
207.5mV
0mV
Figure 71. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
351.8mV
51mV
Figure 72. PAL RGB Video Levels
–38–
REV. 0
ADV7170/ADV7171
UV WAVEFORMS
505mV
334mV
505mV
423mV
171mV
BETACAM LEVEL
BETACAM LEVEL
0mV
82mV
0mV
0mV
0mV
–82mV
؊171mV
؊334mV
–423mV
–505mV
؊505mV
Figure 73. NTSC 100% Color Bars, No Pedestal U Levels
Figure 76. NTSC 100% Color Bars, No Pedestal V Levels
467mV
467mV
391mV
309mV
158mV
BETACAM LEVEL
76mV
BETACAM LEVEL
0mV
0mV
0mV
0mV
–76mV
–158mV
–309mV
–391mV
–467mV
–467mV
Figure 74. NTSC 100% Color Bars with Pedestal U Levels
Figure 77. NTSC 100% Color Bars with Pedestal V Levels
350mV
350mV
293mV
232mV
118mV
SMPTE LEVEL
57mV
SMPTE LEVEL
0mV
0mV
0mV
0mV
–57mV
–118mV
–232mV
–293mV
–350mV
–350mV
Figure 75. PAL 100% Color Bars, U Levels
Figure 78. PAL 100% Color Bars, V Levels
REV. 0
–39–
ADV7170/ADV7171
APPENDIX 7
OPTIONAL OUTPUT FILTER
is not required if the outputs of the ADV7170/ADV7171 are
connected to most analog monitors or analog TVs, however if
the output signals are applied to a system where sampling is
used (e.g., Digital TVs), then a filter is required to prevent
aliasing.
If an output filter is required for the CVBS, Y, UV, Chroma
and RGB outputs of the ADV7170/ADV7171, the filter shown
in Figure 79 can be used. Plots of the filter characteristics are
shown in Figure 80, Figure 81 and Figure 82. An Output Filter
0
L
L
L
1H
2.7H
0.68H
V
– OP
dB
IN
OUT
–5
C
C
C
56pF
R
R
470pF
330pF
75⍀
75⍀
–10
–15
–20
–25
–30
–35
Figure 79. Output Filter
0
–5
–10
V
– OP
–15
–20
–25
–30
dB
1
10
100
FREQUENCY – MHz
–35
–40
–45
–50
–55
–60
–65
–70
Figure 81. Output Filter Plot Close-Up
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
V
– OP
dB
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 80. Output Filter Plot
3
1
2
4
5
6
7
8
9 10
FREQUENCY – MHz
Filter 82. Output Filter Plot Close-Up
–40–
REV. 0
ADV7170/ADV7171
APPENDIX 8
OPTIONAL DAC BUFFERING
When calculating absolute output full-scale current and voltage,
use the following equations:
When external buffering is needed of the ADV7170/ADV7171
DAC outputs, the configuration in Figure 83 is recommended.
This configuration shows the DAC outputs running at half
(18 mA) their full current (36 mA) capability. This will allow
the ADV7170/ADV7171 to dissipate less power; the analog cur-
rent is reduced by 50% with a RSET of 300 Ω and a RLOAD of 75 Ω.
This mode is recommended for 3.3 V operation as optimum
performance is obtained from the DAC outputs at 18 mA with a
VAA of 3.3 V. This buffer also adds extra isolation on the video
outputs (see buffer circuit in Figure 84).
VOUT = IOUT × RLOAD
VREF × K
(
=
)
IOUT
RSET
K = 4.2146 constant ,VREF = 1.235 V
V
AA
ADV7170/ADV7171
OUTPUT
BUFFER
V
REF
DAC A
CVBS
OUTPUT
BUFFER
DAC B
DAC C
DAC D
CVBS
PIXEL
PORT
DIGITAL
CORE
OUTPUT
BUFFER
LUMA
R
SET
OUTPUT
BUFFER
300⍀
CHROMA
Figure 83. Output DAC Buffering Configuration
V
AA
36⍀
OUTPUT TO
TV/MONITOR
INPUT
2N2907
75⍀
75⍀
Figure 84. Recommended Output DAC Buffer
REV. 0
–41–
ADV7170/ADV7171
APPENDIX 9
RECOMMENDED REGISTER VALUES
The ADV7170/ADV7171 registers can be set depending on the
user standard required.
0FHex Closed Captioning Ext Register 1
10Hex Closed Captioning Register 0
11Hex Closed Captioning Register 1
12Hex Pedestal Control Register 0
13Hex Pedestal Control Register 1
14Hex Pedestal Control Register 2
15Hex Pedestal Control Register 3
16Hex CGMS_WSS Reg 0
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
The following examples give the various register formats for
several video standards.
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Addi-
tionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown, the timing mode is set to Mode 0 in slave
format. TR02–TR00 of the Timing Register 0 control the tim-
ing modes. For a detailed explanation of each bit in the com-
mand registers, please turn to the Register Programming section
of the data sheet. TR07 should be toggled after setting up a new
timing mode. Timing Register 1 provides additional control over
the position and duration of the timing signals. In the examples,
this register is programmed in default mode.
17Hex CGMS_WSS Reg 1
18Hex CGMS_WSS Reg 2
19Hex TeleText Control Register
PAL N (FSC = 4.43361875 MHz)
Address
00Hex Mode Register 0
01Hex Mode Register 1
02Hex Mode Register 2
03Hex Mode Register 3
04Hex Mode Register 4
07Hex Timing Register 0
08Hex Timing Register 1
09Hex Subcarrier Frequency Register 0
0AHex Subcarrier Frequency Register 1
0BHex Subcarrier Frequency Register 2
0CHex Subcarrier Frequency Register 3
0DHex Subcarrier Phase Register
0EHex Closed Captioning Ext Register 0
0FHex Closed Captioning Ext Register 1
10Hex Closed Captioning Register 0
11Hex Closed Captioning Register 1
12Hex Pedestal Control Register 0
13Hex Pedestal Control Register 1
14Hex Pedestal Control Register 2
15Hex Pedestal Control Register 3
16Hex CGMS_WSS Reg 0
Data
05Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
PAL B, D, G, H, I (FSC = 4.43361875 MHz)
Address
Data
00Hex Mode Register 0
01Hex Mode Register 1
02Hex Mode Register 2
03Hex Mode Register 3
04Hex Mode Register 4
07Hex Timing Register 0
08Hex Timing Register 1
09Hex Subcarrier Frequency Register 0
0AHex Subcarrier Frequency Register 1
0BHex Subcarrier Frequency Register 2
0CHex Subcarrier Frequency Register 3
0DHex Subcarrier Phase Register
0EHex Closed Captioning Ext Register 0
0FHex Closed Captioning Ext Register 1
10Hex Closed Captioning Register 0
11Hex Closed Captioning Register 1
12Hex Pedestal Control Register 0
13Hex Pedestal Control Register 1
14Hex Pedestal Control Register 2
15Hex Pedestal Control Register 3
16Hex CGMS_WSS Reg 0
05Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
17Hex CGMS_WSS Reg 1
18Hex CGMS_WSS Reg 2
19Hex TeleText Control Register
PAL-60 (FSC = 4.43361875 MHz)
Address
00Hex Mode Register 0
01Hex Mode Register 1
02Hex Mode Register 2
03Hex Mode Register 3
04Hex Mode Register 4
07Hex Timing Register 0
08Hex Timing Register 1
09Hex Subcarrier Frequency Register 0
0AHex Subcarrier Frequency Register 1
0BHex Subcarrier Frequency Register 2
0CHex Subcarrier Frequency Register 3
0DHex Subcarrier Phase Register
0EHex Closed Captioning Ext Register 0
0FHex Closed Captioning Ext Register 1
10Hex Closed Captioning Register 0
11Hex Closed Captioning Register 1
12Hex Pedestal Control Register 0
13Hex Pedestal Control Register 1
Data
04Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
CBHex
8AHex
09Hex
2AHex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
17Hex CGMS_WSS Reg 1
18Hex CGMS_WSS Reg 2
19Hex TeleText Control Register
PAL M (FSC = 3.57561149 MHz)
Address
Data
00Hex Mode Register 0
01Hex Mode Register 1
02Hex Mode Register 2
03Hex Mode Register 3
04Hex Mode Register 4
07Hex Timing Register 0
08Hex Timing Register 1
09Hex Subcarrier Frequency Register 0
0AHex Subcarrier Frequency Register 1
0BHex Subcarrier Frequency Register 2
0CHex Subcarrier Frequency Register 3
0DHex Subcarrier Phase Register
0EHex Closed Captioning Ext Register 0
02Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
A3Hex
EFHex
E6Hex
21Hex
00Hex
00Hex
–42–
REV. 0
ADV7170/ADV7171
PAL-60 (Continued) (FSC = 4.43361875 MHz)
Address
Data
14Hex Pedestal Control Register 2
15Hex Pedestal Control Register 3
16Hex CGMS_WSS Reg 0
17Hex CGMS_WSS Reg 1
18Hex CGMS_WSS Reg 2
19Hex TeleText Control Register
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
Power-Up Reset Values
NTSC (FSC = 3.5795454 MHz)
Address
Data
00Hex Mode Register 0
01Hex Mode Register 1
02Hex Mode Register 2
03Hex Mode Register 3
04Hex Mode Register 4
07Hex Timing Register 0
08Hex Timing Register 1
09Hex Subcarrier Frequency Register 0
0AHex Subcarrier Frequency Register 1
0BHex Subcarrier Frequency Register 2
0CHex Subcarrier Frequency Register 3
0DHex Subcarrier Phase Register
0EHex Closed Captioning Ext Register 0
0FHex Closed Captioning Ext Register 1
10Hex Closed Captioning Register 0
11Hex Closed Captioning Register 1
12Hex Pedestal Control Register 0
13Hex Pedestal Control Register 1
14Hex Pedestal Control Register 2
15Hex Pedestal Control Register 3
16Hex CGMS_WSS Reg 0
00Hex
58Hex
00Hex
00Hex
10Hex
00Hex
00Hex
16Hex
7CHex
F0Hex
21Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
00Hex
17Hex CGMS_WSS Reg 1
18Hex CGMS_WSS Reg 2
19Hex TeleText Control Register
REV. 0
–43–
ADV7170/ADV7171
APPENDIX 10
OUTPUT WAVEFORMS
0.6
0.4
0.2
0.0
؊0.2
L608
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 0.00 dB
APL = 39.1%
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
SYNC = SOURCE
625 LINE PAL
NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2 3 4
Figure 85. 100%/75% PAL Color Bars
0.5
0.0
L575
0.0
10.0
20.0
30.0
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
40.0
50.0
60.0
70.0
APL NEEDS SYNC = SOURCE!
SOUND-IN-SYNC OFF
SYNC = A
625 LINE PAL
NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1
Figure 86. 100%/75% PAL Color Bars Luminance
–44–
REV. 0
ADV7170/ADV7171
0.5
0.0
–0.5
L575
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NO BRUCH SIGNAL
APL NEEDS SYNC = SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
SYNC = A
FRAMES SELECTED: 1
Figure 87. 100%/75% PAL Color Bars Chrominance
100.0
0.5
50.0
0.0
0.0
F1
L76
–50.0
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
APL = 44.6%
PRECISION MODE OFF
SYNCHRONOUS
525 LINE NTSC
NO FILTERING
SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 88. 100%/75% NTSC Color Bars
REV. 0
–45–
ADV7170/ADV7171
0.6
0.4
0.2
50.0
0.0
0.0
–0.2
F2
L238
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.7%
PRECISION MODE OFF
525 LINE NTSC
NO FILTERING
SYNCHRONOUS
SYNC = SOURCE
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 89. 100%/75% NTSC Color Bars Luminance
0.4
50.0
0.2
0.0
–0.2
–0.4
–50.0
F1
L76
0.0
10.0
20.0
30.0
40.0
50.0
60.0
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC = SOURCE!
PRECISION MODE OFF
SYNCHRONOUS
525 LINE NTSC
NO FILTERING
SYNC = B
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 90. 100%/75% NTSC Color Bars Chrominance
–46–
REV. 0
ADV7170/ADV7171
V
APL = 39.6%
SYSTEM LINE L608
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
625 LINE PAL
cy
BURST FROM SOURCE
DISPLAY +V & –V
R
g
M
g
75%
100%
YI
b
U
yl
B
G
Cy
m
g
r
SOUND IN SYNC OFF
Figure 91. PAL Vector Plot
R-Y
APL = 45.1%
SYSTEM LINE L76F1
ANGLE (DEG) 0.0
GAIN x 1.000 0.000dB
525 LINE NTSC
cy
I
BURST FROM SOURCE
R
M
g
Q
YI
b
100%
B-Y
75%
B
G
Cy
–Q
–I
SETUP 7.5%
Figure 92. NTSC Vector Plot
–47–
REV. 0
ADV7170/ADV7171
COLOR BAR (NTSC)
WFM -->
FCC COLOR BAR
FIELD = 2 LINE = 28
LUMINANCE LEVEL (IRE)
0.4
0.2
0.2
0.0
0.2
0.1
0.2
0.1
30.0
20.0
10.0
0.0
–10.0
CHROMINANCE LEVEL (IRE)
0.0 –0.2
1.0
–0.2
–0.3
–0.2
–0.3
0.0
0.0
0.0
–1.0
CHROMINANCE PHASE (DEG)
. . . . .
–0.1
–0.2
–0.2
–0.1
–0.3
–0.2
- - - - -
0.0
–1.0
–2.0
GRAY
YELLOW
CYAN
GREEN
MAGENTA
RED
BLUE
BLACK
AVERAGE: 32 --> 32
REFERENCE 75/7.5/75/7.5 COLOR BAR STANDARD
Figure 93. NTSC Color Bar Measurement
DGDP (NTSC)
BLOCK MODE START F2 L64, STEP = 32, END = 192
DIFFERENTIAL GAIN (%)
WFM -->
MOD 5 STEP
0.05
MIN = 0.00 MAX = 0.11 p-p/MAX = 0.11
0.11 0.07
0.00
0.08
0.07
0.3
0.2
0.1
0.0
–0.1
DIFFERENTIAL PHASE (DEG)
0.00 0.03
MIN = –0.02 MAX = 0.14 pk-pk = 0.16
0.14 0.10
–0.02
0.10
0.20
0.15
0.10
0.05
–0.00
–0.05
–0.10
1ST
2ND
3RD
4TH
5TH
6TH
Figure 94. NTSC Differential Gain and Phase Measurement
–48–
REV. 0
ADV7170/ADV7171
LUMINANCE NONLINEARITY (NTSC)
FIELD = 2 LINE = 21
LUMINANCE NONLINEARITY (%)
WFM -->
5 STEP
pk-pk = 0.2
99.9
99.9
100.0
99.9
99.8
100.4
100.3
100.2
100.1
100.0
99.9
99.8
99.7
99.6
99.5
99.4
99.3
99.2
99.1
99.0
98.9
98.8
98.7
98.6
1ST
2ND
3RD
4TH
5TH
Figure 95. NTSC Luminance Nonlinearity Measurement
CHROMINANCE AM PM (NTSC)
FULL FIELD (BOTH FIELDS)
BANDWIDTH 100Hz TO 500kHz
WFM -->
APPROPRIATE
AM NOISE
–68.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
–45.0
–40.0
dB RMS
PM NOISE
–64.4dB RMS
–75.0
–70.0
–65.0
–60.0
–55.0
–50.0
–45.0
–40.0
dB RMS
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 96. NTSC AMPM Noise Measurement
REV. 0
–49–
ADV7170/ADV7171
NOISE SPECTRUM (NTSC)
WFM -->
PEDESTAL
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 100kHz TO FULL
NOISE LEVEL = –80.1 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
6.0
MHz
Figure 97. NTSC SNR Pedestal Measurement
NOISE SPECTRUM (NTSC)
WFM -->
RAMP SIGNAL
FIELD = 2 LINE = 64
AMPLITUDE (0 dB = 714mV p-p)
BANDWIDTH 10kHz TO FULL (TILT NULL)
NOISE LEVEL = –61.7 dB RMS
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
MHz
Figure 98. NTSC SNR Ramp Measurement
–50–
REV. 0
ADV7170/ADV7171
PARADE SMPTE/EBU PAL
mV Y(A)
mV
250
Pb(B)
mV
Pr(C)
250
700
600
200
150
100
50
200
150
100
50
500
400
300
200
0
0
100
–50
–50
0
–100
–150
–200
–250
–100
–150
–200
–250
؊100
؊200
؊300
Figure 99. PAL YUV Parade Plot
LIGHTNING
L183
COLORBARS: 75% SMPTE/EBU (50Hz)
Pk-WHITE (100%) 700.0mV SETUP 0.0% COLOR Pk-Pk 525.0mV
AVERAGE 32 --> 32
YI
–274.82
0.93%
G
R
CY
88.31
0.28%
M
B
–173.24
0.19%
–88.36
0.19%
174.35
–0.65%
260.51
–0.14%
B-Y
W
YI
CY
864.78
–0.88%
462.80
–0.50%
YI
G
G
307.54
–0.21%
CY
M
216.12
–0.33%
R
M
R
156.63
–0.22%
B
B
61.00
1.92%
B
R
G
M
CY
YI
W
R-Y
CY
–262.17
–0.13%
G
B
YI
41.32
–0.76%
M
R
–218.70
–0.51%
–42.54
0.69%
212.28
–3.43%
252.74
–3.72%
COLOR Pk-Pk: B-Y 532.33mV
Pk-WHITE: 700.4mV (100%) SETUP –0.01%
1.40%
R-Y 514.90mV –1.92%
DELAY: B-Y –6ns R-Y –6ns
Figure 100. PAL YUV Lighting Plot
REV. 0
–51–
ADV7170/ADV7171
COMPONENT NOISE
LINE = 202
AMPLITUDE (0dB = 700mV p-p)
BANDWIDTH 10kHz TO 5.0MHz
NOISE dB RMS
0.0
–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
-->Y –82.1
Pb –82.3
Pr –83.3
–35.0
–40.0
–45.0
–50.0
–55.0
–60.0
–65.0
–70.0
–75.0
–80.0
–85.0
–90.0
–95.0
–100.0
1.0
2.0
3.0
4.0
5.0
6.0
MHz
Figure 101. PAL YUV SNR Plot
COMPONENT MULTIBURST
LINE = 202
AMPLITUDE (0dB = 100% OF 688.1mV
683.4mV
–0.05
668.9mV
–0.68
(dB)
0.04
–0.02
–2.58
4.79
–8.05
0.0
Y
–5.0
–10.0
0.49
0.99
2.00
3.99
5.79
0.21
0.23
–0.78
–2.59
–7.15
0.0
Pb –5.0
–10.0
0.49
0.25
0.99
0.25
1.99
2.39
2.89
–0.77
–2.59
–7.13
0.0
Pr –5.0
–10.0
0.49
0.99
1.99
MHz
2.39
2.89
Figure 102. PAL YUV Multiburst Response
–52–
REV. 0
ADV7170/ADV7171
COMPONENT VECTOR SMPTE/EBU, 75%
R
M
g
YI
BK
B
G
CY
Figure 103. PAL YUV Vector Plot
mV
GREEN (A)
mV
BLUE (B)
mV
RED (C)
700
700
600
700
600
500
400
300
200
100
0
600
500
400
300
200
100
0
500
400
300
200
100
0
؊100
؊200
؊300
؊100
؊200
؊300
؊100
؊200
؊300
Figure 104. PAL RGB Waveforms
REV. 0
–53–
ADV7170/ADV7171
INDEX
Contents
Page No.
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . .
ADV7170/ADV7171 SPECIFICATIONS . . . . . . . . . . . . .
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . .
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . .
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .
1
1
2
4
5
8
8
8
9
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 10
DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 10
INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 10
COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 13
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 13
COLOR SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13
BURST SIGNAL CONTROL . . . . . . . . . . . . . . . . . . . . . . 13
NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 13
PIXEL TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 13
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REAL-TIME CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 13
OUTPUT VIDEO TIMING . . . . . . . . . . . . . . . . . . . . . . . . 21
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 21
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 22
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TIMING REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TIMING REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SUBCARRIER FREQUENCY REGISTER 3–0 . . . . . . . . 28
SUBCARRIER PHASE REGISTER . . . . . . . . . . . . . . . . . . 28
CLOSED CAPTIONING EVEN FIELD . . . . . . . . . . . . . . 28
CLOSED CAPTIONING ODD FIELD . . . . . . . . . . . . . . 28
NTSC PEDESTAL/PAL TELETEXT
CONTROL REGISTERS 3–0 . . . . . . . . . . . . . . . . . . . . . 28
TELETEXT CONTROL REGISTER TC07 . . . . . . . . . . . 28
APPENDIX 1. BOARD DESIGN AND
LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . 30
APPENDIX 2. CLOSED CAPTIONING . . . . . . . . . . . . . 32
APPENDIX 3. COPY GENERATION MANAGEMENT
SYSTEMS (CGMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX 4. WIDE SCREEN SIGNALING . . . . . . . . . 34
APPENDIX 5. TELETEXT INSERTION . . . . . . . . . . . . 35
APPENDIX 6.
NTSC WAVEFORMS (WITH PEDESTAL) . . . . . . . . . 36
NTSC WAVEFORMS (WITHOUT PEDESTAL) . . . . . 37
PAL WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
UV WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
APPENDIX 7. OPTIONAL OUTPUT FILTER . . . . . . . . 40
APPENDIX 8. OPTIONAL DAC BUFFERING . . . . . . . 41
APPENDIX 9. RECOMMENDED REGISTER
VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX 10. OUTPUT WAVEFORMS . . . . . . . . . . . . 44
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 55
–54–
REV. 0
ADV7170/ADV7171
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Quad Flatpack (PQFP)
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
0.398 (10.11)
MAX
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8؇
0.8؇
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
44
12
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.033 (0.84)
0.029 (0.74)
0.016 (0.41)
0.012 (0.30)
0.083 (2.11)
0.077 (1.96)
44-Lead Thin Plastic Quad Flatpack (TQFP)
(SU-44)
0.047 (1.20)
MAX
0.006 (0.15)
0.002 (0.05)
0.472 (12.00) SQ
33
23
34
22
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
44
12
1
11
0.041 (1.05)
0.037 (0.95)
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
REV. 0
–55–
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