ADV7172_15_技术文档

Digital PAL/NTSC Video Encoder

with Six DACs (10 Bits), Color Control

and Enhanced Power Management

a

ADV7172/ADV7173

Color Signal Control/Burst Signal Control

Interlaced/Noninterlaced Operation

Complete On-Chip Video Timing Generator

Programmable Multimode Master/Slave Operation

Macrovision Antitaping Rev 7.1 (ADV7172 Only)²

Closed Captioning Support

FEATURES

ITU-R¹BT601/656 YCrCb to PAL/NTSC Video Encoder

Six High Quality 10-Bit Video DACs

SSAF™ (Super Sub-Alias Filter)

Advanced Power Management Features

PC’98-Compliant (TV Detect with Polling and Auto

Shutdown to Save On Power Consumption)

Low Power DAC Mode

Individual DAC ON/OFF Control

Variable DAC Output Current (5 mA–36 mA)

Ultralow Sleep Mode Current

Hue, Brightness, Contrast and Saturation Controls

CGMS (Copy Generation Management System)

WSS (Wide Screen Signalling)

NTSC-M, PAL-M/N, PAL-B/D/G/H/I, PAL-60

YUV Betacam, MII and SMPTE/EBU N10 Output Levels

Single 27 MHz Clock Required (ꢀ2 Oversampling)

80 dB Video SNR

Teletext Insertion Port (PAL-WST)

On-Board Color Bar Generation

On-Board Voltage Reference

2-Wire Serial MPU Interface (I²C^®-Compatible and Fast I²C)

Single Supply 5 V or 3.3 V Operation

Small 48-Lead LQFP Package

APPLICATIONS

High Performance DVD Playback Systems, Portable

Video Equipment including Digital Still Cameras and

Laptop PCs, Video Games, PC Video/Multimedia and

Digital Satellite/Cable Systems (Set-Top Boxes/IRD)

32-Bit Direct Digital Synthesizer for Color Subcarrier

Multistandard Video Output Support:

Composite (CVBS)

Component S-Video (Y/C)

Component YUV

GENERAL DESCRIPTION

The ADV7172/ADV7173 is an integrated Digital Video

Encoder that converts digital CCIR-601 4:2:2 8-bit component

video data into a standard analog baseband television signal

compatible with worldwide standards.

EuroSCART RGB

There are six DACs available on the ADV7172/ADV7173. In

addition to the Composite output signal there is the facility to

output S-VHS Y/C Video, RGB Video and YUV Video.

Component YUV + CHROMA + LUMA + CVBS

EuroSCART Output RGB + CHROMA + LUMA + CVBS

Programmable Clamping Output Signal

Advanced Programmable Power-On Reset Sequencing

Video Input Data Port Supports:

CCIR-656 4:2:2 8-Bit Parallel Input Format

SMPTE 170M NTSC-Compatible Composite Video

ITU-R BT.470 PAL-Compatible Composite Video

Luma Sharpness Control

Programmable Luma Filters (Low-Pass [PAL/NTSC],

Notch [PAL/NTSC], Extended [SSAF], CIF and QCIF)

Programmable Chroma Filters (Low-Pass [0.65 MHz,

1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF)

Programmable VBI (Vertical Blanking Interval)

Programmable Subcarrier Frequency and Phase

Programmable LUMA Delay

The on-board SSAF (Super Sub-Alias Filter), with extended

luminance frequency response and sharp stopband attenuation,

enables studio quality video playback on modern TVs, giving

optimal horizontal line resolution. An additional sharpness control

feature allows extra luminance boost on the frequency response.

An advanced power management circuit enables optimal control

of power consumption in both normal operating modes and

power down or sleep modes. A PC’98-Compliant autodetect

feature has been added to allow the user to determine whether

or not the DACs are correctly terminated. If not, the ADV7172/

ADV7173 flags that they are not connected through the Status

bit and provides the option of automatically powering them

down, thereby reducing power consumption.

CCIR and Square Pixel Operation

Integrated Subcarrier Locking to External Video Source

The ADV7172/ADV7173 also supports both PAL and NTSC

square pixel operation. The parts also incorporate WSS and

CGMS-A data control generation.

NOTES

¹ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).

²The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest

Macrovision version available.

SSAF is a trademark of Analog Devices, Inc.

I²C is a registered trademark of Philips Corporation.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

use, nor for any infringements of patents or other rights of third parties

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

ADV7172/ADV7173

FUNCTIONAL BLOCK DIAGRAM

CLAMP

ALSB

CLOCK PAL NTSC CSO_HSO VSO

SCLOCK SDATA

M

U

L

T

I

P

L

E

X

E

R

HSYNC

FIELD/

VSYNC

10

10-BIT

DAC

2

I C MPU PORT

YUV TO

RBG

VIDEO TIMING

GENERATOR

DAC A

DAC B

DAC C

MATRIX

+

BLANK

10-BIT

DAC

YUV

RESET

LEVEL

CONTROL

BLOCK

10-BIT

DAC

TTX

TTXREQ

TELETEXT

INSERTION BLOCK

V

BRIGHTNESS AND

CONTRAST CONTROL

LUMA

AA

V

R

REF

DAC

PROGRAMMABLE

FILTER

10

CONTROL

BLOCK

SET2

+

ADD SYNC

+

M

U

L

T

I

P

L

E

X

E

R

+

COMP2

8

Y

U

8

SHARPNESS

FILTER

10

INTERPOLATOR

10-BIT

DAC

P0

YCrCb

TO

DAC E

4:2:2 TO

4:4:4

10

8

COLOR

DATA

10

SATURATION CONTROL

YUV

10

INTER-

MODULATOR

10-BIT

DAC

+

ADD BURST

+

8

PROGRAMMABLE

CHROMA

MATRIX

DAC F

DAC D

POLATOR

+

P7

HUE

V

FILTER

CONTROL

10-BIT

DAC

INTERPOLATOR

10

DAC

CONTROL

BLOCK

REAL-TIME

CONTROL CIRCUIT

SIN/COS

DDS BLOCK

ADV7172/ADV7173

R

SET1

COMP1

GND

SCRESET/RTC

The ADV7172/ADV7173 is designed with four color controls

(hue, contrast, brightness and saturation). All YUV formats

(SMPTE/EBU N10, MII and Betacam) are supported in both

PAL and NTSC.

input data from 1 to 254 on both Y, Cb, and Cr. The ADV7172/

ADV7173 supports PAL (B, D, G, H, I, N, M) and NTSC

(with and without pedestal) standards. The Y data is then

manipulated by being scaled for contrast control and a setup

level is added for brightness control. The Cr, Cb data is also

scaled and saturation control is added. The appropriate Sync,

Blank and Burst levels are then added to the YCrCb data. Mac-

rovision AntiTaping (ADV7172 only), Closed-Captioning and

Teletext levels are also added to Y, and the resultant data is

interpolated to a rate of 27 MHz. The interpolated data is fil-

tered and scaled by three digital FIR Filters.

The output video frames are synchronized with the incoming data

Timing Reference Codes. Optionally the encoder accepts (and can

generate) HSYNC, VSYNC, and FIELD timing signals. These

timing signals can be adjusted to change pulsewidth and position

while the part is in the master mode. The Encoder requires a

single two times pixel rate (27 MHz) clock for standard opera-

tion. Alternatively the Encoder requires a 24.5454 MHz clock

for NTSC or 29.5 MHz clock for PAL square pixel mode

operation. All internal timing is generated on-chip.

The U and V Signals are modulated by the appropriate sub-

carrier sine/cosine phases and a phase offset may be added onto

the color subcarrier during active video to allow hue adjustment.

The resulting U and V signals are then added together to make

up the chrominance signal. The luma (Y) signal can be delayed

1–3 luma cycles (each cycle is 74 ns) with respect to the chroma

signal. The luma and chroma signals are then added together to

make up the composite video signal. All edges are slew rate limited.

HSO/CSO and VSO TTL outputs, synchronous to the analog

output video, are also available. A programmable CLAMP out-

put signal is also available to enable clamping in either the front

or back porch of the video signal.

A separate teletext port enables the user to directly input teletext

data during the vertical blanking interval.

The YCrCb data is also used to generate RGB data with appro-

priate Sync and Blank levels.

The ADV7172/ADV7173 modes are set up over a 2-wire serial

bidirectional port (I²C-Compatible) with two slave addresses.

Functionally the ADV7173 and ADV7172 are the same with the

exception that the ADV7172 can output the Macrovision anti-

copy algorithm.

There are six DACs on the ADV7172/ADV7173. Three of these

DACs are capable of providing 34.66 mA of current. The other

three DACs provide 8.66 mA each.

The six l0-bit DACs can be used to output:

The ADV7172/ADV7173 is packaged in a 48-lead LQFP pack-

age (1.4 mm thickness).

1. Composite Video + RGB Video + LUMA + CHROMA.

2. Composite Video + YUV Video + LUMA + CHROMA.

DATA PATH DESCRIPTION

Alternatively, each DAC can be individually powered off if not

required. A complete description of DAC output configurations

is given in Appendix 8.

For PAL B, D, G, H, I, M, N, and NTSC M, N modes, YCrCb

4:2:2 Data is input via the CCIR-656-Compatible Pixel Port at a

27 MHz Data Rate. The Pixel Data is demultiplexed to form

three data paths. Y typically has a range of 16 to 235, Cr, and

Cb typically have a range of 128 112; however, it is possible to

Video output levels are illustrated in Appendix 6.

–2–

REV. B

ADV7172/ADV7173

SPECIFICATIONS

2

(V_AA= 5 V ꢁ 5%¹, V_REF= 1.235 V, R_SET1,2= 600 ꢂ unless otherwise noted. All specifications T_MINto T_MAX

unless otherwise noted.)

5 V SPECIFICATIONS

Parameter

Test Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity³

10

Bits

1.0

LSB

Differential Nonlinearity³

Guaranteed Monotonic

V_IN= 0.4 V or 2.4 V

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2

V

µA

pF

0.8

1

Input Capacitance, C_IN

10

DIGITAL OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

I_SOURCE= 400 µA

I_SINK= 3.2 mA

2.4

V

µA

pF

0.4

10

ANALOG OUTPUTS

Output Current (DACs A, B, C)⁴

Output Current (DACs A, B, C)⁵

Output Current (DACs D, E, F)⁶

Output Current (DACs D, E, F)⁵

DAC-to-DAC Matching (DACs A, B, C)⁷

DAC-to-DAC Matching (DACs D, E, F)⁷

Output Compliance, V_OC

R_SET1= 150 Ω, R_L= 37.5 Ω

R_SET1= 1041 Ω, R_L= 262.5 Ω

R_SET2= 600 Ω, R_L= 150 Ω

R_SET2= 1041 Ω, R_L= 262.5 Ω

33

34.7

37

mA

%

5

8.66

5

1

8.25

9.25

4.0

1.4

%

V

0

Output Impedance, R_OUT

Output Capacitance, C_OUT

30

kΩ

pF

I_OUT= 0 mA

30

VOLTAGE REFERENCE

Reference Range, V_REF

I_VREFOUT= 20 µA

1.112

4.75

1.235

5.0

1.359

V

POWER REQUIREMENTS

V_AA

5.25

65

Normal Power Mode

I

_DAC(max)^{8, 9}

R_SET1,2= 600 Ω

R_SET1,2= 1041 Ω

59

30

78

mA

I_DAC(min)^{8, 9}

10

I_CCT

90

Low Power Mode

I_DAC(max)¹¹

R_SET1= 150 Ω

64

15

78

mA

I_DAC(min)¹¹

10

I_CCT

90

Sleep Mode

12

I_DAC

I_CCT

0.1

0.01

µA

13

µA

Power Supply Rejection Ratio

COMP = 0.1 µF

0.5

%/%

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³Characterized by design.

⁴Full drive into 75 Ω doubly terminated load.

⁵Minimum drive current (used with buffered/scaled output load).

⁶Full drive into 150 Ω load.

⁷Specification guaranteed by characterization.

⁸I_DACis the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC) to drive DACs A, B, C, D, E, F. Turning off

individual DACs reduces I_DACcorrespondingly, also DACs A, B, C can be configured to output a max current of 37 mA but DAC D, E, F must be turned off.

⁹All six DACs on (DAC A, B, C, D, E, F).

10

I

(Circuit Current) is the continuous current required to drive the device.

CCT

¹¹Only large DACs (DACs A, B, C) on per low power mode.

¹²Total DAC current in Sleep Mode.

¹³Total continuous current during Sleep Mode.

Specifications subject to change without notice.

–3–

REV. B

ADV7172/ADV7173–SPECIFICATIONS

2

(V_AA= 3.0 V–3.6 V¹, V_REF= 1.235 V, R_SET1,2= 600 ꢂ unless otherwise noted. All specifications T_MINto T_MAX

unless otherwise noted.)

3.3 V SPECIFICATIONS

Parameter

Test Conditions¹

Min

Typ

Max

Unit

STATIC PERFORMANCE³

Resolution (Each DAC)

Accuracy (Each DAC)

Integral Nonlinearity

10

Bits

1.0

LSB

Differential Nonlinearity

Guaranteed Monotonic

V_IN= 0.4 V or 2.4 V

DIGITAL INPUTS³

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2

0.8

V

µA

pF

1

Input Capacitance, C_IN

10

DIGITAL OUTPUTS³

Output High Voltage, V_OH

Output Low Voltage, V_OL

Three-State Leakage Current

Three-State Output Capacitance

I_SOURCE= 400 µA

I_SINK= 3.2 mA

2.4

0.4

V

µA

pF

10

ANALOG OUTPUTS³

Output Current (DACs A, B, C)⁴

Output Current (DACs A, B, C)⁵

Output Current (DACs D, E, F)⁶

Output Current (DACs D, E, F)⁵

DAC-to-DAC Matching (DACs A, B, C)³

DAC-to-DAC Matching (DACs D, E, F)³

Output Compliance, V_OC

R_SET1= 150 Ω, R_L= 37.5 Ω

R_SET1= 1041 Ω, R_L= 262.5 Ω

R_SET2= 600 Ω, R_L= 150 Ω

R_SET2= 1041 Ω, R_L= 262.5 Ω

34.7

mA

%

V

5

8.66

5

1

4.0

1.4

Output Impedance, R_OUT

Output Capacitance, C_OUT

30

kΩ

pF

I_OUT= 0 mA

30

POWER REQUIREMENTS^{3, 7}

V_AA

3.0

3.3

3.6

65

V

Normal Power Mode

I_DAC(max)^{8, 9}

R_SET1,2= 600 Ω

R_SET1,2= 1041 Ω

58

30

40

mA

I

_DAC(min)⁸

10

I_CCT

Sleep Mode

11

I_DAC

I_CCT

0.1

0.01

µA

12

µA

Power Supply Rejection Ratio

COMP = 0.1 µF

%/%

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³Guaranteed by characterization.

⁴Full drive into 75 Ω doubly terminated load.

⁵Minimum drive current (used with buffered/scaled output load).

⁶Full Drive into 150 Ω load.

⁷Power measurements are taken with Clock Frequency = 27 MHz. Max T_J= 110°C.

⁸I_DACis the total current (“min” corresponds to 5 mA output per DAC, “max” corresponds to 8.66 mA output per DAC) to drive DACs A, B, C, D, E, F. Turning off

individual DACs reduces I_DACcorrespondingly, also DACs A, B, C can be configured to output a max current of 37 mA.

⁹DACs A, B, C can output 35 mA typically at 3.3 V (R_SET= 150 Ω and R_L= 37.5 Ω), optimum performance obtained at 18 mA DAC Current (R_SET= 300 Ω and

R_L= 75 Ω).

10

I

(Circuit Current) is the continuous current required to drive the device.

CCT

¹¹Total DAC current in Sleep Mode.

¹²Total continuous current during Sleep Mode.

Specifications subject to change without notice.

–4–

REV. B

ADV7172/ADV7173

(V_AA= 5 V ꢁ 5%¹, V_REF= 1.235 V, R_SET1,2= 600 ꢂ unless otherwise noted. All

specifications T_MINto T_MAX²unless otherwise noted.)

5 V DYNAMIC SPECIFICATIONS

Parameter

Conditions¹

Min

Typ

Max

Unit

Differential Gain^{3, 4}

Normal Power Mode

0.3

0.4

0.5

2.0

75

66

60

0.7

1.0

3.0

%

Degrees

%

Differential Phase^{3, 4}

Normal Power Mode

Lower Power Mode

RMS

Peak Periodic

RMS

Differential Gain^{3, 4}

Differential Phase^{3, 4}

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

Degrees

%

ns

%

dB

SNR^{3, 4}(Pedestal)

SNR^{3, 4}(Ramp)

Peak Periodic

58

Hue Accuracy^{3, 4}

0.7

0.9

1.2

0.3

0.2

1.0

0.5

1.0

82

Color Saturation Accuracy^{3, 4}

Chroma Nonlinear Gain^{3, 4}

Chroma Nonlinear Phase^{3, 4}

Chroma/Luma Intermod^{3, 4}

Chroma/Luma Gain Inequality^{3, 4}

Chroma/Luma Delay Inequality^{3, 4}

Luminance Nonlinearity^{3, 4}

Chroma AM Noise^{3, 4}

Chroma PM Noise^{3, 4}

Referenced to 40 IRE

0.5

0.4

1.7

79

80

dB

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³These specifications are for the low-pass filter only and guaranteed by design.

⁴Guaranteed by characterization.

Specifications subject to change without notice.

(V_AA= 3.0 V–3.6 V¹, V_REF= 1.235 V, R_SET1,2= 600 ꢂ unless otherwise noted. All

specifications T_MINto T_MAX²unless otherwise noted.)

3.3 V DYNAMIC SPECIFICATIONS

Parameter

Conditions¹

Min

Typ

Max

Unit

Differential Gain³

Normal Power Mode

Lower Power Mode

RMS

Peak Periodic

RMS

Peak Periodic

0.6

0.5

1.0

0.5

75

70

60

58

1.0

1.1

83

%

Degrees

%

Degrees

dB rms

dB p-p

dB rms

dB p-p

Degrees

%

dB

%

Differential Phase³

Differential Gain³

Differential Phase³

SNR³(Pedestal)

SNR³(Ramp)

Hue Accuracy³

Color Saturation Accuracy³

Luminance Nonlinearity³

Chroma AM Noise³

Chroma PM Noise³

Chroma Nonlinear Gain^{3, 4}

Chroma Nonlinear Phase^{3, 4}

Chroma/Luma Intermod^{3, 4}

79

Referenced to 40 IRE

1.2

0.3

0.2

Degrees

%

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³Guaranteed by characterization.

⁴These specifications are for the low-pass filter only and guaranteed by design.

Specifications subject to change without notice.

–5–

REV. B

ADV7172/ADV7173

5 V TIMING SPECIFICATIONS

Parameter

(V_AA= 5 V ꢁ 5%¹, V_REF= 1.235 V, R_SET1= 600 ꢂ unless otherwise noted. All specifications T_MIN

to T_MAX²unless otherwise noted.)

Conditions

Min

Typ

Max

Unit

MPU PORT^{3, 4}

SCLOCK Frequency

0

400

kHz

µs

SCLOCK High Pulsewidth, t₁

SCLOCK Low Pulsewidth, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

0.6

1.3

0.6

100

µs

After this period the 1st clock is generated

relevant for repeated Start Condition.

µs

ns

µs

300

0.6

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

7

0

ns

CLOCK CONTROL AND

PIXEL PORT^{5, 6}

f_CLOCK

27

MHz

ns

Clock High Time, t₉

Clock Low Time, t₁₀

Data Setup Time, t₁₁

Data Hold Time, t₁₂

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

Digital Output Hold Time, t₁₄

Pipeline Delay, t₁₅

8

4.0

5.0

4

3

15

10

37

24

ns

Clock Cycles

TELETEXT PORT^{3, 7}

Digital Output Access Time, t₁₆

Data Setup Time, t₁₇

20

2

6

ns

Data Hold Time, t₁₈

RESET CONTROL³

RESET Low Time

3

ns

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

⁶Pixel Port consists of the following:

Pixel Inputs:

Pixel Controls:

Clock Input:

P7–P0

HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP

CLOCK

⁷Teletext Port consists of the following:

Teletext Output:

Teletext Input:

TTXREQ

TTX

Specifications subject to change without notice.

–6–

REV. B

ADV7172/ADV7173

(V_AA= 3.0 V–3.6 V¹, V_REF= 1.235 V, R_SET1,2= 600 ꢂ. All specifications T_MINto T_MAX²unless

3.3 V TIMING SPECIFICATIONS otherwise noted.)

Parameter

Conditions

Min

Typ

Max

Unit

MPU PORT^{3, 4}

SCLOCK Frequency

0

400

kHz

µs

SCLOCK High Pulsewidth, t₁

SCLOCK Low Pulsewidth, t₂

Hold Time (Start Condition), t₃

Setup Time (Start Condition), t₄

Data Setup Time, t₅

SDATA, SCLOCK Rise Time, t₆

SDATA, SCLOCK Fall Time, t₇

Setup Time (Stop Condition), t₈

0.6

1.3

0.6

100

µs

After this period the 1st clock is generated

relevant for repeated Start Condition.

µs

ns

µs

300

0.6

ANALOG OUTPUTS^{3, 5}

Analog Output Delay

DAC Analog Output Skew

7

0

ns

CLOCK CONTROL AND

PIXEL PORT^{4, 5, 6}

f_CLOCK

27

MHz

Clock High Time, t₉

Clock Low Time, t₁₀

Data Setup Time, t₁₁

Data Hold Time, t₁₂

Control Setup Time, t₁₁

Control Hold Time, t₁₂

Digital Output Access Time, t₁₃

Digital Output Hold Time, t₁₄

Pipeline Delay, t₁₅

8

4.0

5

ns

3

20

12

37

Clock Cycles

TELETEXT PORT^{3, 4, 7}

Digital Output Access Time, t₁₆

Data Setup Time, t₁₇

23

2

6

ns

Data Hold Time, t₁₈

RESET CONTROL^{3, 4}

RESET Low Time

3

ns

NOTES

¹The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.

²Temperature range T_MINto T_MAX: 0°C to 70°C.

³TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load ≤ 10 pF.

⁴Guaranteed by characterization.

⁵Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

⁶Pixel Port consists of the following:

Pixel Inputs:

Pixel Controls:

Clock Input:

P7–P0

HSYNC, FIELD/VSYNC, BLANK, VSO, CSO_HSO, CLAMP

CLOCK

⁷Teletext Port consists of the following:

Teletext Output:

Teletext Input:

TTXREQ

TTX

Specifications subject to change without notice.

REV. B

–7–

ADV7172/ADV7173

t₅

t₃

SDATA

t₆

t₁

SCLOCK

t₂

t₇

t₄

t₈

Figure 1. MPU Port Timing Diagram

CLOCK

t₁₂

t₉

t₁₀

HSYNC,

FIELD/VSYNC,

CONTROL

I/PS

BLANK

PIXEL INPUT

DATA

Cb

Y

Cr

Y

Cb

Y

t₁₁

t₁₃

HSYNC,

FIELD/VSYNC,

BLANK,

CONTROL

O/PS

CSO_HSO,

VSO, CLAMP

t₁₄

Figure 2. Pixel and Control Data Timing Diagram

TTXREQ

CLOCK

t₁₆

t₁₇

t₁₈

TTX

4 CLOCK

CYCLES

4 CLOCK

CYCLES

4 CLOCK

CYCLES

3 CLOCK

CYCLES

4 CLOCK

CYCLES

Figure 3. Teletext Timing Diagram

DAC Average Current Consumption

DAC D, E, F: The average current consumed by each DAC is the DAC output current as determined by R_SET2/V_REF(see Appendix 8).

DAC A, B, C: In normal power mode the average current consumed by each DAC is the DAC output current as determined by R_SET1

(see Appendix 8).

In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by R_SET1.

Consult AN-551 for detailed information on ADV7172/ADV7173 power management.

–8–

REV. B

ADV7172/ADV7173

PACKAGE THERMAL PERFORMANCE

ABSOLUTE MAXIMUM RATINGS¹

V_AAto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Voltage on Any Digital Input Pin . GND – 0.5 V to V_AA+ 0.5 V

Storage Temperature (T_S) . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T_J) . . . . . . . . . . . . . . . . . . . . . . 150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . 260°C

Analog Outputs to GND². . . . . . . . . . . GND – 0.5 V to V_AA

The 48-lead LQFP package is used for this device. The junc-

tion-to-ambient (θ_JA) thermal resistance in still air on a four

layer PCB is 54.6°C/W. The junction-to-case thermal resistance

(θ_JC) is 16.7°C.

To reduce power consumption when using this part the user is

advised to run the part on a 3.3 V supply, turn off any unused

DACs. However, if 5 V operation is required the user can enable

Low Power mode by setting MR16 to a Logic 1. Another alter-

native way to further reduce power is to use external buffers that

dramatically reduce the DAC currents, the current can be low-

ered to as low as 5 mA (see AN-551 and Appendix 8 for more

details) from a nominal value of 36 mA.

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

²Analog output short circuit to any power supply or common can be of an

indefinite duration.

The user must at all times stay below the maximum junction

temperature of 110°C. The following equation shows how to

calculate this junction temperature:

PIN CONFIGURATION

J

unction Temperature = [V_AA(I_DAC+ I_CCT) × θ_JA] 70°C

where

_DAC= 10 mA + (sum of the average currents consumed by each

powered-on DAC).

I

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

V

COMP1

DAC A

AA

P0

PIN 1

IDENTIFIER

ORDERING GUIDE

3

P1

P2

P3

P4

P5

P6

P7

V

AA

4

DAC B

Temperature

Range

Package

Description

Package

Option

5

V

AA

ADV7172/ADV7173

6

Model

GND

TOP VIEW

(Not to Scale)

7

V

AA

ADV7172KST 0°C to 70°C

Plastic Thin

Quad Flatpack

ST-48

8

DAC C

DAC D

9

10

11

12

ADV7173KST 0°C to 70°C

Plastic Thin

Quad Flatpack

ST-48

CSO HSO

V

AA

V

GND

AA

GND

DAC E

13 14 15 16 17 18 19 20 21 22 23 24

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the ADV7172/ADV7173 features proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,

proper ESD precautions are recommended to avoid performance degradation or loss of

functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–9–

ADV7172/ADV7173

PIN FUNCTION DESCRIPTION

Function

Mnemonic

Input/Output

P7–P0

CLOCK

I

8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) P0 represents the LSB.

TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alter-

natively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

HSYNC

I/O

HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master

Mode) or as an input and accept (Slave Mode) Sync signals.

Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be

configured to output (Master Mode) or as an input (Slave Mode) and accept these

control signals.

FIELD/VSYNC

BLANK

I/O

I

Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level “0.”

This signal is optional.

This pin can be configured as an input by setting MR42 and MR41 of Mode Register 4. It

can be configured as a subcarrier reset pin, in which case a low-to-high transition on this

pin will reset the subcarrier phase to Field 0. Alternatively it may be configured as a Real-

Time Control (RTC) Input.

SCRESET/RTC

V_REF

R_SET1

I/O

I

Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of

the Video Signals from DACs A, B, and C (the “large” DACs).

R_SET2

I

A 600 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of

the Video Signals from DACs D, E, and F (the “small” DACs).

COMP1

O

Compensation Pin for DACs A, B, and C. Connect a 0.1 µF Capacitor from COMP to

V_AA. For Optimum Dynamic Performance in Low Power Mode, the value of the

COMP1 capacitor can be lowered to as low as 2.2 nF.

COMP2

DAC A

DAC B

DAC C

DAC D

DAC E

O

I

I/O

O

I

O

I

Compensation Pin for DACs D, E, and F. Connect a 0.1 µF Capacitor from COMP to V_AA.

GREEN/Composite/Y Analog Output. This DAC is capable of providing 34.66 mA output.

BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 34.66 mA output.

RED/S-Video C/V Analog Output. This DAC is capable of providing 34.66 mA output.

GREEN/Composite/Y Analog Output. This DAC is capable of providing 8.66 mA output.

BLUE/S-Video Y/U Analog Output. This DAC is capable of providing 8.66 mA output.

RED/S-Video C/V Analog Output. This DAC is capable of providing 8.66 mA output.

MPU Port Serial Interface Clock Input.

DAC F

SCLOCK

SDATA

CLAMP

PAL_NTSC

VSO

MPU Port Serial Data Input/Output.

TTL Output Signal to external circuitry to enable clamping of all video signals.

Input signal to select PAL or NTSC mode of operation, pin set to Logic “1” selects PAL.

VSO TTL Output Sync Signal.

Dual Function CSO or HSO TTL Output Sync Signal.

TTL Address Input. This signal sets up the LSB of the MPU address.

CSO_HSO

ALSB

RESET

I

The input resets the on-chip timing generator and sets the ADV7172/ADV7173 into

default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered

OFF, DACs D, E, and F powered ON, Composite and S-Video out.

TTX

I

Teletext Data Input Pin.

TTXREQ

V_AA

GND

O

P

G

Teletext Data Request output signal used to control teletext data transfer.

Power Supply (3 V to 5 V).

Ground Pin.

–10–

REV. B

ADV7172/ADV7173

(continued from page 2)

In Extended Mode there is the option of twelve responses

in the range from –4 dB to +4 dB. The desired response can

be chosen by the user by programming the correct value via

the I²C. The variation of frequency responses can be seen in

Figures 19 to 21.

INTERNAL FILTER RESPONSE

The Y Filter supports several different frequency responses,

including two low-pass responses, two notch responses, an

Extended (SSAF) response with or without gain boost/attenuation,

a CIF response and a QCIF response. The UV Filter supports

several different frequency responses, including four low-pass

responses, a CIF response and a QCIF response. These can be

seen in Figures 4 to 18.

PASSBAND RIPPLE 3 dB BANDWIDTH

STOPBAND

FILTER TYPE

FILTER SELECTION

MR04 MR03 MR02

(dB)

(MHz)

CUTOFF (MHz) ATTENUATION (dB)

0.091

0.15

0.015

0.095

0.051

0.018

MONOTONIC

LOW-PASS (NTSC)

LOW-PASS (PAL)

NOTCH (NTSC)

NOTCH (PAL)

EXTENDED (SSAF)

CIF

0

1

0

1

0

1

0

1

0

1

0

1

0

4.157

4.74

6.54

6.24

6.217

3.0

7.37

7.96

8.3

8.0

7.06

7.15

–56

–64

–68

–66

–61

–50

QCIF

1.5

Figure 4. Luminance Internal Filter Specifications

STOPBAND

PASSBAND RIPPLE 3 dB BANDWIDTH

FILTER TYPE

FILTER SELECTION

CUTOFF (MHz) ATTENUATION (dB)

(dB)

(MHz)

MR07 MR06 MR05

3.01

3.64

3.73

5.0

–45

–58.5

–49

1.3MHz LOW PASS

0.65MHz LOW PASS

1.0MHz LOW PASS

2.0MHz LOW PASS

RESERVED

CIF

QCIF

0

1

0

1

0

1

0

1

0

1

0

1

0

0.084

1.395

0.65

1.0

MONOTONIC

0.0645

–40

2.2

3.01

4.08

–45

–50

0.084

MONOTONIC

0.7

0.5

Figure 5. Chrominance Internal Filter Specifications

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

0

2

4

6

8

10

12

FREQUENCY – MHz

Figure 7. PAL Low-Pass Luma Filter

Figure 6. NTSC Low-Pass Luma Filter

REV. B

–11–

ADV7172/ADV7173

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

FREQUENCY – MHz

Figure 8. NTSC Notch Luma Filter

Figure 11. CIF Luma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

14

2

4

6

8

10

12

FREQUENCY – MHz

Figure 9. PAL Notch Luma Filter

Figure 12. QCIF Luma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

14

2

4

6

8

10

12

FREQUENCY – MHz

Figure 10. Extended Mode (SSAF) Luma Filter

Figure 13. 1.3 MHz Low-Pass Chroma Filter

–12–

REV. B

ADV7172/ADV7173

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

FREQUENCY – MHz

Figure 14. 0.65 MHz Low-Pass Chroma Filter

Figure 17. CIF Chroma Filter

0

–10

–20

–30

–40

–50

–60

–70

0

–10

–20

–30

–40

–50

–60

–70

0

2

4

6

8

10

12

14

2

4

6

8

10

12

14

FREQUENCY – MHz

Figure 15. 1.0 MHz Low-Pass Chroma Filter

Figure 18. QCIF Chroma Filter

0

–10

–5

–20

–30

–40

–50

–60

–70

–10

–15

–20

–25

0

2

4

6

8

10

12

14

1

2

3

4

5

6

7

8

FREQUENCY – MHz

Figure19. ExtendedModeLumaFilterwithProgrammable

Gain, Negative Response

Figure 16. 2.0 MHz Low-Pass Chroma Filter

REV. B

–13–

ADV7172/ADV7173

4

2

4

3

0

2

–2

–4

–6

–8

–10

–12

1

0

–1

–2

–3

0

1

2

3

4

5

6

1

2

3

4

5

6

7

FREQUENCY – MHz

Figure 21. Extended Mode Luma Filter with Programmable

Gain, Combined Response

Figure20. ExtendedModeLumaFilterwithProgrammable

Gain, Positive Response

onto the Y data in PAL mode, NTSC mode without pedestal or

NTSC mode with pedestal, in which case it is added directly

onto the 7.5 IRE pedestal already present.

COLOR BAR GENERATION

The ADV7172/ADV7173 can be configured to generate 100/

7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for

PAL. These are enabled by setting MR46 of Mode Register 4 to

Logic “1.”

The level added is programmed by the user into the Brightness

Control Register (Bits 4–0) and the user is capable of adding

from 0 IRE to a maximum of 14 IRE in 32 (2⁵) steps. Because

of different gains in the datapath for each mode, different values

may need to be programmed to obtain the same IRE setup level

in each mode. Maximum brightness is achieved when 31 is

programmed into the Brightness Control Register. Table I illus-

trates the maximum setup/brightness amplitudes available in the

various modes. Note that if a level of less than 7.5 IRE is required

on the Y data in NTSC mode, then NTSC without pedestal

must be the mode selected.

SQUARE PIXEL MODE

The ADV7172/ADV7173 can be used to operate in square pixel

mode. For NTSC operation, an input clock of 24.5454 MHz is

required. Alternatively, for PAL operation, an input clock of

29.5 MHz is required. The internal timing logic adjusts accord-

ingly for square pixel mode operation.

COLOR SIGNAL CONTROL

The color information can be switched on and off the video

output using Bit MR44 of Mode Register 4.

Table I. Maximum Brightness Levels Available

Brightness Control

BURST SIGNAL CONTROL

The burst information can be switched on and off the video

output using Bit MR45 of Mode Register 4.

Mode

Register

Setup

NTSC PEDESTAL CONTROL

NTSC No Pedestal

NTSC Pedestal

PAL

00011111

14 IRE

13 IRE

99 mV

The pedestal on both odd and even fields can be controlled on a

line-by-line basis using the NTSC Pedestal Control Registers.

This allows the pedestals to be controlled during the Vertical

Blanking Interval.

Color Saturation Control

Color adjustment is achieved by scaling the Cr and Cb input

data by a factor programmed by the user into the Color Control

Registers 1 and 2, Bits 5–0. This factor allows the data to be

scaled between 75% and 125%.

COLOR CONTROLS

The ADV7172/ADV7173 allows the user the advantage of control-

ling the brightness, contrast, hue and saturation of the color.

Contrast Control

Hue Control

Contrast adjustment is achieved by scaling the Y input data

by a factor programmed by the user into the Contrast Control

Register Bits 5–0. This factor allows the data to be scaled

between 75% and 125%.

The hue adjustment is achieved on the composite and chroma

outputs by adding a phase offset onto the color subcarrier in the

active video but leaving the color burst unmodified, i.e., only

the phase between the video and the color burst is modified

and hence the hue is shifted. Hue adjustment is under the con-

trol of the Hue Control Register. The ADV7172/ADV7173

provides a range of 22° change in increments of 0.17578125°.

Brightness Control

The brightness is controlled by adding a programmable setup

level onto the scaled Y data. This brightness level may be added

–14–

REV. B

ADV7172/ADV7173

YUV LEVELS

SUBCARRIER RESET

This functionality is under the control of Mode Register 5, Bits

2–0. Bit 0 (MR50) allows the ADV7172/ADV7173 to output

SMPTE levels on the Y output when configured in NTSC mode,

and Betacam levels on the Y output when configured in PAL

mode and vice-versa.

Together with the SCRESET/RTC PIN and Bits MR42 and

MR41 of Mode Register 4, the ADV7172/ADV7173 can be

used in subcarrier reset mode. The subcarrier phase will reset to

Field 0 at the start of the following field when a low to high

transition occurs on this input pin.

Video

Sync

REAL-TIME CONTROL

Betacam

SMPTE

MII

286 mV

300 mV

714 mV

700 mV

Together with the SCRESET/RTC PIN and Bits MR42 and

MR41 of Mode Register 4, the ADV7172/ADV7173 can be

used to lock to an external video source. The real-time control

mode allows the ADV7172/ADV7173 to automatically alter the

subcarrier frequency to compensate for line length variation.

When the part is connected to a device that outputs a digital

data stream in the RTC format (such as a ADV7185 video

decoder, see Figure 22), the part will automatically change to

the compensated subcarrier frequency on a line-by-line basis.

This digital data stream is 67 bits wide and the subcarrier is

contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex

should be written into all four subcarrier frequency registers

when using this mode.

As the datapath is branched at the output of the filters, the

luma signal relating to the CVBS or S-Video Y/C output is

unaltered. Only the Y output of the YUV outputs is scaled.

Bits 2–1 (MR52–MR51) allow UV levels to have a peak-peak

amplitude of 700 mV or 1000 mV, or the default values of

934 mV in NTSC and 700 mV in PAL.

AUTODETECT CONTROL

The ADV7172/ADV7173 provides the option of automatically

powering down the DACs A, B and C if they are not correctly

terminated (i.e., the 75 Ω cable is not connected to the DAC).

The voltage at the output of DACs A and B are compared to

a selected reference level. This reference voltage (MR64) will

depend on whether the user terminates with 37.5 Ω (75 Ω con-

nected on the DAC end and 75 Ω connected at TV end of cable,

i.e., combined load of 37.5 Ω) or 75 Ω. It cannot operate in a

DAC buffering configuration. There are two modes of auto-

detect operation provided by the ADV7172/ADV7173:

VIDEO TIMING DESCRIPTION

The ADV7172/ADV7173 is intended to interface to off-the-

shelf MPEG1 and MPEG2 Decoders. As a consequence, the

ADV7172/ADV7173 accepts 4:2:2 YCrCb Pixel Data via a

CCIR-656 pixel port and has several video timing modes of

operation that allow it to be configured as either system master

video timing generator or a slave to the system video timing

generator. The ADV7172/ADV7173 generates all of the required

horizontal and vertical timing periods and levels for the analog

video outputs.

(1) Mode 0: The state of termination of the DAC may be read

by reading the status bits in Mode Register 6. MR67 status bit

indicates whether or not the composite DAC is terminated,

MR66 status bit indicates whether or not the luma DAC is

terminated. The user may then decide whether or not to power

down the DACs using MR15–MR0.

The ADV7172/ADV7173 calculates the width and placement

of analog sync pulses, blanking levels and color burst envelopes.

Color bursts are disabled on appropriate lines and serration and

equalization pulses are inserted where required.

(2) Mode 1: The state of the DACs may be read as in Mode 0.

If either of the DACs is unterminated, they are automatically

powered down. If the luma DAC, DAC B is powered down then

DAC C, the chroma DAC, will also be powered down. The

state of termination of the DAC is checked each frame to decide

whether or not it is to be powered up or down.

In addition, the ADV7172/ADV7173 supports a PAL or NTSC

square pixel operation in slave mode. The part requires an input

pixel clock of 24.5454 MHz for NTSC and an input pixel clock

of 29.5 MHz for PAL. The internal horizontal line counters place

the various video waveform sections in the correct location for

the new clock frequencies.

Mode Register 6, Bits 3–2, indicates which mode of operation is

used. Note that Mode Register 1, Bits 5-3, must be enabled

(“1”) for autodetect functionality to work. (DACs A, B, C are

enabled.)

The ADV7172/ADV7173 has four distinct master and four

distinct slave timing configurations. Timing control is estab-

lished with the bidirectional SYNC, BLANK, and FIELD/

VSYNC pins. Timing Mode Register 1 can also be used to

vary the timing pulsewidths and where they occur in relation to

each other.

Vertical Blanking Data Insertion

It is possible to allow encoding of incoming YCbCr data on

those lines of VBI that do not have line sync or pre-/post-

equalization pulses (see Figures 24 to 25). This mode of

operation is called “Partial Blanking” and is selected by setting

MR32 to “1.” It allows the insertion of any VBI data (Opened

VBI) into the encoded output waveform. This data is present in

digitized incoming YCbCr data stream (e.g., WSS data, CGMS,

VPS etc.). Alternatively the entire VBI may be blanked (no VBI

data inserted) on these lines by setting MR32 to “0.”

REV. B

–15–

ADV7172/ADV7173

CLOCK

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

LCC1

GLL

GREEN/COMPOSITE/Y

BLUE/LUMA/U

SCRESET/RTC

P7–P0

RED/CHROMA/V

P19-P12

GREEN/COMPOSITE/Y

BLUE/LUMA/U

HSYNC

RED/CHROMA/V

VIDEO

DECODER

ADV7185

FIELD/VSYNC

ADV7172/ADV7173

SEQUENCE

2

BIT

H/LTRANSITION

COUNT START

RESET

3

BIT

4 BITS

RESERVED

5 BITS

RESERVED

LOW

RESERVED

14 BITS

RESERVED

1

128

FSCPLL INCREMENT

13

0

21

RTC

14

19

TIME SLOT: 01

67 68

NOT USED IN

ADV7172/ADV7173

8/LLC

VALID

INVALID

SAMPLE SAMPLE

NOTES

1

2

3

F

PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7172/ADV7173 FSC DDS REGISTER IS F PLL INCREMENT BITS 21:0 PLUS BITS 0:9

SC

OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE

ADV7172/ADV7173.

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED

NTSC: 0 = NO CHANGE

RESET BIT

RESET ADV7172/ADV7173’s DDS

Figure 22. RTC Timing and Connections

Mode 0 (CCIR–656): Slave Option

(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data.

All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before

and after each line during active picture and retrace. Mode 0 is illustrated in Figure 23. The HSYNC, FIELD/VSYNC, and BLANK

(if not used) pins should be tied high during this mode.

ANALOG

VIDEO

EAV CODE

SAV CODE

0

1

0

8

0

1

0

C

r

F

X

Y

8

0

8

0

1

0

1

0

F

0

X

Y

C

b

C

b

C

r

C

b

0

F

F A

F B

A

B

A

B

8

0

C

r

INPUT PIXELS

Y

ANCILLARY DATA

(HANC)

4 CLOCK

NTSC/PAL M SYSTEM

(525 LlNES/60Hz)

268 CLOCK

1440 CLOCK

PAL SYSTEM

(625 LINES/50Hz)

280 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

Figure 23. Timing Mode 0 (Slave Mode)

–16–

REV. B

ADV7172/ADV7173

Mode 0 (CCIR–656): Master Option

(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7172/ADV7173 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video)

Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit

is output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). The H, V, and F transitions

relative to the video waveform are illustrated in Figure 26.

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

10

11

20

21

22

5

9

8

H

V

F

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

H

V

F

ODD FIELD

EVEN FIELD

Figure 24. Timing Mode 0 (NTSC Master Mode)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

22

23

5

21

H

V

F

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

335

336

318

334

309

310

311

312

313

314

315

316

317

319

320

H

V

F

ODD FIELD EVEN FIELD

Figure 25. Timing Mode 0 (PAL Master Mode)

–17–

REV. B

ADV7172/ADV7173

ANALOG

VIDEO

H

F

V

Figure 26. Timing Mode 0 Data Transitions (Master Mode)

Mode 1: Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode the ADV7172/ADV7173 accepts horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input

when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis-

abled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 27

(NTSC) and Figure 28 (PAL).

DISPLAY

VERTICAL BLANK

7

6

8

10

522

523

524

525

9

11

20

21

22

1

2

3

4

5

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

266

267

268

269

270

271

272

273

274

283

284

285

260

261

262

263

264

265

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 27. Timing Mode 1 (NTSC)

–18–

REV. B

ADV7172/ADV7173

DISPLAY

VERTICAL BLANK

21

22

23

622

623

624

625

1

2

3

4

5

6

7

HSYNC

BLANK

FIELD

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

309

310

311

312

313

314

315

316

317

318

319

320

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD EVEN FIELD

Figure 28. Timing Mode 1 (PAL)

Mode 1: Master Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode the ADV7172/ADV7173 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD

input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is

disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising

clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus-

trates the HSYNC, BLANK, and FIELD for an odd-or-even field transition relative to the pixel data.

HSYNC

FIELD

PAL = 12 * CLOCK/2

NTSC = 16 * CLOCK/2

BLANK

PIXEL

DATA

Cr

Y

Cb

Y

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 29. Timing Mode 1 Odd/Even Field Transitions Master/Slave

REV. B

–19–

ADV7172/ADV7173

Mode 2: Slave Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode the ADV7172/ADV7173 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and

VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field.

The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally

blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

20

21

22

1

2

3

4

6

7

8

10

11

5

9

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

DISPLAY

VERTICAL BLANK

283

285

284

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

HSYNC

BLANK

VSYNC

EVEN FIELD

ODD FIELD

Figure 30. Timing Mode 2 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

6

7

5

21

22

23

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

312

309

310

311

313

314

315

316

318

319

320

335

336

317

334

HSYNC

BLANK

VSYNC

ODD FIELD

EVEN FIELD

Figure 31. Timing Mode 2 (PAL)

–20–

REV. B

ADV7172/ADV7173

Mode 2: Master Option HSYNC, VSYNC, BLANK

(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode the ADV7172/ADV7173 can generate horizontal and vertical SYNC signals. A coincident low transition of both

HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of

an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all

normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL). Figure 32 illustrates the

HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 33 illustrates the HSYNC,

BLANK, and VSYNC for an odd-to-even field transition relative to the pixel data.

HSYNC

VSYNC

PAL = 12 * CLOCK/2

BLANK

NTSC = 16 * CLOCK/2

PIXEL

DATA

Cb

Y

Cr

Y

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 32. Timing Mode 2 Even-to-Odd Field Transition Master/Slave

HSYNC

VSYNC

PAL = 864 * CLOCK/2

NTSC = 858 * CLOCK/2

PAL = 12 * CLOCK/2

NTSC = 16 * CLOCK/2

BLANK

PIXEL

DATA

Cb

Y

Cr

Y

Cb

PAL = 132 * CLOCK/2

NTSC = 122 * CLOCK/2

Figure 33. Timing Mode 2 Odd-to-Even Field Transition Master/Slave

REV. B

–21–

ADV7172/ADV7173

Mode 3: Master/Slave Option HSYNC, BLANK, FIELD

(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode the ADV7172/ADV7173 accepts or generates horizontal SYNC and Odd/Even FIELD signals. A transition of the

FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK

input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in

Figure 34 (NTSC) and Figure 35 (PAL).

DISPLAY

VERTICAL BLANK

522

523

524

525

1

2

3

4

6

7

9

10

11

20

21

22

5

8

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 34. Timing Mode 3 (NTSC)

DISPLAY

VERTICAL BLANK

622

623

624

625

1

2

3

4

5

6

7

21

22

23

HSYNC

BLANK

FIELD

EVEN FIELD ODD FIELD

DISPLAY

VERTICAL BLANK

318

309

310

311

312

313

314

315

316

317

319

320

334

335

336

HSYNC

BLANK

FIELD

ODD FIELD

EVEN FIELD

Figure 35. Timing Mode 3 (PAL)

–22–

REV. B

ADV7172/ADV7173

POWER-ON RESET

SLEEP MODE

After power-up, it is necessary to execute a reset operation. A

reset occurs on the falling edge of a high-to-low transition on

the RESET pin. This initializes the pixel port such that the pixel

inputs P7–P0 are not selected. After reset, the ADV7172/

ADV7173 is automatically set up to operate in NTSC/PAL mode,

depending on the PAL_NTSC pin. The subcarrier frequency

registers are automatically loaded with the correct values for

PAL or NTSC. All other registers, with the exception of Mode

Registers 1 and 2, are set to 00H. Mode Register 1 is set to 07H.

This is to ensure DACs D, E, and F are ON after power-up.

All bits of Mode Register 2 are set to “0,” with the exception of

Bit 3 (i.e., Mode Register 2 reads 08H). Bit MR23 of Mode

Register 2 is set to Logic “1.” This enables the 7.5 IRE pedestal.

If after reset the SCRESET/RTC and NTSC_PAL pins are

both set to high, the part ADV7172/ADV7173 will power-up

in sleep mode to facilitate low power consumption before all

registers have been initialized. If Mode Register 6, Bit 0 (MR60) is

then set to (“1”) sleep mode control passes to Mode Register 2,

Bit 7 (i.e., control via I²C).

SCH PHASE MODE

The SCH phase is configured in default mode to reset every

four (NTSC) or eight (PAL) fields to avoid an accumulation of

SCH phase error over time. In an ideal system, zero SCH phase

error would be maintained forever, but in reality, this is impos-

sible to achieve due to clock frequency variations. This effect is

reduced by the use of a 32-bit DDS, which generates this SCH.

RESET SEQUENCE

Resetting the SCH phase every four or eight fields avoids the

accumulation of SCH phase error, and results in very minor

SCH phase jumps at the start of the four or eight field sequence.

When RESET becomes active, the ADV7172/ADV7173 reverts

to the default output configuration. DACs A, B, C are off and

DACs D, E, F are powered on and output composite, luma and

chroma signals respectively. Mode Register 2, Bit 6 (MR26),

resets to “0.” The ADV7172/ADV7173 internal timing is under

the control of the logic level on the NTSC_PAL pin.

Resetting the SCH phase should not be done if the video source

does not have stable timing or the ADV7172/ADV7173 is con-

figured in RTC mode (MR41 = “1” and MR42 = “1”). Under

these conditions (unstable video) the subcarrier phase reset should

be enabled (MR42 = “0” and MR41 = “1”) but no reset applied.

In this configuration the SCH phase will never be reset, which

that the output video will now track the unstable input video.

When RESET is released Y, Cr, Cb values corresponding to a

black screen are input to the ADV7172/ADV7173. Output

timing signals are still suppressed at this stage.

When the user requires valid data, MR26 is set to “1” to allow

the valid pixel data to pass through the encoder. Digital output

timing signals become active and the encoder timing is now

under the control of the timing registers. If, at this stage, the

user wishes to select a video standard different from that on the

NTSC_PAL pin, Mode Register 2, Bit 5 (MR25) is set (“1”)

and the video standard required is selected by programming

Mode Register 0. Figure 36 illustrates the reset sequence timing.

The subcarrier phase reset when applied will reset the SCH

phase to Field 0 at the start of the next field (e.g., subcarrier

phase reset applied in Field 5 (PAL) on the start of the next

field SCH phase will be reset to Field 0).

RESET

COMPOSITE/Y

CHROMA

XXXXXXX

0

BLACK VALUE WITH SYNC

BLACK VALUE

VALID VIDEO

XXXXXXX

512

MR26

PIXEL DATA VALID

1

0

TIMING ACTIVE

DIGITAL TIMING

XXXXXXX

DIGITAL TIMING SIGNALS SUPPRESSED

Figure 36. RESET Sequence Timing Diagram

REV. B

–23–

ADV7172/ADV7173

EXAMPLE: NTSC

525

1

2

3

4

5

6

7

8

9

10

11-19

OUTPUT

VIDEO

CSO

HSO

VSO

Figure 37. CSO, HSO, VSO Timing Diagram

CSO, HSO, AND VSO OUTPUTS

width on the I²C lines, which means that impulses of less

than 50 ns will not pass into the I²C internal controller. This

mode is recommended for noisy systems.

The ADV7172/ADV7173 supports three timing signals, CSO

(composite sync signal), HSO (horizontal sync signal) and VSO

(vertical sync signal). These output TTL signals are aligned with

the analog video outputs. HSO and CSO are shared on Pin 10.

Mode Register 7, Bit MR75 can be used to configure this out-

put pin. See Figure 37 for an example of these waveforms.

1

0

1

0

1

A1

X

ADDRESS

CONTROL

SET UP BY

ALSB

CLAMP OUTPUT

The ADV7172/ADV7173 has a programmable clamp TTL

output signal. The clamp signal is programmable to the front

and back porch. Mode Register 5, Bit MR57 can be used to

control the porch position. Also the position of the clamp signal

can be varied by 1–3 clock cycles in a positive and negative

direction from the default position. Mode Register 5, Bits MR56,

MR55, and MR54 control this position.

READ/WRITE

CONTROL

0

1

WRITE

READ

Figure 39. ADV7172 Slave Address

0

1

0

1

A1

X

0

ADDRESS

CONTROL

0H

SET UP BY

ALSB

READ/WRITE

CONTROL

0

1

WRITE

READ

MR57 = 1

MR57 = 0

Figure 40. ADV7173 Slave Address

To control the various devices on the bus the following protocol

must be followed. First the master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDATA while SCLOCK remains high. This indicates that

an address/data stream will follow. All peripherals respond to

the Start condition and shift the next eight bits (7-bit address +

R/W bit). The bits are transferred from MSB down to LSB. The

peripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDATA and SCLOCK

lines waiting for the Start condition and the correct transmitted

address. The R/W bit determines the direction of the data. A

Logic “0” on the LSB of the first byte means that the master

will write information to the peripheral. A Logic “1” on the LSB

of the first byte means that the master will read information

from the peripheral.

Figure 38. Clamp Output Timing

MPU PORT DESCRIPTION

The ADV7172 and ADV7173 support a 2-wire serial (I²C-

Compatible) microprocessor bus driving multiple peripherals.

Two inputs serial data (SDATA) and serial clock (SCLOCK)

carry information between any device connected to the bus.

Each slave device is recognized by a unique address. The

ADV7172 and ADV7173 each have four possible slave addresses

for both read and write operations. These are unique addresses

for each device and are illustrated in Figure 39 and Figure 40.

The LSB sets either a read or write operation. Logic Level

“1” corresponds to a read operation while Logic Level “0”

corresponds to a write operation. A1 is set by setting the ALSB

pin of the ADV7172/ADV7173 to Logic Level “0” or Logic

Level “1.” When ALSB is set to “0,” there is greater bandwidth

on the I²C lines, which allows high-speed data transfers on this

bus. When ALSB is set to “1,” there is reduced input band-

–24–

REV. B

ADV7172/ADV7173

The ADV7172/ADV7173 acts as a standard slave device on the

bus. The data on the SDATA pin is eight bits long, supporting

the 7-bit addresses plus the R/W bit. It interprets the first byte

as the device address and the second byte as the starting sub-

address. The subaddresses auto increment allows data to be

written to or read from the starting subaddress. A data transfer

is always terminated by a stop condition. The user can also

access any unique subaddress register on a one-by-one basis

without having to update all the registers. There is one excep-

tion. The subcarrier frequency registers should be updated in

sequence, starting with Subcarrier Frequency Register 0. The

auto increment function should then be used to increment and

access Subcarrier Frequency Registers 1, 2 and 3. The subcarrier

frequency registers should not be accessed independently.

Figure 41 illustrates an example of data transfer for a read

sequence and the Start and Stop conditions.

SDATA

S

1-7

8

9

1-7

SUBADDRESS ACK

8

9

1-7

DATA

8

9

P

SCLOCK

R/W

ACK

START ADDR

ACK

STOP

Figure 41. Bus Data Transfer

Figure 42 shows bus write and read sequences.

REGISTER ACCESSES

The MPU can write to or read from all of the registers of the

ADV7172/ADV7173 except the Subaddress Register, which is a

write-only register. The Subaddress Register determines which

register the next read or write operation accesses. All communi-

cations with the part through the bus start with an access to the

Subaddress Register. A read/write operation is then performed

from/to the target address, which then increments to the next

address until a Stop command on the bus is performed.

Stop and Start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, then these cause an

immediate jump to the idle condition. During a given SCLOCK

high period, the user should issue only one start condition, one

stop condition or a single stop condition followed by a single start

condition. If an invalid subaddress is issued by the user, the

ADV7172/ADV7173 will not issue an acknowledge and will

return to the idle condition. If, in autoincrement mode, the user

exceeds the highest subaddress, the following action will be taken:

REGISTER PROGRAMMING

The following section describes each register, including subaddress

register, mode registers, subcarrier frequency registers, subcar-

rier phase register, timing registers, closed captioning extended

data registers, closed captioning data registers, NTSC pedestal

Control/PAL teletext control registers, CGMS/WSS registers,

contrast register, U- or V-scale registers, hue adjust register,

brightness control register and sharpness control register in

terms of its configuration. All registers can be read from as well

as written to.

1. In Read Mode the highest subaddress register contents

will continue to be output until the master device issues

a no-acknowledge. This indicates the end of a read. A

no-acknowledge condition is where the SDATA line is not

pulled low on the ninth pulse.

2. In Write Mode, the data for the invalid byte will not be loaded

into any subaddress register, a no-acknowledge will be issued

by the ADV7172/ADV7173 and the part will return to the

idle condition.

WRITE

S

SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0

DATA

A(S)

DATA

A(M)

A(S)

P

SEQUENCE

LSB = 1

READ

SEQUENCE

A(S)

S

SLAVE ADDR A(S)

DATA

SLAVE ADDR A(S) SUB ADDR

DATA

P

A(M)

A(S) = ACKNOWLEDGE BY SLAVE

A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

S = START BIT

P = STOP BIT

Figure 42. Write and Read Sequences

REV. B

–25–

ADV7172/ADV7173

Subaddress Register (SR7–SR0)

Figure 43 shows the various operations under the control of the

subaddress register. “0” should always be written to SR7.

The communications register is an 8-bit write-only register. After

the part has been accessed over the bus and a read/write opera-

tion is selected, the subaddress is set up. The subaddress register

determines to/from which register the operation takes place.

Register Select (SR6–SR0)

These bits are set up to point to the required starting address.

SR7

SR6

SR5

SR3

SR2

SR1

SR0

SR4

SR7

ZERO SHOULD

BE WRITTEN

HERE

ADV7172/73 SUBADDRESS REGISTER

Address

00h

SR6 SR5 SR4 SR3 SR2 SR1

SR0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

.

0

.

0

1

.

0

1

0

.

0

1

0

1

0

.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

.

MODE REGISTER 0

MODE REGISTER 1

MODE REGISTER 2

MODE REGISTER 3

MODE REGISTER 4

MODE REGISTER 5

MODE REGISTER 6

MODE REGISTER 7

RESERVED

0

1

0

1

0

1

0

1

0

1

.

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

...

RESERVED

TIMING REGISTER 0

TIMING REGISTER 1

SUB CARRIER FREQUENCY REGISTER 0

SUB CARRIER FREQUENCY REGISTER 1

SUB CARRIER FREQUENCY REGISTER 2

SUB CARRIER FREQUENCY REGISTER 3

SUB CARRIER PHASE REGISTER

CLOSED CAPTIONING EXTENDED DATA BYTE 0

CLOSED CAPTIONING EXTENDED DATA BYTE 1

CLOSED CAPTIONING DATA BYTE 0

CLOSED CAPTIONING DATA BYTE 1

NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0

NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1

NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2

NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3

CGMS/WSS 0

CGMS/WSS 1

CGMS/WSS 2

TELETEXT REQUEST CONTROL REGISTER

CONTRAST CONTROL REGISTER

U SCALE REGISTER

V SCALE REGISTER

HUE ADJUST REGISTER

BRIGHTNESS CONTROL REGISTER

SHARPNESS CONTROL REGISTER

RESERVED

....

.

....

.

...

.

....

.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MACROVISION REGISTER [ADV7172 ONLY]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

Figure 43. Subaddress Register

–26–

REV. B

ADV7172/ADV7173

MODE REGISTER 0 MR0 (MR07–MR00)

(Address (SR4–SR0) = 00H)

MODE REGISTER 1 MR1 (MR17–MR10)

(Address (SR4–SR0) = 01H)

Figure 44 shows the various operations under the control of

Mode Register 0.

Figure 45 shows the various operations under the control of

Mode Register 1.

MR0 BIT DESCRIPTION

MR1 BIT DESCRIPTION

Output Video Standard Selection (MR01–MR00)

These bits are used to set up the encoder mode. The ADV7172/

ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I),

PAL M or PAL N standard video.

DAC Control (MR15–MR10)

MR15–MR10 bits can be used to power down the DACs. This

can be used to reduce the power consumption of the ADV7172/

ADV7173 if any of the DACs are not required in the application.

Luma Filter Select (MR02–MR04)

Low Power Mode Control (MR16)

These bits specify which luma filter is to be selected. The

filter selection is made independent of whether PAL or

NTSC is selected.

This bit enables the lower power mode of the ADV7172/

ADV7173. This will reduce by approximately 50% the average

supply current consumed by each large DAC which is powered

on. For each DAC in low power mode, the relationship between

R_SET1/V_REFand the output current is unchanged by this (see

Appendix 8). This bit is only relevant to the larger DACs,

DACs A, B, and C. DACs D, E, and F are not affected by this

low power mode.

Chroma Filter Select (MR05–MR07)

These bits select the chroma filter. A low-pass filter can be

selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz,

1.3 MHz, or 2 MHz), along with a choice of CIF or QCIF filters.

Reserved (MR17)

A Logic “0” must be written to this bit.

MR07

MR06

MR05

MR04

MR03

MR02

MR01

MR00

CHROMA FILTER SELECT

MR06 MR05

OUTPUT VIDEO

STANDARD SELECTION

MR07

MR01

MR00

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.3MHz LOW-PASS FILTER

0

1

0

1

0

1

NTSC

PAL (B, D, G, H, I)

PAL (M)

0.65MHz LOW-PASS FILTER

1.0MHz LOW-PASS FILTER

2.0MHz LOW-PASS FILTER

RESERVED

CIF

QCIF

PAL (N)

RESERVED

LUMA FILTER SELECT

MR04 MR03 MR02

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOW-PASS FILTER (NTSC)

LOW-PASS FILTER (PAL)

NOTCH FILTER (NTSC)

NOTCH FILTER (PAL)

EXTENDED MODE

CIF

QCIF

RESERVED

Figure 44. Mode Register 0 (MR0)

MR17

MR16

MR15

MR14

MR13

MR12

MR11

MR10

DAC B

DAC C CONTROL

DAC D

DAC C CONTROL

LOW POWER MODE

CONTROL

DAC F

DAC C CONTROL

MR12

MR10

MR16

MR14

0

1

DISABLE

ENABLE

0

1

POWER-DOWN

NORMAL

0

1

POWER-DOWN

NORMAL

0

1

POWER-DOWN

NORMAL

DAC A

DAC C CONTROL

DAC C

DAC C CONTROL

DAC E

DAC C CONTROL

MR17

MR11

MR15

MR13

ZERO SHOULD BE

WRITTEN TO

THIS BIT

0

1

POWER-DOWN

NORMAL

0

1

POWER-DOWN

NORMAL

0

1

POWER-DOWN

NORMAL

Figure 45. Mode Register 1 (MR1)

REV. B

–27–

ADV7172/ADV7173

MODE REGISTER 2 MR2 (MR27–MR20)

(Address (SR4–SR0) = 02H)

Mode Register 2 is an 8-bit-wide register.

Square Pixel Control (MR24)

This bit is used to set up square pixel mode. This is available in

slave mode only. For NTSC, a 24.54 MHz clock must be

supplied. For PAL, a 29.5 MHz clock must be supplied.

Standard I²C Control (MR25)

Figure 46 shows the various operations under the control of

Mode Register 2.

This bit controls the video standard used by the ADV7172/

ADV7173. When this bit is set to “1,” the video standard bits

programmed in Mode Register 0, Bits 0–1, indicate the video

standard. When this bit is set to “0,” the ADV7172/ADV7173

is forced into the standard selected by the NTSC_PAL pin.

MR2 BIT DESCRIPTION

RGB/YUV Control (MR20)

This bit enables the output from the DACs to be set to YUV or

RGB output video standard.

Large DACs Control (MR21)

Pixel Data Valid Control (MR26)

This bit controls the output from DACs A, B, and C. When this

bit is set to “1,” composite, luma, and chroma signals are output

from DACs A, B, and C (respectively). When this bit is set to

“0,” RGB or YUV may be output from these DACs.

After reset, this bit has the value “0” and the pixel data input to

the encoder is blanked such that a black screen is output from

the DACs. The ADV7172/ADV7173 will be set to master mode

timing. When this bit is set to “1” by the user (via the I²C),

pixel data passes to the pins and the encoder reverts to the

timing mode defined by Timing Mode Register 0.

SCART Enable Control (MR22)

This bit is used to switch the DAC outputs from SCART to a

EuroSCART configuration. A complete table of all DAC output

configurations is shown in Table II.

Sleep Mode Control (MR27)

When this bit is set (“1”), sleep mode is enabled. With this

mode enabled the ADV7172/ADV7173 power consumption is

reduced to less than 20 µA. The I²C registers can be written to

and read from when the ADV7172/ADV7173 is in sleep mode.

If “0” is written to MR27 when the device is in sleep mode, the

ADV7172/ADV7173 will come out of sleep mode and resume

normal operation. Also, if the reset signal is applied during sleep

mode, the ADV7172/ADV7173 will come out of sleep mode

and resume normal operation. This mode will only operate

when MR60 is set to a Logic “1”; otherwise sleep mode is con-

trolled by the PAL_NTSC and SCRESET/RTC pin.

Pedestal Control (MR23)

This bit specifies whether a pedestal is to be generated on the

NTSC composite video signal. This bit is invalid in the PAL mode.

MR21

MR27

MR26

MR25

MR24

MR23

MR22

MR20

PIXEL DATA VALID

CONTROL

SQUARE PIXEL

CONTROL

SCART ENABLE

CONTROL

RGB/YUV

CONTROL

MR22

MR20

MR26

MR24

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

RGB OUTPUT

YUV OUTPUT

0

1

DISABLE

ENABLE

2

PEDESTAL

CONTROL

LARGE DACs

CONTROL

SLEEP MODE

CONTROL

STANDARD I C

CONTROL

MR27

MR23

MR21

MR25

0

1

RGB/YUV/COMP

COMP/LUMA/CHROMA

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

PEDESTAL ON

PEDESTAL OFF

Figure 46. Mode Register 2 (MR2)

Table II. DAC Output Configuration Matrix

MR22

MR21

MR20

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

0

1

0

1

0

1

0

1

0

1

0

1

0

1

G

Y

B

U

LUMA

B

U

LUMA

R

V

CVBS

LUMA

B

CHROMA

R

V

CHROMA

R

V

CVBS

CHROMA

R

G

Y

G

Y

G

Y

U

LUMA

B

V

CHROMA

U

–28–

REV. B

ADV7172/ADV7173

MODE REGISTER 3 MR3 (MR37–MR30)

TTXRQ Bit Mode Control (MR34)

(Address (SR4–SR0) = 03H)

Mode Register 3 is an 8-bit-wide register. Figure 47 shows the

various operations under the control of Mode Register 3.

This bit enables switching of the teletext request signal from a

continuous high signal (MR34 = “0”) to a bit wise request

signal (MR34 = “1”).

Closed Captioning Field Selection (MR36–MR35)

These bits control the fields that closed captioning data is dis-

played on. Closed captioning information can be displayed on

an odd field, even field, or both fields.

MR3 BIT DESCRIPTION

Revision Code (MR31–MR30)

This bit is read-only and indicates the revision of the device.

VBI_Open (MR32)

Active Video Filter (MR37)

This bit determines whether or not data in the vertical blank-

ing interval (VBI) is output to the analog outputs or blanked.

VBI_Open is available in all timing modes. Also, if both BLANK

input (TR03) and VBI_Open are enabled, TR03 takes priority.

This bit controls the filter mode applied outside the active video

portion of the line. This filter ensures that the sync rise and

fall times are always on spec regardless of which luma filter

is selected.

Teletext Enable (MR33)

This bit must be set to “1” to enable teletext data insertion on

the TTX pin.

MR36

MR35

MR34

MR33

MR32

MR31

MR30

MR37

VBI OPEN

ACTIVE VIDEO

FILTER

TTXRQ BIT

MODE CONTROL

MR31

MR30

MR32

MR37

MR34

0

1

DISABLE

ENABLE

RESERVED FOR

REVISION CODE

0

1

ENABLE

DISABLE

0

1

DISABLE

ENABLE

CLOSED CAPTIONING

FIELD SELECTION

TELETEXT

ENABLE

MR36 MR35

MR33

0

1

0

1

0

1

NO DATA OUT

0

1

DISABLE

ENABLE

ODD FIELD ONLY

EVEN FIELD ONLY

DATA OUT

(BOTH FIELDS)

Figure 47. Mode Register 3 (MR3)

REV. B

–29–

ADV7172/ADV7173

MODE REGISTER 4 MR4 (MR47–MR40)

(Address (SR4–SR0) = 04H)

Mode Register 4 is a 8-bit wide register. Figure 48 shows the

various operations under the control of Mode Register 4.

Active Video Line Duration (MR43)

This bit switches between two active video line durations. A

“0” selects CCIR REC 601 (720 pixels PAL/NTSC) and a “1”

selects ITU-R.BT 470 “analog” standard for active video dura-

tion (710 pixels NTSC, 702 pixels PAL).

MR4 BIT DESCRIPTION

VSYNC_3H (MR40)

Chrominance Control (MR44)

This bit enables the color information to be switched on and off

the video output.

When this bit is enabled (“1”) in slave mode, it is possible to

drive the VSYNC active low input for 2.5 lines in PAL mode

and 3 lines in NTSC mode. When this bit is enabled in master

mode, the ADV7172/ADV7173 outputs an active low VSYNC

signal for 3 lines in NTSC mode and 2.5 lines in PAL mode.

Burst Control (MR45)

This bit enables the color burst information to be switched on

and off the video output.

Color Bar Control (MR46)

Genlock Selection (MR42–MR41)

This bit can be used to generate and output an internal color

bar test pattern. The color bar configuration is 100/7.5/75/7.5

for NTSC and 100/0/75/0 for PAL. It is important to note that

when color bars are enabled, the ADV7172/ADV7173 is config-

ured in a master timing mode. The output pins VSYNC/FIELD,

HSYNC and BLANK are three-state during color bar mode.

These bits control the genlock feature of the ADV7172/ADV7173.

Setting MR41 to Logic “0” disables the SCRESET/RTC pin

and allows the ADV7172/ADV7173 to operate in normal mode.

By setting MR41 to “1,” one of two operations may be enabled:

1. If MR42 is set to “0,” the SCRESET/RTC pin is configured

as a subcarrier reset input and the subcarrier phase will reset

to Field 0 whenever a low-to-high field transition is detected

on the SCRESET/RTC pin.

Interlaced Mode Control (MR47)

This bit is used to set up the output to interlaced or noninter-

laced mode.

2. If MR42 is set to “1,” the SCRESET/RTC pin is configured

as a real-time control input and the ADV7172/ADV7173 can

be used to lock to an external video source.

MR47

MR46

MR45

MR44

MR43

MR42

MR41

MR40

CHROMINANCE

CONTROL

GENLOCK SELECTION

MR42 MR41

COLOR BAR

CONTROL

MR46

MR44

x

0

1

DISABLE GENLOCK

ENABLE SUBCARRIER

RESET PIN

0

1

ENABLE COLOR

DISABLE COLOR

0

1

DISABLE

ENABLE

1

ENABLE RTC PIN

BURST

ACTIVE VIDEO

LINE DURATION

VSYNC 3H

INTERLACED

CONTROL

MODE CONTROL

MR40

MR43

MR45

MR47

0

1

DISABLE

ENABLE

0

1

720 PIXELS

710/702 PIXELS

0

1

INTERLACED

NONINTERLACED

0

1

ENABLE BURST

DISABLE BURST

Figure 48. Mode Register 4 (MR4)

–30–

REV. B

ADV7172/ADV7173

MODE REGISTER 5 MR5 (MR57–MR50)

RGB Sync (MR53)

(Address (SR4-SR0) = 05H)

Mode Register 5 is an 8-bit-wide register. Figure 49 shows the

various operations under the control of Mode Register 5.

This bit is used to set up the RGB outputs with the sync infor-

mation encoded on all RGB outputs.

Clamp Delay (MR55–MR54)

These bits control the delay or advance of the CLAMP signal in

the front or back porch of the ADV7172/ADV7173. It is possible

to delay or advance the pulse by 0, 1, 2 or 3 clock cycles.

MR5 BIT DESCRIPTION

Y-Level Control (MR50)

This bit controls the Y output level on the ADV7172/ADV7173.

If this bit is set (“0”), the encoder outputs SMPTE levels when

configured in PAL mode and Betacam levels when configured

in NTSC mode. If this bit is set (“1”), the encoder outputs

Betacam levels when configured in PAL mode and SMPTE

levels when configured in NTSC mode.

Clamp Delay Direction (MR56)

This bit controls a positive or negative delay in the CLAMP

signal. If this bit is set (“1”), the delay is negative. If it is not set

(“0”), the delay is positive.

Clamp Position (MR57)

This bit controls the position of the CLAMP signal. If this bit is

set (“1”), the CLAMP signal is located in the back porch posi-

tion. If this bit is set to (“0”), the CLAMP signal is located in

the front porch position.

UV-Levels Control (MR52–MR51)

These bits control the U and V output levels on the ADV7172/

ADV7173. It is possible to have UV levels with a peak-peak

amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV

(MR52 + MR51 = “10”) in NTSC and PAL. It is also possible

to have default values of 934 mV for NTSC and 700 mV for

PAL (MR52 + MR51 = “00”).

MR56

MR55

MR54

MR53

MR52

MR50

MR57

MR51

CLAMP POSITION

MR57

CLAMP DELAY

MR55 MR54

UV-LEVELS CONTROL

MR52 MR51

0

1

0

1

0

1

NO DELAY

1 ꢀ PCLK

2 ꢀ PCLK

3 ꢀ PCLK

0

1

FRONT PORCH

BACK PORCH

0

1

0

1

0

1

DEFAULT LEVELS

700mV

1000mV

RESERVED

RGB

SYNC

Y-LEVEL

CONTROL

CLAMP DELAY

DIRECTION

MR50

MR56

MR53

0

1

DISABLE

ENABLE

0

1

POSITIVE

NEGATIVE

0

1

DISABLE

ENABLE

Figure 49. Mode Register 5 (MR5)

REV. B

–31–

ADV7172/ADV7173

MODE REGISTER 6 MR6 (MR67–MR60)

(Address (SR4–SR0) = 06H)

Mode Register 6 is an 8-bit-wide register. Figure 50 shows the

various operations under the control of Mode Register 6.

DAC Termination Control (MR64)

This bit controls the load termination resistance detected by the

autodetect functionality. If this bit is set (“0”), the autodetect

feature is used to determine if a 75 Ω termination is present. If

this bit is set to (“1”), the autodetect feature is used to indicate

if a 150 Ω termination is present.

MR6 BIT DESCRIPTION

Power-Up Sleep Mode Control (MR60)

Reserved (MR65)

A Logic “0” must be written to this bit.

After reset this bit is set to “0,” if both SCRESET/RTC and

NTSC_PAL pins are tied high, the part will power-up in sleep

mode (to facilitate low power consumption before the I²C is

initialized). When this bit is set to “1” (via the I²C), sleep mode

control passes to Mode Register 2, Bit 7.

Luma DAC Status Bit (MR66)

This bit is a read-only status bit for the autodetect feature of

the ADV7172/ADV7173 and may be read to check whether

or not the composite DAC is terminated. If this bit is set (“1”),

there is no termination; if this bit is set (“0”), the composite DAC

is terminated.

Reserved (MR61)

A Logic “0” must be written to this bit.

Luma Autodetect Control (MR62)

Composite DAC Status Bit (MR67)

This bit controls which mode of autodetect operation is being

used on the luma DAC (DAC B) on the ADV7172/ADV7173.

If this bit is set (“0”), Mode 0 is on; if this bit is set (“1”), then

Mode 1 is being used.

This bit is a read only status bit for the autodetect feature of the

ADV7172/ADV7173 and may be read to check whether or not

the luma DAC is terminated. If this bit is set (“1”), there is no

termination. If this bit is set (“0”), the luma DAC is terminated.

Composite Autodetect Control (MR63)

This bit controls which mode of autodetect operation is being

used on the composite DAC (DAC A) on the ADV7172/

ADV7173. If this bit is set (“0”), Mode 0 is on; if this bit is set

(“1”), then Mode 1 is being used.

MR66

MR65

MR64

MR63

MR62

MR60

MR67

MR61

COMPOSITE

DAC STATUS BIT

COMP AUTODETECT

CONTROL

ZERO SHOULD

BE WRITTEN TO

THIS BIT

ZERO SHOULD

BE WRITTEN TO

THIS BIT

MR63

MR67

0

1

NOT TERMINATED

TERMINATED

0

1

MODE 0

MODE 1

LUMA AUTODETECT

CONTROL

LUMA DAC

STATUS BIT

DAC TERMINATION

CONTROL

POWER-UP SLEEP

MODE CONTROL

MR66

MR64

MR62

MR60

0

1

1 ꢀ MODE

2 ꢀ MODE

0

1

NOT TERMINATED

TERMINATED

0

1

MODE 0

MODE 1

0

1

ENABLE

DISABLE

Figure 50. Mode Register 6 (MR6)

–32–

REV. B

ADV7172/ADV7173

MODE REGISTER 7 MR7 (MR77–MR70)

(Address (SR4–SR0) = 07H)

Mode Register 7 is an 8-bit-wide register. Figure 51 shows the

various operations under the control of Mode Register 7.

Brightness Enable Control (MR73)

This bit is used to enable brightness control on the ADV7172/

ADV7173 by enabling the programmable “setup level” or ped-

estal described in the Brightness Control Register to be added to

the scaled Y data. When this bit is set (“1”), brightness control

is enabled. When this bit is set (“0”), brightness control is disabled.

MR7 BIT DESCRIPTION

Color Control Enable (MR70)

This bit is used to enable control of contrast and saturation of

color. If this bit is set (“1”), color controls are enabled; if this

bit is set (“0”), the color control features are disabled.

Sharpness Response Enable (MR74)

This bit is used to enable the sharpness of the luminance signal

on the ADV7172/ADV7173 (MR04–MR02 = 100). The various

responses of the filter are determined by the Sharpness Response

Register. When this bit is set (“1”) the luma response is altered

by the amount described in the Sharpness Response Register.

When this bit is set (“0”), the sharpness control is disabled (see

Figures 19, 20, and 21 for luma signal responses).

Luma Saturation Control (MR71)

When this bit is set (“1”), the luma signal will be clipped if it

reaches a limit that corresponds to an input luma value of

255 after scaling by the contrast control. This prevents the

chrominance component of the composite video signal being

clipped if the amplitude of the luma is too high. When this bit is

set (“0”), this control is disabled.

CSO_HSO Output Control (MR75)

This bit is used to determine whether HSO or CSO TTL out-

put signal is output at the CSO_HSO pin. If this bit is set (“1”),

then the CSO TTL signal is output. If this bit is set (“0”), then

the HSO TTL signal is output.

Hue Adjust Enable (MR72)

This bit is used to enable hue adjustment on the composite and

chroma output signals of the ADV7172/ADV7173. When this

bit is set (“1”), the hue of the color is adjusted by the phase

offset described in the Hue Control Register. When this bit is

set (“0”) hue adjustment is disabled.

Reserved (MR77–MR76)

A Logic “0” must be written to these bits.

MR77

MR76

MR75

MR74

MR73

MR72

MR71

MR70

CSO_HSO

OUTPUT CONTROL

BRIGHTNESS

ENABLE CONTROL

LUMA SATURATION

CONTROL

MR75

MR71

MR73

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

HSO OUT

CSO OUT

SHARPNESS

COLOR CONTROL

ENABLE

HUE ADJUST

ENABLE

ZERO SHOULD

BE WRITTEN TO

THESE BITS

RESPONSE ENABLE

MR72

MR70

MR74

MR77 MR76

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

Figure 51. Mode Register 7 (MR7)

REV. B

–33–

ADV7172/ADV7173

Luma Delay (TR05–TR04)

These bits control the addition of a delay to the luminance with

respect to the chrominance. Each bit represents a delay of 74 ns.

TIMING REGISTER 0 (TR07–TR00)

(Address (SR4–SR0) = 0AH)

Figure 52 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to.

Min Luma Value (TR06)

The bit is used to control the minimum luma value output by

the ADV7172/ADV7173. When this bit is set to (“1”), the luma

is limited to 7.5 IRE below the blank level. When this bit is set

to (“0”), the luma value can be as low as the sync bottom level.

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

This bit controls whether the ADV7172/ADV7173 is in master

or slave mode.

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the inter-

nal timing counters. This bit should be toggled after power-up,

reset or changed to a new timing mode.

Timing Mode Selection (TR02–TR01)

These bits control the timing mode of the ADV7172/ADV7173.

These modes are described in more detail in the Timing and

Control section of the data sheet.

BLANK Input Control (TR03)

This bit controls whether the BLANK input is used when the

part is in slave mode or whether BLANK is internally generated.

TR01

TR07

TR06

TR05

TR04

TR03

TR02

TR00

MASTER/SLAVE

CONTROL

BLANK INPUT

CONTROL

TIMING

REGISTER RESET

TR03

TR00

TR07

0

1

SLAVE TIMING

MASTER TIMING

0

1

ENABLE

DISABLE

MIN LUMA VALUE

TR06

LUMA DELAY

TIMING MODE

SELECTION

TR05 TR04

TR02 TR01

0

LUMA MIN =

SYNC BOTTOM

LUMA MIN =

0

1

0

1

0

1

0ns DELAY

0

1

0

1

0

1

MODE 0

74ns DELAY

148ns DELAY

222ns DELAY

MODE 1

MODE 2

MODE 3

1

BLANK –7.5 IRE

Figure 52. Timing Register 0

–34–

REV. B

ADV7172/ADV7173

TIMING REGISTER 1 (TR17–TR10)

(Address (SR4–SR0) = 0BH)

Timing Register 1 is an 8-bit-wide register.

HSYNC to FIELD Rising Edge Delay (TR15–TR14)

When the ADV7172/ADV7173 is in Timing Mode 1, these bits

adjust the position of the HSYNC output relative to the FIELD

output rising edge.

Figure 53 shows the various operations under the control of

Timing Register 1. This register can be read from as well writ-

ten to. This register can be used to adjust the width and position

of the master mode timing signals.

VSYNC Width (TR15–TR14)

When the ADV7172/ADV7173 is configured in Timing Mode

2, these bits adjust the VSYNC pulsewidth.

HSYNC to Pixel Data Adjust (TR17–TR16)

TR1 BIT DESCRIPTION

HSYNC Width (TR11–TR10)

These bits adjust the HSYNC pulsewidth.

This enables the HSYNC to be adjusted with respect to the pixel

data. This allows the Cr and Cb components to be swapped. This

adjustment is available in both master and slave timing modes.

HSYNC to FIELD/VSYNC Delay (TR13–TR12)

These bits adjust the position of the HSYNC output relative to

the FIELD/VSYNC output.

TR11

TR17

TR16

TR15

TR14

TR13

TR12

TR10

HSYNC WIDTH

HSYNC TO

HSYNC TO FIELD

RISING EDGE DELAY

(MODE 1 ONLY)

HSYNC TO PIXEL

FIELD/VSYNC DELAY

DATA ADJUST

T

TR11 TR10

A

T

TR13 TR12

TR17 TR16

B

0

1

0

1

0

1

1 ꢀ T

4 ꢀ T

16 ꢀ T

PCLK

T

TR15 TR14

C

0

1

0

1

0

1

0 ꢀ T

4 ꢀ T

8 ꢀ T

0

1

0

1

0

1

0 ꢀ T

1 ꢀ T

2 ꢀ T

3 ꢀ T

PCLK

x

0

1

T

B

PCLK

+ 32ꢃs

128 ꢀ T

PCLK

16 ꢀ T

PCLK

VSYNC WIDTH

(MODE 2 ONLY)

TR15 TR14

0

1

0

1

0

1

1 ꢀ T

4 ꢀ T

16 ꢀ T

PCLK

128 ꢀ T

PCLK

TIMING MODE 1 (MASTER/PAL)

LINE 1

LINE 313

LINE 314

T_A

T_B

HSYNC

T_C

FIELD/VSYNC

Figure 53. Timing Register 1

REV. B

–35–

ADV7172/ADV7173

SUBCARRIER FREQUENCY REGISTERS 3–0

(FSC3–FSC0)

(Address (SR4–SR0) = 0CH–0FH)

CLOSED CAPTIONING ODD FIELD

DATA REGISTER 1–0 (CCD15–CCD00)

(Subaddress (SR4–SR0) = 13–14H)

These 8-bit-wide registers are used to set up the subcarrier

frequency. The value of these registers is calculated by using the

These 8-bit-wide registers are used to set up the closed captioning

data bytes on odd fields. Figure 56 shows how the high and low

bytes are set up in the registers.

following equation:

2³²–1

f_CLK

Subcarrier Frequency Register =

× f_SCF

BYTE 1

BYTE 0

CCD15

CCD13 CCD12 CCD11 CCD10 CCD9 CCD8

CCD14

Example: NTSC Mode,

f

_CLK= 27 MHz,

_SCF= 3.5795454 MHz

CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0

2³²–1

27×10⁶

Subcarrier FrequencyValue=

×3.579454×10⁶

Figure 56. Closed Captioning Data Register

= 21F07C16 HEX

NTSC PEDESTAL/PAL TELETEXT CONTROL

REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)

(Subaddress (SR4–SR0) = 15–18H)

Figure 54 shows how the frequency is set up by the four

registers.

These 8-bit-wide registers are used to enable the NTSC pedes-

tal/PAL Teletext on a line-by-line basis in the vertical blanking

interval for both odd and even fields. Figures 57 and 58 show

the four control registers. A Logic “1” in any of the bits of

these registers has the effect of turning the Pedestal OFF on

the equivalent line when used in NTSC. A Logic “1” in any of

the bits of these registers has the effect of turning Teletext ON

on the equivalent line when used in PAL.

SUBCARRIER PHASE REGISTER (FP7–FP0)

(Address (SR4–SR0) = 10H)

This 8-bit-wide register is used to set up the subcarrier phase.

Each bit represents 1.41°. For normal operation this register is

set to 00Hex.

SUBCARRIER

FREQUENCY

REG 3

FSC30

FSC31

FSC29 FSC28 FSC27 FSC26 FSC25 FSC24

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

SUBCARRIER

FREQUENCY

REG 2

FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16

FIELD 1/3

PCO7

PCO5 PCO4

PCO3

PCO2 PCO1

PCO0

PCO6

SUBCARRIER

FREQUENCY

REG 1

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

FIELD 1/3 PCO15

PCO13 PCO12 PCO11 PCO10 PCO9 PCO8

FSC15

FSC13 FSC12 FSC11 FSC10 FSC9

FSC8

FSC0

FSC14

PCO14

SUBCARRIER

FREQUENCY

REG 0

FSC7 FSC6 FSC5

FSC4

FSC3 FSC2 FSC1

LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10

PCE7 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0

PCE6

FIELD 2/4

Figure 54. Subcarrier Frequency Registers

LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18

PCE15 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8

CLOSED CAPTIONING EVEN FIELD

DATA REGISTER 1–0 (CED15–CED0)

(Address (SR4–SR0) = 11–12H)

PCE14

Figure 57. Pedestal Control Registers

These 8-bit wide registers are used to set up the closed captioning

extended data bytes on even fields. Figure 55 shows how the

high and low bytes are set up in the registers.

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0

FIELD 1/3

BYTE 1

BYTE 0

CED14

CED6

CED15

CED7

CED13 CED12 CED11 CED10 CED9 CED8

CED5 CED4 CED3 CED2 CED1 CED0

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

FIELD 1/3 TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9

TXO8

LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7

TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0

Figure 55. Closed Captioning Extended Data Register

FIELD 2/4

LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15

TXE15 TXE14 TXE13 TXE12 TXE11 TXE10 TXE9

TXE8

Figure 58. Teletext Control Registers

–36–

REV. B

ADV7172/ADV7173

TELETEXT REQUEST CONTROL REGISTER TC07

(TC07–TC00)

C/W BIT DESCRIPTION

CGMS Data (C/W03–C/W00)

(Address (SR4–SR0) = 1CH)

Teletext Control Register is an 8-bit-wide register. See Figure 59.

These four data bits are the final four bits of CGMS data out-

put stream. Note it is CGMS data ONLY in these bit positions

i.e., WSS data does not share this location.

TTXREQ Rising Edge Control (TC07–TC04)

These bits control the position of the rising edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a max of 15

CLOCK cycles.

CGMS CRC Check Control (C/W04)

When this bit is enabled (“1”), the last six bits of the CGMS

data, i.e., the CRC check sequence, are calculated internally by

the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC

values in the register are output to the CGMS data stream.

TTXREQ Falling Edge Control (TC03–TC00)

These bits control the position of the falling edge of TTXREQ.

It can be programmed from zero CLOCK cycles to a max of 15

CLOCK cycles. This controls the active window for Teletext

data. Increasing this value reduces the amount of Teletext Bits

below the default of 360. If Bits TC03–TC00 are 00Hex when

Bits TC07–TC04 are changed, then the falling edge of TTXREQ

will track that of the rising edge (i.e., the time between the fall-

ing and rising edge remains constant).

CGMS Odd Field Control (C/W05)

When this bit is set (“1”), CGMS is enabled for odd fields.

Note that this is only valid in NTSC mode.

CGMS Even Field Control (C/W06)

When this bit is set (“1”), CGMS is enabled for even fields.

Note that this is only valid in NTSC mode.

Wide Screen Signal Control (C/W07)

When this bit is set (“1”), wide screen signalling is enabled.

Note that this is only valid in PAL mode.

CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)

(Address (SR4–SR0) = 19H)

CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60

shows the operations under control of this register.

TC06

TC05

TC04

TC03

TC02

TC01

TC00

TC07

TTXREQ RISING EDGE CONTROL

TC07 TC06 TC05 TC04

TTXREQ FALLING EDGE CONTROL

TC03 TC02 TC01 TC00

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

0

"

1

0

"

1

0

"

1

0

1

"

0

1

0 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

1 PCLK

" PCLK

14 PCLK

15 PCLK

Figure 59. Teletext Request Control Register

C/W07

C/W06

C/W05

C/W04

C/W03

C/W02

C/W01

C/W00

WIDE SCREEN SIGNAL

CONTROL

CGMS ODD FIELD

CONTROL

C/W03–C/W00

CGMS DATA

C/W05

C/W07

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

CGMS EVEN FIELD

CONTROL

CGMS CRC CHECK

CONTROL

C/W06

C/W04

0

1

DISABLE

ENABLE

0

1

DISABLE

ENABLE

Figure 60. CGMS_WSS Register 0

REV. B

–37–

ADV7172/ADV7173

CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10)

(Address (SR4–SR0) = 1AH)

CONTRAST CONTROL REGISTER (CC07–CC00)

(Address (SR4–SR0) = 1DH)

CGMS_WSS Register 1 is an 8-bit-wide register. Figure 61 shows

the operations under control of this register.

The contrast control register is an 8-bit-wide register used to

scale the Y output levels. Figure 63 shows the operations under

control of this register.

C/W1 BIT DESCRIPTION

CGMS/WSS Data (C/W15–C/W10)

CC0 BIT DESCRIPTION

These bit locations are shared by CGMS data and WSS data. In

NTSC mode these bits are CGMS data. In PAL mode these

bits are WSS data.

Reserved (CC07–CC06)

A Logic “0” must be written to these bits.

Y Scalar Value (CC05–CC00)

CGMS Data Only (C/W17–C/W16)

These bits are CGMS data bits only.

These six bits represent the value required to scale the Y pixel

data from 0.75 to 1.25 of its initial level. The value of these six

bits is calculated using the following equation:

CGMS_WSS REGISTER 2 C/W1(C/W27–C/W20)

(Address (SR4-SR0) = 1BH)

CGMS_WSS Register 2 is an 8-bit-wide register. Figure 62

shows the operations under control of this register.

Contrast Control Register = (X –0.785) × 128

where X = Scaling factor for Y

e.g., Scale Y by 0.9

Contrast Control Register = (0.9–0.75) × 128 = 19.2 = 010011

(rounded to the nearest integer)

C/S BIT DESCRIPTION

CGMS/WSS Data (C/W27–C/W20)

These bit locations are shared by CGMS data and WSS data. In

NTSC mode these bits are CGMS data. In PAL mode these

bits are WSS data.

Actual scaling factor = 0.898.

C/W17

C/W16

C/W15

C/W14

C/W13

C/W12

C/W11

C/W10

C/W15–C/W10

CGMS/WSS DATA

C/W17–C/W16

CGMS DATA

Figure 61. CGMS_WSS Register 1

C/W27

C/W26

C/W25

C/W24

C/W23

C/W22

C/W21

C/W20

C/W27–C/W20

CGMS/WSS DATA

Figure 62. CGMS_WSS Register 2

CC07

CC06

CC05

CC04

CC03

CC02

CC01

CC00

CC07–CC06

CC05–CC00

Y SCALAR VALUE

ZERO SHOULD

BE WRITTEN

TO THESE BITS

Figure 63. Contrast Control Register

–38–

REV. B

ADV7172/ADV7173

COLOR CONTROL REGISTERS 2–1 (CC2–CC1)

(Address (SR4–SR0) = 1EH–1FH)

The color control registers are 8-bit-wide registers used to scale

the U and V output levels. Figure 64 shows the operations

under control of these registers.

V Scalar Value (CC25–CC20)

These six bits represent the value required to scale the V pixel

data from 0.75 to 1.25 of its initial level. The value of these six

bits is calculated using the following equation:

Color Control Register 2 = (X – 0.75) × 128

where X = Scaling factor for V

e.g., Scale V by 1.2

CC1 BIT DESCRIPTION

Reserved (CC17–CC16)

A Logic “0” must be written to these bits.

Color Control Register 2 = (1.2 – 0.75) × 128 = 57.6 = 111001

U Scalar Value (CC15–CC10)

(rounded to the nearest integer)

These six bits represent the value required to scale the U level

from 0.75 to 1.25 of its initial level. The value of these six bits is

calculated using the following equation:

HUE CONTROL REGISTER (HCR)

(Address (SR5–SR0) = 20H)

The hue control register is an 8-bit-wide register used to adjust

the hue on the composite and chroma outputs. Figure 65 shows

the operation under control of this register.

Color Control Register 1 = (X – 0.75) × 128

where X = Scaling factor for U

e.g., Scale U by 0.8

Color Control Register 1 = (0.8 – 0.75) × 128 = 6.4 = 000110

HCR BIT DESCRIPTION

Hue Adjust Value (HCR7–HCR0)

(rounded to the nearest integer)

These eight bits represent the value required to vary the hue of

the video data, i.e., the variance in phase of the subcarrier with

respect to the phase of the subcarrier during the color burst.

The ADV7172/ADV7173 provides a range of 22° in incre-

ments of 0.17578125°. For normal operation (zero adjustment)

this register is set to 80 Hex. FFHex and 00Hex represent the

upper and lower limit (respectively) of adjustment attainable.

CC2 BIT DESCRIPTION

Reserved (CC27–CC26)

A Logic “0” must be written to these bits.

Hue Adjust = (0.17568125 × [HCR7 – HCR0 – 128]).

CC17

CC16

CC15

CC14

CC13

CC12

CC11

CC10

CC17–CC16

CC15–CC10

U SCALAR VALUE

ZERO SHOULD

BE WRITTEN

TO THESE BITS

CC27

CC26

CC25

CC24

CC23

CC22

CC21

CC20

CC27–CC26

CC25–CC20

V SCALAR VALUE

ZERO SHOULD

BE WRITTEN

TO THESE BITS

Figure 64. Color Control Registers

HCR7

HCR6

HCR5

HCR4

HCR3

HCR2

HCR1

HCR0

HCR7–HCR0

HUE ADJUST VALUE

Figure 65. Hue Control Register

REV. B

–39–

ADV7172/ADV7173

BRIGHTNESS CONTROL REGISTERS (BCR)

(Address (SR5–SR0) = 21H)

SHARPNESS RESPONSE REGISTER (PR)

(Address (SR5-SR0) = 22H)

The brightness control register is an 8-bit-wide register which

allows brightness control. Figure 66 shows the operation under

control of this register.

The sharpness response register is an 8-bit-wide register. The

four MSBs are set to “0.” The four LSBs are written to in order

to select a desired filter response. Figure 67 shows the operation

under control of this register.

BCR BIT DESCRIPTION

Reserved (BCR7–BCR5)

PR BIT DESCRIPTION

A Logic “0” must be written to these bits.

Reserved (PR7–PR4)

A Logic “0” must be written to these bits.

Brightness Value (BCR4–BCR0)

These five bits represent the value required to vary the “brightness

level” or pedestal added to the luma data. The available range is

from 0 IRE to 7.5 IRE in 18 steps. A value of 18 (10010) corre-

sponds to 7.5 IRE setup level added onto the pixel data. This

brightness control is possible in both PAL and NTSC.

Sharpness Response Value (PR3–PR0)

These four bits are used to select the desired luma filter response.

The option of twelve responses is given supporting a gain boost/

attenuation in the range –4 dB to +4 dB. The value 12 (1100)

written to these four bits corresponds to a boost of +4 dB while

the value 0 (0000) corresponds to –4 dB. For normal opera-

tion these four bits are set to 6 (0110). Refer to Figures 19–21

for filter plots.

BCR7

BCR6

BCR5

BCR4

BCR3

BCR2

BCR1

BCR0

BCR7–BCR5

BCR4–BCR0

ZERO SHOULD

BE WRITTEN

TO THESE BITS

BRIGHTNESS VALUE

Figure 66. Brightness Control Register

PR3

PR2

PR1

PR0

PR7

PR6

PR5

PR4

PR7–PR4

PR3–PR0

ZERO SHOULD

BE WRITTEN

TO THESE BITS

SHARPNESS RESPONSE

VALUE

Figure 67. Sharpness Response Register

–40–

REV. B

ADV7172/ADV7173

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

The ADV7172/ADV7173 is a highly integrated circuit containing

both precision analog and high speed digital circuitry. It has

been designed to minimize interference effects on the integrity

of the analog circuitry by the high speed digital circuitry. It is

imperative that these same design and layout techniques be applied

to the system level design so that high speed, accurate performance

is achieved. The Recommended Analog Circuit Layout shows

the analog interface between the device and monitor.

obtained with 0.1 µF ceramic capacitor decoupling. Each group

of V_AApins on the ADV7172/ADV7173 must have at least one

0.1 µF decoupling capacitor to GND. These capacitors should

be placed as close to the device as possible.

It is important to note that while the ADV7172/ADV7173

contains circuitry to reject power supply noise, this rejection

decreases with frequency. If a high frequency switching power

supply is used, the designer should pay close attention to reduc-

ing power supply noise and consider using a three-terminal voltage

regulator for supplying power to the analog power plane.

The layout should be optimized for lowest noise on the ADV7172/

ADV7173 power and ground lines by shielding the digital inputs

and providing good decoupling. The lead length between groups

of V_AAand GND pins should by minimized to minimize induc-

tive ringing.

Digital Signal Interconnect

The digital inputs to the ADV7172/ADV7173 should be iso-

lated as much as possible from the analog outputs and other

analog circuitry. Also, these input signals should not overlay the

analog power plane.

Ground Planes

The ground plane should encompass all ADV7172/ADV7173

ground pins, voltage reference circuitry, power supply bypass cir-

cuitry for the ADV7172/ADV7173, the analog output traces, and

all the digital signal traces leading up to the ADV7172/ADV7173.

The ground plane is the board’s common ground plane.

Due to the high clock rates involved, long clock lines to the

ADV7172/ADV7173 should be avoided to reduce noise pickup.

Any active termination resistors for the digital inputs should be

connected to the regular PCB power plane (V_CC) and not the

analog power plane.

Power Planes

The ADV7172/ADV7173, and any associated analog circuitry,

should have its own power plane, referred to as the analog

power plane (V_AA). This power plane should be connected to

the regular PCB power plane (V_CC) at a single point through a

ferrite bead. This bead should be located within three inches of

the ADV7172/ADV7173.

Analog Signal Interconnect

The ADV7172/ADV7173 should be located as close to the

output connectors as possible to minimize noise pickup and

reflections due to impedance mismatch.

The video output signals should overlay the ground plane, not

the analog power plane, to maximize the high frequency power

supply rejection.

The metallization gap separating device power plane and

board power plane should be as narrow as possible to mini-

mize the obstruction to the flow of heat from the device into

the general board.

Digital inputs, especially pixel data inputs and clocking signals,

should never overlay any of the analog signal circuitry and

should be kept as far away as possible.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7172/ADV7173 power pins and voltage

reference circuitry.

For best performance, the outputs should each have a 75 Ω load

resistor connected to GND. These resistors should be placed

as close as possible to the ADV7172/ADV7173 to minimize

reflections.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane unless they can be

arranged so that the plane-to-plane noise is common-mode.

The ADV7172/ADV7173 should have no inputs left floating.

Any inputs that are not required should be tied to ground.

Supply Decoupling

For optimum performance, bypass capacitors should be in-

stalled using the shortest leads possible, consistent with reliable

operation, to reduce the lead inductance. Best performance is

REV. B

–41–

ADV7172/ADV7173

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

0.1ꢃF

0.01ꢃF

5V (V

)

5V (V

)

AA

0.1ꢃF

1, 11, 19, 27, 30, 32, 34, 46

V

AA

COMP1

COMP2

36

23

37

2

DAC A

DAC B

DAC C

35

75ꢂ

300ꢂ

V

REF

33

P0

P7

ADV7172/

ADV7173

9

29

10 CSO_HSO

45

42

43

39

VSO

CLAMP

DAC D 28

PAL_NTSC

SCRESET/RTC

5V (V

)

AA

25

24

DAC E

DAC F

14 HSYNC

“UNUSED

INPUTS

300ꢂ

4kꢂ

FIELD/VSYNC

15

16

SHOULD BE

RESET

GROUNDED”

BLANK

4.7ꢃF

5V (V

)

5V (V

)

CC

44 RESET

4kꢂ

100ꢂ

5V (V

)

AA

SCLOCK

SDATA

20

21

22

38

MPU BUS

100ꢂ

10kꢂ

41

TTX

TTXREQ

TTX

R

SET2

40

TTXREQ

48 CLOCK

600ꢂ

R

SET1

150ꢂ

ALSB

17

GND

12, 13, 18, 26, 31, 47

5V (V

)

AA

10kꢂ

27MHz CLOCK

(SAME CLOCK AS

USED BY MPEG2

DECODER)

Figure 68. Recommended Analog Circuit Layout

–42–

REV. B

ADV7172/ADV7173

APPENDIX 2

CLOSED CAPTIONING

The ADV7172/ADV7173 supports closed captioning, conform-

ing to the standard television synchronizing waveform for color

transmission. Closed captioning is transmitted during the

blanked active line time of Line 21 of the odd fields and Line

284 of even fields.

FCC Code of Federal Regulations (CFR) 47 Section 15.119

and EIA608 describe the closed captioning information for

Lines 21 and 284.

The ADV7172/ADV7173 uses a single buffering method. This

means that the closed captioning buffer is only one byte deep,

therefore there will be no frame delay in outputting the closed

captioning data, unlike other 2-byte deep buffering systems.

The data must be loaded at least one line before (Line 20 or

Line 283) it is outputted on Line 21 and Line 284. A typical

implementation of this method is to use VSYNC to interrupt a

microprocessor, which will in turn load the new data (two bytes)

every field. If no new data is required for transmission, zeros must

be inserted in both data registers; this is called NULLING. It is

also important to load “control codes,” all of which are double

bytes, on Line 21, or a TV will not recognize them. If there is a

message like “Hello World,” which has an odd number of char-

acters, it is important to pad it out to an even number to get

“end of caption” 2-byte control code to land in the same field.

Closed captioning consists of a 7-cycle sinusoidal burst that is

frequency and phase locked to the caption data. After the clock

run-in signal, the blanking level is held for two data bits and is

followed by a Logic Level “1” start bit. Sixteen bits of data

follow the start bit. These consist of two 8-bit bytes, seven data

bits and one odd parity bit. The data for these bytes is stored in

closed captioning Data Registers 0 and 1.

The ADV7172/ADV7173 also supports the extended closed

captioning operation, which is active during even fields, and is

encoded on scan Line 284. The data for this operation is stored

in closed captioning extended Data Registers 0 and 1.

All clock run-in signals, and timing to support closed caption-

ing on Lines 21 and 284, are automatically generated by the

ADV7172/ADV7173. All pixels inputs are ignored during

Lines 21 and 284. Closed captioning is enabled.

10.5 ꢁ 0.25ꢃs

12.91ꢃs

7 CYCLES

OF 0.5035 MHz

(CLOCK RUN-IN)

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

P

A

S

T

A

R

T

P

A

R

I

T

Y

D0–D6

R

I

50 IRE

40 IRE

T

Y

BYTE 1

BYTE 0

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F = 3.579545MHz

SC

AMPLITUDE = 40 IRE

10.003ꢃs

33.764ꢃs

27.382ꢃs

Figure 69. Closed Captioning Waveform (NTSC)

REV. B

–43–

ADV7172/ADV7173

APPENDIX 3

COPY GENERATION MANAGEMENT SYSTEM (CGMS)

The ADV7172/ADV7173 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is

transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data

is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7172/ADV7173 is configured in NTSC

mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a refer-

ence pulse of the same amplitude and duration as a CGMS bit (see Figure 70). These bits are output from the configuration registers

in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10,

C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3,

C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the Bit C/W04 is set to a Logic “1,” the last six bits, C19–C14, which

comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7172/ADV7173 based on the lower 14 bits

(C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data.

The calculation of the CRC sequence is based on the polynomial X⁶+ X + 1 with a preset value of 111111. If C/W04 is set to a

Logic “0,” all 20 bits (C0–C19) are directly output from the CGMS registers (no CRC calculated, must be calculated by the user).

Function of CGMS Bits

Word 0 – 6 Bits

Word 1 – 4 Bits

Word 2 – 6 Bits

CRC

– 6 Bits

CRC Polynomial = X⁶+ X + 1 (Preset to 111111)

Word 0

B1

1

16:9

0

4:3

Aspect Ratio

B2

B3

Display Format

Undefined

Letterbox

Normal

Word 0

B4, B5, B6

Identification information about video and other signals (e.g., audio)

Identification signal incidental to Word 0

Word 1

B7, B8, B9, B10

Word 2

B11, B12, B13, B14 Identification signal and information incidental to Word 0

100 IRE

CRC SEQUENCE

C17 C18 C19

REF

70 IRE

C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

C13 C14 C15 C16

0 IRE

49.1ꢃs ꢁ 0.5ꢃs

–40 IRE

11.2ꢃs

2.235ꢃs ꢁ 20ns

Figure 70. CGMS Waveform Diagram

–44–

REV. B

ADV7172/ADV7173

APPENDIX 4

WIDE SCREEN SIGNALING

The ADV7172/ADV7173 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23.

WSS data can only be transmitted when the ADV7172/ADV7173 is configured in PAL mode. The WSS data is 14 bits long, the

function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 71).

The bits are output from the configuration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3,

C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12,

C/W15 = W13. If the Bit C/W07 is set to a Logic “1” it enables the WSS data to be transmitted on Line 23. The latter portion of

Line 23 (42.5 µs from the falling edge of HSYNC) is available for the insertion of video.

Function of CGMS Bits

Bit 0–Bit 2

Aspect Ratio/Format/Position

Bit 3 is odd parity check of Bit 0–Bit 2

B0 B1 B2 B3 Aspect Ratio Format

Position

Nonapplicable

Center

Top

Center

Top

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

4:3

Full Format

Letterbox

Full Format

14:9

16:9

>16:9

14:9

16:9

Center

Nonapplicable Nonapplicable

B4

0

1

B9 B10

Camera Mode

Film Mode

0

1

0

1

0

1

No Open Subtitles

Subtitles In Active Image Area

Subtitles Out of Active Image Area

Reserved

B5

0

Standard Coding

1

Motion Adaptive Color Plus

B11

0

1

No Surround Sound Information

Surround Sound Mode

B6

0

No Helper

1

Modulated Helper

B12

B13

RESERVED

B7

RESERVED

500mV

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

RUN-IN

SEQUENCE

START

CODE

ACTIVE

VIDEO

11.0ꢃs

38.4ꢃs

42.5ꢃs

Figure 71. WSS Waveform Diagram

REV. B

–45–

ADV7172/ADV7173

APPENDIX 5

TELETEXT INSERTION

Time, t_PD,is the time needed by the ADV7172/ADV7173 to interpolate input data on TTX and insert it onto the CVBS or Y out-

puts, such that it appears t_SYNTTXOUT= 10.2 µs after the leading edge of the horizontal signal. Time, TTX_DEL, is the pipeline delay

time by the source that is gated by the TTXREQ signal in order to deliver TTX data.

With the programmability offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct

position of 10.2 µs after the leading edge of horizontal sync pulse, thus enabling a source interface with variable pipeline delays.

The width of the TTXREQ signal must always be maintained such that it allows the insertion of 360 (in order to comply with the

Teletext Standard “PAL-WST”) teletext bits at a text data rate of 6.9375 Mbits/s. This is achieved by setting TC03–TC00 to “0.”

The insertion window is not open if the Teletext Enable (MR33) is set to “0.”

Teletext Protocol

The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:

(27 MHz/4) = 6.75 MHz

(6.9375 × 10⁶/6.75 × 10⁶) = 1.027777

Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7172/ADV7173

uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal

that can be outputted on the CVBS and Y outputs.

At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits

10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock

cycles are 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All

teletext lines are implemented in the same way. Individual control of teletext lines is controlled by Teletext Setup Registers.

45 BYTES (360 BITS) – PAL

ADDRESS & DATA

TELETEXT VBI LINE

RUN-IN CLOCK

Figure 72. Teletext VBI Line

t_SYNTTXOUT

CVBS/Y

t_PD

HSYNC

10.2ꢃs

TTX

DATA

TTX

DEL

TTXREQ

PROGRAMMABLE PULSE EDGES

TTX

ST

t_SYNTTXOUT= 10.2ꢃs

t_PD= PIPELINE DELAY THROUGH ADV7172/ADV7173

TTX

DEL

= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])

Figure 73. Teletext Functionality Diagram

–46–

REV. B

ADV7172/ADV7173

APPENDIX 6

NTSC WAVEFORMS (WITH PEDESTAL)

1268.1mV

130.8 IRE

100 IRE

PEAK COMPOSITE

1048.4mV

REF WHITE

714.2mV

387.6mV

334.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

48.3mV

SYNC LEVEL

–40 IRE

Figure 74. NTSC Composite Video Levels

1048.4mV

100 IRE

REF WHITE

714.2mV

387.6mV

334.2mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

SYNC LEVEL

48.3mV

–40 IRE

Figure 75. NTSC Luma Video Levels

PEAK CHROMA

963.8mV

650mV

629.7mV (p-p)

286mV (p-p)

BLANK/BLACK LEVEL

PEAK CHROMA

335.2mV

0mV

Figure 76. NTSC Chroma Video Levels

100 IRE

REF WHITE

1052.2mV

720.8mV

7.5 IRE

0 IRE

BLACK LEVEL

BLANK LEVEL

387.5mV

331.4mV

SYNC LEVEL

–40 IRE

45.9mV

Figure 77. NTSC RGB Video Levels

REV. B

–47–

ADV7172/ADV7173

NTSC WAVEFORMS (WITHOUT PEDESTAL)

130.8 IRE

100 IRE

1289.8mV

1052.2mV

PEAK COMPOSITE

REF WHITE

714.2mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

338mV

52.1mV

–40 IRE

Figure 78. NTSC Composite Video Levels

1052.2mV

100 IRE

REF WHITE

714.2mV

338mV

52.1mV

0 IRE

BLANK/BLACK LEVEL

SYNC LEVEL

–40 IRE

Figure 79. NTSC Luma Video Levels

PEAK CHROMA

978mV

650mV

694.9mV (p-p)

286mV (p-p)

BLANK/BLACK LEVEL

PEAK CHROMA

299.3mV

0mV

Figure 80. NTSC Chroma Video Levels

100 IRE

1052.2mV

REF WHITE

715.7mV

BLANK/BLACK LEVEL 336.5mV

51mV

0 IRE

SYNC LEVEL

–40 IRE

Figure 81. NTSC RGB Video Levels

–48–

REV. B

ADV7172/ADV7173

PAL WAVEFORMS

PEAK COMPOSITE

1284.2mV

1047.1mV

REF WHITE

696.4mV

350.7mV

50.8mV

BLANK/BLACK LEVEL

SYNC LEVEL

Figure 82. PAL Composite Video Levels

REF WHITE

1047mV

696.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

350.7mV

50.8mV

Figure 83. PAL Luma Video Levels

PEAK CHROMA

989.7mV

672mV (p-p)

300mV (p-p)

BLANK/BLACK LEVEL

650mV

PEAK CHROMA

317.2mV

0mV

Figure 84. PAL Chroma Video Levels

REF WHITE

1050.2mV

698.4mV

BLANK/BLACK LEVEL

SYNC LEVEL

351.8mV

51mV

Figure 85. PAL RGB Video Levels

REV. B

–49–

ADV7172/ADV7173

UV WAVEFORMS

505mV

423mV

334mV

171mV

BETACAM LEVEL

82mV

0mV

–82mV

ꢄ171mV

ꢄ334mV

–423mV

–505mV

ꢄ505mV

Figure 89. NTSC 100% Color Bars, No Pedestal V Levels

Figure 86. NTSC 100% Color Bars, No Pedestal U Levels

467mV

391mV

309mV

158mV

BETACAM LEVEL

76mV

BETACAM LEVEL

0mV

–76mV

–158mV

–309mV

–391mV

–467mV

Figure 87. NTSC 100% Color Bars with Pedestal U Levels

Figure 90. NTSC 100% Color Bars with Pedestal V Levels

350mV

232mV

350mV

293mV

SMPTE LEVEL

118mV

SMPTE LEVEL

57mV

0mV

–57mV

–118mV

–232mV

–293mV

–350mV

Figure 88. PAL 100% Color Bars, U Levels

Figure 91. PAL 100% Color Bars, V Levels

–50–

REV. B

ADV7172/ADV7173

APPENDIX 7

OPTIONAL OUTPUT FILTER

If an output filter is required for the CVBS, Y, UV, Chroma

0

–10

–20

–30

–40

–50

–60

–70

–80

and RGB outputs of the ADV7172/ADV7173, the filter shown

below can be used. The plot of the filter characteristics is

shown in Figure 93. An Output Filter is not required if the

outputs of the ADV7172/ADV7173 are connected to most

analog monitors or analog TVs; however, if the output signals

are applied to a system where sampling is used (e.g., Digital

TVs), then a filter is required to prevent aliasing.

22pF

1.8ꢃH

FILTER I/P

75ꢂ

FILTER O/P

330pF

270pF

100k

1M

10M

100M

FREQUENCY – Hz

Figure 93. Output Filter Plot

Figure 92. Output Filter Used with Output Buffer

APPENDIX 8

OPTIONAL DAC BUFFERING

When external buffering is needed of the ADV7172/ADV7173

DAC outputs, the configuration in Figure 94 is recommended.

This configuration shows the DAC outputs, A, B, C, running at

half (18 mA) their full current (36 mA) capability. This will

allow the ADV7172/ADV7173 to dissipate less power; the analog

DAC outputs at 18 mA with a V_AAof 3.3 V. This buffer also adds

extra isolation on the video outputs (see buffer circuit in Figure

95). Note that DACs D, E, and F will always require buffering

as the full-scale output current from these DACs is limited to

8.66 mA. With DACs A, B, and C, buffering is optional, based

on the user requirements for performance and power consumption.

current is reduced by 50% with a R_SET1= 300 Ω and R_SET2

600 Ω and an R_LOADof 75 Ω. This mode is recommended for

=

When calculating absolute output full-scale current and voltage,

use the following equations:

3.3 V operation as optimum performance is obtained from the

V

AA

V_OUT= I_OUT× R_LOAD

ADV7172/ADV7173

V_REF× K

(

)

I_OUT

=

OUTPUT

BUFFER

V

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

CVBS

LUMA

REF

R_SET

R

SET1

OUTPUT

BUFFER

K = 4.2146 constant,V_REF= 1.235 V

300ꢂ

OUTPUT

BUFFER

CHROMA

V

+

PIXEL

PORT

DIGITAL

CORE

CC

OUTPUT

BUFFER

G

B

5

4

3

1

OUTPUT TO

TV MONITOR

AD8051

2

OUTPUT

BUFFER

R

SET2

INPUT/

OPTIONAL

FILTER O/P

600ꢂ

OUTPUT

BUFFER

R

V

–

CC

Figure 95. Recommended Output DAC Buffer

Figure 94. Output DAC Buffering Configuration

REV. B

–51–

ADV7172/ADV7173

APPENDIX 9

RECOMMENDED REGISTER VALUES

The ADV7172/ADV7173 registers can be set depending on the

user standard required.

PAL B, D, G, H, I (F_SC= 4.43361875 MHz)

Address

Data

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

11Hex

07Hex

68Hex

00Hex

01Hex

00Hex

08Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

The following examples give the various register formats for

several video standards.

In each case the output is set to composite/luma/chroma outputs

with DACs D, E and F powered up to provide 8.66 mA and

with the BLANK input control disabled. Additionally, the burst

and color information are enabled on the output and the inter-

nal color bar generator is switched off. In the examples shown,

the timing mode is set to Mode 0 in slave format. TR02–TR00

of the Timing Register 0 control the timing modes. For a

detailed explanation of each bit in the command registers,

please turn to the Register Programming section of the data

sheet. TR07 should be toggled after setting up a new timing

mode. Timing Register 1 provides additional control over the

position and duration of the timing signals. In the examples this

register is programmed in default mode.

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

NTSC (F_SC= 3.5795454 MHz)

Address

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Data

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

10Hex

07Hex

68Hex

00Hex

08Hex

00Hex

16Hex

7CHex

F0Hex

21Hex

00Hex

CGMS_WSS Reg 1

CGMS_WSS Reg 2

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Brightness Control Register

Sharpness Control Register

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

PAL M (F_SC= 3.57561149 MHz)

Address

Data

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

12Hex

07Hex

68Hex

00Hex

08Hex

00Hex

A3Hex

EFHex

E6Hex

21Hex

00Hex

CGMS_WSS Reg 1

CGMS_WSS Reg 2

Timing Register 0

Timing Register 1

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Brightness Control Register

Sharpness Control Register

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

–52–

REV. B

ADV7172/ADV7173

PAL M (Continued) (F_SC= 3.57561149 MHz)

Address

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

CGMS_WSS Reg 1

CGMS_WSS Reg 2

00Hex

Data

00Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

CGMS_WSS Reg 1

CGMS_WSS Reg 2

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

00Hex

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Brightness Control Register

Sharpness Control Register

PAL-60 (F_SC= 4.43361875 MHz)

Address

Data

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

12Hex

07Hex

68Hex

00Hex

08Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

Brightness Control Register

Sharpness Control Register

PAL N (F_SC= 4.43361875 MHz)

Address

Timing Register 0

Timing Register 1

Data

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

13Hex

07Hex

68Hex

00Hex

08Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

CGMS_WSS Reg 1

CGMS_WSS Reg 2

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

Brightness Control Register

Sharpness Control Register

REV. B

–53–

ADV7172/ADV7173

POWER ON RESET REG VALUES

(PAL_NTSC = 0, NTSC Selected)

POWER ON RESET REG VALUES

(PAL_NTSC = 1, PAL Selected)

Address

Data

Address

Data

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

00Hex

07Hex

08Hex

00Hex

16Hex

7CHex

F0Hex

21Hex

00Hex

01Hex

02Hex

03Hex

04Hex

05Hex

06Hex

07Hex

0AHex

0BHex

0CHex

0DHex

0EHex

0FHex

10Hex

11Hex

12Hex

13Hex

14Hex

15Hex

16Hex

17Hex

18Hex

19Hex

1AHex

1BHex

1CHex

1DHex

1EHex

1FHex

20Hex

21Hex

22Hex

Mode Register 0

Mode Register 1

Mode Register 2

Mode Register 3

Mode Register 4

Mode Register 5

Mode Register 6

Mode Register 7

00Hex

07Hex

08Hex

00Hex

CBHex

8AHex

09Hex

2AHex

00Hex

Timing Register 0

Timing Register 1

Timing Register 0

Timing Register 1

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

Subcarrier Frequency Register 0

Subcarrier Frequency Register 1

Subcarrier Frequency Register 2

Subcarrier Frequency Register 3

Subcarrier Phase Register

Closed Captioning Ext Register 0

Closed Captioning Ext Register 1

Closed Captioning Register 0

Closed Captioning Register 1

Pedestal Control Register 0

Pedestal Control Register 1

Pedestal Control Register 2

Pedestal Control Register 3

CGMS_WSS Reg 0

CGMS_WSS Reg 1

CGMS_WSS Reg 2

CGMS_WSS Reg 1

CGMS_WSS Reg 2

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Brightness Control Register

Sharpness Control Register

Teletext Request Control Register

Contrast Control Register

Color Control Register 1

Color Control Register 2

Hue Control Register

Brightness Control Register

Sharpness Control Register

–54–

REV. B

ADV7172/ADV7173

APPENDIX 10

OPTIONAL DAC BUFFERING

0.6

0.4

0.2

0.0

ꢄ0.2

L608

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 0.00 dB

APL = 39.1%

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = SOURCE

625 LINE PAL

NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

FRAMES SELECTED: 1 2 3 4

Figure 96. 100/0/75/0 PAL Color Bars

0.5

0.0

L575

0.0

10.0

20.0

30.0

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

40.0

50.0

60.0

70.0

APL NEEDS SYNC = SOURCE!

625 LINE PAL

SOUND-IN-SYNC OFF

SYNC = A

NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

FRAMES SELECTED: 1

Figure 97. 100/0/75/0 PAL Color Bars Luminance

REV. B

–55–

ADV7172/ADV7173

0.5

0.0

–0.5

L575

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NO BRUCH SIGNAL

APL NEEDS SYNC = SOURCE!

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

SYNC = A

FRAMES SELECTED: 1

Figure 98. 100/0/75/0 PAL Color Bars Chrominance

100.0

0.5

50.0

0.0

F1

L76

–50.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

APL = 44.6%

PRECISION MODE OFF

SYNCHRONOUS

525 LINE NTSC

NO FILTERING

SYNC = A

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

FRAMES SELECTED: 1 2

Figure 99. 100/7.5/75/7.5 NTSC Color Bars

–56–

REV. B

ADV7172/ADV7173

0.6

0.4

0.2

50.0

0.0

–0.2

F2

L238

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL = 44.7%

PRECISION MODE OFF

525 LINE NTSC

NO FILTERING

SYNCHRONOUS

SYNC = SOURCE

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

FRAMES SELECTED: 1 2

Figure 100. 100/7.5/75/7.5 NTSC Color Bars Luminance

0.4

50.0

0.2

0.0

–0.2

–0.4

–50.0

F1

L76

0.0

10.0

20.0

30.0

40.0

50.0

60.0

MICROSECONDS

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC = SOURCE!

PRECISION MODE OFF

SYNCHRONOUS

525 LINE NTSC

NO FILTERING

SYNC = B

SLOW CLAMP TO 0.00 V AT 6.72 ꢃs

FRAMES SELECTED: 1 2

Figure 101. 100/7.5/75/7.5 NTSC Color Bars Chrominance

REV. B

–57–

ADV7172/ADV7173

V

APL = 39.6%

SYSTEM LINE L608

ANGLE (DEG) 0.0

GAIN ꢀ 1.000 0.000dB

625 LINE PAL

cy

BURST FROM SOURCE

DISPLAY +V & –V

R

g

M

g

75%

100%

YI

b

U

yl

B

G

Cy

m

g

r

SOUND IN SYNC OFF

Figure 102. PAL Vector Plot

R-Y

APL = 45.1%

SYSTEM LINE L76F1

ANGLE (DEG) 0.0

GAIN ꢀ 1.000 0.000dB

525 LINE NTSC

BURST FROM SOURCE

cy

I

R

M

g

Q

YI

b

100%

B-Y

75%

B

G

Cy

–Q

–I

SETUP 7.5%

Figure 103. NTSC Vector Plot

–58–

REV. B

ADV7172/ADV7173

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

48-Lead LQFP

(ST-48)

0.063 (1.60) MAX

30 0 7

0.354 (9.00) BSC

0.276 (7.0) BSC

0.057 (1.45)

0.030 (0.75)

0.018 (0.45)

18 0 4

0.053 (1.35)

37

36

48

1

SEATING

PLANE

TOP VIEW

(PINS DOWN)

0.006 (0.15)

12

13

25

24

0.002 (0.05)

0° MIN

0° – 7°

0.007 (0.18)

0.004 (0.09)

0.019 (0.5)

BSC

0.011 (0.27)

0.006 (0.17)

REV. B

–59–

–60–


型号：	ADV7172_15
厂家：	ADI
描述：	Digital PAL/NTSC Video Encoder with Six DACs
文件：	总60页 (文件大小：469K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7172_15 [ADI]

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