ADV7174BCPZ [ADI]
IC COLOR SIGNAL ENCODER, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40, Color Signal Converter;
| 型号： | ADV7174BCPZ |
| 厂家： | 
ADI |
| 描述： | IC COLOR SIGNAL ENCODER, QCC40, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40, Color Signal Converter 编码器 |
| 文件： | 总52页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Chip Scale PAL/NTSC Video Encoder with
Advanced Power Management
ADV7174/ADV7179
FEATURES
Programmable subcarrier frequency and phase
ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder
High quality 10-bit video DACs
Programmable LUMA delay
Individual on/off control of each DAC
CCIR and square pixel operation
SSAF™ (super sub-alias filter)
Advanced power management features
CGMS (copy generation management system)
WSS (wide screen signaling)
NTSC M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60
Single 27 MHz clock required (×2 oversampling)
Macrovision 7.1 (ADV7174 only)
Integrated subcarrier locking to external video source
Color signal control/burst signal control
Interlaced/noninterlaced operation
Complete on-chip video timing generator
Programmable multimode master/slave operation
Closed captioning support
80 dB video SNR
Teletext insertion port (PAL-WST)
On-board color bar generation
On-board voltage reference
2-wire serial MPU interface (I2C® compatible and fast I2C)
Single-supply 2.8 V and 3.3 V operation
Small 40-lead 6 mm × 6 mm LFCSP package
−40°C to +85°C at 3.3 V
32-bit direct digital synthesizer for color subcarrier
Multistandard video output support:
Composite (CVBS)
Component S-video (Y/C)
Video input data port supports:
CCIR-656 4:2:2 8-bit parallel input format
Programmable simultaneous composite and S-video or RGB
(SCART)/YPbPr video outputs
Programmable luma filters low-pass [PAL/NTSC] notch,
extended SSAF, CIF, and QCIF
Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,
1.2 MHz, and 2.0 MHz], CIF, and QCIF)
−20°C to +85°C at 2.8 V
APPLICATIONS
Portable video applications
Mobile phones
Digital still cameras
Programmable VBI (vertical blanking interval)
FUNCTIONAL BLOCK DIAGRAM
TTXREQ TTX
ADV7174/ADV7179
M
U
L
T
I
P
L
E
X
E
R
10
10
10
POWER
10
10
10
10-BIT
DAC
MANAGEMENT
CONTROL
CGMS AND WSS
INSERTION
BLOCK
TELETEXT
INSERTION
BLOCK
DACA(PIN29)
DACB(PIN28)
DACC(PIN24)
YUV TO
RBG
V
AA
(SLEEP MODE)
10-BIT
DAC
MATRIX
RESET
10-BIT
DAC
10
8
PROGRAMMABLE
9
8
Y
9
COLOR
DATA
ADD
SYNC
INTER-
POLATOR
LUMINANCE
FILTER
4:2:2 TO
YCrCb
4:4:4
INTER-
POLATOR
TO
YUV
MATRIX
P7–P0
8
10
10
U
U
V
8
8
8
8
8
PROGRAMMABLE
CHROMINANCE
FILTER
ADD
BURST
INTER-
POLATOR
8
8
V
10
10
HSYNC
FIELD/VSYNC
BLANK
VIDEO TIMING
GENERATOR
V
REAL-TIME
CONTROL
CIRCUIT
REF
SIN/COS
DDS BLOCK
VOLTAGE
REFERENCE
CIRCUIT
2
I C MPU PORT
R
SET
COMP
CLOCK
SCLOCK SDATA ALSB
SCRESET/RTC
GND
Figure 1.
1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).
2 Throughout the document, N is referenced to PAL – Combination – N.
3 ADV7174 only.
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. The Macrovision anticopy process is licensed for
noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest Macrovision version available.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Specifications subject to change without notice. No license is granted by implication
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADV7174/ADV7179
TABLE OF CONTENTS
Specifications..................................................................................... 4
2.8 V Specifications ...................................................................... 4
2.8 V Timing Specifications ........................................................ 5
3.3 V Specifications ...................................................................... 6
3.3 V Timing Specifications ........................................................ 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
General Description....................................................................... 11
Data Path Description................................................................ 11
Internal Filter Response............................................................. 11
Typical Performance Characteristics ........................................... 13
Features ............................................................................................ 16
Color Bar Generation ................................................................ 16
Square Pixel Mode...................................................................... 16
Color Signal Control.................................................................. 16
Burst Signal Control................................................................... 16
NTSC Pedestal Control ............................................................. 16
Pixel Timing Description .......................................................... 16
8-Bit YCrCb Mode ................................................................. 16
Subcarrier Reset.......................................................................... 16
Real-Time Control ..................................................................... 16
Video Timing Description .................................................... 16
Vertical Blanking Data Insertion.......................................... 17
Mode 0 (CCIR-656): Slave Option....................................... 17
Mode 0 (CCIR-656): Master Option ................................... 17
HSYNC BLANK
, , FIELD.. 24
Mode 3: Master/Slave Option
Power-On Reset.......................................................................... 25
SCH Phase Mode........................................................................ 25
MPU Port Description............................................................... 25
Register Accesses ........................................................................ 26
Register Programming................................................................... 27
Subaddress Register (SR7–SR0) ............................................... 27
Register Select (SR5–SR0)......................................................... 27
Mode Register 1 (MR1)............................................................. 29
Mode Register 2 (MR2)............................................................. 30
Mode Register 3 (MR3)............................................................. 31
Mode Register 4 (MR4)............................................................. 32
Timing Mode Register 0 (TR0) ................................................ 33
Timing Mode Register 1 (TR1) ................................................ 34
Subcarrier Frequency Registers 3–0 ........................................ 35
Subcarrier Phase Register.......................................................... 35
Closed Captioning Even Field Data Registers 1–0 ................ 35
Closed Captioning Odd Field Data Registers 1–0 ................. 36
NTSC Pedestal/PAL Teletext Control Registers 3–0 ............. 36
Teletext Request Control Register (TC07).............................. 37
CGMS_WSS Register 0 (C/W0)............................................... 37
CGMS_WSS Register 1 (C/W1)............................................... 38
CGMS_WSS Register 2 (C/W2)............................................... 38
Appendix 1—Board Design and Layout Considerations.......... 39
Ground Planes ............................................................................ 39
Power Planes ............................................................................... 39
Supply Decoupling..................................................................... 40
Digital Signal Interconnect ....................................................... 40
Analog Signal Interconnect....................................................... 40
Appendix 2—Closed Captioning ................................................. 41
HSYNC BLANK
Mode 1: Slave Option
Mode 1: Master Option
,
, FIELD................ 20
HSYNC BLANK
,
, FIELD ............ 21
HSYNC VSYNC BLANK
Mode 2: Slave Option
Mode 2: Master Option
,
,
.............. 22
HSYNC VSYNC BLANK
.......... 23
,
,
Rev. A | Page 2 of 52
ADV7174/ADV7179
Appendix 3—Copy Generation Management System (CGMS)
............................................................................................................42
NTSC Waveforms (without Pedestal) ......................................46
PAL Waveforms...........................................................................47
Pb Pr Waveforms.........................................................................48
Appendix 7—Optional Output Filter...........................................49
Appendix 8—Recommended Register Values.............................50
Outline Dimensions........................................................................52
Ordering Guide ...........................................................................52
Function of CGMS Bits..............................................................42
Appendix 4—Wide Screen Signaling (WSS) ...............................43
Function of WSS Bits..................................................................43
Appendix 5—Teletext .....................................................................44
Teletext Insertion.........................................................................44
Teletext Protocol..........................................................................44
Appendix 6—Waveforms ...............................................................45
NTSC Waveforms (with Pedestal) ............................................45
REVISION HISTORY
2/04—Changed from REV. 0 to REV A.
Added 2.8 V Version .......................................................... Universal
Format Updated.................................................................. Universal
Device Currents Updated on 3.3 V Specification .......... Universal
Added new Table 1 and Renumbered Subsequent Tables.............4
Added new Table 2 and Renumbered Subsequent Tables ...........5
Change to Figure 54........................................................................38
Change to Figure 55........................................................................39
Change to Figure 79........................................................................48
Changed Ordering Guide Temperature Specifications..............52
Updated Outline Dimensions........................................................52
10/02—Revision 0: Initial Version
Rev. A | Page 3 of 52
ADV7174/ADV7179
SPECIFICATIONS
2.8 V SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 1.
Parameter
Conditions1
Min
Typ
Max
Unit
STATIC PERFORMANCE2
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS2
10
Bits
RSET = 300 Ω
Guaranteed monotonic
3.0
LSB
LSB
1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
DIGITAL OUTPUTS2
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS2
Output Current3
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS2, 4
VAA
1.6
2.4
V
V
µA
pF
0.7
1
VIN = 0.4 V or 2.4 V
10
10
ISOURCE = 400 µA
ISINK = 3.2 mA
V
V
µA
pF
0.4
10
RSET = 150 Ω, RL = 37.5 Ω
33
0
34.7
2.0
37
1.4
30
mA
%
V
kΩ
pF
30
IOUT = 0 mA
2.8
V
Normal Power Mode
IDAC (Max)5
ICCT
RSET = 150 Ω, RL = 37.5 Ω
115
30
120
mA
mA
6
Low Power Mode
IDAC (Max)5
ICCT
62
30
mA
mA
6
Sleep Mode
7
IDAC
ICCT
0.1
0.001
0.01
µA
µA
%/%
8
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
1 Temperature range TMIN to TMAX: –20°C to +85°C.
2 Guaranteed by characterization.
3 DACs can output 35 mA typically at 2.8 V (RSET = 150 Ω and RL = 37.5 Ω). Full drive into 37.5 Ω load.
4 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
5 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
6 ICCT (circuit current) is the continuous current required to drive the device.
7 Total DAC current in sleep mode.
8 Total continuous current during sleep mode.
Rev. A | Page 4 of 52
ADV7174/ADV7179
2.8 V TIMING SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 2.
Parameter
MPU PORT2, 3
Conditions1
Min
Typ
Max
Unit
SCLOCK Frequency
0
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 4
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
0.6
1.3
0.6
0.6
100
After this period the first clock is generated
Relevant for repeated start condition
300
300
0.6
7
0
ns
ns
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
Data Hold Time, t12
3.5
4
ns
ns
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
4
3
ns
ns
ns
ns
12
8
48
4
Digital Output Hold Time, t1
5
Pipeline Delay, tPD
Clock Cycles
TELETEXT3, 4, 6
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
23
2
6
ns
ns
ns
3, 4
RESET
CONTROL
RESET
6
ns
Low Time
1 Temperature range TMIN to TMAX: –20°C to +85°C.
2 TTL input values are 0 V to 2.8 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
3 Guaranteed by characterization.
4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
5 See Figure 60.
6 Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
Rev. A | Page 5 of 52
ADV7174/ADV7179
3.3 V SPECIFICATIONS
VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 3.
Parameter
Conditions1
Min
Typ
Max
Unit
STATIC PERFORMANCE3
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS3
10
Bits
RSET = 300 Ω
Guaranteed Monotonic
0.6
LSB
LSB
1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
V
V
µA
pF
0.8
1
3, 4
VIN = 0.4 V or 2.4 V
Input Capacitance, CIN
DIGITAL OUTPUTS3
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
ANALOG OUTPUTS3
Output Current4, 5
10
10
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
33
0
34.7
5
2.0
37
mA
mA
%
V
kΩ
pF
Output Current6
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
POWER REQUIREMENTS3, 7
VAA
1.4
30
30
IOUT = 0 mA
3.0
3.3
3.6
120
V
Normal Power Mode
IDAC (Max)8
RSET = 150 Ω, RL = 37.5 Ω
RSET = 1041 Ω, RL = 262.5 Ω
115
20
35
mA
mA
mA
IDAC (Min)8
9
ICCT
Low Power Mode
IDAC (Max)8
62
20
35
mA
mA
mA
IDAC (Min)8
9
ICCT
Sleep Mode
10
IDAC
ICCT
0.1
0.001
0.01
µA
µA
%/%
11
Power Supply Rejection Ratio
COMP = 0.1 µF
0.5
1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V.
2 Temperature range TMIN to TMAX: –40°C to +85°C.
3 Guaranteed by characterization.
4 Full drive into 37.5 Ω load.
5 DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω), optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω).
6 Minimum drive current (used with buffered/scaled output load).
7 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C.
8 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 37 mA output per DAC) to drive all three DACs. Turning off individual DACs
reduces IDAC correspondingly.
9 ICCT (circuit current) is the continuous current required to drive the device.
10 Total DAC current in sleep mode.
11 Total continuous current during sleep mode.
Rev. A | Page 6 of 52
ADV7174/ADV7179
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 4.
Parameter
MPU PORT3, 4
Conditions1
Min
Typ
Max
Unit
SCLOCK Frequency
0
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
ANALOG OUTPUTS3, 5
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
0.6
1.3
0.6
0.6
100
After this period, the first clock is generated
Relevant for repeated start condition
300
300
0.6
7
0
ns
ns
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
Data Hold Time, t12
3.5
4
ns
ns
Control Setup Time, t11
Control Hold Time, t12
Digital Output Access Time, t13
Digital Output Hold Time, t14
4
3
ns
ns
ns
ns
12
8
48
6
Pipeline Delay, tPD
Clock Cycles
TELETEXT3, 4
Digital Output Access Time, t16
Data Setup Time, t17
Data Hold Time, t18
23
2
6
ns
ns
ns
3, 4
RESET
CONTROL
RESET
6
ns
Low Time
1 The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
2 Temperature range TMIN to TMAX: –40°C to +85°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4 Guaranteed by characterization.
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 See Figure 60.
Rev. A | Page 7 of 52
ADV7174/ADV7179
t5
t3
t3
SDATA
t6
t1
SCLOCK
t2
t7
t4
t8
Figure 2. MPU Port Timing Diagram
CLOCK
HSYNC,
t9
t10
t12
CONTROL
FIELD/VSYNC,
BLANK
I/P
S
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
Y
t11
t13
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O/PS
t14
Figure 3. Pixel and Control Data Timing Diagram
TTXREQ
CLOCK
t16
t17
t18
TTX
4 CLOCK
CYCLES
4 CLOCK
CYCLES
4 CLOCK
CYCLES
3 CLOCK
CYCLES
4 CLOCK
CYCLES
Figure 4. Teletext Timing Diagram
Rev. A | Page 8 of 52
ADV7174/ADV7179
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability
VAA to GND
4 V
Voltage on Any Digital Input Pin
Storage Temperature (TS)
Junction Temperature (TJ)
Lead Temperature
Soldering, 10 sec
Analog Outputs to GND1
GND – 0.5 V to VAA + 0.5 V
−65°C to +150°C
150°C
260°C
GND – 0.5 V to VAA
2
θJA
30°C/W
__________________________________________________
1 Analog output short circuit to any power supply or common can be of an indefinite duration.
2 With the exposed metal paddle on the underside of LFCSP soldered to GND on the PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 9 of 52
ADV7174/ADV7179
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
39
40
38 37 36 35 34 33 32 31
PIN 1
INDICATOR
1
2
30
29
28
27
26
25
24
23
22
21
CLOCK
V
REF
V
AA
DAC A
DAC B
3
P5
P6
4
V
AA
ADV7174/ADV7179
5
GND
P7
LFCSP
TOP VIEW
(Not to Scale)
6
V
GND
GND
GND
GND
AA
7
DAC C
COMP
8
9
SDATA
SCLOCK
10
V
AA
11 12 13 14 15 16 17 18 19 20
Figure 5. Pin Configurations
Table 6. Pin Function Descriptions
Input/
Output
Mnemonic
P7–P0
CLOCK
Function
I
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0). P0 is the LSB.
TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz
(NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC
I/O
HSYNC
(Modes 1 and 2) Control Signal. This pin may be configured to output (master mode) or accept (slave
mode) sync signals.
FIELD/VSYNC I/O
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output
(master mode) or accept (slave mode) these control signals.
BLANK
I/O
I
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic 0. This signal is optional.
SCRESET/RTC
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a
subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0.
Alternatively, it can be configured as a real-time control (RTC) input.
VREF
RSET
I/O
I
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes of the video signals.
COMP
O
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA. For optimum dynamic performance in low
power mode, the value of the COMP capacitor can be lowered to as low as 2.2 nF.
DAC A
DAC B
DAC C
SCLOCK
SDATA
ALSB
O
O
O
I
I/O
I
DAC Output (see Table 13)
DAC Output (see Table 13).
DAC Output (see Table 13).
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal sets up the LSB of the MPU address.
RESET
I
This input resets the on-chip timing generator and sets the ADV7174/ADV7179 into default mode. This is NTSC
operation, Timing Slave Mode 0, 8-bit operation, 2× composite out signals. DACs A, B, and C are enabled.
TTX
I
Teletext Data.
TTXREQ
VAA
GND
O
P
G
Teletext Data Request Signal/Defaults to GND when Teletext Not Selected.
Power Supply (2.8 V or 3.3 V).
Ground Pin.
Rev. A | Page 10 of 52
ADV7174/ADV7179
GENERAL DESCRIPTION
typically have a range of 128 112; however, it is possible to
input data from 1 to 254 on both Y, Cb, and Cr. The ADV7174/
ADV7179 supports PAL (B/D/G/H/I/M/N) and NTSC (with
The ADV7174/ADV7179 is an integrated digital video encoder
that converts digital CCIR-601 4:2:2 8-bit component video data
into a standard analog baseband television signal compatible
with worldwide standards.
BLANK
and without pedestal) standards. The appropriate SYNC,
,
and burst levels are added to the YCrCb data. Macrovision Anti-
taping (ADV7174 only), closed-captioning, and Teletext levels
are also added to Y and the resultant data is interpolated to a
rate of 27 MHz. The interpolated data is filtered and scaled by
three digital FIR filters.
The on-board SSAF (super sub-alias filter) with extended
luminance frequency response and sharp stop-band attenuation
enables studio quality video playback on modern TVs, giving
optimal horizontal line resolution.
An advanced power management circuit enables optimal con-
trol of power consumption in both normal operating modes
and in power-down or sleep modes.
The U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. The luma (Y) signal can be delayed 1–3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
The luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
The ADV7174/ADV7179 supports both PAL and NTSC square
pixel operation. The parts incorporate WSS and CGMS-A data
control generation.
The YCrCb data is also used to generate RGB data with
The output video frames are synchronized with the incoming
data timing reference codes. Optionally, the encoder accepts
BLANK
appropriate SYNC and
levels. The RGB data is in
synchronization with the composite video output. Alternatively,
analog YPbPr data can be generated instead of RGB data.
HSYNC VSYNC
(and can generate)
,
, and FIELD timing signals.
These timing signals can be adjusted to change pulse width and
position while the part is in the master mode. The encoder
requires a signal two times the pixel rate (27 MHz) clock for
standard operation. Alternatively, the encoder requires a
24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL
square pixel mode operation. All internal timing is generated
on-chip.
The three l0-bit DACs can be used to output:
•
•
•
•
Composite Video + Composite Video
S-Video + Composite Video
YPrPb Video
SCART RGB Video
Alternatively, each DAC can be individually powered off if not
required.
A separate Teletext port enables the user to directly input
Teletext data during the vertical blanking interval.
Video output levels are illustrated in Appendix 6.
The ADV7174/ADV7179 modes are set up over a 2-wire serial
bidirectional port (I2 C compatible) with two slave addresses.
INTERNAL FILTER RESPONSE
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response, a CIF response, and a QCIF
response. The UV filter supports several different frequency
responses, including four low-pass responses, a CIF response,
and a QCIF response. These can be seen in Table 7 and Table 8
and Figure 6 to Figure 18.
The ADV7174/ADV7179 is packaged in a 40-lead 6 mm × 6 mm
LFCSP package.
DATA PATH DESCRIPTION
For PAL B/D/G/H/I/M/N and NTSC M and N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
27 MHz data rate. The pixel data is demultiplexed to form three
data paths. Y typically has a range of 16 to 235, and Cr and Cb
Rev. A | Page 11 of 52
ADV7174/ADV7179
Table 7. Luminance Internal Filter Specifications
Pass-Band Ripple
(dB)
3 dB Bandwidth
(MHz)
Stop-Band Cutoff
(MHz)
Stop-Band Attenuation
(dB)
Filter Type
Filter Selection
MR04 MR03 MR02
Low-Pass
(NTSC)
Low-Pass
(PAL)
0
0
0
0.091
0.15
4.157
4.74
7.37
7.96
−56
−64
0
0
1
Notch (NTSC)
Notch (PATL)
Extended
(SSAF)
0
0
1
1
1
0
0
1
0
0.015
0.095
0.051
6.54
6.24
6.217
8.3
8.0
8.0
−68
−66
−61
CIF
QCIF
1
1
0
1
1
0
0.018
Monotonic
3.0
1.5
7.06
7.15
−61
−50
Table 8. Chrominance Internal Filter Specifications
Pass-Band Ripple
(dB)
3 dB Bandwidth
(MHz)
Stop-Band Cutoff
(MHz)
Stop-Band Attenuation
(dB)
Filter Type
Filter Selection
MR07 MR06 MR05
1.3 MHz
Low-Pass
0.65 MHz
Low-Pass
1.0 MHz
Low-Pass
2.0 MHz
0
0
0
0
0
0
1
1
0
1
0
1
0.084
1.395
0.65
1.0
3.01
3.64
3.73
5.0
−45
Monotonic
Monotonic
0.0645
−58.5
−49
2.2
−40
Low-Pass
Reserved
CIF
QCIF
1
1
1
0
0
1
0
1
0
0.084
Monotonic
0.7
0.5
3.01
4.08
−45
−50
Rev. A | Page 12 of 52
ADV7174/ADV7179
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–20
–30
–40
–50
–60
–70
–10
–20
–30
–40
–50
–60
–70
0
0
0
2
4
6
8
10
12
0
0
0
2
4
6
8
10
12
12
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Chrominance Internal Filter Specifications
Figure 9. PAL Notch Luma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
2
4
6
8
10
12
2
4
6
8
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. PAL Low-Pass Luma Filter
Figure 10. Extended Mode (SSAF) Luma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
2
4
6
8
10
12
2
4
6
8
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. NTSC Notch Luma Filter
Figure 11. CIF Luma Filter
Rev. A | Page 13 of 52
ADV7174/ADV7179
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
0
0
2
4
6
8
10
12
12
12
0
0
0
2
4
6
8
10
12
12
12
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. QCIF Luma Filter
Figure 15. 1.0 MHz Low-Pass Chroma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
2
4
6
8
10
2
4
6
8
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. 1.3 MHz Low-Pass Chroma Filter
Figure 16. 2.0 MHz Low-Pass Chroma Filter
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
2
4
6
8
10
2
4
6
8
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 14. 0.65 MHz Low-Pass Chroma Filter
Figure 17. CIF Chroma Filter
Rev. A | Page 14 of 52
ADV7174/ADV7179
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 18. QCIF Chroma Filter
Rev. A | Page 15 of 52
ADV7174/ADV7179
FEATURES
COLOR BAR GENERATION
REAL-TIME CONTROL
The ADV7174/ADV7179 can be configured to generate 100/
7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color
bars. These are enabled by setting MR17 of Mode Register 1 to
Logic 1.
Together with the SCRESET/RTC pin and Bits MR22 and MR21
of Mode Register 2, the ADV7174/ADV7179 can be used to
lock to an external video source. The real-time control mode
allows the ADV7174/ADV7179 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7183A video
decoder; see Figure 19), the part automatically changes to the
compensated subcarrier frequency on a line-by-line basis. This
digital data stream is 67 bits wide and the subcarrier is contained
in Bits 0 to 21. Each bit is two clock cycles long. 00H should be
written into all four subcarrier frequency registers when using
this mode.
SQUARE PIXEL MODE
The ADV7174/ADV7179 can be used to operate in square pixel
mode. For NTSC operation, an input clock of 24.5454 MHz is
required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. The internal timing logic adjusts accord-
ingly for square pixel mode operation.
COLOR SIGNAL CONTROL
The color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
Video Timing Description
The ADV7174/ADV7179 is intended to interface with off-the-
shelf MPEG1 and MPEG2 decoders. Consequently, the
ADV7174/ADV7179 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either a system
master video timing generator or as a slave to the system video
timing generator. The ADV7174/ADV7179 generates all of the
required horizontal and vertical timing periods and levels for
the analog video outputs.
BURST SIGNAL CONTROL
The burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
NTSC PEDESTAL CONTROL
The pedestal on both odd and even fields can be controlled on a
line-by-line basis using the NTSC pedestal control registers.
This allows the pedestals to be controlled during the vertical
blanking interval.
The ADV7174/ADV7179 calculates the width and placement of
analog sync pulses, blanking levels, and color burst envelopes.
Color bursts are disabled on appropriate lines, and serration and
equalization pulses are inserted where required.
PIXEL TIMING DESCRIPTION
The ADV7174/ADV7179 operates in an 8-bit YCrCb mode.
8-Bit YCrCb Mode
In addition, the ADV7174/ADV7179 supports a PAL or NTSC
square pixel operation in slave mode. The part requires an input
pixel clock of 24.5454 MHz for NTSC and an input pixel clock
of 29.5 MHz for PAL. The internal horizontal line counters
place the various video waveform sections into the correct
location for the new clock frequencies.
This default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. The inputs follow the sequence Cb0, Y0
Cr0, Y1, Cb1, Y2, and so on. The Y, Cb, and Cr data are input on
a rising clock edge.
SUBCARRIER RESET
Together with the SCRESET/RTC pin and Bits MR22 and
MR21 of Mode Register 2, the ADV7174/ADV7179 can be used
in subcarrier reset mode. The subcarrier resets to Field 0 at the
start of the following field when a low-to-high transition occurs
on this input pin.
The ADV7174/ADV7179 has four distinct master and four
distinct slave timing configurations. Timing control is
HSYNC BLANK
established with the bidirectional
,
, and
VSYNC
FIELD/
pins. Timing Mode Register 1 can also be used
to vary the timing pulse widths and where they occur in
relation to each other.
Rev. A | Page 16 of 52
ADV7174/ADV7179
CLOCK
COMPOSITE
VIDEO
(e.g., VCR
OR CABLE)
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7183A)
GREEN/LUMA/Y
RED/CHROMA/Pr
P7–P0
BLUE/COMPOSITE/Pb
HSYNC
FIELD/VSYNC
AD7174/ADV7179
SEQUENCE
RESERVED
2
BIT
H/LTRANSITION
COUNT START
RESET
BIT
5 BITS
RESERVED
4 BITS
RESERVED
3
LOW
13
14 BITS
RESERVED
128
1
PLL INCREMENT
F
SC
0
0
21
RTC
TIME SLOT: 01
6768
14
19
NOT USED IN THE
ADV7174/ADV7179
VALID
SAMPLE SAMPLE
INVALID
8/LLC
NOTES
1
F
F
PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 F DDS REGISTER IS
SC
SC
PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
SC
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.
2
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET BIT
3
RESET ADV7174/ADV7179 DDS
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
nization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/post-
equalization pulses (see Figure 21 to Figure 32). This mode of
operation is called partial blanking and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YCbCr data stream, for example. WSS data,
CGMS, VPS, and so on. Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
HSYNC
VSYNC
Mode 0 is illustrated in Figure 20. The
BLANK
and
mode.
, FIELD/
(if not used) pins should be tied high during this
,
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7174/ADV7179 generates H, V, and F signals required
for the SAV and EAV time codes in the CCIR-656 standard. The
HSYNC
H bit is output on the
pin, the V bit is output on the
BLANK
VSYNC
pin, and the F bit is output on the FIELD/ pin.
Mode 0 (CCIR-656): Slave Option
Mode 0 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL).
The H, V, and F transitions relative to the video waveform are
illustrated in Figure 23.
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7174/ADV7179 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchro-
Rev. A | Page 17 of 52
ADV7174/ADV7179
ANALOG
VIDEO
EAV CODE
SAV CODE
C
b
C
r
C
b
8
0
0
0
F
F
F A A
F B B
A
B
8
0
0
0
C
r
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
Y
Y
Y
INPUT PIXELS
Y
Y
Y
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
4 CLOCK
4 CLOCK
NTSC/PAL M SYSTEM
(525 LlNES/60Hz)
268 CLOCK
1440 CLOCK
1440 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
280 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 20. Timing Mode 0 (Slave Mode)
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
H
V
F
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
V
ODD FIELD
EVEN FIELD
F
Figure 21. Timing Mode 0 (NTSC Master Mode)
Rev. A | Page 18 of 52
ADV7174/ADV7179
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
318
334
335
336
309
310
311
312
313
314
315
316
317
319
320
H
V
F
ODD FIELD
EVEN FIELD
Figure 22. Timing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 23. Timing Mode 0 Data Transitions (Master Mode)
Rev. A | Page 19 of 52
ADV7174/ADV7179
HSYNC
HSYNC BLANK
, FIELD
Mode 1: Slave Option
,
when
BLANK
is low indicates a new frame, i.e., vertical retrace.
BLANK
The
signal is optional. When the
input is
(Timing Register 0 TR0 = X X X X X 0 1 0)
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 1 is illustrated in
Figure 24 (NTSC) and Figure 25 (PAL).
In this mode, the ADV7174/ADV7179 accepts horizontal SYNC
and odd/even FIELD signals. A transition of the FIELD input
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 24. Timing Mode 1 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 25. Timing Mode 1 (PAL)
Rev. A | Page 20 of 52
ADV7174/ADV7179
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL).
HSYNC BLANK
, FIELD
Mode 1: Master Option
,
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
HSYNC BLANK
Figure 26 illustrates the
,
, and FIELD for an
HSYNC
BLANK
input when
retrace. The
is low indicates a new frame, i.e., vertical
odd or even field transition relative to the pixel data.
BLANK
signal is optional. When the
input
HSYNC
FIELD
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Rev. A | Page 21 of 52
ADV7174/ADV7179
HSYNC
signal is optional. When the
disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in
Figure 27 (NTSC) and Figure 28 (PAL).
HSYNC VSYNC BLANK
Mode 2: Slave Option
,
,
transition when
BLANK
is high indicates the start of an even
BLANK
input is
field. The
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7174/ADV7179 accepts horizontal and
vertical SYNC signals. A coincident low transition of both and
VSYNC
VSYNC
inputs indicates the start of an odd field. A
low
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
Figure 27. Timing Mode 2 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
335
336
317
334
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 28. Timing Mode 2 (PAL)
Rev. A | Page 22 of 52
ADV7174/ADV7179
BLANK
HSYNC VSYNC BLANK
Mode 2: Master Option
,
,
input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC BLANK
VSYNC
illustrates the
field transition relative to the pixel data. Figure 30 illustrates the
HSYNC BLANK VSYNC
,
, and
for an even-to-odd
HSYNC
VSYNC
VSYNC
low transition when
and
inputs indicates the start of an odd field. A
HSYNC
,
, and
for an odd-to-even field
is high indicates the start
transition relative to the pixel data.
BLANK
of an even field. The
signal is optional. When the
HSYNC
VSYNC
BLANK
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PAL = 12 × CLOCK/2
NTSC = 16 × CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
Rev. A | Page 23 of 52
ADV7174/ADV7179
BLANK
HSYNC BLANK
, FIELD
Mode 3: Master/Slave Option
,
that is, vertical retrace. The
signal is optional. When the
BLANK
input is disabled, the ADV7174/ADV7179 automatically
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
blanks all normally blank lines as per CCIR-624. Mode 3 is
illustrated in Figure 31 (NTSC) and Figure 32 (PAL).
In this mode, the ADV7174/ADV7179 accepts or generates
horizontal SYNC and odd/even FIELD signals. A transition of
HSYNC
the FIELD input when
is high indicates a new frame,
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD EVEN FIELD
Figure 31. Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
318
334
335
336
309
310
311
312
314
315
316
317
319
320
313
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 32. Timing Mode 3 (PAL)
Rev. A | Page 24 of 52
ADV7174/ADV7179
1
1
0
1
0
1
A1
X
POWER-ON RESET
ADDRESS
CONTROL
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high-to-low transition on
SET UP BY
ALSB
RESET
the
pin. This initializes the pixel port so that the pixel
READ/WRITE
CONTROL
inputs, P7–P0, are selected. After reset, the ADV7174/ADV7179
is automatically set up to operate in NTSC mode. Subcarrier
frequency code 21F07C16H is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. With the exception of Bit MR44,
all bits in Mode Register 0 are set to Logic 0. Bit MR44 of Mode
Register 4 is set to Logic 1. This enables the 7.5 IRE pedestal.
0
1
WRITE
READ
Figure 33. ADV7174 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SCH PHASE MODE
SET UP BY
ALSB
The SCH phase is configured in default mode to reset every
four (NTSC) or eight (PAL) fields to avoid an accumulation of
SCH phase error over time. In an ideal system, 0 SCH phase
error would be maintained forever, but in reality, this is impossi-
ble to achieve due to clock frequency variations. This effect is
reduced by the use of a 32-bit DDS, which generates this SCH.
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 34. ADV7179 Slave Address
To control the various devices on the bus, the following protocol
must be followed: first, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDATA while SCLOCK remains high. This indicates that an
address/data stream will follow. All peripherals respond to the
Resetting the SCH phase every four or eight fields avoids the
accumulation of SCH phase error and results in very minor
SCH phase jumps at the start of the 4- or 8-field sequence.
Resetting the SCH phase should not be done if the video source
does not have stable timing or the ADV7174/ADV7179 is
configured in RTC mode (MR21 = 1 and MR22 = 1). Under
these conditions (unstable video), the subcarrier phase reset
should be enabled (MR22 = 0 and MR21 = 1), but no reset
applied. In this configuration, the SCH phase can never be reset,
which means that the output video can now track the unstable
input video. The subcarrier phase reset, when applied, resets the
SCH phase to Field 0 at the start of the next field, for example,
subcarrier phase reset applied in Field 5 (PAL) on the start of
the next field SCH phase is reset to Field 0.
W
start condition and shift the next eight bits (7-bit address + R/
bit). The bits transfer from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
Acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLOCK lines wait-
ing for the start condition and the correct transmitted address.
W
The R/ bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral. A Logic 1 on the LSB of the first byte
means that the master will read information from the peripheral.
MPU PORT DESCRIPTION
The ADV7174/ADV7179 supports a 2-wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
Two inputs, serial data (SDATA) and serial clock (SCLOCK),
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. The
ADV7174/ADV7179 has four possible slave addresses for both
read and write operations. These are unique addresses for each
device and are illustrated in Figure 33 and Figure 34. The LSB
sets either a read or write operation. Logic 1 corresponds to a
read operation, while Logic 0 corresponds to a write operation.
A 1 is set by setting the ALSB pin of the ADV7174/ ADV7179 to
Logic 0 or Logic 1.
The ADV7174/ADV7179 acts as a standard slave device on the
bus. The data on the SDATA pin is eight bits long, supporting
W
the 7-bit addresses plus the R/ bit. The ADV7174/ADV7179
has 26 subaddresses to enable access to the internal registers. It
therefore interprets the first byte as the device address and the
second byte as the starting subaddress. The subaddresses’ auto
increment allows data to be written to or read from the starting
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without having to update all the
registers. There is one exception. The subcarrier frequency
registers should be updated in sequence, starting with
Subcarrier Frequency Register 0. The auto increment function
should then be used to increment and access Subcarrier
Frequency Registers 1, 2, and 3. The subcarrier frequency
registers should not be accessed independently.
Rev. A | Page 25 of 52
ADV7174/ADV7179
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLOCK high period,
the user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7174/
ADV7179 cannot issue an acknowledge and returns to the idle
condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action is taken:
Figure 35 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 36 shows bus write and read sequences.
SDATA
SCLOCK
S
1–7
8
9
1
–7
8
9
1–7
DATA
8
9
P
START ADDR
ACK SUBADDRESS ACK
ACK
STOP
R/W
Figure 35. Bus Data Transfer
REGISTER ACCESSES
1. In read mode, the highest subaddress register contents
continues to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDATA line is not
pulled low on the ninth pulse.
2. In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no-acknowledge is issued by
the ADV7174/ADV7179, and the part returns to the idle
condition.
The MPU can write to or read from all of the ADV7174/
ADV7179 registers except the subaddress register, which is a
write-only register. The subaddress register determines which
register the next read or write operation accesses. All commu-
nications with the part through the bus start with an access to
the subaddress register. A read/write operation is performed
from to the target address, which then increments to the next
address until a stop command on the bus is performed.
WRITE
SEQUENCE
S
S
SLAVE ADDR A(S) SUB ADDR A(S)
LSB = 0
DATA
A(S)
A(S)
P
DATA
LSB = 1
READ
SEQUENCE
A(M)
A(M)
SLAVE ADDR A(S)
SUB ADDR A(S)
S
SLAVE ADDR A(S)
DATA
DATA
P
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 36. Write and Read Sequences
Rev. A | Page 26 of 52
ADV7174/ADV7179
REGISTER PROGRAMMING
This section describes the configuration of each register,
including the subaddress register, mode registers, subcarrier
frequency registers, the subcarrier phase register, timing
registers, closed captioning extended data registers, closed
captioning data registers, and NTSC pedestal control registers.
Figure 37 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–SR6.
REGISTER SELECT (SR5–SR0)
These bits are set up to point to the required starting address.
SUBADDRESS REGISTER (SR7–SR0)
The communications register is an 8-bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The subaddress
register determines to/from which register the operation takes
place.
SR1
SR7
SR6
SR5
SR4
SR3
SR2
SR0
SR7 – SR6(000)
ZERO SHOULD BE WRITTEN
TO THESE BITS
ADV7174 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
POWER-UP
VALUES
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
RESERVED
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
00h
58h
00h
00h
10h
00h
00h
00h
00h
16h
7Ch
F0h
21h
00h
ADV7179 SUBADDRESS REGISTER
SR5 SR4 SR3 SR2 SR1 SR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
RESERVED
RESERVED
TIMING MODE REGISTER 0
TIMING MODE REGISTER 1
SUBCARRIER FREQUENCY REGISTER 0
SUBCARRIER FREQUENCY REGISTER 1
SUBCARRIER FREQUENCY REGISTER 2
SUBCARRIER FREQUENCY REGISTER 3
SUBCARRIER PHASE REGISTER
CLOSED CAPTIONING EXTENDED DATA BYTE 0
CLOSED CAPTIONING EXTENDED DATA BYTE 1
CLOSED CAPTIONING DATA BYTE 0
CLOSED CAPTIONING DATA BYTE 1
NTSC PEDESTAL CONTROL REGISTER 0/
PAL TTX CONTROL REGISTER 0
NTSC PEDESTAL CONTROL REGISTER 1/
PAL TTX CONTROL REGISTER 1
CLOSED CAPTIONING EXTENDED DATA BYTE 0 00h
CLOSED CAPTIONING EXTENDED DATA BYTE 1 00h
CLOSED CAPTIONING DATA BYTE 0
CLOSED CAPTIONING DATA BYTE 1
NTSC PEDESTAL CONTROL REGISTER 0/
PAL TTX CONTROL REGISTER 0
NTSC PEDESTAL CONTROL REGISTER 1/
PAL TTX CONTROL REGISTER 1
NTSC PEDESTAL CONTROL REGISTER 2/
PAL TTX CONTROL REGISTER 2
NTSC PEDESTAL CONTROL REGISTER 3/
PAL TTX CONTROL REGISTER 3
CGMS_WSS_0
CGMS_WSS_1
CGMS_WSS_2
TELETEXT REQUEST CONTROL REGISTER
RESERVED
RESERVED
00h
00h
00h
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
00h
00h
00h
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
0
1
NTSC PEDESTAL CONTROL REGISTER 2/
PAL TTX CONTROL REGISTER 2
NTSC PEDESTAL CONTROL REGISTER 3/
PAL TTX CONTROL REGISTER 3
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
CGMS_WSS_0
CGMS_WSS_1
CGMS_WSS_2
TELETEXT REQUEST CONTROL REGISTER
RESERVED
RESERVED
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
MACROVISION REGISTERS
Figure 37. Subaddress Register Map
Rev. A | Page 27 of 52
ADV7174/ADV7179
MODE REGISTER 0 (MR0)
Bits:
Address:
MR07 – MR00
SR4–SR0 = 00H
Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
OUTPUT VIDEO
STANDARD SELECTION
CHROMA FILTER SELECT
MR06 MR05
MR07
MR01 MR00
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.3 MHz LOW-PASS FILTER
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, and I)
PAL (M)
0.65 MHz LOW-PASS FILTER
1.0 MHz LOW-PASS FILTER
2.0 MHz LOW-PASS FILTER
RESERVED
CIF
QCIF
RESERVED
LUMA FILTER SELECT
MR03 MR02
RESERVED
MR04
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
0
LOW-PASS FILTER (NTSC)
LOW-PASS FILTER (PAL)
NOTCH FILTER (NTSC)
NOTCH FILTER (PAL)
EXTENDED MODE
CIF
1
0
1
0
1
0
1
QCIF
RESERVED
Figure 38. Mode Register 0
Table 9. MR0 Bit Description
Bit Name
Bit No.
Description
Output Video Standard
Selection
MR01–MR00
These bits are used to set up the ENCODE mode. The ADV7174/ADV7179 can be set up to
output NTSC, PAL (B/D/G/H/I), and PAL (M and N) standard video.
PAL M is available on the ADV7174 only.
Luminance Filter Control
MR02–MR04
These bits specify which luminance filter is to be selected. The filter selection is made
independent of whether PAL or NTSC is selected.
Chrominance Filter Control MR05–MR07
These bits select the chrominance filter. A low-pass filter can be selected with a choice of
cutoff frequencies 0.65 MHz, 1.0 MHz, 1.3 MHz, or 2 MHz, along with a choice of CIF or QCIF
filters.
Rev. A | Page 28 of 52
ADV7174/ADV7179
MODE REGISTER 1 (MR1)
Bits:
MR17–MR10
Address:
SR4–SR0 = 01H
Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to.
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
DAC A
CONTROL
CLOSED CAPTIONING
FIELD SELECTION
RESERVED
MR16
1 SHOULD BE
WRITTEN TO
THIS BIT
MR12
MR11
0
1
NORMAL
POWER-DOWN
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
MR17
DAC B
CONTROL
DAC C
CONTROL
INTERLACE
CONTROL
MR15
MR13
MR10
0
1
NORMAL
POWER-DOWN
0
1
NORMAL
POWER-DOWN
0
1
INTERLACED
NONINTERLACED
0
1
DISABLE
ENABLE
Figure 39. Mode Register 1
Table 10. MR1 Bit Description
Bit Name
Bit No.
Description
Interlace Control
MR10
This bit is used to set up the output to interlaced or noninterlaced mode. Power-down mode
is relevant only when the part is in composite video mode.
Closed Captioning Field
Selection
MR12–MR11
These bits control the fields on which closed captioning data is displayed; closed captioning
information can be displayed on an odd field, even field, or both fields.
DAC Control
MR16–MR15
and MR13
These bits can be used to power down the DACs. Power-down can be used to reduce the
power consumption of the ADV7174/ADV7179 if any of the DACs are not required in the
application.
Reserved
Color Bar Control
MR14
MR17
A Logic 1 must be written to this register.
This bit can be used to generate and output an internal color bar test pattern. The color bar
configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that
when color bars are enabled, the ADV7174/ADV7179 is configured in a master timing mode.
Rev. A | Page 29 of 52
ADV7174/ADV7179
MODE REGISTER 2 (MR2)
Bits:
MR27–MR20
Address:
SR4–SR0 = 02H
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can
be read from as well as written to.
MR26
MR25
MR24
MR23
MR22
MR21
MR27
MR20
CHROMINANCE
CONTROL
GENLOCK CONTROL
MR22 MR21
LOW POWER MODE
MR24
MR26
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
0
1
ENABLE COLOR
DISABLE COLOR
0
1
DISABLE
ENABLE
1
1
ENABLE RTC PIN
MR27
BURST
CONTROL
ACTIVE VIDEO LINE
DURATION
SQUARE PIXEL
CONTROL
MR20
RESERVED
MR23
MR25
0
1
ENABLE BURST
DISABLE BURST
0
1
DISABLE
ENABLE
0
1
720 PIXELS
710 PIXELS/702 PIXELS
Figure 40. Mode Register 2
Table 11. MR2 Bit Description
Bit Name
Bit No.
Description
Square Pixel Control
MR20
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a
24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Genlock Control
MR22–MR21
These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1
configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0
following a low-to-high transition on the SCRESET/RTC pin. Setting MR22 to Logic 1 configures
the SCRESET/RTC pin as a real-time control input.
Active Video Line Duration MR23
This bit switches between two active video line durations. A 0 selects CCIR REC601 (720 pixels
PAL/NTSC), and a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC
and 702 pixels PAL).
Chrominance Control
Burst Control
Low Power Mode
MR24
MR25
MR26
This bit enables the color information to be switched on and off the video output.
This bit enables the burst information to be switched on and off the video output.
This bit enables the lower power mode of the ADV7174/ADV7179. This reduces the DAC
current by 45%.
Reserved
MR27
A Logic 0 must be written to this bit.
Rev. A | Page 30 of 52
ADV7174/ADV7179
MODE REGISTER 3 (MR3)
Bits:
MR37–MR30
Address:
SR4–SR0 = 03H
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37
VBI_OPEN
TTXREQ BIT
MODE CONTROL
CHROMA OUTPUT
SELECT
MR30
MR31
MR32
MR36
MR34
0
1
DISABLE
ENABLE
RESERVED
0
1
NORMAL
BIT REQUEST
0
1
DISABLE
ENABLE
INPUT DEFAULT
COLOR
TELETEXT
ENABLE
DAC OUTPUT
DAC B
MR37
MR35
MR33
DAC A
DAC C
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
0
1
COMPOSITE
GREEN/LUMA/Y
BLUE/COMP/Pb RED/CHROMA/Pr
BLUE/COMP/Pb RED/CHROMA/Pr
Figure 41. Mode Register 3
Table 12. MR3 Bit Description
Bit Name
Bit No.
Description
Revision Code
VBI Open
MR30–MR31
MR32
These bits are read-only and indicate the revision of the device.
This bit determines whether or not data in the vertical blanking interval (VBI) is output to
the analog outputs or blanked. VBI data insertion is not available in Slave Mode 0. Also,
BLANK
BLANK
when both
input control and VBI open are enabled,
input control has
priority, i.e., VBI data insertion will not work.
DAC Output
MR33
MR34
This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A
complete list of all DAC output configurations is shown in Table 13.
With this active high bit it is possible to output an extra chrominance signal C, on DAC A
in any configuration that features a CVBS signal.
Chroma Output Select
Teletext Enable
TTXREQ Bit Mode Control
MR35
MR36
This bit must be set to 1 to enable Teletext data insertion on the TTX pin.
This bit enables switching of the Teletext request signal from a continuous high signal
(MR36 = 0) to a bitwise request signal (MR36 = 1).
Input Default Color
MR37
This bit determines the default output color from the DACs for zero input pixel data (or
disconnected). A Logic 0 means that the color corresponding to 00000000 is displayed. A
Logic 1 forces the output color to black for 00000000 pixel input video data.
Table 13. DAC Output Configuration Matrix
MR34
MR40
MR41
MR33
DAC A
DAC B
DAC C
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
CVBS
CVBS
CVBS
CVBS
B
B
Pb
Pb
C
C
C
C
R
CVBS: Composite Video Baseband Signal
Y: Luminance Component Signal (For YPbPr or Y/C Mode)
C: Chrominance Signal (For Y/C Mode)
Pb: ColorComponent Signal (For YPbPr Mode)
Pr: Color Component Signal (For YPbPr Mode)
R: RED Component Video (For RGB Mode)
G: GREEN Component Video (For RGB Mode)
B: BLUE Component Video (For RGB Mode)
R
Pr
Pr
C
C
C
C
R
R
Pr
Pr
Each DAC can be powered on or off individually
See MR1 Description and Figure 39.
Rev. A | Page 31 of 52
ADV7174/ADV7179
MODE REGISTER 4 (MR4)
Bits:
MR47–MR40
Address:
SR4–SR0 = 04H
Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47
SLEEP MODE
CONTROL
PEDESTAL
CONTROL
RGB SYNC
OUTPUT SELECT
MR42
MR40
MR46
MR44
0
1
DISABLE
ENABLE
0
1
YC OUTPUT
RGB/YPbPr OUTPUT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
MR47
(0)
ACTIVE VIDEO
FILTER CONTROL
RGB/YUV
CONTROL
VSYNC_3H
MR43
MR45
MR41
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
0
1
RGB OUTPUT
YPbPr OUTPUT
Figure 42. Mode Register 4
Table 14. MR4 Bit Description
Bit Name
Bit No.
MR40
MR41
MR42
Description
Output Select
RGB/YPbPr Control
RGB Sync
This bit specifies if the part is in composite video or RGB/YPbPr mode.
This bit enables the output from the RGB DACs to be set to YPbPr output video standard.
This bit is used to set up the RGB outputs with the sync information encoded on all RGB
outputs.
VSYNC_3H
MR43
When this bit is enabled (1) in slave mode, it is possible to drive the VSYNC active low
input for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in
master mode, the ADV7174/ADV7179 outputs an active low VSYNC signal for three lines
in NTSC mode and 2.5 lines in PAL mode.
Pedestal Control
MR44
MR45
This bit specifies whether a pedestal is to be generated on the NTSC composite video
signal. This bit is invalid if the ADV7174/ ADV7179 is configured in PAL mode.
This bit controls the filter mode applied outside the active video portion of the line. This
filter ensures that the sync rise and fall times are always on spec regardless of which luma
filter is selected. A Logic 1 enables this mode.
Active Video Filter Control
Sleep Mode Control
MR46
When this bit is set (1), sleep mode is enabled. With this mode enabled, the
ADV7174/ADV7179 power consumption is reduced to typically 200 nA. The I2C registers
can be written to and read from when the ADV7174/ADV7179 is in sleep mode. If MR46 is
set to a (0) when the device is in sleep mode, the ADV7174/ADV7179 comes out of sleep
mode and resumes normal operation. Also, if the RESET signal is applied during sleep
mode, the ADV7174/ADV7179 comes out of sleep mode and resumes normal operation.
Reserved
MR47
A Logic 0 should be written to this bit.
Rev. A | Page 32 of 52
ADV7174/ADV7179
TIMING MODE REGISTER 0 (TR0)
Bits:
TR07–TR00
Address:
SR4–SR0 = 07H
Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
BLANK INPUT
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02
TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
1
8 BIT
FORBIDDEN
0
0
1
1
0
1
0
1
MODE 0
MODE 1
MODE 2
MODE 3
74ns DELAY
148ns DELAY
222ns DELAY
Figure 43. Timing Register 0
Table 15. TR0 Bit Description
Bit Name
Bit No.
Description
Master/Slave Control
Timing Mode Selection
TR00
TR02–TR01
This bit controls whether the ADV7174/ADV7179 is in master or slave mode.
These bits control the timing mode of the ADV7174/ADV7179. These modes are
described in more detail in the 3.3 V Timing Specifications table.
BLANK Input Control
Luma Delay
TR03
This bit controls whether the BLANK input is used when the part is in slave mode.
TR05–TR04
These bits control the addition of a luminance delay. Each bit represents a delay of
74 ns.
Pixel Port Control
TR06
TR07
This bit is used to set the pixel port to accept 8-bit or YCrCb data on Pins P7–P0.
0 must be written here.
Toggling the TR07 from low to high and to low again resets the internal timing
counters. This bit should be toggled after power-up, reset, or changing to a new
timing mode.
Timing Register Reset
Rev. A | Page 33 of 52
ADV7174/ADV7179
TIMING MODE REGISTER 1 (TR1)
Bits:
TR17–TR10
Address:
SR4–SR0 = 08H
Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register
can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR17
TR16
TR15
TR14
TR13
TR12
TR11
TR10
HSYNC WIDTH
HSYNC TO PIXEL
DATA ADJUST
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
HSYNC TO
FIELD/VSYNC DELAY
T
TR11 TR10
A
TR17 TR16
TR13 TR12
T
0
0
1
1
0
1
0
1
1 × T
4 × T
B
PCLK
PCLK
T
TR15 TR14
C
0
0
1
1
0
1
0
1
0 × T
1 × T
2 × T
3 × T
0
0
1
1
0
1
0
1
0 × T
4 × T
8 × T
PCLK
PCLK
PCLK
PCLK
x
x
0
1
T
T
B
16 × T
PCLK
PCLK
PCLK
PCLK
128 × T
+ 32µs
B
PCLK
16 × T
PCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 × T
4 × T
PCLK
PCLK
16 × T
PCLK
128 × T
PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
T
A
HSYNC
T
T
C
B
FIELD/VSYNC
Figure 44. Timing Register 1
Table 16. TR1 Bit Description
Bit Name Bit No.
TR11–TR10 These bits adjust the HSYNC pulse width.
Description
HSYNC
Width
HSYNC
Delay
VSYNC
to FIELD/
TR13–TR12 These bits adjust the position of the HSYNC output relative to the FIELD/VSYNC output.
HSYNC
Edge Delay
TR15–TR14 When the ADV7174/ADV7179 is in Timing Mode 1, these bits adjust the position of the HSYNC
output relative to the FIELD output rising edge.
to FIELD Rising
VSYNC
TR15–TR14 When the ADV7174/ADV7179 is configured in Timing Mode 2, these bits adjust the VSYNC
pulse width.
Width
HSYNC
TR17–TR16 This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb
components to be swapped. This adjustment is available in both master and slave timing modes.
to Pixel Data Adjust
Rev. A | Page 34 of 52
ADV7174/ADV7179
SUBCARRIER FREQUENCY REGISTERS 3–0
Bits:
FSC3–FSC0
Address:
SR4–SR00 = 09H–0CH
These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following
equation:
No.of Subcarrier Frequency Values in One Line of Video Line
× 232
*
No.of 27 MHz Clock Cycles in OneVideo Line
* Rounded to the nearest integer.
For example, in NTSC mode,
227.5
1716
Subcarrier Frequency Value =
×232 = 569408542d = 21F07C1Eh
Note that on power-up, FSC Register 0 is set to 16h. A value of 1E as derived above is recommended.
Program as
FSC Register 0: 1EH
FSC Register 2: 7CH
FSC Register 3: F0H
FSC Register 4: 21H
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER
FREQUENCY
REG 3
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
SUBCARRIER
FREQUENCY
REG 2
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
SUBCARRIER
FREQUENCY
REG 1
FSC14
FSC6
FSC15
FSC7
FSC13 FSC12 FSC11 FSC10 FSC9
FSC8
FSC0
SUBCARRIER
FREQUENCY
REG 0
FSC5
FSC4
FSC3 FSC2 FSC1
Figure 45. Subcarrier Frequency Register
SUBCARRIER PHASE REGISTER
Bits:
Address:
FP7–FP0
SR4–SR0 = 0DH
This 8-bit-wide register is used to set up the subcarrier phase. Each bit represents 1.41°. For normal operation, this register is set to 00H.
CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
Bits:
CED15–CED0
Address:
SR4–SR0 = 0EH–0FH
These 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. Figure 46 shows how the high and
low bytes are set up in the registers.
CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
Figure 46. Closed Captioning Extended Data Register
BYTE 1
BYTE 0
Rev. A | Page 35 of 52
ADV7174/ADV7179
CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
Bits:
CCD15–CCD0
Subaddress:
SR4–SR0 = 10H–11H
These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes
are set up in the registers.
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0
Figure 47. Closed Captioning Data Register
BYTE 1
BYTE 0
NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
Bits:
Subaddress:
PCE15–PCE0, PCO15–PCO0/TXE15–TXE0, TXO15–TXO0
SR4–SR0 = 12H–15H
These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for
both odd and even fields. Figure 48 and Figure 49 show the four control registers. A Logic 1 in any of the bits of these registers has the
effect of turning the pedestal off on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of
turning Teletext on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO7
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
PCO6 PCO5
PCO4
PCO3 PCO2
PCO1
PCO0
FIELD 1/3
FIELD 1/3
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
FIELD 2/4
FIELD 2/4
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9
PCE8
Figure 48. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXO7 TXO6 TXO5 TXO4 TXO3 TXO2 TXO1 TXO0
FIELD 1/3
FIELD 1/3
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXO15 TXO14 TXO13 TXO12 TXO11 TXO10 TXO9 TXO8
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
TXE7 TXE6 TXE5 TXE4 TXE3 TXE2 TXE1 TXE0
FIELD 2/4
FIELD 2/4
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
TXE15 TXE14 TXE13 TXE12 TXE11 TXE10
TXE9
TXE8
Figure 49. Teletext Control Registers
Rev. A | Page 36 of 52
ADV7174/ADV7179
TELETEXT REQUEST CONTROL REGISTER (TC07)
Bits:
TC07–TC00
Address:
SR4–SR0 = 19H
Teletext control register is an 8-bit-wide register (see Figure 50).
Table 17. Teletext Request Control Register
Bit Name
Bit No.
Description
TTXREQ Rising Edge Control
TC07–TC04
These bits control the position of the rising edge of TTXREQ. It can be
programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see
Figure 50).
TTXREQ Falling Edge Control
TC03–TC00
These bits control the position of the falling edge of TTXREQ. It can be
programmed from zero CLOCK cycles to a max of 15 CLOCK cycles. This controls
the active window for Teletext data. Increasing this value reduces the amount of
Teletext bits below the default of 360. If Bits TC03–TC00 are 00H when Bits TC07–
TC04 are changed, the falling edge of TTXREQ tracks that of the rising edge, i.e.,
the time between the falling and rising edge remains constant (see Figure 49).
CGMS_WSS REGISTER 0 (C/W0)
Bits:
Address:
C/W07–C/W00
SR4–SR0 = 16H
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51 shows the operations under the control of this register.
TC06
TC05
TC04
TC03
TC02
TC01
TC00
TC07
TTXREQ RISING EDGE CONTROL
TC07 TC06 TC05 TC04
TTXREQ FALLING EDGE CONTROL
TC03 TC02 TC01 TC00
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
0
0
"
1
1
0
0
"
1
1
0
0
"
1
1
0
1
"
0
1
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
Figure 50. Teletext Control Register
C/W07
C/W06
C/W05
C/W04
C/W03
C/W02
C/W01
C/W00
WIDE SCREEN
SIGNAL CONTROL
CGMS ODD FIELD
CONTROL
C/W03 – C/W00
C/W07
C/W05
CGMS DATA BITS
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
CGMS CRC CHECK
CONTROL
CGMS EVEN FIELD
CONTROL
C/W06
C/W04
0
1
DISABLE
ENABLE
0
1
DISABLE
ENABLE
Figure 51. CGMS_WSS Register 0
Table 18. C/W0 Bit Description
Bit Name
Bit No.
Description
CGMS Data Bits
C/W03–C/W00
These four data bits are the final four bits of the CGMS data output stream. Note it is
CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
C/W04
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check
sequence, are calculated internally by the ADV7174/ADV7179. If this bit is disabled (0), the
CRC values in the register are output to the CGMS data stream.
CGMS CRC Check Control
CGMS Odd Field Control
CGMS Even Field Control
WSS Control
C/W05
C/W06
C/W07
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
When this bit is set (1), wide screen signaling is enabled. Note this is only valid in PAL mode.
Rev. A | Page 37 of 52
ADV7174/ADV7179
CGMS_WSS REGISTER 1 (C/W1)
Bits:
Address :
C/W17–C/W10
SR4–SR0 = 17H
CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register.
C/W17
C/W16
C/W15
C/W14
C/W13
C/W12
C/W11
C/W10
C/W17 – C/W16
CGMS DATA BITS
C/W15 – C/W10
CGMS/WSS DATA BITS
Figure 52. CGMS_WSS Register 1
Table 19. C/W1 Bit Description
Bit Name
Bit No.
Description
CGMS/WSS Data Bits
C/W15–C/W10
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these bits
are CGMS data. In PAL mode, these bits are WSS data.
CGMS Data Bits
C/W17–C/W16
These bits are CGMS data bits only.
CGMS_WSS REGISTER 2 (C/W2)
Bits:
C/W27–C/W20
Address:
(SR4–SR00) = 18H
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 53 shows the operations under the control of this register.
C/W27
C/W26
C/W25
C/W24
C/W23
C/W22
C/W21
C/W20
C/W27 – C/W20
CGMS/WSS DATA BITS
Figure 53. CGMS_WSS Register 2
Table 20. C/W2 Bit Description
Bit Name
Bit No.
C/W27–C/W20
Description
CGMS/WSS Data Bits
These bit locations are shared by CGMS data and WSS data. In NTSC mode, these
bits are CGMS data. In PAL mode, these bits are WSS data.
Rev. A | Page 38 of 52
ADV7174/ADV7179
APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7174/ADV7179 is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be
applied to the system-level design so that high speed, accurate
performance is achieved. Figure 54 shows the analog interface
between the device and monitor.
POWER PLANES
The ADV7174/ADV7179 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). This power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. This bead should be located within 3 inches of the
ADV7174/ADV7179.
The metallization gap separating the device power plane and
board power plane should be as narrow as possible to minimize
the obstruction to the flow of heat from the device into the
general board.
The layout should be optimized for lowest noise on the
ADV7174/ADV7179 power and ground lines by shielding the
digital inputs and providing good decoupling. The lead length
between groups of VAA and GND pins should be minimized to
reduce inductive ringing.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7174/ADV7179 power pins and voltage
reference circuitry.
GROUND PLANES
The ground plane should encompass all ADV7174/ADV7179
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7174/ADV7179, the analog output traces,
and all the digital signal traces leading up to the ADV7174/
ADV7179. The ground plane is the board’s common ground
plane.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane unless they can be
arranged so that the plane-to-plane noise is common mode.
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1
µF
0.01µF
L1
(FERRITE BEAD)
3.3 V (V
)
AA
3.3V (V
AA
)
3.3 V
(V
3.3 V (V
)
AA
)
CC
33µF
10µ
F
0.1µF
0.1µF
GND
V
AA
23
30
COMP
V
REF
ADV7174/ADV7179
3–5, 35–39
24
DAC C
3.3 V (V
)
AA
P7–P0
75Ω
75Ω
75Ω
4k
Ω
28
29
32
13
DAC B
DAC A
SCRESET/RTC
HSYNC
RESET
100nF
UNUSED
INPUTS
SHOULD BE
GROUNDED
14 FIELD/VSYNC
3.3 V (V
)
CC
3.3 V (V
)
3.3 V (V )
CC
CC
15
BLANK
100k
Ω
Ω
20
34
33
1
RESET
TTX
5kΩ
5kΩ
TTX
100
Ω
Ω
21
22
31
SCLOCK
SDATA
TTXREQ
MPU BUS
100
TTXREQ
CLOCK
100k
R
SET
3.3 V (V
)
AA
ALSB
16
GND
150
Ω
TELETEXT PULL-UP AND
PULL-DOWN RESISTORS
SHOULD ONLY BE USED
IF THESE PINS ARE NOT
CONNECTED
10k
Ω
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
Figure 54. Recommended Analog Circuit Layout
Rev. A | Page 39 of 52
ADV7174/ADV7179
ANALOG SIGNAL INTERCONNECT
SUPPLY DECOUPLING
The ADV7174/ADV7179 should be located as close to the
output connectors as possible to minimize noise pickup and
reflections due to impedance mismatch.
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7174/ADV7179 must have at least one
0.1 µF decoupling capacitor to GND. These capacitors should be
placed as close to the device as possible.
The video output signals should overlay the ground plane, not
the analog power plane, to maximize the high frequency power
supply rejection.
Digital inputs, especially pixel data inputs and clocking signals,
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
It is important to note that while the ADV7174/ADV7179
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to
reducing power supply noise and consider using a 3-terminal
voltage regulator for supplying power to the analog power
plane.
For best performance, the outputs should each have a 75 Ω load
resistor connected to GND. These resistors should be placed as
close as possible to the ADV7174/ADV7179 to minimize
reflections.
DIGITAL SIGNAL INTERCONNECT
The ADV7174/ADV7179 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
The digital inputs to the ADV7174/ADV7179 should be isolated
as much as possible from the analog outputs and other analog
circuitry. Also, these input signals should not overlay the analog
power plane.
The circuit in Figure 55 can be used to generate a 13.5 MHz
HSYNC
waveform using the 27 MHz clock and the
pulse. This
waveform is guaranteed to produce the 13.5 MHz clock in
synchronization with the 27 MHz clock. This 13.5 MHz clock
can be used if the 13.5 MHz clock is required by the MPEG
decoder. This guarantees that the Cr and Cb pixel information
is input to the ADV7174/ADV7179 in the correct sequence.
Due to the high clock rates involved, long clock lines to the
ADV7174/ADV7179 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC) and not to the
analog power plane.
Note that the exposed metal paddle on the bottom side of the
LFCSP package must be soldered to PCB ground for proper
heat dissipation and also for electrical noise and mechanical
strength benefits.
D
Q
13.5MHz
D
Q
CLOCK
HSYNC
CK
CK
Figure 55. Circuit to Generate 13.5 MHz
Rev. A | Page 40 of 52
ADV7174/ADV7179
APPENDIX 2—CLOSED CAPTIONING
ADV7174/ADV7179. All pixel inputs are ignored during Lines
21 and 284. FCC Code of Federal Regulations (CFR) 47 Section
15.119 and EIA-608 describe the closed captioning information
for Lines 21 and 284.
The ADV7174/ADV7179 supports closed captioning, conform-
ing to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of even fields.
The ADV7174/ADV7179 uses a single buffering method. This
means that the closed captioning buffer is only one byte deep,
therefore there will be no frame delay in outputting the closed
captioning data unlike other 2-byte deep buffering systems. The
data must be loaded at least one line before (Line 20 or Line 283)
it is outputted on Line 21 and Line 284. A typical implementation
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency-locked and phase-locked to the caption data. After
the clock run-in signal, the blanking level is held for 2 data bits
and is followed by a Logic 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, 7 data bits, and 1 odd
parity bit. The data for these bytes is stored in closed captioning
Data Registers 0 and 1.
VSYNC
of this method is to use
to interrupt a microprocessor,
which in turn loads the new data (two bytes) every field. If no
new data is required for transmission, you must insert zeros in
both the data registers; this is called nulling. It is also important
to load control codes, all of which are double bytes, on Line 21,
or a TV cannot recognize them. If you have a message such as
“Hello World,” which has an odd number of characters, it is
important to pad it out to an even number to get the end of the
caption 2-byte control code to land in the same field.
The ADV7174/ADV7179 also supports the extended closed
captioning operation, which is active during even fields, and is
encoded on scan Line 284. The data for this operation is stored
in closed captioning extended Data Registers 0 and 1.
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are automatically generated by the
10.5 ± 0.25µs
12.91µs
7 CYCLES
OF 0.5035 MHz
(CLOCK RUN-IN)
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
D0–D6
D0–D6
50 IRE
40 IRE
BYTE 1
BYTE 0
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
33.764µs
27.382µs
Figure 56. Closed Captioning Waveform (NTSC)
Rev. A | Page 41 of 52
ADV7174/ADV7179
APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23
The ADV7174/ADV7179 supports the CGMS, conforming to
the standard. CGMS data is transmitted on Line 20 of the odd
fields and on Line 283 of the even fields. Bits C/W05 and
C/W06 control whether or not CGMS data is output on odd
and even fields. CGMS data can only be transmitted when the
ADV7174/ ADV7179 is configured in NTSC mode. The CGMS
data is 20 bits long, the function of each of these bits is as shown
below. The CGMS data is preceded by a reference pulse of the
same amplitude and duration as a CGMS bit (see Figure 57).
The bits are output from the configuration registers in the
following order: C/W00 = C16, C/W01 = C17, C/W02 = C18,
C/W03 = C19, C/W10 = C8, C/ W11 = C9, C/W12 = C10,
C/W13 = C11, C/W14 = C12, C/ W15 = C13, C/W16 = C14,
= C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If
Bit C/W04 is set to a Logic 1, the last six bits, C19–C14, which
comprise the 6-bit CRC check sequence, are calculated
automatically on the ADV7174/ADV7179 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial X6 + X + 1 with a preset value of 111111. If
C/W04 is set to a Logic 0, all 20 bits (C0–C19) are directly
output from the CGMS registers (no CRC is calculated; it must
be calculated by the user).
FUNCTION OF CGMS BITS
Word 0 –6 Bits
Word 1 –4 Bits
Word 2 –4 Bits
CRC –6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111)
Table 21. Bit 1–Bit 14
Word
Bit
Function
Word 0
1
0
B1
B2
B3
Aspect Ratio
Display Format
Undefined
16:9
Letterbox
4:3
Normal
B4, B5, B6
B7, B8, B9, B10
B11, B12, B13, B14
Identification information about video and other signals, for example, audio
Identification signal incidental to Word 0
Identification signal and information incidental to Word 0
Word 1
Word 2
100 IRE
CRC SEQUENCE
C17 C18 C19
REF
70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
C13 C14 C15 C16
0 IRE
49.1µs ± 0.5µs
–40 IRE
11.2µs
2.235µs ± 20ns
Figure 57. CGMS Waveform Diagram
Rev. A | Page 42 of 52
ADV7174/ADV7179
APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
following order: C/W20 = W0, C/W21 = W1, C/W22 = W2,
C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6,
C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10,
C/W13 = W11, C/W14 = W12, C/W15 = W13. If the Bit C/W07
is set to a Logic 1, it enables the WSS data to be transmitted on
Line 23. The latter portion of Line 23 (42.5 µs from the falling
The ADV7174/ADV7179 supports WSS, conforming to the
standard. WSS data is transmitted on Line 23. WSS data can
only be transmitted when the ADV7174/ ADV7179 is
configured in PAL mode. The WSS data is 14 bits long, the
function of each of these bits is as shown below. The WSS data
is preceded by a run-in sequence and a start code (see Figure 58).
HSYNC
edge of
) is available for the insertion of video.
The bits are output from the configuration registers in the
FUNCTION OF WSS BITS
Table 22. Bit 0–Bit 2 Bit 3 is the odd parity check of Bit 0–Bit 2
Table 23. Bit 4–Bit 7
Aspect
Ratio
Bit
Value Description
B0
B1
B2
B3
Format
Position
B4
0
1
0
1
0
1
Camera Mode
Film Mode
0
0
0
1
4:3
Full
Format
Not
Applicable
Center
Top
Center
Top
B5
B6
Standard Coding
Motion Adaptive Color Plus
No Helper
Modulated Helper
Reserved
1
0
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
1
1
14:9
14:9
16:9
16:9
>16:9
14:9
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full
Format
Not
B7
B8
Center
Center
0
1
No Teletext Subtitles
Teletext Subtitles
No Open Subtitles
Subtitles in Active Image Area
Subtitles out of Active Image Area
Reserved
No Surround Sound Information
Surround Sound Mode
Reserved
B9–B10
0, 0
1, 0
0, 1
1, 1
0
1
1
1
0
16:9
Not
Applicable Applicable
B11
1
B12
B13
Reserved
500mV
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0µs
38.4µs
42.5µs
Figure 58. WSS Waveform Diagram
Rev. A | Page 43 of 52
ADV7174/ADV7179
APPENDIX 5—TELETEXT
TELETEXT INSERTION
TELETEXT PROTOCOL
tPD is the time needed by the ADV7174/ADV7179 to interpolate
input data on TTX and insert it onto the CVBS or Y outputs,
such that it appears tSYNTTXOUT = 10.2 µs after the leading edge of
the horizontal signal. Time TTXDEL is the pipeline delay time by
the source that is gated by the TTXREQ signal in order to
deliver TTX data.
The relationship between the TTX bit clock (6.9375 MHz) and
the system clock (27 MHz) for 50 Hz is
⎛
⎜
⎞
⎟
27 MHz
= 6.75MHz
4
⎝
⎠
(
6.9375×106 6.75×106
)
=1.027777
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 µs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable pipe-
line delays.
Thus, 37 TTX bits correspond to 144 clocks (27 MHz) and each
bit has a width of almost four clock cycles. The ADV7174/
ADV7179 uses an internal sequencer and variable phase inter-
polation filter to minimize the phase jitter and thus generate a
band-limited signal that can be output on the CVBS and Y
outputs.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext standard
PAL-WST) Teletext bits at a text data rate of 6.9375 Mbits/s.
This is achieved by setting TC03–TC00 to 0. The insertion
window is not open if the Teletext enable bit (MR35) is set to 0.
At the TTX input, the bit duration scheme repeats after every 37
TTX bits or 144 clock cycles. The protocol requires that TTX
Bits 10, 19, 28, and 37 are carried by three clock cycles and all
other bits by four clock cycles. After 37 TTX bits, the next bits
with three clock cycles are 47, 56, 65, and 74. This scheme holds
for all following cycles of 37 TTX bits until all 360 TTX bits are
completed. All Teletext lines are implemented in the same way.
Individual control of Teletext lines is controlled by Teletext
setup registers.
45 BYTES (360 BITS) – PAL
ADDRESS AND DATA
TELETEXT VBI LINE
RUN-IN CLOCK
Figure 59. Teletext VBI Line
tSYNTTXOUT
CVBS/Y
HSYNC
tPD
tPD
10.2µs
TTX
DATA
TTX
DEL
TTXREQ
PROGRAMMABLE PULSE EDGES
TTX
ST
tSYNTTXOUT = 10.2
µs
tPD = PIPELINE DELAY THROUGH ADV7174/ADV7179
TTX
DEL
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
Figure 60. Teletext Functionality
Rev. A | Page 44 of 52
ADV7174/ADV7179
APPENDIX 6—WAVEFORMS
NTSC WAVEFORMS (WITH PEDESTAL)
1268.1mV
1048.4mV
130.8 IRE
100 IRE
PEAK COMPOSITE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 61. NTSC Composite Video Levels
1048.4mV
100 IRE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
SYNC LEVEL
48.3mV
–40 IRE
Figure 62. NTSC Luma Video Levels
PEAK CHROMA
963.8mV
629.7mV (p-p)
286mV (p-p)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
335.2mV
0mV
Figure 63. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
387.5mV
331.4mV
SYNC LEVEL
–40 IRE
45.9mV
Figure 64. NTSC RGB Video Levels
Rev. A | Page 45 of 52
ADV7174/ADV7179
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
100 IRE
1289.8mV
1052.2mV
PEAK COMPOSITE
REF WHITE
714.2mV
0 IRE
338mV
52.1mV
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 65. NTSC Composite Video Levels
100 IRE
1052.2mV
REF WHITE
714.2mV
0 IRE
338mV
52.1mV
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 66. NTSC Luma Video Levels
PEAK CHROMA
978mV
694.9mV (p-p)
286mV (p-p)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
299.3mV
0mV
Figure 67. NTSC Chroma Video Levels
100 IRE
1052.2mV
REF WHITE
715.7mV
336.5mV
51mV
0 IRE
BLANK/BLACK LEVEL
SYNC LEVEL
–40 IRE
Figure 68. NTSC RGB Video Levels
Rev. A | Page 46 of 52
ADV7174/ADV7179
PAL WAVEFORMS
PEAK CHROMA
989.7mV
650mV
672mV (p-p)
300mV (p-p)
BLANK/BLACK LEVEL
PEAK CHROMA
317.7mV
0mV
Figure 69. PAL Composite Video Levels
REF WHITE
1047mV
696.4mV
350.7mV
50.8mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 70. PAL Luma Video Levels
PEAK CHROMA
989.7mV
672mV (p-p)
300mV (p-p)
650mV
BLANK/BLACK LEVEL
PEAK CHROMA
317.7mV
0mV
Figure 71. PAL Chroma Video Levels
REF WHITE
1050.2mV
698.4mV
351.8mV
51mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 72. PAL RGB Video Levels
Rev. A | Page 47 of 52
ADV7174/ADV7179
Pb Pr WAVEFORMS
+505mV
+334mV
+505mV
+423mV
+171mV
BETACAM LEVEL
BETACAM LEVEL
0mV
+82mV
0mV
0mV
0mV
–82mV
–171mV
–334mV
–423mV
–05mV
–505mV
Figure 73. NTSC 100% Color Bars, No Pedestal Pb Levels
Figure 76. NTSC 100% Color Bars, No Pedestal Pr Levels
+467mV
+309mV
+467mV
+391mV
+158mV
BETACAM LEVEL
BETACAM LEVEL
+76mV
0mV
0mV
0mV
0mV
–76mV
–158mV
–309mV
–391mV
–467mV
–467mV
Figure 74. NTSC 100% Color Bars with Pedestal Pb Levels
Figure 77. NTSC 100% Color Bars with Pedestal Pr Levels
+350mV
+232mV
+350mV
+293mV
+118mV
SMPTE LEVEL
+57mV
SMPTE LEVEL
0mV
0mV
0mV
0mV
–57mV
–118mV
–232mV
–293mV
–350mV
–350mV
Figure 75. PAL 100% Color Bars, Pb Levels
Figure 78. PAL 100% Color Bars, Pr Levels
Rev. A | Page 48 of 52
ADV7174/ADV7179
APPENDIX 7—OPTIONAL OUTPUT FILTER
0
If an output filter is required for the CVBS, Y, UV, chroma, and
RGB outputs of the ADV7174/ADV7179, the filter shown in
Figure 79 can be used. Plots of the filter characteristics are
shown in Figure 80. An output filter is not required if the
outputs of the ADV7174/ADV7179 are connected to most
analog monitors or analog TVs. However, if the output signals
are applied to a system where sampling is used (e.g., digital
TVs), then a filter is required to prevent aliasing.
10
20
30
40
50
60
70
80
22pF
DISPLAY DEVICE
1.8µH
FILTER I/P
Z
= 75Ω
0
100k
10M
FREQUENCY (Hz)
100M
1M
270pF
330pF
75Ω
75Ω
Figure 80. Output Filter Plot
Figure 79. Output Filter
Rev. A | Page 49 of 52
ADV7174/ADV7179
APPENDIX 8—RECOMMENDED REGISTER VALUES
switched off. In the examples shown, the timing mode is set to
The ADV7174/ADV7179 registers can be set depending on the
user standard required. The power-on reset values can be found
in Figure 37.
Mode 0 in slave format. TR02–TR00 of the Timing Register 0
control the timing modes. For a detailed explanation of each bit
in the command registers, refer to the Register Programming
section. TR07 should be toggled after setting up a new timing
mode. Timing Register 1 provides additional control over the
position and duration of the timing signals. In the examples,
this register is programmed in default mode.
The following examples give the various register formats for
several video standards. In each case, the output is set to compos-
ite output with all DACs powered up and with the input control
BLANK
disabled. Additionally, the burst and
color information
is enabled on the output, and the internal color bar generator is
Table 24. PAL B/D/G/H/I (FSC = 4.43361875 MHz)
Table 25. PAL N (FSC = 4.43361875 MHz)
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Data
05H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Data
05H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Telext Request Control Register
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
Rev. A | Page 50 of 52
ADV7174/ADV7179
Table 26. PAL-60 (FSC = 4.43361875 MHz)
Table 27. NTSC (FSC = 3.5795454 MHz)
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Data
04H
10H
00H
00H
00H
00H
00H
CBH
8AH
09H
2AH
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Address
00H
01H
02H
03H
04H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
Description
Data
00H
10H
00H
00H
10H
00H
00H
1EH1
7CH
F0H
21H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
Mode Register 0
Mode Register 1
Mode Register 2
Mode Register 3
Mode Register 4
Timing Register 0
Timing Register 1
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
CGMS_WSS Register 0
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
CGMS_WSS Register 1
CGMS_WSS Register 2
Teletext Request Control Register
1 On power-up, this register is set to 16h. 1Eh should be written here for
correct FSC
.
Rev. A | Page 51 of 52
ADV7174/ADV7179
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
4.25
4.10 SQ
3.95
TOP
VIEW
5.75
BSC SQ
BOTTOM
VIEW
0.50
0.40
0.30
21
10
11
20
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 81. 40-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-40)
Dimensions shown in millimeters
Note that the exposed metal paddle on the bottom side of the LFCSP package must be soldered to PCB ground for proper heat dissipation
and also for noise and mechanical strength benefits.
ORDERING GUIDE
Model
ADV7179KCP
ADV7179KCP-REEL
ADV7179BCP
ADV7179BCP-REEL
ADV7174KCP
ADV7174KCP-REEL
ADV7174BCP
ADV7174BCP-REEL
EVAL-ADV7179EBM
EVAL-ADV7174EBM
Temperature Range
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
CP-40
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Lead Frame Chip Scale Package
Evaluation Board
Evaluation Board
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02980–0–2/04(A)
Rev. A | Page 52 of 52
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